WO2022170792A1 - 显示面板及其制备方法、显示装置 - Google Patents

显示面板及其制备方法、显示装置 Download PDF

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Publication number
WO2022170792A1
WO2022170792A1 PCT/CN2021/128615 CN2021128615W WO2022170792A1 WO 2022170792 A1 WO2022170792 A1 WO 2022170792A1 CN 2021128615 W CN2021128615 W CN 2021128615W WO 2022170792 A1 WO2022170792 A1 WO 2022170792A1
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WIPO (PCT)
Prior art keywords
signal line
substrate
signal
display panel
layer
Prior art date
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PCT/CN2021/128615
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English (en)
French (fr)
Inventor
卢江楠
刘利宾
商广良
韩龙
冯宇
王丽
李梅
Original Assignee
京东方科技集团股份有限公司
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Priority to US17/923,934 priority Critical patent/US20230180551A1/en
Publication of WO2022170792A1 publication Critical patent/WO2022170792A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel, a manufacturing method thereof, and a display device.
  • a display panel has a display area and a peripheral area outside the display area.
  • the display panel includes a substrate, at least one first signal line, at least one second signal line, an insulating layer and a shielded signal line.
  • the at least one first signal line is disposed on the substrate and located in the peripheral region.
  • the at least one second signal line is disposed on the substrate and located in the peripheral region; the at least one second signal line and the at least one first signal line are disposed in the same layer.
  • the insulating layer covers the at least one first signal line and the at least one second signal line; the insulating layer is provided with at least one groove on the surface of the side away from the substrate; the bottom surface of one groove
  • the orthographic projection on the substrate is between the orthographic projections of a first signal line and a second signal line on the substrate.
  • the shielded signal line covers the at least one groove.
  • the bottom surface of the groove is closer to the top surface of at least one of the first signal line and the second signal line than the top surface of the at least one of the first signal line and the second signal line in a direction perpendicular to the plane of the substrate the substrate.
  • the first signal line and the second signal line are adjacent.
  • the width of the orthographic projection of the bottom surface of the groove on the substrate is less than or equal to the two edges that are close to each other in the orthographic projection of the first signal line and the second signal line on the substrate the distance between.
  • the width of the orthographic projection of the bottom surface of the groove on the substrate is 2 ⁇ m ⁇ 10 ⁇ m.
  • the extending direction of the first signal line and the extending direction of the second signal line are the same.
  • the groove extends along the extending direction of the first signal line and the second signal line.
  • the orthographic projection of the shielded signal line on the substrate covers the orthographic projection of the first signal line on the substrate and the orthographic projection of the second signal line on the substrate Orthographic projection.
  • the shielded signal line is located in the peripheral region and surrounds the display region.
  • the first signal line is configured to transmit a first signal; the second signal line is configured to transmit a second signal.
  • the first signal and the second signal are both pulse signals, and the first signal and the second signal are different.
  • the shielded signal line is configured to transmit a DC signal.
  • the first signal and the second signal have the same pulse period; the first signal and the second signal have a phase difference.
  • the pulse period is 4 ⁇ s ⁇ 100 ⁇ s.
  • the display panel further includes: a plurality of light emitting devices.
  • the plurality of light emitting devices are disposed on the substrate and located in the display area.
  • Each light emitting device includes a first electrode and a second electrode; the first electrode is closer to the substrate than the second electrode.
  • the second electrode is coupled to the shielded signal line.
  • the first electrode of the light emitting device and the shielded signal line are disposed in the same layer.
  • the insulating layer has a double-layer structure.
  • the first electrode of the light emitting device is farther from the substrate than the shielded signal line.
  • the insulating layer has a single-layer structure.
  • the display panel further includes: a plurality of pixel circuits and a driving circuit.
  • the plurality of pixel circuits are disposed on the substrate and located in the display area.
  • the driving circuit is disposed on the substrate and located in the peripheral region.
  • the driving circuit is coupled to the plurality of pixel circuits, the first signal line and the second signal line, respectively.
  • the drive circuit is configured to provide drive signals to the plurality of pixel circuits in response to a first signal received at the first signal line and a second signal received at the second signal line to The plurality of pixel circuits are driven to work.
  • a display device in another aspect, includes: the display panel and the control chip as described in any of the above embodiments.
  • the control chip is coupled to the display panel.
  • the control chip is configured to provide signals to the display panel.
  • a method for manufacturing a display panel includes: providing a substrate having a display area and a peripheral area outside the display area; forming at least one first signal line and at least one second signal line in the peripheral area of the substrate line; forming an insulating layer, the insulating layer covering the at least one first signal line and the at least one second signal line; the insulating layer is formed with at least one groove on the surface of the side away from the substrate ; the orthographic projection of the bottom surface of a groove on the substrate is located between the orthographic projection of a first signal line and a second signal line on the substrate; a shielded signal line is formed, and the shielded signal line covers the at least one groove.
  • the forming an insulating layer includes: forming an insulating material layer on a side of the at least one first signal line and the at least one second signal line away from the substrate; and forming an insulating material layer on the insulating material A photoresist layer is formed on the layer; a half-tone mask is used to expose the photoresist layer, and the photoresist layer is developed to form an area for all removal of the photoresist layer, a semi-reserved area for the photoresist layer, and a photoresist layer.
  • the entire reserve area of the photoresist layer is etched; the insulating material layer is etched to remove the part of the insulating material layer located in the entire removal area of the photoresist layer; an ashing process is used to remove the photoresist layer in the photoresist layer.
  • Part of the semi-reserved area of the adhesive layer etching the part of the insulating material layer located in the semi-reserved area of the photoresist layer to form the at least one groove; peeling off the remaining photoresist layer to obtain the insulating layer.
  • FIG. 1 is a schematic structural diagram of a display panel according to some embodiments.
  • FIG. 2 is a cross-sectional view of the display panel in FIG. 1 along the direction A1-B1;
  • FIG. 3 is a schematic structural diagram of another display panel according to some embodiments.
  • FIG. 4 is a cross-sectional view of the display panel in FIG. 3 along the direction A2-B2;
  • FIG. 5 is a cross-sectional view of the display panel in FIG. 3 along the direction A3-B3;
  • FIG. 6 is a timing diagram of a first signal, a second signal and a DC signal according to some embodiments
  • FIG. 7 is a schematic structural diagram of still another display panel according to some embodiments.
  • FIG. 8 is a circuit diagram of a pixel circuit according to some embodiments.
  • FIG. 9 is a cross-sectional view of the display panel in FIG. 1 along the D1-D2 direction;
  • FIG. 10A is a schematic structural diagram of yet another display panel according to some embodiments.
  • FIG. 10B is a schematic structural diagram of yet another display panel according to some embodiments.
  • FIG. 11 is a schematic structural diagram of a driving circuit according to some embodiments.
  • FIG. 12 is a schematic structural diagram of another driving circuit according to some embodiments.
  • 13 is a circuit diagram of a shift register according to some embodiments.
  • FIG. 14 is a schematic structural diagram of yet another display panel according to some embodiments.
  • FIG. 15 is a schematic structural diagram of yet another display panel according to some embodiments.
  • 16 is a structural block diagram of a display device according to some embodiments.
  • 17A is a schematic process diagram of a method for fabricating a display panel according to some embodiments.
  • 17B is a schematic process diagram of another method for fabricating a display panel according to some embodiments.
  • 18A is a schematic process diagram of yet another method for fabricating a display panel according to some embodiments.
  • 18B is a schematic process diagram of still another method for fabricating a display panel according to some embodiments.
  • FIG. 18C is a schematic process diagram of yet another method for fabricating a display panel according to some embodiments.
  • FIG. 19 is a schematic process diagram of yet another method of fabricating a display panel according to some embodiments.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as “first” or “second” may expressly or implicitly include one or more of that feature.
  • plural means two or more.
  • the expressions “coupled” and “connected” and their derivatives may be used.
  • the term “connected” may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact.
  • the terms “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, yet still co-operate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited by the content herein.
  • Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the drawings due to, for example, manufacturing techniques and/or tolerances, are contemplated.
  • example embodiments should not be construed as limited to the shapes of the regions shown herein, but to include deviations in shapes due, for example, to manufacturing. For example, an etched area shown as a rectangle will typically have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • the distance between two adjacent signal lines is relatively small.
  • the signals transmitted on the adjacent two signal lines are prone to crosstalk, which reduces the stability of the signal and affects the normal operation of some circuits in the display panel, thereby reducing the display effect. .
  • the display panel 100 has a display area AA and a peripheral area S.
  • the peripheral area S is located on at least one side outside the display area AA.
  • the display area AA is an area defined by a dotted frame.
  • the peripheral area S may surround the display area AA.
  • the display panel 100 includes a plurality of sub-pixels P disposed in the display area AA.
  • a plurality of sub-pixels P may be arranged in an array.
  • the sub-pixels P arranged in a row along the first direction X in FIG. 1 are called the same pixel, and the sub-pixels P arranged in a row along the second direction Y in FIG. 1 are called the same column of pixels.
  • each pixel includes a plurality of sub-pixels; the plurality of sub-pixels includes sub-pixels of a first color, sub-pixels of a second color, and sub-pixels of a third color.
  • the first color, the second color and the third color are three primary colors; for example, the first color, the second color and the third color are red, green and blue, respectively; that is, the plurality of sub-pixels include red sub-pixels, green subpixel and blue subpixel.
  • a space rectangular coordinate system is established based on the substrate of the display panel, and in the space rectangular coordinate system, the first direction X and the second direction Y are parallel to the substrate The direction of the plane where the substrate is located, and the third direction Z is a direction perpendicular to the plane where the substrate is located.
  • the display panel 100 includes: a substrate 101 , at least one first signal line 10 , at least one second signal line 20 , and an insulating layer 40 .
  • at least one first signal line 10 , at least one second signal line 20 , shielded signal line 30 and insulating layer 40 are all disposed on the substrate 101 .
  • At least one first signal line 10 and at least one second signal line 20 are both located in the peripheral area S.
  • the insulating layer 40 covers at least one first signal line 10 and at least one second signal line 20, that is, the insulating layer 40 is disposed on the side of at least one first signal line 10 and at least one second signal line 20 away from the substrate 101, and also That is, the insulating layer 40 is disposed above the at least one first signal line 10 and the at least one second signal line 20 .
  • the substrate 101 may be a rigid substrate such as glass, or a flexible substrate such as PI (Polyimide, polyimide); a film layer such as a buffer layer may be provided on the rigid substrate or the flexible substrate.
  • PI Polyimide, polyimide
  • a film layer such as a buffer layer may be provided on the rigid substrate or the flexible substrate.
  • At least one first signal line and at least one second signal line are disposed on the same layer.
  • the film layer where the first signal line and the second signal line are located may be regarded as the first conductive layer.
  • the material of the first signal line is the same as the material of the second signal line, for example, the material may be a metal including molybdenum (Mo), aluminum (Al), copper (Cu) and the like.
  • the first signal line and the second signal line may be formed simultaneously, for example, the first signal line and the second signal line may be formed by patterning the same film layer. In this way, the production process can be reduced and the process can be simplified.
  • one first signal line is adjacent to one second signal line. For example, in the film layer where the first signal line and the second signal line are located, there is no other signal line between the first signal line and the second signal line.
  • the first signal line is configured to transmit the first signal.
  • the second signal line is configured to transmit the second signal.
  • the first signal and the second signal are both pulse signals, and the first signal and the second signal are different.
  • the first signal K1 and the second signal K2 have the same pulse period, and the first signal and the second signal have a phase difference.
  • one pulse period refers to the duration from the rising edge (or falling edge) of one pulse of a pulse signal (eg, the first signal or the second signal) to the rising edge (or falling edge) of the next pulse of the one pulse.
  • the rising edge (or falling edge) of the pulse of the first signal and the rising edge (or falling edge) of the pulse of the second signal are not at the same time;
  • the interval duration between the rising edges (or falling edges) of the pulses of the second signal is greater than 0 and less than one pulse period.
  • the phase difference between the first signal and the second signal is half the pulse period.
  • the first signal and the second signal may both be AC signals; for example, the first signal and the second signal may both be clock signals, and both have the same clock period.
  • the phase difference between the first signal and the second signal is equal to half of the pulse period, for example, the first signal and the second signal are inverted signals of each other.
  • both the first signal and the second signal may be high-frequency signals; for example, the pulse period of the first signal and the pulse period of the second signal are 4 ⁇ s ⁇ 100 ⁇ s, for example, the pulse period may be 4 ⁇ s, 5 ⁇ s, 10 ⁇ s, 25 ⁇ s , 50 ⁇ s, 80 ⁇ s or 100 ⁇ s.
  • the frequency of the first signal and the frequency of the second signal are 10000Hz ⁇ 250000Hz, for example, the frequency may be 10000Hz, 12500Hz, 20000Hz, 40000Hz, 100000Hz, 200000Hz or 250000Hz.
  • the surface of the insulating layer 40 on the side away from the substrate 101 is provided with at least one groove 41 .
  • the orthographic projection of the bottom surface of a groove 41 (ie, the surface of the groove 41 on the side close to the substrate 101 ) F3 on the substrate 101 is located on the substrate 101 with one first signal line 10 and one second signal line 20 on the substrate 101 between the orthographic projections.
  • the one first signal line 10 is adjacent to the one second signal line 20 .
  • the depth direction (eg, the third direction Z in FIG. 2 ) of the at least one groove 41 is perpendicular to the substrate 101 .
  • the insulating layer is recessed toward the substrate side in a direction perpendicular to the substrate in a surface on a side away from the substrate corresponding to a portion between the first signal line and the second signal line, resulting in a groove.
  • the depth of the groove is less than the thickness of the insulating layer; for example, both the bottom surface and the sidewall of the groove are formed by the insulating layer.
  • the display panel 100 further includes a shielded signal line 30 .
  • the shielded signal line 30 covers the groove 41 .
  • the shielded signal line 30 is disposed on a side of the insulating layer 40 away from the substrate 101 .
  • the shielded signal lines cover the bottom surface and side walls of the groove.
  • the shielded signal lines are configured to transmit DC signals.
  • the voltage (or current) amplitude of the DC signal K3 remains constant or approximately constant (eg, the amplitude varies within a small range of values).
  • the DC signal may be a DC low voltage;
  • the shielded signal line may be a supply voltage line configured to carry a low-level supply voltage V SS .
  • the first signal transmitted on the first signal line and the second signal transmitted on the second signal are different and change frequently with time, the first signal and the second signal are prone to appear during the transmission process
  • the problem of crosstalk reduces the stability of the signal and affects the normal operation of some circuits in the display panel. Since the DC signal transmitted on the shielded signal wire in the groove remains fixed or approximately fixed, the first signal wire and the second signal wire can be shielded, so that the first signal wire and the second signal wire can be shielded. Signal crosstalk between two signal lines.
  • the thickness of the insulating layer at the position of the groove is relatively thin, and the shielded signal line is located in the groove, which does not increase the film thickness of the display panel, which is beneficial to realize the thinning of the display panel.
  • the shielded signal line covers at least one groove.
  • the shielded signal line can shield the first signal line and the second signal line to avoid signal crosstalk between the first signal line and the second signal line.
  • the thickness of the insulating layer at the position of the groove is relatively thin, and the shielded signal line is located in the groove, which does not increase the film thickness of the display panel, which is beneficial to realize the thinning of the display panel.
  • the surface F1 of the first signal line 10 and the top surface F2 of the second signal line 20 At least one of the bottom surfaces of the grooves 41 is closer to the substrate 101 . That is, compared to the surface F1 of the first signal line 10 away from the substrate 101 and the surface F2 of the second signal line 20 away from the substrate 101, the surface F3 of the groove 41 close to the substrate 101 is closer to the substrate Bottom 101.
  • the orthographic projection of the shielded signal line on the first signal line may be different from the sidewall of the first signal line close to the second signal line.
  • the orthographic projection of the shielded signal line on the second signal line may be different from the side wall of the second signal line close to the first signal line.
  • the shielding range of the shielded signal line to the first signal line and the second signal line can be expanded, so that the shielding effect of the shielded signal line to the first signal line and the second signal line can be improved, and the first signal line and the second signal line can be avoided. There is signal interference between the lines.
  • the width W of the orthographic projection of the bottom surface of the groove 41 on the substrate 101 is less than or equal to the width W of the first signal line 10 and the second signal line 20 on the substrate 101 .
  • the orthographic projection of the bottom surface of the groove on the substrate is perpendicular to the extending direction of the first signal line or the second signal line (for example, in the first direction X in FIG. 1 ).
  • the size is the width of the orthographic projection of the bottom surface of the groove on the substrate. In this way, the shielded signal line located in the groove can shield the first signal line and the second signal line to avoid signal interference.
  • the width W of the orthographic projection of the surface of the groove 41 on the side close to the substrate 101 on the substrate 101 is 2 ⁇ m ⁇ 10 ⁇ m.
  • the width W may be 2 ⁇ m, 4 ⁇ m, 6 ⁇ m, 7 ⁇ m, 9 ⁇ m or 10 ⁇ m.
  • the width W may be 3 ⁇ m to 5 ⁇ m.
  • the orthographic projection of the shielded signal line 30 on the substrate 101 covers the orthographic projection of the first signal line 10 on the substrate 101 and the orthographic projection of the second signal line 20 on the substrate 101 .
  • the shielded signal line can cover the groove, the first signal line and the second signal line, which can improve the shielding effect of the shielded signal line on the first signal line and the second signal line, and avoid the interference between the first signal line and the second signal line. signal interference occurs.
  • the extending direction of the first signal line 10 and the extending direction of the second signal line 20 are the same.
  • the groove 41 extends along the extending direction of the first signal line 10 and the second signal line 20, that is, the extending direction of the groove 41 is the same as the extending direction of the first signal line 10 or the extending direction of the second signal line 20.
  • the groove 41 , the first signal line 10 and the second signal line 20 all extend along the first direction X in FIG. 1 .
  • the length of the groove is equal to or approximately equal to the length of the first signal line, or, in the extending direction of the second signal line, the length of the groove is equal to or approximately equal to the length of the second signal line the length of the line.
  • the shielding effect of the shielded signal line on the first signal line and the second signal line can be improved, and signal interference between the first signal line and the second signal line can be avoided.
  • the display panel 100 further includes a first conductive pattern 110 .
  • the first conductive pattern 110 is disposed on the substrate 101 and is located on a side of the first signal line 10 close to the substrate 101 .
  • the orthographic projection of the first conductive pattern 110 on the substrate 101 overlaps with the orthographic projection of the first signal line 10 on the substrate 101 .
  • the first conductive pattern 110 is coupled to the first signal line 10 .
  • the first signal line 10 passes through a plurality of first vias 111 (eg, at least two first vias) on the film layer between the film layer where the first signal line 10 is located and the film layer where the first conductive pattern 110 is located. , in contact with the first conductive pattern 110 .
  • the material of the first conductive pattern and the material of the first signal line may be the same.
  • the first conductive pattern may be used to transmit the first signal, that is, the first signal is transmitted by the first signal line in the first conductive layer and the first conductive pattern in the second conductive layer.
  • the resistance of the first signal line can be reduced, and the loss of signal transmission on the first signal line can be reduced, so that the effect of signal transmission can be improved.
  • two adjacent first via holes may pass through each other.
  • the display panel 100 further includes a second conductive pattern 120 .
  • the second conductive pattern 120 is disposed on the substrate 101 and is located on the side of the second signal line 20 close to the substrate 101 .
  • the orthographic projection of the second conductive pattern 120 on the substrate 101 overlaps with the orthographic projection of the second signal line 20 on the substrate 101 .
  • the second conductive pattern 120 is coupled with the second signal line 20 .
  • the second signal line 20 passes through a plurality of second via holes 121 (eg, at least two second via holes) located on the film layer between the film layer where the second signal line 20 is located and the film layer where the second conductive pattern 120 is located. , in contact with the second conductive pattern 120 .
  • the material of the second conductive pattern and the material of the second signal line may be the same.
  • the second conductive pattern may be used to transmit the second signal, that is, the second signal is transmitted by the second signal line in the first conductive layer and the second conductive pattern in the second conductive layer.
  • the resistance of the second signal line can be reduced, the loss of signal transmission on the second signal line can be reduced, and the effect of signal transmission can be improved.
  • two adjacent second via holes may pass through each other.
  • the first conductive pattern and the second conductive pattern are disposed in the same layer.
  • the film layer where the first conductive pattern and the second conductive pattern are located may be regarded as the second conductive layer.
  • the material of the first conductive pattern is the same as the material of the second conductive pattern, for example, metals including molybdenum (Mo), aluminum (Al), copper (Cu) and the like may be used.
  • the first conductive pattern and the second conductive pattern may be formed simultaneously, for example, the first conductive pattern and the second conductive pattern may be formed by patterning the same film layer. In this way, the production process can be reduced and the process can be simplified.
  • the display panel 100 further includes a plurality of pixel circuits 50 .
  • a plurality of pixel circuits 50 are disposed on the substrate 101 and located in the display area AA, for example, one pixel circuit 50 is included in one sub-pixel P.
  • the display panel further includes a plurality of light emitting devices.
  • a plurality of light emitting devices are disposed on the substrate and located in the display area AA.
  • One light emitting device is included in one subpixel.
  • a pixel circuit is coupled to a light emitting device, and the pixel circuit is used to provide a driving current for driving the light emitting device, so as to drive the light emitting device to work.
  • the display panel 100 further includes a third conductive pattern 130 disposed on the side of the first electrode 71 close to the substrate 101 ; the first electrode 71 of the light emitting device 70 is coupled to the pixel circuit 50 through the third conductive pattern 130 catch.
  • the embodiments of the present disclosure do not limit the specific structure of the pixel circuit, which can be designed according to actual conditions.
  • the pixel circuit is composed of thin film transistors (Thin Film Transistor, TFT), capacitors (Capacitor, C) and other electronic devices.
  • the pixel circuit may include two thin film transistors (one switching transistor and one driving transistor) and one capacitor to form a 2T1C structure; in other examples, the pixel circuit may also include more than two thin film transistors (multiple switch transistor and one drive transistor) and at least one capacitor, for example, referring to FIG.
  • the pixel circuit 50 may include a capacitor Cst and seven transistors (six switch transistors M1, M2, M3, M5, M6 and M7 and one drive transistor M4) , which constitutes the 7T1C structure. It should be noted that some drawings in the text (eg, FIG. 9 , etc.) take a transistor in the pixel circuit as an example to represent the pixel circuit, and the actual structure of the pixel circuit is not limited to this.
  • control electrodes (gates) of a part of the switching transistors are used to receive the reset signal Reset.
  • Control electrodes of another part of the switching transistors eg, M2, M3 are used to receive the gate driving signal Gate.
  • the control electrodes of another part of the switching transistors eg, M5, M6) are used for receiving the light emission control signal EM.
  • the pixel circuit turns on the transistor M1 and the transistor M7 in response to the reset signal Reset.
  • the initial signal Initial is transmitted to the control electrode (g) of the driving transistor M4 and the light emitting device 70 through the transistor M1 and the transistor M7, respectively, so as to achieve the purpose of resetting the light emitting device 70 and the control electrode of the driving transistor M4.
  • the transistor M2 under the control of the gate driving signal Gate, the transistor M2 is turned on, the control electrode g of the driving transistor M4 is coupled to the drain (d), and the driving transistor M4 is in a diode-on state.
  • the data signal Data is written to the source (s) of the driving transistor M4 through the transistor M2, and the threshold voltage (Vth) of the driving transistor M4 is compensated.
  • the transistor M5 and the transistor M6 are turned on, and the high-level power supply voltage (or called the first power supply voltage) V DD and the low-level power supply voltage (or called the second power supply voltage) V SS The current path between them is turned on.
  • the driving current (I sd ) generated by the driving transistor M4 is transmitted to the light emitting device 70 through the above current path, so as to drive the light emitting device 70 to emit light.
  • the light-emitting device can be a current-driven device, and further, a current-driven light-emitting diode can be used, such as a Micro Light Emitting Diode (Micro LED), a Mini Light Emitting Diode (Mini LED) , Organic Light Emitting Diode (OLED) or Quantum Light Emitting Diode (QLED).
  • a current-driven light-emitting diode can be used, such as a Micro Light Emitting Diode (Micro LED), a Mini Light Emitting Diode (Mini LED) , Organic Light Emitting Diode (OLED) or Quantum Light Emitting Diode (QLED).
  • each light emitting device 70 includes a first electrode 71 and a second electrode 72 .
  • the first electrode 71 is closer to the substrate 101 than the second electrode 72 .
  • the first electrode and the second electrode are an anode and a cathode, respectively.
  • the light emitting device 70 further includes a light emitting functional layer 73 between the second electrode 72 and the first electrode 71 .
  • the light-emitting functional layer may include, for example, a light-emitting layer, a hole transport layer (Hole Transport Layer, HTL) located between the light-emitting layer and the first electrode, and an electron transport layer (Electron Transport Layer) located between the light-emitting layer and the second electrode. , ETL).
  • a hole injection layer Hole Injection Layer, HIL
  • EIL Electron Injection Layer
  • the first electrode may be formed of, for example, a transparent conductive material having a high work function, and the electrode material may include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium zinc oxide ( GZO) zinc oxide (ZnO), indium oxide (In 2 O 3 ), aluminum zinc oxide (AZO), carbon nanotubes, etc.;
  • the second electrode may be formed of, for example, materials with high conductivity and low work function, and the electrode materials may include Alloys such as magnesium aluminum alloy (MgAl) and lithium aluminum alloy (LiAl), or simple metals such as magnesium (Mg), aluminum (Al), lithium (Li), and silver (Ag).
  • the material of the light-emitting layer can be selected according to the color of the emitted light.
  • the material of the light-emitting layer includes a fluorescent light-emitting material or a phosphorescent light-emitting material.
  • the light-emitting layer may adopt a doping system, that is, mixing a doping material into a host light-emitting material to obtain a usable light-emitting material.
  • a doping system that is, mixing a doping material into a host light-emitting material to obtain a usable light-emitting material.
  • metal compound materials, derivatives of anthracene, aromatic diamine compounds, triphenylamine compounds, aromatic triamine compounds, biphenyl diamine derivatives, triarylamine polymers and the like can be used as the host light emitting material.
  • the display panel 100 further includes a pixel defining layer PDL, which can be used to define the region where the sub-pixels are located, for example, can be used to define the formation position of the light emitting functional layer of the light emitting device 70 .
  • the light emitting functional layer 420 is located in the opening of the pixel defining layer PDL.
  • the second electrode is coupled with the shielded signal line.
  • the display panel 100 further includes a fourth conductive pattern 140 , the fourth conductive pattern 140 is closer to the substrate 101 than the second electrode 72 , and the second electrode 72 is coupled to the fourth conductive pattern 140 , The fourth conductive pattern 140 is coupled to the shielded signal line 30 .
  • the fourth conductive pattern 140 is provided in the same layer as the shielded signal line 30 ; or, referring to FIG. 10B , the fourth conductive pattern 140 is provided in the same layer as the first electrode 71 , and the fourth conductive pattern 140 is provided with the first electrode 71 Materials are the same.
  • FIG. 10A and FIG. 10B are only schematic diagrams, and the specific structure and connection mode can be designed according to actual conditions.
  • the second electrode receives a DC signal from the shielded signal line, and the DC signal is a DC low voltage.
  • the shielded signal lines 30 are located in the peripheral area S and surround the display area AA.
  • the second electrodes of the plurality of light emitting devices in the display area AA may be coupled to the shielded signal lines, and may relatively uniformly receive DC signals (eg, DC low voltage) transmitted from the shielded signal lines, thereby reducing impedance.
  • the second electrode covers the display area AA; the second electrode covering the display area AA may be formed through an evaporation process.
  • the display panel 100 further includes a driving circuit 60 .
  • the driving circuit 60 is disposed on the substrate 101 and located in the peripheral region S. As shown in FIG.
  • the driving circuit 60 is coupled to the plurality of pixel circuits 50 , the first signal line 10 and the second signal line 20 , respectively.
  • the driving circuit is configured to provide driving signals to the plurality of pixel circuits to drive the plurality of pixel circuits to operate in response to the first signal received at the first signal line and the second signal received at the second signal line.
  • a plurality of pixel circuits are arranged in an array; the driving circuit is used to provide driving signals to each row of pixel circuits row by row, so that the plurality of pixel circuits can work row by row.
  • the driving signal provided by the driving circuit may include a gate scan signal (Gate) or an emission control signal (EM).
  • the driver circuit includes a plurality of shift registers.
  • the drive circuit 60 includes a plurality of shift registers SR (eg, SR(1), SR(2), SR(3), SR(4), . . . ).
  • SR shift registers
  • a plurality of shift registers SR are cascaded; for example, the input terminal of the first-stage shift register (for example, the shift register SR(1) in FIG. 11 ) is connected to the start signal line (for example, the start signal in FIG. 11 ).
  • Line STV is coupled, the output terminal Oput of the shift register SR(1) is coupled to the input terminal Iput of the shift register SR(2), and the output terminal Oput of the shift register SR(2) is coupled to the shift register SR(3) ) is coupled to the input terminal Iput of the shift register SR(3), the output terminal Oput of the shift register SR(3) is coupled to the input terminal Iput of the shift register SR(4), and so on.
  • one shift register is coupled to one row of pixel circuits, and the shift register is used to output driving signals to one row of pixel circuits.
  • the driving signal output by the shift register SR in the driving circuit 60 is the gate driving signal Gate.
  • the first-stage shift register SR(1) outputs the gate driving signal Gate(1) to drive The first row of pixel circuits works
  • the second-stage shift register SR(2) outputs the gate drive signal Gate(2) to drive the second row of pixel circuits to work
  • the third-stage shift register SR(3) outputs the gate drive signal
  • the signal Gate(3) drives the pixel circuits of the third row to work
  • the shift register SR(4) of the fourth stage outputs the gate driving signal Gate(4) to drive the pixel circuits of the fourth row to work, and so on.
  • the driving signal output by the shift register SR in the driving circuit 60 is the light-emitting control signal EM
  • the first-stage shift register SR(1) outputs the light-emitting control signal EM(1) to drive the first The row pixel circuit works
  • the second-stage shift register SR(2) outputs the light-emitting control signal EM(2) to drive the second-row pixel circuit to work
  • the third-stage shift register SR(3) outputs the light-emitting control signal EM(3) ) to drive the pixel circuits of the third row to work
  • the shift register SR(4) of the fourth stage outputs the light emission control signal EM(4) to drive the pixel circuits of the fourth row to work, and so on.
  • the number of driving circuits may be plural.
  • the plurality of driving circuits include a first driving circuit and a second driving circuit.
  • the first driving circuit is used for outputting the gate scanning signal
  • the second driving circuit is used for outputting the light-emitting control signal.
  • the at least one first signal line includes two first signal lines, the first driving circuit is coupled to one of the two first signal lines, and the second driving circuit is coupled to one of the two first signal lines.
  • the other first signal line is coupled.
  • the first signals transmitted on the two first signal lines are different; for example, the first signals transmitted on the two first signal lines may be of the same type, but the signal timing and voltage amplitude are different.
  • the at least one second signal line includes two second signal lines, the first driving circuit is coupled to one of the two second signal lines, and the second driving circuit is coupled to one of the two second signal lines.
  • the other first signal line is coupled.
  • the second signals transmitted on the two second signal lines are different; for example, the second signals transmitted on the two second signal lines may be of the same type, but the signal timing and voltage amplitude are different.
  • a shift register consists of electronic devices such as transistors and capacitors.
  • the shift register SR may include a plurality of transistors (eg, T1, T2, T3, T4, T5, T6, T7, T8, T9) and a capacitor (eg, Ct).
  • the control electrode and the first electrode of the transistor T1 are coupled to the input end Iput, the first electrode of the transistor T2 is coupled to the first clock signal end CK1, the second electrode of the transistor T2 is coupled to the output end Oput, and the transistor T4 is connected to the output end Oput.
  • the control electrode and the first electrode are coupled to the second clock signal terminal CK2, and the first electrode of the transistor T5 is coupled to the second clock signal terminal CK2.
  • the gate noise reduction signal terminal RST of the transistor T3 is coupled, and the transistors T3, T6, T7, T8 and T9 are all coupled to the voltage terminal VL.
  • the first clock signal terminal CK1 of the odd-numbered stage shift registers eg, SR(1) and SR(3) in FIG.
  • the CK2 is coupled to the second signal line 20 and can transmit the second signal.
  • the first clock signal terminal CK1 of the even-numbered shift registers eg, SR( 2 ) and SR( 4 ) in FIG. 11
  • the second clock signal terminal CK2 is coupled to the first signal line 10 connected; at this time, both the first signal and the second signal are clock signals, and they are mutually inverted signals.
  • the voltage terminal VL is coupled to the voltage line VGL, for example, the voltage line VGL is used for transmitting a DC low voltage signal.
  • FIG. 7 only illustrates one-side driving (ie, the driving circuit 60 is provided on one side of the peripheral area S of the display panel 100 to sequentially drive the pixel circuits in the sub-pixels row by row from one side).
  • the display panel may be driven simultaneously on both sides (that is, in the peripheral area S of the display panel 100 along the row direction of the pixel circuit arrangement (or the row direction of the sub-pixel arrangement, such as the first direction X in FIG. 7 )
  • the driving circuits 60 are respectively provided on each side, and the pixel circuits in the sub-pixels are driven in sequence from both sides by the two driving circuits 60 simultaneously.
  • the display panel 100 may adopt double-sided cross driving (that is, the driving circuits 60 are respectively arranged on the two sides in the row direction of the pixel circuit arrangement in the peripheral area S of the display panel 100, and the two driving circuits 60 alternately drive the , sequentially driving the pixel circuits in the sub-pixels row by row).
  • at least one first signal line includes a plurality of first signal lines
  • at least one second signal line includes a plurality of second signal lines
  • the plurality of first signal lines and the plurality of second signal lines are respectively located in the display area Outside of the opposite sides in the row direction of the pixel circuit arrangement.
  • the first electrode 71 of the light emitting device 70 is disposed on the same layer as the shielded signal line 30 .
  • the material of the shielded signal line is the same as that of the first electrode.
  • the material for shielding the signal line may include a transparent conductive material such as ITO and the like.
  • the shielded signal line and the first electrode may be formed by patterning the same film layer. In this way, the process steps can be simplified and the cost can be saved.
  • the thickness of the film layer existing between the shielded signal line and the second electrode is relatively small, which can facilitate the coupling of the second electrode and the shielded signal line.
  • the insulating layer has a double-layer structure; that is, the number of insulating layers is double-layered, that is, the insulating layer between the film layer where the first signal line and the second signal line are located and the film layer where the shielding signal line is located has two layers.
  • the insulating layer 40 of the double-layer structure includes a first insulating layer PLN1 and a second insulating layer PLN2.
  • the first insulating layer PLN1 and the second insulating layer PLN2 are stacked in a direction perpendicular to the substrate 101 , and the second insulating layer PLN2 is farther from the substrate 101 than the first insulating layer PLN1 .
  • the bottom surface of the groove is composed of the first insulating layer
  • the sidewall of the groove is composed of the second insulating layer and the first insulating layer.
  • the groove penetrates the second insulating layer, and the depth of the groove is greater than the thickness of the second insulating layer and less than the thickness of the insulating layer (that is, the thickness of the first insulating layer and the second insulating layer). sum of thickness).
  • the first electrode 71 of the light emitting device 70 is farther from the substrate 101 than the shielded signal line 30 .
  • the material for shielding the signal line may include a metallic material.
  • the insulating layer has a single-layer structure, that is, the number of insulating layers is one layer, that is, there is one insulating layer between the film layer where the first signal line and the second signal line are located and the film layer where the shielding signal line is located.
  • the insulating layer 40 of the single-layer structure may be regarded as the first insulating layer ( PLN1 ).
  • the thickness of the film layer between the film layer where the first signal line and the second signal line are located and the film layer where the shielded signal line is located is relatively small, so that the difference between the shielded signal line and the first signal line and the second signal line can be improved.
  • the shielding effect of inter-signal interference may be the second insulating layer (PLN2).
  • the display panel does not include the first conductive pattern and the second conductive pattern, it is located between the film layer (for example, the first conductive layer) where the first signal lines and the second signal lines are located and the film layer where the shielded signal lines are located.
  • the insulating film layer in between may have two layers, such as a first insulating layer (PLN1) and a second insulating layer (PLN2).
  • PPN1 first insulating layer
  • PPN2 second insulating layer
  • the display panel includes the first conductive pattern and the second conductive pattern, it is located between the film layer (for example, the first conductive layer) where the first signal lines and the second signal lines are located and the film layer where the shielded signal lines are located.
  • the insulating film layer in between may have a single layer, such as the first insulating layer (PLN1).
  • the film layer located between the film layer where the first conductive pattern and the second conductive pattern are located (for example, the second conductive layer) and the film layer where the first signal line and the second signal line are located (for example, the first conductive layer) can be an interlayer dielectric layer (ILD); the film layer located between the film layer where the first electrode of the light-emitting device is located and the film layer where the shielding signal line is located may be the second insulating layer (PLN2).
  • ILD interlayer dielectric layer
  • the transistor includes an active pattern (ie, an active layer), a gate electrode (eg, a control electrode), a source electrode and a drain electrode
  • the display panel further includes a gate insulating layer between the gate electrode of the transistor and the active pattern (GI)
  • the source electrode and the drain electrode are located on the side of the gate away from the substrate, the source electrode and the drain electrode are arranged in the same layer, and the source electrode and the drain electrode are coupled to the active pattern.
  • an interlayer dielectric (ILD) exists between the source and drain electrodes and the gate electrode.
  • the source electrode and the drain electrode can be arranged in the same layer as the first signal line and the second signal line; or, for example, the film layer where the source electrode and the drain electrode are located can be compared with the film layer where the first signal line and the second signal line are located. Closer to the substrate, for example, there is a first insulating layer ( PLN1 ) between the film layer where the first signal line and the second signal line are located and the film layer where the source electrode and the drain electrode are located.
  • PLN1 first insulating layer
  • the embodiments of the present disclosure do not limit the types of transistors, which can be designed according to actual conditions.
  • the transistors used in the embodiments of the present disclosure may be P-type transistors or N-type transistors, and may be bottom-gate transistors or top-gate transistors.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors (Field Effect Transistor, FET), or other switching devices with the same characteristics, which are not limited in the embodiments of the present disclosure.
  • the used transistors may include metal oxide thin film transistors (such as those made of IGZO as the active pattern material) and low temperature polysilicon thin film transistors (such as those made of P-Si as the material of the active pattern).
  • the control electrode of each transistor is the gate of the transistor, the first electrode is one of the source electrode and the drain electrode of the transistor, and the second electrode is the other one of the source electrode and the drain electrode of the transistor. Since the source and drain of the transistor may be symmetrical in structure, the source and drain of the transistor may be indistinguishable in structure, that is, the first electrode and the second electrode of the transistor in the embodiments of the present disclosure Diodes may be indistinguishable in structure.
  • Embodiments of the present disclosure provide a display device.
  • the display device includes the display substrate in any one of the above embodiments.
  • the display device 200 further includes a control chip 300 , and the control chip 300 is coupled to the display panel 100 .
  • the control chip may include a timing controller (Timing Controller, TCON).
  • TCON Timing Controller
  • the control chip is configured to provide signals to the display panel.
  • the control chip may provide the first signal to the first signal line in the display panel, the second signal to the second signal line, and the DC signal to the shielded signal line.
  • the display device may further include an outer frame disposed around the display panel.
  • the above-described display device may be any device that displays images, whether in motion (eg, video) or stationary (eg, still images), and whether text or images. More specifically, it is contemplated that the embodiments may be implemented in or associated with a wide variety of electronic devices, such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs) , handheld or portable computers, GPS receivers/navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, TV monitors, flat panel monitors, computer monitors, automotive monitors (e.g., odometer displays, etc.), navigators, cockpit controls and/or displays, displays of camera views (eg, displays of rear-view cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, building structures, packaging and aesthetic structures (eg, a display for an image of a piece of jewelry), etc.
  • PDAs personal data assistants
  • handheld or portable computers GPS receivers/navigators
  • the entire structure of the display panel is not described.
  • those skilled in the art can set other structures according to specific application scenarios, which are not limited in the embodiments of the present disclosure.
  • the display device has the same beneficial effects as the above-mentioned display panel, which will not be repeated here.
  • the display panel may be the display panel described in any of the above embodiments, for example, refer to the display panel 100 in FIG. 1 .
  • the preparation method includes the following steps S10-S40.
  • a substrate 101 is provided.
  • the substrate 101 has a display area AA and a peripheral area S outside the display area AA.
  • the substrate may be a glass plate, a quartz plate, a metal plate, a resin-based plate, or the like.
  • the material of the substrate may include an organic material such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and Resin materials such as polyethylene naphthalate.
  • the substrate may be formed of a plurality of material layers, for example, the substrate may include a substrate, the material of the substrate may be composed of the above-mentioned materials, and a buffer layer may be formed on the surface of the substrate as a transition layer, which can prevent The harmful substances intrude into the interior of the display panel, which can increase the adhesion of the film layer in the display panel on the substrate.
  • the material of the buffer layer may include silicon oxide, silicon nitride, silicon oxynitride, or the like.
  • At least one first signal line 10 and at least one second signal line 20 are formed in the peripheral region S of the substrate 101 . Wherein, the position of one first signal line 10 is adjacent to the position of one second signal line 20 .
  • a conductive film 801 is formed in the peripheral region S of the substrate 101, and the conductive film 801 is patterned to obtain at least one first signal line 10 and at least one second signal line 20. .
  • driver circuits and pixel circuits may be formed on the substrate.
  • the method for forming the driver circuit and the pixel circuit on the substrate is related to the type of transistor, for example, the transistor may be a top-gate, bottom-gate, dual-gate or other type of thin film transistor.
  • the driving circuit layer on the substrate reference may be made to the conventional process, which will not be repeated here.
  • the pixel circuit 50 may be formed in the display area AA of the substrate 101; source and drain of each transistor.
  • an insulating layer 40 is formed.
  • the insulating layer 40 covers at least one first signal line 10 and at least one second signal line 20 .
  • At least one groove 41 is formed on the surface of the insulating layer 40 on the side away from the substrate 101 .
  • the orthographic projection of the bottom surface F3 of one groove 41 on the substrate 101 is located between the orthographic projections of the adjacent first signal line 10 and the second signal line 20 on the substrate 101 .
  • the material of the insulating layer can be an organic material such as epoxy, polyimide, polyamide, acrylic or other suitable materials.
  • forming the insulating layer may include the following steps.
  • an insulating material layer 802 is formed on a side of the at least one first signal line 10 and the at least one second signal line 20 away from the substrate 101 .
  • insulating material may be deposited on the side of the at least one first signal line 10 and the at least one second signal line 20 away from the substrate 101 to obtain the insulating material layer 802 .
  • a photoresist layer 803 is formed on the insulating material layer 802 .
  • the material of the photoresist layer is a photosensitive resin material, such as photoresist; for example, the photosensitive resin material is a positive photoresist.
  • the photoresist layer 803 is exposed by the halftone mask 90, the photoresist layer 803 is developed, and the photoresist layer all removal area 813, the photoresist layer semi-reserved area 823 and the photoresist layer are all retained. District 833.
  • the completely removed area of the photoresist layer may correspond to the part of the via hole to be formed in the insulating material layer
  • the half-reserved area of the photoresist layer may correspond to the part of the groove to be formed in the insulating material layer
  • the entire reserved area of the glue layer may correspond to the remaining portion in the insulating material layer.
  • the halftone mask 90 includes a first area 91 , a second area 92 and a third area 93 .
  • the light transmittances of the first area 91 , the second area 92 and the third area 93 are sequentially decreased.
  • the first area 91 may be set as an opening, and for example, the third area 93 may be set as opaque.
  • the part of the photoresist layer 803 corresponding to the first area 91 is completely covered. Exposure, the portion of the photoresist layer 803 corresponding to the second region 92 is completely exposed, and the portion of the photoresist layer 803 corresponding to the third region 93 is not exposed.
  • the insulating material layer 802 is etched, and the part of the insulating material layer 802 located in the entire removal area 813 of the photoresist layer is removed.
  • the part of the photoresist layer 803 located in the photoresist semi-reserved region 823 is removed by an ashing process.
  • At least one groove 41 is formed by etching a portion of the insulating material layer 802 located in the semi-reserved region 823 of the photoresist layer.
  • the remaining photoresist layer 803 is peeled off to obtain the insulating layer 40 .
  • the insulating layer 40 of the double-layer structure includes a first insulating layer ( PLN1 ) and a second insulating layer ( PLN2 ); referring to FIG. 15 , the insulating layer 40 of the double-layer structure includes a first insulating layer ( PLN1 ).
  • PLN1 first insulating layer
  • PLN2 second insulating layer
  • a shielded signal line 30 is formed, and the shielded signal line 30 covers at least one groove 41 .
  • a conductive material can be deposited on a substrate to obtain a conductive material layer, and the conductive material layer can be patterned to obtain a shielded signal line.
  • the third conductive pattern 130 may be formed in the display area AA.
  • the holes are coupled to the pixel circuit 50 .
  • the third conductive pattern is coupled with the drain of the driving transistor in the pixel circuit.
  • the first electrode 71 of the light emitting device 70 may be coupled with the pixel circuit 50 through the third conductive pattern 130 .
  • the shielded signal line is closer to the substrate than the first electrode of the light emitting device.
  • the insulating layer 40 has a double-layer structure, and the insulating layer 40 of the double-layer structure includes a first insulating layer (PLN1) and a second insulating layer (PLN2), and a transparent layer may be formed on the second insulating layer (PLN2).
  • the conductive material layer is patterned on the transparent conductive material layer to obtain a shielded signal line, and the first electrode of the light-emitting device is obtained simultaneously.

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Abstract

一种显示面板，具有显示区和位于显示区外的周边区。显示面板包括：衬底、同层设置于衬底上且位于周边区内的至少一条第一信号线和至少一条第二信号线、覆盖至少一条第一信号线和至少一条第二信号线的绝缘层和屏蔽信号线。绝缘层在远离衬底的一侧的表面设置有至少一个凹槽；一个凹槽的底面在衬底上的正投影位于一条第一信号线和一条第二信号线在所述衬底上的正投影之间。屏蔽信号线覆盖至少一个凹槽。

Description

显示面板及其制备方法、显示装置
本申请要求于2021年02月09日提交的、申请号为202110179988.2的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及其制备方法、显示装置。
背景技术
随着显示技术的进步，用户观感体验的要求越来越高。并且，随着显示产品的拥有量的增大，人们对于显示品质也提出了更高的要求。
发明内容
一方面，提供一种显示面板。所述显示面板具有显示区和位于显示区外的周边区。所述显示面板包括衬底、至少一条第一信号线、至少一条第二信号线、绝缘层和屏蔽信号线。所述至少一条第一信号线设置于所述衬底上且位于所述周边区内。所述至少一条第二信号线设置于所述衬底上且位于所述周边区内；所述至少一条第二信号线和所述至少一条第一信号线同层设置。所述绝缘层覆盖所述至少一条第一信号线和所述至少一条第二信号线；所述绝缘层在远离所述衬底的一侧的表面设置有至少一个凹槽；一个凹槽的底面在所述衬底上的正投影位于一条第一信号线和一条第二信号线在所述衬底上的正投影之间。所述屏蔽信号线覆盖所述至少一个凹槽。
在一些实施例中，沿垂直于衬底所在平面的方向，相比于所述第一信号线和所述第二信号线中的至少一者中的顶面，所述凹槽的底面更靠近所述衬底。
在一些实施例中，所述第一信号线和所述第二信号线相邻。所述凹槽的底面在所述衬底上的正投影的宽度，小于或等于所述第一信号线和所述第二信号线在所述衬底上的正投影中相互靠近的两个边沿之间的距离。
在一些实施例中，所述凹槽的底面在所述衬底上的正投影的宽度为2μm～10μm。
在一些实施例中，所述第一信号线的延伸方向和所述第二信号线的延伸方向相同。所述凹槽沿所述第一信号线和所述第二信号线的延伸方向延伸。
在一些实施例中，所述屏蔽信号线在所述衬底上的正投影覆盖所述第一信号线在所述衬底上的正投影和所述第二信号线在所述衬底上的正投影。
在一些实施例中，所述屏蔽信号线位于所述周边区内且围绕所述显示区。
在一些实施例中，所述第一信号线被配置为传输第一信号；所述第二信号线被配置为传输第二信号。所述第一信号和所述第二信号均为脉冲信号，且所述第一信号和所述第二信号不相同。所述屏蔽信号线被配置为传输直流信号。
在一些实施例中，所述第一信号和所述第二信号具有相同的脉冲周期；所述第一信号和所述第二信号具有相位差。
在一些实施例中，所述脉冲周期为4μs～100μs。
在一些实施例中，所述显示面板还包括：多个发光器件。所述多个发光器件设置于所述衬底上且位于所述显示区内。每个发光器件包括第一电极和第二电极；所述第一电极相比于所述第二电极靠近所述衬底。所述第二电极与所述屏蔽信号线耦接。
在一些实施例中，所述发光器件的第一电极与所述屏蔽信号线同层设置。所述绝缘层为双层结构。
在一些实施例中，所述发光器件的第一电极相比于所述屏蔽信号线远离所述衬底。所述绝缘层为单层结构。
在一些实施例中，所述显示面板还包括：多个像素电路和驱动电路。所述多个像素电路设置于所述衬底上且位于所述显示区内。所述驱动电路设置于所述衬底上且位于所述周边区内。所述驱动电路分别与所述多个像素电路、所述第一信号线和所述第二信号线耦接。所述驱动电路被配置为，响应于在所述第一信号线处接收的第一信号和在所述第二信号线处接收的第二信号，向所述多个像素电路提供驱动信号，以驱动所述多个像素电路工作。
另一方面，提供一种显示装置。所述显示装置包括：如上述任一实施例所述的显示面板和控制芯片。所述控制芯片与所述显示面板耦接。所述控制芯片被配置为向所述显示面板提供信号。
又一方面，提供一种显示面板的制备方法。所述制备方法包括：提供衬底，所述衬底具有显示区和位于所述显示区外的周边区；在所述衬底的周边区内形成至少一条第一信号线和至少一条第二信号线；形成绝缘层，所述绝缘层覆盖所述至少一条第一信号线和所述至少一条第二信号线；所述绝缘层在远离所述衬底的一侧的表面形成有至少一个凹槽；一个凹槽的底面在所述衬底上的正投影位于一条第一信号线和一条第二信号线在所述衬底上的正投影之间；形成屏蔽信号线，所述屏蔽信号线覆盖所述至少一个凹槽。
在一些实施例中，所述形成绝缘层，包括：在所述至少一条第一信号线和所述至少一条第二信号线远离所述衬底的一侧形成绝缘材料层；在所述绝 缘材料层上形成光刻胶层；采用半色调掩膜板曝光所述光刻胶层，显影所述光刻胶层，形成光刻胶层全部去除区、光刻胶层半保留区以及光刻胶层全部保留区；蚀刻所述绝缘材料层，去除所述绝缘材料层中位于所述光刻胶层全部去除区的部分；采用灰化工艺，去除所述光刻胶层中位于所述光刻胶层半保留区的部分；蚀刻所述绝缘材料层中位于所述光刻胶层半保留区的部分，形成所述至少一个凹槽；剥离剩余的光刻胶层，得到所述绝缘层。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，然而，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的一种显示面板的结构示意图；
图2为图1中的显示面板沿A1-B1方向的剖视图；
图3为根据一些实施例的另一种显示面板的结构示意图；
图4为图3中的显示面板沿A2-B2方向的剖视图；
图5为图3中的显示面板沿A3-B3方向的剖视图；
图6为根据一些实施例的第一信号、第二信号和直流信号的一种时序图；
图7为根据一些实施例的又一种显示面板的结构示意图；
图8为根据一些实施例的一种像素电路的电路图；
图9为图1中的显示面板沿D1-D2方向的剖视图；
图10A为根据一些实施例的又一种显示面板的结构示意图；
图10B为根据一些实施例的又一种显示面板的结构示意图；
图11为根据一些实施例的一种驱动电路的结构示意图；
图12为根据一些实施例的另一种驱动电路的结构示意图；
图13为根据一些实施例的一种移位寄存器的电路图；
图14为根据一些实施例的又一种显示面板的结构示意图；
图15为根据一些实施例的又一种显示面板的结构示意图；
图16为根据一些实施例的一种显示装置的结构框图；
图17A为根据一些实施例的一种显示面板的制备方法的过程示意图；
图17B为根据一些实施例的另一种显示面板的制备方法的过程示意图；
图18A为根据一些实施例的又一种显示面板的制备方法的过程示意图；
图18B为根据一些实施例的又一种显示面板的制备方法的过程示意图；
图18C为根据一些实施例的又一种显示面板的制备方法的过程示意图；
图19为根据一些实施例的又一种显示面板的制备方法的过程示意图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，然而，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术 语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
如本文所使用的那样，“约”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
在显示面板中，例如受走线空间的限制，相邻两条信号线的间距相对较小。在显示面板中的各条信号线进行信号传输的过程中，相邻两条信号线上传输的信号容易出现串扰，降低信号的稳定性，影响显示面板中一些电路的正常工作，从而降低显示效果。
本公开的一些实施例提供一种显示面板。如图1所示，显示面板100具有显示区AA和周边区S。例如，周边区S位于显示区AA外的至少一侧。例如，参考图1，显示区AA为由虚线框限定的区域。周边区S可以围绕显示区AA。
示例性地，显示面板100包括设置于显示区AA中的多个子像素P。例如，多个子像素P可以呈阵列排布。例如，沿图1中第一方向X排列成一排的子像素P称为同一像素，沿图1中第二方向Y排列成一排的子像素P称为同一列像素。示例性地，每个像素包括多个子像素；多个子像素包括第一颜色子像素、第二颜色子像素和第三颜色子像素。例如，第一颜色、第二颜色和第三颜色为三基色；例如，第一颜色、第二颜色和第三颜色分别为红色、绿色和蓝色；即，多个子像素包括红色子像素、绿色子像素和蓝色子像素。
需要说明的是，在本公开的一些实施例中，以显示面板的衬底为基准建立空间直角坐标系，在该空间直角坐标系中，第一方向X、第二方向Y为平 行于衬底所在平面的方向，第三方向Z为垂直于衬底所在平面的方向。
示例性地，参考图1和图2，显示面板100包括：衬底101、至少一条第一信号线10、至少一条第二信号线20和绝缘层40。其中，至少一条第一信号线10、至少一条第二信号线20、屏蔽信号线30和绝缘层40均设置于衬底101上。至少一条第一信号线10和至少一条第二信号线20均位于周边区S内。绝缘层40覆盖至少一条第一信号线10和至少一条第二信号线20，即绝缘层40设置于至少一条第一信号线10和至少一条第二信号线20远离衬底101的一侧，也即绝缘层40设置于至少一条第一信号线10和至少一条第二信号线20的上方。
示例性地，衬底101可以为玻璃等刚性衬底，或者PI(Polyimide，聚酰亚胺)等柔性衬底；该刚性衬底或柔性衬底上可以设置有例如缓冲层等的膜层。
示例性地，至少一条第一信号线和至少一条第二信号线同层设置。例如，第一信号线和第二信号线所在的膜层可以被看作是第一导电层。例如，第一信号线的材料和第二信号线的材料相同，例如材料可以采用包括钼(Mo)、铝(Al)、铜(Cu)等金属。例如，第一信号线和第二信号线可以同步形成，例如，第一信号线和第二信号线可以由同一膜层构图形成。这样，可以减少生产工序，简化工艺。示例性地，一条第一信号线与一条第二信号线相邻。例如，在第一信号线和第二信号线所在的膜层中，第一信号线和第二信号线之间没有其他信号线。
其中，第一信号线被配置为传输第一信号。第二信号线被配置为传输第二信号。第一信号和第二信号均为脉冲信号，且第一信号和第二信号不相同。示例性地，参考图6，第一信号K1和第二信号K2具有相同的脉冲周期，且第一信号和第二信号具有相位差。其中，一个脉冲周期指的是脉冲信号(例如第一信号或第二信号)的一个脉冲的上升沿(或下降沿)至该一个脉冲的下一个脉冲的上升沿(或下降沿)的时长。例如，第一信号的脉冲的上升沿(或下降沿)与第二信号的脉冲的上升沿(或下降沿)未处于同一时刻；例如，第一信号的脉冲的上升沿(或下降沿)与第二信号的脉冲的上升沿(或下降沿)之间的间隔时长大于0且小于一个脉冲周期。例如，第一信号和第二信号的相位差为脉冲周期的一半。例如，第一信号和第二信号可以均为交流信号；例如，第一信号和第二信号可以均为时钟信号，且两者具有相同的时钟周期。例如，第一信号和第二信号的相位差等于脉冲周期的一半，例如，第一信号和第二信号互为反转信号。
示例性地，第一信号和第二信号可以均为高频信号；例如，第一信号的脉冲周期和第二信号的脉冲周期为4μs～100μs，例如脉冲周期可以为4μs、5μs、10μs、25μs、50μs、80μs或者100μs。例如，第一信号的频率和第二信号的频率为10000Hz～250000Hz，例如，频率可以为10000Hz、12500Hz、20000Hz、40000Hz、100000Hz、200000Hz或者250000Hz。
在此情况下，参考图2，绝缘层40在远离衬底101的一侧的表面设置有至少一个凹槽41。一个凹槽41的底面(即，凹槽41中靠近衬底101一侧的表面)F3在衬底101上的正投影位于一条第一信号线10和一条第二信号线20在衬底101上的正投影之间。例如，该一条第一信号线10和一条第二信号线20相邻。例如，至少一个凹槽41的深度方向(例如图2中的第三方向Z)垂直于衬底101。例如，绝缘层在远离衬底的一侧的表面中对应于第一信号线和第二信号线之间的部分，沿垂直于衬底的方向朝向衬底一侧凹陷，得到凹槽。示例性地，凹槽的深度小于绝缘层的厚度；例如，凹槽的底面和侧壁均由绝缘层构成。
并且，参考图1和图2，显示面板100还包括屏蔽信号线30。屏蔽信号线30覆盖凹槽41。例如，屏蔽信号线30设置于绝缘层40远离衬底101的一侧。例如，屏蔽信号线覆盖凹槽的底面和侧壁。
示例性地，屏蔽信号线被配置为传输直流信号。例如，参考图6，直流信号K3的电压(或电流)幅值保持固定不变或者近似固定不变(例如幅值在较小的数值范围内变化)。例如，直流信号可以为直流低电压；例如，该屏蔽信号线可以为电源电压线，该电源电压线被配置为传输低水平电源电压V SS。
在此情况下，由于第一信号线上传输的第一信号和第二信号上传输的第二信号不相同，且随时间变化较为频繁，使得第一信号和第二信号在传输过程中容易出现串扰的问题，导致信号的稳定性降低，影响显示面板中一些电路的正常工作。由于在凹槽内的屏蔽信号线上传输的直流信号保持固定不变或者近似固定不变，因此可以对第一信号线和第二信号线起到屏蔽作用，从而可以避免第一信号线和第二信号线之间的信号串扰。并且，绝缘层在凹槽位置处的厚度较薄，且屏蔽信号线位于凹槽内，不会增加显示面板的膜层厚度，有利于显示面板实现轻薄化。
因此，在本公开的实施例提供的显示面板中，至少一条第一信号线和至少一条第二信号线被绝缘层覆盖，绝缘层上设置有至少一个凹槽，一个凹槽的位置对应于相邻的第一信号线和第二信号线之间，屏蔽信号线覆盖至少一个凹槽。这样，屏蔽信号线可以对第一信号线和第二信号线起到屏蔽作用， 避免第一信号线和第二信号线之间的信号串扰。并且，绝缘层在凹槽位置处的厚度较薄，且屏蔽信号线位于凹槽内，不会增加显示面板的膜层厚度，有利于显示面板实现轻薄化。
在一些实施例中，参考图2，沿垂直于衬底101所在平面的方向(例如第三方向Z)，相比于第一信号线10的顶面F1和第二信号线20的顶面F2中的至少一者，凹槽41的底面更靠近衬底101。即，相比于第一信号线10远离衬底101一侧的表面F1和第二信号线20远离衬底101一侧的表面F2，凹槽41靠近衬底101一侧的表面F3更靠近衬底101。例如，沿平行于衬底所在平面且垂直于第一信号线延伸方向的方向上，屏蔽信号线在第一信号线上的正投影可以与第一信号线中靠近第二信号线的侧壁有重叠，沿平行于衬底所在平面且垂直于第二信号线延伸方向的方向上，屏蔽信号线在第二信号线上的正投影可以与第二信号线中靠近第一信号线的侧壁有重叠。这样，可以扩大屏蔽信号线对第一信号线和第二信号线的屏蔽范围，从而可以提高屏蔽信号线对第一信号线和第二信号线的屏蔽作用，避免第一信号线和第二信号线之间出现信号干扰。
在一些实施例中，参考图1和图2，凹槽41的底面在衬底101上的正投影的宽度W，小于或等于第一信号线10和第二信号线20在衬底101上的正投影中相互靠近的两个边沿之间的距离Q。例如，在衬底所在平面内，凹槽的底面在衬底上的正投影在垂直于第一信号线或第二信号线的延伸方向上(例如在图1中的第一方向X上)的尺寸即为凹槽的底面在衬底上的正投影的宽度。这样，位于凹槽内的屏蔽信号线可以对第一信号线和第二信号线起到屏蔽作用，以避免信号干扰。
在一些实施例中，参考图1和图2，凹槽41中靠近衬底101一侧的表面在衬底101上的正投影的宽度W为2μm～10μm。例如宽度W可以为2μm、4μm、6μm、7μm、9μm或者10μm。例如，宽度W可以为3μm～5μm。
在一些实施例中，屏蔽信号线30在衬底101上的正投影覆盖第一信号线10在衬底101上的正投影和第二信号线20在衬底101上的正投影。这样，屏蔽信号线可以覆盖凹槽、第一信号线和第二信号线，可以提高屏蔽信号线对第一信号线和第二信号线的屏蔽作用，避免第一信号线和第二信号线之间出现信号干扰。
在一些实施例中，参考图1，第一信号线10的延伸方向和第二信号线20的延伸方向相同。凹槽41沿第一信号线10和第二信号线20的延伸方向延伸，即，凹槽41的延伸方向与第一信号线10的延伸方向或第二信号线20的延伸 方向相同。例如，凹槽41、第一信号线10和第二信号线20均沿图1中的第一方向X延伸。例如，在第一信号线的延伸方向上，凹槽的长度等于或近似等于第一信号线的长度，或者，在第二信号线的延伸方向上，凹槽的长度等于或近似等于第二信号线的长度。这样，可以提高屏蔽信号线对第一信号线和第二信号线的屏蔽作用，避免第一信号线和第二信号线之间出现信号干扰。
在一些实施例中，参考图3和图4，显示面板100还包括第一导电图案110。第一导电图案110设置于衬底101上且位于第一信号线10靠近衬底101的一侧。第一导电图案110在衬底101上的正投影与第一信号线10在衬底101上的正投影有重叠。第一导电图案110和第一信号线10耦接。例如，第一信号线10通过位于第一信号线10所在膜层和第一导电图案110所在膜层之间的膜层上的多个第一过孔111(例如至少两个第一过孔)，与第一导电图案110接触。例如，第一导电图案的材料与第一信号线的材料可以相同。在此情况下，第一导电图案可以用于传输第一信号，即，第一信号由第一导电层中的第一信号线和第二导电层中的第一导电图案传输。这样，可以减小第一信号线的电阻，降低信号在第一信号线上传输的损失，从而可以提高信号传输的效果。此外，沿第一信号线的延伸方向，相邻两个第一过孔可以相互贯通。
在一些实施例中，参考图3和图5，显示面板100还包括第二导电图案120。第二导电图案120设置于衬底101上且位于第二信号线20靠近衬底101的一侧。第二导电图案120在衬底101上的正投影与第二信号线20在衬底101上的正投影有重叠。第二导电图案120和第二信号线20耦接。例如，第二信号线20通过位于第二信号线20所在膜层和第二导电图案120所在膜层之间的膜层上的多个第二过孔121(例如至少两个第二过孔)，与第二导电图案120接触。例如，第二导电图案的材料与第二信号线的材料可以相同。在此情况下，第二导电图案可以用于传输第二信号，即，第二信号由第一导电层中的第二信号线和第二导电层中的第二导电图案传输。这样，可以减小第二信号线的电阻，降低信号在第二信号线上传输的损失，从而可以提高信号传输的效果。此外，沿第二信号线的延伸方向，相邻两个第二过孔可以相互贯通。
在一些实施例中，第一导电图案和第二导电图案同层设置。例如，第一导电图案和第二导电图案所在的膜层可以被看作是第二导电层。第一导电图案的材料和第二导电图案的材料相同，例如材料可以采用包括钼(Mo)、铝(Al)、铜(Cu)等金属。例如，第一导电图案和第二导电图案可以同步形成，例如，第一导电图案和第二导电图案可以由同一膜层构图形成。这样，可以减少生产工序，简化工艺。
在一些实施例中，参考图7，显示面板100还包括多个像素电路50。多个像素电路50设置于衬底101上且位于显示区AA内，例如，一个像素电路50包含在一个子像素P中。在一些实施例中，显示面板还包括多个发光器件。多个发光器件设置于衬底上且位于显示区AA内。一个发光器件包含在一个子像素中。例如，一个像素电路与一个发光器件耦接，像素电路用于向驱动发光器件提供驱动电流，以驱动发光器件工作。例如，参考图9，显示面板100还包括第三导电图案130，设置于第一电极71靠近衬底101的一侧；发光器件70的第一电极71通过第三导电图案130与像素电路50耦接。
本公开的实施例对像素电路的具体结构不作限定，可以根据实际情况进行设计。像素电路由薄膜晶体管(Thin Film Transistor，TFT)、电容(Capacitor，C)等电子器件组成。在一些示例中，像素电路可以包括两个薄膜晶体管(一个开关晶体管和一个驱动晶体管)和一个电容，构成2T1C结构；在另一些示例中，像素电路还可以包括两个以上的薄膜晶体管(多个开关晶体管和一个驱动晶体管)和至少一个电容，例如参考图8，像素电路50可以包括电容Cst和七个晶体管(六个开关晶体管M1、M2、M3、M5、M6和M7以及一个驱动晶体管M4)，构成7T1C结构。需要说明的是，文中的一些附图(例如图9等)以像素电路中的一个晶体管为例来代表像素电路，实际像素电路的结构不限于此。
例如，如图8所示，一部分开关晶体管(例如，M1、M7)的控制极(栅极)用于接收复位信号Reset。另一部分开关晶体管(例如，M2、M3)的控制极用于接收栅极驱动信号Gate。又一部分开关晶体管(例如，M5、M6)的控制极用于接收发光控制信号EM。例如，像素电路响应于复位信号Reset，晶体管M1和晶体管M7导通。初始信号Initial通过晶体管M1和晶体管M7，分别传输至驱动晶体管M4的控制极(g)以及发光器件70，达到对发光器件70以及驱动晶体管M4的控制极进行复位的目的。之后，在栅极驱动信号Gate的控制下，晶体管M2导通，驱动晶体管M4的控制极g与漏极(d)耦接，该驱动晶体管M4成二极管导通状态。此时，数据信号Data通过该晶体管M2写入至驱动晶体管M4的源极(s)，并对驱动晶体管M4的阈值电压(Vth)进行补偿。之后，在发光控制信号EM的控制下，晶体管M5和晶体管M6导通，高水平电源电压(或称为第一电源电压)V DD与低水平电源电压(或称为第二电源电压)V SS之间的电流通路导通。驱动晶体管M4产生的驱动电流(I sd)通过上述电流通路传输至发光器件70，以驱动发光器件70进行发光。
在一些示例中，发光器件可以采用电流驱动型器件，进一步地，可以采 用电流型发光二极管，如微型发光二极管(Micro Light Emitting Diode，Micro LED)、迷你发光二极管(Mini Light Emitting Diode，Mini LED)、有机电致发光二极管(Organic Light Emitting Diode，OLED)或者量子点发光二极管(Quantum Light Emitting Diode，QLED)。
示例性地，参考图9，每个发光器件70包括第一电极71和第二电极72。第一电极71相比于第二电极72靠近衬底101。例如，第一电极和第二电极分别为阳极和阴极。例如，参考图9，发光器件70还包括位于第二电极72和第一电极71之间的发光功能层73。其中，发光功能层例如可以包括发光层、位于发光层和第一电极之间的空穴传输层(Hole Transport Layer，HTL)、位于发光层和第二电极之间的电子传输层(Electron Transport Layer，ETL)。当然，根据需要在一些实施例中，还可以在空穴传输层和第一电极之间设置空穴注入层(Hole Injection Layer，HIL)，可以在电子传输层和第二电极之间设置电子注入层(Electron Injection Layer，EIL)。
在一些示例中，第一电极例如可由具有高功函数的透明导电材料形成，其电极材料可以包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟镓(IGO)、氧化镓锌(GZO)氧化锌(ZnO)、氧化铟(In 2O 3)、氧化铝锌(AZO)和碳纳米管等；第二电极例如可由高导电性和低功函数的材料形成，其电极材料可以包括镁铝合金(MgAl)和锂铝合金(LiAl)等合金或者镁(Mg)、铝(Al)、锂(Li)和银(Ag)等金属单质。发光层的材料可以根据其发射光颜色的不同进行选择。例如，发光层的材料包括荧光发光材料或磷光发光材料。例如，在本公开的一些实施例中，发光层可以采用掺杂体系，即在主体发光材料中混入掺杂材料来得到可用的发光材料。例如，主体发光材料可以采用金属化合物材料、蒽的衍生物、芳香族二胺类化合物、三苯胺化合物、芳香族三胺类化合物、联苯二胺衍生物和三芳胺聚合物等。
示例性地，参考图9，显示面板100还包括像素界定层PDL，像素界定层可以用于限定子像素所在的区域，例如，可以用于限定发光器件70的发光功能层的形成位置。例如，发光功能层420位于像素界定层PDL的开口中。
其中，第二电极与屏蔽信号线耦接。例如，参考图10A和图10B，显示面板100还包括第四导电图案140，第四导电图案140相比于第二电极72靠近衬底101，第二电极72与第四导电图案140耦接，第四导电图案140与屏蔽信号线30耦接。例如，参考图10A，第四导电图案140与屏蔽信号线30同层设置；或者，参考图10B，第四导电图案140与第一电极71同层设置，第四导电图案140与第一电极71材料相同。需要说明的是，图10A和图10B 仅为示意图，具体的结构和连接方式可以根据实际情况进行设计。其中，第二电极接收来自屏蔽信号线的直流信号，该直流信号为直流低电压。
在一些实施例中，参考图1，屏蔽信号线30位于周边区S内且围绕显示区AA。显示区AA中的多个发光器件的第二电极可以与屏蔽信号线耦接，可以相对均匀地接收来自屏蔽信号线上传输的直流信号(例如直流低电压)，从而降低阻抗。例如，第二电极覆盖显示区AA；可以通过蒸镀工艺形成覆盖显示区AA的第二电极。
在一些实施例中，如图7所示，显示面板100还包括驱动电路60。驱动电路60设置于衬底101上且位于周边区S内。驱动电路60分别与多个像素电路50、第一信号线10和第二信号线20耦接。
其中，驱动电路被配置为响应于在第一信号线处接收的第一信号和在第二信号线处接收的第二信号，向多个像素电路提供驱动信号，以驱动多个像素电路工作。例如，多个像素电路呈阵列排布；驱动电路用于向每行像素电路逐行提供驱动信号，使得多个像素电路实现逐行工作。示例性地，驱动电路提供的驱动信号可以包括栅极扫描信号(Gate)或发光控制信号(EM)。
示例性地，驱动电路包括多个移位寄存器。例如，参考图11和图12，驱动电路60包括多个移位寄存器SR(例如SR(1)、SR(2)、SR(3)、SR(4)……)。例如，多个移位寄存器SR级联；例如，第一级移位寄存器(例如图11中的移位寄存器SR(1))的输入端与起始信号线(例如图11中的起始信号线STV)耦接，移位寄存器SR(1)的输出端Oput与移位寄存器SR(2)的输入端Iput耦接，移位寄存器SR(2)的输出端Oput与移位寄存器SR(3)的输入端Iput耦接，移位寄存器SR(3)的输出端Oput与移位寄存器SR(4)的输入端Iput耦接，依次类推。
例如，一个移位寄存器与一行像素电路耦接，该移位寄存器用于向一行像素电路输出驱动信号。例如，参考图11，驱动电路60中的移位寄存器SR输出的驱动信号为栅极驱动信号Gate，例如，第一级移位寄存器SR(1)输出栅极驱动信号Gate(1)，以驱动第一行像素电路工作，第二级移位寄存器SR(2)输出栅极驱动信号Gate(2)，以驱动第二行像素电路工作，第三级移位寄存器SR(3)输出栅极驱动信号Gate(3)，以驱动第三行像素电路工作，第四级移位寄存器SR(4)输出栅极驱动信号Gate(4)，以驱动第四行像素电路工作，依次类推。例如，参考图12，驱动电路60中的移位寄存器SR输出的驱动信号为发光控制信号EM，例如，第一级移位寄存器SR(1)输出发光控制信号EM(1)，以驱动第一行像素电路工作，第二级移位寄存器SR(2)输出发光控制信号EM(2)，以驱动第二行像素电路工作，第三级移位寄存器SR(3)输出发光控制 信号EM(3)，以驱动第三行像素电路工作，第四级移位寄存器SR(4)输出发光控制信号EM(4)，以驱动第四行像素电路工作，依次类推。
在此情况下，驱动电路的数量可以为多个。例如，多个驱动电路包括第一驱动电路和第二驱动电路。第一驱动电路用于输出栅极扫描信号，第二驱动电路用于输出发光控制信号。其中，至少一条第一信号线包括两条第一信号线，第一驱动电路与两条第一信号线中的一条第一信号线耦接，第二驱动电路与两条第一信号线中的另一条第一信号线耦接。两条第一信号线上传输的第一信号不相同；例如，两条第一信号线上传输的第一信号可以是相同类型，但是信号时序、电压幅值不同。同样，至少一条第二信号线包括两条第二信号线，第一驱动电路与两条第二信号线中的一条第二信号线耦接，第二驱动电路与两条第二信号线中的另一条第一信号线耦接。两条第二信号线上传输的第二信号不相同；例如，两条第二信号线上传输的第二信号可以是相同类型，但是信号时序、电压幅值不同。
示例性地，本公开的实施例对驱动电路的具体结构不作限定，可以根据实际情况进行设计。另外，本公开的实施例对移位寄存器的具体结构不作限定，可以根据实际情况进行设计。示例性地，移位寄存器由晶体管和电容等电子器件组成。例如，参考图13，移位寄存器SR可以包括多个晶体管(例如T1、T2、T3、T4、T5、T6、T7、T8、T9)和一个电容(例如Ct)。其中，晶体管T1的控制极和第一极与输入端Iput耦接，晶体管T2的第一极与第一时钟信号端CK1耦接，晶体管T2的第二极与输出端Oput耦接，晶体管T4的控制极和第一极与第二时钟信号端CK2耦接，晶体管T5的第一极与第二时钟信号端CK2耦接。另外，晶体管T3的控制极降噪信号端RST耦接，晶体管T3、T6、T7、T8和T9均与电压端VL耦接。例如，奇数级移位寄存器(例如图11中的SR(1)和SR(3))的第一时钟信号端CK1与第一信号线10耦接，可以传输第一信号，第二时钟信号端CK2与第二信号线20耦接，可以传输第二信号。偶数级移位寄存器(例如图11中的SR(2)和SR(4))的第一时钟信号端CK1与第二信号线20耦接，第二时钟信号端CK2与第一信号线10耦接；此时，第一信号和第二信号均为时钟信号，且互为反转信号。另外，电压端VL与电压线VGL耦接，例如电压线VGL用于传输直流低电压信号。
示例性地，本公开的实施例对显示面板的驱动方式不作限定，可以根据实际情况进行设计。例如，图7仅示意出了以采用单侧驱动(即在显示面板100的周边区S的单侧设置驱动电路60，从单侧逐行依次驱动子像素中的像素电路)。例如，显示面板可以采用双侧同时驱动(即在显示面板100的周 边区S中沿像素电路排列的行方向(或子像素排列的行方向，例如图7中的第一方向X)上的两个侧边分别设置驱动电路60，通过两个驱动电路60同时从两侧逐行依次驱动子像素中的像素电路)。例如，显示面板100可以采用双侧交叉驱动(即在显示面板100的周边区S中沿像素电路排列的行方向上的两个侧边分别设置驱动电路60，通过两个驱动电路60交替从两侧，逐行依次驱动子像素中的像素电路)。在此情况下，至少一条第一信号线包括多条第一信号线，至少一条第二信号线包括多条第二信号线，多条第一信号线和多条第二信号线分别位于显示区在像素电路排列的行方向上的相对两侧以外。
在一些实施例中，如图14所示，发光器件70的第一电极71与屏蔽信号线30同层设置。例如，屏蔽信号线的材料与第一电极的材料相同。例如，屏蔽信号线的材料可以包括透明导电材料，例如ITO等。例如，屏蔽信号线与第一电极可以由同一膜层构图形成。这样，可以简化工艺步骤，节约成本。并且，屏蔽信号线与第二电极之间存在的膜层的厚度相对较小，可以方便第二电极与屏蔽信号线的耦接。
示例性地，绝缘层为双层结构；即绝缘层的层数为双层，也即第一信号线和第二信号线所在膜层与屏蔽信号线所在膜层之间的绝缘层有两层。例如，参考图14，双层结构的绝缘层40包括第一绝缘层PLN1和第二绝缘层PLN2。第一绝缘层PLN1和第二绝缘层PLN2沿垂直于衬底101的方向层叠设置，且第二绝缘层PLN2相比于第一绝缘层PLN1远离衬底101。示例性地，凹槽的底面由第一绝缘层构成，凹槽的侧壁由第二绝缘层和第一绝缘层构成。例如，沿垂直于衬底所在平面的方向，凹槽贯通第二绝缘层，凹槽的深度大于第二绝缘层的厚度，且小于绝缘层的厚度(即第一绝缘层和第二绝缘层的厚度之和)。
在一些实施例中，如图15所示，发光器件70的第一电极71相比于屏蔽信号线30远离衬底101。例如，屏蔽信号线的材料可以包括金属材料。示例性地，绝缘层为单层结构，即绝缘层的层数为一层，也即第一信号线和第二信号线所在膜层与屏蔽信号线所在膜层之间的绝缘层有一层。例如，参考图15，单层结构的绝缘层40可以被看作为第一绝缘层(PLN1)。在此情况下，第一信号线和第二信号线所在膜层与屏蔽信号线所在膜层之间的膜层厚度较小，从而可以提高屏蔽信号线对第一信号线和第二信号线之间信号干扰的屏蔽效果。另外，在此情况下，位于发光器件的第一电极所在膜层与屏蔽信号线所在膜层之间的膜层可以为第二绝缘层(PLN2)。
示例性地，在显示面板不包括第一导电图案和第二导电图案的情况下，位于第一信号线和第二信号线所在膜层(例如第一导电层)与屏蔽信号线所在膜层之间的绝缘膜层可以有双层，例如第一绝缘层(PLN1)和第二绝缘层(PLN2)。又示例性地，在显示面板包括第一导电图案和第二导电图案的情况下，位于第一信号线和第二信号线所在膜层(例如第一导电层)与屏蔽信号线所在膜层之间的绝缘膜层可以有单层，例如第一绝缘层(PLN1)。位于第一导电图案与第二导电图案所在膜层(例如第二导电层)和第一信号线与第二信号线所在膜层(例如第一导电层)之间的膜层可以为层间介质层(ILD)；位于发光器件的第一电极所在膜层与屏蔽信号线所在膜层之间的膜层可以为第二绝缘层(PLN2)。
另外，例如，晶体管包括有源图案(也即有源层)、栅极(例如控制极)、源极和漏极，显示面板还包括位于晶体管的栅极和有源图案之间的栅绝缘层(GI)，源极和漏极位于栅极远离衬底的一侧，源极和漏极同层设置，源极和漏极与有源图案耦接。例如，源极和漏极与栅极之间存在层间介质层(ILD)。例如，源极和漏极可以与第一信号线和第二信号线同层设置；或者，例如，源极和漏极所在膜层可以相比于第一信号线和第二信号线所在膜层更靠近衬底，例如，第一信号线和第二信号线所在膜层与源极和漏极所在膜层之间存在第一绝缘层(PLN1)。
示例性地，本公开的实施例对晶体管的类型不作限定，可以根据实际情况进行设计。例如，本公开的实施例中所采用的晶体管可以为P型晶体管或N型晶体管，可以为底栅型晶体管或顶栅型晶体管。例如，本公开的实施例中所采用的晶体管可以为薄膜晶体管、场效应晶体管(Field Effect Transistor，FET)或其他特性相同的开关器件，本公开的实施例对此并不设限。例如，采用的晶体管可以包括金属氧化物薄膜晶体管(例如有源图案的材料采用IGZO的薄膜晶体管)和低温多晶硅薄膜晶体管(例如有源图案的材料采用P-Si的薄膜晶体管)等。其中，各晶体管的控制极为晶体管的栅极，第一极为晶体管的源极和漏极中一者，第二极为晶体管的源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。
本公开的实施例提供一种显示装置。该显示装置包括上述任一项实施例中的显示基板。例如，如图16所示，显示装置200还包括控制芯片300，该控制芯片300与显示面板100耦接。示例性地，控制芯片可以包括时序控制 器(Timing Controller，TCON)。其中，控制芯片被配置为向显示面板提供信号。例如，控制芯片可以向显示面板中的第一信号线提供第一信号，向第二信号线提供第二信号，向屏蔽信号线提供直流信号。
此外，显示装置还可以包括设置于显示面板周围的外框。
示例性地，上述显示装置可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
需要说明的是，为表示清楚，并没有叙述该显示面板的全部结构。为实现显示面板的必要功能，本领域技术人员可以根据具体应用场景进行设置其他结构，本公开的实施例对此不做限制。显示装置具有与上述显示面板具有相同的有益效果，此处不再赘述。
本公开的一些实施例提供一种显示面板的制备方法。例如，显示面板可以为上述任一实施例中所述的显示面板，例如，参考图1中的显示面板100。
其中，制备方法包括以下步骤S10～S40。
S10、参考图1，提供衬底101。其中，衬底101具有显示区AA和位于显示区AA外的周边区S。
示例性地，衬底可以为玻璃板、石英板、金属板或树脂类板件等。例如，衬底的材料可以包括有机材料，例如该有机材料可以包括聚酰亚胺、聚碳酸酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜、聚对苯二甲酸乙二醇酯和聚萘二甲酸乙二醇酯等树脂类材料。例如，该衬底可以由多个材料层形成，例如衬底可以包括基板，基板的材料可以由上述的材料构成，基板的表面上可以形成缓冲层以作为过渡层，其即可以防止衬底中的有害物质侵入显示面板的内部，又可以增加显示面板中的膜层在衬底上的附着力。例如，缓冲层的材料可以包括氧化硅、氮化硅或氧氮化硅等。
S20、参考图1，在衬底101的周边区S内形成至少一条第一信号线10和至少一条第二信号线20。其中，一条第一信号线10的位置与一条第二信号 线20的位置相邻。
示例性地，参考图17A和图17B，在衬底101的周边区S内形成导电薄膜801，对该导电薄膜801进行图案化，得到至少一条第一信号线10和至少一条第二信号线20。
例如，在衬底上可以形成驱动电路和像素电路。其中，在衬底上形成驱动电路和像素电路的制备方法与晶体管的类型有关，例如，晶体管可以为顶栅型、底栅型、双栅型或者其它类型的薄膜晶体管。在衬底上形成驱动电路层的过程可以参见常规工艺，在此不做赘述。例如，参考图17A和图17B，可以在衬底101的显示区AA内可以形成像素电路50；例如，可以在形成至少一条第一信号线和至少一条第二信号线的同时，形成像素电路中的各个晶体管的源极和漏极。
S30、参考图2，形成绝缘层40。其中，绝缘层40覆盖至少一条第一信号线10和至少一条第二信号线20。绝缘层40在远离衬底101的一侧的表面形成有至少一个凹槽41。一个凹槽41的底面F3在衬底101上的正投影位于相邻的第一信号线10和第二信号线20在衬底101上的正投影之间。
例如，绝缘层的材料可以采用有机材料，例如环氧树脂、聚酰亚胺、聚酰胺、丙烯酸或其他合适的材料。
在一些示例中，形成绝缘层，可以包括以下步骤。
参考图18A，在至少一条第一信号线10和至少一条第二信号线20远离衬底101的一侧形成绝缘材料层802。例如，可以在至少一条第一信号线10和至少一条第二信号线20远离衬底101的一侧沉积绝缘材料，得到绝缘材料层802。参考图18B，在绝缘材料层802上形成光刻胶层803。例如，该光刻胶层的材料采用光敏树脂材料，例如，光刻胶；例如，该光敏树脂材料为正性光刻胶。参考图18B，采用半色调掩膜板90曝光光刻胶层803，显影光刻胶层803，形成光刻胶层全部去除区813、光刻胶层半保留区823以及光刻胶层全部保留区833。例如，光刻胶层全部去除区可以对应于绝缘材料层中的待形成的过孔的部分，光刻胶层半保留区可以对应于绝缘材料层中的待形成的凹槽的部分，光刻胶层全部保留区可以对应于绝缘材料层中的剩余部分。
例如，参考图18B，半色调掩模板90包括第一区域91、第二区域92和第三区域93。第一区域91、第二区域92和第三区域93的透光率依次减小，例如第一区域91可以设置为开口，例如第三区域93设置为不透光。如此，通过设计第一区域91、第二区域92和第三区域93的透光率，并在曝光过程中控制曝光强度，以使得光刻胶层803的与第一区域91对应的部分被完全曝 光、光刻胶层803的与第二区域92对应的部分被完全曝光、光刻胶层803的与第三区域93对应的部分不被曝光。
参考图18B和图18C，蚀刻绝缘材料层802，去除绝缘材料层802中位于光刻胶层全部去除区813的部分。采用灰化工艺，去除光刻胶层803中位于光刻胶半保留区823的部分。蚀刻绝缘材料层802中位于光刻胶层半保留区823的部分，形成至少一个凹槽41。剥离剩余的光刻胶层803，得到绝缘层40。
需要说明的是，采用上述的形成绝缘层的步骤，可以得到单层结构的绝缘层，或者双层结构的绝缘层。其中，参考图14，双层结构的绝缘层40包括第一绝缘层(PLN1)和第二绝缘层(PLN2)；参考图15，双层结构的绝缘层40包括第一绝缘层(PLN1)。对于双层结构的绝缘层的具体制备过程，可以参考上文描述，在此不作赘述。
S40、参考图1和图2，形成屏蔽信号线30，屏蔽信号线30覆盖至少一个凹槽41。例如，可以在衬底上沉积导电材料，得到导电材料层，对导电材料层进行图案化，得到屏蔽信号线。
示例性地，参考图19，在衬底101的周边区S形成屏蔽信号线30的同时，可以在显示区AA形成第三导电图案130，该第三导电图案130通过位于绝缘层40上的过孔与像素电路50耦接。例如，第三导电图案与像素电路中的驱动晶体管的漏极耦接。之后，参考图15，在衬底上形成发光器件70的过程中，发光器件70的第一电极71可以通过第三导电图案130与像素电路50耦接。在此情况下，屏蔽信号线相比于发光器件的第一电极靠近衬底。
例如，参考图14，绝缘层40为双层结构，双层结构的绝缘层40包括第一绝缘层(PLN1)和第二绝缘层(PLN2)，可以在第二绝缘层(PLN2)上形成透明导电材料层，对该透明导电材料层进行图案化，得到屏蔽信号线，并同步得到发光器件的第一电极。
需要说明的是，上述显示面板的制备方法的有益效果和上述实施例所述的显示面板的有益效果相同，此处不再赘述。
需要说明的是，本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不 局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种显示面板，具有显示区和位于所述显示区外的周边区；所述显示面板包括：
    衬底；
    至少一条第一信号线，设置于所述衬底上且位于所述周边区内；
    至少一条第二信号线，设置于所述衬底上且位于所述周边区内；其中，所述至少一条第二信号线和所述至少一条第一信号线同层设置；
    绝缘层，覆盖所述至少一条第一信号线和所述至少一条第二信号线；其中，所述绝缘层在远离所述衬底的一侧的表面设置有至少一个凹槽；一个凹槽的底面在所述衬底上的正投影位于一条第一信号线和一条第二信号线在所述衬底上的正投影之间；以及
    屏蔽信号线，覆盖所述至少一个凹槽。
  2. 根据权利要求1所述的显示面板，其中，沿垂直于衬底所在平面的方向，相比于所述第一信号线和所述第二信号线中的至少一者的顶面，所述凹槽的底面更靠近所述衬底。
  3. 根据权利要求1或2所述的显示面板，其中，所述第一信号线和所述第二信号线相邻；
    所述凹槽的底面在所述衬底上的正投影的宽度，小于或等于所述第一信号线和所述第二信号线在所述衬底上的正投影中相互靠近的两个边沿之间的距离。
  4. 根据权利要求1～3中任一项所述的显示面板，其中，所述凹槽的底面在所述衬底上的正投影的宽度为2μm～10μm。
  5. 根据权利要求1～4中任一项所述的显示面板，其中，所述第一信号线的延伸方向和所述第二信号线的延伸方向相同；
    所述凹槽沿所述第一信号线和所述第二信号线的延伸方向延伸。
  6. 根据权利要求1～5中任一项所述的显示面板，其中，所述屏蔽信号线在所述衬底上的正投影覆盖所述第一信号线在所述衬底上的正投影和所述第二信号线在所述衬底上的正投影。
  7. 根据权利要求1～6中任一项所述的显示面板，其中，所述屏蔽信号线位于所述周边区内且围绕所述显示区。
  8. 根据权利要求1～7中任一项所述的显示面板，其中，所述第一信号线被配置为传输第一信号；所述第二信号线被配置为传输第二信号；所述第一信号和所述第二信号均为脉冲信号，且所述第一信号和所述第二信号不相同；
    所述屏蔽信号线被配置为传输直流信号。
  9. 根据权利要求8所述的显示面板，其中，所述第一信号和所述第二信号具有相同的脉冲周期；所述第一信号和所述第二信号具有相位差。
  10. 根据权利要求9所述的显示面板，其中，所述脉冲周期为4μs～100μs。
  11. 根据权利要求1～10中任一项所述的显示面板，还包括：
    多个发光器件，设置于所述衬底上且位于所述显示区内；
    每个发光器件包括第一电极和第二电极；其中，所述第一电极相比于所述第二电极靠近所述衬底；所述第二电极与所述屏蔽信号线耦接。
  12. 根据权利要求11所述的显示面板，其中，所述发光器件的第一电极与所述屏蔽信号线同层设置；
    所述绝缘层为双层结构。
  13. 根据权利要求11所述的显示面板，其中，所述发光器件的第一电极相比于所述屏蔽信号线远离所述衬底；
    所述绝缘层为单层结构。
  14. 根据权利要求1～13中任一项所述的显示面板，还包括：
    多个像素电路，设置于所述衬底上且位于所述显示区内；以及
    驱动电路，设置于所述衬底上且位于所述周边区内；其中，所述驱动电路分别与所述多个像素电路、所述第一信号线和所述第二信号线耦接；
    所述驱动电路被配置为，响应于在所述第一信号线处接收的第一信号和在所述第二信号线处接收的第二信号，向所述多个像素电路提供驱动信号，以驱动所述多个像素电路工作。
  15. 一种显示装置，包括：
    如权利要求1～14中任一项所述的显示面板；以及
    控制芯片，与所述显示面板耦接；所述控制芯片被配置为向所述显示面板提供信号。
  16. 一种显示面板的制备方法，包括：
    提供衬底，其中，所述衬底具有显示区和位于所述显示区外的周边区；
    在所述衬底的周边区内形成至少一条第一信号线和至少一条第二信号线；
    形成绝缘层，其中，所述绝缘层覆盖所述至少一条第一信号线和所述至少一条第二信号线；所述绝缘层在远离所述衬底的一侧的表面形成有至少一个凹槽；一个凹槽的底面在所述衬底上的正投影位于一条第一信号线和一条第二信号线在所述衬底上的正投影之间；以及
    形成屏蔽信号线，其中，所述屏蔽信号线覆盖所述至少一个凹槽。
  17. 根据权利要求16所述的制备方法，其中，形成所述绝缘层，包括：
    在所述至少一条第一信号线和所述至少一条第二信号线远离所述衬底的一侧形成绝缘材料层；
    在所述绝缘材料层上形成光刻胶层；
    采用半色调掩膜板曝光所述光刻胶层，显影所述光刻胶层，形成光刻胶层全部去除区、光刻胶层半保留区以及光刻胶层全部保留区；
    蚀刻所述绝缘材料层，去除所述绝缘材料层中位于所述光刻胶层全部去除区的部分；
    采用灰化工艺，去除所述光刻胶层中位于所述光刻胶层半保留区的部分；
    蚀刻所述绝缘材料层中位于所述光刻胶层半保留区的部分，形成所述至少一个凹槽；以及
    剥离剩余的光刻胶层，得到所述绝缘层。
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