WO2023142071A1 - 阵列基板、显示面板及显示装置 - Google Patents

阵列基板、显示面板及显示装置 Download PDF

Info

Publication number
WO2023142071A1
WO2023142071A1 PCT/CN2022/075077 CN2022075077W WO2023142071A1 WO 2023142071 A1 WO2023142071 A1 WO 2023142071A1 CN 2022075077 W CN2022075077 W CN 2022075077W WO 2023142071 A1 WO2023142071 A1 WO 2023142071A1
Authority
WO
WIPO (PCT)
Prior art keywords
row
driving electrodes
area
driving
sub
Prior art date
Application number
PCT/CN2022/075077
Other languages
English (en)
French (fr)
Inventor
程羽雕
闫卓然
黄耀
王琦伟
龙跃
黄炜赟
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280000102.6A priority Critical patent/CN116897430A/zh
Priority to PCT/CN2022/075077 priority patent/WO2023142071A1/zh
Priority to PCT/CN2022/092866 priority patent/WO2023142307A1/zh
Priority to CN202280001208.8A priority patent/CN117280894A/zh
Publication of WO2023142071A1 publication Critical patent/WO2023142071A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel and a display device.
  • optical elements such as an image acquisition device in a display device are arranged below the display screen to increase the gap between the area of the display screen and the area of the front panel of the display device. ratio and make it close to 100%.
  • an array substrate has a first area and a second area, and the second area surrounds at least part of the first area.
  • the array substrate includes: multiple rows of first driving electrodes and multiple connecting lines. Multiple rows of first drive electrodes are located in the first region; one connection line is electrically connected to one first drive electrode in a row of first drive electrodes; at least one row of the first drive electrodes is connected to a connection line via at least one row line.
  • the area extends to the second area, and a line area is adjacent to a row of first driving electrodes; at least one row of connecting lines connected to the first driving electrodes is located in a different layer.
  • At least some of the plurality of connecting lines are transparent connecting lines; at least one row of transparent connecting lines connected to the first driving electrodes extends to the the second area; and at least one row of transparent connection lines connected to the first driving electrodes are located in different layers.
  • At least one row of transparent connecting lines connected to the first driving electrodes includes: first-type transparent connecting lines and second-type transparent connecting lines;
  • the first driving electrodes electrically connected to one type of transparent connecting lines are closer to the center of the row of the first driving electrodes than the first driving electrodes electrically connected to the second type of transparent connecting lines; wherein The number of the first type of transparent connection lines is greater than the number of the second type of transparent connection lines, and the first type of transparent connection lines and the second type of transparent connection lines are located in different layers.
  • At least one row of the first-type transparent connection lines connected to the first driving electrodes is connected to the first driving electrode on the same side as the row of the first driving electrodes and is closest to the row of the first driving electrodes.
  • the wiring area in row N1 extends to the second area, and N1 is a positive integer greater than or equal to 2.
  • the first driving electrodes in the adjacent N2 rows are taken as a period; N2 is a positive integer greater than or equal to 2; in the same period, the first driving electrodes connected to the first driving electrodes in each row A class of transparent connection lines are located in different layers.
  • At least part of the second-type transparent connecting lines connected to at least one row of the first driving electrodes, and any row of the first driving electrodes in the same cycle as the row of the first driving electrodes are arranged on the same layer, and all the first-type transparent connection lines connected to the row of first drive electrodes in the same cycle as the row of first drive electrodes are located.
  • the routing area extends to the second area.
  • At least part of the second-type transparent connecting lines connected to at least one row of the first driving electrodes, and any row of the first driving electrodes in a different period from the row of the first driving electrodes are arranged on the same layer, and all the first-type transparent connection lines connected to the row of first drive electrodes in a different period from the row of first drive electrodes are located.
  • the routing area extends to the second area.
  • At least some of the plurality of connecting lines are transparent connecting lines; the first area includes at least two sub-areas arranged in sequence along a set direction, and the set direction is defined by a row.
  • the centers of the first driving electrodes point to one end of the row of the first driving electrodes; the transparent connection lines connected to the first driving electrodes in different sub-regions are respectively located in different layers.
  • the at least two sub-regions include a first sub-region, a second sub-region, and a third sub-region sequentially arranged along the set direction.
  • the number of the first driving electrodes located in different sub-regions is equal.
  • At least one row of transparent connection lines connected to the first driving electrodes extends to the second region via at least one row of the wiring regions adjacent to the row of first driving electrodes.
  • the first area further includes an edge area, and the edge area is located between the at least two sub-areas and the second area in the set direction; among the plurality of connecting lines At least part of the connection lines are metal connection lines; in the edge area, at least the connection lines connected to the first driving electrodes corresponding to the green sub-pixel area are metal connection lines.
  • connection lines are metal connection lines; the connection lines connected to at least one row of the first driving electrodes further include the metal connection lines; Among the first driving electrodes, the first driving electrode electrically connected to the metal connecting line is farther away from the first driving electrode in the row than the first driving electrode electrically connected to the transparent connecting line. center of the electrode.
  • the number of the first driving electrodes electrically connected to the metal connection line does not exceed a first threshold value, and the value range of the first threshold value is 2- 5.
  • multiple rows of first driving circuits are located in the second region; one of the first driving electrodes in one row of the first driving electrodes is connected to the first driving electrodes in one row of the first driving circuits through one of the connecting lines.
  • a first driving circuit is electrically connected; wherein, among the connecting lines connected to a row of the first driving electrodes, the length of the metal connecting line is shorter than the length of the transparent connecting line.
  • the metal connecting wires connected to the first driving electrodes that are farther away from the center of a row of first driving electrodes are shorter; and/or, the farther away from the center of a row of first driving electrodes The shorter the transparent connecting line connected to the first driving electrode.
  • a row of the first driving circuits and a row of the first driving electrodes are electrically connected in a manner of being close to each other and being far away from each other.
  • the array substrate further includes: multiple rows of second driving electrodes located in the second area; multiple rows of second driving circuits located in the second area;
  • the second drive circuit is electrically connected to one second drive electrode in a row of second drive electrodes; wherein, the first drive circuit in a row is distributed among multiple second drive circuits in a row of second drive circuits .
  • the second area includes a first sub-area and a second sub-area, and the first sub-area is adjacent to the first area; wherein, the second sub-area located in the first sub-area
  • the area of the driving electrode is smaller than the area of the second driving electrode located in the second sub-region, and the area of the first driving electrode is smaller than the area of the second driving electrode located in the second sub-region; all The first driving electrodes and all the second driving electrodes located in the first sub-region are divided into multiple repeating units, and one repeating unit includes 2k rows and 4h column driving electrodes; wherein, k and h are greater than or equal to 1 positive integer of .
  • the entire boundary of the first region and the first subregion includes a straight line segment and a stepped line segment, and two adjacent straight line segments are connected by one stepped line segment; wherein, the The ladder line segment includes a plurality of sub-line segments connected in sequence, and one sub-line segment straddles 2k row driving electrodes or 4h column driving electrodes.
  • At least one of the second driving electrodes located in the first sub-region has the same body shape as at least one of the first driving electrodes; and/or, located in the first sub-region The area of at least one of the second driving electrodes is equal to the area of at least one of the first driving electrodes.
  • the main body shape of the first driving electrode is oval or circular; the main body shape of the second driving electrode located in the first sub-region is oval or circular.
  • the array substrate further includes: a substrate; a driving circuit layer located on one side of the substrate, and both the first driving circuit and the second driving circuit are located in the driving circuit layer ;
  • the driving circuit layer includes a first source-drain electrode layer and a second source-drain electrode layer away from the substrate in turn; at least two transparent conductive layers located on the side of the driving circuit layer away from the substrate; wherein , the transparent connection line is located in the transparent conductive layer, and the metal connection line is located in the first source-drain electrode layer or the second source-drain electrode layer.
  • both the first region and the second region have a plurality of sub-pixel regions; the size of the metal connection line in the row direction is larger than the size of one sub-pixel region in the row direction.
  • the first area includes an optical component area; the minimum distance between the metal connection line and the optical component area is greater than the size of one sub-pixel area in the row direction.
  • the length of the portion of the metal connection line located in the first area is shorter than the length of the portion of the metal connection line located in the second area.
  • a display panel in another aspect, includes: the array substrate as described in any one of the above embodiments; a light-emitting functional layer located on one side of the array substrate; a common electrode layer located on a side of the light-emitting functional layer away from the array substrate; and, An encapsulation layer located on a side of the common electrode layer away from the array substrate.
  • a display device in yet another aspect, includes: the display panel and optical components as described in the above embodiments.
  • the orthographic projection of the optical component on the display panel is located in the first area.
  • FIG. 1 is a structural diagram of an array substrate according to some embodiments of the present disclosure
  • Figure 2 is a cross-sectional view of the array substrate shown in Figure 1 along the A-A' direction;
  • FIG. 3 is a circuit diagram of a sub-pixel according to some embodiments of the present disclosure.
  • FIG. 4A is a partial structural view of a display substrate according to some embodiments of the present disclosure.
  • FIG. 4B is a partial structural view of another display substrate according to some embodiments of the present disclosure.
  • FIG. 4C is a partial structural view of another display substrate according to some embodiments of the present disclosure.
  • Fig. 5 is a partial structural diagram of another display substrate according to some embodiments of the present disclosure.
  • Fig. 6 is a partial structural view of another display substrate according to some embodiments of the present disclosure.
  • Fig. 7 is a partial structural diagram of another display substrate according to some embodiments of the present disclosure.
  • Fig. 8 is a partial structural view of another display substrate according to some embodiments of the present disclosure.
  • Fig. 9 is a partial structural view of another display substrate according to some embodiments of the present disclosure.
  • Fig. 10 is a partial structural diagram of another display substrate according to some embodiments of the present disclosure.
  • Fig. 11 is a structural diagram of a display panel according to some embodiments of the present disclosure.
  • Fig. 12 is a structural diagram of a display device according to some embodiments of the present disclosure.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality” means two or more.
  • the expressions “coupled” and “connected” and their derivatives may be used.
  • the term “connected” may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more elements are in direct physical or electrical contact.
  • the terms “coupled” or “communicatively coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited by the context herein.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, A and B A combination of A and C, a combination of B and C, and a combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations in shape from the drawings as a result, for example, of manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • the transistor used in the shift register can be a thin film transistor (Thin Film Transistor, referred to as TFT), a field effect transistor (Metal Oxide Semiconductor, MOS for short) or other switching devices with the same characteristics, the embodiments of the present disclosure are described by taking thin film transistors as examples.
  • TFT Thin Film Transistor
  • MOS Metal Oxide Semiconductor
  • the gate of each transistor used in each circuit is the gate of the transistor
  • the first pole is one of the source and drain of the transistor
  • the second pole is the source and drain of the transistor.
  • the two poles may be structurally indistinguishable.
  • the film layer where the source electrode and the drain electrode are located may be referred to as a source-drain electrode layer.
  • the capacitor can be a capacitive device that is independently manufactured through a process, for example, by making a special capacitive electrode to realize the capacitive device, and each capacitive electrode of the capacitor can be made through a metal layer, a semiconductor layer (such as doped polysilicon) ) and so on.
  • the capacitor can also be a parasitic capacitance between transistors, or it can be realized by the transistor itself and other devices and lines, or it can be realized by using the parasitic capacitance between the lines of the circuit itself.
  • nodes do not represent actual components, but represent the confluence points of relevant electrical connections in the circuit diagram, that is, these nodes are confluence points of relevant electrical connections in the circuit diagram, etc. Nodes that are made effective.
  • the transistors included in the circuits provided in the embodiments of the present disclosure may all be N-type transistors, or all may be P-type transistors. Alternatively, some of the transistors included in each circuit may be N-type transistors, and the other part may be P-type transistors.
  • active level refers to a level at which a transistor can be turned on.
  • the P-type transistor can be turned on under the control of a low-level signal
  • the N-type transistor can be turned on under the control of a high-level signal.
  • the transistors are all P-type transistors (at this time, the active level is low level) as an example for illustration. It should be noted that the transistors in the circuits mentioned below adopt the same conduction type, which can simplify the process flow, reduce process difficulty, and improve the yield of products (such as the array substrate 100, the display panel 1000 and the display device 2000).
  • some embodiments of the present disclosure provide an array substrate 100 having a first area A1 and a second area A2 , and the second area A2 surrounds at least part of the first area A1 .
  • the number of the first area A1 may be at least one, and the number of the second area A2 may be, for example, one.
  • the structure of the array substrate 100 will be schematically described.
  • the second area A2 may completely surround the first area A1 .
  • the shape of the first area A1 may be, for example, a circle, an ellipse, a rectangle or other irregular shapes.
  • the second area A2 may surround a part of the first area A1 , that is, a part of the boundary of the second area A2 is in contact with a part of the boundary of the first area A1 .
  • the shape of the first area A1 may be, for example, a rectangle, a rectangle with rounded corners, a drop shape, or a semicircle.
  • the above-mentioned array substrate 100 may include: a substrate 1 .
  • the aforementioned substrate 1 may be a rigid substrate.
  • the rigid substrate may be a glass substrate or a PMMA (Polymethyl methacrylate, polymethyl methacrylate) substrate or the like.
  • the aforementioned substrate 1 may be a flexible substrate.
  • the flexible substrate can be PET (Polyethylene terephthalate, polyethylene terephthalate) substrate, PEN (Polyethylene naphthalate two formic acid glycol ester, polyethylene naphthalate) substrate or PI ( Polyimide, polyimide) substrate, etc.
  • PET Polyethylene terephthalate, polyethylene terephthalate
  • PEN Polyethylene naphthalate two formic acid glycol ester, polyethylene naphthalate
  • PI Polyimide, polyimide
  • the array substrate 100 may further include: a driving circuit layer 2 disposed on the substrate 1 .
  • the driving circuit layer 2 may include multiple first driving circuits 21 and multiple second driving circuits 22 .
  • the structure of the first driving circuit 21 or the second driving circuit 22 may include structures such as “2T1C”, “6T1C”, “7T1C”, “6T2C” or “7T2C”.
  • T represents a transistor
  • the number before “T” represents the number of transistors
  • C represents a storage capacitor
  • the number before “C” represents the number of storage capacitors.
  • the structure of the first driving circuit 21 and the structure of the second driving circuit 22 may be the same, for example.
  • the structures of both are 7T1C structures.
  • FIG. 3 is an equivalent circuit diagram of the second driving circuit 22 , of course, the equivalent circuit diagram of the first driving circuit 21 may be the same as that shown in FIG. 3 .
  • the second drive circuit 22 includes: a switch transistor T1, a drive transistor T2, a compensation transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, a first reset transistor T6, a second reset transistor T7 and a storage capacitor Cst .
  • the first reset transistor T6 and the second reset transistor T7 can be turned on under the control of the reset signal, and receive signals from the initial signal terminal
  • the initial signal transmitted by Vinit the first reset transistor T6 can transmit the initial signal to one end of the storage capacitor Cst to reset it; the second reset transistor T7 can transmit the initial signal to the second pole of the second reset transistor T7, Reset it.
  • the driving transistor T2 may be turned on under the control of the initial signal.
  • the switching transistor T1 and the compensation transistor T3 can be turned on under the control of the scanning signal, and the data signal transmitted by the data signal terminal Data can be It is transmitted to the control electrode of the driving transistor T2 through the switching transistor T1, the driving transistor T2, and the compensation transistor T3 in sequence, and the control electrode of the driving transistor T2 is charged until the driving transistor T2 is turned off. At this time, compensation for the threshold voltage of the driving transistor T2 is completed.
  • the first light emission control transistor T4 and the second light emission control transistor T5 can be turned on under the control of the enable signal, and receive signals from For the first voltage signal of the first voltage signal terminal ELVDD, the driving transistor T2 can generate a driving signal according to the data signal and the first voltage signal, and transmit the driving signal difference to the second pole of the second reset transistor T7.
  • the plurality of second driving circuits 22 may be arranged in multiple columns along the first direction X, and in multiple rows along the second direction Y.
  • each column of second driving circuits 22 may include a plurality of second driving circuits 22 , and the plurality of second driving circuits 22 are arranged in sequence along the second direction Y.
  • Each row of second driving circuits 22 may include a plurality of second driving circuits 22 , and the plurality of second driving circuits 22 are arranged in sequence along the first direction X.
  • the first direction X intersects the second direction Y.
  • the angle between the first direction X and the second direction Y can be selected and set according to actual needs.
  • the included angle between the first direction X and the second direction Y is 85°, 88° or 90° and so on.
  • a row of the first driving circuits 21 is distributed among the plurality of second driving circuits 22 in a row of the second driving circuits 22 .
  • any two adjacent columns of the first driving circuits 21 may be spaced apart from the second driving circuits 22 having the same number of columns, thus ensuring the uniformity of the arrangement.
  • two columns of second driving circuits 22 are arranged between any two adjacent columns of first driving circuits 21 .
  • the driving circuit layer 2 included in the array substrate 100 may include a semiconductor layer, a first gate conductive layer, a second gate conductive layer, and a source-drain electrode layer stacked in sequence along a direction perpendicular to and away from the substrate 1. .
  • the semiconductor layer may include active layers of transistors in the first driving circuit 21 and the second driving circuit 22 .
  • the first gate conductive layer may include control electrodes of transistors in the first drive circuit 21 and the second drive circuit 22 , and a plate of each storage capacitor.
  • the first gate conductive layer may also include gate lines for transmitting scan signals and reset signal lines for transmitting reset signals.
  • the second gate conductive layer may include the other plate of each storage capacitor in the first driving circuit 21 and the second driving circuit 22 .
  • the second gate conductive layer may also include initial signal lines for transmitting initial signals.
  • the source-drain electrode layer may include the first pole and the second pole of each transistor in the first driving circuit 21 and the second driving circuit 22 .
  • the first source and the first The film layer where the drain is located may be called the first source-drain electrode layer; the film layer where the second source electrode and the second drain are located may be called the second source-drain electrode layer.
  • FIG. 2 only the first source-drain electrode layer 201 and the second source-drain electrode layer 202 are shown. The first source-drain electrode layer 201 and the second source-drain electrode layer 202 are sequentially away from the substrate 1 .
  • the array substrate 100 may further include: a driving electrode layer 3 located on a side of the driving circuit layer 2 away from the substrate 1 .
  • the above driving electrode layer 3 may include a plurality of first driving electrodes 31 and a plurality of second driving electrodes 32 .
  • one first driving circuit 21 may be electrically connected to one first driving electrode 31 .
  • the first driving circuit 21 can provide driving signals to the corresponding first driving electrodes 31 .
  • one second driving circuit 22 may be electrically connected to one second driving electrode 32 .
  • the second driving circuit 22 can provide driving signals to the corresponding second driving electrodes 32 .
  • the plurality of first driving circuits 21 and the plurality of second driving circuits 22 in the above-mentioned driving circuit layer 2 may both be located in the second area A2.
  • the plurality of first driving electrodes 31 in the above-mentioned driving electrode layer 3 may all be located in the first area A1, and the plurality of second driving electrodes 32 may all be located in the second area A2. That is, only a plurality of first driving electrodes 31 are provided in the first area A1, and no corresponding driving circuit is provided; the second driving electrodes 32 and the second driving electrodes 32 corresponding to the second driving electrodes 32 are provided in the second area A2.
  • a plurality of first driving circuits 21 are scattered and arranged on one side of the first area A1 .
  • a plurality of first driving circuits 21 are scattered and arranged on both sides of the first area A1 .
  • the second The second driving circuit 22 in the area A2 is compressed so that the first driving circuit 21 corresponding to the first driving electrode 31 is placed in the second area A2.
  • the first driving circuit 21 that provides the driving signal for the first driving electrode 31 is arranged in the second area A2, which reduces the structure that can block light in the first area A1, and the external light can also be transmitted from the array.
  • the substrate 100 is located on one side of the part of the first area A1 (for example, the light-emitting side), passes through the gap between any two adjacent first driving electrodes 31, and passes through the gap between any two adjacent first driving electrodes 31, from the other side of the part of the array substrate 100 located in the first area A1. (for example, the non-light-emitting side) is emitted, so that the part of the array substrate 100 located in the first area A1 has a higher light transmittance.
  • the distribution density of the plurality of first driving electrodes 31 and the distribution density of the plurality of second driving electrodes 32 may be the same.
  • the brightness and resolution difference between the first area A1 and the second area A2 can be reduced, a more uniform full-screen display effect can be achieved, and it is also beneficial to ensure that the array substrate 100 has better image display quality.
  • the distribution density of the plurality of first driving electrodes 31 may be smaller than the distribution density of the plurality of second driving electrodes 32 . Therefore, by increasing the distance between any two adjacent first driving electrodes 31, the shielding of external light by the first driving electrodes 31 can be reduced, and the medium transmittance of the first region A1 of the array substrate 100 can be increased.
  • the area of the light part can further increase the amount of external light that can pass through the part of the array substrate 100 located in the first area A1, so that the light transmittance of the part of the array substrate 100 located in the first area A1 is better.
  • the array substrate 100 may further include: at least two layers of transparent conductive layers 4 located on the side of the driving electrode layer 3 away from the substrate 1 .
  • the at least two transparent conductive layers 4 may be stacked in sequence along a direction perpendicular to the substrate 1 .
  • the number of transparent conductive layers 4 may be two layers, or three layers, etc.
  • the number of transparent conductive layers 4 is three.
  • the first transparent conductive layer 041, the second transparent conductive layer 042 and the third transparent conductive layer 043 are all located on the side of the driving electrode layer 3 away from the substrate 1, and the first transparent conductive layer 041, the second transparent conductive layer 042 and the third transparent conductive layer
  • the three transparent conductive layers 043 are separated from the substrate 1 in turn.
  • a row of wiring regions 04 is adjacent to a row of first driving electrodes 31 .
  • the above-mentioned array substrate 100 further includes: a plurality of connecting wires 40 .
  • the connecting wire 40 extends to the second area A2 via the wiring area 04 .
  • One end of a connection line 40 is electrically connected to one first driving electrode 31 in a row of first driving electrodes 31 , and the other end is electrically connected to the corresponding first driving circuit 21 located in the second area A2 . Therefore, the electrical connection between the first driving circuit 21 and the first driving electrodes 31 can be realized by using the connecting wires 40 , and the first driving circuit 21 can transmit driving signals to the corresponding first driving electrodes 31 through the connecting wires 40 .
  • connection lines 40 connected to the first driving electrodes 31 extends to the second area A2 through at least one line area 04 .
  • At least one row of connecting wires 40 connected to the first driving electrodes 31 extends to the second area A2 through at least one wiring area 04, and is electrically connected to the first driving circuit 21 located in the second area A2, so that the first driving circuit 21 Driving signals may be transmitted to the corresponding first driving electrodes 31 through the connecting wires 40 .
  • At least one row of the connecting lines 40 connected to the first driving electrodes 31 extends to the second area A2 via at least one routing area 04
  • the connecting line 40 extends to the second area A2 via a routing area 04; it may also be that at least one row of the connecting line 40 connected to the first driving electrodes 31 extends to the second area A2 via two or more routing areas 04 .
  • Various embodiments of the present disclosure do not limit this. For example, as shown in FIG. 5 and FIG. 6, at least one row of the connecting lines 40 connected to the first driving electrodes 31 extends to the second area A2 through two routing areas 04; as shown in FIG. 4A, at least one row of the first driving electrodes 31 A connection line 40 connected to a driving electrode 31 extends to the second area A2 through the three wiring areas 04 .
  • connection wires 40 connected to at least one row of the first driving electrodes 31 are located in different layers.
  • At least one row of the connecting wires 40 connected to the first driving electrodes 31 is located in different layers, which means: in the thickness direction of the array substrate 100 (for example, the direction a-a shown in FIG. 2 '), at least one row of the connecting wires 40 connected to the first driving electrodes 31 are located in different film layers.
  • the connecting line 40 to which a row of the first driving electrodes 31 is connected is located at least one source-drain electrode layer and at least one transparent conductive layer at the same time.
  • the connection wires 40 connected to the first driving electrodes 31 in one row are located on at least two transparent conductive layers at the same time.
  • the connecting wires 40 connected to at least one row of the first driving electrodes 31 on different layers by arranging the connecting wires 40 connected to at least one row of the first driving electrodes 31 on different layers, the electrical connection with the first driving electrodes 31 of one row can be increased.
  • the layout space of the connecting wires 40 thereby realizing the layout of a large number of connecting wires 40 in a limited space, avoiding that when the number of the first driving electrodes 31 in a row of the first driving electrodes 31 is large, it is impossible to arrange more connections on the same layer.
  • Lines 40 so that some of the first driving electrodes 31 cannot be electrically connected to the corresponding first driving circuits 21 through the connecting lines 40 .
  • connection lines 40 in the plurality of connection lines 40 are transparent connection lines 41 .
  • the transparent connection line 41 is located in the above-mentioned transparent conductive layer 4 .
  • the transparent connecting line 41 can be made of transparent materials such as indium tin oxide (ITO) or indium gallium zinc oxide (IGZO).
  • At least one row of transparent connecting lines 41 connected to the first driving electrodes 31 extends to the second area A2 via at least two routing areas 04 .
  • One end of a transparent connection line 41 is electrically connected to one first driving electrode 31 in a row of first driving electrodes 31 , and the other end is electrically connected to the corresponding first driving circuit 21 located in the second area A2 . Therefore, the electrical connection between the first driving circuit 21 and the first driving electrodes 31 can be realized by using the transparent connecting lines 41 , and the first driving circuit 21 can transmit driving signals to corresponding first driving electrodes 31 through the transparent connecting lines 41 .
  • the transparent connection lines 41 connected to at least one row of the first driving electrodes 31 extend to the second area A2 through at least two routing areas 04
  • the transparent connecting lines 41 extend to the second area A2 through two routing areas 04; it is also possible that the transparent connecting lines 41 connected to at least one row of the first driving electrodes 31 extend to the second area A2 through three or more routing areas 04.
  • Various embodiments of the present disclosure do not limit this. For example, as shown in FIG. 4A , at least one row of transparent connecting lines 41 connected to the first driving electrodes 31 extends to the second area A2 via the three wiring areas 04 .
  • At least one row of transparent connecting lines 41 connected to the first driving electrodes 31 are located in different layers.
  • At least one row of transparent connection lines 41 connected to the first driving electrodes 31 are located in different layers, which means: in the thickness direction of the array substrate 100 (such as the direction a- In a′), at least one row of transparent connecting lines 41 connected to the first driving electrodes 31 are located on different transparent conductive layers 4 .
  • the first driving electrode 31 is electrically connected to the first driving circuit 21 located in the second area A2 through the transparent connecting line 41, so that the first driving circuit 21 can communicate with the corresponding first driving electrode 31 through the transparent connecting line 41.
  • the transmission of the driving signal can also reduce the blocking of light, so that the light can also pass through any two adjacent first driving electrodes 31 from the side of the array substrate 100 located in the first area A1 (for example, the light-emitting side).
  • the gap between them is emitted from the other side (for example, the non-light-emitting side) of the part of the array substrate 100 located in the first area A1, so that the part of the array substrate 100 located in the first area A1 has a higher light transmittance; and, by
  • the transparent connection lines 41 connected to at least one row of the first drive electrodes 31 are arranged on different layers, which can increase the layout space of the transparent connection lines 41 electrically connected to the first drive electrodes 31 of one row, thereby achieving a limited number of layouts in the space
  • the bulky transparent connecting wire 41 makes the first driving electrode 31 and the first driving circuit 2 realize one-to-one connection through the transparent connecting wire 41 .
  • At least one row of the transparent connection lines 41 connected to the first driving electrodes 31 includes: a first type of transparent connection line 411 and a second type of transparent connection line 412 .
  • the first driving electrodes 31 in the 004th row include the first-type transparent connecting lines 411 and the second-type transparent connecting lines 412; the first driving electrodes 31 in the 007th row include the first-type transparent connecting lines line 411 and the second type of transparent connecting line 412; the first driving electrode 31 of the 008th row includes the first type of transparent connecting line 411 and the second type of transparent connecting line 412; the first driving electrode 31 of the 010th row includes the first type of transparent connecting line line 411 and the second type of transparent connecting line 412; the first driving electrode 31 in row 011 includes the first type of transparent connecting wire 411 and the second type of transparent connecting wire 412; the first driving electrode 31 in row 013 includes the first type of transparent connecting wire line 411 and the second type of transparent connection line 412. It should be noted that this is only an example, and those skilled in the art can understand that there may be other rows that also include the first-type transparent connection lines 411 and the second-type transparent connection lines 412; the first driving electrodes 31 in the 007
  • the first driving electrodes 31 electrically connected to the first-type transparent connecting lines 411 are closer to the first driving electrodes 31 of the row than the first driving electrodes 31 electrically connected to the second-type transparent connecting lines 412. center.
  • the number of the first type of transparent connection lines 411 is greater than the number of the second type of transparent connection lines 412, and the first type of transparent connection lines 411 and the second type of transparent connection lines 412 are located on different layers .
  • first type of transparent connection line 411 and the second type of transparent connection line 412 are located in different layers, which means: in the thickness direction of the array substrate 100 (such as the direction a-a shown in FIG. 2 '), the first-type transparent connection lines 411 and the second-type transparent connection lines 412 are located on different transparent conductive layers 4 .
  • the layout space of the transparent connecting wires 41 electrically connected to the row of first driving electrodes 31 can be increased, thereby Realize the layout of a large number of connecting lines 40 in a limited space, avoiding that when the number of first driving electrodes 31 in a row of first driving electrodes 31 is large, more connecting lines 40 cannot be laid out on the same layer, resulting in partial first driving The electrodes 31 cannot be electrically connected to the corresponding first driving circuit 21 through the connecting wire 40 .
  • At least one row of the first-type transparent connection lines 411 connected to the first driving electrodes 31 is located on the same side of the row of first driving electrodes 31 and is closest to the row of first driving electrodes.
  • the N1 line area 04 of the electrode 31 extends to the second area A2.
  • N1 is a positive integer greater than or equal to 2.
  • N1 3.
  • At least one row of the first-type transparent connecting lines 411 connected to the first driving electrodes 31 extends to the third-row line area 04 located on the same side of the row of first driving electrodes 31 and closest to the row of first driving electrodes 31 .
  • the first-type transparent connection lines 411 connected to at least one row of the first driving electrodes 31 are scattered in the N1 line area 04, which can increase the layout of the connection lines 40 electrically connected to the first driving electrodes 31 in one row. Space, so as to realize the layout of a large number of connecting wires 40 in a limited space, so that the first driving electrode 31 and the first driving circuit 21 can realize one-to-one connection through the first type of transparent connecting wire 411, and the first driving circuit 21 can pass through The first-type transparent connection lines 411 transmit driving signals to corresponding first driving electrodes 31 .
  • the adjacent N2 rows of first driving electrodes 31 are used as a cycle.
  • N2 is a positive integer greater than or equal to 2; in the same period, the first-type transparent connecting lines 411 connected to the first driving electrodes 31 in each row are located in different layers.
  • the first driving electrode 31 in the adjacent row 001, the first driving electrode 31 in the 002nd row, and the first driving electrode 31 in the 003th row are defined as a cycle 01.
  • the adjacent first driving electrodes 31 in the 004th row, the first driving electrodes 31 in the 005th row and the first driving electrodes 31 in the 006th row are another period 01.
  • the adjacent first driving electrodes 31 in the 007th row, the first driving electrodes 31 in the 008th row and the first driving electrodes 31 in the 009th row are another cycle 01.
  • the adjacent first driving electrodes 31 in the 010th row, the first driving electrodes 31 in the 011th row, and the first driving electrodes 31 in the 012th row are another cycle 01.
  • the adjacent first driving electrodes 31 in the 013th row, the first driving electrodes 31 in the 014th row and the first driving electrodes 31 in the 015th row are another cycle 01.
  • the first-type transparent connecting lines 411 connected to the first driving electrodes 31 in three rows in the same period are located in different layers.
  • the transparent connecting lines 41 connected to the first driving electrodes 31 in row 001 include: transparent connecting lines 411 of the first type; transparent connecting lines 41 connected to the first driving electrodes 31 in row 002 It includes: first-type transparent connection lines 411 ; the transparent connection lines 41 connected to the first driving electrodes 31 in row 003 include: first-type transparent connection lines 411 .
  • a type of transparent connection line 411 is located in different layers.
  • the first-type transparent connection line 411 connected to the first drive electrode 31 in the 004th row, the first-type transparent connection line 411 connected to the first drive electrode 31 in the 005th row, and the first-type transparent connection line 411 connected to the first drive electrode 31 in the 006th row are located in different layers.
  • the first-type transparent connection line 411 connected to the first drive electrode 31 in the 007th row, the first-type transparent connection line 411 connected to the first drive electrode 31 in the 008th row, and the first-type transparent connection line 411 connected to the first drive electrode 31 in the 009th row are located in different layers.
  • first-type transparent connection line 411 connected to the first drive electrode 31 in the 010th row, the first-type transparent connection line 411 connected to the first drive electrode 31 in the 011th row, and the first-type transparent connection line 411 connected to the first drive electrode 31 in the 012th row are located in different layers.
  • first-type transparent connection line 411 connected to the first drive electrode 31 in the 013th row, the first-type transparent connection line 411 connected to the first drive electrode 31 in the 014th row and the first drive electrode 31 in the 015th row are located in different layers.
  • first-type transparent connection lines 411 connected to the first driving electrodes 31 in three rows in the same period are located in different layers, which means: in the thickness direction of the array substrate 100 (for example, in FIG. 2 In the direction a-a') shown, the first-type transparent connection lines 411 connected to the first drive electrodes 31 in three rows in the same period are respectively located on different transparent conductive layers 4 .
  • the first-type transparent connection lines 411 connected to the first drive electrodes 31 of each row can be increased.
  • the wiring space of the connecting lines 411 so as to realize the layout of a large number of transparent wirings in a limited space, and avoid the short circuit between the first-type transparent connecting lines 411 when a large number of first-type transparent connecting lines 411 are arranged on the same layer , reducing the structural design and process difficulty.
  • the second-type transparent connection lines 412 connected to at least one row of the first driving electrodes 31, and any row of the first driving electrodes 31 in the same period 01 as the row of the first driving electrodes 31 The first-type transparent connecting lines 411 connected to one driving electrode 31 are arranged on the same layer, and are located via the first-type transparent connecting lines 411 connected to the first driving electrodes 31 in the same period as the first driving electrodes 31 in the row.
  • the wiring area 04 extends to the second area A2.
  • the first driving electrodes 31 in row 004 include first-type transparent connection lines 411 and second-type transparent connection lines 412 .
  • the second type of transparent connecting lines 412 connected to the first driving electrodes 31 in row 004 may include a first part of transparent connecting lines 4121 and a second part of transparent connecting lines 4122 .
  • the first part of the transparent connecting line 4121 connected to the first driving electrode 31 in the 004th row can be arranged on the same layer as the first type of transparent connecting line 411 connected to the first driving electrode 31 in the 005th row, and the first driving electrode 4121 in the 005th row
  • the wiring area 04 where the first-type transparent connection line 411 connected to the electrode 31 is located extends to the second area A2.
  • the first driving electrodes 31 in row 007 include first-type transparent connection lines 411 and second-type transparent connection lines 412 .
  • the second type of transparent connecting lines 412 connected to the first driving electrodes 31 in row 007 may include a first part of transparent connecting lines 4121 and a second part of transparent connecting lines 4122 .
  • the first part of the transparent connecting line 4121 connected to the first driving electrode 31 in the 007th row can be set on the same layer as the first type of transparent connecting line 411 connected to the first driving electrode 31 in the 008th row, and the first driving electrode 4121 in the 008th row
  • the wiring area 04 where the first-type transparent connection line 411 connected to the electrode 31 is located extends to the second area A2.
  • the first driving electrodes 31 in row 008 include first-type transparent connection lines 411 and second-type transparent connection lines 412 . At least part of the second-type transparent connecting lines 412 connected to the first driving electrodes 31 in the 008th row can be arranged on the same layer as the first-type transparent connecting lines 411 connected to the first driving electrodes 31 in the 009th row, and through the 009th row
  • the wiring area 04 where the first-type transparent connection line 411 connected to the first driving electrode 31 is located extends to the second area A2.
  • the first driving electrodes 31 in row 010 include first-type transparent connection lines 411 and second-type transparent connection lines 412 . At least part of the second-type transparent connection lines 412 connected to the first drive electrodes 31 in the 010th row can be arranged on the same layer as the first-type transparent connection lines 411 connected to the first drive electrodes 31 in the 012th row, and through the 012th row
  • the wiring area 04 where the first-type transparent connection line 411 connected to the first driving electrode 31 is located extends to the second area A2.
  • the first driving electrodes 31 in row 011 include first-type transparent connection lines 411 and second-type transparent connection lines 412 . At least part of the second-type transparent connecting lines 412 connected to the first driving electrodes 31 in the 011th row can be arranged on the same layer as the first-type transparent connecting lines 411 connected to the first driving electrodes 31 in the 012th row, and through the 012th row
  • the wiring area 04 where the first-type transparent connection line 411 connected to the first driving electrode 31 is located extends to the second area A2.
  • the first driving electrodes 31 in row 013 include first-type transparent connection lines 411 and second-type transparent connection lines 412 . At least part of the second-type transparent connecting lines 412 connected to the first driving electrodes 31 in the 013th row can be arranged on the same layer as the first-type transparent connecting lines 411 connected to the first driving electrodes 31 in the 015th row, and through the 015th row
  • the wiring area 04 where the first-type transparent connection line 411 connected to the first driving electrode 31 is located extends to the second area A2.
  • “same layer” refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to form a patterning process.
  • a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure can be continuous or discontinuous, and these specific patterns may also be at different heights Or have different thicknesses.
  • the second-type transparent connection lines 412 connected to at least one row of the first driving electrodes 31 and any row of the first driving electrodes 31 in the same period 01 as the row of first driving electrodes 31
  • the first type of transparent connection lines 411 connected to the driving electrodes 31 are arranged on the same layer, which not only simplifies the manufacturing process, but also makes up for the number of first driving electrodes 31 in one row in the same period.
  • the layout space of the first-type transparent connection lines 411 in a row with a large number increases the layout space of the first-type transparent connection lines 411 electrically connected to a row with a large number of first driving electrodes 31 in the same period, In this way, a large number of first-type transparent connecting lines 411 can be arranged in a limited space.
  • At least part of the second-type transparent connecting line 412 connected to at least one row of the first driving electrodes 31 is connected to any row of the first driving electrodes 31 in a different period from the row of first driving electrodes 31.
  • the connected first-type transparent connection lines 411 are arranged on the same layer, and pass through the wiring area where the first-type transparent connection lines 411 connected to the first drive electrodes 31 in a different period from the row of first drive electrodes 31 are located. 04 extends to the second area A2.
  • the first driving electrodes 31 in row 004 include first-type transparent connection lines 411 and second-type transparent connection lines 412 .
  • the second type of transparent connecting lines 412 connected to the first driving electrodes 31 in row 004 may include a first part of transparent connecting lines 4121 and a second part of transparent connecting lines 4122 .
  • the second part of the transparent connection line 4122 connected to the first drive electrode 31 in the 004th row can be set on the same layer as the first type transparent connection line 411 connected to the first drive electrode 31 in the 003rd row, and through the first The routing area 04 where the first-type transparent connection line 411 connected to the driving electrode 31 is located extends to the second area A2.
  • the first driving electrodes 31 in row 007 include first-type transparent connection lines 411 and second-type transparent connection lines 412 .
  • the second type of transparent connecting lines 412 connected to the first driving electrodes 31 in row 007 may include a first part of transparent connecting lines 4121 and a second part of transparent connecting lines 4122 .
  • the second part of the transparent connecting line 4122 connected to the first driving electrode 31 in the 007th row can be set on the same layer as the first type of transparent connecting line 411 connected to the first driving electrode 31 in the 006th row, and through the first The routing area 04 where the first-type transparent connection line 411 connected to the driving electrode 31 is located extends to the second area A2.
  • the first driving electrodes 31 in row 010 include first-type transparent connection lines 411 and second-type transparent connection lines 412 . At least part of the second-type transparent connecting lines 412 connected to the first driving electrodes 31 in the 010th row can be arranged on the same layer as the first-type transparent connecting lines 411 connected to the first driving electrodes 31 in the 009th row, and through the 009th row
  • the wiring area 04 where the first-type transparent connection line 411 connected to the first driving electrode 31 is located extends to the second area A2.
  • the first driving electrodes 31 in row 013 include first-type transparent connection lines 411 and second-type transparent connection lines 412 . At least part of the second-type transparent connecting lines 412 connected to the first driving electrodes 31 in the 013th row can be arranged on the same layer as the first-type transparent connecting lines 411 connected to the first driving electrodes 31 in the 012th row, and through the 012th row
  • the wiring area 04 where the first-type transparent connection line 411 connected to the first driving electrode 31 is located extends to the second area A2.
  • the second-type transparent connection lines 412 connected to at least one row of the first driving electrodes 31 and any row in a different period from the first driving electrodes 31 of the row are connected to each other.
  • the first-type transparent connection lines 411 connected to the first driving electrodes 31 are arranged in the same layer, which not only simplifies the manufacturing process, but also makes up for the first driving electrodes 31 in a cycle with a small number of first driving electrodes 31 in other cycles.
  • the layout space of the first-type transparent connection lines 411 in a row with a large number of electrodes 31 increases the layout space of the first-type transparent connection lines 411 electrically connected with a row with a large number of first driving electrodes 31, thereby A large number of first-type transparent connecting lines 411 can be arranged in a limited space.
  • the first area A1 includes at least two sub-areas A01 sequentially arranged along a set direction.
  • the set direction is from the center b of a row of the first driving electrodes 31 to one end b' of the row of first driving electrodes 31 (such as the direction b-b' shown in FIG. 4B ).
  • the transparent connection lines 41 connected to the first driving electrodes 31 located in different sub-regions A01 are respectively located in different layers.
  • the transparent connection lines 41 connected to the first driving electrodes 31 located in different sub-regions A01 are respectively located in different layers, which means: in the thickness direction of the array substrate 100 (for example, as shown in FIG. In the direction a-a′) shown in FIG.
  • the first area A1 in a direction b-b' from the center b of a row of first driving electrodes 31 to one end b' of the row of first driving electrodes 31, the first area A1 includes two sub-areas A01.
  • the transparent connection lines 41 connected to the first driving electrodes 31 located in the two sub-regions A01 are respectively located in different layers.
  • the transparent connecting lines 41 connected to the first driving electrodes 31 located in the two sub-areas A01 extend from the routing area 04 to the second area A2.
  • the at least two The sub-areas include a first sub-area A011, a second sub-area A012 and a third sub-area A013.
  • the transparent connection lines 41 connected to the first driving electrodes 31 located in the three sub-regions A01 are respectively located in different layers.
  • the transparent connection line 41 connected to the first driving electrodes 31 in the first sub-region A011 is located at The first transparent conductive layer 041 ; the transparent connection line 41 connected to the first driving electrode 31 in the second sub-region A012 is located in the second transparent conductive layer 042 .
  • the transparent connection lines 41 connected to the first driving electrodes 31 in the third sub-region A013 are located on the third transparent conductive layer 043 .
  • the transparent connection lines 41 connected to the first driving electrodes 31 located in the three sub-areas A01 all extend from the wiring area 04 to the second area A2.
  • the transparent connecting line 41 may cross the first driving circuit 21 and/or The second driving circuit 22 forms a parasitic capacitance with it.
  • the existence of the parasitic capacitance easily affects the accuracy of the driving signal received by the first driving electrode 31 .
  • the transparent connection line located in the middle area of the first area A1 adopts the wiring method of vertical wiring to realize the electrical connection between the first driving electrode 31 and the first driving circuit 21;
  • the regions on both sides of the middle region inside adopt the wiring method of horizontal wiring, so as to realize the electrical connection between the first driving electrode 31 and the first driving circuit 21 .
  • the length of the transparent connection line will be increased by adopting the vertical wiring method, and the transparent connection line in the middle area of the first area A1 and the transparent connection lines in the two side areas are not evenly filtered, and the transparent connection line is formed in the transparent connection line.
  • the variation of the parasitic capacitance of the first region A1 is not uniform, which will cause a "dark-bright-dark” or "bright-dark-bright” brightness difference between the middle region and the two side regions of the first region A1, which will affect the display effect.
  • the first area A1 includes at least two sub-areas A01 sequentially arranged along a set direction, and the transparent connection lines 41 connected to the first driving electrodes 31 located in different sub-areas A01 are respectively located in different layers, so that The layout space of the connecting wires 40 electrically connected to a row of first driving electrodes 31 is increased, so that a large number of transparent connecting wires 41 can be laid out in a limited space, and thus the transparent connecting wires 41 can all be extended from the routing area 04 To the second area A2, the regular arrangement of the transparent connecting lines 41 can improve the first driving circuit 21 and/or the second driving circuit 21 and/or the second driving circuit 41 connected by the transparent connecting lines 41 connected to any two adjacent first driving electrodes 31.
  • the law of the quantity difference of the circuit 22 is convenient to improve the change uniformity of the parasitic capacitance formed in the transparent connecting line 41 connected by two adjacent first driving electrodes 31, and improve the driving signal received by the first driving electrodes 31.
  • the routing environment of the transparent connecting lines 41 is uniform, which can improve the brightness difference of the display panel 1000 and improve the display effect of the display panel 1000.
  • the number of the first driving electrodes 31 located in different sub-regions A01 is equal.
  • the first area A1 is rectangular, and in each row of the first driving electrodes 31 in the first area A1, the number of the first driving electrodes 31 located in different sub-areas A01 equal.
  • the number of the first driving electrodes 31 located in different sub-regions A01 is equal, that is, some or all rows of the first driving electrodes 31 are equal in number.
  • the number of transparent connection lines 41 extending from different sub-regions A01 in the electrodes 31 is equal; moreover, the transparent connection lines 41 connected to the first drive electrodes 31 in different sub-regions A01 are respectively located in different layers, which increases the number of connections with
  • the layout space of the connecting wires 40 electrically connected to the first driving electrodes 31 in this row can realize the layout of a large number of transparent connecting wires 41 in a limited space, moreover, the planning of the direction of the transparent connecting wires 41 is more regular, and the array substrate 100 is simplified.
  • the structure reduces the difficulty of preparing and forming the array substrate 100 .
  • the transparent connection lines 41 connected to the first driving electrodes 31 in one row extend to the second area A02 via one or two wiring regions 04 adjacent to the first driving electrodes 31 in the row.
  • a row of transparent connection lines 41 connected to the first driving electrodes 31 extends to the second region A02 via a row of wiring regions 04 adjacent to the row of first driving electrodes 31 .
  • At least one row of transparent connection lines 41 connected to the first driving electrodes 31 extends to the second row via two wiring regions 04 adjacent to the row of first driving electrodes 31 .
  • the first area A1 may include a plurality of green sub-pixel regions, a plurality of blue sub-pixel regions and a plurality of red sub-pixel regions.
  • the plurality of first driving electrodes 31 includes a plurality of first driving electrodes 31 corresponding to the red sub-pixel area, a plurality of first driving electrodes 31 corresponding to the blue sub-pixel area, and a plurality of first driving electrodes 31 corresponding to the green sub-pixel area. Drive electrodes 31 .
  • the transparent connection line 41 connected to the first driving electrode 31 corresponding to the green sub-pixel area extends to the second area A02 via one of the line areas adjacent to the first driving electrode 31 of the row.
  • the first drive electrode 31 corresponding to the red sub-pixel area and the first drive electrode 31 corresponding to the blue sub-pixel area are connected to the transparent connecting line 41, through another line area adjacent to the first drive electrode 31 of the row extending to the second area A02.
  • the green sub-pixel when it needs to be lighted, the green sub-pixel needs to be charged longer than the red sub-pixel and the blue sub-pixel. different.
  • the transparent connection lines 41 connected to the first driving electrodes 31 of a row extend to the second area A02 via one or two line regions 04 adjacent to the first driving electrodes 31 of the row, which can increase the The layout space of the transparent connecting wires 41 electrically connected to a row of first driving electrodes 31, so as to realize the layout of a large number of transparent connecting wires 41 in a limited space, so that the first driving electrodes 31 and the first driving circuit 2 pass through the transparent connecting wires 41 Realize one-to-one connection.
  • the green sub- The first drive electrode 31 corresponding to the pixel area is connected to the transparent connection line 41, and the first drive electrode 31 corresponding to the red sub-pixel area and the first drive electrode 31 corresponding to the blue sub-pixel area are connected to the transparent connection line 41 via
  • the different wiring areas extend to the second area A02, which is more convenient to control the wiring arrangement of the green sub-pixel area, red sub-pixel area and blue sub-pixel area, and is convenient to improve the green sub-pixel when the sub-pixel needs to be lit. The problem with the charging time required for the red sub-pixel and the blue sub-pixel is different.
  • the edge area A02 is located between at least two sub-areas A01 and the second area A2 in the set direction.
  • the connecting wires 40 are metal connecting wires 42 .
  • the metal connection line 42 may be located in the first source-drain electrode layer 201 or the second source-drain electrode layer 202 .
  • connection line connected to the first driving electrode 31 corresponding to the green sub-pixel area is the metal connection line 42 .
  • the connecting line connecting the first driving electrode 31 corresponding to the red sub-pixel area and the first driving electrode 31 corresponding to the blue sub-pixel area may be a metal connecting line 42, or It may be a transparent connection line 41 , which is not limited in the embodiments of the present disclosure.
  • connection line connecting the green sub-pixel is relatively shorter than the red sub-pixel and the blue sub-pixel.
  • the first driving circuit corresponding to the green sub-pixel is closer to the first area A1 than the first driving circuits corresponding to the red sub-pixel and the blue sub-pixel.
  • connection line connected to the green sub-pixel a metal connection line 42
  • the metal connection line 42 is relatively short, which reduces the parasitic capacitance in the connection line connected to the green sub-pixel.
  • the charging time of the sub-pixel is longer, the charging capacity is more sufficient, and it is easier to be lit, thereby improving the display effect of the display panel.
  • the connecting wires 40 are metal connecting wires 42 .
  • the metal connection line 42 may be located in the first source-drain electrode layer 201 or the second source-drain electrode layer 202 .
  • the connecting wires 40 connected to at least one row of the first driving electrodes 31 include metal connecting wires 42 .
  • the first driving electrodes 31 electrically connected to the metal connection lines 42 are farther away from the first driving electrodes 31 in the row than the first driving electrodes 31 electrically connected to the transparent connecting lines 41. The center of the electrode 41.
  • connection lines 40 connected to the first driving electrodes 31 in row 001 include metal connection lines 42 .
  • the first driving electrodes 31 electrically connected to the metal connecting lines 42 are farther away from the first driving electrodes 31 in the row than the first driving electrodes 31 electrically connected to the transparent connecting lines 41. 41 Center.
  • connection lines 40 connected to at least one row of the first driving electrodes 31 include metal connection lines 42, the metal connection lines 42 and the transparent connection lines 41 are located in different film layers, which makes up for the first row of the row.
  • the layout space of the connecting wires 40 electrically connected to the driving electrodes 31 increases the layout space of the connecting wires 40 electrically connected to the first driving electrodes 31 of the row, thereby realizing a large number of connecting wires 40 in a limited space;
  • the first driving electrodes 31 electrically connected to the metal connecting lines 42 are farther away from the center of the first driving electrodes 41 in the row than the first driving electrodes 31 electrically connected to the transparent connecting lines 41, which can ensure that the center of the first area A1 A portion of the region has a higher light transmittance.
  • the number of the first driving electrodes 31 electrically connected to the metal connection line 42 does not exceed the first threshold.
  • the value range of the first threshold is 2-5.
  • the number of the first driving electrodes 31 electrically connected to the metal connection lines 42 may be 2, 3, 4, 5.
  • the number of the first driving electrodes 31 electrically connected to the metal connection lines 42 is two.
  • the number of the first driving electrodes 31 electrically connected to the metal connection line 42 does not exceed 2 to 5, which can make up for the connection between the first driving electrodes 31 in the row.
  • the layout space of the line 40 increases the layout space of the connecting line 40 electrically connected to the first driving electrode 31 of the row, and the number of the metal connecting lines 42 is small, so as to avoid a short circuit between the metal connecting lines 42 of the same layer. Reduced structural design and process difficulty.
  • the length of the metal connection line 42 is shorter than the length of the transparent connection line 41 .
  • the length of the metal connection line 42 is short, and the parasitic capacitance between the metal connection line 42 and the entire film layer of the array substrate 100 is small, which can prevent the parasitic capacitance jump between the metal connection line 42 and the transparent connection line 41.
  • This phenomenon improves the flicker phenomenon of the display screen caused by the jump, makes the display uniformity of the first area A1 and the second area A2, and improves the quality of the image displayed on the array substrate 100 .
  • the metal connection lines 42 connected to the first driving electrodes 31 that are farther away from the center of a row of the first driving electrodes 31 are shorter.
  • the shorter the metal connection line 42 connected to the first driving electrodes 31 that is farther away from the center of a row of first driving electrodes 31 means: the farther away from the first driving electrodes of the center of a row of first driving electrodes 31
  • the shorter the length of the metal connection wire 42 connected by the 31 is.
  • the length of the metal connection line 42 refers to, for example, the size of the metal connection line 42 in the first direction X. As shown in FIG.
  • the farther away from the center of a row of the first driving electrodes 31 the transparent connection line 41 connected to the first driving electrodes 31 is shorter.
  • the shorter the transparent connecting line 41 connected to the first driving electrodes 31 that is farther away from the center of a row of first driving electrodes 31 means: the farther away from the first driving electrodes of the center of a row of first driving electrodes 31
  • the length of the transparent connection line 41 connected by 31 is shorter.
  • the length of the transparent connection line 41 refers to, for example, the size of the transparent connection line 41 in the first direction X.
  • the regularity of the number difference of the first drive circuits 21 crossed by any two adjacent connecting lines 41 in the connecting lines 41 can be improved, thereby facilitating the improvement of the number difference between any two adjacent connecting lines 41.
  • Variation uniformity of the parasitic capacitance formed in the connection line 40 can be improved.
  • a row of the first driving circuits 21 and a row of the first driving electrodes 31 are electrically connected in a manner of being close to each other and far away from each other.
  • a row of the first driving electrodes 31 includes the first to Nth first driving electrodes 31 .
  • a row of the first driving circuits 21 includes the first to Nth first driving circuits 21 .
  • the first first driving electrode 31 is closest to the second area A2
  • the Nth first driving electrode 31 is closest to the second area A2. away from the second area A2.
  • the first first driving circuit 21 is closest to the first area A1, and the Nth first driving circuit 21 is farthest from the second area A2.
  • the i-th first driving electrode 31 is electrically connected to the i-th first driving circuit 21 .
  • i 1 ⁇ N. That is, the first first drive electrode 31 can be electrically connected to the first first drive circuit 21 through the connection line 40, and the second first drive electrode 31 can be connected to the second first drive circuit 21 through the connection line 40. Electrical connection...
  • the N-1th first driving electrode 31 can be electrically connected to the N-1th first driving circuit 21 through the connecting wire 40, and the N-th first driving electrode 31 can be connected to the N-th first driving electrode 31 through the connecting wire 40.
  • the first drive circuit 21 is electrically connected.
  • the present disclosure adopts the above-mentioned setting method and connection method, which not only facilitates the planning of the path of the connecting line 40, improves the regularity of the length difference between any two adjacent connecting lines 40, but also reduces the number of connecting lines 40 that need to be used. quantity, simplify the structure of the array substrate 100, and reduce the difficulty of preparing and forming the array substrate 100.
  • the second area A2 includes a first sub-area A21 and a second sub-area A22. Among them, the first sub-area A21 is adjacent to the first area A1.
  • the area of the second driving electrode 32 located in the first sub-region A21 is smaller than the area of the second driving electrode 32 located in the second sub-region A22, and the area of the first driving electrode 31 is smaller than that located in the second sub-region A22.
  • the area of the second driving electrode 32 in the second sub-region A22 is smaller than the area of the second driving electrode 32 located in the second sub-region A22.
  • the light transmittance of the first sub-region A21 and the first region A1 is greater than that of the second region A2.
  • the first driving electrodes 31 and the second driving electrodes 32 located in the first sub-region A21 are divided into multiple repeating units, and one repeating unit includes 2k rows and 4h column driving electrodes; wherein, k, h is a positive integer greater than or equal to 1.
  • a repeating unit may include driving electrodes with 2 rows and 4 columns, driving electrodes with 4 rows and 4 columns, or driving electrodes with 2 rows and 8 columns.
  • the first sub-area A21 and the first area A1 are displayed using the same display algorithm
  • the second sub-area A22 is displayed using a different display algorithm from the first sub-area A21 and the first area A1, ensuring that the displayed After the algorithm processing, the second sub-region A22, the first sub-region A21 and the first region A1 can display accurate colors, avoiding the color shift problem caused when the two regions are displayed using the same display algorithm, and weakening the first sub-region
  • the jagged phenomenon of the entire edge of A21 and the first region A1 during display is convenient to improve the display uniformity of the array substrate 100 and improve the quality of the image displayed on the array substrate 100 .
  • both the first region A1 and the second region A2 have a plurality of sub-pixel regions P.
  • the size of the metal connection line 42 in the row direction is larger than the size of one sub-pixel region P in the row direction.
  • the size of the metal connection line 42 in the row direction refers to: the size of the metal connection line 42 in the extending direction of a row of first driving electrodes 31 (such as the first direction X shown in FIG. 8 ).
  • the size of a sub-pixel region P in the row direction refers to the size of a sub-pixel region P in the extending direction of a row of first driving electrodes 31 (eg, the first direction X shown in FIG. 8 ).
  • the first sub-region A21 includes two sub-pixel regions P.
  • the size a of the metal connection line 42 connected to the first driving electrode 31 located at the edge of the first area A1 and close to the second area A2 in the row direction is larger than the size b of a sub-pixel area P in the row direction.
  • the first sub-area A21 including at least one sub-pixel area P is set, so that the first sub-area A21 and the first area A1 can be displayed using the same display algorithm as a whole.
  • the second sub-area A22 When a display algorithm different from that of the first sub-region A21 and the first region A1 is used for display, after being processed by the display algorithm, the second sub-region A22, the first sub-region A21 and the first region A1 can all display colors accurately, improving the The color shift problem weakens the jagged phenomenon of the entire edge of the first sub-region A21 and the first region A1 during display, so as to improve the display uniformity of the array substrate 100 and improve the image quality displayed on the array substrate 100 .
  • the first area A1 includes the optical component area A11, and the minimum distance c between the metal connection line 42 and the optical component area A11 is greater than the size b of a sub-pixel area P in the row direction .
  • the center of the optical component area A11 may coincide with the center of the first area A1.
  • the minimum distance c between the metal connection line 42 and the optical component area A11 is greater than the size b of a sub-pixel area P in the row direction, so that the metal connection line 42 can be prevented from affecting the light transmittance of the optical component area A11. It is ensured that external light can pass through the optical component area A11 and enter the optical component, be collected by the optical component, and enable the optical component to work normally.
  • the length of the metal connection line 42 located in the first area A1 is shorter than the length of the metal connection line 42 located in the second area A2 .
  • the metal connection line 42 connected to the first driving electrode 31 is located at the first The length a1 of the portion of the area A1 is smaller than the length a2 of the portion of the metal connection line 42 located in the second area A2.
  • the metal connection line 42 can make up for a line of first driving
  • the metal connection line 40 electrically connected to the electrode 31
  • FIG. 10 is a partial schematic diagram of the first area A1 and the first sub-area A21.
  • the entire boundary of the first area A1 and the first sub-area A21 includes a straight line segment 51 and a stepped line segment 52 , and two adjacent straight line segments 51 are connected by one stepped line segment 52 .
  • the stepped line segment 52 includes a plurality of sub-line segments connected in sequence, and one sub-line segment straddles 2k row driving electrodes or 4h column driving electrodes.
  • the entire boundary of the first area A1 and the first sub-area A21 includes two straight line segments 51 and two stepped line segments 52, and the stepped line segments 52 include the first type of sub-line segment 521 and the second type of sub-line segment.
  • the second type of sub-line segment 522 is exemplary, as shown in FIG. 10 .
  • the first type of sub-line segment 521 is parallel to the first direction X; the first type of sub-line segment 521 straddles 4h columns of driving electrodes.
  • the second type of sub-line segment 522 is parallel to the second direction Y; the second type of sub-line segment 522 spans 2k rows of driving electrodes.
  • the driving electrodes at the boundary of the first region A1 and the first subregion A21 can be displayed using the same display algorithm, avoiding the first driving electrode 31 at the boundary of the first region A1 and the first driving electrode 31 at the first subregion A21.
  • the second drive electrode 32 uses different display algorithms to display the color shift problem, which eliminates the jagged phenomenon when displaying the edges of the first sub-region A21 and the first region A1, which facilitates the improvement of the display uniformity of the array substrate 100, and improves the The quality of the image displayed on the array substrate 100 .
  • the main body shape of at least one second driving electrode 32 located in the first sub-region A21 is the same as the main body shape of at least one first driving electrode 31 .
  • the main body shape of the first driving electrode is oval or circular; the main body shape of at least one second driving electrode 32 located in the first sub-region A21 is oval or circular.
  • the main body shape of at least one second driving electrode 32 located in the first sub-region A21 is the same as the main body shape of at least one first driving electrode 31, and both are oval or circular, which can make the first
  • the overall boundary between the area A1 and the first sub-area A21 is smoother and softer.
  • the boundary between the first sub-area A21 and the first area A1 can be weakened.
  • the jaggy phenomenon is convenient to improve the display uniformity of the display panel 1000 and improve the quality of the image displayed on the display panel 1000 .
  • the area of at least one second driving electrode 32 located in the first sub-region A21 is equal to the area of at least one first driving electrode 31 .
  • the area of at least one second driving electrode 32 located in the first subregion A21 is equal to the area of at least one first driving electrode 31, both of which are smaller than the area of the second driving electrode 32 in the second subregion A22, not only
  • the manufacturing process can be simplified, and the diffraction of the first region A1 is further reduced, and the light transmittance of the first region A1 is improved.
  • the display panel 1000 includes: the array substrate 100 according to any one of the above-mentioned embodiments, the light emitting function layer 110 , the common electrode layer 120 and the encapsulation layer 130 .
  • the light emitting functional layer 110 is located on one side of the array substrate 100 .
  • the light emitting functional layer 110 may include a light emitting layer (electroluminescent, EL for short).
  • the luminescent functional layer 110 includes, in addition to the luminescent layer, an electron transport layer (election transporting layer, ETL for short), an electron injection layer (election injection layer, EIL for short), a hole transport layer (hole transporting layer). , HTL for short) and one or more layers in the hole injection layer (HIL for short).
  • the display panel 1000 is an organic electroluminescent display substrate
  • the light emitting layer is an organic light emitting layer.
  • the light emitting layer is a quantum dot light emitting layer.
  • the common electrode layer 120 is located on a side of the light emitting functional layer 110 away from the array substrate 100 .
  • the first driving electrode 31 and the second driving electrode 32 may be reflective anodes, and the common electrode layer 120 may include a plurality of transmissive cathodes.
  • the transmissive cathode can be selected from alloys such as Mg/Ag or metal/inorganic composite materials.
  • the encapsulation layer 130 is located on a side of the common electrode layer 120 away from the array substrate 100 .
  • the encapsulation layer 130 may be an encapsulation film (Thin Film Encapsulation, TFE for short), or an encapsulation substrate.
  • TFE Thin Film Encapsulation
  • the display device 2000 includes: the display panel 1000 as described in some embodiments above and the optical element 200 disposed on the non-light-emitting side of the display panel 100 . Wherein, the orthographic projection of the optical element 200 on the display panel 100 is located in the first area A1.
  • the aforementioned optical element 200 may include a photosensitive device.
  • the photosensitive device may include an image collector (such as a camera) or an infrared receiver.
  • the boundary of the camera may coincide with the boundary of the first area A1, or be located inside the boundary of the first area A1.
  • the center of the lens of the camera may coincide with the overall center of the first area A1 and the first sub-area A21 (such as the overall center O of the first area A1 and the first sub-area A21 shown in FIGS. 9 and 10 ), by This can further improve the imaging effect of the image captured by the camera through the first area A1, so as to ensure high-quality video or photography of the camera.
  • the number of optical elements 200 can be set according to actual needs.
  • the display device 2000 may further include a frame, a source driver chip, FPC (Flexible Printed Circuit, flexible circuit board), PCB (Printed Circuit Board, printed circuit board) or other electronic accessories.
  • FPC Flexible Printed Circuit, flexible circuit board
  • PCB Printed Circuit Board, printed circuit board
  • the beneficial effects achieved by the display device 2000 provided in the present disclosure are the same as the beneficial effects achieved by the display panel 1000 provided by the above technical solution, and will not be repeated here.
  • the display device 2000 described above may be any device that displays whether it is moving (for example, video) or fixed (for example, still image) and regardless of text or images. More specifically, it is contemplated that the described embodiments may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile phones, wireless devices, Personal Digital Assistants (Personal Digital Assistants) Assistant (PDA), handheld or portable computer, Global Positioning System (GPS) receiver/navigator, camera, Moving Picture Experts Group 4 (MP4) video player, video camera , game consoles, watches, clocks, calculators, television monitors, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and/or displays, camera view displays (e.g., vehicle Displays for mid-rear view cameras), electronic photos, electronic billboards or signage, projectors, architectural structures, packaging and aesthetic structures (for example, a display for an image of a piece of jewelry), etc.
  • PDA Personal Digital Assistants
  • GPS Global Positioning

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板，具有第一区域和第二区域。所述第二区域包围至少部分所述第一区域。阵列基板包括：多行第一驱动电极和多条连接线。多行第一驱动电极位于所述第一区域；一条连接线与一行第一驱动电极中的一个第一驱动电极电连接。至少一行所述第一驱动电极所连接的连接线经由至少一行走线区延伸至所述第二区域，一行走线区与一行第一驱动电极相邻；至少一行所述第一驱动电极所连接的连接线位于不同层。

Description

阵列基板、显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板、显示面板及显示装置。
背景技术
随着科学技术的不断发展，用户对显示装置的屏占比(显示屏的面积与显示装置的前面板的面积的比例)有着越来越高的追求。
相关技术领域中，出现了全面屏的概念，也即，将显示装置中的图像采集器等光学元件设置在显示屏的下方，以增大显示屏的面积与显示装置的前面板的面积之间的比例，并使得该比例趋近于100％。
发明内容
一方面，提供一种阵列基板。所述阵列基板具有第一区域和第二区域，所述第二区域包围至少部分所述第一区域。所述阵列基板包括：多行第一驱动电极、多条连接线。多行第一驱动电极位于所述第一区域；一条连接线与一行第一驱动电极中的一个第一驱动电极电连接；至少一行所述第一驱动电极所连接的连接线经由至少一行走线区延伸至所述第二区域，一行走线区与一行第一驱动电极相邻；至少一行所述第一驱动电极所连接的连接线位于不同层。
在一些实施例中，所述多条连接线中的至少部分连接线为透明连接线；至少一行所述第一驱动电极所连接的透明连接线经由至少两行所述走线区延伸至所述第二区域；并且，至少一行所述第一驱动电极所连接的透明连接线位于不同层。
在一些实施例中，至少一行所述第一驱动电极所连接的透明连接线包括：第一类透明连接线和第二类透明连接线；该行所述第一驱动电极中，与所述第一类透明连接线电连接的所述第一驱动电极，相对于与所述第二类透明连接线电连接的所述第一驱动电极，更靠近该行所述第一驱动电极的中心；其中，所述第一类透明连接线的数量大于所述第二类透明连接线的数量，且所述第一类透明连接线与第二类透明连接线位于不同层。
在一些实施例中，至少一行所述第一驱动电极所连接的所述第一类透明连接线，经由位于该行所述第一驱动电极同一侧且最靠近该行所述第一驱动电极的N1行所述走线区延伸至所述第二区域，N1为大于或等于2的正整数。
在一些实施例中，以相邻的N2行所述第一驱动电极为一个周期；N2为 大于或等于2的正整数；在同一周期内，各行所述第一驱动电极所连接的所述第一类透明连接线位于不同层。
在一些实施例中，至少一行所述第一驱动电极所连接的至少部分所述第二类透明连接线，和与该行所述第一驱动电极处于同一周期内的任意一行所述第一驱动电极所连接的所述第一类透明连接线同层设置，且经由与该行第一驱动电极处于同周期内的该行第一驱动电极所连接的所述第一类透明连接线所在的所述走线区延伸至所述第二区域。
在一些实施例中，至少一行所述第一驱动电极所连接的至少部分所述第二类透明连接线，和与该行所述第一驱动电极处于不同周期内的任意一行所述第一驱动电极所连接的所述第一类透明连接线同层设置，且经由与该行第一驱动电极处于不同周期内的该行第一驱动电极所连接的所述第一类透明连接线所在的所述走线区延伸至所述第二区域。
在一些实施例中，所述多条连接线中的至少部分连接线为透明连接线；所述第一区域包括沿设定方向依次排布的至少两个子区域，所述设定方向由一行所述第一驱动电极的中心指向该行所述第一驱动电极的一端；位于不同的子区域内的所述第一驱动电极所连接的所述透明连接线分别位于不同层。
在一些实施例中，所述至少两个子区域包括沿所述设定方向依次排布的第一个子区域、第二个子区域、第三个子区域。
在一些实施例中，至少一行所述第一驱动电极中，位于不同子区域中的所述第一驱动电极的数量相等。
在一些实施例中，至少一行所述第一驱动电极所连接的透明连接线，经由与该行第一驱动电极相邻的至少一行所述走线区延伸至所述第二区域。
在一些实施例中，所述第一区域还包括边缘区域，所述边缘区域在所述设定方向上位于所述至少两个子区域与所述第二区域之间；所述多条连接线中的至少部分连接线为金属连接线；在所述边缘区域内，至少与绿色子像素区域对应的第一驱动电极所连接的所述连接线为金属连接线。
在一些实施例中，所述多条连接线中的至少部分连接线为金属连接线；至少一行所述第一驱动电极中所连接的所述连接线还包括所述金属连接线；该行所述第一驱动电极中，与所述金属连接线电连接的所述第一驱动电极，相对于与所述透明连接线电连接的所述第一驱动电极，更远离该行所述第一驱动电极的中心。
在一些实施例中，一行所述第一驱动电极中，与所述金属连接线电连接的所述第一驱动电极的数量不超过第一阈值，所述第一阈值的取值范围为 2～5。
在一些实施例中，多行第一驱动电路，位于所述第二区域；一行所述第一驱动电极中的一个所述第一驱动电极通过一条所述连接线与一行第一驱动电路中的一个第一驱动电路电连接；其中，一行所述第一驱动电极所连接的所述连接线中，所述金属连接线的长度小于所述透明连接线的长度。
在一些实施例中，越远离一行所述第一驱动电极的中心的所述第一驱动电极所连接的所述金属连接线越短；和/或，越远离一行所述第一驱动电极的中心的所述第一驱动电极所连接的所述透明连接线越短。
在一些实施例中，一行所述第一驱动电路与一行所述第一驱动电极，按照近接近、远接远的方式实现电连接。
在一些实施例中，所述阵列基板还包括：多行第二驱动电极，位于所述第二区域；多行第二驱动电路，位于所述第二区域；一行第二驱动电路中的一个第二驱动电路与一行第二驱动电极中的一个第二驱动电极电连接；其中，一行所述第一驱动电路分散布置于一行所述第二驱动电路中的多个所述第二驱动电路之间。
在一些实施例中，所述第二区域包括第一子区域和第二子区域，所述第一子区域与所述第一区域邻接；其中，位于所述第一子区域的所述第二驱动电极的面积小于位于所述第二子区域的所述第二驱动电极的面积，并且所述第一驱动电极的面积小于位于所述第二子区域的所述第二驱动电极的面积；所有所述第一驱动电极和位于所述第一子区域的所有所述第二驱动电极分为多个重复单元，一个重复单元包括2k行4h列驱动电极；其中，k、h为大于或等于1的正整数。
在一些实施例中，所述第一区域和所述第一子区域两者整体的边界包括直线段和阶梯线段，相邻的两个直线段之间通过一个所述阶梯线段连接；其中，所述阶梯线段包括依次连接的多个子线段，一个子线段跨过2k行驱动电极或4h列驱动电极。
在一些实施例中，位于所述第一子区域的至少一个所述第二驱动电极的主体形状与至少一个所述第一驱动电极的主体形状相同；和/或，位于所述第一子区域的至少一个所述第二驱动电极的面积与至少一个所述第一驱动电极的面积相等。
在一些实施例中，所述第一驱动电极的主体形状为椭圆形或圆形；位于所述第一子区域的所述第二驱动电极的主体形状为椭圆形或圆形。
在一些实施例中，所述阵列基板，还包括：衬底；位于所述衬底一侧的 驱动电路层，所述第一驱动电路和所述第二驱动电路均位于所述驱动电路层中；所述驱动电路层包括依次远离所述衬底的第一源漏电极层和第二源漏电极层；位于所述驱动电路层远离所述衬底一侧的至少两层透明导电层；其中，所述透明连接线位于所述透明导电层中，所述金属连接线位于所述第一源漏电极层或所述第二源漏电极层中。
在一些实施例中，所述第一区域和所述第二区域中均具有多个子像素区域；所述金属连接线在行方向上的尺寸大于一个所述子像素区域在行方向上的尺寸。
在一些实施例中，所述第一区域中包括光学部件区域；所述金属连接线与所述光学部件区域之间的最小距离大于一个所述子像素区域在所述行方向上的尺寸。
在一些实施例中，所述金属连接线的位于所述第一区域的部位的长度小于所述金属连接线的位于所述第二区域的部位的长度。
另一方面，提供一种显示面板。所述显示面板包括：如上述任一实施例所述的阵列基板；位于所述阵列基板一侧的发光功能层；位于所述发光功能层远离所述阵列基板一侧的公共电极层；以及，位于所述公共电极层远离所述阵列基板一侧的封装层。
又一方面，提供一种显示装置。所述显示装置包括：如上述实施例所述的显示面板和光学部件。所述光学部件在所述显示面板上的正投影位于所述第一区域内。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据本公开一些实施例中的阵列基板的结构图；
图2为图1所示的阵列基板沿A-A’向的一种剖视图；
图3为根据本公开一些实施例中的一种子像素的电路图；
图4A为根据本公开一些实施例中的一种显示基板的局部结构图；
图4B为根据本公开一些实施例中的另一种显示基板的局部结构图；
图4C为根据本公开一些实施例中的又一种显示基板的局部结构图；
图5为根据本公开一些实施例中的又一种显示基板的局部结构图；
图6为根据本公开一些实施例中的又一种显示基板的局部结构图；
图7为根据本公开一些实施例中的又一种显示基板的局部结构图；
图8为根据本公开一些实施例中的又一种显示基板的局部结构图；
图9为根据本公开一些实施例中的又一种显示基板的局部结构图；
图10为根据本公开一些实施例中的又一种显示基板的局部结构图；
图11为根据本公开一些实施例中的一种显示面板的结构图；
图12为根据本公开一些实施例中的一种显示装置的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施 例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
在本公开的实施例提供的电路结构(例如移位寄存器、像素驱动电路)中，移位寄存器所采用的晶体管可以为薄膜晶体管(Thin Film Transistor，简称TFT)、场效应晶体管(Metal Oxide Semiconductor，简称MOS)或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。
在本公开的实施例提供的电路结构中，各电路所采用的各晶体管的控制极为晶体管的栅极，第一极为晶体管的源极和漏极中一者，第二极为晶体管的源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性的，在晶体管为P型晶体管的情况下，晶体管的第一极为源极，第二极为漏极；示例性的，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。其中，源极和漏极所在膜层可以称为源漏电极层。
在本公开的实施例中，电容器可以是通过工艺制程单独制作的电容器件，例如通过制作专门的电容电极来实现电容器件，该电容器的各个电容电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现。电容器也可以是晶体管之间的寄生电容，或者通过晶体管本身与其他器件、线路来实现，又或者 利用电路自身线路之间的寄生电容来实现。
在本公开的实施例提供的电路中，“节点”并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点，也就是说，这些节点是由电路图中相关电连接的汇合点等效而成的节点。
在本公开的实施例提供的电路所包括的晶体管，可以均为N型晶体管，也可以均为P型晶体管。或者，各电路所包括的晶体管中的一部分晶体管可以为N型晶体管，另一部分可以为P型晶体管。
在本公开中，“有效电平”指的是，可以使晶体管导通的电平。其中，P型晶体管可以在低电平信号的控制下导通，N型晶体管可以在高电平信号的控制下导通。
下面，在本公开的实施例提供的电路中，以晶体管均为P型晶体管(此时有效电平为低电平)为例进行说明。需要说明的是，下面提及的各电路中的晶体管采用相同的导通类型，可以简化工艺流程，减少工艺难度，提高产品(例如阵列基板100、显示面板1000及显示装置2000)的良率。
请参阅图1，本公开的一些实施例提供了一种阵列基板100，该阵列基板100具有第一区域A1和第二区域A2，第二区域A2包围至少部分第一区域A1。
此处，第一区域A1的数量可以为至少一个，第二区域A2的数量例如可以为一个。下面，如图1所示，以第一区域A1的数量和第二区域A2的数量均为一个为例，对阵列基板100的结构进行示意性说明。
在一些示例中，如图1所示，第二区域A2可以完全包围第一区域A1。此时，第一区域A1的形状例如可以为圆形、椭圆形、矩形或其他不规则的图形等。
在另一些示例中，第二区域A2可以围绕第一区域A1的一部分，也即，第二区域A2的边界的一部分与第一区域A1的边界的一部分接触。此时，第一区域A1的形状例如可以为矩形、圆角矩形、水滴形或半圆形等。
在一些实施例中，请参阅图2，上述阵列基板100可以包括：衬底1。
上述衬底1的类型包括多种，可以根据实际需要选择设置。
在一些示例中，上述衬底1可以为刚性衬底。其中，该刚性衬底可以为玻璃衬底或PMMA(Polymethyl methacrylate，聚甲基丙烯酸甲酯)衬底等。
在一些示例中，上述衬底1可以为柔性衬底。其中，该柔性衬底可以为PET(Polyethylene terephthalate，聚对苯二甲酸乙二醇酯)衬底、PEN(Polyethylene naphthalate two formic acid glycol ester，聚萘二甲酸乙二醇酯) 衬底或PI(Polyimide，聚酰亚胺)衬底等。此时，上述阵列基板100例如可以实现柔性显示。
在一些实施例中，请继续参阅图2，上述阵列基板100还可以包括：设置在衬底1上的驱动电路层2。
示例性的，上述驱动电路层2可以包括多个第一驱动电路21和多个第二驱动电路22。
上述第一驱动电路21、第二驱动电路22的结构包括多种，可以根据实际需要选择设置。例如，第一驱动电路21或第二驱动电路22的结构可以包括“2T1C”、“6T1C”、“7T1C”、“6T2C”或“7T2C”等结构。此处，“T”表示为晶体管，位于“T”前面的数字表示为晶体管的数量，“C”表示为存储电容器，位于“C”前面的数字表示为存储电容器的数量。
示例性的，如图3所示，第一驱动电路21的结构和第二驱动电路22的结构，例如可以相同。例如，两者的结构均为7T1C结构。其中，图3为第二驱动电路22的等效电路图，当然，第一驱动电路21的等效电路图可以与图3所示的等效电路相同。
例如，第二驱动电路22包括：开关晶体管T1、驱动晶体管T2、补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6、第二复位晶体管T7和存储电容器Cst。
其中，在复位信号端RST所传输的复位信号的电平为有效电平的情况下，第一复位晶体管T6和第二复位晶体管T7可以在该复位信号的控制下导通，接收来自初始信号端Vinit所传输的初始信号，第一复位晶体管T6可以将初始信号传输至存储电容器Cst的一端，对其进行复位；第二复位晶体管T7可以将初始信号传输至第二复位晶体管T7的第二极，对其进行复位。此处，驱动晶体管T2可以在初始信号的控制下导通。
在扫描信号端Gate所传输的扫描信号的电平为有效电平的情况下，开关晶体管T1和补偿晶体管T3可以在该扫描信号的控制下导通，数据信号端Data所传输的数据信号，可以依次经开关晶体管T1、驱动晶体管T2、补偿晶体管T3传输至驱动晶体管T2的控制极，对驱动晶体管T2的控制极进行充电，直至驱动晶体管T2截止。此时，完成对驱动晶体管T2的阈值电压的补偿。
在使能信号端EM所传输的使能信号的电平为有效电平的情况下，第一发光控制晶体管T4和第二发光控制晶体管T5可以在该使能信号的控制下导通，接收来自第一电压信号端ELVDD的第一电压信号，驱动晶体管T2可以根据数据信号及第一电压信号生成驱动信号，并将驱动信号差传输至第二复 位晶体管T7的第二极。
在一些实施例中，请参阅图5和图6，上述多个第二驱动电路22可以沿第一方向X排列为多列，沿第二方向Y排列为多行。其中，每列第二驱动电路22可以包括多个第二驱动电路22，该多个第二驱动电路22沿第二方向Y依次排列。每行第二驱动电路22可以包括多个第二驱动电路22，该多个第二驱动电路22沿第一方向X依次排列。
其中，第一方向X与第二方向Y相交叉。此处，第一方向X和第二方向Y之间的夹角，可以根据实际需要选择设置。例如，第一方向X和第二方向Y之间的夹角为85°、88°或90°等。
在一些实施例中，请继续参阅图5和图6，一行所述第一驱动电路21分散布置于一行所述第二驱动电路22中的多个第二驱动电路22之间。例如，每间隔相邻的多列第二驱动电路22，存在一列第一驱动电路21。也即是说，每相邻两列第一驱动电路21之间可以间隔多列相邻的第二驱动电路22。
其中，任意相邻两列第一驱动电路21之间可以间隔相同列数的第二驱动电路22，如此确保了排布的均一性。
示例性的，如图5和图6所示，任意相邻两列第一驱动电路21之间均设置两列第二驱动电路22。
在一些实施例中，阵列基板100所包括的驱动电路层2，可以包括沿垂直且远离衬底1的方向依次层叠的半导体层、第一栅导电层、第二栅导电层、源漏电极层。
在一些示例中，半导体层可以包括第一驱动电路21和第二驱动电路22中各晶体管的有源层。第一栅导电层可以包括第一驱动电路21和第二驱动电路22中各晶体管的控制极，以及各存储电容器的一个极板。当然，第一栅导电层还可以包括用于传输扫描信号的栅线、用于传输复位信号的复位信号线。第二栅导电层可以包括第一驱动电路21和第二驱动电路22中各存储电容器的另一个极板。当然，第二栅导电层还可以包括用于传输初始信号的初始信号线。源漏电极层可以包括第一驱动电路21和第二驱动电路22中各晶体管的第一极、第二极。在上述第一驱动电路21、第二驱动电路22所包含的晶体管中至少一个晶体管包括第一源极、第一漏极、第二源极和第二漏极时，第一源极和第一漏极所在膜层可以称为第一源漏电极层；第二源极和第二漏极所在膜层可以称为第二源漏电极层。如图2所示，仅示出第一源漏电极层201和第二源漏电极层202。第一源漏电极层201和第二源漏电极层202依次远离衬底1。
在一些实施例中，请继续参阅图2，上述阵列基板100还可以包括：位于驱动电路层2远离衬底1一侧的驱动电极层3。
示例性的，上述驱动电极层3可以包括多个第一驱动电极31和多个第二驱动电极32。
示例性的，一个第一驱动电路21可以和一个第一驱动电极31电连接。例如，第一驱动电路21和第一驱动电极31之间一一对应设置。第一驱动电路21可以为相应的第一驱动电极31提供驱动信号。
示例性的，一个第二驱动电路22可以和一个第二驱动电极32电连接。例如，第二驱动电路22和第二驱动电极32之间一一对应设置。第二驱动电路22可以为相应的第二驱动电极32提供驱动信号。
在一些示例中，请继续参阅图5和图6，上述驱动电路层2中的多个第一驱动电路21和多个第二驱动电路22可以均位于第二区域A2。上述驱动电极层3中的多个第一驱动电极31可以均位于第一区域A1，多个第二驱动电极32可以均位于第二区域A2。也即，在第一区域A1内只设置多个第一驱动电极31，不设置相应的驱动电路；在第二区域A2内设置有第二驱动电极32和与第二驱动电极32对应的第二驱动电路22，以及与多个第一驱动电极31对应的多个第一驱动电路21。也就是说，在第一区域A1内不设置任何驱动电路。
在一些示例中，如图5所示，多个第一驱动电路21分散布置在第一区域A1的一侧。
在一些示例中，如图6所示，多个第一驱动电路21分散布置在第一区域A1的两侧。
需要说明的是，为了能够在不减少第二区域A2内的第二驱动电极32的数量的前提下，为第一驱动电路21的设置提供充足的空间，可以通过沿第一方向X对第二区域A2内的第二驱动电路22进行压缩，以便将第一驱动电极31对应的第一驱动电路21放置在第二区域A2。
本公开的一些示例将为第一驱动电极31提供驱动信号的第一驱动电路21设置在第二区域A2，减少了第一区域A1中能够对光线进行遮挡的结构，外界光线也便能够从阵列基板100位于第一区域A1的部分的一侧(例如出光侧)，穿过任意相邻两个第一驱动电极31之间的间隙，从阵列基板100位于第一区域A1的部分的另一侧(例如非出光侧)出射，使得阵列基板100位于第一区域A1的部分具有较高的透光率。
在一些示例中，上述多个第一驱动电极31的分布密度，与上述多个第二 驱动电极32的分布密度可以相同。由此，可以降低第一区域A1和第二区域A2的亮度和分辨率差异，实现更加均匀的全面屏显示效果，还有利于确保阵列基板100具有较好的图像显示质量。
在一些示例中，上述多个第一驱动电极31的分布密度，可以小于上述多个第二驱动电极32的分布密度。由此，可以通过增大任意相邻的两个第一驱动电极31之间的间距，减小第一驱动电极31对外界光线的遮挡，增大阵列基板100的第一区域A1的中可透光部分的面积，从而可以进一步增大外界光线可以透过阵列基板100位于第一区域A1的部分的量，使得阵列基板100位于第一区域A1的部分的透光率更好。
在一些实施例中，请继续参阅图2，上述阵列基板100还可以包括：位于驱动电极层3远离衬底1一侧的至少两层透明导电层4。其中，该至少两层透明导电层4可以沿垂直于衬底1的方向，依次层叠设置。例如，透明导电层4的数量可以为两层，或者三层等。
示例性的，如图2所示，透明导电层4的数量的三层。第一透明导电层041、第二透明导电层042和第三透明导电层043均位于驱动电极层3远离衬底1的一侧，且第一透明导电层041、第二透明导电层042和第三透明导电层043依次远离衬底1。
在一些实施例中，请参阅图4A～图6，一行走线区04与一行第一驱动电极31相邻。上述阵列基板100还包括：多条连接线40。连接线40经由走线区04延伸至第二区域A2。一条连接线40的一端与一行第一驱动电极31中的一个第一驱动电极31电连接，另一端与位于第二区域A2的和其对应的第一驱动电路21电连接。由此可以利用连接线40实现第一驱动电路21和第一驱动电极31之间的电连接，第一驱动电路21便可以通过连接线40向相应的第一驱动电极31传输驱动信号。
在一些实施例中，如图4A～图6所示，至少一行所述第一驱动电极31所连接的连接线40经由至少一行走线区04延伸至第二区域A2。
至少一行所述第一驱动电极31所连接的连接线40经由至少一行走线区04延伸至第二区域A2，与位于第二区域A2的第一驱动电路21电连接，第一驱动电路21便可以通过连接线40向相应的第一驱动电极31传输驱动信号。
需要说明的是，“至少一行所述第一驱动电极31所连接的连接线40经由至少一行走线区04延伸至第二区域A2”可以是，至少一行所述第一驱动电极31所连接的连接线40经由一行走线区04延伸至第二区域A2；也可以是，至少一行所述第一驱动电极31所连接的连接线40经由两行或多行走线 区04延伸至第二区域A2。本公开各个实施例对此不做限定。例如，如图5和图6所示，至少一行所述第一驱动电极31所连接的连接线40经由两行走线区04延伸至第二区域A2；如图4A所示，至少一行所述第一驱动电极31所连接的连接线40经由三行走线区04延伸至第二区域A2。
在一些示例中，至少一行所述第一驱动电极31所连接的连接线40位于不同层。
本领域技术人员可以理解的是，至少一行所述第一驱动电极31所连接的连接线40位于不同层，是指：在阵列基板100的厚度方向(例如图2中所示的方向a-a’)上，至少一行所述第一驱动电极31所连接的连接线40位于不同的膜层。例如，一行所述第一驱动电极31所连接的连接线40同时位于至少一层源漏电极层和至少一层透明导电层。又如，一行所述第一驱动电极31所连接的连接线40同时位于至少两层透明导电层。
由此，本公开的一些实施例所提供的阵列基板100，通过将至少一行所述第一驱动电极31所连接的连接线40设置在不同层，可以增大与一行第一驱动电极31电连接的连接线40的布局空间，从而实现有限的空间内布局数量庞大的连接线40，避免一行第一驱动电极31中的第一驱动电极31的数量较多时，在同一层无法布局较多的连接线40，而导致部分第一驱动电极31无法通过连接线40与对应的第一驱动电路21电连接。
在一些实施例中，请继续参阅图4A～图6，多条连接线40中的至少部分连接线40为透明连接线41。透明连接线41位于上述透明导电层4中。该透明连接线41可以由氧化铟锡(indium tin oxide，ITO)或铟镓锌氧化物(indium gallium zinc oxide，IGZO)等透明材料制成。
至少一行所述第一驱动电极31所连接的透明连接线41经由至少两行走线区04延伸至第二区域A2。一条透明连接线41的一端与一行第一驱动电极31中的一个第一驱动电极31电连接，另一端与位于第二区域A2的和其对应的第一驱动电路21电连接。由此可以利用透明连接线41实现第一驱动电路21和第一驱动电极31之间的电连接，第一驱动电路21便可以通过透明连接线41向相应的第一驱动电极31传输驱动信号。
需要说明的是，“至少一行所述第一驱动电极31所连接的透明连接线41经由至少两行走线区04延伸至第二区域A2”可以是，至少一行所述第一驱动电极31所连接的透明连接线41经由两行走线区04延伸至第二区域A2；也可以是，至少一行所述第一驱动电极31所连接的透明连接线41经由三行或多行走线区04延伸至第二区域A2。本公开各个实施例对此不做限定。例 如，如图4A所示，至少一行所述第一驱动电极31所连接的透明连接线41经由三行走线区04延伸至第二区域A2。
在一些示例中，至少一行所述第一驱动电极31所连接的透明连接线41位于不同层。
本领域技术人员可以理解的是，至少一行所述第一驱动电极31所连接的透明连接线41位于不同层，是指：在阵列基板100的厚度方向(例如图2中所示的方向a-a’)上，至少一行所述第一驱动电极31所连接的透明连接线41位于不同的透明导电层4。
本实施例中，第一驱动电极31通过透明连接线41和位于第二区域A2的第一驱动电路21电连接，可以使第一驱动电路21通过透明连接线41向相应的第一驱动电极31传输驱动信号，还可以减少对光线的阻挡，使光线也便能够从阵列基板100位于第一区域A1的部分的一侧(例如出光侧)，穿过任意相邻两个第一驱动电极31之间的间隙，从阵列基板100位于第一区域A1的部分的另一侧(例如非出光侧)出射，使得阵列基板100位于第一区域A1的部分具有较高的透光率；而且，通过将至少一行所述第一驱动电极31所连接的透明连接线41设置在不同层，可以增大与一行第一驱动电极31电连接的透明连接线41的布局空间，从而实现有限的空间内布局数量庞大的透明连接线41，使得第一驱动电极31与第一驱动电路2通过透明连接线41实现一对一连接。
在一些实施例中，请参阅图4A和图7，至少一行所述第一驱动电极31所连接的透明连接线41包括：第一类透明连接线411和第二类透明连接线412。
在一些示例中，请继续参阅图7，第004行第一驱动电极31包括第一类透明连接线411和第二类透明连接线412；第007行第一驱动电极31包括第一类透明连接线411和第二类透明连接线412；第008行第一驱动电极31包括第一类透明连接线411和第二类透明连接线412；第010行第一驱动电极31包括第一类透明连接线411和第二类透明连接线412；第011行第一驱动电极31包括第一类透明连接线411和第二类透明连接线412；第013行第一驱动电极31包括第一类透明连接线411和第二类透明连接线412。需要说明的是，此处仅为举例说明，本领域技术人员可以理解的是，还可以存在其它行同样包括第一类透明连接线411和第二类透明连接线412。
其中，与第一类透明连接线411电连接的第一驱动电极31，相对于与第二类透明连接线412电连接的第一驱动电极31，更靠近该行所述第一驱动电 极31的中心。
在一些示例中，请继续参阅图7，第一类透明连接线411的数量大于第二类透明连接线412的数量，且第一类透明连接线411与第二类透明连接线412位于不同层。
本领域技术人员可以理解的是，第一类透明连接线411与第二类透明连接线412位于不同层，是指：在阵列基板100的厚度方向(例如图2中所示的方向a-a’)上，第一类透明连接线411与第二类透明连接线412位于不同的透明导电层4。
本实施例中，通过将至少一行所述第一驱动电极31所连接的透明连接线41设置在不同层，可以增大与一行第一驱动电极31电连接的透明连接线41的布局空间，从而实现有限的空间内布局数量庞大的连接线40，避免一行第一驱动电极31中的第一驱动电极31的数量较多时，在同一层无法布局较多的连接线40，而导致部分第一驱动电极31无法通过连接线40与对应的第一驱动电路21电连接。
在一些实施例中，请参阅图4A，至少一行所述第一驱动电极31所连接的第一类透明连接线411，经由位于该行第一驱动电极31同一侧且最靠近该行第一驱动电极31的N1行走线区04延伸至第二区域A2。其中，N1为大于或等于2的正整数。
示例性的，如图4A所示，N1＝3。至少一行所述第一驱动电极31所连接的第一类透明连接线411，经由位于该行第一驱动电极31同一侧且最靠近该行第一驱动电极31的3行走线区04延伸至第二区域A2。
本实施例中，至少一行所述第一驱动电极31所连接的第一类透明连接线411分散在N1行走线区04，可以增大与一行第一驱动电极31电连接的连接线40的布局空间，从而实现有限的空间内布局数量庞大的连接线40，使第一驱动电极31与第一驱动电路21通过第一类透明连接线411实现一对一连接，第一驱动电路21便可以通过第一类透明连接线411向相应的第一驱动电极31传输驱动信号。
在一些实施例中，以相邻的N2行第一驱动电极31为一个周期。其中，N2为大于或等于2的正整数；在同一周期内，各行所述第一驱动电极31所连接的第一类透明连接线411位于不同层。
在一些示例中，请参阅图7，N2＝3。以相邻的第001行第一驱动电极31、第002行第一驱动电极31和第003行第一驱动电极31为一个周期01。相邻的第004行第一驱动电极31、第005行第一驱动电极31和第006行第一驱动 电极31为另一个周期01。相邻的第007行第一驱动电极31、第008行第一驱动电极31和第009行第一驱动电极31为又一个周期01。相邻的第010行第一驱动电极31、第011行第一驱动电极31和第012行第一驱动电极31为又一个周期01。相邻的第013行第一驱动电极31、第014行第一驱动电极31和第015行第一驱动电极31为又一个周期01。
其中，同一个周期内的3行第一驱动电极31所连接的第一类透明连接线411位于不同层。
示例性的，请继续参阅图7，第001行第一驱动电极31所连接的透明连接线41包括：第一类透明连接线411；第002行第一驱动电极31所连接的透明连接线41包括：第一类透明连接线411；第003行第一驱动电极31所连接的透明连接线41包括：第一类透明连接线411。第001行第一驱动电极31所连接的第一类透明连接线411、第002行第一驱动电极31所连接的第一类透明连接线411以及第003行第一驱动电极31所连接的第一类透明连接线411位于不同层。
同理，第004行第一驱动电极31所连接的第一类透明连接线411、第005行第一驱动电极31所连接的第一类透明连接线411和第006行第一驱动电极31所连接的第一类透明连接线411位于不同层。
同理，第007行第一驱动电极31所连接的第一类透明连接线411、第008行第一驱动电极31所连接的第一类透明连接线411和第009行第一驱动电极31所连接的第一类透明连接线411位于不同层。
同理，第010行第一驱动电极31所连接的第一类透明连接线411、第011行第一驱动电极31所连接的第一类透明连接线411和第012行第一驱动电极31所连接的第一类透明连接线411位于不同层。
同理，第013行第一驱动电极31所连接的第一类透明连接线411、第014行第一驱动电极31所连接的第一类透明连接线411和第015行第一驱动电极31所连接的第一类透明连接线411位于不同层。
本领域技术人员可以理解的是，同一个周期内的3行第一驱动电极31所连接的第一类透明连接线411位于不同层，是指：在阵列基板100的厚度方向(例如图2中所示的方向a-a’)上，同一个周期内的3行第一驱动电极31所连接的第一类透明连接线411分别位于不同的透明导电层4。
本实施例中，通过分层设置同一个周期内的各行第一驱动电极31所连接的第一类透明连接线411，可以增大与各行所述第一驱动电极31所连接的第一类透明连接线411的布线空间，从而实现在有限的空间内布局数量庞大的 透明走线，避免同层设置数量较多的第一类透明连接线411时，第一类透明连接线411之间发生短路，降低了结构设计和工艺难度。
在一些实施例中，至少一行所述第一驱动电极31所连接的至少部分第二类透明连接线412，和与该行所述第一驱动电极31处于同一周期01内的任意一行所述第一驱动电极31所连接的第一类透明连接线411同层设置，且经由与该行第一驱动电极31处于同周期内的第一驱动电极31所连接的第一类透明连接线411所在的走线区04延伸至第二区域A2。
在一些示例中，请继续参阅图7，第004行第一驱动电极31包括第一类透明连接线411和第二类透明连接线412。第004行第一驱动电极31所连接的第二类透明连接线412可以包括第一部分透明连接线4121和第二部分透明连接线4122。第004行第一驱动电极31所连接的第一部分透明连接线4121可以和与第005行第一驱动电极31所连接的第一类透明连接线411同层设置，且经由第005行第一驱动电极31所连接的第一类透明连接线411所在的走线区04延伸至第二区域A2。
同理，第007行第一驱动电极31包括第一类透明连接线411和第二类透明连接线412。第007行第一驱动电极31所连接的第二类透明连接线412可以包括第一部分透明连接线4121和第二部分透明连接线4122。第007行第一驱动电极31所连接的第一部分透明连接线4121可以和与第008行第一驱动电极31所连接的第一类透明连接线411同层设置，且经由第008行第一驱动电极31所连接的第一类透明连接线411所在的走线区04延伸至第二区域A2。
同理，第008行第一驱动电极31包括第一类透明连接线411和第二类透明连接线412。第008行第一驱动电极31所连接的至少部分第二类透明连接线412可以和与第009行第一驱动电极31所连接的第一类透明连接线411同层设置，且经由第009行第一驱动电极31所连接的第一类透明连接线411所在的走线区04延伸至第二区域A2。
同理，第010行第一驱动电极31包括第一类透明连接线411和第二类透明连接线412。第010行第一驱动电极31所连接的至少部分第二类透明连接线412可以和与第012行第一驱动电极31所连接的第一类透明连接线411同层设置，且经由第012行第一驱动电极31所连接的第一类透明连接线411所在的走线区04延伸至第二区域A2。
同理，第011行第一驱动电极31包括第一类透明连接线411和第二类透明连接线412。第011行第一驱动电极31所连接的至少部分第二类透明连接线412可以和与第012行第一驱动电极31所连接的第一类透明连接线411同 层设置，且经由第012行第一驱动电极31所连接的第一类透明连接线411所在的走线区04延伸至第二区域A2。
同理，第013行第一驱动电极31包括第一类透明连接线411和第二类透明连接线412。第013行第一驱动电极31所连接的至少部分第二类透明连接线412可以和与第015行第一驱动电极31所连接的第一类透明连接线411同层设置，且经由第015行第一驱动电极31所连接的第一类透明连接线411所在的走线区04延伸至第二区域A2。
需要说明的是，“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。
本实施例中，通过使至少一行所述第一驱动电极31所连接的至少部分第二类透明连接线412，和与该行所述第一驱动电极31处于同一周期01内的任意一行第一驱动电极31所连接的第一类透明连接线411同层设置，既简化了制作工艺，还可以使同周期内第一驱动电极31个数较少的一行弥补了同周期内第一驱动电极31个数较多的一行的第一类透明连接线411的布局空间，增大了与同周期内第一驱动电极31个数较多的一行电连接的第一类透明连接线411的布局空间，从而实现有限的空间内布局数量庞大的第一类透明连接线411。
在一些实施例中，至少一行所述第一驱动电极31所连接的至少部分第二类透明连接线412，和与该行第一驱动电极31处于不同周期内的任意一行第一驱动电极31所连接的第一类透明连接线411同层设置，且经由与该行第一驱动电极31处于不同周期内的第一驱动电极31所连接的第一类透明连接线411所在的所述走线区04延伸至所述第二区域A2。
在一些示例中，请继续参阅图7，第004行第一驱动电极31包括第一类透明连接线411和第二类透明连接线412。第004行第一驱动电极31所连接的第二类透明连接线412可以包括第一部分透明连接线4121和第二部分透明连接线4122。第004行第一驱动电极31所连接的第二部分透明连接线4122可以和与第003行第一驱动电极31所连接的第一类透明连接线411同层设置，且经由第003行第一驱动电极31所连接的第一类透明连接线411所在的走线区04延伸至第二区域A2。
同理，第007行第一驱动电极31包括第一类透明连接线411和第二类透 明连接线412。第007行第一驱动电极31所连接的第二类透明连接线412可以包括第一部分透明连接线4121和第二部分透明连接线4122。第007行第一驱动电极31所连接的第二部分透明连接线4122可以和与第006行第一驱动电极31所连接的第一类透明连接线411同层设置，且经由第006行第一驱动电极31所连接的第一类透明连接线411所在的走线区04延伸至第二区域A2。
同理，第010行第一驱动电极31包括第一类透明连接线411和第二类透明连接线412。第010行第一驱动电极31所连接的至少部分第二类透明连接线412可以和与第009行第一驱动电极31所连接的第一类透明连接线411同层设置，且经由第009行第一驱动电极31所连接的第一类透明连接线411所在的走线区04延伸至第二区域A2。
同理，第013行第一驱动电极31包括第一类透明连接线411和第二类透明连接线412。第013行第一驱动电极31所连接的至少部分第二类透明连接线412可以和与第012行第一驱动电极31所连接的第一类透明连接线411同层设置，且经由第012行第一驱动电极31所连接的第一类透明连接线411所在的走线区04延伸至第二区域A2。
本实施例中，通过使至少一行所述第一驱动电极31所连接的至少部分所述第二类透明连接线412，和与该行所述第一驱动电极31处于不同周期内的任意一行所述第一驱动电极31所连接的第一类透明连接线411同层设置，既简化了制作工艺，还可以使周期内第一驱动电极31个数较少的一行弥补了其它周期内第一驱动电极31个数较多的一行的第一类透明连接线411的布局空间，增大了与第一驱动电极31个数较多的一行电连接的第一类透明连接线411的布局空间，从而实现有限的空间内布局数量庞大的第一类透明连接线411。
在一些实施例中，请参阅图4B和图4C，第一区域A1包括沿设定方向依次排布的至少两个子区域A01。其中，该设定方向为由一行所述第一驱动电极31的中心b指向该行第一驱动电极31的一端b’(例如图4B中所示的方向b-b’)。位于不同的子区域A01内的第一驱动电极31所连接的透明连接线41分别位于不同层。
本领域技术人员可以理解的是，位于不同的子区域A01内的第一驱动电极31所连接的透明连接线41分别位于不同层，是指：在阵列基板100的厚度方向(例如图2中所示的方向a-a’)上，位于不同的子区域A01内的第一驱动电极31所连接的透明连接线41位于不同的透明导电层4。
在一些示例中，在由一行所述第一驱动电极31的中心b指向该行第一驱动电极31的一端b’的方向b-b’上，第一区域A1包括两个子区域A01。位于 两个子区域A01内的第一驱动电极31所连接的透明连接线41分别位于不同层。位于两个子区域A01内的第一驱动电极31所连接的透明连接线41均由走线区04延伸至第二区域A2。
在一些示例中，请参阅图4B和图4C，在由一行所述第一驱动电极31的中心b指向该行第一驱动电极31的一端b’的方向b-b’上，所述至少两个子区域包括第一个子区域A011、第二个子区域A012和第三个子区域A013。位于三个子区域A01内的第一驱动电极31所连接的透明连接线41分别位于不同层。例如，在由一行所述第一驱动电极31的中心b指向该行第一驱动电极31的一端的方向上，第一个子区域A011内的第一驱动电极31所连接的透明连接线41位于第一透明导电层041；第二个子区域A012内的第一驱动电极31所连接的透明连接线41位于第二透明导电层042。第三个子区域A013内的第一驱动电极31所连接的透明连接线41位于第三透明导电层043。位于三个子区域A01内的第一驱动电极31所连接的透明连接线41均由走线区04延伸至第二区域A2。
本公开发明人经研究发现，透明连接线41在延伸至第二区域A2实现第一驱动电极31和第一驱动电路21的电连接的过程中，可能会跨过第一驱动电路21和/或第二驱动电路22，并与其形成寄生电容。寄生电容的存在，容易影响第一驱动电极31所接收的驱动信号的准确性。
通常在第一区域A1内，位于第一区域A1内的中间区域的透明连接线采用纵向走线的布线方式，实现第一驱动电极31和第一驱动电路21的电连接；位于第一区域A1内的中间区域的两侧区域采用横向布线的走线方式，实现第一驱动电极31和第一驱动电路21的电连接。
采用纵向走线的布线方式，会增加透明连接线的长度，而且位于第一区域A1的中间区域的透明连接线与两侧区域的透明连接线走线过滤不均匀，进而透明连接线中所形成的寄生电容的变化不均匀，会使第一区域A1的中间区域与两侧区域产生“暗-亮-暗”或者“亮-暗-亮”的亮度差异，影响显示效果。
本实施例中，第一区域A1包括沿设定方向依次排布的至少两个子区域A01，位于不同的子区域A01内的第一驱动电极31所连接的透明连接线41分别位于不同层，从而增大了与一行第一驱动电极31电连接的连接线40的布局空间，从而实现有限的空间内布局数量庞大的透明连接线41，而且由此透明连接线41均可以由走线区04延伸至第二区域A2，透明连接线41的规律排布，可以提高任意两个相邻的第一驱动电极31所连接的透明连接线41所跨过的第一驱动电路21和/或第二驱动电路22的数量差异的规律，进而便 于提高两个相邻的第一驱动电极31所连接的透明连接线41中所形成的寄生电容的变化均匀性，提高第一驱动电极31所接收的驱动信号的准确性，在将阵列基板100应用至显示面板1000中，透明连接线41的走线环境均匀，可改善显示面板1000的亮度差异，提高显示面板1000的显示效果。
在一些实施例中，至少一行所述第一驱动电极31中，位于不同子区域A01中的所述第一驱动电极31的数量相等。
在一些示例中，请参阅图4C，第一区域A1为矩形，第一区域A1中的每行所述第一驱动电极31中，位于不同子区域A01中的所述第一驱动电极31的数量相等。
本实施例中，部分行或者全部行所述第一驱动电极31中，位于不同子区域A01中的所述第一驱动电极31的数量相等，也即，部分行或者全部行所述第一驱动电极31中从不同子区域A01所延伸出的透明连接线41的数量相等；而且，不同子区域A01内的第一驱动电极31所连接的透明连接线41分别位于不同层，既增大了与该行第一驱动电极31电连接的连接线40的布局空间，从而实现有限的空间内布局数量庞大的透明连接线41，而且，对透明连接线41的走向路径规划更规律，简化阵列基板100的结构，降低制备形成阵列基板100的难度。
在一些实施例中，一行所述第一驱动电极31所连接的透明连接线41，经由与该行第一驱动电极31相邻的一行或者两行走线区04延伸至第二区域A02。
在一些示例中，一行所述第一驱动电极31所连接的透明连接线41，经由与该行第一驱动电极31相邻的一行走线区04延伸至第二区域A02。
在另一些示例中，如图4C所示，至少一行所述第一驱动电极31所连接的透明连接线41，经由与该行第一驱动电极31相邻的两行走线区04延伸至第二区域A02。
其中，第一区域A1中可以包括多个绿色子像素区域、多个蓝色子像素区域以及多个红色子像素区域。多个第一驱动电极31包括多个与红色子像素区域对应的第一驱动电极31、多个与蓝色子像素区域对应的第一驱动电极31以及多个与绿色子像素区域对应的第一驱动电极31。
在一些示例中，与绿色子像素区域对应的第一驱动电极31所连接透明连接线41，经由与该行第一驱动电极31相邻的其中一行走线区延伸至第二区域A02。与红色子像素区域对应的第一驱动电极31以及与蓝色子像素区域对应的第一驱动电极31所连接透明连接线41，经由与该行第一驱动电极31相邻 的另一行走线区延伸至第二区域A02。
本领域技术人员可以理解的是，在绿色子像素与红色子像素和蓝色子像素相比，在需要被点亮时，绿色子像素需要与红色子像素和蓝色子像素所需要得充电时间不同。
本实施例中，一行所述第一驱动电极31所连接的透明连接线41，经由与该行第一驱动电极31相邻的一行或者两行走线区04延伸至第二区域A02，可以增大与一行第一驱动电极31电连接的透明连接线41的布局空间，从而实现有限的空间内布局数量庞大的透明连接线41，使得第一驱动电极31与第一驱动电路2通过透明连接线41实现一对一连接。此外，在至少一行所述第一驱动电极31所连接的透明连接线41，经由与该行第一驱动电极31相邻的两行走线区04延伸至第二区域A02的情况下，与绿色子像素区域对应的第一驱动电极31所连接透明连接线41，和与红色子像素区域对应的第一驱动电极31以及与蓝色子像素区域对应的第一驱动电极31所连接透明连接线41经不同的走线区延伸至第二区域A02，更便于控制绿色子像素区域、红色子像素区域以及蓝色子像素区域的走线排布，便于改善在子像素需要被点亮时，绿色子像素与红色子像素和蓝色子像素所需要得充电时间不同的问题。
在一些实施例中，请继续参阅图4B和图4C，第一区域A1边缘区域A02。边缘区域A02在所述设定方向上位于至少两个子区域A01和第二区域A2之间。
在一些示例中，请继续参阅图4A～图7，多条连接线40中的至少部分连接线为金属连接线42。其中，金属连接线42可以位于第一源漏电极层201或第二源漏电极层202。
在一些示例中，在边缘区域A02内，至少与绿色子像素区域对应的第一驱动电极31所连接的连接线为金属连接线42。
需要说明的是，在边缘区域A02内，与红色子像素区域对应的第一驱动电极31和与蓝色子像素区域对应的第一驱动电极31所连接的连接线可以为金属连接线42，也可以为透明连接线41，本公开的实施例对此不做限制。
在一些示例中，绿色子像素与红色子像素和蓝色子像素相比，绿色子像素所连接的连接线相对较短。例如，绿色子像素对应的第一驱动电路与红色子像素和蓝色子像素对应的第一驱动电路相比，更靠近第一区域A1。
本实施例中，通过使绿色子像素所连接的连接线为金属连接线42，金属连接线42较短，减少了绿色子像素所连接的连接线中的寄生电容，在相同的时间内，绿色子像素的充电时间更长，充电量更足，更容易被点亮，由此可 以提高显示面板的显示效果。
在一些实施例中，请继续参阅图4A～图7，多条连接线40中的至少部分连接线为金属连接线42。其中，金属连接线42可以位于第一源漏电极层201或第二源漏电极层202。
其中，至少一行所述第一驱动电极31中所连接的连接线40包括金属连接线42。该行所述第一驱动电极31中，与金属连接线42电连接的第一驱动电极31，相对于与透明连接线41电连接的第一驱动电极31，更远离该行所述第一驱动电极41的中心。
在一些示例中，请参阅图6和图7，至少第001行第一驱动电极31所连接的连接线40包括金属连接线42。
示例性的，如图6所示，与金属连接线42电连接的第一驱动电极31，相对于与透明连接线41电连接的第一驱动电极31，更远离该行所述第一驱动电极41的中心。
本实施例中，通过使至少一行所述第一驱动电极31中所连接的连接线40包括金属连接线42，金属连接线42与透明连接线41位于不同的膜层，弥补了该行第一驱动电极31电连接的连接线40的布局空间，增大了与该行第一驱动电极31电连接的连接线40的布局空间，从而实现有限的空间内布局数量庞大的连接线40；而且与金属连接线42电连接的第一驱动电极31，相对于与透明连接线41电连接的第一驱动电极31，更远离该行所述第一驱动电极41的中心，可以保证第一区域A1中心区域的部分具有较高的透光率。
在一些实施例中，一行所述第一驱动电极31中，与金属连接线42电连接的第一驱动电极31的数量不超过第一阈值。其中，第一阈值的取值范围为2～5。例如，与金属连接线42电连接的第一驱动电极31的数量可以为2、3、4、5。
在一些示例中，请继续参阅图7，第001行第一驱动电极31中，与金属连接线42电连接的第一驱动电极31的数量为2。
本实施例中，一行所述第一驱动电极31中，与金属连接线42电连接的第一驱动电极31的数量不超过2～5，既可以弥补该行第一驱动电极31电连接的连接线40的布局空间，增大了与该行第一驱动电极31电连接的连接线40的布局空间，而且，金属连接线42的数量较少，避免同层金属连接线42之间发生短路，降低了结构设计和工艺难度。
在一些实施例中，请继续参阅图5和图6，一行所述第一驱动电极31所连接的连接线40中，金属连接线42的长度小于透明连接线41的长度。
本实施例中，金属连接线42的长度较短，金属连接线42与阵列基板100整个膜层之间的寄生电容较小，可以防止金属连接线42与透明连接线41之间发生寄生电容跳变现象，改善了由于跳变引起的显示画面闪烁现象，使第一区域A1和第二区域A2的显示均一性，提高阵列基板100显示的图像的品质。
在一些实施例中，请参阅图6，越远离一行所述第一驱动电极31的中心的第一驱动电极31所连接的金属连接线42越短。
此时，越远离一行所述第一驱动电极31的中心的第一驱动电极31所连接的金属连接线42越短是指：越远离一行所述第一驱动电极31的中心的第一驱动电极31所连接的金属连接线42的长度越短。金属连接线42的长度，例如指的是：金属连接线42在第一方向X上的尺寸。
在一些实施例中，请继续参阅图6，越远离一行所述第一驱动电极31的中心的第一驱动电极31所连接的透明连接线41越短。
此时，越远离一行所述第一驱动电极31的中心的第一驱动电极31所连接的透明连接线41越短是指：越远离一行所述第一驱动电极31的中心的第一驱动电极31所连接的透明连接线41的长度越短。透明连接线41的长度，例如指的是：透明连接线41在第一方向X上的尺寸。
由此，在连接线40延伸的过程中，便可以提高连接线41中任意相邻两条连接线41所跨过的第一驱动电路21的数量差异的规律，进而便于提高任意相邻两条连接线40中所形成的寄生电容的变化均匀性。
在一些实施例中，一行所述第一驱动电路21与一行所述第一驱动电极31，按照近接近、远接远的方式实现电连接。
示例性的，沿第一方向X且由第二区域A2指向第一区域A1的中心，一行所述第一驱动电极31，包括第1个～第N个第一驱动电极31。位于第一区域A1的一侧，沿第一方向X且由第一区域A1指向第二区域A2，一行所述第一驱动电路21，包括第1个～第N个第一驱动电路21。
可以理解的是，沿第一方向X且由第二区域A2指向第一区域A1的中心情况下，第1个第一驱动电极31最靠近第二区域A2，第N个第一驱动电极31最远离第二区域A2。
沿第一方向X且由第一区域A1指向第二区域A2的情况下，第1个第一驱动电路21最靠近第一区域A1，第N个第一驱动电路21最远离第二区域A2。
例如，第i个第一驱动电极31和第i个第一驱动电路21电连接。其中， i＝1～N。也即，第1个第一驱动电极31可以通过连接线40和第1个第一驱动电路21电连接，第2个第一驱动电极31可以通过连接线40和第2个第一驱动电路21电连接……第N-1个第一驱动电极31可以通过连接线40和第N-1个第一驱动电路21电连接，第N个第一驱动电极31可以通过连接线40和第N个第一驱动电路21电连接。
本公开采用上述设置方式及连接方式，不仅便于对连接线40的走向路径进行规划，提高任意相邻两条连接线40的长度差异的规律性，还可以减小所需使用的连接线40的数量，简化阵列基板100的结构，降低制备形成阵列基板100的难度。
在一些实施例中，请参阅图8和图9。第二区域A2包括第一子区域A21和第二子区域A22。其中，第一子区域A21与第一区域A1邻接。
在一些示例中，请参阅图9，位于第一子区域A21的第二驱动电极32的面积小于位于第二子区域A22的第二驱动电极32的面积，并且第一驱动电极31的面积小于位于第二子区域A22的所述第二驱动电极32的面积。
由此，第一子区域A21和第一区域A1的透光率较第二区域A2更大。
在一些示例中，请参阅图10，第一驱动电极31和位于第一子区域A21的第二驱动电极32分为多个重复单元，一个重复单元包括2k行4h列驱动电极；其中，k、h为大于或等于1的正整数。示例性的，一个重复单元可以包括2行4列驱动电极、4行4列驱动电极或2行8列驱动电极等。
在一些示例中，第一子区域A21和第一区域A1采用相同的显示算法进行显示，第二子区域A22采用与第一子区域A21和第一区域A1不同的显示算法进行显示，保证经显示算法处理后，第二子区域A22与第一子区域A21以及第一区域A1均能够显色准确，避免两个区域采用相同的显示算法进行显示时导致的色偏问题，减弱了第一子区域A21和第一区域A1整体的边缘在显示时的锯齿现象，便于提高阵列基板100的显示均一性，提高阵列基板100显示的图像的品质。
在一些实施例中，请继续参阅图8，第一区域A1和第二区域A2中均具有多个子像素区域P。金属连接线42在行方向上的尺寸大于一个子像素区域P在行方向上的尺寸。
需要说明的是，金属连接线42在行方向上的尺寸，例如指的是：金属连接线42在一行第一驱动电极31的延伸方向(例如图8中所示的第一方向X)上的尺寸。一个子像素区域P在行方向上的尺寸，例如指的是：一个子像素区域P在一行第一驱动电极31的延伸方向(例如图8中所示的第一方向X) 上的尺寸。
在一些示例中，请继续参阅图8，第一子区域A21包括两个子像素区域P。此时，位于第一区域A1的边缘，且靠近第二区域A2的第一驱动电极31所连接的金属连接线42在行方向上的尺寸a大于一个子像素区域P在行方向上的尺寸b。
本实施例中，设置至少包含一个子像素区域P的第一子区域A21，使得第一子区域A21和第一区域A1整体可以采用相同的显示算法进行显示，此时，在第二子区域A22采用与第一子区域A21和第一区域A1不同的显示算法进行显示时，经显示算法处理后，第二子区域A22与第一子区域A21以及第一区域A1均能够显色准确，改善了色偏问题，减弱了第一子区域A21和第一区域A1整体的边缘在显示时的锯齿现象，便于提高阵列基板100的显示均一性，提高阵列基板100显示的图像的品质。
在一些实施例中，请继续参阅图8，第一区域A1中包括光学部件区域A11，金属连接线42与光学部件区域A11之间的最小距离c大于一个子像素区域P在行方向上的尺寸b。
在一些示例中，光学部件区域A11的中心可以和第一区域A1的中心重合。
本实施例中，通过金属连接线42与光学部件区域A11之间的最小距离c大于一个子像素区域P在行方向上的尺寸b，可以避免金属连接线42影响光学部件区域A11的透光率，保证外界光线可以透过光学部件区域A11入射至光学部件，被光学部件采集，并使得光学部件能够正常工作。
在一些实施例中，请继续参阅图8，金属连接线42的位于第一区域A1的部位的长度小于该金属连接线42位于第二区域A2的部位的长度。
示例性的，请参阅图8，以位于第一区域A1的边缘，且靠近第二区域A2的第一驱动电极31为例，该第一驱动电极31所连接的金属连接线42的位于第一区域A1的部位的长度a1小于该金属连接线42位于第二区域A2的部位的长度a2。
本实施例中，通过使金属连接线42位于第一区域A1的部位的长度a1小于该金属连接线42位于第二区域A2的部位的长度a2，可以在通过金属连接线42弥补一行第一驱动电极31电连接的连接线40的布局空间的基础上，保证第一区域A1边缘部分较少的区域的透光率受到金属连接线42的影响，可以保证第一区域A1内的大部分区域具有较高的透光率。
在一些实施例中，请继续参阅图10，图10为第一区域A1和第一子区域 A21的局部示意图。第一区域A1和第一子区域A21整体的边界包括直线段51和阶梯线段52，相邻的两个直线段51之间通过一个所述阶梯线段52连接。其中，阶梯线段52包括依次连接的多个子线段，一个子线段跨过2k行驱动电极或4h列驱动电极。
示例性的，如图10所示，第一区域A1和第一子区域A21两者整体的边界包括两条直线段51和两条阶梯线段52，阶梯线段52包括第一类子线段521和第二类子线段522。
其中，第一类子线段521平行于第一方向X；第一类子线段521跨过4h列驱动电极。第二类子线段522平行于第二方向Y；第二类子线段522跨过2k行驱动电极。
由此，第一区域A1和第一子区域A21的边界的驱动电极可以采用相同的显示算法进行显示，避免位于第一区域A1的边界的第一驱动电极31和位于第一子区域A21的第二驱动电极32，采用不同的显示算法进行显示时导致的色偏问题，消除了第一子区域A21和第一区域A1的边缘显示时的锯齿现象，便于提高阵列基板100的显示均一性，提高阵列基板100显示的图像的品质。
在一些实施例中，请继续参阅图9，位于第一子区域A21的至少一个所述第二驱动电极32的主体形状与至少一个第一驱动电极31的主体形状相同。示例性的，第一驱动电极的主体形状为椭圆形或圆形；位于第一子区域A21的至少一个所述第二驱动电极32的主体形状为椭圆形或圆形。
本实施例中，位于第一子区域A21的至少一个所述第二驱动电极32的主体形状与至少一个第一驱动电极31的主体形状相同，且同为椭圆形或圆形，可以使第一区域A1和第一子区域A21整体的边界更平滑、更柔和，在将阵列基板100应用至显示面板1000，显示面板1000显示图像时，可以减弱第一子区域A21和第一区域A1的边缘的锯齿现象，便于提高显示面板1000的显示均一性，提高显示面板1000显示的图像的品质。
在一些实施例中，请继续参阅图9，位于第一子区域A21的至少一个第二驱动电极32的面积与至少一个第一驱动电极31的面积相等。
本实施例中，位于第一子区域A21的至少一个第二驱动电极32的面积与至少一个第一驱动电极31的面积相等，均小于第二子区域A22的第二驱动电极32的面积，不仅可以简化制作工艺，而且进一步降低了第一区域A1的衍射，提高了第一区域A1的光透光率。
本公开的一些实施例提供了一种显示面板1000。请参阅图11，该显示面 板1000包括：如上述一些实施例中的任一项所述的阵列基板100、发光功能层110、公共电极层120以及封装层130。
其中，发光功能层110位于阵列基板100的一侧。
示例性的，发光功能层110可以包括发光层(electroluminescent，简称EL)。在另一些示例中，发光功能层110除包括发光层外，还包括电子传输层(election transporting layer，简称ETL)、电子注入层(election injection layer，简称EIL)、空穴传输层(hole transporting layer，简称HTL)以及空穴注入层(hole injection layer，简称HIL)中的一层或多层。在显示面板1000为有机电致发光显示基板的情况下，发光层为有机发光层。在显示面板1000为量子点电致发光显示基板的情况下，发光层为量子点发光层。
公共电极层120位于发光功能层110远离阵列基板100的一侧。
示例性的，第一驱动电极31和第二驱动电极32为可以反射阳极，公共电极层120可以包括多个透射阴极。其中，透射阴极可选用Mg/Ag等合金或金属/无机复合材料。
封装层130位于公共电极层120远离阵列基板100的一侧。
示例性的，封装层130可以为封装薄膜(Thin Film Encapsulation，简称TFE)，也可以为封装基板。
本公开的一些实施例所提供的显示面板1000所能实现的有益效果与上述一些实施例中所提供的阵列基板100所能实现的有益效果相同，此处不再赘述。
本公开的一些实施例提供了一种显示装置2000。如图12所示，该显示装置2000包括：如上述一些实施例中所述的显示面板1000以及设置在该显示面板100的非出光侧的光学元件200。其中，光学元件200在显示面板100上的正投影位于第一区域A1。
在一些示例中，上述光学元件200可以包括感光器件。示例性的，该感光器件可以包括图像采集器(例如摄像头)或红外接收器等。
示例性的，该感光器件包括摄像头时，该摄像头的边界可以与第一区域A1的边界重合，或者位于第一区域A1的边界内侧。该摄像头的镜头的中心可以和上述第一区域A1和第一子区域A21整体的中心(例如图9和图10所示的第一区域A1和第一子区域A21整体的中心O)重合，由此可以进一步提高了摄像头通过第一区域A1获取图像的成像效果，以确保摄像头的高质量的摄像或摄影。
此处，光学元件200的设置数量可以根据实际需要选择设置。
示例性的，上述显示装置2000还可以包括框架、源极驱动芯片、FPC(Flexible Printed Circuit，柔性线路板)、PCB(Printed Circuit Board，印刷线路板)或其他电子配件等。
本公开提供的述显示装置2000所能实现的有益效果，与上述技术方案提供的显示面板1000所能达到的有益效果相同，在此不做赘述。
上述显示装置2000可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(Personal Digital Assistant，简称PDA)、手持式或便携式计算机、全球定位系统(Global Positioning System，简称GPS)接收器/导航器、相机、动态图像专家组(Moving Picture Experts Group 4，简称MP4)视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (28)

  1. 一种阵列基板，具有第一区域和第二区域，所述第二区域包围至少部分所述第一区域；所述阵列基板包括：
    多行第一驱动电极，位于所述第一区域；
    多条连接线，一条连接线与一行第一驱动电极中的一个第一驱动电极电连接；
    其中，至少一行所述第一驱动电极所连接的连接线经由至少一行走线区延伸至所述第二区域，一行走线区与一行第一驱动电极相邻；
    至少一行所述第一驱动电极所连接的连接线位于不同层。
  2. 根据权利要求1所述的阵列基板，其中，所述多条连接线中的至少部分连接线为透明连接线；
    至少一行所述第一驱动电极所连接的透明连接线经由至少两行所述走线区延伸至所述第二区域；并且，至少一行所述第一驱动电极所连接的透明连接线位于不同层。
  3. 根据权利要求2所述的阵列基板，其中，
    至少一行所述第一驱动电极所连接的透明连接线包括：第一类透明连接线和第二类透明连接线；该行所述第一驱动电极中，与所述第一类透明连接线电连接的所述第一驱动电极，相对于与所述第二类透明连接线电连接的所述第一驱动电极，更靠近该行所述第一驱动电极的中心；
    其中，所述第一类透明连接线的数量大于所述第二类透明连接线的数量，且所述第一类透明连接线与第二类透明连接线位于不同层。
  4. 根据权利要求3所述的阵列基板，其中，
    至少一行所述第一驱动电极所连接的所述第一类透明连接线，经由位于该行所述第一驱动电极同一侧且最靠近该行所述第一驱动电极的N1行所述走线区延伸至所述第二区域，N1为大于或等于2的正整数。
  5. 根据权利要求3或4所述的阵列基板，其中，以相邻的N2行所述第一驱动电极为一个周期；N2为大于或等于2的正整数；
    在同一周期内，各行所述第一驱动电极所连接的所述第一类透明连接线位于不同层。
  6. 根据权利要求5所述的阵列基板，其中，至少一行所述第一驱动电极所连接的至少部分所述第二类透明连接线，和与该行所述第一驱动电极处于同一周期内的任意一行所述第一驱动电极所连接的所述第一类透明连接线同层设置，且经由与该行第一驱动电极处于同周期内的该行第一驱动电极所连 接的所述第一类透明连接线所在的所述走线区延伸至所述第二区域。
  7. 根据权利要求5或6所述的阵列基板，其中，至少一行所述第一驱动电极所连接的至少部分所述第二类透明连接线，和与该行所述第一驱动电极处于不同周期内的任意一行所述第一驱动电极所连接的所述第一类透明连接线同层设置，且经由与该行第一驱动电极处于不同周期内的该行第一驱动电极所连接的所述第一类透明连接线所在的所述走线区延伸至所述第二区域。
  8. 根据权利要求1所述的阵列基板，其中，所述多条连接线中的至少部分连接线为透明连接线；
    所述第一区域包括沿设定方向依次排布的至少两个子区域，所述设定方向由一行所述第一驱动电极的中心指向该行所述第一驱动电极的一端；
    位于不同的子区域内的所述第一驱动电极所连接的所述透明连接线分别位于不同层。
  9. 根据权利要求8所述的阵列基板，其中，
    所述至少两个子区域包括沿所述设定方向依次排布的第一个子区域、第二个子区域、第三个子区域。
  10. 根据权利要求8或9所述的阵列基板，其中，
    至少一行所述第一驱动电极中，位于不同子区域中的所述第一驱动电极的数量相等。
  11. 根据权利要求8～10中任一项所述的阵列基板，其中，
    至少一行所述第一驱动电极所连接的透明连接线，经由与该行第一驱动电极相邻的一行或两行所述走线区延伸至所述第二区域。
  12. 根据权利要求8～11中任一项所述的阵列基板，其中，所述第一区域还包括边缘区域，所述边缘区域在所述设定方向上位于所述至少两个子区域与所述第二区域之间；
    所述多条连接线中的至少部分连接线为金属连接线；
    在所述边缘区域内，至少与绿色子像素区域对应的第一驱动电极所连接的所述连接线为金属连接线。
  13. 根据权利要求2～11中任一项所述的阵列基板，其中，所述多条连接线中的至少部分连接线为金属连接线；
    至少一行所述第一驱动电极中所连接的所述连接线还包括所述金属连接线；
    该行所述第一驱动电极中，与所述金属连接线电连接的所述第一驱动电极，相对于与所述透明连接线电连接的所述第一驱动电极，更远离该行所述 第一驱动电极的中心。
  14. 根据权利要求12或13所述的阵列基板，其中，
    一行所述第一驱动电极中，与所述金属连接线电连接的所述第一驱动电极的数量不超过第一阈值，所述第一阈值的取值范围为2～5。
  15. 根据权利要求12～14中任一项所述的阵列基板，还包括：
    多行第一驱动电路，位于所述第二区域；一行所述第一驱动电极中的一个所述第一驱动电极通过一条所述连接线与一行第一驱动电路中的一个第一驱动电路电连接；
    其中，一行所述第一驱动电极所连接的所述连接线中，所述金属连接线的长度小于所述透明连接线的长度。
  16. 根据权利要求15所述的阵列基板，其中，
    越远离一行所述第一驱动电极的中心的所述第一驱动电极所连接的所述金属连接线越短；和/或，越远离一行所述第一驱动电极的中心的所述第一驱动电极所连接的所述透明连接线越短。
  17. 根据权利要求15或16所述的阵列基板，还包括：
    一行所述第一驱动电路与一行所述第一驱动电极，按照近接近、远接远的方式实现电连接。
  18. 根据权利要求15～17中任一项所述的阵列基板，还包括：
    多行第二驱动电极，位于所述第二区域；
    多行第二驱动电路，位于所述第二区域；一行第二驱动电路中的一个第二驱动电路与一行第二驱动电极中的一个第二驱动电极电连接；
    其中，一行所述第一驱动电路分散布置于一行所述第二驱动电路中的多个所述第二驱动电路之间。
  19. 根据权利要求18所述的阵列基板，其中，所述第二区域包括第一子区域和第二子区域，所述第一子区域与所述第一区域邻接；
    其中，位于所述第一子区域的所述第二驱动电极的面积小于位于所述第二子区域的所述第二驱动电极的面积，并且所述第一驱动电极的面积小于位于所述第二子区域的所述第二驱动电极的面积；
    所有所述第一驱动电极和位于所述第一子区域的所有所述第二驱动电极分为多个重复单元，一个重复单元包括2k行4h列驱动电极；其中，k、h为大于或等于1的正整数。
  20. 根据权利要求19所述的阵列基板，其中，
    所述第一区域和所述第一子区域两者整体的边界包括直线段和阶梯线 段，相邻的两个直线段之间通过一个所述阶梯线段连接；
    其中，所述阶梯线段包括依次连接的多个子线段，一个子线段跨过2k行驱动电极或4h列驱动电极。
  21. 根据权利要求19或20所述的阵列基板，其中，
    位于所述第一子区域的至少一个所述第二驱动电极的主体形状与至少一个所述第一驱动电极的主体形状相同；和/或，
    位于所述第一子区域的至少一个所述第二驱动电极的面积与至少一个所述第一驱动电极的面积相等。
  22. 根据权利要求19～21中任一项所述的阵列基板，其中，
    所述第一驱动电极的主体形状为椭圆形或圆形；
    位于所述第一子区域的所述第二驱动电极的主体形状为椭圆形或圆形。
  23. 根据权利要求18～22中任一项所述的阵列基板，还包括：
    衬底；
    位于所述衬底一侧的驱动电路层，所述第一驱动电路和所述第二驱动电路均位于所述驱动电路层中；所述驱动电路层包括依次远离所述衬底的第一源漏电极层和第二源漏电极层；
    位于所述驱动电路层远离所述衬底一侧的至少两层透明导电层；
    其中，所述透明连接线位于所述透明导电层中，所述金属连接线位于所述第一源漏电极层或所述第二源漏电极层中。
  24. 根据权利要求12～23中任一项所述的阵列基板，其中，所述第一区域和所述第二区域中均具有多个子像素区域；
    所述金属连接线在行方向上的尺寸大于一个所述子像素区域在行方向上的尺寸。
  25. 根据权利要求24所述的阵列基板，其中，所述第一区域中包括光学部件区域；
    所述金属连接线与所述光学部件区域之间的最小距离大于一个所述子像素区域在所述行方向上的尺寸。
  26. 根据权利要求12～23中任一项所述的阵列基板，其中，
    所述金属连接线的位于所述第一区域的部位的长度小于所述金属连接线的位于所述第二区域的部位的长度。
  27. 一种显示面板，包括：
    如权利要求1～26中任一项所述的阵列基板；
    位于所述阵列基板一侧的发光功能层；
    位于所述发光功能层远离所述阵列基板一侧的公共电极层；以及，
    位于所述公共电极层远离所述阵列基板一侧的封装层。
  28. 一种显示装置，包括：
    权利要求27所述的显示面板；
    光学部件，所述光学部件在所述显示面板上的正投影位于所述第一区域内。
PCT/CN2022/075077 2022-01-29 2022-01-29 阵列基板、显示面板及显示装置 WO2023142071A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN202280000102.6A CN116897430A (zh) 2022-01-29 2022-01-29 阵列基板、显示面板及显示装置
PCT/CN2022/075077 WO2023142071A1 (zh) 2022-01-29 2022-01-29 阵列基板、显示面板及显示装置
PCT/CN2022/092866 WO2023142307A1 (zh) 2022-01-29 2022-05-13 显示面板及显示装置
CN202280001208.8A CN117280894A (zh) 2022-01-29 2022-05-13 显示面板及显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/075077 WO2023142071A1 (zh) 2022-01-29 2022-01-29 阵列基板、显示面板及显示装置

Publications (1)

Publication Number Publication Date
WO2023142071A1 true WO2023142071A1 (zh) 2023-08-03

Family

ID=87470207

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/CN2022/075077 WO2023142071A1 (zh) 2022-01-29 2022-01-29 阵列基板、显示面板及显示装置
PCT/CN2022/092866 WO2023142307A1 (zh) 2022-01-29 2022-05-13 显示面板及显示装置

Family Applications After (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/092866 WO2023142307A1 (zh) 2022-01-29 2022-05-13 显示面板及显示装置

Country Status (2)

Country Link
CN (2) CN116897430A (zh)
WO (2) WO2023142071A1 (zh)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110890026A (zh) * 2019-12-05 2020-03-17 昆山国显光电有限公司 显示面板及显示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109116644A (zh) * 2018-08-29 2019-01-01 上海天马微电子有限公司 显示面板和显示装置
CN114550606A (zh) * 2019-12-02 2022-05-27 武汉天马微电子有限公司 一种显示面板和显示装置
CN112038373B (zh) * 2020-08-28 2022-08-23 武汉天马微电子有限公司 一种显示面板及显示装置
CN112151592B (zh) * 2020-09-30 2022-10-04 武汉天马微电子有限公司 显示面板及显示装置
CN116153240A (zh) * 2021-06-07 2023-05-23 Oppo广东移动通信有限公司 显示面板和显示设备
CN113571570A (zh) * 2021-07-29 2021-10-29 合肥维信诺科技有限公司 显示面板及显示装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110890026A (zh) * 2019-12-05 2020-03-17 昆山国显光电有限公司 显示面板及显示装置

Also Published As

Publication number Publication date
CN116897430A (zh) 2023-10-17
CN117280894A (zh) 2023-12-22
WO2023142307A1 (zh) 2023-08-03

Similar Documents

Publication Publication Date Title
US11322567B2 (en) Display panel, manufacture method thereof and display apparatus
US11244609B2 (en) Display device and OLED display panel thereof
US11847964B2 (en) Display panel and display device
US11900885B2 (en) Display panel and display apparatus
US20230098206A1 (en) Display panel and method for driving the same, and display apparatus
CN114822250B (zh) 一种显示面板及显示装置
CN114784073A (zh) 显示面板和显示装置
CN218831229U (zh) 显示面板及显示装置
WO2023142071A1 (zh) 阵列基板、显示面板及显示装置
US20240147785A1 (en) Display Substrate and Preparation Method Therefor, and Display Apparatus
CN114843288A (zh) 显示基板及显示装置
CN219592985U (zh) 显示基板及显示装置
WO2023226023A1 (zh) 显示面板及显示装置
EP4202909A1 (en) Display substrate and display apparatus
WO2023137766A1 (zh) 显示面板、显示模组及显示装置
WO2023060520A1 (zh) 显示面板及显示装置
WO2023165016A1 (zh) 显示面板及显示装置
WO2023130382A1 (zh) 显示基板及显示装置
US20240169925A1 (en) Display panel and display device
WO2024021099A1 (zh) 显示面板及显示装置
WO2022205285A1 (zh) 显示面板及显示装置
CN115605050A (zh) 显示基板和显示装置
CN117812955A (zh) 显示基板及显示装置
CN116682365A (zh) 显示基板及显示装置
CN117529151A (zh) 显示面板及显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 202280000102.6

Country of ref document: CN