WO2023060520A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2023060520A1
WO2023060520A1 PCT/CN2021/123928 CN2021123928W WO2023060520A1 WO 2023060520 A1 WO2023060520 A1 WO 2023060520A1 CN 2021123928 W CN2021123928 W CN 2021123928W WO 2023060520 A1 WO2023060520 A1 WO 2023060520A1
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WO
WIPO (PCT)
Prior art keywords
pixel
type
substrate
opening
openings
Prior art date
Application number
PCT/CN2021/123928
Other languages
English (en)
French (fr)
Inventor
陈家兴
张波
刘彪
牛佐吉
许杨
龙祎璇
尚庭华
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/123928 priority Critical patent/WO2023060520A1/zh
Priority to EP21960256.2A priority patent/EP4350735A1/en
Priority to CN202180002922.4A priority patent/CN116686411A/zh
Publication of WO2023060520A1 publication Critical patent/WO2023060520A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • the present disclosure relates to the field of display technology, for example, to a display panel and a display device.
  • OLED display panels have gradually become one of the mainstream in the display field due to their low power consumption, high color saturation, wide viewing angle, thin thickness, and flexibility. one.
  • a display panel in one aspect, includes a substrate, a circuit structure layer, a first electrode layer and a pixel defining layer.
  • the circuit structure layer is located on one side of the substrate, and the circuit structure layer includes a plurality of pixel drive circuits; the plurality of pixel drive circuits are arranged along a first direction to form a row of pixel drive circuits, and the plurality of pixel drive circuits
  • the circuit rows are arranged in sequence along the second direction; the first direction and the second direction intersect.
  • the first electrode layer is located on a side of the circuit structure layer away from the substrate, and the first electrode layer includes a plurality of first electrodes; one first electrode is electrically connected to a pixel driving circuit.
  • the pixel defining layer is located on a side of the first electrode layer away from the substrate, and the pixel defining layer has a plurality of pixel openings; one pixel opening exposes at least part of a first electrode.
  • the pixel driving circuit includes a driving transistor and a data compensation transistor.
  • the orthographic projection of at least one first electrode on the substrate at least partially overlaps the orthographic projection of the gate of the data compensation transistor in the pixel driving circuit corresponding to the first electrode on the substrate, and at the same time overlaps with Orthographic projections of gates of data compensation transistors in at least one pixel drive circuit adjacent to the pixel drive circuit corresponding to the first electrode on the substrate at least partially overlap; the at least one first electrode corresponds to The orthographic projection of the pixel opening on the substrate is separated from the orthographic projection of the gate of the data compensation transistor in the pixel driving circuit corresponding to the first electrode on the substrate.
  • the orthographic projection of the data compensation transistor corresponding to the first electrode on the substrate has the first virtual straight line extending along the first direction in the first direction.
  • An overlapping portion; the orthographic projection of the data compensation transistor in the pixel driving circuit adjacent to the pixel driving circuit corresponding to the first electrode on the substrate has a second overlapping portion with the first imaginary straight line;
  • a distance between the first overlapping portion and the second overlapping portion in the first direction is greater than a pixel opening corresponding to the first overlapping portion in the first direction.
  • the plurality of pixel openings are arranged in multiple rows and multiple columns; two adjacent rows of pixel openings are staggered from each other along the first direction; among the two adjacent rows of pixel openings, one row of pixel openings includes The first type of pixel openings and the second type of pixel openings are alternately arranged in the first direction, and the other row of pixel openings includes the third type of pixel openings arranged in sequence along the first direction; in two adjacent columns of pixel openings, one column of pixel openings
  • the openings include first-type pixel openings and second-type pixel openings arranged alternately along the second direction, and the other row of pixel openings includes third-type pixel openings sequentially arranged along the second direction.
  • the opening area of the first type of pixel opening is smaller than the opening area of the second type of pixel opening
  • the opening area of the first type of pixel opening is larger than the opening area of the third type of pixel opening.
  • any first-type pixel opening is adjacent to the first-type pixel opening The distance between the two second-type pixel openings is equal.
  • any first-type pixel opening and two second-type pixel openings adjacent to the first-type pixel opening The distances between the pixel openings are not equal.
  • the pixel openings of the first type and the pixel openings of the second type adjacent to one column of the pixel openings are the same as the pixel openings of the first type and the pixel openings of the adjacent column of the pixel openings adjacent to each other.
  • the geometric centers of the four pixel openings of the second type are sequentially connected to form a virtual trapezoid.
  • centers of the first type of pixel openings and centers of the second type of pixel openings have an interval in the second direction.
  • the pitch is less than or equal to half the size of the first-type pixel opening in the second direction.
  • the orthographic projection of the first electrode corresponding to the first type of pixel opening on the substrate, and the gate of the data compensation transistor in the pixel driving circuit corresponding to the first electrode The orthographic projections on the substrate at least partially overlap, and at the same time, the orthographic projections of the gate of the data compensation transistor in at least one pixel driving circuit adjacent to the pixel driving circuit corresponding to the first electrode on the substrate at least partially overlap; and/or, the orthographic projection of the first electrode corresponding to the second-type pixel opening on the substrate, and the gate of the data compensation transistor in the pixel driving circuit corresponding to the first electrode
  • the orthographic projections of the electrodes on the substrate at least partially overlap, and at the same time, the gate of the data compensation transistor in at least one pixel driving circuit adjacent to the pixel driving circuit corresponding to the first electrode is on the substrate
  • the orthographic projections of are at least partially overlapping.
  • the orthographic projection of the first-type pixel opening on the substrate and the gate of the data compensation transistor in the pixel driving circuit corresponding to the first-type pixel opening on the substrate Orthographic separation; and/or, the orthographic projection of the third type of pixel opening on the substrate and the gate of the data compensation transistor in the pixel driving circuit corresponding to the third type of pixel opening are on the substrate Orthographic separation on .
  • the pixel openings of the first type and the pixel openings of the third type are alternately arranged to form a first group of pixel openings along the third direction, and the pixel openings of the second type and the pixel openings of the third type are arranged along the
  • the third direction is alternately arranged to form a second group of pixel openings, the first group of pixel openings and the second group of pixel openings are alternately arranged in a fourth direction; the third direction intersects with the fourth direction.
  • the orthographic projection of the first electrode corresponding to the first-type pixel opening on the substrate, and a third-type pixel opening adjacent to the first-type pixel opening Orthographic projections of the gates of the data compensation transistors in the pixel driving circuit corresponding to the pixel openings on the substrate at least partially overlap;
  • the orthographic projection of the first electrode on the substrate, and at least part of the orthographic projection of the gate of the data compensation transistor corresponding to a third-type pixel opening adjacent to the second-type pixel opening on the substrate overlap.
  • the orthographic projections on the substrate of the two first electrodes corresponding to the adjacent first-type pixel openings and the second-type pixel openings are respectively and Orthographic projections of gates of data compensation transistors corresponding to two third-type pixel openings on the same side of the first-type pixel opening and the second-type pixel opening on the substrate at least partially overlap .
  • the display panel has a display area; the plurality of pixel openings closest to the boundary of the display area include at least one row of the first type of pixel openings and the second pixel openings arranged alternately along the first direction. Two types of pixel openings, and/or at least one column of the first type of pixel openings and the second type of pixel openings arranged alternately along the second direction.
  • the first type of pixel opening is configured to define an effective light emitting area of the first color light
  • the second type of pixel opening is configured to define an effective light emitting area of the second color light
  • the third The pixel opening is configured to define an effective light-emitting area for light of the third color.
  • the light of the first color is red light
  • the light of the second color is blue light
  • the light of the third color is green light.
  • the circuit structure layer includes an active layer, a first gate layer, a second gate layer, and a source-drain electrode layer that are sequentially away from the substrate.
  • the display panel further includes a conductive connection layer located between the circuit structure layer and the first electrode layer.
  • the display panel includes a plurality of reset signal lines for supplying reset signals to the first electrodes.
  • the plurality of reset signal lines include: a first reset signal line located on the second gate layer and extending along the first direction; A second reset signal line extending in two directions.
  • Orthographic projections of the first reset signal line and the second reset signal line on the substrate overlap, and at the overlapping position, the first reset signal line and the second reset signal line pass through the via hole electrical connection; when the first reset signal line is located at the second gate layer and the second reset signal line is located at the source-drain electrode layer, the second reset signal line and the active layer pass through Via connection.
  • the display panel further includes a plurality of power signal lines.
  • the plurality of power signal lines include: a first power signal line located at the source-drain electrode layer and extending along the second direction, and a second power signal line located at the conductive connection layer and extending along the second direction Wire.
  • the first power signal line is electrically connected to the second power signal line, the orthographic projections of the first power signal line and the second power signal line on the substrate overlap, and at least one pixel opening is in The orthographic projection on the substrate is within the range of the orthographic projection of the second power signal line on the substrate.
  • the second power signal line has a plurality of protrusions, and the orthographic projection of a protrusion on the substrate is the same as the orthographic projection of a pixel opening corresponding to a first electrode on the substrate. overlap at least partially.
  • the display panel further includes: a plurality of data signal lines located in the conductive connection layer and extending along the second direction, the plurality of data signal lines are sequentially along the first direction arrangement.
  • the first type of pixel opening, the second type of pixel opening and the third type of pixel opening are configured to be arranged in at least one of the following ways: the orthographic projection of the first type of pixel opening on the substrate It is located between the orthographic projections of two adjacent data signal lines on the substrate; or, the orthographic projection of the second type pixel opening on the substrate is located between the two adjacent data signal lines.
  • the orthographic projections of two adjacent data signal lines on the substrate overlap partially with the orthographic projections of the second-type pixel opening on the substrate,
  • the orthographic projections of the two adjacent data signal lines on the substrate have approximately the same area as the two overlapping parts of the orthographic projections of the second-type pixel openings on the substrate; or, the The orthographic projection of the pixel opening of the third type on the substrate is located between the orthographic projections of two adjacent data signal lines on the substrate.
  • the first type of pixel opening, the second type of pixel opening and the third type of pixel opening are configured to be set in at least one of the following ways:
  • the bisecting plane of the line is a symmetrical plane, and the first type of pixel opening is mirror-symmetrical; or, taking the bisecting plane of the two adjacent data signal lines as a symmetrical plane, the second type of pixel opening is mirror-symmetrical; Or, taking the bisecting plane of the two adjacent data signal lines as a symmetrical plane, the third type of pixel openings are mirror-symmetrical.
  • the display panel further includes: a first planar layer, a conductive connection layer and a second planar layer located between the circuit structure layer and the first electrode layer and sequentially away from the substrate.
  • the first planar layer has a plurality of first via holes
  • the conductive connection layer includes a plurality of conductive parts
  • the second planar layer has a plurality of second via holes.
  • the display panel has a plurality of sub-pixel regions, and in the sub-pixel region: the first electrode is electrically connected to the conductive part through the second via hole, and the conductive part is electrically connected to the pixel driving circuit through the first via hole; the first via hole
  • the minimum distance between the orthographic projection of the edge of the second via hole on the substrate and the orthographic projection of the pixel opening on the substrate is smaller than the orthographic projection and the orthographic projection of the edge of the second via hole on the substrate The minimum distance between orthographic projections of the pixel openings on the substrate.
  • the first vias corresponding to each pixel opening are located on a straight line extending along the first direction, and the second vias corresponding to each pixel opening are located along a straight line extending along the first direction.
  • the first direction is alternately located on two sides of the same straight line extending along the first direction.
  • the first vias corresponding to the pixel openings are respectively located at the same positions in the corresponding pixel driving circuits; the first vias corresponding to the first type of pixel openings The second via holes and the second via holes corresponding to the second type of pixel openings are respectively located at the same positions in the corresponding pixel driving circuits.
  • the positions of the first via holes corresponding to the pixel openings in the second direction are different;
  • the light emission control signal line in the layer and extending along the first direction, the intersection of the orthographic projection of each of the first via holes on the substrate and the orthographic projection of the light emission control signal line on the substrate are approximately equal.
  • the first via hole corresponding to each pixel opening and the second via hole corresponding to each pixel opening are located on the same straight line extending along the second direction.
  • a display device in another aspect, includes: the display panel as described in any one of the above embodiments.
  • FIG. 1 is a structural diagram of a display device provided by some embodiments of the present disclosure
  • FIG. 2 is a structural diagram of a display panel provided by some embodiments of the present disclosure.
  • Fig. 3 is a kind of sectional structural diagram of A-A ' place among Fig. 2;
  • FIG. 4 is a structural diagram of another display panel provided by some embodiments of the present disclosure.
  • FIG. 5A is a structural diagram of another display panel provided by some embodiments of the present disclosure.
  • FIG. 5B is a positional relationship diagram of a source-drain metal layer, a conductive connection layer, and a first electrode layer at a sub-pixel area provided by some embodiments of the present disclosure
  • FIG. 6A is a positional relationship diagram between the active layer and the first gate layer at a sub-pixel region in FIG. 5A;
  • FIG. 6B is another positional relationship diagram between the active layer and the first gate layer in a sub-pixel region provided by some embodiments of the present disclosure
  • FIG. 6C is another diagram of the positional relationship between the active layer and the first gate layer in a sub-pixel region provided by some embodiments of the present disclosure.
  • FIG. 6D is a positional relationship diagram between the active layer and the first gate layer at the two sub-pixel regions in FIG. 5A;
  • FIG. 7 is an equivalent circuit diagram at a sub-pixel region in FIG. 5A;
  • FIG. 8A is a positional diagram of an active layer, a first gate layer, and a second gate layer at a sub-pixel region in FIG. 5A;
  • FIG. 8B is a positional relationship diagram of the active layer, the first gate layer, the second gate layer, the source-drain metal layer and the conductive connection layer in a sub-pixel area provided by some embodiments of the present disclosure
  • FIG. 8C is another positional relationship diagram of the active layer, the first gate layer, the second gate layer, the source-drain metal layer, and the conductive connection layer at a sub-pixel area provided by some embodiments of the present disclosure
  • FIG. 9 is a positional diagram of the active layer, the first gate layer, the second gate layer, and the source-drain metal layer in FIG. 5A;
  • FIG. 10 is a positional diagram of the active layer, the first gate layer, the second gate layer, the source-drain metal layer and the conductive connection layer in FIG. 5A;
  • Fig. 11 is an arrangement diagram of a pixel opening provided by some embodiments of the present disclosure.
  • FIG. 12 is an arrangement diagram of another pixel opening provided by some embodiments of the present disclosure.
  • Fig. 13 is another arrangement diagram of pixel openings provided by some embodiments of the present disclosure.
  • Fig. 14 is another arrangement diagram of pixel openings provided by some embodiments of the present disclosure.
  • Fig. 15 is another arrangement diagram of pixel openings provided by some embodiments of the present disclosure.
  • Fig. 16 is another arrangement diagram of pixel openings provided by some embodiments of the present disclosure.
  • Fig. 17 is a structural diagram of another display panel provided by some embodiments of the present disclosure.
  • Fig. 18 is another kind of cross-sectional structure diagram at A-A' place in Fig. 2;
  • FIG. 19A is a positional relationship diagram of a pixel opening, a first via hole, and a second via hole provided by some embodiments of the present disclosure
  • FIG. 19B is another positional relationship diagram of a pixel opening, a first via hole, and a second via hole provided by some embodiments of the present disclosure.
  • FIG. 19C is another positional relationship diagram of the pixel opening, the first via hole and the second via hole provided by some embodiments of the present disclosure.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality” means two or more.
  • the expressions “coupled” and “connected” and their derivatives may be used.
  • the term “connected” may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more elements are in direct physical or electrical contact.
  • the terms “coupled” or “communicatively coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited by the context herein.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, A and B A combination of A and C, a combination of B and C, and a combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • parallel As used herein, “parallel”, “perpendicular”, and “same” include the stated situation and the situation similar to the stated situation, and the range of the similar situation is within the acceptable deviation range, wherein the The acceptable deviation ranges are as determined by one of ordinary skill in the art taking into account the measurement in question and errors associated with measurement of the particular quantity (ie, limitations of the measurement system).
  • “parallel” includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; Deviation within 5°.
  • “Same” includes absolutely the same and approximately the same, wherein approximately the same within an acceptable tolerance range, for example, the difference between the two that can be the same is less than or equal to 5% of either of them.
  • Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations in shape from the drawings as a result, for example, of manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • the display device 1000 includes a display panel 100 .
  • the display device 1000 includes various types, such as an organic light-emitting diode (Organic Light-Emitting Diode, referred to as OLED) display device, a quantum dot light-emitting diode (Quantum Dot Light Emitting Diodes, referred to as QLED) display device. Or light emitting diode (Light Emitting-Diodes, referred to as LED) display device.
  • OLED Organic Light-Emitting Diode
  • QLED Quantum Dot Light Emitting Diodes
  • LED light emitting diode
  • the organic light-emitting diode (Organic Light-Emitting Diode, referred to as OLED) display device may include, for example, an active matrix organic light-emitting diode (Active Matrix/Organic Light-Emitting Diode, referred to as AMOLED) display device.
  • OLED Organic Light-Emitting Diode
  • AMOLED Active Matrix/Organic Light-Emitting Diode
  • the above-mentioned display device 1000 also includes various product forms, for example, it can be any device that displays no matter whether it is moving (eg, video) or fixed (eg, still image), and regardless of text or image. More specifically, the above-mentioned display device 1000 can be set in or associated with various electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs) , handheld or portable computers, GPS receivers/navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (such as odometer display), navigator, cockpit controller and/or display, camera view display (such as may be a rear view camera display in a vehicle), electronic photographs, electronic billboards or signage, projectors, architectural structures, Packaging and aesthetics (such as a display that could be an image of a piece of jewelry), etc.
  • PDAs personal data assistants
  • handheld or portable computers GPS receivers/navi
  • some embodiments of the present disclosure provide a display panel 100 , and the display panel 100 can be applied in the above-mentioned display device 1000 .
  • the display panel 100 can also be applied to other devices.
  • the display panel 100 has a display area A inside the dotted box and a peripheral area B outside the dotted box. Wherein, the portion of the display panel 100 located in the display area A can display images.
  • the present disclosure does not limit the setting location of the peripheral area B.
  • the peripheral area B may be located on one side, two sides or three sides of the display area A, etc.
  • FIG. the peripheral area B may also surround the display area A in a circle.
  • the display panel 100 may be of various types, for example, it may be an OLED display panel, a QLED display panel, or an LED display panel. Wherein, the OLED display panel may include an AMOLED display panel, for example.
  • the display panel 100 has a plurality of sub-pixel regions P. As shown in FIG. 2 , please continue to refer to FIG. 2 , the display panel 100 has a plurality of sub-pixel regions P. As shown in FIG. 2
  • a plurality of sub-pixel regions P are located in the display area A. As shown in FIG.
  • the display panel 100 includes a substrate 1 .
  • substrate 1 may be a rigid substrate.
  • the rigid substrate may be, for example, a glass substrate or a PMMA (Polymethyl methacrylate, polymethyl methacrylate) substrate or the like.
  • the substrate 1 may be a flexible substrate.
  • the flexible substrate can be, for example, a PET (Polyethylene terephthalate, polyethylene terephthalate) substrate, a PI (Polyimide, polyimide) substrate or a PEN (Polyethylene naphthalate two formic acid glycol ester, polyethylene naphthalate Ethylene glycol formate) substrate, etc.
  • the display panel 100 further includes a circuit structure layer 2 and a first electrode layer 3 located on one side of the substrate 1 and in turn away from the substrate 1 .
  • the circuit structure layer 2 includes a plurality of pixel driving circuits 21
  • the first electrode layer 3 includes a plurality of first electrodes 31
  • one first electrode 31 is electrically connected to one pixel driving circuit 21 .
  • the first electrode 31 is directly electrically connected to the pixel driving circuit 21 .
  • the display panel 100 further includes a planar layer located between the circuit structure layer 2 and the first electrode layer 3, and the planar layer has a plurality of via holes; a first electrode 31 is connected to a pixel driver through a via hole The circuit 21 is electrically connected.
  • the display panel 100 further includes a conductive connection layer 8 located between the circuit structure layer 2 and the first electrode layer 3, the conductive connection layer 8 includes a plurality of conductive parts 81, a first An electrode 31 is indirectly electrically connected to a pixel driving circuit 21 through a conductive portion 81 .
  • the display panel 100 further includes a first flat layer 7 and a second flat layer 9 .
  • the first planar layer 7 is located between the circuit structure layer 2 and the conductive connection layer 8 , and a plurality of first via holes 71 are formed on the first planar layer 7 .
  • the second flat layer 9 is located between the conductive connection layer 8 and the first electrode layer 3 , and has a plurality of second via holes 91 on the second flat layer 9 .
  • a conductive portion 81 is electrically connected to a pixel driving circuit 21 through a first via hole 71
  • a first electrode 31 is electrically connected to a conductive portion 81 through a second via hole 91 .
  • the display panel 100 further includes a plurality of gate lines GL and a plurality of data signal lines DL.
  • a plurality of gate lines GL extend along the first direction X and are arranged sequentially along the second direction Y; a plurality of data signal lines DL extend along the second direction Y and are arranged sequentially along the first direction X.
  • the multiple data signal lines DL are located on the side of the multiple gate lines GL away from the substrate 1 , and the multiple data signal lines DL and the multiple gate lines GL are insulated from each other.
  • a plurality of data signal lines DL are located in the conductive connection layer 8 .
  • a plurality of gate lines GL may be disposed on the same layer as at least one metal layer in the circuit structure layer 2 .
  • the "same layer” mentioned in some of the above examples refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to form a patterning process.
  • a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure can be continuous or discontinuous, and these specific patterns may also be at different heights Or have different thicknesses.
  • the above-mentioned data signal line DL and the conductive connection layer 8 can be prepared and formed at the same time, and any metal layer in the above-mentioned gate line GL and the circuit structure layer 2 can be prepared and formed at the same time, which is beneficial to simplify The manufacturing process of the display panel 100.
  • a plurality of gate lines GL and a plurality of data signal lines DL are intersected to define a plurality of sub-pixel regions P, and the plurality of sub-pixel regions P correspond to a plurality of pixel driving circuits 21 one-to-one. .
  • the sub-pixel regions P arranged in a row along the first direction X can be called the sub-pixel regions P of the same row
  • the sub-pixel regions P arranged in a column along the second direction Y can be called the sub-pixel regions P of the same column .
  • a plurality of pixel driving circuits 21 are arranged along the first direction X to form a pixel driving circuit row I1, and a plurality of pixel driving circuit rows I1 are arranged in sequence along the second direction Y; a plurality of pixel driving circuits 21 are arranged along the second direction Y to form a pixel driving circuit row I2, and a plurality of pixel driving circuit rows I2 are arranged in sequence along the first direction X; wherein, the first direction X and the second direction Y intersect (for example, the first direction X and the second direction X The two directions Y are vertical).
  • each pixel driving circuit 21 in the same pixel driving circuit row I1 can be electrically connected to a gate line GL
  • each pixel driving circuit 21 in the same pixel driving circuit column I2 can be electrically connected to a data signal line DL .
  • the gate line GL can provide scanning signals to the same row of pixel driving circuits 21 electrically connected to it
  • the data signal line DL can provide data signals to the same column of pixel driving circuits 21 electrically connected to it.
  • each pixel driving circuit 21 in the same pixel driving circuit row I1 may also be electrically connected to multiple gate lines GL, which is not limited in various embodiments of the present disclosure.
  • the display panel 100 further includes a light-emitting functional layer 4 and a second electrode layer 5 located on the side of the first electrode layer 3 away from the substrate 1 and away from the substrate 1 in turn.
  • the light emitting functional layer 4 includes a plurality of light emitting parts 41
  • the second electrode layer 5 includes a plurality of second electrodes 51 .
  • one first electrode 31 , one light emitting portion 41 and one second electrode 51 constitute one light emitting device.
  • a pixel driving circuit 21 is electrically connected to a light emitting device, and the pixel driving circuit 21 is configured to provide a driving voltage to the light emitting device electrically connected thereto, so as to control the light emitting state of the light emitting device.
  • the first electrode 31 may be an anode or a cathode.
  • the second electrode 51 may be a cathode or an anode.
  • the first electrode 31 is an anode
  • the second electrode 51 is a cathode.
  • the first electrode layer 3 composed of a plurality of first electrodes 31 is an anode layer
  • the second electrode layer 3 composed of a plurality of second electrodes 51 is an anode layer.
  • the electrode layer 5 is a cathode layer.
  • the first electrode 31 is a cathode
  • the second electrode 51 is an anode.
  • the first electrode layer 3 composed of a plurality of first electrodes 31 is a cathode layer
  • the first electrode layer 3 composed of a plurality of second electrodes 51 is a cathode layer
  • the second electrode layer 5 is an anode layer.
  • the above-mentioned second electrode layer 5 may be, for example, a whole-surface structure.
  • the above-mentioned light emitting functional layer 4 may be, for example, a whole-surface structure, or may be a plurality of block structures.
  • the above-mentioned light emitting device may be, for example, an OLED (Organic Light Emitting Diode, organic light emitting diode) device, or a QLED (Quantum Dot Light Emitting Diodes, quantum dot light emitting diode) device.
  • the light emitting mode of the above-mentioned light emitting device may be, for example, top emitting light.
  • the light-emitting functional layer 4 includes a light-emitting layer.
  • the light emitting functional layer 4 may further include a hole injection layer and/or a hole transport layer disposed between the anode layer and the light emitting layer.
  • the light emitting functional layer 4 may further include an electron transport layer and/or an electron injection layer disposed between the light emitting layer and the cathode layer.
  • the structure of the pixel driving circuit 21 may include “2T1C”, “6T1C”, “7T1C”, “6T2C” or “7T2C”.
  • T represents a thin film transistor
  • the number before “T” represents the number of thin film transistors
  • C represents a storage capacitor C
  • the number before “C” represents the number of storage capacitor C.
  • the driving transistor DT among the plurality of thin film transistors included in the pixel driving circuit 21 , there is one driving transistor DT and at least one switching transistor ST.
  • the switching transistor ST refers to a thin film transistor electrically connected to the gate line GL among the plurality of thin film transistors included in the pixel driving circuit 21 .
  • the driving transistor DT refers to a thin film transistor that is electrically connected to the storage capacitor C, the switching transistor ST and the light emitting device at the same time among the plurality of thin film transistors included in the pixel driving circuit 21 .
  • the driving transistor DT and the light emitting device may be directly electrically connected (such as shown in FIG. 4 ), or may be indirectly electrically connected (for example, a switching transistor ST may be added between the driving transistor DT and the light emitting device).
  • each thin film transistor included in the pixel driving circuit 21 may be, for example, a thin film transistor with a bottom gate structure, or may be a thin film transistor with a top gate structure.
  • the display panel 100 further includes a pixel defining layer 6 located between the second electrode layer 5 and the light-emitting functional layer 4, and the pixel defining layer 6 includes a plurality of pixel openings 61; a pixel opening 61 exposes at least part of one first electrode 31 .
  • the plurality of pixel openings 61 includes at least one first-type pixel opening 611 , at least one second-type pixel opening 612 and at least one third-type pixel opening 613 .
  • the first type of pixel opening 611 is configured to limit the effective light emitting area of the first color light
  • the second type of pixel opening 612 is configured to limit the effective light emitting area of the second color light
  • the third type of pixel opening 613 is configured to limit The effective light-emitting area of the third color light; the first color light, the second color light and the third color light are the three primary color light.
  • the opening area of the first type of pixel opening 611 is smaller than that of the second type of pixel opening 612 , and the opening area of the first type of pixel opening 611 is larger than that of the third type of pixel opening 613 .
  • the first color light is red light
  • the second color light is blue light
  • the third color light is green light.
  • a pixel light-emitting area can be superimposed to form a pixel light-emitting area, so that the pixel light-emitting area can Display multiple colors of light, and realize multi-grayscale (for example, 256 grayscale) display.
  • multi-grayscale for example, 256 grayscale
  • the display panel 100 further includes a plurality of support pads 10 located between the pixel defining layer 6 and the second electrode layer 4 .
  • the plurality of support pads 10 are used to support the mask used in manufacturing the display panel 100 and the structures formed on the plurality of support pads 10 .
  • the circuit structure layer 2 includes at least one metal layer 22 , and part of the at least one metal layer 22 constitutes part of the structures of the plurality of pixel driving circuits 21 .
  • the part of the at least one metal layer 22 constitutes part of the structure in the plurality of pixel driving circuits 21, for example, the part of the structure in the at least one metal layer 22 can be used as a part of the structure in the plurality of pixel driving circuits 21 .
  • At least one metal layer 22 includes a first gate layer 221 , a second gate layer 222 , and a source-drain metal layer 223 that are sequentially away from the substrate 1 .
  • the circuit structure layer 2 further includes an active layer 23 , a first insulating layer 24 , a second insulating layer 25 and an interlayer dielectric layer 26 .
  • the active layer 23 is located on the side of the first gate layer 221 facing the substrate 1
  • the first insulating layer 24 is located between the active layer 23 and the first gate layer 221
  • the second insulating layer 25 is located on the first gate layer.
  • the interlayer dielectric layer 26 is located between the second gate layer 222 and the source-drain metal layer 223 .
  • a pixel driving circuit in a sub-pixel region P, includes a driving transistor DT and at least one switching transistor ST.
  • At least one switch transistor ST includes a data compensation transistor.
  • data compensation transistors there are various types of the above-mentioned data compensation transistors, for example, they may be non-oxide transistors.
  • the structure of the display panel 100 will be schematically described by taking the “7TIC” pixel driving circuit 21 as an example with reference to FIG. 5A to FIG. 10 .
  • FIG. 5A is a structural diagram of another display panel 100 provided by some embodiments of the present disclosure.
  • a position relationship diagram of the first gate layer 221, the pixel drive circuit 21 may include a drive transistor T3, a first light emission control transistor T6, a second light emission control transistor T5, a data writing transistor T4, a storage capacitor C, and a data compensation transistor T2, the first reset transistor T7 and the second reset transistor T1.
  • the data compensation transistor T2 may be, for example, a switching transistor ST.
  • FIG. 6B shows a positional relationship diagram between the active layer ( 231 , 232 ) and the first gate layer 221 at another sub-pixel region.
  • the second reset transistor T1 and the data compensation transistor T2 are metal oxide transistors
  • the drive transistor T3, the data writing transistor T4, the second light emission control transistor T5, the first light emission control transistor T6, and the first reset transistor T7 are low temperature transistors. polysilicon transistors.
  • the active layer 231 of the above-mentioned low-temperature polysilicon transistor is located on the side of the first gate layer 221 close to the substrate, and the active layer 232 of the above-mentioned metal oxide transistor is located on the side of the first gate layer 221 away from the substrate, for example It may be located between the first gate layer 221 and the second gate layer 222 .
  • Such a design can effectively improve the anti-leakage performance of the second reset transistor T1 and the data compensation transistor T2, and at the same time help to reduce production costs.
  • FIG. 6C shows another positional relationship diagram between the active layer ( 231 , 232 ) and the first gate layer 221 at the sub-pixel region.
  • the first reset transistor T7 is also a metal oxide transistor. This design is also beneficial to improve the anti-leakage performance of the first reset transistor T7 and further reduce the manufacturing cost.
  • the driving transistor T3 may have a single-gate structure
  • the first light emission control transistor T6 may have a single-gate structure
  • the second light emission control transistor T5 may have a single-gate structure
  • the data writing transistor T4 may, for example,
  • the data compensation transistor T2 may have a double-gate structure
  • the first reset transistor T7 may have a single-gate structure
  • the second reset transistor T1 may have a double-gate structure.
  • FIG. 7 is an equivalent circuit diagram of a sub-pixel region in FIG. 5A , the driving transistor DT is configured to provide a driving voltage to a light emitting device electrically connected thereto, so as to control the light emitting state of the light emitting device.
  • FIG. 9 is a positional diagram of the active layer 23, the first gate layer 221, the second gate layer 222 and the source-drain metal layer 223 in FIG. 5A, and FIG. A positional relationship diagram of the middle active layer 23 , the first gate layer 221 , the second gate layer 222 , the source-drain metal layer 223 and the conductive connection layer 8 .
  • the display panel 100 includes a plurality of data signal lines DL and a plurality of power signal lines.
  • the plurality of data signal lines DL extend in the second direction Y.
  • the power signal line can be electrically connected to the first voltage terminal VDD in FIG. 7 to provide a voltage signal.
  • the power signal lines include a first power signal line VL1 located on the source-drain electrode layer 223 and extending along the second direction Y.
  • the power signal line includes a first power signal line VL1 located on the source-drain electrode layer 223 and extending along the second direction Y, and a first power signal line VL1 located on the conductive connection layer 8 and extending along the second direction Y.
  • the first power signal line VL1 and the second power signal line VL2 are electrically connected, the orthographic projections of the first power signal line VL1 and the second power signal line VL2 on the substrate 1 overlap, and at least one pixel opening 61 (for example , the orthographic projection of the first type of pixel opening 611) on the substrate 1 is within the range of the orthographic projection of the second power signal line VL2 on the substrate 1 .
  • This design can reduce the light transmittance of the film layer between the pixel opening 61 and the pixel driving circuit 21, forming a better light blocking effect; at the same time, it can also make the first electrode 31 below the pixel opening 61 flat, improving the uniformity of light emission. sex.
  • the second power signal line VL2 has a plurality of protrusions K, the orthographic projection of one protrusion K on the substrate 1 and the pixel opening 61 corresponding to one first electrode 31 on the substrate 1
  • the orthographic projections on are at least partially overlapping.
  • the orthographic projection of the protrusion K of the second power signal line VL2 on the substrate 1 and the orthographic projection of the pixel opening 61 corresponding to one first electrode 31 on the substrate 1 at least partially overlap, thus The light transmittance of the film layer between the pixel opening 61 and the pixel driving circuit 21 can be reduced to form a better light blocking effect; at the same time, the first electrode 31 below the pixel opening 61 can be flattened to improve the uniformity of light emission.
  • the display panel 100 also includes a gate line GL located on the side of the power signal line VL facing the substrate 1 and parallel to each other, an emission control signal line EM, a first reset control signal line Rst1 and a second reset control signal line. Signal line Rst2.
  • the extension directions of the gate line GL, the emission control signal line EM, the first reset control signal line Rst1 and the second reset control signal line Rst2 intersect with the extension direction of the data signal line DL, for example, the gate line GL, the emission control signal line
  • the extension direction of the signal line EM, the first reset control signal line Rst1 and the second reset control signal line Rst2 is perpendicular to the extension direction of the data signal line DL.
  • a part of the first gate layer 221 constitutes the drive transistor T3, the first light emission control transistor T6, the second light emission control transistor T5, the data writing transistor T4, and the pixel drive circuit 21.
  • the data compensation transistor T2 the gates of the first reset transistor T7 and the second reset transistor T1, the second pole C2 in the storage capacitor C, the gate lines GL parallel to each other, the light emission control signal line EM, the first reset control The signal line Rst1 and the second reset control signal line Rst2.
  • the display panel 100 also includes a plurality of reset signal lines located between the film layer where the gate line GL is located and the film layer where the data signal line DL is located. /or the gate of the drive transistor T3 provides a reset signal.
  • FIG. 8A is a positional diagram of the active layer 23, the first gate layer 221, and the second gate layer 222 at a sub-pixel region P in FIG.
  • the signal lines include a first first reset signal line Vint1 and a second first reset power signal Vint2 extending along the first direction X.
  • FIG. 8B and FIG. 8C are respectively the active layer 23, the first gate layer 221, and the second gate layer at a sub-pixel region P provided by some embodiments of the present disclosure.
  • the multiple reset signal lines may also include a first second reset signal line Vint1' extending along the second direction Y and a second reset signal line Vint1' extending along the second direction Y.
  • a second second reset signal line Vint2' extending in the direction Y.
  • the first first reset signal line Vint1 is electrically connected to the first second reset signal line Vint1', and is used to reset the gate of the drive transistor T3;
  • the second first reset signal line Vint2 is connected to the second
  • the second reset signal line Vint2' is electrically connected to reset the first electrode 31 (ie, the anode of the light emitting device).
  • a part of the second gate layer 222 constitutes the first electrode C1 of the storage capacitor C in the pixel driving circuit 21, the first first reset signal line Vint1 and the second The first reset signal line Vint2.
  • a part of the source-drain metal layer 223 constitutes the first power signal line VL1 and the second second reset signal line Vint2 ′ in the pixel driving circuit 21 .
  • the orthographic projection of the second first reset signal line Vint2 on the substrate 1 overlaps the orthographic projection of the second second reset signal line Vint2' on the substrate 1.
  • the second The first reset signal line Vint2 is electrically connected to the second second reset signal line Vint2' through the via hole J1.
  • the second second reset signal line Vint2' is connected to the active layer 23 through the via hole J4.
  • a part of the second gate layer 222 constitutes the first pole C1 of the storage capacitor C in the pixel driving circuit 21 .
  • Part of the active layer 23 constitutes the first first reset signal line Vint1 and the second first reset signal line Vint2 .
  • the second second reset signal line Vint2' is electrically connected to the second first reset signal line Vint2, therefore, the second The second reset signal line Vint2 ′ does not need to be additionally connected to the active layer 23 through a via hole.
  • the display panel 100 also includes a connection block F located on the source-drain electrode layer 223, the first second reset signal line Vint1' is electrically connected to the connection block F through the via hole J2, and the connection block F is connected to the first connection block F through the via hole J3.
  • the first reset signal line Vint1 is electrically connected, so that the first first reset signal line Vint1 is electrically connected to the first second reset signal line Vint1 ′.
  • the first and second reset signal line Vint1' is shown as a straight line. It can be understood that in actual products, in order to avoid interference with other structures arranged on the same layer, a A bend escape portion may be provided on the first and second reset signal line Vint1'. For example, when the first second reset signal line Vint1 ′ is located in the conductive connection layer 8 , the transition block located in the conductive connection layer 8 and connected to the first electrode 31 can be avoided by the bending escape portion.
  • the bend avoidance part can be used to align the gates of the source-drain electrode layer 223 and simultaneously connect the data compensation transistor T2 and the drive transistor T3. Avoid using the transfer block of the pole.
  • the present disclosure does not limit the number of the above-mentioned bending avoidance parts, that is, the number of the bending avoidance parts may be one or multiple, for example, it may be set according to the number of structures that need to avoid.
  • FIG. 10 is a positional relationship of the active layer 23 , the first gate layer 221 , the second gate layer 222 , the source-drain metal layer 223 and the conductive connection layer 8 in FIG. 5A picture.
  • Part of the conductive connection layer 8 constitutes the data signal line DL in the pixel driving circuit 21 .
  • a part of the conductive connection layer 8 also constitutes the second power signal line VL2 .
  • the first pole of the data writing transistor T4 is configured to be electrically connected to the data signal line DL to receive a data signal
  • the second pole of the data writing transistor T4 is configured to pass
  • the node N2 is electrically connected to the first pole of the driving transistor T3, and the gate of the data writing transistor T4 is configured to be electrically connected to the gate line GL to receive the gate control signal;
  • the first pole of the data compensation transistor T2 is connected to the driving transistor T3 through the node N3.
  • the second pole of the transistor T3 is electrically connected, the second pole of the data compensation transistor T2 is electrically connected to the gate of the driving transistor T3 through the node N1, and the gate of the data compensation transistor T2 is configured to be electrically connected to the gate line GL to receive the gate control signal.
  • the first pole C1 of the storage capacitor C is electrically connected to the first voltage terminal VDD, and the second pole C2 of the storage capacitor C is electrically connected to the gate of the driving transistor T3 through the node N1.
  • the first pole of the first reset transistor T7 is configured to be electrically connected to the second first reset signal line Vint2 to receive the reset signal, and the second pole of the first reset transistor T7 is electrically connected to the first end of the light emitting device through the node N4 , the gate of the first reset transistor T7 is configured to be electrically connected to the second reset control signal line Rst2 to receive the reset control signal; the first pole of the second reset transistor T1 is configured to be electrically connected to the first first reset signal line Vint1 Electrically connected to receive a reset signal, the second pole of the second reset transistor T1 is electrically connected to the gate of the driving transistor T3 through the node N1, and the gate of the second reset transistor T1 is configured to be electrically connected to the first reset control signal line Rst1 to receive the reset control signal.
  • the first electrode of the first light emission control transistor T6 is electrically connected to the second electrode of the driving transistor T3 through the node N3, the second electrode of the first light emission control transistor T6 is electrically connected to the first electrode of the light emitting device through the node N4, and the first light emission
  • the gate of the control transistor T6 is configured to be electrically connected to the light emission control signal line EM to receive the light emission control signal;
  • the first pole of the second light emission control transistor T5 is electrically connected to the first voltage terminal VDD, and the second electrode of the second light emission control transistor T5
  • the two poles are electrically connected to the first pole of the driving transistor T3 through the node N2, and the gate of the second light emission control transistor T5 is configured to be connected to the light emission control signal line EM to receive the light emission control signal;
  • the second pole of the light emitting device is connected to the second pole of the light emitting device.
  • the voltage terminal VSS is electrically connected.
  • At this time, at least one switching transistor ST includes a first light emission control transistor T6, a second light emission control transistor T5, a data write transistor T4, a data compensation transistor T2, a first reset transistor T7 and a second reset transistor T1.
  • the nodes N1, N2, N3, and N4 do not represent actual components, but represent the confluence of relevant electrical connections in the circuit diagram, that is to say , these nodes are nodes equivalent to the confluence of related electrical connections in the circuit diagram.
  • thin film transistors can be divided into N-type transistors and P-type transistors.
  • the thin-film transistors in the embodiments of the present disclosure are P-type transistors, and the P-type transistors can be, for example, P-type MOS transistors, that is, In the description of the embodiment of the present disclosure, the drive transistor T3, the first light emission control transistor T6, the second light emission control transistor T5, the data write transistor T4, the data compensation transistor T2, the first reset transistor T7 and the second reset transistor T1 etc. can be P-type transistors.
  • the thin film transistors in the embodiments of the present disclosure are not limited to P-type transistors, and those skilled in the art can also use N-type transistors to implement one or more thin film transistors in the embodiments of the present disclosure according to actual needs.
  • the N-type transistor may be an N-type MOS transistor.
  • the opening area of the third type of pixel opening 613 is smaller than the opening area of the first type of pixel opening 611 and the opening area of the second type of pixel opening 612, at the same time, because one pixel opening 61 needs to expose At least part of a first electrode 31, so that the area of the first electrode 31 corresponding to the third type of pixel opening 613 is also smaller than the area of the first electrode 31 corresponding to the first type of pixel opening 611 and the area corresponding to the second type of pixel opening 611
  • the first electrode 31 so that in the sub-pixel region P corresponding to the third-type pixel opening 613 , the first electrode 31 cannot cover all the switching transistors ST (including the data compensation transistor T2 ) in the pixel driving circuit 21 .
  • At least one switching transistor ST (including the data compensation transistor T2) is covered and protected without a film layer, resulting in Illumination affects the characteristics of the switching transistor ST (data compensation transistor T2 ), so problems such as leakage current of the switching transistor ST (data compensation transistor T2 ) are prone to occur, which will eventually affect the display effect.
  • some embodiments of the present disclosure provide a display panel 100 .
  • the orthographic projection of the pixel opening 61 corresponding to at least one first electrode 31 on the substrate 1 and the gate of the data compensation transistor T2 in the pixel driving circuit 21 corresponding to the first electrode 31 are on the substrate. Orthographic separation on 1.
  • the orthographic projection of the first-type pixel opening 611 on the substrate 1 and the gate of the data compensation transistor T2 in the pixel driving circuit 21 corresponding to the first-type pixel opening 611 are on the substrate 1 Orthographic separation of .
  • the orthographic projection of the third-type pixel opening 613 on the substrate 1 and the data compensation transistor T2 in the pixel driving circuit 21 corresponding to the third-type pixel opening 613 The orthographic projection of the gate on the substrate 1 can also be separated.
  • the orthographic projection of the at least one first electrode 31 on the substrate 1 is at least partially intersected with the orthographic projection of the gate of the data compensation transistor T2 in the pixel driving circuit 21 corresponding to the first electrode 31 on the substrate 1. At the same time, at least partially overlap with the orthographic projection of the gate of the data compensation transistor T2 in at least one pixel driving circuit 21 adjacent to the pixel driving circuit 21 corresponding to the first electrode 31 on the substrate 1 .
  • the data compensation transistor may be, for example, a non-oxide transistor.
  • the orthographic projection of the data compensation transistor T2 corresponding to the first electrode 31 on the substrate 1 is different from that extending along the first direction X
  • the first imaginary straight line S1 has a first overlapping portion P1; the orthographic projection of the data compensation transistor T2 in the pixel driving circuit 21 adjacent to the pixel driving circuit 21 corresponding to the first electrode 31 on the substrate 1 is the same as the first
  • the virtual straight line S1 has a second overlapping portion P2; the distance between the first overlapping portion P1 and the second overlapping portion P2 in the first direction X is larger than the pixel opening 61 corresponding to the first overlapping portion P1 in the first direction Dimensions on X.
  • At least one first electrode 31 covers and protects the gate of the data compensation transistor T2 in the pixel driving circuit 21 corresponding to itself, and covers and protects the gate of the data compensation transistor T2 corresponding to the electrode 31.
  • the gate of the data compensation transistor T2 in at least one pixel drive circuit 21 adjacent to the pixel drive circuit 21 corresponding to the first electrode 31 can prevent the light from affecting the characteristics of the data compensation transistor T2, thereby avoiding the leakage current of the data compensation transistor T2 and other problems, finally improving the performance stability of the display panel 100 .
  • the distance between the first overlapping portion P1 and the second overlapping portion P2 in the first direction X is greater than the size of the pixel opening 61 corresponding to the first overlapping portion P1 in the first direction X,
  • the distance between the data compensation transistor T2 corresponding to the first electrode 31 and the data compensation transistor T2 in the pixel driving circuit 21 adjacent to the pixel driving circuit 21 corresponding to the first electrode 31 is relatively large, which is beneficial to prevent The problem of signal interference occurs between the two data compensation transistors T2.
  • a plurality of pixel openings 61 are arranged in multiple rows and columns; two adjacent rows of pixel openings 61 are staggered along the first direction X. Referring to FIG.
  • one row of pixel openings 61 includes first-type pixel openings 611 and second-type pixel openings 612 arranged alternately along the first direction X, and the other row of pixel openings includes pixel openings arranged in sequence along the first direction X.
  • a plurality of third type pixel openings 613 is arranged in sequence along the first direction X.
  • one column of pixel openings includes first-type pixel openings 611 and second-type pixel openings 612 arranged alternately along the second direction Y, and the other column of pixel openings includes multiple pixel openings arranged in sequence along the second direction Y.
  • the display panel 100 can The aliasing effect of the display panel 100 is weakened, thereby reducing the aliasing effect of the edge of the display panel 100, so that the display quality is significantly improved.
  • first type of pixel openings 611 and the second type of pixel openings 612 in the same row are alternately arranged in the first direction X.
  • the center of the first-type pixel opening 611 and the center of the second-type pixel opening 612 may have no spacing in the second direction Y as shown in FIGS. 11, 12, 14 and 15 (that is, the same row In the first type of pixel opening 611 and the second type of pixel opening 612, the center of the first type of pixel opening 611 and the center of the second type of pixel opening 612 are located on the same straight line along the first direction X), or for example 13 and FIG.
  • the first type of pixel openings 611 and the second type of pixel openings 612 in the same row are alternately arranged in the second direction Y.
  • the center of the first-type pixel opening 611 and the center of the second-type pixel opening 612 may have no spacing in the first direction X as shown in FIGS. 11, 12, 13, 14 and 15 (that is, , in the first type of pixel opening 611 and the second type of pixel opening 612 in the same column, the center of the first type of pixel opening 611 and the center of the second type of pixel opening 612 are located on the same straight line along the second direction Y), or For example, there may be a certain distance in the first direction X as shown in FIG. The centers of the two types of pixel openings 612 are not located on the same straight line along the second direction Y).
  • the center of the first-type pixel opening 611 may be, for example, the geometric center of the first-type pixel opening 611 .
  • the center of the second-type pixel opening 612 may be, for example, the geometric center of the second-type pixel opening 612 .
  • any first-type pixel opening 611 and the first-type pixel opening 611 are equal.
  • a pixel light-emitting area can be superimposed to form a pixel light-emitting area, so that the pixel light-emitting area can display various colors.
  • Color light and achieve multi-grayscale (for example, 256 grayscale) display.
  • multi-grayscale for example, 256 grayscale
  • any first-type pixel opening 611 and the first-type pixel are not equal.
  • a pixel light-emitting area can be superimposed to form a pixel light-emitting area, so that the pixel light-emitting area can display various colors.
  • Color light and achieve multi-grayscale (for example, 256 grayscale) display.
  • multi-grayscale for example, 256 grayscale
  • the adjacent first-type pixel openings 611 and second-type pixel openings 612 in a column of pixel openings 61 are the same as the adjacent first-type pixel openings 611 and second-type pixel openings 61 in adjacent columns of pixel openings 61
  • the geometric centers of the four pixel openings 612 are connected to form a virtual trapezoid Q.
  • a pixel light-emitting area can be superimposed to form a pixel light-emitting area, so that the pixel light-emitting area can display various colors.
  • Color light and achieve multi-grayscale (for example, 256 grayscale) display.
  • multi-grayscale for example, 256 grayscale
  • the centers of the first-type pixel openings 611 and the second-type pixel openings 612 have a certain distance in the second direction Y.
  • Such a design can make the light of various colors in a pixel light-emitting area cooperate better, so that the picture display accuracy of the display panel 100 is higher, the definition is better, and the display effect is better.
  • the distance may be less than or equal to half of the size of the first-type pixel opening 611 in the second direction Y, for example.
  • This design can further reduce the jaggedness of the display panel 100 at the edge of the display area while ensuring the display accuracy and clarity of the display panel 100, thereby better reducing the jagged edge of the display panel 100.
  • the display quality of the display panel 100 is improved.
  • the distance may be less than or equal to half of the size of the first-type pixel opening 611 in the first direction X, for example.
  • This design can further reduce the jaggedness of the display panel 100 at the edge of the display area while ensuring the display accuracy and clarity of the display panel 100, thereby better reducing the jagged edge of the display panel 100.
  • the display quality of the display panel 100 is improved.
  • the plurality of pixel openings 61 closest to the boundary of the display area A include at least one row of first-type pixel openings 611 and second-type pixel openings 612 arranged alternately along the first direction X. , and/or, at least one row of first-type pixel openings 611 and second-type pixel openings 612 arranged alternately along the second direction Y.
  • Such design can make the plurality of pixel openings 61 closest to the boundary of the display area A include more first-type pixel openings 611 and second-type pixel openings 612.
  • the opening area of the first type of pixel opening 612 is larger than that of the third type of pixel opening 613, so the gap between the plurality of pixel openings 61 closest to the boundary of the display area A can be reduced as much as possible, further improving the display area of the display panel 100.
  • the jaggedness of the edge produces a weakening effect, thereby better reducing the jagged edge of the display panel 100 and further improving the display quality of the display panel 100 .
  • the plurality of pixel openings closest to the boundary of the display area A may be, for example, two rows of pixel openings 61 closest to the boundary of the display area A, and a plurality of pixel openings 61 closest to the boundary of the display area A. Two columns of pixel openings 61 .
  • the plurality of pixel openings 61 closest to the boundary of the display area A only include a row of first-type pixel openings 611 and second-type pixel openings 612 alternately arranged along the first direction X (such as the dotted line frame shown in H1).
  • the plurality of pixel openings 61 closest to the boundary of the display area A only include a row of first-type pixel openings 611 and second-type pixel openings 612 arranged alternately along the second direction Y (such as the dotted line box L1).
  • the plurality of pixel openings 61 closest to the boundary of the display area A include a row of first-type pixel openings 611 and second-type pixel openings 612 arranged alternately along the first direction X (such as the dotted line frame H2 ), and a row of first-type pixel openings 611 and second-type pixel openings 612 arranged alternately along the second direction Y (for example, as shown by the dotted line box L2 ).
  • the plurality of pixel openings 61 closest to the boundary of the display area A only include two rows of first-type pixel openings 611 and second-type pixel openings 612 arranged alternately along the first direction X (for example, dashed box H3 and dashed box H4).
  • the plurality of pixel openings 61 closest to the boundary of the display area A only include two rows of first-type pixel openings 611 and second-type pixel openings 612 arranged alternately along the second direction Y (for example, dashed box L3 and dashed box L4).
  • the plurality of pixel openings 61 closest to the boundary of the display area A include two rows of first-type pixel openings 611 and second-type pixel openings 612 arranged alternately along the first direction X (such as the dotted line box H5 and dotted line box H6), and two rows of first-type pixel openings 611 and second-type pixel openings 612 arranged alternately along the second direction Y (for example, as shown by dotted-line box L5 and dotted-line box L6).
  • the opening area ratio of the first type pixel opening 611 , the second type pixel opening 612 and the third type pixel opening 613 is (2.09 ⁇ 2.10):(3.69 ⁇ 3.70):(1.41 ⁇ 1.42).
  • the jaggedness of the display panel 100 at the edge of the display area can be further controlled.
  • the effect of weakening the feeling is produced, so as to better reduce the jagged edge effect of the display panel 100 and further improve the display quality of the display panel 100 .
  • the opening shape of the first type of pixel opening 611 is approximately any one of square, rectangle, rhombus, circle, ellipse, olive, hexagon and octagon.
  • the shape of the opening may be, for example, a square.
  • Such a design can make the opening shape of the first-type pixel opening 611 more regular, and make it more regularly arranged with the second-type pixel opening 612 and the third-type pixel opening 613, that is, make the various types of pixel openings in a pixel light-emitting area
  • the colors of the light are better coordinated, so that the display panel 100 has higher display precision, better definition and better display effect.
  • the opening shape of the second type of pixel opening 612 is approximately any one of square, rectangle, rhombus, circle, ellipse, olive, hexagon and octagon.
  • the shape of the opening may be, for example, a square.
  • Such a design can make the opening shape of the second-type pixel opening 612 more regular, and make it more regularly arranged with the first-type pixel opening 611 and the third-type pixel opening 613, that is, make the various types of pixel openings in a pixel light-emitting area
  • the colors of the light are better coordinated, so that the display panel 100 has higher display precision, better definition and better display effect.
  • the opening shape of the third type of pixel opening 613 is approximately any one of square, rectangle, rhombus, circle, ellipse, olive, hexagon and octagon.
  • the shape of the opening may be, for example, a rectangle.
  • Such a design can make the opening shape of the third-type pixel opening 613 more regular, and make it more regularly arranged with the first-type pixel opening 611 and the second-type pixel opening 612, that is, make the various types of pixel openings in a pixel light-emitting area The colors of the light are better coordinated, so that the display panel 100 has higher display precision, better definition and better display effect.
  • the opening shapes of the first-type pixel opening 611 , the second-type pixel opening 612 and the third-type pixel opening 613 are substantially rectangular.
  • the size of the first type of pixel opening 611 is 14.48 ⁇ m ⁇ 14.48 ⁇ m; the size of the second type of pixel opening 612 is 19.23 ⁇ m ⁇ 19.23 ⁇ m; the size of the third type of pixel opening 613 is 12.63 ⁇ m ⁇ 11.21 ⁇ m.
  • This design can not only make the arrangement of the first type of pixel opening 611, the second type of pixel opening 612 and the third type of pixel opening 613 more regular, that is, make the light of various colors in the light-emitting area of a pixel better match , so that the picture display accuracy of the display panel 100 is higher, the definition is better, and the display effect is better; and the jagged feeling of the display panel 100 at the edge of the display area can be further weakened, so that the display panel 100 can be better reduced.
  • the edge jagged effect further improves the display quality of the display panel 100 .
  • the second type of pixel opening 61 through the arrangement of the first type of pixel opening 611 , the second type of pixel opening 612 , and the third type of pixel opening 613 among the plurality of pixel openings 61 , and the arrangement of the first type of pixel opening 611 , the second type of pixel opening 61
  • the types of light corresponding to the effective light-emitting areas defined by the second-type pixel opening 612 and the third-type pixel opening 613 respectively, and the opening areas of the first-type pixel opening 611 , the second-type pixel opening 612 , and the third-type pixel opening 613 Limiting the light of various colors in the light-emitting area of a pixel can not only better cooperate, but also can weaken the jagged feeling of the display panel 100 at the edge of the display area, reducing the edge jagged effect of the display panel 100, so that The image display precision of the display panel 100 is higher, the definition is better, the display effect is better, and the display quality is significantly improved.
  • the orthographic projection of the first electrode 31 corresponding to the first type of pixel opening 611 on the substrate 1 , and the data compensation in the pixel driving circuit 21 corresponding to the first electrode 31 The orthographic projection of the gate of the transistor T2 on the substrate 1 at least partially overlaps with the gate of the data compensation transistor T2 in at least one pixel driving circuit 21 adjacent to the pixel driving circuit 21 corresponding to the first electrode 31.
  • the orthographic projections of the poles on the substrate 1 overlap at least partially.
  • the first electrode 31 corresponding to the first-type pixel opening 611 cover and protect the gate of the data compensation transistor T2 in the pixel driving circuit 21 corresponding to itself, and covering and protecting the first electrode 31
  • the gate of the data compensation transistor T2 in at least one pixel drive circuit 21 adjacent to the pixel drive circuit 21 corresponding to 31 can prevent light from affecting the characteristics of the data compensation transistor T2, thereby avoiding problems such as leakage current of the data compensation transistor T2, Finally, the performance stability of the display panel 100 is improved.
  • the orthographic projection of the first electrode 31 corresponding to the second type of pixel opening 612 on the substrate 1, and the data compensation in the pixel driving circuit 21 corresponding to the first electrode 31 The orthographic projection of the gate of the transistor T2 on the substrate 1 at least partially overlaps with the gate of the data compensation transistor T2 in at least one pixel driving circuit 21 adjacent to the pixel driving circuit 21 corresponding to the first electrode 31.
  • the orthographic projections of the poles on the substrate 1 overlap at least partially.
  • the first electrode 31 corresponding to the second-type pixel opening 612 cover and protect the gate of the data compensation transistor T2 in the pixel driving circuit 21 corresponding to itself, and by covering and protecting the first electrode 31
  • the gate of the data compensation transistor T2 in at least one pixel drive circuit 21 adjacent to the pixel drive circuit 21 corresponding to 31 can prevent light from affecting the characteristics of the data compensation transistor T2, thereby avoiding problems such as leakage current of the data compensation transistor T2, Finally, the performance stability of the display panel 100 is improved.
  • the first type of pixel openings 611 and the third type of pixel openings 613 are alternately arranged along the third direction D1 to form a first group of pixel openings G1 (such as shown in FIG. 12 ), the second type of pixel openings 612 and the third type of pixel openings 613 are alternately arranged along the third direction D1 to form the second group of pixel openings G2 (such as shown in FIG. 12 ), the first group of pixel openings G1 and the second group of pixel openings G2 Alternately arranged in the fourth direction D2; wherein, the third direction D1 intersects the fourth direction D2.
  • the orthographic projection of the first electrode 31 corresponding to the first type pixel opening 611 on the substrate 1, and the first electrode 31 adjacent to the first type pixel opening 611 at least partially overlap; please continue to refer to FIG.
  • first-type pixel openings 611 and the third-type pixel openings 613 in the first group of pixel openings G1 are alternately arranged in the third direction D1.
  • the center of the first-type pixel opening 611 and the center of the third-type pixel opening 613 may be in the fourth direction D2 as shown in FIG. 11 , FIG. 12 , FIG. 14 and FIG. 15
  • There is no pitch that is, the center of the first-type pixel opening 611 and the center of the third-type pixel opening 613 are located on the same straight line along the third direction D1), or, for example, as shown in FIG. 13 and FIG.
  • the center of the first-type pixel opening 611 and the center of the second-type pixel opening 612 can be in the fourth direction D2 as shown in FIG. 11 , FIG. 12 , FIG. 14 and FIG. 15
  • There is no pitch that is, the center of the first-type pixel opening 611 and the center of the second-type pixel opening 612 are located on the same straight line along the third direction D1), or, for example, as shown in FIG. 13 and FIG.
  • the center of the third-type pixel opening 613 may be, for example, the geometric center of the third-type pixel opening 613 .
  • the direction in which the first-type pixel openings 611 and the third-type pixel openings 613 are alternately arranged is defined as the third direction D1.
  • the third direction D1 is different depending on the direction in which the first-type pixel openings 611 and the third-type pixel openings 613 are alternately arranged.
  • the fourth direction D2 is also different according to the direction in which the first-type pixel openings 611 and the third-type pixel openings 613 are alternately arranged.
  • the third direction D1 is perpendicular to the fourth direction D2
  • the angles between the third direction D1 and the first direction X and the second direction Y are both about 45 degrees
  • the second direction and the second direction are perpendicular to each other.
  • the angles between the first direction X and the second direction Y are also about 45 degrees.
  • the orthographic projections of the two first electrodes 31 on the substrate 1 corresponding to the adjacent first-type pixel openings 611 and the second-type pixel openings 612 are respectively located at the The orthographic projections of the gates of the data compensation transistor T2 on the substrate 1 corresponding to the two third-type pixel openings 613 on the same side of the adjacent first-type pixel openings 611 and second-type pixel openings 612 are at least partially intersected. stack.
  • This design can reduce the manufacturing difficulty of the first electrode 31 of the first type pixel opening 611 and the first electrode 31 of the second type pixel opening 612 , and simplify the manufacturing process of the display panel 100 .
  • the data compensation transistor T2 may be, for example, a non-oxide transistor.
  • the orthographic projection of the corresponding first electrode 31 on the substrate 1 at least partially overlaps with the orthographic projection of the gate of the data compensation transistor T2 in the pixel driving circuit 21 corresponding to the third type of pixel opening 613 on the substrate 1 , that is, make the first electrode 31 corresponding to the first-type pixel opening 611 and the first electrode 31 corresponding to the second-type pixel opening 612 cover at least part of the pixel driving circuit 21 corresponding to the third-type pixel opening 613
  • the gate of the data compensation transistor T2 can cover and protect the gate of the data compensation transistor T2 to prevent the impact of light on the threshold compensation voltage of the data compensation transistor T2, thereby further improving the performance stability of the display panel 100 .
  • the first electrode corresponding to the first-type pixel opening 611 also covers the node N1 corresponding to the first-type pixel opening 611; and/or, the second-type pixel opening 612
  • the corresponding first electrode 31 also covers the node N1 corresponding to the second type pixel opening 612 .
  • the performance stability of the display panel 100 can be further improved.
  • the arrangement of the pixel openings 61 in some of the above examples is only for schematic illustration, and the arrangement of the plurality of pixel openings 61 in the present disclosure is not limited to the above examples, and any one of them can form a third type of pixel
  • the first electrode 31 or the first electrode 31 corresponding to the first type of pixel opening 611 provided in the above examples is adopted.
  • the first electrode 31 corresponding to the second pixel opening 612 covers at least one switching transistor ST in the pixel driving circuit 21 corresponding to the third pixel opening 613, both of which can avoid the impact of light on the characteristics of the switching transistor ST. Therefore, the performance stability effect of the display panel 100 is improved.
  • a plurality of data signal lines DL are located in the conductive connection layer 8 between the circuit structure layer 2 and the first electrode layer 3 .
  • the first type of pixel opening 611 , the second type of pixel opening 612 and the third type of pixel opening 613 are configured in accordance with at least one of the first mode, the second mode and the third mode.
  • Manner 1 The orthographic projection of the edge of the first pixel opening 611 on the substrate 1 is located between the orthographic projections of two adjacent data signal lines DL on the substrate 1 .
  • the orthographic projection of the edge of the control first-type pixel opening 611 on the substrate 1 is located on two adjacent data signal lines.
  • the exposed portion is stepped, which can ensure the flatness of the portion exposed by the first-type pixel opening 611 in the first electrode layer 3 .
  • the light-emitting functional layer 4 is continued to be fabricated on the part of the first electrode layer 3 exposed by the first-type pixel opening 611, the flatness of the light-emitting functional layer 4 at this part can also be ensured, thereby ensuring the display panel 100 The uniformity of the first color light when displayed.
  • the orthographic projection of the edge of the second pixel opening 612 on the substrate 1 is located between the orthographic projections of two adjacent data signal lines DL on the substrate 1; or, two adjacent data signal lines
  • the orthographic projections of DL on the substrate 1 partially overlap with the orthographic projections of the edge of the second-type pixel opening 612 on the substrate 1, and the orthographic projections of two adjacent data signal lines DL on the substrate 1 overlap with the second
  • the areas of the two overlapping parts of the orthographic projection of the edge of the seed pixel opening 612 on the substrate 1 are approximately the same.
  • the orthographic projection of the edge of the second-type pixel opening 612 on the substrate 1 is controlled to be located on two adjacent data signal lines.
  • the exposed portion is stepped, which can ensure the flatness of the portion exposed by the second type pixel opening 612 in the first electrode layer 3 .
  • the flatness of the light-emitting functional layer 4 at this part can also be ensured, thereby ensuring the display panel 100 The uniformity of the second color light when displayed.
  • the opening area of the second-type pixel opening 612 may be larger than the first-type pixel opening 611 and the third-type pixel opening 613, for example, in this case, since the second-type pixel opening 612 has a larger opening area, adjacent The distance between the two data signal lines DL is small, at this time, the orthographic projection of the edge of the second type pixel opening 612 on the substrate 1 will be the same as that of the adjacent two data signal lines DL on the substrate 1 The orthographic projections partially overlap.
  • Mode 3 The orthographic projection of the edge of the third type pixel opening 613 on the substrate 1 is located between the orthographic projections of two adjacent data signal lines DL on the substrate 1 .
  • the orthographic projection of the edge of the third type pixel opening 613 on the substrate 1 is controlled to be located on two adjacent data signal lines.
  • the exposed portion is stepped, which can ensure the flatness of the portion exposed by the third type pixel opening 613 in the first electrode layer 3 .
  • the flatness of the light-emitting functional layer 4 at this part can also be ensured, thereby ensuring the display panel 100 The uniformity of the third color light when displayed.
  • first-type pixel opening 611, second-type pixel opening 612, and third-type pixel opening 613 are configured to be set according to at least one of the first, second, and third methods, for example, only according to The setting in one of the ways, for example, can be set in combination with two or three of the ways at the same time, which can be selected according to actual needs.
  • the first-type pixel opening 611 is a mirror surface symmetry.
  • Such a design can improve the uniformity of the arrangement of the first-type pixel openings 611 and the data signal lines DL, thereby further ensuring the display quality of the display panel 100 .
  • the second-type pixel opening 612 is a mirror surface symmetry. This design can improve the uniformity of the arrangement of the second-type pixel opening 612 and the data signal line DL.
  • the manufacturing difficulty of the second-type pixel opening 612 can be reduced under the condition of avoiding color shift in the effective light-emitting area defined by the second-type pixel opening 612, thereby When further ensuring the display quality of the display panel 100 , the manufacturing process of the display panel 100 is simplified.
  • the third type of pixel opening 613 is a mirror surface symmetry.
  • Such a design can improve the uniformity of the arrangement of the third type pixel opening 613 and the data signal line DL, thereby further ensuring the display quality of the display panel 100 .
  • the second via hole 91 is formed on the second flat layer 9 that is closer to the pixel defining layer 6 than the first flat layer 7 , and the edge of the second via hole 91 is on the substrate.
  • the distance between the orthographic projection of the edge of the pixel opening 61 on the substrate 1 and the orthographic projection of the edge of the pixel opening 61 on the substrate 1 is smaller than the orthographic projection of the edge of the first via hole 71 on the substrate 1 and the edge of the pixel opening 61 on the substrate 1 The distance between the orthographic projections of .
  • the second via hole 91 needs to be made near the portion of the first electrode 31 exposed by the pixel opening 61, a certain inclination appears in this portion because it is in the transition region between the flat surface and the concave surface, thereby reducing the The flatness of the part will adversely affect the flatness of the light emitting functional layer 4 disposed above the part, reducing the uniformity of light emission of the display panel 100 as a whole.
  • the orthographic projection of the edge of the second via hole 91 on the substrate 1 may at least partially overlap with the orthographic projection of the edge of the pixel opening 61 on the substrate 1 .
  • the second via hole 91 since the second via hole 91 is just located at the part where the first electrode 31 is exposed by the pixel opening 61, it has a greater influence on the flatness of this part, that is, it has a greater influence on the uniformity of light emission of the display panel 100 as a whole. The impact is greater.
  • the orthographic projection of the edge of the first via hole 71 on the substrate 1 and the edge of the pixel opening 61 on the substrate 1 The minimum distance between the orthographic projections of is smaller than the minimum distance between the orthographic projections of the edge of the second via hole 91 on the substrate 1 and the orthographic projection of the edge of the pixel opening 61 on the substrate 1 .
  • the second via hole 91 in the same sub-pixel region P, by making the second via hole 91 farther away from the pixel opening 61 than the first via hole 71, the exposure of the first electrode 31 by the pixel opening 61 is avoided.
  • the position is affected by the second via hole 91 , which ensures the flatness of the position and further prevents the light-emitting functional layer 4 disposed above the position from being adversely affected, thereby improving the uniformity of light emission of the display panel 100 as a whole.
  • first via hole 71 is closer to the pixel opening 61 than the second via hole 91, since the first via hole 71 is covered with the second flat layer 9, the second flat layer 9 can The hole 71 plays a flat role, so the first via hole 71 does not affect the flatness of the portion of the first electrode 31 exposed by the pixel opening 61 .
  • the first via hole 71 and the second via hole 91 are located on the same side of the pixel opening 61 .
  • the orthographic projection of the edge of the first via hole 71 on the substrate 1 is different from the orthographic projection of the edge of the second via hole 91 on the substrate 1. overlapping.
  • the minimum distance between the orthographic projection of the edge of the first via hole 71 on the substrate 1 and the orthographic projection of the edge of the second via hole 91 on the substrate 1 may not be less than 1.3 ⁇ m.
  • the exposure position is shifted, which ultimately ensures a sufficient contact area between the first electrode 31 and the conductive connection layer 8 , avoiding the occurrence of disconnection.
  • the orthographic projection of the edge of the first via hole 71 on the substrate 1 is approximately rectangular, circular or oval. Such a design can make the shape of the first via hole 71 more regular, thereby reducing the difficulty of making the conductive connection layer 8 on the side away from the substrate 1 .
  • the corners of the rectangle may be rounded as shown in FIG. 19A , or may be right angles.
  • the depth of the first via hole 71 is 1.6 ⁇ m ⁇ 2 ⁇ m. Such design can improve the uniformity of the first via hole 71 during exposure and the uniformity of etching.
  • the orthographic projection of the edge of the second via hole 91 on the substrate 1 is approximately rectangular, circular or oval. Such a design can make the shape of the second via hole 91 more regular, and reduce the difficulty of making the first electrode layer 3 on the side away from the substrate 1 .
  • the corners of the rectangle may be rounded as shown in FIG. 19A , or may be right angles.
  • the depth of the second via hole 91 is 1.6 ⁇ m ⁇ 2 ⁇ m. Such a design can improve the uniformity of the exposure and etching of the second via hole 91 .
  • the metal film layers under the first via holes 71 are substantially the same.
  • each first via hole 71 by controlling the metal film layer under each first via hole 71 to be approximately the same, the uniformity of each first via hole 71 during exposure and etching can be improved.
  • the metal film layer below the second via hole 91 corresponding to the first type pixel opening 611 and the second via hole 91 corresponding to the second type pixel opening 612 are substantially the same.
  • the second via hole 91 can be improved.
  • the metal film layer below the second via hole 91 corresponding to the third type of pixel opening 613 is substantially the same.
  • the metal film layer below the second via hole 91 corresponding to the third type of pixel opening 613 by controlling the metal film layer below the second via hole 91 corresponding to the third type of pixel opening 613 to be approximately the same, the consistency of the second via hole 91 during exposure and the uniformity during etching can be improved. sex.
  • the shape and size of a via hole 71 are substantially the same; and/or, the second via hole 91 in the sub-pixel area P where the first type pixel opening 611 is located is the same as the second via hole 91 in the sub-pixel area P where the second type pixel opening 612 is located.
  • the shapes and sizes of the second via holes 91 are approximately the same; and/or, the shapes and sizes of the first via holes 71 in the two sub-pixel regions P where the two adjacent third-type pixel openings 613 are located are approximately the same; And/or, the shapes and sizes of the second via holes 91 in the two sub-pixel regions P where the two adjacent third-type pixel openings 613 are located are substantially the same.
  • the first via hole 71 (or the second via hole 91 ) in the sub-pixel region P where the first-type pixel opening 611 is located and the sub-pixel region P where the second-type pixel opening 612 is located.
  • the shapes and sizes of the first via holes 71 (or the second via holes 91) are substantially the same, and the first via holes 71 ( Or the shape and size of the second via hole 91) are substantially the same, which can improve the consistency of the first via hole 71 (or the second via hole 91) during exposure and the uniformity during etching.
  • the edge of the first via hole 71 in the sub-pixel region P where the first-type pixel opening 611 is located defines the first region M1; the sub-pixel region P where the second-type pixel opening 612 is located
  • the edge of the first via hole 71 in the center defines the second region M2; in all the metal layers 22, the total thickness of the parts located in the first region M1 is substantially the same as the total thickness of the parts located in the second region M2.
  • the total number of layers located in the first region M1 is the same as the total number of layers located in the second region M2 .
  • the total number of layers located in the first region M1 and the total number of layers located in the second region M2 are both one layer.
  • the parts located in the first region M1 and the parts located in the second region M2 are approximately the same in shape and size.
  • the thickness of the metal film layer under the first via hole 71 in the sub-pixel region P where the pixel opening 611 is located is substantially the same as that of the metal film layer under the first via hole 71 in the sub-pixel region P where the second-type pixel opening 612 is located.
  • the shape and size of the first via holes 71 in the sub-pixel region P where the first-type pixel openings 611 are located and the first via holes 71 in the sub-pixel region P where the second-type pixel openings 612 are located are substantially the same, Finally, its consistency in exposure and uniformity in etching are improved.
  • the edge of the second via hole 91 in the sub-pixel region P where the first-type pixel opening 611 is located defines a third region M3; the sub-pixel region where the second-type pixel opening 612 is located
  • the edge of the second via hole 91 in P defines a fourth region M4; in all metal layers 22, the total thickness of the parts located in the third region M3 is substantially the same as the total thickness of the parts located in the fourth region M4.
  • the total number of layers in the third region M3 is the same as that in the fourth region M4 .
  • the total number of layers located in the third region M3 and the total number of layers located in the fourth region M4 are two.
  • the shapes and sizes of the parts located in the third region M3 and the parts located in the second region M4 are substantially the same.
  • the thickness of the metal film layer under the second via hole 91 in the sub-pixel region P where the pixel opening 611 is located is approximately the same as that of the metal film layer under the second via hole 91 in the sub-pixel region P where the second-type pixel opening 612 is located.
  • the shape and size of the second via holes 91 in the sub-pixel region P where the first-type pixel openings 611 are located and the second via holes 91 in the sub-pixel region P where the second-type pixel openings 612 are located are substantially the same, Finally, its consistency in exposure and uniformity in etching are improved.
  • the edge of the first via hole 71 in the sub-pixel region P where the third-type pixel opening 613 is located defines a fifth region M5;
  • the total thickness of the two parts of the fifth region M5 is substantially the same.
  • the total number of layers in two parts located in two adjacent fifth regions M5 is the same.
  • the total number of layers in the two parts located in the two adjacent fifth regions M5 is one layer.
  • the total thickness, the total number of layers, and even the shape and size of the two parts of the two adjacent fifth regions M5 in all metal layers 22 to be the same, so that the adjacent two The thickness of the metal film layer under the first via hole 71 in the two sub-pixel regions P where the third-type pixel opening 613 is located is approximately the same, so that two sub-pixel regions P where two adjacent third-type pixel openings 613 are located.
  • the shapes and sizes of the first via holes 71 are substantially the same, which finally further improves the uniformity during exposure and the uniformity during etching.
  • the edge of the second via hole 91 in the sub-pixel region P where the third-type pixel opening 613 is located defines a sixth region M6;
  • the total thickness of the two parts of the sixth region M6 is substantially the same.
  • the total number of layers in the two positions located in two adjacent sixth regions M6 is the same.
  • the total number of layers in the two parts located in the two adjacent sixth regions M6 is two layers.
  • the thickness of the metal film layer under the second via hole 91 in the two sub-pixel regions P where the third-type pixel opening 613 is located is approximately the same, so that two sub-pixel regions P where two adjacent third-type pixel openings 613 are located.
  • the shapes and sizes of the second via holes 91 are substantially the same, which further improves the uniformity during exposure and the uniformity during etching.
  • the first via hole 71 corresponding to each pixel opening 61 is located on a straight line O1 extending along the first direction X, each pixel opening
  • the second via holes 91 corresponding to 61 are alternately located on both sides of the same straight line O1 extending along the first direction X along the first direction X.
  • each The second via holes 91 corresponding to the pixel openings 61 are alternately located on both sides of the same straight line O1 extending along the first direction X along the first direction X. As shown in FIG. 19B , in two adjacent rows of pixel openings 61 , the geometric center of the first via hole 71 corresponding to each pixel opening 61 is located on a straight line O1 extending along the first direction X, each The second via holes 91 corresponding to the pixel openings 61 are alternately located on both sides of the same straight line O1 extending along the first direction X along the first direction X. As shown in FIG.
  • the first via holes 71 corresponding to each pixel opening 61 are respectively located at the same position in the respective corresponding pixel driving circuits 21 ;
  • the second via hole 91 corresponding to the pixel opening 611 and the second via hole 91 corresponding to the second-type pixel opening 612 are respectively located at the same position in the corresponding pixel driving circuit 21 .
  • the second via holes 91 corresponding to the third-type pixel openings 613 are respectively located at the same positions in the corresponding pixel driving circuits 21 .
  • the distance between the first via hole 71 and the second via hole 91 corresponding to each pixel opening 61 in the corresponding pixel driving circuit 21 relationship so that in two adjacent rows of pixel openings 61, the thickness of the metal film layer below the first via hole 71 corresponding to each pixel opening 61 is approximately the same, and the second via hole 91 corresponding to the first type of pixel opening 611 and the second via hole 91 corresponding to the first type of pixel opening 611
  • the thickness of the metal film under the second via holes 91 corresponding to the second type of pixel openings 612 is approximately the same, and even the thickness of the metal films under the second via holes 91 corresponding to the third type of pixel openings 613 is approximately the same. Improves its consistency and uniformity in exposure and etching.
  • the positions of the first via holes 71 corresponding to each pixel opening 61 in the second direction Y are different.
  • the display panel 100 further includes a light emission control signal line located in the first gate layer and extending along the first direction X, and the orthographic projection of each first via hole 71 on the substrate 1 is related to the light emission control signal line The overlapping areas of the orthographic projections of the lines on the substrate are all equal.
  • the first via hole 71 corresponding to each pixel opening 61 and the second via hole 91 corresponding to each pixel opening 61 are located along the second direction Y. Extended on the same straight line O2.
  • the first via hole 71 corresponding to the first type pixel opening 611 arranged along the first direction X and adjacent to the first type pixel opening 612 corresponds to the first via hole 71 corresponding to the second type pixel opening 612.
  • the line connecting the geometric centers forms the second virtual straight line S2;
  • the line connecting the geometric centers of the first via holes 71 corresponding to the two second-type pixel openings 613 arranged along the first direction X and adjacent to each other forms the third virtual straight line S3;
  • the angle between the second virtual straight line S2 and the third virtual straight line S3 ranges from 0° to 30°.
  • the distance between the second virtual straight line S2 and the third virtual straight line S3 is smaller than that of the first via hole 71 in the second direction Y size of.
  • the first via holes 71 corresponding to each pixel opening 61 are arranged sequentially along the first direction X, and/or, the first via holes 71 corresponding to each pixel opening 61
  • the second via holes 91 are arranged in sequence along the first direction X.
  • first via holes 71 (or second via holes 91) are arranged in sequence along the first direction X.
  • the corresponding first via holes 71 may, for example, be located on the same straight line, or may not be located on the same straight line.
  • the centers of the first via holes 71 in the same row have no spacing in the second direction Y (that is, the centers of the first via holes 71 in the same row are located on the same straight line); and Or, the centers of the second via holes 91 in the same row have no spacing in the second direction Y (that is, the centers of the second via holes 91 in the same row are located on the same straight line).
  • the centers of the first via holes 71 in the same row have a certain distance in the second direction Y (that is, the centers of the first via holes 71 in the same row are not located on the same straight line). It may be less than or equal to half the size of the first via hole 71 in the second direction Y; and/or, the centers of the second via holes 91 in the same row have a certain distance in the second direction Y (that is, the same row Centers of the second via holes 91 are not located on the same straight line), the distance may be less than or equal to half of the size of the second via holes 91 in the second direction Y, for example.
  • the first via holes 71 corresponding to each pixel opening 61 are arranged in sequence along the same first direction X.
  • first via holes 71 are arranged sequentially along the same first direction X. At this time, in the same row of pixel openings 61, the centers of the first via holes 71 corresponding to the pixel openings 61 may be located on the same straight line, for example. on, or may not lie on the same straight line.
  • the centers of the first via holes 71 in the same row have a certain distance in the second direction Y (that is, the centers of the first via holes 71 in the same row are not located on the same straight line ), the distance may be less than or equal to half of the size of the first via hole 71 in the second direction Y, for example.
  • the centers of the first via holes 71 in the same row have no spacing in the second direction Y (that is, the centers of the first via holes 71 in the same row are located on the same straight line).
  • the center of the via hole 71 (or the second via hole 91 ) has no pitch in the second direction Y, so that in all the metal layers 22, each part located in the first region M1 and the first region on the same row as the first region M1
  • the shapes and sizes of the parts of the second region M2 (or the parts of the third region M3 and the parts of the fourth region M4 on the same row as the third region M3) are substantially the same, and the fifth region M5 located in the same row
  • the shape and size of each part in (or each part in the sixth region M6 in the same row) are approximately the same, so that the thickness of the metal film layer under the first via hole 71 (or second via hole 91) in the same row are approximately the same, so that the shapes and sizes of the first via holes
  • the first via holes 71 corresponding to each pixel opening 61 are arranged in sequence along the second direction Y, and/or, the first via holes 71 corresponding to each pixel opening 61
  • the second via holes 91 are arranged in sequence along the second direction Y.
  • first via holes 71 (or second via holes 91 ) are arranged in sequence along the second direction Y.
  • the first via holes 71 (or For example, the centers of the second via holes 91) may be located on the same straight line, or may not be located on the same straight line.
  • the centers of the first via holes 71 in the same column have no spacing in the first direction X (that is, the centers of the first via holes 71 in the same column are located on the same straight line); and Or, the centers of the second via holes 91 in the same row have no spacing in the first direction X (that is, the centers of the second via holes 91 in the same row are located on the same straight line).
  • the centers of the first via holes 71 in the same column have a certain distance in the first direction X (that is, the centers of the first via holes 71 in the same column are not located on the same straight line). It may be less than or equal to half the size of the first via hole 71 in the first direction X; and/or, the centers of the second via holes 91 in the same column have a certain distance in the first direction X (that is, the The centers of the second via holes 91 are not located on the same straight line), for example, the distance may be less than or equal to half of the size of the second via holes 91 in the first direction X.
  • the center of the via hole 71 (or the second via hole 91) has no pitch in the first direction X, so that in all the metal layers 22, each part located in the first region M1 and the first region in the same column as the first region M1
  • the shapes and sizes of the parts of the second region M2 (or the parts of the third region M3 and the parts of the fourth region M4 on the same row as the third region M3) are substantially the same, and the fifth region M5 located in the same row
  • the shape and size of each part in (or each part in the sixth region M6 in the same column) are approximately the same, so that the thickness of the metal film layer under the first via hole 71 (or second via hole 91) in the same row are approximately the same, so that the shapes and sizes of the first via holes
  • the center of the above-mentioned first via hole 71 may be, for example, the geometric center of the first via hole 71 .
  • the center of the above-mentioned second via hole 91 may be, for example, the geometric center of the second via hole 91 .
  • the second via hole 91 in the same sub-pixel region P, firstly, by making the second via hole 91 farther away from the pixel opening 61 than the first via hole 71, the position of the first electrode 31 at the pixel opening 61 is avoided.
  • the part of the area defined by 61 is affected by the second via hole 91, which ensures the flatness of this part and further avoids the adverse effect on the light-emitting functional layer 4 arranged above this part, thereby improving the overall light emission of the display panel 100.
  • 71 (or the second via hole 91 ) in the sub-pixel region P where the first-type pixel opening 611 is located and the first via hole in the sub-pixel region P where the second-type pixel opening 612 is located, 71 (or the second via holes 91) are approximately the same in shape and size, and control the first via holes 71 (or the second via holes 91) in the two sub-pixel regions P where the adjacent two third-type pixel openings 613 are located. 91) are approximately the same in shape and size, which can improve the uniformity of the first via hole 71 (or the second via hole 91) during exposure and during etching.
  • the display panel 100 includes: a substrate 1 and a circuit structure layer 2 located on one side of the substrate 1 and away from the substrate 1 in turn, a first planar layer 7 , a conductive connection layer 8 , and a second planar layer 9 , the first electrode layer 3 and the pixel defining layer 6 .
  • the circuit structure layer 2 includes a plurality of pixel driving circuits 21; the first flat layer 7 has a plurality of first vias 71; the conductive connection layer 8 includes a plurality of conductive parts 81; the second flat layer 9 has a plurality of second vias 71; The hole 91 ; the first electrode layer 3 includes a plurality of first electrodes 31 ; the pixel defining layer 6 has a plurality of pixel openings 61 .
  • the display panel 100 has a plurality of sub-pixel regions P.
  • the pixel opening 61 exposes at least part of the first electrode 31, the first electrode 31 is electrically connected to the conductive part 81 through the second via hole 91, and the conductive part 81 passes through the second via hole 91.
  • a via hole 71 is electrically connected to the pixel drive circuit 21; the minimum distance between the orthographic projection of the edge of the first via hole 71 on the substrate 1 and the orthographic projection of the edge of the pixel opening 61 on the substrate 1 is smaller than the second The minimum distance between the orthographic projection of the edge of the via hole 91 on the substrate 1 and the orthographic projection of the edge of the pixel opening 61 on the substrate 1 .
  • the second via hole 91 in the same sub-pixel region P, by making the second via hole 91 farther away from the pixel opening 61 than the first via hole 71, the portion of the first electrode 31 exposed by the pixel opening 61 is avoided. Affected by the second via hole 91 , the flatness of this portion is ensured, further avoiding adverse effects on the light-emitting functional layer 4 disposed above this portion, thereby improving the overall uniformity of light emission of the display panel 100 .
  • first via hole 71 is closer to the pixel opening 61 than the second via hole 91, since the first via hole 71 is covered with the second flat layer 9, the second flat layer 9 can The hole 71 plays a flat role, so the first via hole 71 does not affect the flatness of the portion of the first electrode 31 exposed by the pixel opening 61 .

Abstract

一种显示面板（100），包括依次层叠的衬底（1）、电路结构层（2）、第一电极层（3）和像素界定层（6）。电路结构层（2）包括多个像素驱动电路（21），第一电极层（3）包括多个第一电极（31），第一电极（3）与像素驱动电路（21）电连接；像素界定层（6）具有多个像素开口（61），像素开口（61）露出第一电极（31）的至少部分。至少一个第一电极（31）在衬底（1）上的正投影，和第一电极（31）所对应的像素驱动电路（21）中的数据补偿晶体管（T2）的栅极在衬底（1）上的正投影至少部分交叠，同时和与第一电极（31）所对应的像素驱动电路（21）相邻的至少一个像素驱动电路（21）中的数据补偿晶体管（T2）的栅极在衬底（1）上的正投影至少部分交叠；至少一个第一电极（31）所对应的像素开口（61）在衬底（1）上的正投影和第一电极（31）所对应的像素驱动电路（21）中的数据补偿晶体管（T2）的栅极在衬底（1）上的正投影分离。

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，例如涉及一种显示面板及显示装置。
背景技术
有机电致发光二极管(Organic Light-Emitting Diode，简称OLED)显示面板板凭借其低功耗、高色饱和度、广视角、薄厚度、能实现柔性化等优异性能，逐渐成为显示领域的主流之一。
发明内容
一方面，提供一种显示面板。所述显示面板包括衬底、电路结构层、第一电极层和像素界定层。所述电路结构层位于所述衬底的一侧，所述电路结构层包括多个像素驱动电路；所述多个像素驱动电路沿第一方向排列构成像素驱动电路行，所述多个像素驱动电路行沿第二方向依次排列；所述第一方向和所述第二方向相交。所述第一电极层位于所述电路结构层远离所述衬底的一侧，所述第一电极层包括多个第一电极；一个第一电极与一个像素驱动电路电连接。所述像素界定层位于所述第一电极层远离所述衬底的一侧，所述像素界定层具有多个像素开口；一个像素开口露出一个第一电极的至少部分。其中，所述像素驱动电路包括驱动晶体管和数据补偿晶体管。至少一个第一电极在所述衬底上的正投影，和该第一电极所对应的像素驱动电路中的数据补偿晶体管的栅极在所述衬底上的正投影至少部分交叠，同时和与该第一电极所对应的像素驱动电路相邻的至少一个像素驱动电路中的数据补偿晶体管的栅极在所述衬底上的正投影至少部分交叠；所述至少一个第一电极所对应的像素开口在所述衬底上的正投影和该第一电极所对应的像素驱动电路中的数据补偿晶体管的栅极在所述衬底上的正投影分离。对于所述至少一个第一电极中的一个第一电极：和该第一电极所对应的数据补偿晶体管在所述衬底上的正投影与沿所述第一方向延伸的第一虚拟直线具有第一交叠部分；和该第一电极所对应的像素驱动电路相邻的像素驱动电路中的数据补偿晶体管在所述衬底上的正投影与所述第一虚拟直线具有第二交叠部分；所述第一交叠部分与所述第二交叠部分在所述第一方向上的间隔尺寸大于所述第一交叠部分所对应的像素开口在所述第一方向上的尺寸。
在一些实施例中，所述多个像素开口排列成多行多列；相邻的两行像素开口沿所述第一方向彼此错开；相邻的两行像素开口中，一行像素开口包括沿所述第一方向交替排列的第一种像素开口和第二种像素开口，另一行像素 开口包括沿所述第一方向依次排列的第三种像素开口；相邻的两列像素开口中，一列像素开口包括沿所述第二方向交替排列的第一种像素开口和第二种像素开口，另一列像素开口包括沿所述第二方向依次排列的第三种像素开口。其中，所述第一种像素开口的开口面积小于所述第二种像素开口的开口面积，且所述第一种像素开口的开口面积大于所述第三种像素开口的开口面积。
在一些实施例中，在所述第一种像素开口和所述第二种像素开口交替排列所形成的任一行像素开口中，任一第一种像素开口和与该第一种像素开口相邻的两个第二种像素开口之间的距离相等。在所述第一种像素开口和所述第二种像素开口交替排列所形成的任一列像素开口中，任一第一种像素开口和与该第一种像素开口相邻的两个第二种像素开口之间的距离不相等。
在一些实施例中，一列所述像素开口中相邻的所述第一种像素开口和所述第二种像素开口与相邻列所述像素开口中相邻的所述第一种像素开口和所述第二种像素开口四者的几何中心依次连接构成虚拟梯形。
在一些实施例中，在同一行像素开口中，所述第一种像素开口的中心和所述第二种像素开口的中心在所述第二方向上具有间距。
在一些实施例中，所述间距小于或等于所述第一种像素开口在所述第二方向上的尺寸的一半。
在一些实施例中，所述第一种像素开口所对应的第一电极在所述衬底上的正投影，和该第一电极所对应的像素驱动电路中的数据补偿晶体管的栅极在所述衬底上的正投影至少部分交叠，同时和与该第一电极所对应的像素驱动电路相邻的至少一个像素驱动电路中的数据补偿晶体管的栅极在所述衬底上的正投影至少部分交叠；和/或，所述第二种像素开口所对应的第一电极在所述衬底上的正投影，和该第一电极所对应的像素驱动电路中的数据补偿晶体管的栅极在所述衬底上的正投影至少部分交叠，同时和与该第一电极所对应的像素驱动电路相邻的至少一个像素驱动电路中的数据补偿晶体管的栅极在所述衬底上的正投影至少部分交叠。
在一些实施例中，所述第一种像素开口在所述衬底上的正投影和该第一种像素开口所对应的像素驱动电路中的数据补偿晶体管的栅极在所述衬底上的正投影分离；和/或，所述第三种像素开口在所述衬底上的正投影和该第三种像素开口所对应的像素驱动电路中的数据补偿晶体管的栅极在所述衬底上的正投影分离。
在一些实施例中，所述第一种像素开口和所述第三种像素开口沿第三方向交替排列成第一组像素开口，所述第二种像素开口和所述第三种像素开口 沿第三方向交替排列成第二组像素开口，所述第一组像素开口和所述第二组像素开口在第四方向上交替排列；所述第三方向与所述第四方向相交。其中，在所述第一组像素开口中，所述第一种像素开口所对应的第一电极在所述衬底上的正投影，和与该第一种像素开口相邻的一个第三种像素开口所对应的像素驱动电路中的数据补偿晶体管的栅极在所述衬底上的正投影至少部分交叠；在所述第二组像素开口中，所述第二种像素开口所对应的第一电极在所述衬底上的正投影，和与该第二种像素开口相邻的一个第三种像素开口所对应的数据补偿晶体管的栅极在所述衬底上的正投影至少部分交叠。
在一些实施例中，相邻的所述第一种像素开口和所述第二种像素开口两者所对应的两个第一电极在所述衬底上的正投影，分别和位于该相邻的所述第一种像素开口和所述第二种像素开口两者同一侧的两个第三种像素开口所对应的数据补偿晶体管的栅极在所述衬底上的正投影至少部分交叠。
在一些实施例中，所述显示面板具有显示区；最靠近所述显示区的边界的多个像素开口包括至少一行沿所述第一方向交替排列的所述第一种像素开口和所述第二种像素开口，和/或，至少一列沿所述第二方向交替排列的所述第一种像素开口和所述第二种像素开口。
在一些实施例中，所述第一种像素开口被配置为限定第一颜色光线的有效发光区域，所述第二种像素开口被配置为限定第二颜色光线的有效发光区域，所述第三种像素开口被配置为限定第三颜色光线的有效发光区域。所述第一颜色光线为红色光线，所述第二颜色光线为蓝色光线，所述第三颜色光线为绿色光线。
在一些实施例中，所述电路结构层包括依次远离所述衬底的有源层、第一栅极层、第二栅极层和源漏电极层。所述显示面板还包括位于所述电路结构层与所述第一电极层之间的导电连接层。所述显示面板包括给所述第一电极提供复位信号的多条复位信号线。所述多条复位信号线包括：位于所述第二栅极层且沿所述第一方向延伸的第一复位信号线以及位于所述源漏电极层或所述导电连接层且沿所述第二方向延伸的第二复位信号线。所述第一复位信号线与所述第二复位信号线在所述衬底上的正投影交叠，在交叠位置，所述第一复位信号线与所述第二复位信号线通过过孔电连接；在所述第一复位信号线位于所述第二栅极层，所述第二复位信号线位于所述源漏电极层时，所述第二复位信号线与所述有源层通过过孔连接。
在一些实施例中，所述显示面板还包括多条电源信号线。所述多条电源信号线包括：位于所述源漏电极层且沿所述第二方向延伸的第一电源信号线 以及位于所述导电连接层且沿所述第二方向延伸的第二电源信号线。所述第一电源信号线和所述第二电源信号线电连接，所述第一电源信号线和所述第二电源信号线在所述衬底上的正投影交叠，至少一个像素开口在所述衬底上的正投影位于所述第二电源信号线在所述衬底上的正投影范围内。
在一些实施例中，所述第二电源信号线具有多个突出部，一个突出部在所述衬底上的正投影与一个第一电极所对应的像素开口在所述衬底上的正投影至少部分交叠。
在一些实施例中，所述显示面板还包括：位于所述导电连接层中、且沿所述第二方向延伸的多条数据信号线，所述多条数据信号线沿所述第一方向依次排列。所述第一种像素开口、所述第二种像素开口和所述第三种像素开口被配置为按照以下至少一种方式设置：所述第一种像素开口在所述衬底上的正投影位于相邻的两条数据信号线在所述衬底上的正投影之间；或者，所述第二种像素开口在所述衬底上的正投影位于相邻的两条数据信号线在所述衬底上的正投影之间；或，相邻的两条数据信号线在所述衬底上的正投影均与所述第二种像素开口在所述衬底上的正投影部分重叠，所述相邻的两条数据信号线在所述衬底上的正投影与所述第二种像素开口在所述衬底上的正投影的两个重叠部分的面积大致相同；或者，所述第三种像素开口在所述衬底上的正投影位于相邻的两条数据信号线在所述衬底上的正投影之间。
在一些实施例中，所述第一种像素开口、所述第二种像素开口和所述第三种像素开口被配置为按照以下至少一种方式设置：以所述相邻的两条数据信号线的平分面为对称面，所述第一种像素开口呈镜面对称；或者，以所述相邻的两条数据信号线的平分面为对称面，所述第二种像素开口呈镜面对称；或者，以所述相邻的两条数据信号线的平分面为对称面，所述第三种像素开口呈镜面对称。
在一些实施例中，所述显示面板还包括：位于所述电路结构层和所述第一电极层之间且依次远离所述衬底的第一平坦层、导电连接层和第二平坦层。其中，所述第一平坦层上具有多个第一过孔；所述导电连接层包括多个导电部；所述第二平坦层上具有多个第二过孔。所述显示面板具有多个子像素区域，在子像素区域中：第一电极通过第二过孔与导电部电连接，导电部通过第一过孔与像素驱动电路电连接；所述第一过孔的边缘在所述衬底上的正投影与所述像素开口在所述衬底上的正投影之间的最小距离，小于所述第二过孔的边缘在所述衬底上的正投影与所述像素开口在所述衬底上的正投影之间的最小距离。
在一些实施例中，在相邻的两行像素开口中，各像素开口所对应的第一过孔位于沿所述第一方向延伸的一条直线上，各像素开口所对应的第二过孔沿所述第一方向交替位于所述沿所述第一方向延伸的同一直线的两侧。
在一些实施例中，在相邻的两行所述像素开口中，各像素开口所对应的第一过孔分别位于各自对应的像素驱动电路中的相同位置；所述第一种像素开口所对应的第二过孔和所述第二种像素开口所对应的第二过孔分别位于各自对应的像素驱动电路中的相同位置。
在一些实施例中，在相邻的两行所述像素开口中，各像素开口所对应的第一过孔在所述第二方向上的位置不同；所述显示面板还包括位于第一栅极层中且沿所述第一方向延伸的发光控制信号线，各所述第一过孔在所述衬底上的正投影与所述发光控制信号线在所述衬底上的正投影的交叠面积均大致相等。
在一些实施例中，在同一列所述像素开口中，各像素开口所对应的第一过孔和各像素开口所对应的第二过孔位于沿所述第二方向延伸的同一直线上。
再一方面，提供一种显示装置。所述显示装置包括：如上述任一实施例所述的显示面板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为本公开一些实施例提供的一种显示装置的结构图；
图2为本公开一些实施例提供的一种显示面板的结构图；
图3为图2中A-A′处的一种截面结构图；
图4为本公开一些实施例提供的另一种显示面板的结构图；
图5A为本公开一些实施例提供的又一种显示面板的结构图；
图5B为本公开一些实施例提供的一个子像素区域处的源漏金属层、导电连接层与第一电极层的一种位置关系图；
图6A为图5A中一个子像素区域处的有源层与第一栅极层的一种位置关系图；
图6B为本公开一些实施例提供的一个子像素区域处的有源层与第一栅极层的另一种位置关系图；
图6C为本公开一些实施例提供的一个子像素区域处的有源层与第一栅极层的又一种位置关系图；
图6D为图5A中两个子像素区域处的有源层与第一栅极层的一种位置关系图；
图7为图5A中一个子像素区域处的等效电路图；
图8A为图5A中一个子像素区域处的有源层、第一栅极层与第二栅极层的一种位置关系图；
图8B为本公开一些实施例提供的一个子像素区域处的有源层、第一栅极层、第二栅极层、源漏金属层与导电连接层的一种位置关系图；
图8C为本公开一些实施例提供的一个子像素区域处的有源层、第一栅极层、第二栅极层、源漏金属层与导电连接层的另一种位置关系图；
图9为图5A中有源层、第一栅极层、第二栅极层与源漏金属层的一种位置关系图；
图10为图5A中有源层、第一栅极层、第二栅极层、源漏金属层与导电连接层的一种位置关系图；
图11为本公开一些实施例提供的一种像素开口的排列图；
图12为本公开一些实施例提供的另一种像素开口的排列图；
图13为本公开一些实施例提供的再一种像素开口的排列图；
图14为本公开一些实施例提供的又一种像素开口的排列图；
图15为本公开一些实施例提供的又一种像素开口的排列图；
图16为本公开一些实施例提供的又一种像素开口的排列图；
图17为本公开一些实施例提供的又一种显示面板的结构图；
图18为图2中A-A′处的另一种截面结构图；
图19A为本公开一些实施例提供的像素开口、第一过孔与第二过孔的一种位置关系图；
图19B为本公开一些实施例提供的像素开口、第一过孔与第二过孔的另一种位置关系图；
图19C为本公开一些实施例提供的像素开口、第一过孔与第二过孔的又一种位置关系图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地 描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本文所使用的那样，“平行”、“垂直”、“相同”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相同”包括绝对相同和近似相同，其中近似相同的可接受偏差范围内例如可以是相同的两者之间的差值小于或等于其中任一者的5％。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本公开一些实施例提供了一种显示装置1000。请参阅图1，该显示装置1000包括显示面板100。
需要说明的是，上述显示装置1000的类型包括多种，例如可以为有机发光二极管(Organic Light-Emitting Diode，简称OLED)显示装置、量子点发光二极管(Quantum Dot Light Emitting Diodes，简称QLED)显示装置或发光二极管(Light Emitting-Diodes，简称LED)显示装置等。其中，该有机发光二极管(Organic Light-Emitting Diode，简称OLED)显示装置例如可以包括有源矩阵有机发光二极体(Active Matrix/Organic Light Emitting Diode，简称AMOLED)显示装置。
上述显示装置1000的产品形式也包括多种，例如可以为显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是图像的任何装置。更明确地说，上述显示装置1000可设置在多种电子装置中或与多种电子装置关联，上述多种电子装置例如可以为(但不限于)移动电话、无线装置、个人数据 助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如可以为里程表显示器)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如可以为车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如可以为对于一件珠宝的图像的显示器)等。
请参阅图2，本公开一些实施例提供了一种显示面板100，该显示面板100可以应用于上述显示装置1000中。当然，该显示面板100也可以应用于其它的装置中。
在一些示例中，请参阅图2，该显示面板100具有位于虚线框内的显示区A和位于虚线框外的周边区B。其中，显示面板100中位于显示区A的部位能够进行图像显示。
需要说明的是，本公开对周边区B的设置位置不做限制。例如，周边区B可以位于显示区A的一侧、两侧或三侧等。又例如，周边区B也可以围绕显示区A一圈。
上述显示面板100的类型可以有多种，例如可以为OLED显示面板、QLED显示面板或LED显示面板等。其中，OLED显示面板例如可以包括AMOLED显示面板。
在一些示例中，请继续参阅图2，该显示面板100具有多个子像素区域P。
示例性的，多个子像素区域P位于显示区A。
在一些实施例中，请参阅图2～图4，该显示面板100包括衬底1。
在一些示例中，衬底1可以为刚性衬底。该刚性衬底例如可以为玻璃衬底或PMMA(Polymethyl methacrylate，聚甲基丙烯酸甲酯)衬底等。
在另一些示例中，衬底1可以为柔性衬底。该柔性衬底例如可以为PET(Polyethylene terephthalate，聚对苯二甲酸乙二醇酯)衬底、PI(Polyimide，聚酰亚胺)衬底或PEN(Polyethylene naphthalate two formic acid glycol ester，聚萘二甲酸乙二醇酯)衬底等。
在一些实施例中，请参阅图3，该显示面板100还包括位于衬底1的一侧且依次远离衬底1的电路结构层2和第一电极层3。电路结构层2包括多个像素驱动电路21，第一电极层3包括多个第一电极31，一个第一电极31与一个像素驱动电路21电连接。
在一些示例中，第一电极31与像素驱动电路21之间直接电连接。
示例性的，该显示面板100还包括位于电路结构层2和第一电极层3之 间的平坦层，该平坦层上具有多个过孔；一个第一电极31通过一个过孔与一个像素驱动电路21电连接。
在另一些示例中，请继续参阅图3，该显示面板100还包括位于电路结构层2和第一电极层3之间的导电连接层8，导电连接层8包括多个导电部81，一个第一电极31通过一个导电部81与一个像素驱动电路21间接电连接。
示例性的，请继续参阅图3，该显示面板100还包括第一平坦层7和第二平坦层9。第一平坦层7位于电路结构层2和导电连接层8之间，该第一平坦层7上具有多个第一过孔71。第二平坦层9位于导电连接层8和第一电极层3之间，该第二平坦层9上具有多个第二过孔91。一个导电部81通过一个第一过孔71与一个像素驱动电路21电连接，一个第一电极31通过一个第二过孔91与一个导电部81电连接。
在一些示例中，请参阅图4，显示面板100还包括多条栅线GL和多条数据信号线DL。其中，多条栅线GL沿第一方向X延伸，并沿第二方向Y依次排列；多条数据信号线DL沿第二方向Y延伸，并沿第一方向X依次排列。
示例性的，多条数据信号线DL位于多条栅线GL远离衬底1的一侧，且多条数据信号线DL与多条栅线GL之间相互绝缘。
示例性的，在显示面板100包括导电连接层8的情况下，多条数据信号线DL位于导电连接层8中。
示例性的，在显示面板100包括电路结构层2的情况下，多条栅线GL可以与电路结构层2中的至少一层金属层同层设置。
需要说明的是，上述一些示例中提及的“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。这样一来，可以在一次构图工艺中，同时制备形成上述数据信号线DL和导电连接层8，以及同时制备形成上述栅线GL和电路结构层2中的任意一层金属层，从而有利于简化显示面板100的制备工艺。
在一些示例中，请继续参阅图4，多条栅线GL和多条数据信号线DL相互交叉设置，限定出多个子像素区域P，多个子像素区域P与多个像素驱动电路21一一对应。
示例性的，可以把沿第一方向X排列成一行的子像素区域P称为同一行子像素区域P，可以把沿第二方向Y排列成一列的子像素区域P称为同一列 子像素区域P。
在此基础上，请继续参阅图4，多个像素驱动电路21沿第一方向X排列构成像素驱动电路行I1，多个像素驱动电路行I1沿第二方向Y依次排列；多个像素驱动电路21沿第二方向Y排列构成像素驱动电路行I2，多个像素驱动电路行I2沿第一方向X依次排列；其中，第一方向X和第二方向Y相交(例如，第一方向X和第二方向Y垂直)。
示例性的，同一个像素驱动电路行I1中的各像素驱动电路21可以与一条栅线GL电连接，同一个像素驱动电路列I2中的各像素驱动电路21可以与一条数据信号线DL电连接。其中，栅线GL可以给与其电连接的同一行像素驱动电路21提供扫描信号，数据信号线DL可以给与其电连接的同一列像素驱动电路21提供数据信号。
容易理解的是，同一个像素驱动电路行I1中的各像素驱动电路21还可以与多条栅线GL电连接，本公开各个实施例对此不做限定。
在一些示例中，请参阅图3，该显示面板100还包括位于第一电极层3远离衬底1的一侧且依次远离衬底1的发光功能层4和第二电极层5。发光功能层4包括多个发光部41，第二电极层5包括多个第二电极51。在一个子像素区域P中，一个第一电极31、一个发光部41和一个第二电极51构成一个发光器件。其中，一个像素驱动电路21与一个发光器件电连接，像素驱动电路21被配置为提供驱动电压至与其电连接的发光器件，以控制该发光器件的发光状态。
需要说明的是，第一电极31可以是阳极，也可以是阴极。对应的，第二电极51可以是阴极，也可以是阳极。示例性的，第一电极31为阳极，则第二电极51为阴极，此时，多个第一电极31构成的第一电极层3则为阳极层，多个第二电极51构成的第二电极层5则为阴极层。又示例性的，第一电极31为阴极，则第二电极51为阳极，此时，多个第一电极31构成的第一电极层3则为阴极层，多个第二电极51构成的第二电极层5则为阳极层。
上述第二电极层5例如可以为整面结构。上述发光功能层4例如可以为整面结构，或者也可以为多个块状结构。
上述发光器件例如可以为OLED(OrganicLight Emitting Diode，有机发光二极管)器件，也可以为QLED(Quantum Dot Light Emitting Diodes，量子点发光二极管)器件。上述发光器件的出光方式例如可以为顶出光。
此外，多个发光部41整体构成了发光功能层4，发光功能层4的层状结构可以包括多种，可以根据实际需要选择设置。
示例性的，发光功能层4包括发光层。
示例性的，发光功能层4还可以包括设置在阳极层和发光层之间的空穴注入层和/或空穴传输层。
示例性的，发光功能层4还可以包括设置在发光层和阴极层之间的电子传输层和/或电子注入层。
需要说明的是，上述像素驱动电路21的结构包括多种，可以根据实际需要选择设置。例如，像素驱动电路21的结构可以包括“2T1C”、“6T1C”、“7T1C”、“6T2C”或“7T2C”等。此处，“T”表示为薄膜晶体管，位于“T”前面的数字表示为薄膜晶体管的数量；“C”表示为存储电容器C，位于“C”前面的数字表示为存储电容器C的数量。
在一些示例中，请参阅图4，像素驱动电路21所包括的多个薄膜晶体管中，包括一个驱动晶体管DT和至少一个开关晶体管ST。
此处，开关晶体管ST指的是，像素驱动电路21所包括的多个薄膜晶体管中，与栅线GL电连接的薄膜晶体管。
驱动晶体管DT指的是，像素驱动电路21所包括的多个薄膜晶体管中，同时与存储电容器C、开关晶体管ST和发光器件电连接的薄膜晶体管。
需要说明的是，驱动晶体管DT与发光器件之间可以直接电连接(例如图4所示)，也可以间接电连接(例如可以在驱动晶体管DT与发光器件之间增加开关晶体管ST)。
示例性的，上述像素驱动电路21所包括的各个薄膜晶体管例如可以为底栅结构的薄膜晶体管，或者可以为顶栅结构的薄膜晶体管。
在一些实施例中，请参阅图3，显示面板100还包括位于第二电极层5和发光功能层4之间的像素界定层6，该像素界定层6包括多个像素开口61；一个像素开口61露出一个第一电极31的至少部分。
在一些示例中，请参阅图5A，多个像素开口61包括至少一个第一种像素开口611、至少一个第二种像素开口612和至少一个第三种像素开口613。
其中，第一种像素开口611被配置为限定第一颜色光线的有效发光区域，第二种像素开口612被配置为限定第二颜色光线的有效发光区域，第三种像素开口613被配置为限定第三颜色光线的有效发光区域；第一颜色光线、第二颜色光线和第三颜色光线为三基色光线。
示例性的，请参阅图5A，第一种像素开口611的开口面积小于第二种像素开口612的开口面积，第一种像素开口611的开口面积大于第三种像素开口613的开口面积。
示例性的，第一颜色光线为红色光线，第二颜色光线为蓝色光线，第三颜色光线为绿色光线。
在上述一些示例中，通过第一种像素开口611、第二种像素开口612和第三种像素开口613分别透过不同颜色的光线，可以叠加形成一个像素发光区域，从而使得该像素发光区域能够显示多种颜色的光线，并实现多灰阶(例如256灰阶)显示。在此基础上，通过调整第一种像素开口611的开口面积、第二种像素开口612的开口面积、第三种像素开口613的开口面积三者之间的大小关系，可以使显示面板100的画面显示精度较高，清晰度较好，显示效果较佳。
在一些示例中，请参阅图3，显示面板100还包括位于像素界定层6和第二电极层4之间的多个支撑垫10。
在上述一些示例中，多个支撑垫10用于对制作显示面板100时采用的掩膜版以及形成于该多个支撑垫10上方的结构进行支撑。
在一些示例中，请参阅图3，电路结构层2包括至少一层金属层22，至少一层金属层22的部分构成多个像素驱动电路21中的部分结构。
需要说明的是，上述至少一层金属层22的部分构成多个像素驱动电路21中的部分结构，例如可以为至少一层金属层22中的部分结构作为多个像素驱动电路21中的部分结构。
示例性的，请继续参阅图3，至少一层金属层22包括依次远离衬底1的第一栅极层221、第二栅极层222和源漏金属层223。
示例性的，请继续参阅图3，电路结构层2还包括有源层23、第一绝缘层24、第二绝缘层25和层间介质层26。有源层23位于第一栅极层221朝向衬底1的一侧，第一绝缘层24位于有源层23和第一栅极层221之间，第二绝缘层25位于第一栅极层221和第二栅极层222之间，层间介质层26位于第二栅极层222和源漏金属层223之间。
在一些示例中，请继续参阅图4，在一个子像素区域P中，一个像素驱动电路包括驱动晶体管DT和至少一个开关晶体管ST。
示例性的，至少一个开关晶体管ST包括数据补偿晶体管。
需要说明的是，上述数据补偿晶体管的类型包括多种，例如可以为非氧化物晶体管。
下面，以“7TIC”像素驱动电路21为例，结合图5A～图10对显示面板100的结构进行示意性说明。
在一些示例中，请参阅图5A和图6A，图5A为本公开一些实施例提供 的又一种显示面板100的结构图，图6A为图5A中一个子像素区域P处有源层23与第一栅极层221的一种位置关系图，像素驱动电路21可以包括驱动晶体管T3、第一发光控制晶体管T6、第二发光控制晶体管T5、数据写入晶体管T4、存储电容C、数据补偿晶体管T2、第一复位晶体管T7和第二复位晶体管T1。其中，数据补偿晶体管T2例如可以为开关晶体管ST。
在另一些示例中，请参阅图6B，图6B示出了另一种子像素区域处有源层(231、232)与第一栅极层221的位置关系图。此时，第二复位晶体管T1、数据补偿晶体管T2为金属氧化物晶体管，驱动晶体管T3、数据写入晶体管T4、第二发光控制晶体管T5、第一发光控制晶体管T6、第一复位晶体管T7为低温多晶硅晶体管。其中，上述低温多晶硅晶体管的有源层231位于第一栅极层221靠近衬底的一侧，上述金属氧化物晶体管的有源层232位于第一栅极层221远离衬底的一侧，例如可以位于第一栅极层221与第二栅极层222之间。这样设计，可以有效地改善第二复位晶体管T1和数据补偿晶体管T2的防漏电性能，同时有利于降低生产成本。
在又一些示例中，请参阅图6C，图6C示出了又一种子像素区域处有源层(231、232)与第一栅极层221的位置关系图。在该示例中，与上述图6B不同的是，第一复位晶体管T7也为金属氧化物晶体管，这样设计，还有利于改善第一复位晶体管T7的防漏电性能，进一步降低制作成本。
在上述一些实施例中，驱动晶体管T3例如可以为单栅结构，第一发光控制晶体管T6例如可以为单栅结构，第二发光控制晶体管T5例如可以为单栅结构，数据写入晶体管T4例如可以为单栅结构，数据补偿晶体管T2例如可以为双栅结构，第一复位晶体管T7例如可以为单栅结构，第二复位晶体管T1例如可以为双栅结构。
请参阅图7，图7为图5A中一个子像素区域处的等效电路图，驱动晶体管DT被配置为提供驱动电压至与其电连接的发光器件，以控制该发光器件的发光状态。
请参阅图9和图10，图9为图5A中有源层23、第一栅极层221、第二栅极层222与源漏金属层223的一种位置关系图，图10为图5A中有源层23、第一栅极层221、第二栅极层222、源漏金属层223与导电连接层8的一种位置关系图。
在一些示例中，如图5A所示，显示面板100包括多条数据信号线DL和多条电源信号线。多条数据信号线DL沿第二方向Y延伸。电源信号线可以与图7中的第一电压端VDD电连接以提供电压信号。电源信号线包括位于源 漏电极层223且沿第二方向Y延伸的第一电源信号线VL1。
在另一些示例中，如图5B所示，电源信号线包括位于源漏电极层223且沿第二方向Y延伸的第一电源信号线VL1和位于导电连接层8且沿第二方向Y延伸的第二电源信号线VL2。此时，第一电源信号线VL1和第二电源信号线VL2电连接，第一电源信号线VL1和第二电源信号线VL2在衬底1上的正投影交叠，至少一个像素开口61(例如，第一种像素开口611)在衬底1上的正投影位于第二电源信号线VL2在衬底1上的正投影范围内。这样设计，可以减小像素开口61与像素驱动电路21之间膜层的透光率，形成较好的光线阻挡效果；同时，还可以使像素开口61下方的第一电极31平坦，提高发光均匀性。
示例性的，请参阅图5B，第二电源信号线VL2具有多个突出部K，一个突出部K在衬底1上的正投影与一个第一电极31所对应的像素开口61在衬底1上的正投影至少部分交叠。
在该示例中，由于第二电源信号线VL2的突出部K在衬底1上的正投影与一个第一电极31所对应的像素开口61在衬底1上的正投影至少部分交叠，从而可以减小像素开口61与像素驱动电路21之间膜层的透光率，形成较好的光线阻挡效果；同时，还可以使像素开口61下方的第一电极31平坦，提高发光均匀性。
请参阅图6A和图10，显示面板100还包括位于电源信号线VL朝向衬底1一侧且彼此平行的栅线GL、发光控制信号线EM、第一复位控制信号线Rst1以及第二复位控制信号线Rst2。其中，栅线GL、发光控制信号线EM、第一复位控制信号线Rst1以及第二复位控制信号线Rst2四者的延伸方向与数据信号线DL的延伸方向相交，例如，栅线GL、发光控制信号线EM、第一复位控制信号线Rst1以及第二复位控制信号线Rst2四者的延伸方向与数据信号线DL的延伸方向垂直。
在一些示例中，请参阅图6A，第一栅极层221中的一部分构成了像素驱动电路21中驱动晶体管T3、第一发光控制晶体管T6、第二发光控制晶体管T5、数据写入晶体管T4、数据补偿晶体管T2、第一复位晶体管T7和第二复位晶体管T1七者的栅极、存储电容C中的第二极C2、以及彼此平行的栅线GL、发光控制信号线EM、第一复位控制信号线Rst1以及第二复位控制信号线Rst2。
显示面板100还包括位于栅线GL所在膜层与数据信号线DL所在膜层之间的多条复位信号线，多条复位信号线被配置为给第一电极31(即发光器件 的阳极)和/或驱动晶体管T3的栅极提供复位信号。
在一些示例中，请参阅图8A，图8A为图5A中一个子像素区域P处有源层23、第一栅极层221与第二栅极层222的一种位置关系图，多条复位信号线包括沿第一方向X延伸的第一条第一复位信号线Vint1和第二条第一复位电源信号Vint2。
在此基础上，请参阅图8B和图8C，图8B和图8C分别为本公开一些实施例提供的一个子像素区域P处的有源层23、第一栅极层221、第二栅极层222、源漏金属层223和导电连接层8的一种位置关系图，多条复位信号线例如还可以包括沿第二方向Y延伸的第一条第二复位信号线Vint1′和沿第二方向Y延伸的第二条第二复位信号线Vint2′。其中，第一条第一复位信号线Vint1与第一条第二复位信号线Vint1′电连接，用于给驱动晶体管T3的栅极进行复位；第二条第一复位信号线Vint2与第二条第二复位信号线Vint2′电连接，用于给第一电极31(即发光器件的阳极)进行复位。
在一些示例中，请参阅图8A和图8B，第二栅极层222的一部分构成了像素驱动电路21中存储电容C的第一极C1、第一条第一复位信号线Vint1以及第二条第一复位信号线Vint2。
在此基础上，示例性的，参阅图8B，源漏金属层223中的一部分构成了像素驱动电路21中的第一电源信号线VL1和第二条第二复位信号线Vint2′。此时，第二条第一复位信号线Vint2在衬底1上的正投影与第二条第二复位信号线Vint2′在衬底1上的正投影交叠，在交叠位置，第二条第一复位信号线Vint2与第二条第二复位信号线Vint2′通过过孔J1电连接。第二条第二复位信号线Vint2′与有源层23通过过孔J4连接。
在另一些示例中，如图8C所示，第二栅极层222的一部分构成了像素驱动电路21中存储电容C的第一极C1。有源层23的一部分构成第一条第一复位信号线Vint1以及第二条第一复位信号线Vint2。此时，由于有源层23的一部分构成第二条第一复位信号线Vint2，且第二条第二复位信号线Vint2′与第二条第一复位信号线Vint2电连接，因此，第二条第二复位信号线Vint2′无需再额外通过过孔连接至有源层23。
在上述一些示例的基础上，示例性的，如图8B和图8C所示，导电连接层8中的一部分构成了像素驱动电路21中的第一条第二复位信号线Vint1′。此时，显示面板100还包括位于源漏电极层223的连接块F，第一条第二复位信号线Vint1′通过过孔J2与连接块F电连接，连接块F通过过孔J3与第一条第一复位信号线Vint1电连接，从而使得第一条第一复位信号线Vint1与第 一条第二复位信号线Vint1′电连接。
需要说明的是，在图8B和图8C中，第一条第二复位信号线Vint1′以直线进行了示意，可以理解，在实际产品中，为了避免与同层设置的其它结构产生干涉，还可在该第一条第二复位信号线Vint1′上设置弯曲避让部。例如，在第一条第二复位信号线Vint1′位于导电连接层8中时，可以通过弯曲避让部对位于该导电连接层8且与第一电极31连接的转接块进行避让。又例如，在该第一条第二复位信号线Vint1′位于源漏电极层223中时，可以通过弯曲避让部对位于该源漏电极层223且同时连接数据补偿晶体管T2与驱动晶体管T3的栅极的转接块进行避让。另外，可以理解的是，本公开不对上述弯曲避让部的数量进行限制，也即该弯曲避让部的数量可以是一个，也可以是多个，例如可以根据需要避让的结构数量进行设置。
在一些示例中，请参阅图10，图10为图5A中有源层23、第一栅极层221、第二栅极层222、源漏金属层223与导电连接层8的一种位置关系图。导电连接层8中的一部分构成了像素驱动电路21中的数据信号线DL。在此基础上，参阅图5B，导电连接层8中的一部分还构成了第二电源信号线VL2。
在一些示例中，请参阅图5A和图7，数据写入晶体管T4的第一极被配置为与数据信号线DL电连接以接收数据信号，数据写入晶体管T4的第二极被配置为通过节点N2与驱动晶体管T3的第一极电连接，数据写入晶体管T4的栅极被配置为与栅线GL电连接以接收栅极控制信号；数据补偿晶体管T2的第一极通过节点N3与驱动晶体管T3的第二极电连接，数据补偿晶体管T2的第二极通过节点N1与驱动晶体管T3的栅极电连接，数据补偿晶体管T2的栅极被配置为与栅线GL电连接以接收栅极控制信号。存储电容C的第一极C1与第一电压端VDD电连接，存储电容C的第二极C2通过节点N1与驱动晶体管T3的栅极电连接。
第一复位晶体管T7的第一极被配置为与第二条第一复位信号线Vint2电连接以接收复位信号，第一复位晶体管T7的第二极通过节点N4与发光器件的第一端电连接，第一复位晶体管T7的栅极被配置为与第二复位控制信号线Rst2电连接以接收复位控制信号；第二复位晶体管T1的第一极被配置为与第一条第一复位信号线Vint1电连接以接收复位信号，第二复位晶体管T1的第二极通过节点N1与驱动晶体管T3的栅极电连接，第二复位晶体管T1的栅极被配置为与第一复位控制信号线Rst1电连接以接收复位控制信号。
第一发光控制晶体管T6的第一极通过节点N3与驱动晶体管T3的第二极电连接，第一发光控制晶体管T6的第二极通过节点N4与发光器件的第一 极电连接，第一发光控制晶体管T6的栅极被配置为与发光控制信号线EM电连接以接收发光控制信号；第二发光控制晶体管T5的第一极与第一电压端VDD电连接，第二发光控制晶体管T5的第二极通过节点N2与驱动晶体管T3的第一极电连接，第二发光控制晶体管T5的栅极被配置为与发光控制信号线EM连接以接收发光控制信号；发光器件的第二极与第二电压端VSS电连接。
此时，至少一个开关晶体管ST包括第一发光控制晶体管T6、第二发光控制晶体管T5、数据写入晶体管T4、数据补偿晶体管T2、第一复位晶体管T7和第二复位晶体管T1。
需要说明的是，在上述一些示例提供的像素驱动电路21中，节点N1、节点N2、节点N3、节点N4并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点，也就是说，这些节点是由电路图中相关电连接的汇合点等效而成的节点。
此外，按照薄膜晶体管的特性，薄膜晶体管可以分为N型晶体管和P型晶体管，本公开的实施例中的薄膜晶体管为P型晶体管，该P型晶体管例如可以为P型MOS晶体管，也即，在本公开的实施例的描述中，驱动晶体管T3、第一发光控制晶体管T6、第二发光控制晶体管T5、数据写入晶体管T4、数据补偿晶体管T2、第一复位晶体管T7和第二复位晶体管T1等均可以为P型晶体管。然而，容易理解的是，本公开的实施例的薄膜晶体管不限于P型晶体管，本领域技术人员还可以根据实际需要，利用N型晶体管实现本公开的实施例中的一个或多个薄膜晶体管的功能，该N型晶体管例如可以为N型MOS晶体管。
由图5A～图10可以看出，由于第三种像素开口613的开口面积小于第一种像素开口611的开口面积以及第二种像素开口612的开口面积，同时，由于一个像素开口61需要露出一个第一电极31的至少部分，使得第三种像素开口613所对应的第一电极31的面积也小于第一种像素开口611所对应的第一电极31以及第二种像素开口611所对应的第一电极31，从而导致第三种像素开口613所对应的子像素区域P中，第一电极31无法覆盖到像素驱动电路21中的全部开关晶体管ST(包括数据补偿晶体管T2)。也即，当显示面板100处于光照条件下时，在与第三种像素开口613对应的子像素区域P中，至少一个开关晶体管ST(包括数据补偿晶体管T2)上方无膜层进行覆盖保护，导致光照影响开关晶体管ST(数据补偿晶体管T2)的特性，从而容易出现开关晶体管ST(数据补偿晶体管T2)漏电流等问题，最终会影响显示效果。
基于此，本公开一些实施例提供了一种显示面板100。请参阅图5A，至少一个第一电极31所对应的像素开口61在衬底1上的正投影和该第一电极31所对应的像素驱动电路21中的数据补偿晶体管T2的栅极在衬底1上的正投影分离。
例如，请参阅图5A，第一种像素开口611在衬底1上的正投影和该第一种像素开口611所对应的像素驱动电路21中的数据补偿晶体管T2的栅极在衬底1上的正投影分离。在此基础上，示例性的，请参阅图5A，第三种像素开口613在衬底1上的正投影和该第三种像素开口613所对应的像素驱动电路21中的数据补偿晶体管T2的栅极在衬底1上的正投影也可以分离。
所述至少一个第一电极31在衬底1上的正投影，和该第一电极31所对应的像素驱动电路21中的数据补偿晶体管T2的栅极在衬底1上的正投影至少部分交叠，同时和与该第一电极31所对应的像素驱动电路21相邻的至少一个像素驱动电路21中的数据补偿晶体管T2的栅极在衬底1上的正投影至少部分交叠。其中，数据补偿晶体管例如可以为非氧化物晶体管。
在此基础上，对于上述至少一个第一电极31中的一个第一电极31：和该第一电极31所对应的数据补偿晶体管T2在衬底1上的正投影与沿第一方向X延伸的第一虚拟直线S1具有第一交叠部分P1；和该第一电极31所对应的像素驱动电路21相邻的像素驱动电路21中的数据补偿晶体管T2在衬底1上的正投影与第一虚拟直线S1具有第二交叠部分P2；第一交叠部分P1与第二交叠部分P2在第一方向X上的间隔尺寸大于第一交叠部分P1所对应的像素开口61在第一方向X上的尺寸。
综上所述，本公开一些实施例提供的显示面板100，通过使至少一个第一电极31覆盖保护其自身所对应的像素驱动电路21中的数据补偿晶体管T2的栅极，以及覆盖保护与该第一电极31所对应的像素驱动电路21相邻的至少一个像素驱动电路21中的数据补偿晶体管T2的栅极，能够避免光照影响数据补偿晶体管T2的特性，从而避免出现数据补偿晶体管T2漏电流等问题，最终提高了显示面板100的性能稳定性。
在此基础上，由于第一交叠部分P1与第二交叠部分P2在第一方向X上的间隔尺寸大于第一交叠部分P1所对应的像素开口61在第一方向X上的尺寸，使得第一电极31所对应的数据补偿晶体管T2与和该第一电极31所对应的像素驱动电路21相邻的像素驱动电路21中的数据补偿晶体管T2之间的间距较大，从而有利于防止这两个数据补偿晶体管T2之间出现信号干扰的问题。
在一些示例中，请参阅图11～图16，多个像素开口61排列成多行多列； 相邻的两行像素开口61沿第一方向X彼此错开。
相邻的两行像素开口61中，一行像素开口61包括沿第一方向X交替排列的第一种像素开口611和第二种像素开口612，另一行像素开口包括沿第一方向X依次排列的多个第三种像素开口613。
相邻的两列像素开口61中，一列像素开口包括沿第二方向Y交替排列的第一种像素开口611和第二种像素开口612，另一列像素开口包括沿第二方向Y依次排列的多个第三种像素开口613。
在上述一些示例中，通过对多个像素开口61中的第一种像素开口611、第二种像素开口612、第三种像素开口613的排列方式进行限定，能够对显示面板100在显示区域边缘的锯齿感产生弱化效果，从而降低显示面板100的边缘锯齿效应，使得显示画质得到了明显提升。
需要说明的是，同一行的第一种像素开口611和第二种像素开口612在第一方向X上交替排列。此时，第一种像素开口611的中心和第二种像素开口612的中心可以例如图11、图12、图14和图15所示的在第二方向Y上没有间距(也即，同一行的第一种像素开口611和第二种像素开口612中，第一种像素开口611的中心和第二种像素开口612的中心位于沿第一方向X的同一条直线上)，或者也可以例如图13和图16所示的在第二方向Y上具有一定的间距(也即，同一行的第一种像素开口611和第二种像素开口612中，第一种像素开口611的中心和第二种像素开口612的中心不位于沿第一方向X的同一条直线上)。
同理，同一列的第一种像素开口611和第二种像素开口612在第二方向Y上交替排列。此时，第一种像素开口611的中心和第二种像素开口612的中心可以例如图11、图12、图13、图14和图15所示的在第一方向X上没有间距(也即，同一列的第一种像素开口611和第二种像素开口612中，第一种像素开口611的中心和第二种像素开口612的中心位于沿第二方向Y的同一条直线上)，或者也可以例如图16所示的在第一方向X上具有一定的间距(也即，同一行的第一种像素开口611和第二种像素开口612中，第一种像素开口611的中心和第二种像素开口612的中心不位于沿第二方向Y的同一条直线上)。
其中，上述第一种像素开口611的中心例如可以为第一种像素开口611的几何中心。同理，上述第二种像素开口612的中心例如可以为第二种像素开口612的几何中心。
示例性的，请参阅图11，在第一种像素开口611和第二种像素开口612 交替排列所形成的任一行像素开口61中，任一第一种像素开口611和与该第一种像素开口611相邻的两个第二种像素开口612之间的距离(也即，图11中的J1和J2)相等。
这样设计，基于第一种像素开口611、第二种像素开口612和第三种像素开口613分别透过不同颜色的光线，可以叠加形成一个像素发光区域，从而使得该像素发光区域能够显示多种颜色的光线，并实现多灰阶(例如256灰阶)显示。在此基础上，通过调整第一种像素开口611和第二种像素开口612之间的距离，可以提高显示面板100的画面显示精度、清晰度以及显示效果。
示例性的，请参阅图14，在第一种像素开口611和第二种像素开口612交替排列所形成的任一列像素开口61中，任一第一种像素开口611和与该第一种像素开口611相邻的两个第二种像素开口612之间的距离(也即，图14中的J3和J4)不相等。
这样设计，基于第一种像素开口611、第二种像素开口612和第三种像素开口613分别透过不同颜色的光线，可以叠加形成一个像素发光区域，从而使得该像素发光区域能够显示多种颜色的光线，并实现多灰阶(例如256灰阶)显示。在此基础上，通过进一步调整第一种像素开口611和第二种像素开口612之间的距离，可以进一步提高显示面板100的画面显示精度、清晰度以及显示效果。
示例性的，请参阅图14，一列像素开口61中相邻的第一种像素开口611和第二种像素开口612与相邻列像素开口61中相邻的第一种像素开口611和第二种像素开口612四者的几何中心相互连接构成虚拟梯形Q。
这样设计，基于第一种像素开口611、第二种像素开口612和第三种像素开口613分别透过不同颜色的光线，可以叠加形成一个像素发光区域，从而使得该像素发光区域能够显示多种颜色的光线，并实现多灰阶(例如256灰阶)显示。在此基础上，通过相邻的两列像素开口61中的第一种像素开口611和第二种像素开口612之间的位置关系，可以更进一步提高显示面板100的画面显示精度、清晰度以及显示效果。
示例性的，在同一行像素开口61中，第一种像素开口611的中心和第二种像素开口612的中心在第二方向Y上具有一定的间距。这样设计，可以使一个像素发光区域中的各种颜色的光线更好地配合，从而使显示面板100的画面显示精度更高，清晰度更好，显示效果更佳。其中，该间距例如可以小于或等于第一种像素开口611在第二方向Y上的尺寸的一半。这样设计，可以在保证显示面板100的画面显示精度和清晰度的情况下，进一步地对显示 面板100在显示区域边缘的锯齿感产生弱化效果，从而更好地降低显示面板100的边缘锯齿效应，提升显示面板100的显示画质。
示例性的，在同一列像素开口61中，第一种像素开口611的中心和第二种像素开口612的中心在第一方向X上具有一定的间距。这样设计，可以使一个像素发光区域中的各种颜色的光线更好地配合，从而使显示面板100的画面显示精度更高，清晰度更好，显示效果更佳。其中，该间距例如可以小于或等于第一种像素开口611在第一方向X上的尺寸的一半。这样设计，可以在保证显示面板100的画面显示精度和清晰度的情况下，进一步地对显示面板100在显示区域边缘的锯齿感产生弱化效果，从而更好地降低显示面板100的边缘锯齿效应，提升显示面板100的显示画质。
在一些示例中，请参阅图11～图16，最靠近显示区A的边界的多个像素开口61包括至少一行沿第一方向X交替排列的第一种像素开口611和第二种像素开口612，和/或，至少一列沿第二方向Y交替排列的第一种像素开口611和第二种像素开口612。这样设计，能够使最靠近显示区A的边界的多个像素开口61中包括更多的第一种像素开口611和第二种像素开口612，此时，由于第一种像素开口611和第二种像素开口612的开口面积均大于第三种像素开口613，故而能够尽可能地减小最靠近显示区A的边界的多个像素开口61之间的间隙，进一步地对显示面板100在显示区域边缘的锯齿感产生弱化效果，从而更好地降低显示面板100的边缘锯齿效应，进一步地提升显示面板100的显示画质。
其中，在显示区A为矩形的情况下，最靠近显示区A的边界的多个像素开口例如可以是最靠近显示区A的边界的两行像素开口61，以及最靠近显示区A的边界的两列像素开口61。
示例性的，请参阅图11，最靠近显示区A的边界的多个像素开口61仅包括一行沿第一方向X交替排列的第一种像素开口611和第二种像素开口612(例如虚线框H1所示)。
再示例性的，请参阅图12，最靠近显示区A的边界的多个像素开口61仅包括一列沿第二方向Y交替排列的第一种像素开口611和第二种像素开口612(例如虚线框L1所示)。
又示例性的，请参阅图13，最靠近显示区A的边界的多个像素开口61包括一行沿第一方向X交替排列的第一种像素开口611和第二种像素开口612(例如虚线框H2所示)，以及一列沿第二方向Y交替排列的第一种像素开口611和第二种像素开口612(例如虚线框L2所示)。
又示例性的，请参阅图14，最靠近显示区A的边界的多个像素开口61仅包括两行沿第一方向X交替排列的第一种像素开口611和第二种像素开口612(例如虚线框H3和虚线框H4所示)。
又示例性的，请参阅图15，最靠近显示区A的边界的多个像素开口61仅包括两列沿第二方向Y交替排列的第一种像素开口611和第二种像素开口612(例如虚线框L3和虚线框L4所示)。
又示例性的，请参阅图16，最靠近显示区A的边界的多个像素开口61包括两行沿第一方向X交替排列的第一种像素开口611和第二种像素开口612(例如虚线框H5和虚线框H6所示)，以及两列沿第二方向Y交替排列的第一种像素开口611和第二种像素开口612(例如虚线框L5和虚线框L6所示)。
在一些示例中，第一种像素开口611、第二种像素开口612和第三种像素开口613三者的开口面积比为(2.09～2.10):(3.69～3.70):(1.41～1.42)。
在上述一些示例中，通过对第一种像素开口611、第二种像素开口612和第三种像素开口613三者的开口面积比进行限定，能够进一步地对显示面板100在显示区域边缘的锯齿感产生弱化效果，从而更好地降低显示面板100的边缘锯齿效应，进一步地提升显示面板100的显示画质。
示例性的，第一种像素开口611的开口形状大致为正方形、矩形、菱形、圆形、椭圆形、橄榄形、六边形和八边形中的任意一种。其中，该开口形状例如可以为正方形。这样设计，能够使第一种像素开口611的开口形状更加规则，使其与第二种像素开口612和第三种像素开口613排列得更加规整，也即，使一个像素发光区域中的各种颜色的光线更好地配合，从而使显示面板100的画面显示精度更高，清晰度更好，显示效果更佳。
示例性的，第二种像素开口612的开口形状大致为正方形、矩形、菱形、圆形、椭圆形、橄榄形、六边形和八边形中的任意一种。其中，该开口形状例如可以为正方形。这样设计，能够使第二种像素开口612的开口形状更加规则，使其与第一种像素开口611和第三种像素开口613排列得更加规整，也即，使一个像素发光区域中的各种颜色的光线更好地配合，从而使显示面板100的画面显示精度更高，清晰度更好，显示效果更佳。
示例性的，第三种像素开口613的开口形状大致为正方形、矩形、菱形、圆形、椭圆形、橄榄形、六边形和八边形中的任意一种。其中，该开口形状例如可以为矩形。这样设计，能够使第三种像素开口613的开口形状更加规则，使其与第一种像素开口611和第二种像素开口612排列得更加规整，也即，使一个像素发光区域中的各种颜色的光线更好地配合，从而使显示面板 100的画面显示精度更高，清晰度更好，显示效果更佳。
在一些示例中，请参阅图11～图16，第一种像素开口611、第二种像素开口612和第三种像素开口613三者的开口形状均大致为矩形。
在此基础上，示例性的，第一种像素开口611的尺寸为14.48μm×14.48μm；第二种像素开口612的尺寸为19.23μm×19.23μm；第三种像素开口613的尺寸为12.63μm×11.21μm。这样设计，不仅能够使第一种像素开口611、第二种像素开口612和第三种像素开口613排列得更加规整，也即，使一个像素发光区域中的各种颜色的光线更好地配合，从而使显示面板100的画面显示精度更高，清晰度更好，显示效果更佳；而且能够进一步地对显示面板100在显示区域边缘的锯齿感产生弱化效果，从而更好地降低显示面板100的边缘锯齿效应，进一步地提升显示面板100的显示画质。
由此，在上述一些示例中，通过对多个像素开口61中的第一种像素开口611、第二种像素开口612、第三种像素开口613的排列方式以及第一种像素开口611、第二种像素开口612、第三种像素开口613分别限定的有效发光区域所对应的光线种类，以及第一种像素开口611、第二种像素开口612、第三种像素开口613三者的开口面积进行限定，不仅能够使一个像素发光区域中的各种颜色的光线更好地配合，而且能够对显示面板100在显示区域边缘的锯齿感产生弱化效果，降低显示面板100的边缘锯齿效应，从而使显示面板100的画面显示精度更高，清晰度更好，显示效果更佳，显示画质得到明显提升。
在一些实施例中，请参阅图5A，第一种像素开口611所对应的第一电极31在衬底1上的正投影，和该第一电极31所对应的像素驱动电路21中的数据补偿晶体管T2的栅极在衬底1上的正投影至少部分交叠，同时和与该第一电极31所对应的像素驱动电路21相邻的至少一个像素驱动电路21中的数据补偿晶体管T2的栅极在衬底1上的正投影至少部分交叠。
在上述一些实施例中，通过使第一种像素开口611所对应的第一电极31覆盖保护自身所对应的像素驱动电路21中的数据补偿晶体管T2的栅极，以及覆盖保护与该第一电极31所对应的像素驱动电路21相邻的至少一个像素驱动电路21中的数据补偿晶体管T2的栅极，能够避免光照影响数据补偿晶体管T2的特性，从而避免出现数据补偿晶体管T2漏电流等问题，最终提高了显示面板100的性能稳定性。
在一些实施例中，请参阅图5A，第二种像素开口612所对应的第一电极31在衬底1上的正投影，和该第一电极31所对应的像素驱动电路21中的数 据补偿晶体管T2的栅极在衬底1上的正投影至少部分交叠，同时和与该第一电极31所对应的像素驱动电路21相邻的至少一个像素驱动电路21中的数据补偿晶体管T2的栅极在衬底1上的正投影至少部分交叠。
在上述一些实施例中，通过使第二种像素开口612所对应的第一电极31覆盖保护自身所对应的像素驱动电路21中的数据补偿晶体管T2的栅极，以及覆盖保护与该第一电极31所对应的像素驱动电路21相邻的至少一个像素驱动电路21中的数据补偿晶体管T2的栅极，能够避免光照影响数据补偿晶体管T2的特性，从而避免出现数据补偿晶体管T2漏电流等问题，最终提高了显示面板100的性能稳定性。
在一些实施例中，请参阅图5A和图11～图16，第一种像素开口611和第三种像素开口613沿第三方向D1交替排列成第一组像素开口G1(例如图12所示)，第二种像素开口612和第三种像素开口613沿第三方向D1交替排列成第二组像素开口G2(例如图12所示)，第一组像素开口G1和第二组像素开口G2在第四方向D2上交替排列；其中，第三方向D1与第四方向D2相交。
其中，请参阅图5A，在第一组像素开口G1中，第一种像素开口611所对应的第一电极31在衬底1上的正投影，和与该第一种像素开口611相邻的一个第三种像素开口613所对应的像素驱动电路21中的数据补偿晶体管T2的栅极在衬底1上的正投影至少部分交叠；请继续参阅图5A，在第二组像素开口G2中，第二种像素开口612所对应的第一电极31在衬底1上的正投影和与该第二种像素开口612相邻的一个第三种像素开口613所对应的像素驱动电路21中的数据补偿晶体管T2的栅极在衬底1上的正投影至少部分交叠。
需要说明的是，第一组像素开口G1中的第一种像素开口611和第三种像素开口613在第三方向D1上交替排列。此时，第一组像素开口G1中，第一种像素开口611的中心和第三种像素开口613的中心可以例如图11、图12、图14和图15所示的在第四方向D2上没有间距(也即，第一种像素开口611的中心和第三种像素开口613的中心位于沿第三方向D1的同一条直线上)，或者也可以例如图13和图16所示的在第四方向D2上具有一定的间距(也即，第一种像素开口611的中心和第三种像素开口613的中心不位于沿第四方向D2的同一条直线上)，该间距例如可以小于或等于第三种像素开口613在第四方向D2上的尺寸的一半。
同理，第二组像素开口G1中，第一种像素开口611的中心和第二种像素开口612的中心可以例如图11、图12、图14和图15所示的在第四方向D2上没有间距(也即，第一种像素开口611的中心和第二种像素开口612的中 心位于沿第三方向D1的同一条直线上)，或者也可以例如图13和图16所示的在第四方向D2上具有一定的间距(也即，第一种像素开口611的中心和第二种像素开口612的中心不位于沿第四方向D2的同一条直线上)，该间距例如可以小于或等于第三种像素开口613在第四方向D2上的尺寸的一半。
其中，上述第三种像素开口613的中心例如可以为第三种像素开口613的几何中心。
此外，第一种像素开口611和第三种像素开口613交替排列的方向定义为第三方向D1，当第一种像素开口611和第三种像素开口613交替排列的方向不同时，第三方向D1随着第一种像素开口611和第三种像素开口613交替排列的方向的不同而不同。同理，第四方向D2也随着第一种像素开口611和第三种像素开口613交替排列的方向的不同而不同。
示例性的，请参阅图11～图16，第三方向D1与第四方向D2垂直，第三方向D1与第一方向X和第二方向Y的夹角均为约45度，第二方向与第一方向X和第二方向Y的夹角也均为约45度。
在一些示例中，请参阅图5A，相邻的第一种像素开口611和第二种像素开口612两者所对应的两个第一电极31在衬底1上的正投影，分别和位于该相邻的第一种像素开口611和第二种像素开口612两者同一侧的两个第三种像素开口613所对应的数据补偿晶体管T2的栅极在衬底1上的正投影至少部分交叠。这样设计，能够降低第一种像素开口611的第一电极31和第二种像素开口612的第一电极31的制作难度，简化显示面板100的制作工艺。
在上述一些实施例中，数据补偿晶体管T2例如可以为非氧化物晶体管，通过使第一种像素开口611所对应的第一电极31在衬底1上的正投影和第二种像素开口612所对应的第一电极31在衬底1上的正投影，与第三种像素开口613所对应的像素驱动电路21中的数据补偿晶体管T2的栅极在衬底1上的正投影至少部分交叠，也即，使第一种像素开口611所对应的第一电极31和第二种像素开口612所对应的第一电极31至少覆盖部分第三种像素开口613所对应的像素驱动电路21中的数据补偿晶体管T2的栅极，能够对数据补偿晶体管T2的栅极进行覆盖保护，避免光照对该数据补偿晶体管T2的阈值补偿电压造成影响，从而进一步地提高了显示面板100的性能稳定性。
示例性的，请继续参阅图5A和图6A，第一种像素开口611所对应的第一电极还覆盖该第一种像素开口611所对应的节点N1；和/或，第二种像素开口612所对应的第一电极31还覆盖该第二种像素开口612所对应的节点N1。
在上述一些示例中，通过使第一种像素开口611所对应的第一电极31或 第二种像素开口612所对应的第一电极31覆盖其自身所对应的像素驱动电路21中的节点N1，能够进一步地提高显示面板100的性能稳定性。
值得说明的是，上述一些示例中的像素开口61的排列方式仅用作示意性说明，本公开的多个像素开口61的排列方式不限于上述一些示例，在任意一种能够造成第三种像素开口613所对应的像素驱动电路21中的至少一个开关晶体管ST上方无膜层进行覆盖保护的排列方式中，采用上述一些示例提供的使第一种像素开口611所对应的第一电极31或第二种像素开口612所对应的第一电极31覆盖第三种像素开口613所对应的像素驱动电路21中的至少一个开关晶体管ST的方法，均能够达到避免光照对开关晶体管ST的特性造成影响，从而提高显示面板100的性能稳定性的效果。
在一些实施例中，请参阅图5A和图17，多条数据信号线DL位于电路结构层2和第一电极层3之间的导电连接层8中。
第一种像素开口611、第二种像素开口612和第三种像素开口613被配置为按照方式一、方式二和方式三中的至少一种设置。
方式一：第一种像素开口611的边缘在衬底1上的正投影位于相邻的两条数据信号线DL在衬底1上的正投影之间。
对此，由于多条数据信号线DL制作在第一电极层3朝向衬底1的一侧，控制第一种像素开口611的边缘在衬底1上的正投影位于相邻的两条数据信号线DL在衬底1上的正投影之间，也即，避免多条数据信号线DL制作在第一种像素开口611的正下方，从而避免第一电极层3中被第一种像素开口611所暴露出来的部位呈台阶状，这样能够保证第一电极层3中被第一种像素开口611所暴露出来的部位的平坦性。在此基础上，在第一电极层3被第一种像素开口611所暴露出来的部位上继续制作发光功能层4时，也能够保证发光功能层4在该部位的平坦性，从而保证显示面板100在显示时的第一颜色光线的均一性。
方式二：第二种像素开口612的边缘在衬底1上的正投影位于相邻的两条数据信号线DL在衬底1上的正投影之间；或，相邻的两条数据信号线DL在衬底1上的正投影均与第二种像素开口612的边缘在衬底1上的正投影部分重叠，相邻的两条数据信号线DL在衬底1上的正投影与第二种像素开口612的边缘在衬底1上的正投影的两个重叠部分的面积大致相同。
对此，由于多条数据信号线DL制作在第一电极层3朝向衬底1的一侧，控制第二种像素开口612的边缘在衬底1上的正投影位于相邻的两条数据信号线DL在衬底1上的正投影之间，也即，避免多条数据信号线DL制作在第 二种像素开口612的正下方，从而避免第一电极层3中被第二种像素开口612所暴露出来的部位呈台阶状，这样能够保证第一电极层3中被第二种像素开口612所暴露出来的部位的平坦性。在此基础上，在第一电极层3被第二种像素开口612所暴露出来的部位上继续制作发光功能层4时，也能够保证发光功能层4在该部位的平坦性，从而保证显示面板100在显示时的第二颜色光线的均一性。
此外，由于第二种像素开口612的开口面积例如可以大于第一种像素开口611和第三种像素开口613，在此情况下，由于第二种像素开口612的开口面积较大，而相邻的两条数据信号线DL之间的间距较小，此时第二种像素开口612的边缘在衬底1上的正投影则会与相邻的两条数据信号线DL在衬底1上的正投影部分重叠。在此基础上，通过控制相邻的两条数据信号线DL在衬底1上的正投影与第二种像素开口612的边缘在衬底1上的正投影的两个重叠部分的面积大致相同，能够避免第二种像素开口612所限定的有效发光区域出现色偏，从而保证显示面板100的显示画质。
方式三：第三种像素开口613的边缘在衬底1上的正投影位于相邻的两条数据信号线DL在衬底1上的正投影之间。
对此，由于多条数据信号线DL制作在第一电极层3朝向衬底1的一侧，控制第三种像素开口613的边缘在衬底1上的正投影位于相邻的两条数据信号线DL在衬底1上的正投影之间，也即，避免多条数据信号线DL制作在第三种像素开口613的正下方，从而避免第一电极层3中被第三种像素开口613所暴露出来的部位呈台阶状，这样能够保证第一电极层3中被第三种像素开口613所暴露出来的部位的平坦性。在此基础上，在第一电极层3被第三种像素开口613所暴露出来的部位上继续制作发光功能层4时，也能够保证发光功能层4在该部位的平坦性，从而保证显示面板100在显示时的第三颜色光线的均一性。
需要说明的是，上述第一种像素开口611、第二种像素开口612和第三种像素开口613被配置为按照方式一、方式二和方式三中的至少一种设置，例如可以是仅按照其中的一种方式设置，又例如可以是同时按照其中的两种或三种方式组合设置，具体可以根据实际需要进行选择。
示例性的，请继续参阅图17，以相邻的两条数据信号线DL的平分面(该平分面在衬底1上的投影为直线a)为对称面，相邻的两条数据信号线DL在衬底1上的正投影与第二种像素开口612的边缘在衬底1上的正投影的两个重叠部分呈镜面对称。这样设计，能够进一步地保证上述两个重叠部分的一 致，以避免第二种像素开口612所限定的有效发光区域出现色偏，从而进一步地保证显示面板100的显示画质。
示例性的，请继续参阅图17，以相邻的两条数据信号线DL的平分面(该平分面在衬底1上的投影为直线a)为对称面，第一种像素开口611呈镜面对称。这样设计，能够提高第一种像素开口611与数据信号线DL在排布时的均匀性，从而进一步地保证显示面板100的显示画质。
示例性的，请继续参阅图13，以相邻的两条数据信号线DL的平分面(该平分面在衬底1上的投影为直线a)为对称面，第二种像素开口612呈镜面对称。这样设计，能够提高第二种像素开口612与数据信号线DL在排布时的均匀性，此外，当相邻的两条数据信号线DL在衬底1上的正投影均与第二种像素开口612的边缘在衬底1上的正投影部分重叠时，能够在避免第二种像素开口612所限定的有效发光区域出现色偏的条件下，降低第二种像素开口612的制作难度，从而在进一步地保证显示面板100的显示画质时，简化显示面板100的制作工艺。
示例性的，请继续参阅图17，以相邻的两条数据信号线DL的平分面(该平分面在衬底1上的投影为直线a)为对称面，第三种像素开口613呈镜面对称。这样设计，能够提高第三种像素开口613与数据信号线DL在排布时的均匀性，从而进一步地保证显示面板100的显示画质。
下面，结合图3对显示面板100中第一过孔71和第二过孔91的结构进行示意性说明。
在一些实施例中，请参阅图3，第二过孔91形成在相对于第一平坦层7更加靠近像素界定层6的第二平坦层9上，且第二过孔91的边缘在衬底1上的正投影与像素开口61的边缘在衬底1上的正投影之间的距离小于第一过孔71的边缘在衬底1上的正投影与像素开口61的边缘在衬底1上的正投影之间的距离。此时，由于需要在第一电极31被像素开口61所暴露出来的部位附近制作第二过孔91，使得该部位因处于平坦面与下凹面的过渡区域而出现一定的倾斜，从而降低了该部位的平坦性，导致设置在该部位上方的发光功能层4的平坦性受到不利影响，降低了显示面板100整体的发光均匀性。
在此基础上，第二过孔91的边缘在衬底1上的正投影例如还可以与像素开口61的边缘在衬底1上的正投影至少部分重叠。此时，由于第二过孔91正好位于第一电极31被像素开口61所暴露出来的部位，故而对该部位的平坦性的影响更大，也即，对显示面板100整体的发光均匀性的影响更大。
基于此，在本公开的一些实施例中，请参阅图18，在子像素区域P中， 第一过孔71的边缘在衬底1上的正投影与像素开口61的边缘在衬底1上的正投影之间的最小距离，小于第二过孔91的边缘在衬底1上的正投影与像素开口61的边缘在衬底1上的正投影之间的最小距离。
在上述一些实施例中，在同一子像素区域P中，通过使第二过孔91相对于第一过孔71更远离像素开口61，从而避免了第一电极31被像素开口61所暴露出来的部位受到第二过孔91的影响，保证了该部位的平坦性，进一步避免了设置在该部位上方的发光功能层4受到不利影响，从而提高了显示面板100整体的发光均匀性。需要说明的是，虽然第一过孔71相对于第二过孔91更靠近像素开口61，但由于第一过孔71上覆盖了第二平坦层9，第二平坦层9可以对第一过孔71起到平坦作用，故而第一过孔71并不会影响到第一电极31被像素开口61所暴露出来的部位的平坦性。
在一些示例中，请继续参阅图18，第一过孔71和第二过孔91位于像素开口61的同一侧。
在一些示例中，请继续参阅图18，在子像素区域P中，第一过孔71的边缘在衬底1上的正投影与第二过孔91的边缘在衬底1上的正投影不重叠。其中，在子像素区域P中，第一过孔71的边缘在衬底1上的正投影与第二过孔91的边缘在衬底1上的正投影之间的最小距离例如可以不小于1.3μm。
在上述一些示例中，在同一子像素区域P中，通过限定第一过孔71的边缘在衬底1上的正投影与第二过孔91的边缘在衬底1上的正投影之间的最小距离不小于1.3μm，能够避免第一过孔71的边缘在衬底1上的正投影与第二过孔91的边缘在衬底1上的正投影之间的距离太近，从而避免了因位于第一过孔71正上方的第二平坦层9较厚而造成曝光位置偏移的情况，最终保证了第一电极31与导电连接层8的接触面积充分，避免了断路的发生。
示例性的，第一过孔71的边缘在衬底1上的正投影为类矩形、圆形或椭圆形。这样设计，能够使第一过孔71的形状更加规则，从而降低在其远离衬底1的一侧制作导电连接层8的难度。
需要说明的是，上述第一过孔71的边缘在衬底1上的正投影为类矩形时，该类矩形的拐角例如可以为如图19A所示的圆角，或者也可以为直角。
示例性的，第一过孔71的深度为1.6μm～2μm。这样设计，能够提高第一过孔71在曝光时的一致性和刻蚀时的均一性。
示例性的，第二过孔91的边缘在衬底1上的正投影为类矩形、圆形或椭圆形。这样设计，能够使第二过孔91的形状更加规则，降低在其远离衬底1的一侧制作第一电极层3的难度。
需要说明的是，上述第二过孔91的边缘在衬底1上的正投影为类矩形时，该类矩形的拐角例如可以为如图19A所示的圆角，或者也可以为直角。
示例性的，第二过孔91的深度为1.6μm～2μm。这样设计，能够提高第二过孔91在曝光时的一致性和刻蚀时的均一性。
在一些实施例中，请参阅图17，各第一过孔71下方的金属膜层大致相同。
在上述一些实施例中，通过控制各第一过孔71下方的金属膜层大致相同，能够提高各第一过孔71在曝光时的一致性和在刻蚀时的均一性。
在一些示例中，请继续参阅图17，第一种像素开口611所对应的第二过孔91与第二种像素开口612所对应的第二过孔91下方的金属膜层大致相同。
在上述一些示例中，通过控制第一种像素开口611所对应的第二过孔91与第二种像素开口612所对应的第二过孔91下方的金属膜层大致相同，能够提高第二过孔91在曝光时的一致性和在刻蚀时的均一性。
在一些示例中，请继续参阅图17，第三种像素开口613所对应的第二过孔91下方的金属膜层大致相同。
在上述一些示例中，通过控制第三种像素开口613所对应的第二过孔91下方的金属膜层大致相同，能够提高第二过孔91在曝光时的一致性和在刻蚀时的均一性。
在一些实施例中，请继续参阅图18和图19A，第一种像素开口611所在的子像素区域P中的第一过孔71与第二种像素开口612所在的子像素区域P中的第一过孔71的形状和大小均大致相同；和/或，第一种像素开口611所在的子像素区域P中的第二过孔91与第二种像素开口612所在的子像素区域P中的第二过孔91的形状和大小均大致相同；和/或，相邻的两个第三种像素开口613所在的两个子像素区域P中的第一过孔71的形状和大小均大致相同；和/或，相邻的两个第三种像素开口613所在的两个子像素区域P中的第二过孔91的形状和大小均大致相同。
在上述一些实施例中，通过控制第一种像素开口611所在的子像素区域P中的第一过孔71(或第二过孔91)与第二种像素开口612所在的子像素区域P中的第一过孔71(或第二过孔91)的形状和大小均大致相同，以及控制相邻的两个第三种像素开口613所在的两个子像素区域P中的第一过孔71(或第二过孔91)的形状和大小均大致相同，能够提高第一过孔71(或第二过孔91)在曝光时的一致性和在刻蚀时的均一性。
在一些示例中，请参阅图18，第一种像素开口611所在的子像素区域P中的第一过孔71的边缘限定出第一区域M1；第二种像素开口612所在的子 像素区域P中的第一过孔71的边缘限定出第二区域M2；所有金属层22中，位于第一区域M1的部位的总厚度与位于第二区域M2的部位的总厚度大致相同。
示例性的，请继续参阅图18，所有金属层22中，位于第一区域M1的部位的总层数与位于第二区域M2的部位的总层数相同。
例如，请继续参阅图18，所有金属层22中，位于第一区域M1的部位的总层数与位于第二区域M2的部位的总层数均为一层。
示例性的，请继续参阅图18，所有金属层22中，位于第一区域M1的部位与位于第二区域M2的部位的形状和大小均大致相同。
在上述一些示例中，通过控制所有金属层22中，位于第一区域M1的部位和第二区域M2的部位两者的总厚度、总层数、甚至是形状和大小均相同，使得第一种像素开口611所在的子像素区域P中的第一过孔71下方的金属膜层与第二种像素开口612所在的子像素区域P中的第一过孔71下方的金属膜层厚度大致相同，从而实现了第一种像素开口611所在的子像素区域P中的第一过孔71与第二种像素开口612所在的子像素区域P中的第一过孔71的形状和大小均大致相同，最终提高了其在曝光时的一致性和在刻蚀时的均一性。
在一些示例中，请继续参阅图18，第一种像素开口611所在的子像素区域P中的第二过孔91的边缘限定出第三区域M3；第二种像素开口612所在的子像素区域P中的第二过孔91的边缘限定出第四区域M4；所有金属层22中，位于第三区域M3的部位的总厚度与位于第四区域M4的部位的总厚度大致相同。
示例性的，请继续参阅图18，所有金属层22中，位于第三区域M3的部位的总层数与位于第四区域M4的部位的总层数相同。
例如，请继续参阅图18，所有金属层22中，位于第三区域M3的部位的总层数与位于第四区域M4的部位的总层数均为两层。
示例性的，请继续参阅图18，所有金属层22中，位于第三区域M3的部位与位于第二区域M4的部位的形状和大小均大致相同。
在上述一些示例中，通过控制所有金属层22中，位于第三区域M3的部位和第四区域M4的部位两者的总厚度、总层数、甚至是形状和大小均相同，使得第一种像素开口611所在的子像素区域P中的第二过孔91下方的金属膜层与第二种像素开口612所在的子像素区域P中的第二过孔91下方的金属膜层厚度大致相同，从而实现了第一种像素开口611所在的子像素区域P中的 第二过孔91与第二种像素开口612所在的子像素区域P中的第二过孔91的形状和大小均大致相同，最终提高了其在曝光时的一致性和在刻蚀时的均一性。
在一些示例中，请继续参阅图18，第三种像素开口613所在的子像素区域P中的第一过孔71的边缘限定出第五区域M5；所有金属层22中，位于相邻的两个第五区域M5的两个部位的总厚度大致相同。
示例性的，请继续参阅图18，所有金属层22中，位于相邻的两个第五区域M5的两个部位的总层数相同。
例如，请继续参阅图18，所有金属层22中，位于相邻的两个第五区域M5的两个部位的总层数均为一层。
示例性的，请继续参阅图18，所有金属层22中，位于相邻的两个第五区域M5的两个部位的形状和大小均大致相同。
在上述一些示例中，通过控制所有金属层22中，位于相邻的两个第五区域M5的两个部位的总厚度、总层数、甚至是形状和大小均相同，使得相邻的两个第三种像素开口613所在的两个子像素区域P中的第一过孔71下方的金属膜层厚度大致相同，从而实现了相邻的两个第三种像素开口613所在的两个子像素区域P中的第一过孔71的形状和大小均大致相同，最终进一步地提高了其在曝光时的一致性和在刻蚀时的均一性。
在一些示例中，请继续参阅图18，第三种像素开口613所在的子像素区域P中的第二过孔91的边缘限定出第六区域M6；所有金属层22中，位于相邻的两个第六区域M6的两个部位的总厚度大致相同。
示例性的，请继续参阅图18，所有金属层22中，位于相邻的两个第六区域M6的两个部位的总层数相同。
例如，请继续参阅图18，所有金属层22中，位于相邻的两个第六区域M6的两个部位的总层数均为两层。
示例性的，请继续参阅图18，所有金属层22中，位于相邻的两个第六区域M6的两个部位的形状和大小均大致相同。
在上述一些示例中，通过控制所有金属层22中，位于相邻的两个第六区域M6的两个部位的总厚度、总层数、甚至是形状和大小均相同，使得相邻的两个第三种像素开口613所在的两个子像素区域P中的第二过孔91下方的金属膜层厚度大致相同，从而实现了相邻的两个第三种像素开口613所在的两个子像素区域P中的第二过孔91的形状和大小均大致相同，最终进一步地提高了其在曝光时的一致性和在刻蚀时的均一性。
在一些实施例中，请参阅图19A，在相邻的两行像素开口61中，各像素开口61所对应的第一过孔71位于沿第一方向X延伸的一条直线O1上，各像素开口61所对应的第二过孔91沿第一方向X交替位于沿第一方向X延伸的同一直线O1的两侧。
在一些示例中，请参阅图19B，在相邻的两行像素开口61中，各像素开口61所对应的第一过孔71的几何中心位于沿第一方向X延伸的一条直线O1上，各像素开口61所对应的第二过孔91沿第一方向X交替位于沿第一方向X延伸的同一直线O1的两侧。
在一些示例中，请参阅图19A，在相邻的两行像素开口61中，各像素开口61所对应的第一过孔71分别位于各自对应的像素驱动电路21中的相同位置；第一种像素开口611所对应的第二过孔91和第二种像素开口612所对应的第二过孔91分别位于各自对应的像素驱动电路21中的相同位置。
示例性的，请继续参阅图19A，各第三种像素开口613所对应的第二过孔91分别位于各自对应的像素驱动电路21中的相同位置。
在上述一些示例中，通过限定相邻的两行像素开口61中，各像素开口61所对应的第一过孔71以及第二过孔91在各自对应的像素驱动电路21中的位置之间的关系，能够使得相邻的两行像素开口61中，各像素开口61所对应的第一过孔71下方的金属膜层厚度大致相同，第一种像素开口611所对应的第二过孔91和第二种像素开口612所对应的第二过孔91下方的金属膜层厚度大致相同，甚至是各第三种像素开口613所对应的第二过孔91下方的金属膜层厚度大致相同，最终提高了其在曝光和刻蚀时的一致性和均一性。
在一些实施例中，请参阅图19C，在相邻的两行像素开口61中，各像素开口61所对应的第一过孔71在第二方向Y上的位置不同。
在此基础上，显示面板100还包括位于第一栅极层中且沿第一方向X延伸的发光控制信号线，各第一过孔71在衬底1上的正投影与所述发光控制信号线在所述衬底上的正投影的交叠面积均相等。
在一些实施例中，请参阅图19A，在同一列像素开口61中，各像素开口61所对应的第一过孔71和各像素开口61所对应的第二过孔91位于沿第二方向Y延伸的同一直线O2上。
在一些示例中，请参阅图19A，沿第一方向X排列且相邻的第一种像素开口611所对应的第一过孔71和第二种像素开口612所对应的第一过孔71的几何中心连线构成第二虚拟直线S2；沿第一方向X排列且相邻的两个第二种像素开口613所对应的第一过孔71的几何中心连线构成第三虚拟直线S3； 第二虚拟直线S2和第三虚拟直线S3之间的夹角的范围是0°～30°。
示例性的，请参阅图19A，若第二虚拟直线S2和第三虚拟直线S3平行，第二虚拟直线S2和第三虚拟直线S3之间的距离小于第一过孔71在第二方向Y上的尺寸。
在一些实施例中，请参阅图19A，在同一行像素开口61中，各像素开口61所对应的第一过孔71沿第一方向X依次排列，和/或，各像素开口61所对应的第二过孔91沿第一方向X依次排列。
需要说明的是，上述第一过孔71(或第二过孔91)沿第一方向X依次排列，此时，同一行像素开口61中，各像素开口61所对应的第一过孔71(或第二过孔91)的中心例如可以位于同一条直线上，或者也可以不位于同一条直线上。
示例性的，请继续参阅图19A，同一行的第一过孔71的中心在第二方向Y上没有间距(也即，同一行的第一过孔71的中心位于同一条直线上)；和/或，同一行的第二过孔91的中心在第二方向Y上没有间距(也即，同一行的第二过孔91的中心位于同一条直线上)。
再示例性的，同一行的第一过孔71的中心在第二方向Y上具有一定的间距(也即，同一行的第一过孔71的中心不位于同一条直线上)，该间距例如可以小于或等于第一过孔71在第二方向Y上的尺寸的一半；和/或，同一行的第二过孔91的中心在第二方向Y上具有一定的间距(也即，同一行的第二过孔91的中心不位于同一条直线上)，该间距例如可以小于或等于第二过孔91在第二方向Y上的尺寸的一半。
示例性的，请继续参阅图19A，相邻的两行像素开口61中，各像素开口61所对应的第一过孔71沿同一第一方向X依次排列。
需要说明的是，上述第一过孔71沿同一第一方向X依次排列，此时，同一行像素开口61中，各像素开口61所对应的第一过孔71的中心例如可以位于同一条直线上，或者也可以不位于同一条直线上。
示例性的，请继续参阅图19A，同一行的第一过孔71的中心在第二方向Y上具有一定的间距(也即，同一行的第一过孔71的中心不位于同一条直线上)，该间距例如可以小于或等于第一过孔71在第二方向Y上的尺寸的一半。
再示例性的，同一行的第一过孔71的中心在第二方向Y上没有间距(也即，同一行的第一过孔71的中心位于同一条直线上)。
在上述一些示例中，通过控制同一行像素开口61中的各像素开口61所对应的第一过孔71(或第二过孔91)沿第一方向X依次排列，甚至是同一行 的第一过孔71(或第二过孔91)的中心在第二方向Y上没有间距，使得所有金属层22中，位于第一区域M1的各部位和与该第一区域M1在同一行上的第二区域M2的各部位(或第三区域M3的部位和与该第三区域M3在同一行上的第四区域M4的部位)的形状和大小均大致相同，以及位于同一行的第五区域M5中的各部位(或同一行的第六区域M6中的各部位)的形状和大小均大致相同，从而使得同一行的第一过孔71(或第二过孔91)下方的金属膜层厚度大致相同，从而实现了同一行的第一过孔71(或第二过孔91)的形状和大小均大致相同，最终进一步地提高了在曝光时的一致性和在刻蚀时的均一性。
在一些示例中，请继续参阅图19A，在同一列像素开口61中，各像素开口61所对应的第一过孔71沿第二方向Y依次排列，和/或，各像素开口61所对应的第二过孔91沿第二方向Y依次排列。
需要说明的是，上述第一过孔71(或第二过孔91)沿第二方向Y依次排列，此时，同一列像素开口61中各像素开口61所对应的第一过孔71(或第二过孔91)的中心例如可以位于同一条直线上，或者也可以不位于同一条直线上。
示例性的，请继续参阅图19A，同一列的第一过孔71的中心在第一方向X上没有间距(也即，同一列的第一过孔71的中心位于同一条直线上)；和/或，同一列的第二过孔91的中心在第一方向X上没有间距(也即，同一列的第二过孔91的中心位于同一条直线上)。
再示例性的，同一列的第一过孔71的中心在第一方向X上具有一定的间距(也即，同一列的第一过孔71的中心不位于同一条直线上)，该间距例如可以小于或等于第一过孔71在第一方向X上的尺寸的一半；和/或，同一列的第二过孔91的中心在第一方向X上具有一定的间距(也即，同一列的第二过孔91的中心不位于同一条直线上)，该间距例如可以小于或等于第二过孔91在第一方向X上的尺寸的一半。
在上述一些示例中，通过控制同一列像素开口61中的各像素开口61所对应的第一过孔71(或第二过孔91)沿第二方向Y依次排列，甚至是同一行的第一过孔71(或第二过孔91)的中心在第一方向X上没有间距，使得所有金属层22中，位于第一区域M1的各部位和与该第一区域M1在同一列上的第二区域M2的各部位(或第三区域M3的部位和与该第三区域M3在同一列上的第四区域M4的部位)的形状和大小均大致相同，以及位于同一列的第五区域M5中的各部位(或同一列的第六区域M6中的各部位)的形状和大小均 大致相同，从而使得同一列的第一过孔71(或第二过孔91)下方的金属膜层厚度大致相同，从而实现了同一列的第一过孔71(或第二过孔91)的形状和大小均大致相同，最终进一步地提高了在曝光时的一致性和在刻蚀时的均一性。
需要说明的是，上述第一过孔71的中心例如可以为第一过孔71的几何中心。上述第二过孔91的中心例如可以为第二过孔91的几何中心。
由此，在上述一些实施例中，在同一子像素区域P中，首先，通过使第二过孔91相对于第一过孔71更远离像素开口61，从而避免了第一电极31位于像素开口61所限定的区域的部位受到第二过孔91的影响，保证了该部位的平坦性，进一步避免了设置在该部位上方的发光功能层4受到不利影响，从而提高了显示面板100整体的发光均匀性；同时，通过限定第一过孔71的边缘在衬底1上的正投影与第二过孔91的边缘在衬底1上的正投影之间的最小距离，避免了第一过孔71的边缘在衬底1上的正投影与第二过孔91的边缘在衬底1上的正投影之间的距离太近，从而避免了因位于第一过孔71正上方的第二平坦层9较厚而造成曝光位置偏移的情况，最终保证了第一电极31与导电连接层8的接触面积充分，避免了断路的发生。
此外，通过控制第一种像素开口611所在的子像素区域P中的第一过孔71(或第二过孔91)与第二种像素开口612所在的子像素区域P中的第一过孔71(或第二过孔91)的形状和大小均大致相同，以及控制相邻的两个第三种像素开口613所在的两个子像素区域P中的第一过孔71(或第二过孔91)的形状和大小均大致相同，能够提高第一过孔71(或第二过孔91)在曝光时的一致性和在刻蚀时的均一性。
本公开的另一些实施例提供了一种显示面板100，该显示面板100可以应用于上述显示装置1000中。当然，该显示面板100也可以应用于其它的装置中。请参阅图18，该显示面板100包括：衬底1和位于衬底1的一侧且依次远离衬底1的电路结构层2、第一平坦层7、导电连接层8、第二平坦层9、第一电极层3和像素界定层6。
电路结构层2包括多个像素驱动电路21；第一平坦层7上具有多个第一过孔71；导电连接层8包括多个导电部81；第二平坦层9上具有多个第二过孔91；第一电极层3包括多个第一电极31；像素界定层6具有多个像素开口61。
显示面板100具有多个子像素区域P，在子像素区域中：像素开口61露出第一电极31的至少部分，第一电极31通过第二过孔91与导电部81电连 接，导电部81通过第一过孔71与像素驱动电路21电连接；第一过孔71的边缘在衬底1上的正投影与像素开口61的边缘在衬底1上的正投影之间的最小距离，小于第二过孔91的边缘在衬底1上的正投影与像素开口61的边缘在衬底1上的正投影之间的最小距离。
在这些实施例中，在同一子像素区域P中，通过使第二过孔91相对于第一过孔71更远离像素开口61，从而避免了第一电极31被像素开口61所暴露出来的部位受到第二过孔91的影响，保证了该部位的平坦性，进一步避免了设置在该部位上方的发光功能层4受到不利影响，从而提高了显示面板100整体的发光均匀性。需要说明的是，虽然第一过孔71相对于第二过孔91更靠近像素开口61，但由于第一过孔71上覆盖了第二平坦层9，第二平坦层9可以对第一过孔71起到平坦作用，故而第一过孔71并不会影响到第一电极31被像素开口61所暴露出来的部位的平坦性。
需要说明的是，本公开另一些实施例提供的显示面板100，还可以与上述任一实施例进行组合，此处不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (23)

  1. 一种显示面板，包括：
    衬底；
    位于所述衬底一侧的电路结构层，所述电路结构层包括多个像素驱动电路；所述多个像素驱动电路沿第一方向排列构成像素驱动电路行，所述多个像素驱动电路行沿第二方向依次排列；所述第一方向和所述第二方向相交；
    位于所述电路结构层远离所述衬底一侧的第一电极层，所述第一电极层包括多个第一电极；一个第一电极与一个像素驱动电路电连接；以及，
    位于所述第一电极层远离所述衬底一侧的像素界定层，所述像素界定层具有多个像素开口；一个像素开口露出一个第一电极的至少部分；
    所述像素驱动电路包括驱动晶体管和数据补偿晶体管；
    至少一个第一电极在所述衬底上的正投影，和该第一电极所对应的像素驱动电路中的数据补偿晶体管的栅极在所述衬底上的正投影至少部分交叠，同时和与该第一电极所对应的像素驱动电路相邻的至少一个像素驱动电路中的数据补偿晶体管的栅极在所述衬底上的正投影至少部分交叠；
    所述至少一个第一电极所对应的像素开口在所述衬底上的正投影和该第一电极所对应的像素驱动电路中的数据补偿晶体管的栅极在所述衬底上的正投影分离；
    对于所述至少一个第一电极中的一个第一电极：和该第一电极所对应的数据补偿晶体管在所述衬底上的正投影与沿所述第一方向延伸的第一虚拟直线具有第一交叠部分；和该第一电极所对应的像素驱动电路相邻的像素驱动电路中的数据补偿晶体管在所述衬底上的正投影与所述第一虚拟直线具有第二交叠部分；所述第一交叠部分与所述第二交叠部分在所述第一方向上的间隔尺寸大于所述第一交叠部分所对应的像素开口在所述第一方向上的尺寸。
  2. 根据权利要求1所述的显示面板，其中，
    所述多个像素开口排列成多行多列；相邻的两行像素开口沿所述第一方向彼此错开；
    相邻的两行像素开口中，一行像素开口包括沿所述第一方向交替排列的第一种像素开口和第二种像素开口，另一行像素开口包括沿所述第一方向依次排列的第三种像素开口；
    相邻的两列像素开口中，一列像素开口包括沿所述第二方向交替排列的第一种像素开口和第二种像素开口，另一列像素开口包括沿所述第二方向依次排列的第三种像素开口；
    其中，所述第一种像素开口的开口面积小于所述第二种像素开口的开口面积，且所述第一种像素开口的开口面积大于所述第三种像素开口的开口面积。
  3. 根据权利要求2所述的显示面板，其中，
    在所述第一种像素开口和所述第二种像素开口交替排列所形成的任一行像素开口中，任一第一种像素开口和与该第一种像素开口相邻的两个第二种像素开口之间的距离相等；
    在所述第一种像素开口和所述第二种像素开口交替排列所形成的任一列像素开口中，任一第一种像素开口和与该第一种像素开口相邻的两个第二种像素开口之间的距离不相等。
  4. 根据权利要求2或3所述的显示面板，其中，
    一列所述像素开口中相邻的所述第一种像素开口和所述第二种像素开口与相邻列所述像素开口中相邻的所述第一种像素开口和所述第二种像素开口四者的几何中心依次连接构成虚拟梯形。
  5. 根据权利要求2～4中任一项所述的显示面板，其中，
    在同一行像素开口中，所述第一种像素开口的中心和所述第二种像素开口的中心在所述第二方向上具有间距。
  6. 根据权利要求5所述的显示面板，其中，
    所述间距小于或等于所述第一种像素开口在所述第二方向上的尺寸的一半。
  7. 根据权利要求2～6中任一项所述的显示面板，其中，
    所述第一种像素开口所对应的第一电极在所述衬底上的正投影，和该第一电极所对应的像素驱动电路中的数据补偿晶体管的栅极在所述衬底上的正投影至少部分交叠，同时和与该第一电极所对应的像素驱动电路相邻的至少一个像素驱动电路中的数据补偿晶体管的栅极在所述衬底上的正投影至少部分交叠；和/或，
    所述第二种像素开口所对应的第一电极在所述衬底上的正投影，和该第一电极所对应的像素驱动电路中的数据补偿晶体管的栅极在所述衬底上的正投影至少部分交叠，同时和与该第一电极所对应的像素驱动电路相邻的至少一个像素驱动电路中的数据补偿晶体管的栅极在所述衬底上的正投影至少部分交叠。
  8. 根据权利要求2～7中任一项所述的显示面板，其中，
    所述第一种像素开口在所述衬底上的正投影和该第一种像素开口所对应 的像素驱动电路中的数据补偿晶体管的栅极在所述衬底上的正投影分离；和/或，
    所述第三种像素开口在所述衬底上的正投影和该第三种像素开口所对应的像素驱动电路中的数据补偿晶体管的栅极在所述衬底上的正投影分离。
  9. 根据权利要求2～8中任一项所述的显示面板，其中，
    所述第一种像素开口和所述第三种像素开口沿第三方向交替排列成第一组像素开口，所述第二种像素开口和所述第三种像素开口沿第三方向交替排列成第二组像素开口，所述第一组像素开口和所述第二组像素开口在第四方向上交替排列；所述第三方向与所述第四方向相交；
    其中，在所述第一组像素开口中，所述第一种像素开口所对应的第一电极在所述衬底上的正投影，和与该第一种像素开口相邻的一个第三种像素开口所对应的像素驱动电路中的数据补偿晶体管的栅极在所述衬底上的正投影至少部分交叠；
    在所述第二组像素开口中，所述第二种像素开口所对应的第一电极在所述衬底上的正投影，和与该第二种像素开口相邻的一个第三种像素开口所对应的数据补偿晶体管的栅极在所述衬底上的正投影至少部分交叠。
  10. 根据权利要求9所述的显示面板，其中，
    相邻的所述第一种像素开口和所述第二种像素开口两者所对应的两个第一电极在所述衬底上的正投影，分别和位于该相邻的所述第一种像素开口和所述第二种像素开口两者同一侧的两个第三种像素开口所对应的数据补偿晶体管的栅极在所述衬底上的正投影至少部分交叠。
  11. 根据权利要求2～10中任一项所述的显示面板，其中，
    所述显示面板具有显示区；最靠近所述显示区的边界的多个像素开口包括至少一行沿所述第一方向交替排列的所述第一种像素开口和所述第二种像素开口，和/或，至少一列沿所述第二方向交替排列的所述第一种像素开口和所述第二种像素开口。
  12. 根据权利要求2～11中任一项所述的显示面板，其中，
    所述第一种像素开口被配置为限定第一颜色光线的有效发光区域，所述第二种像素开口被配置为限定第二颜色光线的有效发光区域，所述第三种像素开口被配置为限定第三颜色光线的有效发光区域；
    所述第一颜色光线为红色光线，所述第二颜色光线为蓝色光线，所述第三颜色光线为绿色光线。
  13. 根据权利要求2～12中任一项所述的显示面板，其中，
    所述电路结构层包括依次远离所述衬底的有源层、第一栅极层、第二栅极层和源漏电极层；
    所述显示面板还包括位于所述电路结构层与所述第一电极层之间的导电连接层；
    所述显示面板包括给所述第一电极提供复位信号的多条复位信号线，所述多条复位信号线包括：
    位于所述第二栅极层或有源层且沿所述第一方向延伸的第一复位信号线以及位于所述源漏电极层或所述导电连接层且沿所述第二方向延伸的第二复位信号线；
    所述第一复位信号线与所述第二复位信号线在所述衬底上的正投影交叠，在交叠位置，所述第一复位信号线与所述第二复位信号线通过过孔电连接；
    在所述第一复位信号线位于所述第二栅极层，所述第二复位信号线位于所述源漏电极层时，所述第二复位信号线与所述有源层通过过孔连接。
  14. 根据权利要求13所述的显示面板，其中，所述显示面板还包括多条电源信号线，所述多条电源信号线包括：
    位于所述源漏电极层且沿所述第二方向延伸的第一电源信号线以及位于所述导电连接层且沿所述第二方向延伸的第二电源信号线；
    其中，所述第一电源信号线和所述第二电源信号线电连接，所述第一电源信号线和所述第二电源信号线在所述衬底上的正投影交叠，至少一个像素开口在所述衬底上的正投影位于所述第二电源信号线在所述衬底上的正投影范围内。
  15. 根据权利要求14所述的显示面板，其中，
    所述第二电源信号线具有多个突出部，一个突出部在所述衬底上的正投影与一个第一电极所对应的像素开口在所述衬底上的正投影至少部分交叠。
  16. 根据权利要求13所述的显示面板，还包括：
    位于所述导电连接层中、且沿所述第二方向延伸的多条数据信号线，所述多条数据信号线沿所述第一方向依次排列；
    所述第一种像素开口、所述第二种像素开口和所述第三种像素开口被配置为按照以下至少一种方式设置：
    所述第一种像素开口在所述衬底上的正投影位于相邻的两条数据信号线在所述衬底上的正投影之间；或者，
    所述第二种像素开口在所述衬底上的正投影位于相邻的两条数据信号线 在所述衬底上的正投影之间；或，相邻的两条数据信号线在所述衬底上的正投影均与所述第二种像素开口在所述衬底上的正投影部分重叠，所述相邻的两条数据信号线在所述衬底上的正投影与所述第二种像素开口在所述衬底上的正投影的两个重叠部分的面积大致相同；或者，
    所述第三种像素开口在所述衬底上的正投影位于相邻的两条数据信号线在所述衬底上的正投影之间。
  17. 根据权利要求16所述的显示面板，其中，
    所述第一种像素开口、所述第二种像素开口和所述第三种像素开口被配置为按照以下至少一种方式设置：
    以所述相邻的两条数据信号线的平分面为对称面，所述第一种像素开口呈镜面对称；或者，
    以所述相邻的两条数据信号线的平分面为对称面，所述第二种像素开口呈镜面对称；或者，
    以所述相邻的两条数据信号线的平分面为对称面，所述第三种像素开口呈镜面对称。
  18. 根据权利要求2～17中任一项所述的显示面板，还包括：
    位于所述电路结构层和所述第一电极层之间且依次远离所述衬底的第一平坦层、导电连接层和第二平坦层；其中，所述第一平坦层上具有多个第一过孔；所述导电连接层包括多个导电部；所述第二平坦层上具有多个第二过孔；
    所述显示面板具有多个子像素区域，在子像素区域中：
    第一电极通过第二过孔与导电部电连接，导电部通过第一过孔与像素驱动电路电连接；
    所述第一过孔的边缘在所述衬底上的正投影与所述像素开口在所述衬底上的正投影之间的最小距离，小于所述第二过孔的边缘在所述衬底上的正投影与所述像素开口在所述衬底上的正投影之间的最小距离。
  19. 根据权利要求18所述的显示面板，其中，
    在相邻的两行像素开口中，各像素开口所对应的第一过孔位于沿所述第一方向延伸的一条直线上，各像素开口所对应的第二过孔沿所述第一方向交替位于所述沿所述第一方向延伸的同一直线的两侧。
  20. 根据权利要求19所述的显示面板，其中，
    在相邻的两行所述像素开口中，各像素开口所对应的第一过孔分别位于各自对应的像素驱动电路中的相同位置；
    所述第一种像素开口所对应的第二过孔和所述第二种像素开口所对应的第二过孔分别位于各自对应的像素驱动电路中的相同位置。
  21. 根据权利要求19所述的显示面板，其中，
    在相邻的两行所述像素开口中，各像素开口所对应的第一过孔在所述第二方向上的位置不同；
    所述显示面板还包括位于第一栅极层中，且沿所述第一方向延伸的发光控制信号线，各所述第一过孔在所述衬底上的正投影与所述发光控制信号线在所述衬底上的正投影的交叠面积均大致相等。
  22. 根据权利要求18～21中任一项所述的显示面板，其中，
    在同一列所述像素开口中，各像素开口所对应的第一过孔和各像素开口所对应的第二过孔位于沿所述第二方向延伸的同一直线上。
  23. 一种显示装置，包括：
    如权利要求1～22中任一项所述的显示面板。
PCT/CN2021/123928 2021-10-14 2021-10-14 显示面板及显示装置 WO2023060520A1 (zh)

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CN110034132A (zh) * 2019-06-12 2019-07-19 成都京东方光电科技有限公司 一种阵列基板、显示面板及显示装置
CN111799320A (zh) * 2020-09-01 2020-10-20 京东方科技集团股份有限公司 显示面板以及显示装置
WO2021018301A1 (zh) * 2019-07-31 2021-02-04 京东方科技集团股份有限公司 显示基板以及显示装置
CN113078174A (zh) * 2021-04-13 2021-07-06 厦门天马微电子有限公司 阵列基板、显示面板及显示装置
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KR20180062897A (ko) * 2016-12-01 2018-06-11 엘지디스플레이 주식회사 유기 발광 표시 장치
CN110034132A (zh) * 2019-06-12 2019-07-19 成都京东方光电科技有限公司 一种阵列基板、显示面板及显示装置
WO2021018301A1 (zh) * 2019-07-31 2021-02-04 京东方科技集团股份有限公司 显示基板以及显示装置
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