WO2023226023A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2023226023A1
WO2023226023A1 PCT/CN2022/095713 CN2022095713W WO2023226023A1 WO 2023226023 A1 WO2023226023 A1 WO 2023226023A1 CN 2022095713 W CN2022095713 W CN 2022095713W WO 2023226023 A1 WO2023226023 A1 WO 2023226023A1
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WIPO (PCT)
Prior art keywords
signal line
sub
conductive layer
reset signal
signal lines
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PCT/CN2022/095713
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English (en)
French (fr)
Inventor
承天一
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/095713 priority Critical patent/WO2023226023A1/zh
Priority to CN202280001505.2A priority patent/CN117716807A/zh
Publication of WO2023226023A1 publication Critical patent/WO2023226023A1/zh

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  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • OLED Organic Light Emitting Diode
  • a display panel is provided.
  • the display panel has a functional device setting area and a main display area at least partially surrounding the functional device setting area; a mounting hole is provided in the functional device setting area, and the functional device setting area includes a main display area surrounding the mounting hole. border area.
  • the display panel includes a substrate, a plurality of pixel circuits, a plurality of enable signal lines, a plurality of scan signal lines and a plurality of reset signal lines.
  • the plurality of pixel circuits are disposed on the substrate and located in the main display area.
  • the plurality of enable signal lines are electrically connected to the pixel circuit; at least one enable signal line includes a first sub-enable signal line located in the main display area and a second sub-enable signal located in the frame area.
  • the plurality of scanning signal lines are electrically connected to the pixel circuit; at least one scanning signal line includes a first sub-scanning signal line located in the main display area and a second sub-scanning signal line located in the frame area.
  • the plurality of reset signal lines are electrically connected to the pixel circuit; at least one reset signal line includes a first sub-reset signal line located in the main display area and a second sub-reset signal line located in the frame area.
  • the second sub-enable signal line of the plurality of enable signal lines there are at least three signal lines located on three different layers.
  • the display panel sequentially includes a first gate conductive layer, a second gate conductive layer, and a third gate conductive layer, and the plurality of strips Among the second sub-enable signal line of the enable signal line, the second sub-scan signal line of the plurality of scan signal lines and the second sub-reset signal line of the plurality of reset signal lines, there are at least three signal lines respectively.
  • the first gate conductive layer, the second gate conductive layer and the third gate conductive layer Located on the first gate conductive layer, the second gate conductive layer and the third gate conductive layer.
  • a second sub-enable signal line among the plurality of enable signal lines is located on the second gate conductive layer.
  • At least two reset signal lines include a first sub-reset signal line located in the main display area and a second sub-reset signal line located in the frame area; among the at least two reset signal lines, some of the second sub-reset signal lines
  • the reset signal line is located on the first gate conductive layer, and some of the second sub-reset signal lines are located on the third gate conductive layer.
  • the second sub-scan signal line among the plurality of scan signal lines is located on the second gate conductive layer.
  • the orthographic projection of the second sub-reset signal line located on the third gate conductive layer on the substrate is the same as the second sub-enable signal line located on the second gate conductive layer and/ Or the orthographic projections of the second sub-scanning signal lines on the substrate at least partially overlap. And/or, the orthographic projection of the second sub-reset signal line located on the third gate conductive layer on the substrate is the same as the orthographic projection of the second sub-reset signal line located on the first gate conductive layer on the substrate. Orthographic projections on at least partially overlap.
  • the at least two reset signal lines include a plurality of first reset signal lines and a plurality of second reset signal lines.
  • the first reset signal line is configured to transmit a first reset signal; at least one first reset signal line includes the first sub-reset signal line and the second sub-reset signal line, and the first reset signal line
  • the second sub-reset signal line is located on the first gate conductive layer.
  • the second reset signal line is configured to transmit a second reset signal; at least one second reset signal line includes the first sub-reset signal line and the second sub-reset signal line, and the second reset signal line
  • the second sub-reset signal line is located on the third gate conductive layer.
  • the plurality of scan signal lines include a plurality of first scan signal lines, and the plurality of first scan signal lines are configured to transmit first scan signals; at least one first scan signal line includes the The first sub-scanning signal line and the second sub-scanning signal line are located on the second gate conductive layer.
  • the display panel has a peripheral area, the peripheral area is located at least on a first side and a second side of the main display area, and the first side and the second side are the main display area. Opposite sides of the area.
  • the plurality of scan signal lines also include a plurality of second scan signal lines, the plurality of second scan signal lines are configured to transmit second scan signals; the plurality of second scan signal lines include first type scan signals lines, second type scanning signal lines and third type scanning signal lines, the mounting holes are located in the extending direction of the second type scanning signal lines and the third type scanning signal lines.
  • the first type of scanning signal line extends from the peripheral area located on the first side of the main display area to the peripheral area located on the second side of the display area along the first direction.
  • the second type of scanning signal line extends from the peripheral area located on the first side of the main display area to the frame area along the first direction.
  • the third type of scanning signal line extends from the peripheral area located on the second side of the display area to the frame area along the first direction.
  • the display panel further includes a first scan driving circuit and a second scan driving circuit.
  • the first scan drive circuit is disposed in the peripheral area and is located on the first side of the main display area; the first scan drive circuit, the first scan signal line, and the first type scan signal line , the second type scanning signal line, the enable signal line, and the reset signal line are electrically connected.
  • the second scan drive circuit is disposed in the peripheral area and is located on the second side of the main display area; the second scan drive circuit and the first type of scan signal line and the third type of scan signal Wire connection.
  • the first scan driving circuit includes a plurality of first shift registers connected in cascade, each first shift register is connected to at least two of the first scan signal lines, and at least two of the first scan signal lines.
  • the energy signal line, at least two first reset signal lines and at least two second reset signal lines are electrically connected, and each first shift register is also connected to at least two first type scanning signal lines or at least two The second type of scanning signal lines are electrically connected.
  • the second scan driving circuit includes a plurality of second shift registers connected in cascade, each second shift register is connected to at least two of the first type of scanning signal lines or at least two of the third type of scanning signal lines. Electrical connection.
  • one first scanning signal line includes the first sub-scanning signal line and the second sub-scanning signal line.
  • each of the remaining first scan signal lines includes two scan line segments, and one scan line segment is connected to one end of the first shift register and the second sub-scan signal line, and the other scan line segment is connected to the The other end of the second sub-scanning signal line is electrically connected and extends to the boundary of the second side of the main display area.
  • one enable signal line includes the first sub-enable signal line and the second sub-enable signal line, and the remaining Each enable signal line includes two enable trace segments, and one enable trace segment is connected to one end of the first shift register and the second sub-enable signal line, and the other enable trace segment is connected to The other end of the second sub-enable signal line is electrically connected and extends to the boundary of the second side of the main display area.
  • one first reset signal line includes the first sub-reset signal line and the second sub-reset signal line, and the remaining Each first reset signal line includes two first reset wiring segments, and one first reset wiring segment is connected to one end of the first shift register and the second sub-reset signal line, and the other first reset wiring segment
  • the trace segment is electrically connected to the other end of the second sub-reset signal line and extends to the boundary of the second side of the main display area.
  • one second reset signal line includes the first sub-reset signal line and the second sub-reset signal line, and the remaining Each second reset signal line includes two second reset wiring segments, and one second reset wiring segment is connected to one end of the first shift register and the second sub-reset signal line, and the other second reset wiring segment
  • the trace segment is electrically connected to the other end of the second sub-reset signal line and extends to the boundary of the second side of the main display area.
  • the display panel further includes a first source-drain conductive layer and a second source-drain conductive layer, and the first source-drain conductive layer is disposed on a side of the third gate conductive layer away from the substrate. side, the second source-drain conductive layer is disposed on a side of the first source-drain conductive layer away from the substrate.
  • the display panel also includes a plurality of data lines electrically connected to the pixel circuit; at least two data lines include a first sub-data line located in the main display area and a first sub-data line located in the frame area. Second sub-data lines; located in at least two second sub-data lines in the frame area, some second sub-data lines are located in the first source-drain conductive layer, and other second sub-data lines are located in the second Source and drain conductive layers.
  • the orthographic projection of the second sub-data line located on the first source-drain conductive layer on the substrate is different from the orthographic projection of the signal line located on the third gate conductive layer on the substrate.
  • two opposite side surfaces of the signal line located on the third gate conductive layer are first slopes, and the distance between the two first slopes of the same signal line is far away from the boundary of the substrate. , less than the distance between the two first inclined planes close to the boundary of the substrate.
  • an angle between the first slope and a plane of the substrate away from the first gate conductive layer is less than or equal to 30°.
  • the orthographic projection of the signal line located on the first gate conductive layer on the substrate is staggered from the orthographic projection of the signal line located on the second gate conductive layer on the substrate. . And/or, the boundary of the orthographic projection of the signal line located on the second gate conductive layer on the substrate, and the boundary of the orthographic projection of the signal line located on the first gate conductive layer on the substrate Inside.
  • two opposite side surfaces of the signal line located on the first gate conductive layer are second slopes, and the distance between the two second slopes of the same signal line is away from the boundary of the substrate, is less than the distance between the two second inclined surfaces close to the boundary of the substrate.
  • an angle between the second slope and a plane of the substrate away from the first gate conductive layer is less than or equal to 30°.
  • the display panel further includes an interlayer insulating layer, a second gate insulating layer and a third gate insulating layer.
  • the interlayer insulating layer is disposed between the first source-drain conductive layer and the third gate conductive layer
  • the second gate insulating layer is disposed between the first gate conductive layer and the second gate conductive layer.
  • the third gate insulating layer is disposed between the second gate conductive layer and the third gate conductive layer.
  • the thickness of the third gate insulating layer is greater than the thickness of the interlayer insulating layer, and is greater than the thickness of the second gate insulating layer.
  • the thickness of the interlayer insulating layer is And/or, the thickness of the second gate insulating layer is And/or, the thickness of the third gate insulating layer is
  • the display device includes the display panel as described in any of the above embodiments.
  • Figure 1 is a structural diagram of a display device according to some embodiments.
  • Figure 2 is a structural diagram of a display panel according to some embodiments.
  • Figure 3 is a cross-sectional view along A-A' in Figure 2;
  • Figure 4 is a circuit diagram of a sub-pixel according to some embodiments.
  • Figure 5 is a structural diagram of another display panel according to some embodiments.
  • Figure 6 is a partial enlarged view of M in Figure 5;
  • Figure 7 is a cross-sectional view along A-A' in Figure 6;
  • Figure 8 is another cross-sectional view along A-A' in Figure 6;
  • Figure 9 is another cross-sectional view along A-A' in Figure 6;
  • Figure 10 is another cross-sectional view along A-A' in Figure 6;
  • Figure 11 is another cross-sectional view along A-A' in Figure 6;
  • Figure 12 is an electron microscope image along A-A' in Figure 6;
  • Figure 13 is a structural diagram of another display panel according to some embodiments.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
  • connection and its derivatives may be used.
  • some embodiments may be described using the term “connected” to indicate that two or more components are in direct physical or electrical contact with each other.
  • the embodiments disclosed herein are not necessarily limited by the content herein.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C” and includes the following combinations of A, B and C: A only, B only, C only, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • Example embodiments are described herein with reference to cross-sectional illustrations and/or plan views that are idealized illustrations.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
  • the control pole of each transistor is a gate of the transistor, a first pole is one of the source and drain of the transistor, and a second pole is the other of the source and drain of the transistor. Since the source and drain of the transistor may be symmetrical in structure, the source and drain of the transistor may be structurally indistinguishable. That is to say, the first electrode and the third electrode of the transistor in the embodiment of the present disclosure The two poles can be structurally indistinguishable. For example, when the transistor is a P-type transistor, the first pole of the transistor is the source, and the second pole is the drain; for example, when the transistor is an N-type transistor, the first pole of the transistor is the drain, The second pole is the source.
  • “same layer” refers to a layer structure formed by using the same film formation process to form a film layer for forming a specific pattern, and then using the same mask to form a patterning process.
  • a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights. Or have different thicknesses.
  • a display device 1000 which may be any device that displays images, whether moving (eg, video) or fixed (eg, still images), and whether text or text.
  • the display device 1000 can be a television, a laptop, a tablet, a mobile phone, a personal digital assistant (Personal Digital Assistant; PDA for short), a navigator, a wearable device, or a virtual reality (Virtual Reality; VR for short) ) equipment and any other product or component with a display function.
  • PDA Personal Digital Assistant
  • VR Virtual Reality
  • the display device 1000 includes a display panel 100 .
  • the above-mentioned display device 1000 may also include a housing 200, a functional device 300, a circuit board, and other electronic accessories.
  • the display panel 100, the functional device 300 and the circuit board can be disposed in the housing 100.
  • circuit board can be bound to the display panel 100 at the end of the display panel 100 and bent to the back side of the display panel 100 to reduce the outer frame of the display panel 100 and increase the screen-to-body ratio.
  • the functional device 300 can be integrated directly below the non-display side of the display panel 100 to reduce the outer frame of the display panel 100 and increase the screen-to-body ratio.
  • the functional device 300 can be a camera, an infrared sensor, a proximity sensor, an eye tracking module, a face recognition module, etc.
  • the functional device 300 is a camera.
  • the display panel 100 may be provided with a mounting hole H, and the functional device 300 may be installed at the mounting hole H to prevent the display panel 100 from blocking the lighting of the functional device 300 .
  • the above-mentioned display panel 100 includes multiple types, and can be selected and set according to actual needs.
  • the above display panel 100 can be: an organic light emitting diode (OLED for short) display panel, a quantum dot light emitting diode (Quantum Dot Light Emitting Diode for short: QLED) display panel, a micro light emitting diode (Micro light emitting diode).
  • OLED organic light emitting diode
  • QLED Quantum Dot Light Emitting Diode for short
  • Micro light emitting diode Micro light emitting diode
  • Light Emitting Diodes abbreviated as: Micro LED
  • the above-mentioned display panel 100 has a display area A, and a peripheral area B disposed on at least one side of the display area A.
  • the peripheral area B is arranged around the display area A as an example.
  • the display area A is an area for displaying an image, and is configured to provide a plurality of sub-pixels P.
  • the peripheral area B is an area where no image is displayed, and the peripheral area B is configured to provide display driving circuits, such as the scan driving circuit 110 and the source driving circuit 120 .
  • the scan driving circuit 110 may include a light emitting control circuit and a gate driving circuit.
  • the following takes the scanning driving circuit 110 including a light emitting control circuit and a gate driving circuit as an example to schematically illustrate some embodiments of the present disclosure.
  • the display area A when the functional device 300 is integrated below the display panel 100 , the display area A also has a functional device setting area A1 and a main body that at least partially surrounds the functional device setting area A1 .
  • the mounting hole H is provided in the functional device setting area A1
  • the functional device setting area A1 also includes a frame area A10 surrounding the mounting hole H.
  • the main display area A2 surrounding the functional device setting area A1 is taken as an example for illustration.
  • the frame area A10 includes a redundant area A11, a wiring area A12, and a packaging area A13 in sequence.
  • the redundant area A11 is configured to provide a process gap between the wiring area A12 and the main display area A2
  • the wiring area A12 is configured to provide circuit wiring
  • the packaging area A13 is configured to provide a packaging layer to block water and Oxygen erosion.
  • the packaging area A13 is provided with inner isolation pillars 30 , blocking portions 40 and outer isolation pillars 50 .
  • Some embodiments of the present disclosure are schematically described below, taking the display area A including the functional device setting area A1 and the main display area A2 that at least partially surrounds the functional device setting area A1 as an example.
  • the above-mentioned display panel 100 may include a substrate 10 and a scan driving circuit 110 .
  • the substrate 10 is used to carry the scan driving circuit 110 .
  • substrate 10 may be a rigid substrate.
  • the rigid substrate may be a glass substrate or a PMMA (Polymethyl Methacrylate) substrate.
  • substrate 10 may be a flexible substrate.
  • the flexible substrate can be a polyethylene terephthalate (Polyethylene Terephthalate, referred to as: PET) substrate, a polyethylene naphthalate two formic acid glycol ester (abbreviated as: PEN) substrate Bottom or polyimide (Polyimide, referred to as: PI) substrate, etc.
  • PET polyethylene Terephthalate
  • PEN polyethylene naphthalate two formic acid glycol ester
  • PI polyimide
  • the above-mentioned display panel 100 may also include a plurality of sub-pixels P.
  • the plurality of sub-pixels P and the scan driving circuit 110 are disposed on the same side of the substrate 10 and are located in the main display area. A2.
  • the plurality of sub-pixels P may be arranged in multiple rows and columns, each row includes a plurality of sub-pixels P arranged along the first direction X, each column includes a plurality of sub-pixels P arranged along the second direction Y, the first direction
  • the two directions Y are roughly vertical.
  • each sub-pixel P may include a pixel circuit 130 and a light-emitting device 140 electrically connected to the pixel circuit 130.
  • the light-emitting device 140 may be an OLED.
  • the above-mentioned display panel 100 may further include a plurality of enable signal lines EL, a plurality of scan signal lines GL, a plurality of reset signal lines RL and a plurality of data lines DL.
  • FIG. 2 only illustrates part of the enable signal line EL, the scan signal line GL, the reset signal line RL and a plurality of data lines DL.
  • the plurality of enable signal lines EL, the plurality of scan signal lines GL and the plurality of reset signal lines RL generally extend along the first direction X
  • the plurality of data lines DL generally extend along the second direction Y.
  • “approximately extending along the second direction Y” means that the overall routing direction of the data line DL is along the second direction Y, but it is not limited to that every position of the data line DL is strictly along the second direction.
  • Y extension That is, “extending substantially along the second direction Y” here not only includes data lines DL that strictly extend along the second direction Y at every position, but also includes data lines DL in which local line segments are bent to avoid interference, taking into account the interference of other structures. . For example, part of the data line DL is bent around the mounting hole H and bypasses the mounting hole H in the frame area A10. This article will describe in detail the structure of the pixel circuit and the specific film layer structure later in this article.
  • the pixel circuit 130 of the sub-pixel P in the same row can be electrically connected to a set of signal lines (enable signal line EL, multiple scan signal lines GL, multiple reset signal lines RL) extending substantially along the first direction X. Connection, the pixel circuits 130 of the sub-pixels P in the same column may be electrically connected to one data line DL.
  • the above-mentioned set of signal lines extending generally along the first direction X includes at least one enable signal line EL, at least one scan signal line GL and at least one reset signal line RL.
  • the number of signals included in the above-mentioned set of signal lines extending generally along the first direction X depends on the structure of the pixel circuit 130, which will be described later in this article in conjunction with the structure of the pixel circuit 130.
  • the pixel circuit 130 adopts Low Temperature Polycrystalline Oxide (LTPO for short) technology, that is, a pixel circuit 130 also includes Low Temperature Polycrystalline Silicon (Low Temperature Poly-Silicon for short, LTPS for short). Thin film transistors and oxide (Oxide) thin film transistors, which can achieve high charge mobility, stability and scalability at low production costs.
  • LTPO Low Temperature Polycrystalline Oxide
  • Oxide Oxide
  • the pixel circuit 130 has two active layers at the same time, wherein the material of the active layer pattern of the LTPS thin film transistor is low-temperature polysilicon, and the material of the active layer pattern of the oxide thin film transistor is oxide.
  • pixel circuit 130 As an LTPO pixel circuit as an example, some embodiments of the present disclosure are schematically described below.
  • the pixel circuit 130 has a variety of structures, and the configuration can be selected according to actual needs.
  • the structure of the pixel circuit 130 may include a "2T1C”, “3T1C”, “6T1C”, “7T1C”, “8T1C”, “6T2C” or “7T2C” structure.
  • T represents the transistor
  • the number in front of “T” represents the number of transistors
  • C represents the storage capacitor
  • the number in front of "C” represents the number of storage capacitors.
  • the stability of the transistors and the light-emitting device 140 in the pixel circuit 130 may decrease (for example, the threshold voltage of the driving transistor drifts), affecting the display effect of the display panel 100, so that it is necessary to Pixel P is compensated.
  • a pixel compensation circuit may be provided in the sub-pixel P, so that the sub-pixel P is internally compensated by the pixel compensation circuit.
  • the driving transistor or light-emitting device can be sensed through the transistor inside the sub-pixel P, and the sensed data can be transmitted to an external sensing circuit, so that the external sensing circuit can be used to calculate the driving voltage value that needs to be compensated and provide feedback. , thereby achieving external compensation for sub-pixel P.
  • the pixel circuit 130 is any one of the pixel circuits 130 located in the N-th row of sub-pixels P; where N is a positive integer.
  • the pixel circuit 130 includes 8 transistors T and 1 storage capacitor Cst.
  • the first transistor T1 is a reset transistor for resetting the first node
  • the second transistor T2 is a diode connection transistor
  • the third transistor T3 is a driving transistor
  • the fourth transistor T4 is a data writing transistor
  • the fifth transistor T5 and The sixth transistor T6 is a light emission control transistor
  • the seventh transistor T7 is a reset transistor for resetting the anode of the light emitting device (the fourth node N4)
  • the eighth transistor is a reset transistor for resetting the second node and the third node.
  • the third transistor T3 may have a double-gate structure to improve the stability of the third transistor T3.
  • T3, T4, T5, T6, T7 and T8 are P-type LTPS transistors, so that these transistors have higher mobility and more stable source voltage, suitable for driving light emitting devices.
  • 140; T1 and T2 are N-type Oxide transistors, so that the first transistor T1 and the second transistor T2 have lower leakage current and can better maintain the voltage stability of the third transistor T3 and the storage capacitor Cst.
  • nodes N1, N2, N3 and N4 do not represent actual existing components, but represent the meeting points of relevant electrical connections in the circuit diagram. That is to say, these nodes are determined by the circuit diagram. A node equivalent to the meeting point of relevant electrical connections.
  • a set of signal lines may include an enable signal line EL, two scan signal lines GL and two reset signal lines RL.
  • the enable signal line EL is electrically connected to the enable signal terminal EM of the pixel circuit 130 and is configured to transmit the enable signal Em.
  • the two scanning signal lines GL may include a first scanning signal line GL1 and a second scanning signal line GL2.
  • the first scanning signal line GL1 is electrically connected to the first scanning signal terminal GATE1 of the pixel circuit 130 and is configured to transmit the first scanning signal Gate1.
  • the second scanning signal line GL2 is electrically connected to the second scanning signal terminal GATE2 of the pixel circuit 130 and is configured to transmit the second scanning signal Gate2.
  • the two reset signal lines RL may include a first reset signal line RL1 and a second reset signal line RL2.
  • the first reset signal line RL1 is electrically connected to the first reset signal terminal RESET1 of the pixel circuit 130 and is configured to transmit the first reset signal Reset1.
  • the second reset signal line RL2 is electrically connected to the second reset signal terminal RESET2 of the pixel circuit 130 and is configured to transmit the second reset signal Reset2.
  • the third scanning signal terminal GATE3 of the pixel circuit 130 can be connected to the same signal line as the second reset signal terminal RESET2 of the pixel circuit 130.
  • the second reset signal terminal RESET2 of the pixel circuit 130 and the third scanning signal terminal GATE3 can be connected to the same signal line.
  • the signal terminals GATE3 are both electrically connected to the second reset signal line RL2.
  • the enable signal line, the scan signal line and the reset signal line are distributed on two layers, and the signal lines distributed on the two layers are on the substrate.
  • the orthographic projections on the substrate are staggered, resulting in the overall area occupied by the orthographic projections of the enable signal lines, scan signal lines and reset signal lines on the substrate being larger, that is, the size of the frame area is larger.
  • the display black border at the edge of the mounting hole is larger, resulting in a decrease in the screen-to-body ratio of the display panel and affecting the integrity of the display screen.
  • At least one enable signal line EL includes one located in the main display area A2
  • at least one scanning signal line GL includes a first sub-scanning signal line GL11 located in the main display area A2 and a second sub-scanning signal line GL12 located in the frame area A10.
  • at least one reset signal line RL includes a first sub-reset signal line RL11 located in the main display area A2 and a second sub-reset signal line RL12 located in the frame area A10.
  • the second sub-enable signal line EL12 of the plurality of enable signal lines EL the second sub-scan signal line GL12 of the plurality of scan signal lines GL and the second sub-scan signal line GL12 of the plurality of reset signal lines RL
  • the sub-reset signal lines RL12 at least three signal lines (at least one of the second sub-enable signal line EL12, the second sub-scanning signal line GL12 and the second sub-reset signal line RL12) are located on three different layers.
  • the overall area occupied by the signal lines located on three different layers can be reduced, so that all The overall area required by the second sub-enable signal line EL12, the second sub-scan signal line GL12, and the second sub-reset signal line RL12 is reduced. That is to say, the area of the frame area A10 can be reduced, thereby reducing the display black border at the edge of the mounting hole H during the display process, and improving the screen-to-body ratio of the display panel 100 .
  • the overall area required by all the second sub-enable signal lines EL12, the second sub-scan signal line GL12 and the second sub-reset signal line RL12 is reduced, thereby reducing the area of the frame area A10 (see Figure 6).
  • the display black border at the edge of the mounting hole H is reduced, and the screen-to-body ratio of the display panel 100 is increased.
  • the orthographic projections of the signal lines located in three different layers on the substrate 10 at least partially overlap.
  • An exemplary description will be given later in this article in conjunction with specific signal lines and specific film layer structures.
  • the display panel 100 may sequentially include a first gate conductive layer 12, a second gate Conductive layer 14 and third gate conductive layer 16 .
  • the display panel 100 may also include a first gate insulating layer 11 , a second gate insulating layer 13 and a third gate insulating layer 15 .
  • the first gate insulating layer 11 is disposed between the substrate 10 and the first gate conductive layer 12
  • the second gate insulating layer 13 is disposed between the first gate conductive layer 12 and the second gate conductive layer 14
  • the third gate insulating layer 15 is disposed between the second gate conductive layer 14 and the third gate conductive layer 16 .
  • the enable signal line EL, the scan signal line GL, and the reset signal line RL may be provided on at least one of the first gate conductive layer 12, the second gate conductive layer 14, and the third gate conductive layer 16.
  • the signal lines electrically connected to the LTPO pixel circuit of 8T1C may include the enable signal line EL, the first scan signal line GL1, the second scan signal line GL2, the first reset signal line RL1 and the second reset signal line. RL2.
  • the first sub-enable signal line EL11 of the enable signal line EL, the first sub-reset signal line RL11 of the first reset signal line RL1 and the second scanning signal line GL2 may be disposed on the first gate conductive layer 12 (see FIG. 7 ) and/or the second gate conductive layer 14 (see FIG. 7 ).
  • part of the first sub-scanning signal line GL11 of the first scanning signal line GL1 may be provided on the second gate conductive layer 14 (see FIG. 7 ), and part of the wiring may be provided on the third gate conductive layer 14 .
  • Conductive layer 16 (see Figure 7).
  • the first sub-reset signal line RL11 of the second reset signal line RL2 may be partially provided on the second gate conductive layer 14 (see FIG. 7 ), and part of the wiring may be provided on the third gate conductive layer 16 (see FIG. 7 ).
  • the first sub-scanning signal line GL11 above the channel region of the second transistor T2 is provided in the third gate conductive layer 16 (see Figure 7), and the seventh The first sub-reset signal line RL11 above the channel region of the transistor T7 is provided on the third gate conductive layer 16 (see FIG. 7 ).
  • the second sub-enable signal line EL12 of the plurality of enable signal lines EL there are at least three signal lines that may be respectively located on the first gate conductive layer 12, the second gate conductive layer 14, and the third gate conductive layer 16.
  • the signal lines electrically connected to the LTPO pixel circuit of 8T1C may include the enable signal line EL, the first scan signal line GL1, the second scan signal line GL2, the first reset signal line RL1 and the second reset signal line. RL2.
  • the signal line transmitting the signal can be driven on both sides. input; in order to save costs, simplify the scan driving circuit 110 of the peripheral area B and reduce the size of the peripheral area B, the signal line transmitting the signal can be input in a single-side driving mode.
  • single-sided driving means that the display panel 100 can provide the scan driving circuit 110 on one side in the peripheral area B along the extending direction of the signal lines, and drive each signal line row by row from one side.
  • Double-sided driving means that the display panel 100 can be provided with scan drive circuits 110 on both sides in the peripheral area B along the extension direction of the signal lines, and the two scan drive circuits 110 drive each row from both sides at the same time. signal line.
  • the second scan signal line GL2 adopts a double-sided driving method to enable the signal line EL, the first scan signal line GL1, the first reset signal line RL1 and the second reset signal
  • the lines RL2 all adopt a single-side driving method to reduce the size of the peripheral area B and reduce the cost while ensuring the accuracy of writing the data signal Data.
  • the peripheral area B is located at least on the first side and the second side of the main display area A2, and the peripheral area B on the first side and the second side of the main display area A2 is provided with a scan drive circuit. 110.
  • the first side and the second side are opposite sides of the main display area A2 along the extension direction of the signal line.
  • the scan driving circuit 110 includes a first scan driving circuit 111 and a second scan driving circuit 112 .
  • the first scan drive circuit 111 is provided in the peripheral area B and is located on the first side of the main display area A2; the first scan drive circuit 111 is connected with the first scan signal line GL1, the second scan signal line GL2, the enable signal line EL, The reset signal line RL is electrically connected.
  • the second scan drive circuit 112 is disposed in the peripheral area B and is located on the second side of the main display area A2; the second scan drive circuit 112 is electrically connected to the second scan signal line GL2.
  • the second scan signal line GL2 adopts a double-side drive method
  • the enable signal line EL, the first scan signal line GL1, the first reset signal line RL1 and the second reset signal line RL2 all adopt a single-side drive method.
  • the enable signal line EL extending in the direction (first direction X) through the mounting hole H includes a first sub-enable signal line EL11 and a second sub-enable signal line EL11.
  • the first scanning signal line GL1 extending through the mounting hole H includes a first sub-scanning signal line GL11 and a second sub-scanning signal line GL12.
  • the first reset signal line RL1 and the second reset signal line RL2 extending through the mounting hole H both include a first sub-reset signal line RL1 and a second sub-reset signal line RL2.
  • the second scanning signal line GL2 adopts a double-side driving method, the second scanning signal line GL2 can be disconnected at the mounting hole H to avoid the mounting hole H. With this arrangement, the second scanning signal line GL2 does not need to pass through the frame area A10, that is, there is no need to dispose the second scanning signal line GL2 on the frame area A10, and the area of the frame area A10 can be further reduced.
  • the plurality of second scanning signal lines GL2 include first type scanning signal lines GL21 , second type scanning signal lines GL22 and third type scanning signal lines GL23 .
  • the mounting hole H is located on the second type scanning signal line GL21 . In the extending direction of the line GL22 and the third type scanning signal line GL23.
  • the first type of scanning signal line GL21 extends from the peripheral area B located on the first side of the main display area A2 along the first direction X to the peripheral area B located on the second side of the main display area A2.
  • the second type of scanning signal line GL22 extends from the peripheral area B located on the first side of the main display area A2 to the frame area A10 along the first direction X.
  • the third type of scanning signal line GL23 extends from the peripheral area B located on the second side of the main display area A2 to the frame area A10 along the first direction X.
  • the first scan driving circuit 111 is electrically connected to the first scanning signal line GL1, the first type scanning signal line GL21, the second type scanning signal line GL22, the enable signal line EL, and the reset signal line RL.
  • the circuit 112 is electrically connected to the first type scanning signal line GL21 and the third type scanning signal line GL23.
  • the second sub-enable signal line EL12 of the plurality of enable signal lines EL, the second sub-scan signal line GL12 of the plurality of scan signal lines GL and the second sub-reset signal line RL12 of the plurality of reset signal lines RL are in The distribution of the first gate conductive layer 12, the second gate conductive layer 14 and the third gate conductive layer 16 is not unique.
  • the second sub-enable signal line EL12 among the plurality of enable signal lines EL is located on the second gate conductive layer 14 .
  • At least two reset signal lines RL include a first sub-reset signal line RL11 located in the main display area A1 and a second sub-reset signal line RL12 located in the frame area A10.
  • some second sub-reset signal lines The line RL12 is located on the first gate conductive layer 12
  • some second sub-reset signal lines RL12 are located on the third gate conductive layer 16 .
  • the second sub-scan signal line GL12 among the plurality of scan signal lines GL is located on the second gate conductive layer 14 .
  • the second sub-enable signal line EM12 among the plurality of enable signal lines EM is located on the second gate conductive layer 14 .
  • At least two reset signal lines RL include the above-mentioned first reset signal line RL1 and the above-mentioned second reset signal line RL2.
  • At least one first reset signal line RL1 includes a first sub-reset signal line RL11 and a second sub-reset signal line RL12, and the second sub-reset signal line RL11 of the first reset signal line RL1 is located on the first gate conductive layer 12.
  • At least one second reset signal line RL1 includes a first sub-reset signal line RL11 and a second sub-reset signal line RL12, and the second sub-reset signal line RL12 of the second reset signal line RL2 is located on the third gate conductive layer 16.
  • the plurality of scanning signal lines GL include the above-mentioned first scanning signal line GL1 and the above-mentioned second scanning signal line GL2.
  • At least one first scanning signal line GL1 includes a first sub-scanning signal line GL11 and a second sub-scanning signal line GL12, and the A second sub-scan signal line GL12 of a scan signal line GL1 is located on the second gate conductive layer 14 . From the above, it can be known that the second scanning signal line GL2 does not need to be provided in the frame area A10.
  • the second sub-reset signal line RL11 of the first reset signal line RL1 is located on the first gate conductive layer 12, the second sub-enable signal line EM12 of the enable signal line EM, and the first scan signal line GL1
  • the second sub-scanning signal line GL12 is located on the second gate conductive layer 14
  • the second sub-reset signal line RL12 of the second reset signal line RL2 is located on the third gate conductive layer 16 .
  • the orthographic projection of the second sub-reset signal line RL12 located on the third gate conductive layer 16 on the substrate 10 can be consistent with the second sub-enable signal line located on the second gate conductive layer 14 .
  • the orthographic projection of the signal line RL12 and/or the second sub-scanning signal line GL12 on the substrate 10 at least partially overlaps to reduce the second sub-reset signal line RL12 located in the third gate conductive layer 16 and the second sub-reset signal line RL12 located in the second gate conductive layer 16.
  • the overall area required by the sub-reset signal line RL12 is reduced, thereby reducing the area of the frame area A10.
  • the orthographic projection of the second sub-reset signal line RL12 located on the third gate conductive layer 16 on the substrate 10 can be in line with the second sub-reset signal line RL12 located on the first gate conductive layer 12 .
  • the orthographic projection on the substrate 10 at least partially overlaps to reduce the total space occupied by the second sub-reset signal line RL12 located on the third gate conductive layer 16 and the second sub-reset signal line RL12 located on the first gate conductive layer 12 Therefore, the area required by all the second sub-enable signal lines EL12, the second sub-scan signal lines GL12 and the second sub-reset signal lines RL12 is reduced, thereby reducing the area of the frame area A10.
  • the orthographic projection of the second sub-reset signal line RL12 located on the third gate conductive layer 16 on the substrate 10 is different from the second sub-enable signal line RL12 located on the second gate conductive layer 14 and /Or the orthographic projection of the second sub-scanning signal line GL12 on the substrate 10 at least partially overlaps, and at least partially intersects with the orthographic projection of the second sub-reset signal line RL12 located on the first gate conductive layer 12 on the substrate 10 stack to reduce the second sub-reset signal line RL12 located on the third gate conductive layer 16, the second sub-enable signal line RL12 and/or the second sub-scan signal line GL12 located on the second gate conductive layer 14, and the second sub-reset signal line RL12 located on the second gate conductive layer 14.
  • the total area occupied by the second sub-reset signal line RL12 of the first gate conductive layer 12 is such that all the second sub-enable signal lines EL12, the second sub-scanning signal line GL12 and the second sub-reset signal line RL12 are collectively occupied by the area.
  • the required occupied area is reduced, thereby reducing the area of the frame area A10.
  • the above-mentioned scan driving circuit 110 may include multiple shift registers, and one shift register may be electrically connected to multiple pixel circuits 130 in at least one row of sub-pixels P.
  • the scan drive circuit 110 includes the above-mentioned first scan drive circuit 111 and the above-mentioned second scan drive circuit 112 .
  • the first scan drive circuit 111 includes a plurality of cascaded third scan drive circuits.
  • a shift register RS1 each first shift register RS1 is connected to at least two first scan signal lines GL1, at least two enable signal lines EL, at least two first reset signal lines RL1 and at least two second reset lines
  • the signal line RL2 is electrically connected, and each first shift register 111 is also electrically connected to at least two first-type scanning signal lines GL21 or at least two second-type scanning signal lines GL22.
  • the second scan driving circuit 112 includes a plurality of cascaded second shift registers RS2.
  • Each second shift register RS2 is electrically connected to at least two first type scanning signal lines GL21 or at least two third type scanning signal lines GL23. connect.
  • FIG. 13 only the first shift register and the two second reset signal lines are electrically connected as an example for illustration.
  • one first scanning signal line GL1 includes a first sub-scanning signal line GL11 and a first scanning signal line GL1.
  • the second sub-scan signal line GL12 each of the remaining first scan signal lines GL1 includes two scan line segments, and one scan line segment is connected to one end of the first shift register RS1 and the second sub-scan signal line GL12, and the other one is connected to the first shift register RS1 and one end of the second sub-scan signal line GL12.
  • a scanning line segment is electrically connected to the other end of the second sub-scanning signal line GL12 and extends to the boundary of the second side of the main display area A2 to reduce the number of the second sub-scanning signal lines GL12 provided on the frame area A10. This further reduces the overall area required by all the second sub-enable signal lines EL12, the second sub-scan signal line GL12 and the second sub-reset signal line RL12, thereby further reducing the area of the frame area A10.
  • FIG. 13 only the second reset signal line is taken as an example for illustration.
  • one enable signal line EL includes a first sub-enable signal line EL11 and a second sub-enable signal.
  • Line EL12 each of the remaining enable signal lines EL includes two enable trace segments, and one enable trace segment is connected to one end of the first shift register RS1 and the second sub-enable signal line EL12, and the other enables
  • the trace segment is electrically connected to the other end of the second sub-enable signal line EL12 and extends to the boundary of the second side of the main display area A2 to reduce the number of the second sub-enable signal line EL12 provided on the frame area A10.
  • one first reset signal line RL1 includes a first sub-reset signal line RL11 and a second sub-reset signal.
  • Line RL12 each of the remaining first reset signal lines RL1 includes two first reset wiring segments, and one first reset wiring segment is connected to one end of the first shift register RS1 and the second sub-reset signal line RL12, and the other The first reset wiring segment is electrically connected to the other end of the second sub-reset signal line RL12 and extends to the boundary of the second side of the main display area A2 to reduce the number of the second sub-reset signal line RL12 provided on the frame area A10 , thereby further reducing the overall area required by all the second sub-enable signal lines EL12, the second sub-scan signal line GL12 and the second sub-reset signal line RL12, thereby further reducing the area of the frame area A10.
  • FIG. 13 only the second reset
  • one second reset signal line RL2 includes a first sub-reset signal line RL11 and a second sub-reset signal.
  • Line RL12 each of the remaining second reset signal lines includes two second reset line segments, and one second reset line segment is connected to one end of the first shift register RS1 and the second sub-reset signal line RL12, and the other second reset line segment is connected to the first shift register RS1 and one end of the second sub-reset signal line RL12.
  • the two reset wiring segments are electrically connected to the other end of the second sub-reset signal line RL12 and extend to the boundary of the second side of the main display area A2 to reduce the number of the second sub-reset signal line RL12 provided on the frame area A10. This further reduces the overall area required by all the second sub-enable signal lines EL12, the second sub-scan signal line GL12 and the second sub-reset signal line RL12, thereby further reducing the area of the frame area A10.
  • FIG. 13 only the second reset signal line is taken as an example for illustration.
  • the display panel 100 further includes a first source-drain conductive layer 18 and a second source-drain conductive layer 20 .
  • the first source-drain conductive layer 18 is provided On the side of the third gate conductive layer 16 away from the substrate 10
  • the second source-drain conductive layer 20 is disposed on the side of the first source-drain conductive layer 18 away from the substrate 10 .
  • the display panel 100 may also include an interlayer insulating layer 17 , a first flat layer 19 and a second flat layer 21 .
  • the interlayer insulating layer 17 is disposed between the third gate conductive layer 16 and the first source-drain conductive layer 18.
  • the first planarization layer 19 is disposed between the first source-drain conductive layer 18 and the second source-drain conductive layer 20.
  • the two flat layers 21 are disposed on the side of the second source-drain conductive layer 20 away from the substrate 10 .
  • At least two data lines DL include a first sub-data line DL11 located in the main display area A2 and a second sub-data line DL12 located in the frame area A10.
  • some second sub-data lines DL12 are located in the first source-drain conductive layer 18, and other second sub-data lines DL12 are located in the second source-drain conductive layer 20 .
  • the overall area occupied by the data lines DL located at different layers can be reduced, thereby reducing the overall area occupied by all the data lines DL. That is to say, the area of the frame area A10 can be further reduced, thereby reducing the display black border at the edge of the mounting hole H during the display process, and improving the screen-to-body ratio of the display panel 100 .
  • the thickness of the third gate insulating layer 15 is greater than the thickness of the interlayer insulating layer 17 .
  • the thickness of the interlayer insulating layer 17 is The thickness of the third gate insulating layer 15 is
  • the material of the interlayer insulating layer 17 includes inorganic insulating materials.
  • the material of the interlayer insulating layer 17 includes silicon nitride and/or silicon oxide.
  • the material of the third gate insulating layer 15 includes an inorganic insulating material.
  • the material of the third gate insulating layer 15 includes a silicon nitride and/or silicon oxide layer.
  • the two opposite side surfaces of the signal line located on the third gate conductive layer 16 are first slopes, and the two first slopes of the same signal line are away from the boundary between the substrate 10
  • the distance is less than the distance between the two first slopes close to the boundary of the substrate 10, which can reduce the gradient of the interlayer insulating layer 17 climbing at the boundary of the signal line located on the third gate conductive layer 16, reducing the interlayer
  • the risk of the insulating layer 17 breaking at the boundary slope of the signal line located in the third gate conductive layer 16 (position C in Figure 12), thereby reducing the risk of the signal line located in the third gate conductive layer 16 being connected to the first source-drain conductive layer.
  • the second sub-data line DL12 of layer 18 creates the risk of short circuit.
  • the angle between the first slope and the plane of the surface of the substrate 10 away from the first gate conductive layer 12 is less than or equal to 30°.
  • the orthographic projection of the second sub-data line DL12 located on the first source-drain conductive layer 18 on the substrate 10 is different from the signal line located on the third gate conductive layer 16 .
  • the orthographic projections on the substrate 10 are staggered to prevent the interlayer insulating layer 17 from breaking (position C in FIG. 12 ), causing the second sub-data line DL12 located in the first source-drain conductive layer 18 to be separated from the third gate conductive layer 16 There is a short circuit problem between the signal lines.
  • the boundary of the orthographic projection of the second sub-data line DL12 located on the first source-drain conductive layer 18 on the substrate 10 is at the orthogonal projection of the signal line located on the third gate conductive layer 16 on the substrate 10 .
  • the interlayer insulating layer 17 within the projected boundary to prevent the interlayer insulating layer 17 from breaking at the boundary slope of the signal line located in the third gate conductive layer 16 (position C in FIG. 12), causing the second source-drain conductive layer 18 to A short circuit problem occurs between the sub-data line DL12 and the signal line located on the third gate conductive layer 16 .
  • the second sub-data line DL12 located on the first source-drain conductive layer 18 is on the substrate 10
  • the boundary of the orthographic projection is within the boundary of the orthographic projection of the signal line located on the third gate conductive layer 16 away from the surface of the substrate 10 on the substrate 10 .
  • the thickness of the third gate insulating layer 15 is greater than the thickness of the second gate insulating layer 13 .
  • the thickness of the second gate insulating layer 13 is And/or, the thickness of the third gate insulating layer 15 is
  • the opposite sides of the signal line located on the first gate conductive layer 12 are second slopes, and the two second slopes of the same signal line are far away from the boundary of the substrate 10 , less than the distance between the two second slopes close to the boundary of the substrate 10, which can reduce the gradient of the second gate insulating layer 13 climbing at the boundary of the signal line located on the first gate conductive layer 12, reducing the second The risk of the gate insulating layer 13 breaking at the boundary slope of the signal line located on the first gate conductive layer 12 is thereby reduced, thereby reducing the risk of the signal line located on the first gate conductive layer 12 being short of the signal line located on the second gate conductive layer 14 risk.
  • the angle between the second slope and the plane of the surface of the substrate 10 away from the first gate conductive layer 12 is less than or equal to 30°.
  • the orthographic projection of the signal line located on the first gate conductive layer 12 on the substrate 10 is different from the orthographic projection of the signal line located on the second gate conductive layer 14 on the substrate 10 .
  • the orthographic projections are staggered to avoid the problem of a short circuit between the signal line located on the first gate conductive layer 12 and the signal line located on the second gate conductive layer 14 due to breakage of the second gate insulating layer 13 .
  • the boundary of the orthographic projection of the signal line located on the second gate conductive layer 14 on the substrate 10 is at the boundary of the orthographic projection of the signal line located on the first gate conductive layer 12 on the substrate 10. within the boundary to prevent the second gate insulating layer 13 from breaking at the boundary slope of the signal line located in the first gate conductive layer 12, causing the signal line located in the first gate conductive layer 12 to be different from the signal line located in the second gate conductive layer There is a short circuit problem between the signal lines of 14.
  • the boundary of the orthographic projection of the signal lines located on the second gate conductive layer 14 on the substrate 10 is, Within the boundary of the orthographic projection of the signal line located on the first gate conductive layer 12 away from the surface of the substrate 10 on the substrate 10 .
  • related technology 1 represents an embodiment of a display panel using an 8T1C LTPO pixel circuit
  • related technology 2 represents an embodiment of a display panel using a 7T1C LTPS pixel circuit.
  • the embodiment of the present disclosure can reduce the overall size of the frame area by 256.2 ⁇ m when using a display panel with an 8T1C LTPO pixel circuit, achieving the same results as using a 7T1C LTPS.
  • the overall size of the frame area of the display panel of the pixel circuit is approximately the same.

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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示面板（100），具有功能器件设置区（A1），及至少部分围绕功能器件设置区（A1）的主显示区（A2）；功能器件设置区（A1）中设置有安装孔（H），功能器件设置区（A1）包括围绕安装孔（H）的边框区（A10）。显示面板（100）包括衬底（10）、多个像素电路（130）、多条使能信号线（EL）、多条扫描信号线（GL）和多条复位信号线（RL）。至少一条使能信号线（EL）包括位于边框区（A10）的第二子使能信号线（EL12）。至少一条扫描信号线（GL）包括位于边框区（A10）的第二子扫描信号线（GL12）。至少一条复位信号线（RL12）包括位于边框区（A10）的第二子复位信号线（RL）。其中，多条使能信号线（EL）的第二子使能信号线（EL12）、多条扫描信号线（GL）的第二子扫描信号线（GL12）和多条复位信号线（RL）的第二子复位信号线（RL12）中，至少存在三条信号线位于不同的三层。

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
随着显示技术的飞速发展，显示装置已经逐渐遍及在人们的生活中。其中，有机发光二极管(Organic Light Emitting Diode，简称：OLED)由于具有自发光、低功耗、宽视角、响应速度快、高对比度以及柔性显示等优点，因而被广泛的应用于手机、电视、笔记本电脑等智能产品中。
发明内容
一方面，提供一种显示面板。所述显示面板具有功能器件设置区，及至少部分围绕所述功能器件设置区的主显示区；所述功能器件设置区中设置有安装孔，所述功能器件设置区包括围绕所述安装孔的边框区。
所述显示面板包括衬底、多个像素电路、多条使能信号线、多条扫描信号线和多条复位信号线。所述多个像素电路设置于所述衬底上，且位于所述主显示区。所述多条使能信号线与所述像素电路电连接；至少一条使能信号线包括位于所述主显示区的第一子使能信号线和位于所述边框区的第二子使能信号线。所述多条扫描信号线与所述像素电路电连接；至少一条扫描信号线包括位于所述主显示区的第一子扫描信号线和位于所述边框区的第二子扫描信号线。所述多条复位信号线与所述像素电路电连接；至少一条复位信号线包括位于所述主显示区的第一子复位信号线和位于所述边框区的第二子复位信号线。
其中，所述多条使能信号线的第二子使能信号线、所述多条扫描信号线的第二子扫描信号线和所述多条复位信号线的第二子复位信号线中，至少存在三条信号线位于不同的三层。
在一些实施例中，所述多条使能信号线的第二子使能信号线、所述多条扫描信号线的第二子扫描信号线和所述多条复位信号线的第二子复位信号线中，位于不同的三层的信号线在所述衬底上的正投影至少部分交叠。
在一些实施例中，沿垂直于所述衬底且远离所述衬底的方向，所述显示面板依次包括第一栅导电层、第二栅导电层和第三栅导电层，所述多条使能信号线的第二子使能信号线、所述多条扫描信号线的第二子扫描信号线和所述多条复位信号线的第二子复位信号线中，至少存在三条信号线分别位于所述第一栅导电层、所述第二栅导电层和所述第三栅导电层。
在一些实施例中，所述多条使能信号线中的第二子使能信号线位于所述第二栅导电层。至少两条复位信号线包括位于所述主显示区的第一子复位信号线和位于所述边框区的第二子复位信号线；所述至少两条复位信号线中，一些所述第二子复位信号线位于所述第一栅导电层，另一些所述第二子复位信号线位于所述第三栅导电层。所述多条扫描信号线中的第二子扫描信号线位于所述第二栅导电层。
在一些实施例中，位于所述第三栅导电层的第二子复位信号线在所述衬底上的正投影，与位于所述第二栅导电层的第二子使能信号线和/或第二子扫描信号线在所述衬底上的正投影至少部分交叠。和/或，位于所述第三栅导电层的第二子复位信号线在所述衬底上的正投影，与位于所述第一栅导电层的第二子复位信号线在所述衬底上的正投影至少部分交叠。
在一些实施例中，所述至少两条复位信号线包括多条第一复位信号线和多条第二复位信号线。所述第一复位信号线被配置为传输第一复位信号；至少一条第一复位信号线包括所述第一子复位信号线和所述第二子复位信号线，且所述第一复位信号线的第二子复位信号线位于所述第一栅导电层。所述第二复位信号线被配置为传输第二复位信号；至少一条第二复位信号线包括所述第一子复位信号线和所述第二子复位信号线，且所述第二复位信号线的第二子复位信号线位于所述第三栅导电层。
在一些实施例中，所述多条扫描信号线包括多条第一扫描信号线，所述多条第一扫描信号线被配为传输第一扫描信号；至少一条第一扫描信号线包括所述第一子扫描信号线和所述第二子扫描信号线，且所述第一扫描信号线的第二子扫描信号线位于所述第二栅导电层。
在一些实施例中，所述显示面板具有周边区，所述周边区至少位于所述主显示区的第一侧和第二侧，所述第一侧和所述第二侧为所述主显示区相对的两侧。
所述多条扫描信号线还包括多条第二扫描信号线，所述多条第二扫描信号线被配置为传输第二扫描信号；所述多条第二扫描信号线包括第一类扫描信号线、第二类扫描信号线和第三类扫描信号线，所述安装孔位于所述第二类扫描信号线和所述第三类扫描信号线的延伸方向上。
其中，所述第一类扫描信号线由位于所述主显示区的第一侧的周边区，沿第一方向延伸至位于所述显示区的第二侧的周边区。所述第二类扫描信号线由位于所述主显示区的第一侧的周边区，沿所述第一方向延伸至所述边框区。所述第三类扫描信号线由位于所述显示区的第二侧的周边区，沿所述第 一方向延伸至所述边框区。
在一些实施例中，所述显示面板还包括第一扫描驱动电路和第二扫描驱动电路。所述第一扫描驱动电路设置于所述周边区，且位于所述主显示区的第一侧；所述第一扫描驱动电路与所述第一扫描信号线、所述第一类扫描信号线、所述第二类扫描信号线、所述使能信号线、所述复位信号线电连接。所述第二扫描驱动电路设置于所述周边区，且位于所述主显示区的第二侧；所述第二扫描驱动电路与所述第一类扫描信号线、所述第三类扫描信号线电连接。
在一些实施例中，所述第一扫描驱动电路包括级联的多个第一移位寄存器，每个第一移位寄存器与至少两条所述第一扫描信号线、至少两条所述使能信号线、至少两条所述第一复位信号线和至少两条第二复位信号线电连接，每个第一移位寄存器还与至少两条所述第一类扫描信号线或至少两条所述第二类扫描信号线电连接。所述第二扫描驱动电路包括级联的多个第二移位寄存器，每个第二移位寄存器与至少两条所述第一类扫描信号线或至少两条所述第三类扫描信号线电连接。
在一些实施例中，与同一个第一移位寄存器连接的至少两条第一扫描信号线中，一条第一扫描信号线包括所述第一子扫描信号线和所述第二子扫描信号线，其余的每条第一扫描信号线包括两条扫描走线段，且一条扫描走线段与所述第一移位寄存器和所述第二子扫描信号线的一端连接，另一条扫描走线段与所述第二子扫描信号线的另一端电连接，且延伸至所述主显示区的第二侧的边界。
和/或，与同一个第一移位寄存器连接的至少两条使能信号线中，一条使能信号线包括所述第一子使能信号线和所述第二子使能信号线，其余的每条使能信号线包括两条使能走线段，且一条使能走线段与所述第一移位寄存器和所述第二子使能信号线的一端连接，另一条使能走线段与所述第二子使能信号线的另一端电连接，且延伸至所述主显示区的第二侧的边界。
和/或，与同一个第一移位寄存器连接的至少两条第一复位信号线中，一条第一复位信号线包括所述第一子复位信号线和所述第二子复位信号线，其余的每条第一复位信号线包括两条第一复位走线段，且一条第一复位走线段与所述第一移位寄存器和所述第二子复位信号线的一端连接，另一条第一复位走线段与所述第二子复位信号线的另一端电连接，且延伸至所述主显示区的第二侧的边界。
和/或，与同一个第一移位寄存器连接的至少两条第二复位信号线中， 一条第二复位信号线包括所述第一子复位信号线和所述第二子复位信号线，其余的每条第二复位信号线包括两条第二复位走线段，且一条第二复位走线段与所述第一移位寄存器和所述第二子复位信号线的一端连接，另一条第二复位走线段与所述第二子复位信号线的另一端电连接，且延伸至所述主显示区的第二侧的边界。
在一些实施例中，所述显示面板还包括第一源漏导电层和第二源漏导电层，所述第一源漏导电层设置于所述第三栅导电层远离所述衬底的一侧，所述第二源漏导电层设置于所述第一源漏导电层远离所述衬底的一侧。
所述显示面板还包括多条数据线，所述多条数据线与所述像素电路电连接；至少两条数据线包括位于所述主显示区的第一子数据线和位于所述边框区的第二子数据线；位于所述边框区的至少两条第二子数据线中，一些第二子数据线位于所述第一源漏导电层，另一些第二子数据线位于所述第二源漏导电层。
在一些实施例中，位于所述第一源漏导电层的第二子数据线在所述衬底上的正投影，与位于所述第三栅导电层的信号线在所述衬底上的正投影错开设置。和/或，位于所述第一源漏导电层的子数据线在所述衬底上的正投影的边界，在位于所述第三栅导电层的信号线在所述衬底上的正投影的边界内。
在一些实施例中，位于所述第三栅导电层的信号线的相对的两个侧面为第一斜面，且同一个信号线的两个第一斜面远离所述衬底的边界之间的距离，小于两个第一斜面靠近所述衬底的边界之间的距离。
在一些实施例中，所述第一斜面与所述衬底远离所述第一栅导电层的表面所在的平面的夹角的小于或等于30°。
在一些实施例中，位于所述第一栅导电层的信号线在所述衬底上的正投影，与位于所述第二栅导电层的信号线在所述衬底上的正投影错开设置。和/或，位于所述第二栅导电层的信号线在所述衬底上的正投影的边界，在位于所述第一栅导电层的信号线在所述衬底上的正投影的边界内。
在一些实施例中，位于所述第一栅导电层的信号线的相对的两侧面为第二斜面，且同一个信号线的两个第二斜面远离所述衬底的边界之间的距离，小于两个第二斜面靠近所述衬底的边界之间的距离。
在一些实施例中，所述第二斜面与所述衬底远离所述第一栅导电层的表面所在的平面的夹角的小于或等于30°。
在一些实施例中，所述显示面板还包括层间绝缘层、第二栅绝缘层和第 三栅绝缘层。所述层间绝缘层设置于所述第一源漏导电层和所述第三栅导电层之间，所述第二栅绝缘层设置于所述第一栅导电层和所述第二栅导电层之间，所述第三栅绝缘层设置于所述第二栅导电层和所述第三栅导电层之间。所述第三栅绝缘层的厚度大于所述层间绝缘层的厚度，以及大于所述第二栅绝缘层的厚度。
在一些实施例中，所述层间绝缘层的厚度为
Figure PCTCN2022095713-appb-000001
和/或，所述第二栅绝缘层的厚度为
Figure PCTCN2022095713-appb-000002
和/或，所述第三栅绝缘层的厚度为
Figure PCTCN2022095713-appb-000003
另一方面，提供一种显示装置。所述显示装置包括如上述任一实施例所述的显示面板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例中的一种显示装置的结构图；
图2为根据一些实施例中的一种显示面板的结构图；
图3为图2沿A-A＇处的剖视图；
图4为根据一些实施例中的子像素的电路图；
图5为根据一些实施例中的另一种显示面板的结构图；
图6为图5中M处的局部放大图；
图7为图6沿A-A＇处的一种剖视图；
图8为图6沿A-A＇处的另一种剖视图；
图9为图6沿A-A＇处的再一种剖视图；
图10为图6沿A-A＇处的又一种剖视图；
图11为图6沿A-A＇处的又一种剖视图；
图12为图6沿A-A＇处的电镜图；
图13为根据一些实施例中的另一种显示面板的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实 施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实 施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
在一些实施例中，各晶体管的控制极为晶体管的栅极，第一极为晶体管的源极和漏极中一者，第二极为晶体管的源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性的，在晶体管为P型晶体管的情况下，晶体管的第一极为源极，第二极为漏极；示例性的，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
在本文中，“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。
如图1所示，本公开的一些实施例提供一种显示装置1000，该显示装置1000可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。示例性地，该显示装置1000可以为电视机、笔记本电脑、平板电脑、手机、个人数字助理(Personal Digital Assistant；简称：PDA)、导航仪、可穿戴设备、虚拟现实(Virtual Reality；简称：VR)设备等任何具有显示功能的产品或者部件。
在一些实施例中，如图1所示。显示装置1000包括显示面板100。
示例性地，上述显示装置1000还可以包括壳体200、功能器件300、电路板以及其他电子配件。其中，显示面板100、功能器件300和电路板可以设置在该壳体100内。
此外，电路板可以在显示面板100的端部与显示面板100绑定，并弯折至显示面板100的背侧，以缩减显示面板100的外边框，提高屏占比。功能器件300可以集成于显示面板100的非显示侧的正下方，以缩减显示面板100的外边框，提高屏占比。
需要说明的是，该功能器件300可以为摄像头、红外传感器、近距离传 感器、眼球追踪模组和人脸识别模组等等。示例性地，如图1所示，该功能器件300为摄像头。
其中，参阅图1、图2和图3，显示面板100可以设有安装孔H，功能器件300可以安装在安装孔H处，以避免显示面板100阻挡功能器件300的采光。
上述显示面板100的类型包括多种，可以根据实际需要选择设置。示例性地，上述显示面板100可以为：有机发光二极管(Organic Light Emitting Diode，简称：OLED)显示面板、量子点发光二极管(Quantum Dot Light Emitting Diode，简称：QLED)显示面板、微发光二极管(Micro Light Emitting Diodes，简称：Micro LED)显示面板等，本公开实施例对此不做具体限定。
下面以上述显示面板100为OLED显示面板为例，对本公开的一些实施例进行示意性说明。
在一些实施例中，如图2所示，上述显示面板100具有显示区A，以及设置在显示区A的至少一侧的周边区B。图2中以周边区B围绕显示区A设置为例。
其中，显示区A为显示图像的区域，被配置为设置多个子像素P。周边区B为不显示图像的区域，周边区B被配置为设置显示驱动电路，例如，扫描驱动电路110和源极驱动电路120。
需要说明的是，扫描驱动电路110可以包括发光控制电路和栅极驱动电路，以下以扫描驱动电路110包括发光控制电路和栅极驱动电路为例，对本公开的一些实施例进行示意性说明。
此外，如图1、图2和图3所示，在功能器件300集成于显示面板100的下方的情况下，显示区A还具有功能器件设置区A1和至少部分环绕功能器件设置区A1的主显示区A2，安装孔H设置于功能器件设置区A1，且功能器件设置区A1还包括围绕安装孔H的边框区A10。图1和图2中以主显示区A2环绕功能器件设置区A1为例进行示意。
在一些实施例中，如图3所示，由主显示区A2指向安装孔H，边框区A10依次包括冗余区A11、走线区A12和封装区A13。冗余区A11被配置为，为走线区A12与主显示区A2提供工艺间隙，走线区A12被配置为，设置电路走线，封装区A13被配置为，设置封装层，以阻隔水和氧气的侵蚀。
示例性地，封装区A13设有内隔离柱30、阻挡部40和外隔柱50。
以下以显示区A包括功能器件设置区A1和至少部分环绕功能器件设置区A1的主显示区A2为例，对本公开的一些实施例进行示意性说明。
在一些实施例中，如图2和图3所示，上述显示面板100可以包括衬底10和扫描驱动电路110。该衬底10用于承载扫描驱动电路110。
上述衬底10的类型包括多种，可以根据实际需要选择设置。
示例性地，衬底10可以为刚性衬底。例如，该刚性衬底可以为玻璃衬底或PMMA(Polymethyl Methacrylate，聚甲基丙烯酸甲酯)衬底等。
示例性地，衬底10可以为柔性衬底。例如，该柔性衬底可以为聚对苯二甲酸乙二醇酯(Polyethylene Terephthalate，简称：PET)衬底、聚萘二甲酸乙二醇酯(Polyethylene Naphthalate Two Formic Acid Glycol Ester，简称：PEN)衬底或聚酰亚胺(Polyimide，简称：PI)衬底等。
在一些实施例中，如图2和图3所示，上述显示面板100还可以包括多个子像素P，多个子像素P与扫描驱动电路110设置于衬底10的同一侧，且位于主显示区A2。
其中，多个子像素P可以排列为多行多列，每行包括沿第一方向X排列的多个子像素P，每列包括沿第二方向Y排列的多个子像素P，第一方向X和第二方向Y大致垂直。
需要说明的是，参阅图4，每个子像素P可以包括像素电路130及与该像素电路130电连接的发光器件140，该发光器件140可以为OLED。
在一些实施例中，如图2所示，上述显示面板100还可以包括多条使能信号线EL、多条扫描信号线GL、多条复位信号线RL以及多条数据线DL。图2中仅示例出部分使能信号线EL、扫描信号线GL、复位信号线RL以及多条数据线DL。
其中，多条使能信号线EL、多条扫描信号线GL和多条复位信号线RL大致沿第一方向X延伸，多条数据线DL大致沿第二方向Y延伸。
在本文中，“大致沿第一方向X延伸”是指，信号线(使能信号线EL、多条扫描信号线GL、多条复位信号线RL)整体上的走线方向沿第一方向X，但是并不局限为信号线的每一位置均严格的沿第一方向X延伸。即，这里的“大致沿第一方向X延伸”不但包括每一个位置均严格沿第一方向X延伸的信号线，而且考虑到其他结构的干扰，还包括局部线段进行弯曲避让的信号线。例如，部分信号线在安装孔H的周侧弯曲，并在边框区A10上绕过安装孔H，本文的后面会结合像素电路的结构以及具体的膜层结构进行详细描述。
在本文中，“大致沿第二方向Y延伸”是指，数据线DL整体上的走线方向沿第二方向Y，但是并不局限为数据线DL的每一位置均严格的沿第二方 向Y延伸。即，这里的“大致沿第二方向Y延伸”不但包括每一个位置均严格沿第二方向Y延伸的数据线DL，而且考虑到其他结构的干扰，还包括局部线段进行弯曲避让的数据线DL。例如，部分数据线DL在安装孔H的周侧弯曲，并在边框区A10上绕过安装孔H，本文的后面会结合像素电路的结构以及具体的膜层结构进行详细描述。
在此基础上，同一行子像素P的像素电路130可以与大致沿第一方向X延伸的一组信号线(使能信号线EL、多条扫描信号线GL、多条复位信号线RL)电连接，同一列子像素P的像素电路130可以与一条数据线DL电连接。
需要说明的是，上述大致沿第一方向X延伸的一组信号线，包括至少一条使能信号线EL、至少一条扫描信号线GL和至少一条复位信号线RL。该上述大致沿第一方向X延伸的一组信号线所包括的信号的数量，取决于像素电路130的结构，本文的后面会结合像素电路130的结构进行描述。
在一些实施例中，参阅图4，像素电路130采用低温多晶氧化物(即Low Temperature Polycrystalline Oxide，简称LTPO)技术，即一个像素电路130同时包括低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)薄膜晶体管和氧化物(Oxide)薄膜晶体管，这样可以以低生产成本实现高的电荷迁移率、稳定性和可扩展性。
在此情况下，该像素电路130同时具有两种有源层，其中，LTPS薄膜晶体管的有源层图案的材料为低温多晶硅，氧化物薄膜晶体管的有源层图案的材料为氧化物。
以下以像素电路130为LTPO像素电路为例，对本公开的一些实施例进行示意性说明。
应理解，像素电路130的结构包括多种，可以根据实际需要选择设置。例如，像素电路130的结构可以包括“2T1C”、“3T1C”、“6T1C”、“7T1C”、“8T1C”、“6T2C”或“7T2C”等结构。其中，“T”表示为晶体管，位于“T”前面的数字表示为晶体管的数量，“C”表示为存储电容器，位于“C”前面的数字表示为存储电容器的数量。
此外，在显示面板100使用的过程中，像素电路130中的晶体管及发光器件140的稳定性可能会下降(例如驱动晶体管的阈值电压漂移)，影响显示面板100的显示效果，这样便需要对子像素P进行补偿。
对子像素P进行补偿的方式可以包括多种，可以根据实际需要选择设置。例如，可以在子像素P中设置像素补偿电路，以利用该像素补偿电路对子像素P进行内部补偿。又如，可以通过子像素P内部的晶体管对驱动晶体 管或发光器件进行感测，并将感测到的数据传输到外部感应电路，以利用该外部感应电路计算需要补偿的驱动电压值并进行反馈，从而实现对子像素P的外部补偿。
本公开以采用内部补偿的方式，且像素电路130采用“8T1C”的结构为例，对子像素P的结构及工作过程进行示意性说明。并且，在下面的描述中，像素电路130为位于第N行子像素P中的像素电路130中的任一个；其中，N为正整数。
示例性地，如图4所示，像素电路130包括8个晶体管T与1个存储电容器Cst。
其中，第一晶体管T1为用于为第一节点复位的复位晶体管，第二晶体管T2为二极管连接晶体管，第三晶体管T3为驱动晶体管，第四晶体管T4为数据写入晶体管，第五晶体管T5和第六晶体管T6为发光控制晶体管，第七晶体管T7为用于为发光器件的阳极(第四节点N4)复位的复位晶体管,第八晶体管用于为第二节点和第三节点复位的复位晶体管。
需要说明的是，第三晶体管T3可以为双栅结构，以提高第三晶体管T3稳定性。
在一些实施例中，如图4所示，T3、T4、T5、T6、T7和T8是P型LTPS晶体管，使得这些晶体管具有更高的迁移率和更稳定的源极电压，适合驱动发光器件140；T1和T2是N型Oxide晶体管，使得第一晶体管T1和第二晶体管T2具有更低的漏电流，可以更好地保持第三晶体管T3和存储电容器Cst的电压稳定。
需要说明的是，如图4所示的电路中，节点N1、N2、N3和N4并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点，也就是说，这些节点是由电路图中相关电连接的汇合点等效而成的节点。
基于上述像素电路130的结构，参阅图5，一组信号线，可以包括一条使能信号线EL、两条扫描信号线GL和两条复位信号线RL。
如图4和图5所示，使能信号线EL与像素电路130的使能信号端EM电连接，且被配置为传输使能信号Em。
如图4和图5所示，两条扫描信号线GL可以包括第一扫描信号线GL1和第二扫描信号线GL2。第一扫描信号线GL1与像素电路130的第一扫描信号端GATE1电连接，且被配为传输第一扫描信号Gate1。第二扫描信号线GL2与像素电路130的第二扫描信号端GATE2电连接，且被配为传输第二扫描信号Gate2。
如图4和图5所示，两条复位信号线RL可以包括第一复位信号线RL1和第二复位信号线RL2。第一复位信号线RL1与像素电路130的第一复位信号端RESET1电连接，且被配置为传输第一复位信号Reset1。第二复位信号线RL2与像素电路130的第二复位信号端RESET2电连接，且被配为传输第二复位信号Reset2。
需要说明的是，像素电路130的第三扫描信号端GATE3，可以与像素电路130的第二复位信号端RESET2连接同一条信号线，例如，像素电路130的第二复位信号端RESET2和第三扫描信号端GATE3均与第二复位信号线RL2电连接。
但是，相关技术中，在采用8T1C的LTPO像素电路的显示面板中，在边框区，使能信号线、扫描信号线和复位信号线分布在两层，且分布在两层的信号线在衬底上的正投影错开设置，导致使能信号线、扫描信号线和复位信号线在衬底上的正投影总体所占用的面积较大，即边框区的尺寸较大。这样的话，在显示过程中，安装孔的边缘的显示黑边较大，导致显示面板的屏占比下降，且影响显示画面的完整性。
基于此，如图2、图3和图6所示，本公开的一些实施例提供一种显示面板100，多条使能信号线EL中，至少一条使能信号线EL包括位于主显示区A2的第一子使能信号线EL11和位于边框区A10的第二子使能信号线EL12。多条扫描信号线GL中，至少一条扫描信号线GL包括位于主显示区A2的第一子扫描信号线GL11和位于边框区A10的第二子扫描信号线GL12。多条复位信号线RL中，至少一条复位信号线RL包括位于主显示区A2的第一子复位信号线RL11和位于边框区A10的第二子复位信号线RL12。
其中，参阅图6和图7，多条使能信号线EL的第二子使能信号线EL12、多条扫描信号线GL的第二子扫描信号线GL12和多条复位信号线RL的第二子复位信号线RL12中，至少存在三条信号线(第二子使能信号线EL12、第二子扫描信号线GL12和第二子复位信号线RL12中的至少一者)位于不同的三层。
可以理解的是，位于同层的信号线在形成的过程中，为了避免相邻的走线之间产短路的问题，位于同层的信号线之间需要留有工艺间隙。位于不同层的信号线在形成的过程中，无需考虑该工艺间隙，即位于不同层的信号线在衬底10上的正投影的可以部分重合或完全重合，或位于不同层的信号线在衬底10上的正投影的边界之间的距离可以小于上述工艺间隙的距离，从 而缩减位于不同层的信号线总体所需要占用的面积。
基于此，第二子使能信号线EL12、第二子扫描信号线GL12和第二子复位信号线RL12中，位于不同的三层的信号线总体所占用的面积可以进行缩减，从而使得所有的第二子使能信号线EL12、第二子扫描信号线GL12和第二子复位信号线RL12总体所需要占用的面积缩减。也就是说，边框区A10的面积可以缩减，从而减小显示过程中安装孔H的边缘的显示黑边，提高显示面板100的屏占比。
示例性地，如图7、图8和图9所示，多条使能信号线EL的第二子使能信号线EL12、多条扫描信号线GL的第二子扫描信号线GL12和多条复位信号线RL的第二子复位信号线RL12中，位于不同的三层的信号线在衬底10上的正投影至少部分交叠，以使得位于不同层的信号线总体所占用的面积缩减，进而使得所有的第二子使能信号线EL12、第二子扫描信号线GL12和第二子复位信号线RL12总体所需要占用的面积缩减，从而减小边框区A10(参见图6)的面积，减小显示过程中安装孔H的边缘的显示黑边，提高显示面板100的屏占比。
这里，位于不同的三层的信号线在衬底10上的正投影至少部分交叠，本文的后面会结合具体的信号线以及具体的膜层结构进行示例性的描述。
在采用上述8T1C的LTPO像素电路的显示面板100中，沿垂直于衬底10且远离衬底10的方向，如图7所示，显示面板100可以依次包括第一栅导电层12、第二栅导电层14和第三栅导电层16。
需要说明的是，如图7所示，显示面板100还可以包括第一栅绝缘层11、第二栅绝缘层13和第三栅绝缘层15。第一栅绝缘层11设置于衬底10与第一栅导电层12之间，第二栅绝缘层13设置于第一栅导电层12与第二栅导电层14之间，第三栅绝缘层15设置于第二栅导电层14和第三栅导电层16之间。
这里，使能信号线EL、扫描信号线GL和复位信号线RL可以设置于第一栅导电层12、第二栅导电层14和第三栅导电层16中的至少一者。
如上所述，与8T1C的LTPO像素电路电连接的信号线，可以包括使能信号线EL、第一扫描信号线GL1、第二扫描信号线GL2、第一复位信号线RL1和第二复位信号线RL2。
此时，参阅图6，在主显示区A2，使能信号线EL的第一子使能信号线EL11、第一复位信号线RL1的第一子复位信号线RL11和第二扫描信号线GL2的第一子扫描信号线GL11均可以设置于第一栅导电层12(参见图7) 和/或第二栅导电层14(参见图7)。
参阅图6，在主显示区A2，第一扫描信号线GL1的第一子扫描信号线GL11可以部分走线设置于第二栅导电层14(参见图7)，部分走线设置于第三栅导电层16(参见图7)。第二复位信号线RL2的第一子复位信号线RL11可以部分走线设置于第二栅导电层14(参见图7)，部分走线设置于第三栅导电层16(参见图7)。
其中，参阅图4和图6，在8T1C的LTPO像素电路中，第二晶体管T2的沟道区上方的第一子扫描信号线GL11设置于第三栅导电层16(参见图7)，第七晶体管T7的沟道区上方的第一子复位信号线RL11设置于第三栅导电层16(参见图7)。
此时，多条使能信号线EL的第二子使能信号线EL12、多条扫描信号线GL的第二子扫描信号线GL12和多条复位信号线RL的第二子复位信号线RL12中，至少存在三条信号线可以分别位于第一栅导电层12、第二栅导电层14和第三栅导电层16。
如上所述，与8T1C的LTPO像素电路电连接的信号线，可以包括使能信号线EL、第一扫描信号线GL1、第二扫描信号线GL2、第一复位信号线RL1和第二复位信号线RL2。
应理解，为了提高同一行的像素电路130中各个像素电路130所接收的信号的准确性，减小信号线的长度所带来的压降的影响，传输该信号的信号线可以采用双侧驱动的方式输入；为了节约成本，简化周边区B的扫描驱动电路110以及缩减周边区B的尺寸，传输该信号的信号线可以采用单侧驱动的方式输入。
需要说明的是，单侧驱动是指，显示面板100可以在周边区B中沿信号线的延伸方向上的单侧设置扫描驱动电路110，从单侧逐行依次驱动各信号线。双侧驱动是指，显示面板100可以在周边区B中沿信号线的延伸方向上的两个侧边分别设置扫描驱动电路110，通过两个扫描驱动电路110同时从两侧逐行依次驱动各信号线。
在一些实施例中，参阅图5和图6，第二扫描信号线GL2采用双侧驱动的方式，使能信号线EL、第一扫描信号线GL1、第一复位信号线RL1和第二复位信号线RL2均采用单侧驱动的方式，以在保证数据信号Data写入的精度的情况下，缩减周边区B的尺寸以及减小成本。
此时，参阅图2和图5，周边区B至少位于主显示区A2的第一侧和第二侧，主显示区A2的第一侧和第二侧的周边区B均设置有扫描驱动电路 110。其中，第一侧和第二侧为主显示区A2沿信号线的延伸方向上的相对的两侧。
示例性地，如图2和图5所示，扫描驱动电路110包括第一扫描驱动电路111和第二扫描驱动电路112。第一扫描驱动电路111设置于周边区B，且位于主显示区A2的第一侧；第一扫描驱动电路111与第一扫描信号线GL1、第二扫描信号线GL2、使能信号线EL、复位信号线RL电连接。第二扫描驱动电路112设置于周边区B，且位于主显示区A2的第二侧；第二扫描驱动电路112与第二扫描信号线GL2电连接。
以下以第二扫描信号线GL2采用双侧驱动的方式，使能信号线EL、第一扫描信号线GL1、第一复位信号线RL1和第二复位信号线RL2均采用单侧驱动的方式为例，对本公开的一些实施例进行示意性说明。
此时，参阅图5和图6，多条使能信号线EM中，延伸方向(第一方向X)经过安装孔H的使能信号线EL包括第一子使能信号线EL11和第二子使能信号线EL112。多条第一扫描信号线GL1中，延伸方向经过安装孔H的第一扫描信号线GL1包括第一子扫描信号线GL11和第二子扫描信号线GL12。延伸方向经过安装孔H的第一复位信号线RL1和第二复位信号线RL2，均包括第一子复位信号线RL1和第二子复位信号线RL2。
这里，由于第二扫描信号线GL2采用双侧驱动的方式，因此，第二扫描信号线GL2在安装孔H处可以断开，以避让安装孔H。以这种方式设置，第二扫描信号线GL2无需经过边框区A10，即边框区A10上无需设置第二扫描信号线GL2，边框区A10的面积可以进一步地缩减。
例如，如图5所示，多条第二扫描信号线GL2包括第一类扫描信号线GL21、第二类扫描信号线GL22和第三类扫描信号线GL23，安装孔H位于第二类扫描信号线GL22和第三类扫描信号线GL23的延伸方向上。
其中，第一类扫描信号线GL21由位于主显示区A2的第一侧的周边区B，沿第一方向X延伸至位于主显示区A2的第二侧的周边区B。第二类扫描信号线GL22由位于主显示区A2的第一侧的周边区B，沿第一方向X延伸至边框区A10。第三类扫描信号线GL23由位于主显示区A2的第二侧的周边区B，沿第一方向X延伸至边框区A10。
此时，第一扫描驱动电路111与第一扫描信号线GL1、第一类扫描信号线GL21、第二类扫描信号线GL22、使能信号线EL、复位信号线RL电连接，第二扫描驱动电路112与第一类扫描信号线GL21、第三类扫描信号线GL23电连接。
应理解，多条使能信号线EL的第二子使能信号线EL12、多条扫描信号线GL的第二子扫描信号线GL12和多条复位信号线RL的第二子复位信号线RL12在第一栅导电层12、第二栅导电层14和第三栅导电层16的分布情况并不唯一。
示例性地，参阅图6、图7、图8和图9，多条使能信号线EL中的第二子使能信号线EL12位于第二栅导电层14。至少两条复位信号线RL包括位于主显示区A1的第一子复位信号线RL11和位于边框区A10的第二子复位信号线RL12，至少两条复位信号线RL中，一些第二子复位信号线RL12位于第一栅导电层12，另一些第二子复位信号线RL12位于第三栅导电层16。多条扫描信号线GL中的第二子扫描信号线GL12位于第二栅导电层14。
例如，如图6、图7、图8和图9所示，多条使能信号线EM中的第二子使能信号线EM12位于第二栅导电层14。至少两条复位信号线RL包括上述第一复位信号线RL1和上述第二复位信号线RL2。至少一条第一复位信号线RL1包括第一子复位信号线RL11和第二子复位信号线RL12，且第一复位信号线RL1的第二子复位信号线RL11位于第一栅导电层12。至少一条第二复位信号线RL1包括第一子复位信号线RL11和第二子复位信号线RL12，且第二复位信号线RL2的第二子复位信号线RL12位于第三栅导电层16。多条扫描信号线GL包括上述第一扫描信号线GL1和上述第二扫描信号线GL2，至少一条第一扫描信号线GL1包括第一子扫描信号线GL11和第二子扫描信号线GL12，且第一扫描信号线GL1的第二子扫描信号线GL12位于第二栅导电层14。由上述可知，第二扫描信号线GL2可以不设置在边框区A10。
由上述可知，第一复位信号线RL1的第二子复位信号线RL11位于第一栅导电层12，使能信号线EM中的第二子使能信号线EM12、以及第一扫描信号线GL1的第二子扫描信号线GL12位于第二栅导电层14，第二复位信号线RL2的第二子复位信号线RL12位于第三栅导电层16。
在此基础上，如图8所示，位于第三栅导电层16的第二子复位信号线RL12在衬底10上的正投影，可以与位于第二栅导电层14的第二子使能信号线RL12和/或第二子扫描信号线GL12在衬底10上的正投影至少部分交叠，以缩减位于第三栅导电层16的第二子复位信号线RL12，与位于第二栅导电层14的第二子使能信号线RL12和/或第二子扫描信号线GL12总体所占用的面积，进而使得所有的第二子使能信号线EL12、第二子扫描信号线GL12和第二子复位信号线RL12总体所需要占用的面积缩减，从而减小边 框区A10的面积。
或者，如图7所示，位于第三栅导电层16的第二子复位信号线RL12在衬底10上的正投影，可以与位于第一栅导电层12的第二子复位信号线RL12在衬底10上的正投影至少部分交叠，以缩减位于第三栅导电层16的第二子复位信号线RL12，与位于第一栅导电层12的第二子复位信号线RL12总体所占用的面积，进而使得所有的第二子使能信号线EL12、第二子扫描信号线GL12和第二子复位信号线RL12总体所需要占用的面积缩减，从而减小边框区A10的面积。
或者，如图9所示，位于第三栅导电层16的第二子复位信号线RL12在衬底10上的正投影，与位于第二栅导电层14的第二子使能信号线RL12和/或第二子扫描信号线GL12在衬底10上的正投影至少部分交叠，以及与位于第一栅导电层12的第二子复位信号线RL12在衬底10上的正投影至少部分交叠，以缩减位于第三栅导电层16的第二子复位信号线RL12，与位于第二栅导电层14的第二子使能信号线RL12和/或第二子扫描信号线GL12，以及位于第一栅导电层12的第二子复位信号线RL12总体所占用的面积，进而使得所有的第二子使能信号线EL12、第二子扫描信号线GL12和第二子复位信号线RL12总体所需要占用的面积缩减，从而减小边框区A10的面积。
在一些实施例中，参阅图2、图5和图13，上述扫描驱动电路110可以包括多个移位寄存器，一个移位寄存器可以与至少一行子像素P中的多个像素电路130电连接。
示例性地，如图2、图5和图13所示，扫描驱动电路110包括上述第一扫描驱动电路111和上述第二扫描驱动电路112，第一扫描驱动电路111包括级联的多个第一移位寄存器RS1，每个第一移位寄存器RS1与至少两条第一扫描信号线GL1、至少两条使能信号线EL、至少两条第一复位信号线RL1和至少两条第二复位信号线RL2电连接，每个第一移位寄存器111还与至少两条第一类扫描信号线GL21或至少两条第二类扫描信号线GL22电连接。第二扫描驱动电路112包括级联的多个第二移位寄存器RS2，每个第二移位寄存器RS2与至少两条第一类扫描信号线GL21或至少两条第三类扫描信号线GL23电连接。图13中仅以第一移位寄存器与两条第二复位信号线电连接为例进行示意。
在此基础上，参阅图5和图13，与同一个第一移位寄存器RS1连接的至少两条第一扫描信号线GL1中，一条第一扫描信号线GL1包括第一子扫 描信号线GL11和第二子扫描信号线GL12，其余的每条第一扫描信号线GL1包括两条扫描走线段，且一条扫描走线段与第一移位寄存器RS1和第二子扫描信号线GL12的一端连接，另一条扫描走线段与第二子扫描信号线GL12的另一端电连接，且延伸至主显示区A2的第二侧的边界，以减少边框区A10上设置的第二子扫描信号线GL12的数量，进而使得所有的第二子使能信号线EL12、第二子扫描信号线GL12和第二子复位信号线RL12总体所需要占用的面积进一步地缩减，从而进一步地减小边框区A10的面积。图13中仅以第二复位信号线为例进行示意。
参阅图5和图13，与同一个第一移位寄存器RS1连接的至少两条使能信号线EL中，一条使能信号线EL包括第一子使能信号线EL11和第二子使能信号线EL12，其余的每条使能信号线EL包括两条使能走线段，且一条使能走线段与第一移位寄存器RS1和第二子使能信号线EL12的一端连接，另一条使能走线段与第二子使能信号线EL12的另一端电连接，且延伸至主显示区A2的第二侧的边界，以减少边框区A10上设置的第二子使能信号线EL12的数量，进而使得所有的第二子使能信号线EL12、第二子扫描信号线GL12和第二子复位信号线RL12总体所需要占用的面积进一步地缩减，从而进一步地减小边框区A10的面积。图13中仅以第二复位信号线为例进行示意。
参阅图5和图13，与同一个第一移位寄存器RS1连接的至少两条第一复位信号线RL1中，一条第一复位信号线RL1包括第一子复位信号线RL11和第二子复位信号线RL12，其余的每条第一复位信号线RL1包括两条第一复位走线段，且一条第一复位走线段与第一移位寄存器RS1和第二子复位信号线RL12的一端连接，另一条第一复位走线段与第二子复位信号线RL12的另一端电连接，且延伸至主显示区A2的第二侧的边界，以减少边框区A10上设置的第二子复位信号线RL12的数量，进而使得所有的第二子使能信号线EL12、第二子扫描信号线GL12和第二子复位信号线RL12总体所需要占用的面积进一步地缩减，从而进一步地减小边框区A10的面积。图13中仅以第二复位信号线为例进行示意。
参阅图5和图13，与同一个第一移位寄存器RS1连接的至少两条第二复位信号线RL2中，一条第二复位信号线RL2包括第一子复位信号线RL11和第二子复位信号线RL12，其余的每条第二复位信号线包括两条第二复位走线段，且一条第二复位走线段与第一移位寄存器RS1和第二子复位信号线RL12的一端连接，另一条第二复位走线段与第二子复位信号线RL12的 另一端电连接，且延伸至主显示区A2的第二侧的边界，以减少边框区A10上设置的第二子复位信号线RL12的数量，进而使得所有的第二子使能信号线EL12、第二子扫描信号线GL12和第二子复位信号线RL12总体所需要占用的面积进一步地缩减，从而进一步地减小边框区A10的面积。图13中仅以第二复位信号线为例进行示意。
在一些实施例中，如图6、图7、图8和图9所示，显示面板100还包括第一源漏导电层18和第二源漏导电层20，第一源漏导电层18设置于第三栅导电层16远离衬底10的一侧，第二源漏导电层20设置于第一源漏导电层18远离衬底10的一侧。
需要说明的是，显示面板100还可以包括层间绝缘层17、第一平坦层19和第二平平坦层21。层间绝缘层17设置于第三栅导电层16与第一源漏导电层18之间，第一平坦层19设置于第一源漏导电层18与第二源漏导电层20之间，第二平坦层21设置于第二源漏导电层20远离衬底10的一侧。
在此基础上，参阅图6、图7、图8和图9，至少两条数据线DL包括位于主显示区A2的第一子数据线DL11和位于边框区A10的第二子数据线DL12。其中，位于边框区A10的至少两条第二子数据线DL12中，一些第二子数据线DL12位于第一源漏导电层18，另一些第二子数据线DL12位于第二源漏导电层20。
以这种方式这种，位于不同层的数据线DL总体所占用的面积可以进行缩减，从而使得所有的数据线DL总体所需要占用的面积缩减。也就是说，边框区A10的面积可以进一步地缩减，从而减小显示过程中安装孔H的边缘的显示黑边，提高显示面板100的屏占比。
在一些实施例中，参阅图7、图8和图9，上述第三栅绝缘层15的厚度大于层间绝缘层17的厚度。
示例性地，层间绝缘层17的厚度为
Figure PCTCN2022095713-appb-000004
第三栅绝缘层15的厚度为
Figure PCTCN2022095713-appb-000005
需要说明的是，层间绝缘层17的材料包括无机绝缘材料，例如，层间绝缘层17的材料包括氮化硅和/或氧化硅。第三栅绝缘层15的材料包括无机绝缘材料，例如，第三栅绝缘层15的材料包括氮化硅和/或氧化硅层。
此时，如图11所示，位于第三栅导电层16的信号线的相对的两个侧面为第一斜面，且同一个信号线的两个第一斜面远离衬底10的边界之间的距离，小于两个第一斜面靠近衬底10的边界之间的距离，这样可以减小层间绝缘层17在位于第三栅导电层16的信号线的边界爬坡的倾斜度，降低层间 绝缘层17在位于第三栅导电层16的信号线的边界爬坡处断裂(图12中C处)的风险，进而降低位于第三栅导电层16的信号线，与位于第一源漏导电层18的第二子数据线DL12产生短接的风险。
需要说明的是，第一斜面与衬底10远离第一栅导电层12的表面所在的平面的夹角的小于或等于30°。
此外，如图7、图8和图9所示，位于第一源漏导电层18的第二子数据线DL12在衬底10上的正投影，与位于第三栅导电层16的信号线在衬底10上的正投影错开设置，以避免层间绝缘层17断裂(图12中C处)导致位于第一源漏导电层18的第二子数据线DL12，与位于第三栅导电层16的信号线之间产生短接的问题。
如图10所示，位于第一源漏导电层18的第二子数据线DL12在衬底10上的正投影的边界，在位于第三栅导电层16的信号线在衬底10上的正投影的边界内，以避免层间绝缘层17在位于第三栅导电层16的信号线的边界爬坡处断裂(图12中C处)，而导致位于第一源漏导电层18的第二子数据线DL12，与位于第三栅导电层16的信号线之间产生短接的问题。
需要说明的是，在位于第三栅导电层16的信号线的相对的两个侧面为第一斜面的情况下，位于第一源漏导电层18的第二子数据线DL12在衬底10上的正投影的边界，在位于第三栅导电层16的信号线远离衬底10的表面在衬底10上的正投影的边界内。
在一些实施例中，如图7、图8和图9所示，上述第三栅绝缘层15的厚度大于第二栅绝缘层13的厚度。
示例性地，第二栅绝缘层13的厚度为
Figure PCTCN2022095713-appb-000006
和/或，第三栅绝缘层15的厚度为
Figure PCTCN2022095713-appb-000007
此时，如图11所示，位于第一栅导电层12的信号线的相对的两侧面为第二斜面，且同一个信号线的两个第二斜面远离衬底10的边界之间的距离，小于两个第二斜面靠近衬底10的边界之间的距离，这样可以减小第二栅绝缘层13在位于第一栅导电层12的信号线的边界爬坡的倾斜度，降低第二栅绝缘层13在位于第一栅导电层12的信号线的边界爬坡处断裂的风险，进而降低位于第一栅导电层12的信号线，与位于第二栅导电层14的信号线产生短接的风险。
需要说明的是，第二斜面与衬底10远离第一栅导电层12的表面所在的平面的夹角的小于或等于30°。
此外，如图7、图8和图9所示，位于第一栅导电层12的信号线在衬 底10上的正投影，与位于第二栅导电层14的信号线在衬底10上的正投影错开设置，以避免第二栅绝缘层13断裂导致位于第一栅导电层12的信号线，与位于第二栅导电层14的信号线之间产生短接的问题。
参阅图7、图8和图9，位于第二栅导电层14的信号线在衬底10上的正投影的边界，在位于第一栅导电层12的信号线在衬底10上的正投影的边界内，以避免第二栅绝缘层13在位于第一栅导电层12的信号线的边界爬坡处断裂，而导致位于第一栅导电层12的信号线，与位于第二栅导电层14的信号线之间产生短接的问题。
需要说明的是，在位于第一栅导电层12的信号线的相对的两侧面为第二斜面的情况下，位于第二栅导电层14的信号线在衬底10上的正投影的边界，在位于第一栅导电层12的信号线远离衬底10的表面在衬底10上的正投影的边界内。
为了对本公开的实施例的技术效果进行客观评价，以下，将上述实施例提供的显示面板与相关技术中的显示面板的边框区进行对比，对比结果见表1。
表1尺寸对比表
实施例 安装孔直径/μm 边框区/μm 封装区/μm 走线区/μm
相关技术1 2740 753.8 278 476.1
相关技术2 2740 497.6 278 219.6
本公开 2740 497.6 39 219.6
其中，相关技术1代表采用8T1C的LTPO像素电路的显示面板的实施例，相关技术2代表采用7T1C的LTPS像素电路的显示面板的实施例。
由表1可知，在安装孔H的尺寸为2740μm情况下，本公开的实施例在采用8T1C的LTPO像素电路的显示面板时，可以将边框区整体的尺寸缩减256.2μm，实现与采用7T1C的LTPS像素电路的显示面板的边框区整体的的尺寸大致相等。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (21)

  1. 一种显示面板，具有功能器件设置区，及至少部分围绕所述功能器件设置区的主显示区；所述功能器件设置区中设置有安装孔，所述功能器件设置区包括围绕所述安装孔的边框区；
    所述显示面板包括：
    衬底；
    多个像素电路，设置于所述衬底上，且位于所述主显示区；
    多条使能信号线，与所述像素电路电连接；至少一条使能信号线包括位于所述主显示区的第一子使能信号线和位于所述边框区的第二子使能信号线；
    多条扫描信号线，与所述像素电路电连接；至少一条扫描信号线包括位于所述主显示区的第一子扫描信号线和位于所述边框区的第二子扫描信号线；
    多条复位信号线，与所述像素电路电连接；至少一条复位信号线包括位于所述主显示区的第一子复位信号线和位于所述边框区的第二子复位信号线；
    其中，所述多条使能信号线的第二子使能信号线、所述多条扫描信号线的第二子扫描信号线和所述多条复位信号线的第二子复位信号线中，至少存在三条信号线位于不同的三层。
  2. 根据权利要求1所述的显示面板，其中，所述多条使能信号线的第二子使能信号线、所述多条扫描信号线的第二子扫描信号线和所述多条复位信号线的第二子复位信号线中，位于不同的三层的信号线在所述衬底上的正投影至少部分交叠。
  3. 根据权利要求1或2所述的显示面板，其中，沿垂直于所述衬底且远离所述衬底的方向，所述显示面板依次包括第一栅导电层、第二栅导电层和第三栅导电层，所述多条使能信号线的第二子使能信号线、所述多条扫描信号线的第二子扫描信号线和所述多条复位信号线的第二子复位信号线中，至少存在三条信号线分别位于所述第一栅导电层、所述第二栅导电层和所述第三栅导电层。
  4. 根据权利要求3所述的显示面板，其中，所述多条使能信号线中的第二子使能信号线位于所述第二栅导电层；
    至少两条复位信号线包括位于所述主显示区的第一子复位信号线和位于所述边框区的第二子复位信号线；所述至少两条复位信号线中，一些所述第二子复位信号线位于所述第一栅导电层，另一些所述第二子复位信号线位于 所述第三栅导电层；
    所述多条扫描信号线中的第二子扫描信号线位于所述第二栅导电层。
  5. 根据权利要求4所述的显示面板，其中，位于所述第三栅导电层的第二子复位信号线在所述衬底上的正投影，与位于所述第二栅导电层的第二子使能信号线和/或第二子扫描信号线在所述衬底上的正投影至少部分交叠；
    和/或，位于所述第三栅导电层的第二子复位信号线在所述衬底上的正投影，与位于所述第一栅导电层的第二子复位信号线在所述衬底上的正投影至少部分交叠。
  6. 根据权利要求4或5所述的显示面板，其中，所述至少两条复位信号线包括：
    第一复位信号线，被配置为传输第一复位信号；至少一条第一复位信号线包括所述第一子复位信号线和所述第二子复位信号线，且所述第一复位信号线的第二子复位信号线位于所述第一栅导电层；
    第二复位信号线，被配置为传输第二复位信号；至少一条第二复位信号线包括所述第一子复位信号线和所述第二子复位信号线，且所述第二复位信号线的第二子复位信号线位于所述第三栅导电层。
  7. 根据权利要求4～6中任一项所述的显示面板，其中，所述多条扫描信号线包括：
    多条第一扫描信号线，被配为传输第一扫描信号；至少一条第一扫描信号线包括所述第一子扫描信号线和所述第二子扫描信号线，且所述第一扫描信号线的第二子扫描信号线位于所述第二栅导电层。
  8. 根据权利要求7所述的显示面板，具有周边区，所述周边区至少位于所述主显示区的第一侧和第二侧，所述第一侧和所述第二侧为所述主显示区相对的两侧；
    所述多条扫描信号线还包括：
    多条第二扫描信号线，被配置为传输第二扫描信号；所述多条第二扫描信号线包括第一类扫描信号线、第二类扫描信号线和第三类扫描信号线，所述安装孔位于所述第二类扫描信号线和所述第三类扫描信号线的延伸方向上；
    其中，所述第一类扫描信号线由位于所述显示区的第一侧的周边区，沿第一方向延伸至位于所述显示区的第二侧的周边区；所述第二类扫描信号线由位于所述主显示区的第一侧的周边区，沿所述第一方向延伸至所述边框区；所述第三类扫描信号线由位于所述主显示区的第二侧的周边区，沿所述第一 方向延伸至所述边框区。
  9. 根据权利要求8所述的显示面板，还包括：
    第一扫描驱动电路，设置于所述周边区，且位于所述主显示区的第一侧；所述第一扫描驱动电路与所述第一扫描信号线、所述第一类扫描信号线、所述第二类扫描信号线、所述使能信号线、所述复位信号线电连接；
    第二扫描驱动电路，设置于所述周边区，且位于所述主显示区的第二侧；所述第二扫描驱动电路与所述第一类扫描信号线、所述第三类扫描信号线电连接。
  10. 根据权利要求9所述的显示面板，其中，所述第一扫描驱动电路包括级联的多个第一移位寄存器，每个第一移位寄存器与至少两条所述第一扫描信号线、至少两条所述使能信号线、至少两条所述第一复位信号线和至少两条第二复位信号线电连接，每个第一移位寄存器还与至少两条所述第一类扫描信号线或至少两条所述第二类扫描信号线电连接；
    所述第二扫描驱动电路包括级联的多个第二移位寄存器，每个第二移位寄存器与至少两条所述第一类扫描信号线或至少两条所述第三类扫描信号线电连接。
  11. 根据权利要求10所述的显示面板，其中，与同一个第一移位寄存器连接的至少两条第一扫描信号线中，一条第一扫描信号线包括所述第一子扫描信号线和所述第二子扫描信号线，其余的每条第一扫描信号线包括两条扫描走线段，且一条扫描走线段与所述第一移位寄存器和所述第二子扫描信号线的一端连接，另一条扫描走线段与所述第二子扫描信号线的另一端电连接，且延伸至所述主显示区的第二侧的边界；
    和/或，与同一个第一移位寄存器连接的至少两条使能信号线中，一条使能信号线包括所述第一子使能信号线和所述第二子使能信号线，其余的每条使能信号线包括两条使能走线段，且一条使能走线段与所述第一移位寄存器和所述第二子使能信号线的一端连接，另一条使能走线段与所述第二子使能信号线的另一端电连接，且延伸至所述主显示区的第二侧的边界；
    和/或，与同一个第一移位寄存器连接的至少两条第一复位信号线中，一条第一复位信号线包括所述第一子复位信号线和所述第二子复位信号线，其余的每条第一复位信号线包括两条第一复位走线段，且一条第一复位走线段与所述第一移位寄存器和所述第二子复位信号线的一端连接，另一条第一复位走线段与所述第二子复位信号线的另一端电连接，且延伸至所述主显示区的第二侧的边界；
    和/或，与同一个第一移位寄存器连接的至少两条第二复位信号线中，一条第二复位信号线包括所述第一子复位信号线和所述第二子复位信号线，其余的每条第二复位信号线包括两条第二复位走线段，且一条第二复位走线段与所述第一移位寄存器和所述第二子复位信号线的一端连接，另一条第二复位走线段与所述第二子复位信号线的另一端电连接，且延伸至所述主显示区的第二侧的边界。
  12. 根据权利要求3～11中任一项所述的显示面板，还包括第一源漏导电层和第二源漏导电层，所述第一源漏导电层设置于所述第三栅导电层远离所述衬底的一侧，所述第二源漏导电层设置于所述第一源漏导电层远离所述衬底的一侧；
    所述显示面板还包括：
    多条数据线，与所述像素电路电连接；至少两条数据线包括位于所述主显示区的第一子数据线和位于所述边框区的第二子数据线；位于所述边框区的至少两条第二子数据线中，一些第二子数据线位于所述第一源漏导电层，另一些第二子数据线位于所述第二源漏导电层。
  13. 根据权利要求12所述的显示面板，其中，位于所述第一源漏导电层的第二子数据线在所述衬底上的正投影，与位于所述第三栅导电层的信号线在所述衬底上的正投影错开设置；
    和/或，位于所述第一源漏导电层的第二子数据线在所述衬底上的正投影的边界，在位于所述第三栅导电层的信号线在所述衬底上的正投影的边界内。
  14. 根据权利要求12或13所述的显示面板，其中，位于所述第三栅导电层的信号线的相对的两个侧面为第一斜面，且同一个信号线的两个第一斜面远离所述衬底的边界之间的距离，小于两个第一斜面靠近所述衬底的边界之间的距离。
  15. 根据权利要求14所述的显示面板，其中，所述第一斜面与所述衬底远离所述第一栅导电层的表面所在的平面的夹角的小于或等于30°。
  16. 根据权利要求3～15中任一项所述的显示面板，其中，位于所述第一栅导电层的信号线在所述衬底上的正投影，与位于所述第二栅导电层的信号线在所述衬底上的正投影错开设置；
    和/或，位于所述第二栅导电层的信号线在所述衬底上的正投影的边界，在位于所述第一栅导电层的信号线在所述衬底上的正投影的边界内。
  17. 根据权利要求3～16所述的显示面板，其中，位于所述第一栅导电层的信号线的相对的两侧面为第二斜面，且同一个信号线的两个第二斜面远离 所述衬底的边界之间的距离，小于两个第二斜面靠近所述衬底的边界之间的距离。
  18. 根据权利要求17所述的显示面板，其中，所述第二斜面与所述衬底远离所述第一栅导电层的表面所在的平面的夹角的小于或等于30°。
  19. 根据权利要求3～18中任一项所述的显示面板，还包括：
    层间绝缘层，设置于所述第一源漏导电层和所述第三栅导电层之间；
    第二栅绝缘层，设置于所述第一栅导电层和所述第二栅导电层之间；
    第三栅绝缘层，设置于所述第二栅导电层和所述第三栅导电层之间；所述第三栅绝缘层的厚度大于所述层间绝缘层的厚度，以及大于所述第二栅绝缘层的厚度。
  20. 根据权利要求19所述的显示面板，其中，所述层间绝缘层的厚度为
    Figure PCTCN2022095713-appb-100001
    和/或，所述第二栅绝缘层的厚度为
    Figure PCTCN2022095713-appb-100002
    和/或，所述第三栅绝缘层的厚度为
    Figure PCTCN2022095713-appb-100003
  21. 一种显示装置，包括如权利要求1～20中任一项所述的显示面板。
PCT/CN2022/095713 2022-05-27 2022-05-27 显示面板及显示装置 WO2023226023A1 (zh)

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