WO2023236210A1 - 显示面板及其修复方法、显示装置 - Google Patents

显示面板及其修复方法、显示装置 Download PDF

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Publication number
WO2023236210A1
WO2023236210A1 PCT/CN2022/098244 CN2022098244W WO2023236210A1 WO 2023236210 A1 WO2023236210 A1 WO 2023236210A1 CN 2022098244 W CN2022098244 W CN 2022098244W WO 2023236210 A1 WO2023236210 A1 WO 2023236210A1
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WIPO (PCT)
Prior art keywords
signal line
substrate
gate
conductive block
display panel
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PCT/CN2022/098244
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English (en)
French (fr)
Inventor
王海涛
汪军
成军
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280001726.XA priority Critical patent/CN117616562A/zh
Priority to PCT/CN2022/098244 priority patent/WO2023236210A1/zh
Publication of WO2023236210A1 publication Critical patent/WO2023236210A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel, a repair method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • a display panel includes a substrate, a scanning signal line and at least one first conductive block.
  • the scanning signal line is provided on the substrate; the scanning signal line includes a wiring body and at least one transfer pad, and the transfer pad is provided at an end of the wiring body.
  • the at least one first conductive block is located on a different layer from the scanning signal line and is electrically insulated from the scanning signal line; the orthographic projection of the first conductive block on the substrate is in contact with the transfer pad Orthographic projections on the substrate at least partially overlap.
  • the trace body extends generally along the first direction, and the size of the transfer pad in the second direction is greater than the width of the trace body; the second direction is different from the first direction. Roughly vertical.
  • the display panel further includes a pixel circuit and at least one second conductive block.
  • the pixel circuit is disposed on the substrate; the pixel circuit includes a plurality of transistors, and the transistors include gates.
  • At least one second conductive block is located on a different layer from the gate of the transistor and is electrically insulated from the gate of the transistor; the orthographic projection of the second conductive block on the substrate is in contact with the pixel circuit. Orthographic projections of the gates of at least one transistor on the substrate at least partially overlap.
  • the pixel circuit includes a switching transistor, and an orthographic projection of the second conductive block on the substrate at least partially intersects an orthographic projection of the gate of the switching transistor on the substrate.
  • the pixel circuit includes a sensing transistor, and an orthographic projection of the second conductive block on the substrate is at least the same as an orthographic projection of the gate of the sensing transistor on the substrate. Partially overlapped.
  • the gate of the transistor is integrally provided with the scanning signal line.
  • the display panel has a display area and a peripheral area at least partially surrounding the display area, and the scanning signal line is located in the display area.
  • the display panel further includes a scan driving circuit, at least one gate signal line and a third conductive block.
  • the scan driving circuit is disposed on the substrate and located in the peripheral area.
  • the at least one gate signal line is arranged in the same layer as the scanning signal line and is located in the peripheral area.
  • the at least one gate signal line extends along a second direction and is electrically connected to the scan driving circuit; the second direction is substantially perpendicular to the extension direction of the scan signal line.
  • the third conductive block is arranged in the same layer as the scanning signal line and is located between the at least one gate signal line and the scanning signal line.
  • the display panel further includes at least one fourth conductive block, the at least one fourth conductive block and the third conductive block are located on different layers and are electrically insulated from the third conductive block;
  • the orthographic projection of the fourth conductive block on the substrate at least partially overlaps the orthographic projection of at least one third conductive block on the substrate.
  • each of the scan signal lines and the at least one gate signal line is provided with one third conductive block.
  • the display panel further includes a plurality of pixel circuits, the plurality of pixel circuits are arranged in multiple rows and multiple columns, and each row of pixel circuits is electrically connected to a plurality of scanning signal lines.
  • a plurality of scanning signal lines electrically connected to the same row of pixel circuits are a group of scanning signal lines, and a plurality of third conductive blocks located between a group of scanning signal lines and the at least one gate signal line are a group of third conductive blocks. .
  • the orthographic projections of the set of third conductive blocks on the substrate at least partially overlap with the orthographic projections of the same fourth conductive block on the substrate.
  • the display panel further includes an adapter line, one end of the adapter line is electrically connected to the adapter pad of the scan signal line, and the other end is electrically connected to the scan drive circuit; the adapter line is connected to The scanning signal lines are located on different layers, and the orthographic projection of the transfer line on the substrate partially overlaps the orthographic projection of at least one gate signal line on the substrate.
  • the gate signal lines that overlap with the orthographic projection of the transfer line on the substrate at least one gate signal line is provided with at least one hollow area, and the orthographic projection of each hollow area on the substrate is, It overlaps with the orthographic projection of at least one transfer line on the substrate; and the length of the hollow area in the second direction is greater than the width of the transfer line in the second direction.
  • the gate signal line closest to the display area is a set gate signal line
  • the set gate signal line is on the substrate.
  • the orthographic projection overlaps with the orthographic projection of the transfer line on the substrate, and the hollow area is provided on the setting gate signal line.
  • the at least one gate signal line includes a gate initialization signal line, at least one clock signal line, a first gate voltage signal line and a second gate voltage signal line. From the display area to the peripheral area, the first gate voltage signal line, the second gate voltage signal line, the at least one clock signal line and the gate initialization signal line are arranged in sequence; the setting gate signal line is The first gate voltage signal line.
  • the display panel includes a plurality of pixel circuits, the plurality of pixel circuits are arranged in multiple rows and multiple columns, and each row of pixel circuits is electrically connected to multiple scanning signal lines.
  • a plurality of scanning signal lines electrically connected to the same row of pixel circuits are a group of scanning signal lines
  • a plurality of transfer lines electrically connected to a group of scanning signal lines are a group of transfer lines
  • a group of transfer lines are on the substrate.
  • the orthographic projections on the substrate partially overlap with the orthographic projections of the same hollow area on the substrate.
  • the shape of the hollow area is generally elongated.
  • the display panel includes a plurality of pixel circuits, the plurality of pixel circuits are arranged in multiple rows and multiple columns, and each row of pixel circuits is electrically connected to at least one scanning signal line.
  • at least one gate signal line includes alternately connected first wiring segments and second wiring segments, and the first wiring segments are disposed on One side of a row of pixel circuits in the first direction; the first wiring segment includes a plurality of sub-line segments arranged in parallel, and both ends of each sub-line segment are connected to adjacent second wiring segments on both sides.
  • the orthographic projections of the plurality of sub-trace segments of the first wiring segment on the substrate partially overlap with the orthographic projection of at least one transfer line on the substrate.
  • the orthographic projection of the transfer line on the substrate is staggered from the orthographic projection of the third conductive block on the substrate.
  • the display panel includes a plurality of pixel circuits, the plurality of pixel circuits are arranged in multiple rows and multiple columns, and each row of pixel circuits is electrically connected to multiple scanning signal lines.
  • multiple scanning signal lines electrically connected to the same row of pixel circuits are a group of scanning signal lines, and the orthographic projections of the multiple transfer pads of a group of scanning signal lines on the substrate are all connected to the same first conductive Orthographic projections of the blocks on the substrate at least partially overlap.
  • the display panel includes a first conductive block, a second conductive block and a fourth conductive block, the first conductive block, the second conductive block and the fourth conductive block are made of the same material and Same layer settings.
  • the display panel sequentially includes a light shielding layer, a first insulating layer, a semiconductor layer, a gate insulating layer, a gate conductive layer, and an interlayer insulating layer. and source and drain conductive layers.
  • the first conductive block, the second conductive block and the fourth conductive block are located on the light shielding layer.
  • the pixel circuit includes a drive transistor.
  • the light-shielding layer further includes at least one light-shielding block, and the orthographic projection of the light-shielding block on the substrate at least partially coincides with the orthographic projection of the channel region of the driving transistor on the substrate.
  • the display panel further includes a gate signal line and a third conductive block, and the scanning signal line, the third conductive block and the gate signal line are located on the gate conductive layer.
  • the display panel includes a second conductive block, a third conductive layer, a fourth conductive block and two scan driving circuits.
  • the two scan driving circuits are disposed on opposite sides of the display area in the first direction, and the first conductive block, the second conductive block, the third conductive layer and the fourth conductive layer
  • the blocks are arranged symmetrically with respect to a centerline of the display area along a second direction; the second direction is substantially perpendicular to the first direction.
  • the display device includes the display panel as described in any of the above embodiments.
  • a method for repairing a display panel includes a scan signal line, a scan drive circuit, a gate signal line and an adapter line.
  • the gate signal line is electrically connected to the scan drive circuit.
  • One end of the adapter line is electrically connected to the scan signal line, and the other end of the adapter line is electrically connected to the scan signal line. electrically connected to the scan driving circuit.
  • the scanning signal line and the gate signal line are arranged on the same layer, the transfer line and the scanning signal line are located on different layers, and the orthographic projection of the transfer line on the substrate is the same as the gate signal line.
  • the orthographic projections on the substrate partially overlap;
  • the gate signal line includes alternately connected first wiring segments and second wiring segments, and the first wiring segments are provided on one side of a row of pixel circuits in the first direction;
  • the first wiring segment includes a plurality of sub-line segments arranged in parallel, and both ends of each sub-line segment are connected to the second wiring segments adjacent to both sides; the plurality of sub-line segments of the first wiring segment are in the
  • the orthographic projection on the substrate partially overlaps with the orthographic projection of the transfer line on the substrate.
  • the repair method includes: when the transfer line and the gate signal line are short-circuited, determine a target sub-line segment; the target sub-line segment is one of the multiple sub-line segments of the first line segment of the gate signal line. A sub-trace segment that is short-circuited with the patch cord. Cut both ends of the target sub-trace segment so that the two ends of the target sub-trace segment are disconnected from the adjacent second trace segments on both sides.
  • Figure 1 is a structural diagram of a display device according to some embodiments.
  • Figure 2 is a structural diagram of a display panel according to some embodiments.
  • Figure 3 is a structural diagram of another display panel according to some embodiments.
  • Figure 4 is a cross-sectional view of another display panel according to some embodiments.
  • Figure 5 is a circuit diagram of a sub-pixel according to some embodiments.
  • Figure 6 is a timing diagram of the circuit of the sub-pixel shown in Figure 5;
  • Figure 7 is a structural diagram of a display panel according to some embodiments.
  • Figure 8 is a structural diagram of yet another display panel according to some embodiments.
  • Figure 9 is a circuit wiring diagram of the display panel shown in Figure 8.
  • Figure 10 is a cross-sectional view along A-A' in Figure 9;
  • Figure 11 is a cross-sectional view along B-B' in Figure 9;
  • Figure 12 is a flowchart of a repair method of a display panel according to some embodiments.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
  • connection and its derivatives may be used.
  • some embodiments may be described using the term “connected” to indicate that two or more components are in direct physical or electrical contact with each other.
  • the embodiments disclosed herein do not necessarily limit the present disclosure.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C” and includes the following combinations of A, B and C: A only, B only, C only, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • parallel includes absolutely parallel and approximately parallel, and the acceptable deviation range of approximately parallel may be, for example, a deviation within 5°;
  • perpendicular includes absolutely vertical and approximately vertical, and the acceptable deviation range of approximately vertical may also be, for example, Deviation within 5°.
  • equal includes absolute equality and approximate equality, wherein the difference between the two that may be equal within the acceptable deviation range of approximately equal is less than or equal to 5% of either one, for example.
  • the control pole of each transistor is a gate of the transistor, a first pole of the transistor is one of the source and drain of the transistor, and a second pole of the transistor is the other of the source and drain of the transistor. Since the source and drain of the transistor may be symmetrical in structure, the source and drain of the transistor may be structurally indistinguishable. That is to say, the first electrode and the third electrode of the transistor in the embodiment of the present disclosure The two poles can be structurally indistinguishable. For example, when the transistor is a P-type transistor, the first pole of the transistor is the source, and the second pole is the drain; for example, when the transistor is an N-type transistor, the first pole of the transistor is the drain, The second pole is the source.
  • “same layer” refers to a layer structure in which the same film formation process is used to form a film layer for forming a specific pattern, and then the same mask is used to form the film layer through a patterning process.
  • a patterning process may include multiple exposure, development or etching processes, and the film layers of the specific pattern in the formed layer structure may be continuous or discontinuous. These specific pattern film layers They may also be at different heights or have different thicknesses.
  • a display device 1000 which may be any device that displays images, whether moving (eg, video) or fixed (eg, still images), and whether text or text.
  • the display device 1000 can be a television, a laptop, a tablet, a mobile phone, a personal digital assistant (Personal Digital Assistant; PDA for short), a navigator, a wearable device, or a virtual reality (Virtual Reality; VR for short) ) equipment and any other product or component with a display function.
  • PDA Personal Digital Assistant
  • VR Virtual Reality
  • a display device 1000 includes a display panel 100 .
  • the above-mentioned display device 1000 may also include a housing 200 , a circuit board (not shown in FIG. 1 ), and other electronic accessories.
  • the display panel 100 and the circuit board may be disposed in the housing 200 .
  • the above-mentioned display panel 100 includes multiple types, and can be selected and set according to actual needs.
  • the above display panel 100 can be: an organic light emitting diode (OLED for short) display panel, a quantum dot light emitting diode (Quantum Dot Light Emitting Diode for short: QLED) display panel, a micro light emitting diode (Micro light emitting diode).
  • OLED organic light emitting diode
  • QLED quantum dot Light emitting diode
  • Micro light emitting diode Micro light emitting diode
  • Light Emitting Diodes abbreviated as: Micro LED
  • the above-mentioned display panel 100 has a display area A, and a peripheral area B disposed on at least one side of the display area A.
  • the peripheral area B is arranged around the display area A as an example.
  • the display area A is an area for displaying images and is configured to provide a plurality of sub-pixels P.
  • the peripheral area B is an area where no image is displayed, and the peripheral area B is configured to provide display driving circuits and circuit wiring, such as the scan driving circuit 110, the source driving circuit 120, and the gate signal line 170.
  • the display panel 100 may include a substrate 10 , a scan driving circuit 110 and at least one gate signal line 170 .
  • the scan drive circuit 110 and the gate signal line 170 are disposed on the substrate 10 .
  • the gate signal line 170 is electrically connected to the scan drive circuit 110 , and the gate signal line 170 is configured to provide control to the scan drive circuit 110 Signal.
  • the control signal includes at least one of a first gate voltage signal VGL, a second control signal VGH, an initialization signal STV and a clock signal.
  • substrate 10 may be a rigid substrate.
  • the rigid substrate may be a glass substrate or a PMMA (Polymethyl Methacrylate) substrate.
  • substrate 10 may be a flexible substrate.
  • the flexible substrate can be a polyethylene terephthalate (Polyethylene Terephthalate, referred to as: PET) substrate, a polyethylene naphthalate two formic acid glycol ester (abbreviated as: PEN) substrate Bottom or polyimide (Polyimide, referred to as: PI) substrate, etc.
  • PET polyethylene Terephthalate
  • PEN polyethylene naphthalate two formic acid glycol ester
  • PI polyimide
  • the above-mentioned display panel 100 may also include a plurality of sub-pixels P.
  • the plurality of sub-pixels P and the scan driving circuit 110 are disposed on the same side of the substrate 10 and are located in the display area A. .
  • the components included in the sub-pixel P can be shown in FIG. 4 and FIG. 5 .
  • each sub-pixel P may include a pixel circuit 130 provided on the substrate 10 and a light-emitting device 140 electrically connected to the pixel circuit 130 .
  • the pixel circuit 130 includes a plurality of transistors 131 .
  • the transistor 131 includes an active layer 1311, a source electrode 1312, a drain electrode 1313 and a gate electrode 1314.
  • the source electrode 1312 and the drain electrode 1313 are respectively in contact with the active layer 1311.
  • the light-emitting device 140 includes a first electrode layer 141 , a light-emitting functional layer 142 and a second electrode layer 143 .
  • the first electrode layer 141 and the source of the transistor 131 serving as a driving transistor among the plurality of transistors 131 1312 or drain 1313 are electrically connected.
  • the first electrode layer 141 and the drain electrode 1313 of the transistor 131 are electrically connected for illustration.
  • source electrode 1212 and drain electrode 1213 can be interchanged, that is, 1312 in Figure 4 represents the drain electrode, and 1313 in Figure 4 represents the source electrode.
  • multiple sub-pixels P may be arranged in multiple rows and multiple columns, each row includes multiple sub-pixels P arranged along the first direction X, and each column includes multiple sub-pixels P arranged along the second direction Y.
  • the first direction X and the second direction Y are approximately perpendicular.
  • the display panel 100 may further include at least one scanning signal line 150 extending generally along the first direction X, and at least one data line 160 extending generally along the second direction Y. .
  • the scanning signal line 150 is electrically connected to the scanning driving circuit 110
  • the data line 160 is electrically connected to the source driving circuit 120.
  • the pixel circuits 130 of the sub-pixels P in the same row can be electrically connected to the scanning signal lines 150 extending substantially along the first direction X, and the pixel circuits 130 of the sub-pixels P in the same column can be electrically connected. Electrically connected to a data line 160.
  • the scan driving circuit 110 only includes a gate driving circuit 111
  • the scanning signal line 150 only includes a gate scanning signal line GL
  • the gate scanning signal line GL is configured to transmit the scanning signal Gate and /or reset signal Reset.
  • the scan driving circuit 110 includes a light-emitting driving circuit in addition to the gate driving circuit 111.
  • the scanning signal line 150 includes an enable signal line in addition to the gate scan signal line GL.
  • the signal line is configured to transmit the enable signal Em.
  • the pixel circuit 130 has a variety of structures, and the configuration can be selected according to actual needs.
  • the structure of the pixel circuit 130 may include a "2T1C”, “3T1C”, “6T1C”, “7T1C”, “8T1C”, “6T2C” or “7T2C” structure.
  • T represents the transistor
  • the number in front of “T” represents the number of transistors
  • C represents the storage capacitor
  • the number in front of "C” represents the number of storage capacitors.
  • the stability of the transistors and the light-emitting device 140 in the pixel circuit 130 may decrease (for example, the threshold voltage of the driving transistor drifts), affecting the display effect of the display panel 100, so that it is necessary to Pixel P is compensated.
  • a pixel compensation circuit may be provided in the sub-pixel P, so that the sub-pixel P is internally compensated by the pixel compensation circuit.
  • the driving transistor or light-emitting device can be sensed through the transistor inside the sub-pixel P, and the sensed data can be transmitted to an external sensing circuit, so that the external sensing circuit can be used to calculate the driving voltage value that needs to be compensated and provide feedback. , thereby achieving external compensation for sub-pixel P.
  • the pixel circuit 130 is any one of the pixel circuits 130 located in the N-th row of sub-pixels P; where N is a positive integer.
  • the scan driving circuit 110 includes only the gate driving circuit 111 , and the above-mentioned scanning signal line 150 includes only the gate scanning signal line GL.
  • the gate scanning signal line GL can transmit the scanning signal Gate and the reset signal Reset respectively. Please refer to the following for details.
  • the pixel circuit 130 may include: a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst.
  • the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal G1
  • the first electrode of the first transistor T1 is electrically connected to the data signal terminal DATA
  • the second electrode of the first transistor T1 is electrically connected to the first scan signal terminal G1.
  • Node N1 is electrically connected.
  • the first transistor T1 is configured to transmit the data signal received at the data signal terminal DATA to the first node N1 in response to the first scan signal received at the first scan signal terminal G1.
  • the data signal may include, for example, a detection data signal and a display data signal.
  • the detection data signal is used in the blanking period
  • the display data signal is used in the display period.
  • the display period and blanking period reference may be made to the descriptions in some embodiments below and will not be described again here.
  • the control electrode of the second transistor T2 is electrically connected to the first node N1
  • the first electrode of the second transistor T2 is electrically connected to the first voltage signal terminal ELVDD
  • the second electrode of the second transistor T2 is electrically connected to the second node N1.
  • Node N2 is electrically connected.
  • the second transistor T2 is configured to transmit the voltage signal received at the first voltage signal terminal ELVDD to the second node N2 under the control of the voltage of the first node N1.
  • the first end of the storage capacitor Cst is electrically connected to the first node N1, and the second end of the storage capacitor Cst is electrically connected to the second node N2.
  • the first transistor T1 also charges the storage capacitor Cst.
  • the anode of the light-emitting device 140 is electrically connected to the second node N2, and the cathode of the light-emitting device 140 is electrically connected to the second voltage signal terminal ELVSS.
  • the light-emitting device 140 is configured to emit light in cooperation with the voltage signal from the second node N2 and the voltage signal transmitted by the second voltage signal terminal ELVSS.
  • the control electrode of the third transistor T3 is electrically connected to the second scanning signal terminal G2, the first electrode of the third transistor T3 is electrically connected to the sensing signal terminal SENSE, and the second electrode of the third transistor T3 is electrically connected to the second scanning signal terminal G2.
  • the two nodes N2 are electrically connected.
  • the third transistor T3 is configured to detect the electrical characteristics of the second transistor T2 in response to the second scan signal received at the second scan signal terminal G2 to achieve external compensation.
  • the electrical characteristics may include the threshold voltage and/or carrier mobility of the second transistor T2.
  • the sensing signal terminal SENSE may provide a reset signal or acquire a sensing signal, where the reset signal is used to reset the second node N2 and the sensing signal is used to acquire the threshold voltage of the second transistor T2.
  • nodes N1 and N2 do not represent actual existing components, but represent the meeting points of relevant electrical connections in the circuit diagram. That is to say, these nodes are connected by relevant electrical connections in the circuit diagram.
  • one frame period may include a display period and a blanking period in sequence.
  • the sub-pixel P performs image display.
  • the blanking period sub-pixel P undergoes external compensation.
  • the following is only a schematic description of the display periods.
  • the working process of the sub-pixel P may include, for example, a reset phase P1, a data writing phase P2, and a light emitting phase P3.
  • the level of the second scanning signal provided by the second scanning signal terminal G2 is high level, and the sensing signal terminal SENSE provides a reset signal (the level of the reset signal is, for example, low level).
  • the third transistor T3 is turned on under the control of the second scan signal, receives the reset signal, and transmits the reset signal to the second node N2 to reset the second node N2.
  • the level of the first scanning signal provided by the first scanning signal terminal G1 is high level, and the level of the display data signal provided by the data signal terminal DATA is high level.
  • the first transistor T1 is turned on under the control of the first scan signal, receives the display data signal, and transmits the display data signal to the first node N1 while charging the storage capacitor Cst.
  • the level of the first scanning signal provided by the first scanning signal terminal G1 is low level
  • the level of the second scanning signal provided by the second scanning signal terminal G2 is low level
  • the level of the first scanning signal provided by the second scanning signal terminal G2 is low level.
  • the level of the voltage signal provided by the voltage signal terminal ELVDD is high level.
  • the first transistor T1 is turned off under the control of the first scan signal
  • the third transistor T3 is turned off under the control of the second scan signal.
  • the storage capacitor Cst starts to discharge, so that the voltage of the first node N1 remains at a high level.
  • the second transistor T2 is turned on under the control of the voltage of the first node N1, receives the voltage signal from the first voltage signal terminal ELVDD, and transmits the voltage signal to the second node N2, so that the light emitting device 140 is at the second node N2
  • the voltage signal of the second voltage signal terminal ELVSS cooperates with the voltage signal of the second voltage signal terminal ELVSS to emit light.
  • multiple pixel circuits 130 in the same row of sub-pixels P can be electrically connected to the same scanning signal line 150, Referring to FIG. 3 and FIG. 5 , multiple pixel circuits 130 in the same row of sub-pixels P may also be electrically connected to two scanning signal lines 150 .
  • multiple pixel circuits 130 in the same row of sub-pixels P and two gate scanning signal lines GL, and the two gate scanning signal lines GL may include a first gate scanning signal line GL1 and the second gate scanning signal line GL2.
  • the first gate scanning signal line GL1 is electrically connected to the first scanning signal terminals G1 of the plurality of pixel circuits 130 in the sub-pixel P in the Nth row, that is, the first gate scanning signal line GL1 is electrically connected to the control electrode of the first transistor T1 ;
  • the first gate scanning signal line GL1 is configured to transmit the first scanning signal.
  • the second gate scanning signal line GL2 is electrically connected to the second scanning signal terminals G2 of the plurality of pixel circuits 130 in the sub-pixel P of the Nth row, that is, is electrically connected to the control electrode of the third transistor T3 ;
  • the second gate scanning signal line GL2 is configured to transmit the second scanning signal.
  • ESD Electrostatic Discharge
  • the discharge process will breakdown the insulating film layer, causing a short circuit between the conductive layers of different layers.
  • the scanning signal line and the gate signal line (the first gate voltage signal line or the second gate voltage signal line, etc.) in the peripheral area are short-circuited, resulting in horizontal dark lines on the display panel; for another example, the trench between the scanning signal line and the transistor The channel area is short-circuited, resulting in vertical dark lines on the display panel.
  • the channel region of the transistor 131 may be that in the active layer 1311 of the transistor 131 , the orthographic projection of the active layer 1311 on the substrate 10 and the gate electrode 1314 of the transistor 131 on the substrate 10 are The overlapped portion of the orthographic projection.
  • some embodiments of the present disclosure provide a display panel 100 , which further includes at least one first conductive block 30 .
  • the first conductive block 30 is located in a different position from the scanning signal line 150 . layer, and is electrically insulated from the scanning signal line 150.
  • the scanning signal line 150 includes a wiring body 151 and at least one transfer pad 152 , and the transfer pad 152 is provided at an end of the wiring body 151 .
  • the transfer pad 152 may be configured to connect to the transfer wires 180 located on other film layers, and to be electrically connected to the scan driving circuit 110 through the transfer wires 180 .
  • the scanning signal lines 150 are arranged on the same layer as the gate signal lines 170 .
  • the scanning signal lines generally extend along the first direction X
  • the gate signal lines 170 generally extend along the second direction Y.
  • at least one gate signal line 170 is located on the side of the scan driving circuit 110 close to the display area A.
  • the display panel 100 further includes an adapter line 180 , one end of the adapter line 180 is electrically connected to the adapter pad 152 of the scan signal line 150 , and the other end is electrically connected to the scan drive circuit 110 , so that the scan signal line 150 and the scan drive circuit 110 Electrical connection.
  • the transfer line 180 and the scanning signal line 150 are located on different layers, and the orthographic projection of the transfer line 180 on the substrate 10 partially overlaps with the orthographic projection of at least one gate signal line 170 on the substrate 10 .
  • the above-mentioned wiring body 151 extends generally along the first direction Connection to adapter pad 152.
  • the number of transfer pads 152 depends on whether the scanning signal line 150 is driven on one side or on both sides.
  • the scanning signal line 150 when the scanning signal line 150 adopts the single-side driving method shown in FIG. 7 , the scanning signal line 150 includes a wiring body 151 (see FIG. 9 ) and an adapter pad 152 (See FIG. 9 ).
  • the transfer pad 152 (see FIG. 9 ) is disposed at one end of the wiring body 151 (see FIG. 9 ) close to the scan drive circuit 110 and is electrically connected to the scan drive circuit 110 through the transfer wire 180 .
  • the size of the peripheral area B of the display panel 100 can be reduced and the manufacturing cost of the display panel 100 can be reduced.
  • the single-sided driving method for the scanning signal line 150 means that the display panel 100 includes a scanning driving circuit 110, and the scanning driving circuit 110 is disposed in the first direction of the display area A (the extending direction of the scanning signal line 150). ), each scanning signal line 150 is sequentially driven row by row.
  • the scanning signal line 150 when the scanning signal line 150 adopts the double-side driving method as shown in FIG. 8 , the scanning signal line 150 includes a wiring body 151 and two transfer pads 152 .
  • the pads 152 are respectively disposed at two opposite ends of the wiring body 151 , and are electrically connected to the corresponding scan driving circuits 110 through adapter wires 180 .
  • the accuracy of signals received from the scanning signal lines 150 by each pixel circuit 130 in the same row can be improved, and the impact of the voltage drop caused by the length of the scanning signal lines 150 can be reduced.
  • the double-sided driving method for the scanning signal line 150 means that the display panel 100 includes two scanning driving circuits 110 , and the two scanning driving circuits 110 are respectively disposed in the first direction of the display area A (the scanning signal line 150), the two scan driving circuits 110 simultaneously drive each scanning signal line 150 row by row from both sides.
  • the orthographic projection of the first conductive block 30 on the substrate 10 at least partially overlaps with the orthographic projection of the transfer pad 152 on the substrate 10 .
  • the orthographic projection of the transfer pad 152 on the substrate 10 is located within the orthographic projection of the first conductive block 30 on the substrate 10 , so that the transfer pad 152 is in contact with the first conductive block 30 .
  • the facing area of the block 30 is the largest, thereby maximizing the amount of charge that can be stored in the first capacitor formed by the transfer pad 152 and the first conductive block 30 .
  • the portion of the first conductive block 30 opposite to the transfer pad 152 forms a first capacitor. Since the first capacitor can store charges, the first capacitor can reduce the risk of electrostatic discharge at the transfer pads 152 at one or both ends of the extension direction of the scanning signal line 150 , thereby reducing the risk of electrostatic discharge at the transfer pads 152 causing different layers.
  • the risk of short circuit between conductive layers for example, reduces the risk of short circuit between the scan signal line 150 and the gate signal line 170 in the peripheral area B, thereby reducing the risk of horizontal dark lines on the display panel 100 .
  • the display panel 100 may further include at least one second conductive block 40 , and the second conductive block 40 and the gate electrode 1314 of the transistor 131 are located on a different layer. and is electrically insulated from the gate 1314 of the transistor 131 .
  • the orthographic projection of the second conductive block 40 on the substrate 10 at least partially overlaps with the orthographic projection of the gate 1314 of at least one transistor 131 in the pixel circuit 130 on the substrate 10 .
  • the orthographic projection of the gate 1314 of at least one transistor 131 in the pixel circuit 130 on the substrate 10 is located within the orthographic projection of the second conductive block 40 on the substrate 10 , so that the facing area of the gate 1314 and the second conductive block 40 is maximized, so that the amount of charge that can be stored in the second capacitor formed by the gate 1314 and the second conductive block 40 is maximized.
  • the portion of the second conductive block 40 opposite to the gate electrode 1314 of the transistor 131 forms a second capacitor. Since the second capacitor can store charges, the second capacitor can reduce the risk of electrostatic discharge from the gate electrode 1314 of the transistor 131, thereby reducing the risk of electrostatic discharge from the gate electrode 1314 of the transistor 131 causing a short circuit between conductive layers of different layers, for example The risk of a short circuit between the gate 1314 of the transistor 131 and the channel region of the transistor 131 is reduced, thereby reducing the risk of vertical dark lines on the display panel 100 .
  • the gate 1314 of the transistor 131 may be integrally provided with the scanning signal line 150 .
  • the pixel circuit 130 includes a switching transistor (T1 in FIG. 5), an orthographic projection of the second conductive block 40 on the substrate 10, and a gate electrode 1314 of the switching transistor. Orthographic projections on substrate 10 at least partially overlap.
  • the gate electrode 1314 of the switching transistor is located in the orthographic projection of the second conductive block 40 on the substrate 10 .
  • the facing area between the gate electrode 1314 of the switching transistor and the second conductive block 40 is maximized, thereby maximizing the amount of charge that can be stored in the second capacitor formed by the gate electrode 1314 of the switching transistor and the second conductive block 40, thereby reducing the switching cost. Risk of shorting the gate 1314 of the transistor to the channel region.
  • the gate electrode 1314 of the switching transistor may be integrally provided with the scanning signal line 150 .
  • the first transistor T1 is a switching transistor.
  • the scanning signal line 150 includes a first gate scanning signal line GL1.
  • the first gate scanning signal line GL1 is electrically connected to the first scanning signal terminal G1 of the pixel circuit 130. That is, the first gate scanning signal line GL1 is located between the first transistor T1 and the first scanning signal line GL1.
  • the portion above the active layer 1311 may directly serve as the gate electrode 1314 of the first transistor T1.
  • the gate electrode 1314 of the first transistor T1 is integrally provided with the first gate scanning signal line GL1.
  • the pixel circuit 130 adopts an external compensation method, that is, the pixel circuit 130 also includes a sensing transistor (T3 in Figure 5), and the second conductive block 40 is on the substrate.
  • the orthographic projection on substrate 10 at least partially overlaps with the orthographic projection of the gate 1314 of the sensing transistor on substrate 10 .
  • the gate electrode 1314 of the sensing transistor is located within the orthographic projection of the second conductive block 40 on the substrate 10 .
  • the gate electrode 1314 of the sensing transistor is located within the orthographic projection of the second conductive block 40 on the substrate 10 .
  • the risk of shorting the gate 1314 of the sensing transistor to the channel region is reduced.
  • the gate electrode 1314 of the sensing transistor may be integrally provided with the scanning signal line 150 .
  • the third transistor T3 is a sensing transistor.
  • the scanning signal line 150 includes a second gate scanning signal line GL2.
  • the second gate scanning signal line GL2 is electrically connected to the second scanning signal terminal G2 of the pixel circuit 130. That is, the second gate scanning signal line GL2 is located between the third transistor T3 and the third transistor T3.
  • the portion above the active layer 1311 may directly serve as the gate electrode 1314 of the third transistor T3.
  • the gate electrode 1314 of the third transistor T3 is integrally provided with the second gate scanning signal line GL2.
  • the above-mentioned display panel 100 may further include at least one third conductive block 50 .
  • the third conductive block 50 is arranged on the same layer as the scanning signal line 150 and is located on the gate signal line. 170 and scanning signal line 150.
  • the display panel 100 further includes a plurality of third conductive blocks 50 , and a third conductive block is provided between each scan signal line 150 and the gate signal line 170 .
  • Block 50 a third conductive block is provided between each scan signal line 150 and the gate signal line 170 .
  • a third conductive block 50 is disposed between the gate signal line 170 and the scanning signal line 150, and the third conductive block 50 is not connected to other circuits, that is, the third conductive block 50 is floating. state.
  • the short circuit between the scan signal line 150 or the adapter line 180 and the gate signal line 170 requires at least two electrostatic discharges. Therefore, the risk of a short circuit between the gate signal line 170 and the scan signal line 150 can be reduced.
  • the first electrostatic discharge may be that electrostatic discharge occurs at the adapter pad 152 of the scanning signal line 150, causing the scanning signal line 150 or the adapter line 180 to be electrically connected to the third conductive block 50;
  • the second electrostatic discharge may be , the electrostatic discharge at the third conductive block 50 causes a short circuit between the third conductive block 50 and the gate signal line 170 , which further causes a short circuit between the scanning signal line 150 or the transfer line 180 and the gate signal line 170 .
  • the orthographic projection of the above-mentioned transfer line 180 on the substrate 10 is staggered from the orthographic projection of the third conductive block 50 on the substrate 10 to reduce the distance between the transfer line 180 and the third conductive block 50 . Risk of short circuit of three conductive blocks 50.
  • the display panel 100 may further include at least one fourth conductive block 60 .
  • the fourth conductive block 60 and the third conductive block 50 are located on different layers and are electrically insulated from the third conductive block 50 .
  • the orthographic projection of the fourth conductive block 60 on the substrate 10 at least partially overlaps the orthographic projection of the at least one third conductive block 50 on the substrate 10 .
  • the orthographic projection of the third conductive block 50 on the substrate 10 is located within the orthographic projection of the fourth conductive block 60 on the substrate 10 , so that the third conductive block 50 is connected with the third conductive block 50 .
  • the facing area of the four conductive blocks 60 is the largest, thereby maximizing the amount of charge that can be stored in the third capacitor formed by the third conductive block 50 and the fourth conductive block 60 .
  • the portion of the third conductive block 50 opposite to the fourth conductive block 60 forms a third capacitor. Since the third capacitor can store charges, the third capacitor can reduce the risk of electrostatic discharge at the third conductive block 50 , that is, reduce the risk of a second electrostatic discharge, thereby reducing the risk of shortcomings between the scan signal line 150 and the gate signal line 170 . risk.
  • the first conductive block 30 , the second conductive block 40 and the fourth conductive block 60 are made of the same material and are arranged in the same layer.
  • the specific film layer 60 is located can be referred to below, and the embodiments of the present disclosure will not be described in detail here.
  • two scanning driving circuits 110 are disposed on opposite sides of the display area A in the first direction X.
  • a conductive block 30 , a second conductive block 40 , a third conductive block 50 and a fourth conductive block 60 are arranged symmetrically with respect to the center line L of the display area A along the second direction Y.
  • multiple pixel circuits 130 in the same row of sub-pixels P can be electrically connected to one scanning signal line 150, or can be electrically connected to multiple scanning signal lines 150.
  • Signal line 150 is electrically connected.
  • each row of pixel circuits 130 is electrically connected to a plurality of scanning signal lines 150 .
  • a plurality of scanning signal lines 150 electrically connected to the same row of pixel circuits 130 are a group of scanning signal lines 150
  • a plurality of third conductive blocks 50 located between a group of scanning signal lines 150 and the gate signal lines 170 are a group. The third conductive block 50.
  • multiple pixel circuits 130 in the same row of sub-pixels P are electrically connected to two scanning signal lines 150 . That is to say, one group of scanning signal lines 150 includes two scanning signal lines 150 , and a group of third conductive blocks 50 includes two third conductive blocks 50 .
  • the orthographic projection of a group of third conductive blocks 50 on the substrate 10 at least partially overlaps with the orthographic projection of the same fourth conductive block 60 on the substrate 10 .
  • a group of third conductive blocks 50 can share a fourth conductive block 60, which facilitates production and lowers the cost.
  • the orthographic projections of the multiple transfer pads 152 of a set of scanning signal lines 150 on the substrate 10 are the same as the orthographic projections of the same first conductive block 30 on the substrate 10 . At least partially overlap. Arranged in this way, multiple transfer pads 152 of a set of scanning signal lines 150 can share a first conductive block 30 , which facilitates production and lowers the cost.
  • At least one gate signal line 170 is provided with at least one hollow.
  • Area H The orthographic projection of each hollow area H on the substrate 10 partially overlaps with the orthographic projection of at least one transfer line 180 on the substrate 10 ; and, the length of the hollow area H in the second direction Y is greater than the transfer line 180 The width in the second direction Y.
  • the shape of the above-mentioned hollow area H may be substantially elongated.
  • At least one gate signal line 170 includes alternately connected first wiring segments 171 and the second wiring segment 172, the first wiring segment 171 is disposed on one side of the row of pixel circuits 130 in the first direction X.
  • the first trace segment 171 includes a plurality of sub-trace segments 1710 arranged in parallel, and both ends of each sub-trace segment 1710 are connected to the adjacent second trace segments 172 on both sides.
  • the orthographic projections of the plurality of sub-route segments 1710 of the first wiring segment 171 on the substrate 10 partially overlap with the orthographic projection of at least one transfer line 180 on the substrate 10 .
  • the gate signal line 170 closest to the display area A is the set gate signal line 173 , and the set gate signal line 173 is at
  • the orthographic projection on the substrate 10 partially overlaps with the orthographic projection of the transfer line 180 on the substrate 10 (see FIG. 10 ), and a hollow area H is provided on the set gate signal line 173 . That is, the gate signal line 173 is set to include alternately connected first wiring segments 171 and second wiring segments 172 .
  • At least one gate signal line 170 includes a gate initialization signal line SL, at least one clock signal line CL, a first gate voltage signal line VL1 and a second gate voltage signal line VL2 .
  • two clock signal lines CL are used as examples for illustration.
  • the first gate voltage signal line VL1, the second gate voltage signal line VL2, at least one clock signal line CL and the gate initialization signal line SL are arranged in sequence.
  • the gate signal line 173 is set to the first gate voltage signal line VL1.
  • the short-circuited sub-trace segment 1710 can be cut to solve the short-circuit problem between the transfer line 180 and the gate signal line 170, which facilitates maintenance.
  • a plurality of adapter lines 180 electrically connected to a group of scanning signal lines 150 is a group of adapter lines 180 .
  • the orthographic projection of a set of transfer lines 180 on the substrate 10 overlaps with the orthographic projection of the same hollow area H on the substrate 10 , that is, the orthographic projection of the same first wiring segment 171 on the substrate 10 The projections partially overlap.
  • multiple pixel circuits 130 in the same row of sub-pixels P are electrically connected to two scanning signal lines 150 . That is to say, a group of scanning signal lines 150 includes two scanning signal lines 150 , and a group of switching lines 180 includes two switching lines 180 .
  • the orthographic projections of two of the set of adapter lines 180 on the substrate 10 are the same as the orthographic projections of the same hollow area H on the substrate 10 (see FIG. 10 ). Overlap, that is, overlap with the orthographic projection of the same first trace segment 171 on the substrate 10 (see FIG. 10 ). Arranged in this way, a group of adapter wires 180 can share a first wiring segment 171 for maintenance, which facilitates production and lowers the cost.
  • the display panel 100 sequentially includes a light shielding layer 11 , a first insulating layer 12 , a semiconductor layer 13 , and a gate insulation layer.
  • layer 14 gate conductive layer 15, interlayer insulating layer 16 and source-drain conductive layer 17.
  • the active layer of the transistor of the pixel circuit 130 may be located on the semiconductor layer 13; the gate electrode of the transistor of the pixel circuit 130, the scanning signal line 150, the third conductive block 50 and the gate signal line 170 may be located on the gate conductive layer 15; the first The conductive block 30 , the second conductive block 40 and the fourth conductive block 60 may be located on the light shielding layer 11 .
  • the material of the semiconductor layer 13 includes metal oxide semiconductor materials, such as indium gallium zinc oxide, which can achieve high charge mobility, stability and scalability with low production cost.
  • the above-mentioned light-shielding layer 11 can also include at least one light-shielding block 70, the orthographic projection of the light-shielding block 70 on the substrate 10, and the driving transistor 130 in the pixel circuit ( Figure 5
  • the orthographic projection of the channel area of T2) on the substrate 10 at least partially overlaps to block the channel area of the driving transistor (T2 in FIG. 5) and prevent light from directly irradiating the channel of the driving transistor (T2 in FIG. 5). channel region, causing the threshold voltage of the driving transistor to drift.
  • the display panel 100 may also include a buffer layer BF, a passivation layer PVX, a planarization layer PLN, a pixel definition layer PDL and an encapsulation layer 20.
  • the buffer layer BF is disposed between the light-shielding layer 11 and the substrate 10
  • the passivation layer PVX is disposed on the side of the source-drain conductive layer 17 away from the substrate 10
  • the flat layer PLN is disposed on the side of the passivation layer PVX away from the substrate 10
  • the pixel definition layer PDL is disposed on the side of the flat layer PLN away from the substrate 10
  • the encapsulation layer 20 is disposed on the side of the pixel definition layer PDL away from the substrate 10 .
  • the pixel defining layer PDL is provided with a plurality of openings to define the light-emitting area of the light-emitting device.
  • the encapsulation layer 20 is used to encapsulate the pixel circuit 130 and the light-emitting device 140.
  • the encapsulation layer 20 can be an encapsulation film or an encapsulation substrate, which is not specifically limited in the embodiment of the present disclosure.
  • the display panel 100 includes a scan signal line 150, a scan drive circuit 110, a gate signal line 170, and a transfer line 180.
  • the gate signal line 170 is electrically connected to the scan drive circuit 110.
  • one end of the adapter line 180 is electrically connected to the scanning signal line 150
  • the other end is electrically connected to the scanning driving circuit 110 .
  • the scanning signal line 150 and the gate signal line 170 are arranged on the same layer, the adapter line 180 and the scan signal line 150 are located on different layers, and the orthographic projection of the adapter line 180 on the substrate 10 is the same as the orthogonal projection of the gate signal line 170 on the substrate 10 .
  • the projections partially overlap.
  • the gate signal line 170 includes alternately connected first wiring segments 171 and second wiring segments 172 , and the first wiring segments 171 are disposed on one side of a row of pixel circuits 130 in the first direction X.
  • the first trace segment 171 includes a plurality of parallel sub-trace segments 1710, and both ends of each sub-trace segment 1710 are connected to the adjacent second trace segments 172 on both sides; the multiple sub-trace segments 1710 of the first trace segment 171 are in
  • the orthographic projections on the substrate 10 partially overlap with the orthographic projections of the patch cord 180 on the substrate 10 .
  • the repair method includes S1 to S2.
  • the target sub-trace segment is the sub-trace segment 1710 short-circuited with the transfer line 180 among the plurality of sub-trace segments 1710 of the first trace segment 171 of the gate signal line 170 .

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Abstract

一种显示面板包括衬底、扫描信号线和至少一个第一导电块。扫描信号线设置于衬底上；扫描信号线包括走线主体和至少一个转接垫，转接垫设置于走线主体的端部。至少一个第一导电块与扫描信号线位于不同层，且与扫描信号线电绝缘；第一导电块在衬底上的正投影，与转接垫在衬底上的正投影至少部分交叠。

Description

显示面板及其修复方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及其修复方法、显示装置。
背景技术
随着显示技术的飞速发展，显示装置已经逐渐遍及在人们的生活中。其中，有机发光二极管(Organic Light Emitting Diode，简称：OLED)由于具有自发光、低功耗、宽视角、响应速度快、高对比度以及柔性显示等优点，因而被广泛的应用于手机、电视、笔记本电脑等智能产品中。
发明内容
一方面，提供一种显示面板。所述显示面板包括衬底、扫描信号线和至少一个第一导电块。所述扫描信号线设置于所述衬底上；所述扫描信号线包括走线主体和至少一个转接垫，所述转接垫设置于所述走线主体的端部。所述至少一个第一导电块与所述扫描信号线位于不同层，且与所述扫描信号线电绝缘；所述第一导电块在所述衬底上的正投影，与所述转接垫在所述衬底上的正投影至少部分交叠。
在一些实施例中，所述走线主体大致沿第一方向延伸，所述转接垫在第二方向的尺寸，大于所述走线主体的宽度；所述第二方向与所述第一方向大致垂直。
在一些实施例中，所述显示面板还包括像素电路和至少一个第二导电块。所述像素电路设置与所述衬底上；所述像素电路包括多个晶体管，所述晶体管包括栅极。至少一个第二导电块与所述晶体管的栅极位于不同层，且与所述晶体管的栅极电绝缘；所述第二导电块在所述衬底上的正投影，与所述像素电路中的至少一个晶体管的栅极在所述衬底上的正投影至少部分交叠。
在一些实施例中，所述像素电路包括开关晶体管，所述第二导电块在所述衬底上的正投影，与所述开关晶体管的栅极在所述衬底上的正投影至少部分交叠。
在一些实施例中，所述像素电路包括感测晶体管，所述第二导电块在所述衬底上的正投影，与所述感测晶体管的栅极在所述衬底上的正投影至少部 分交叠。
在一些实施例中，所述晶体管的栅极与所述扫描信号线一体设置。
在一些实施例中，所述显示面板具有显示区和至少部分环绕所述显示区的周边区，所述扫描信号线位于所述显示区。其中，所述显示面板还包括扫描驱动电路、至少一条栅信号线和第三导电块。所述扫描驱动电路设置于所述衬底上，且位于所述周边区。所述至少一条栅信号线与所述扫描信号线同层设置，且位于所述周边区。所述至少一条栅信号线沿第二方向延伸，且与所述扫描驱动电路电连接；所述第二方向与所述扫描信号线的延伸方向大致垂直。所述第三导电块与所述扫描信号线同层设置，且位于所述至少一条栅信号线与所述扫描信号线之间。
在一些实施例中，所述显示面板还包括至少一个第四导电块，所述至少一个第四导电块与所述第三导电块位于不同层，且与所述第三导电块电绝缘；所述第四导电块在所述衬底上的正投影，与至少一个第三导电块在所述衬底上的正投影至少部分交叠。
在一些实施例中，每条所述扫描信号线与所述至少一条栅信号线均设有一个所述第三导电块。所述显示面板还包括多个像素电路，所述多个像素电路排列为多行多列，每行像素电路与多条扫描信号线电连接。与同一行像素电路电连接的多条扫描信号线为一组扫描信号线，位于一组扫描信号线与所述至少一条栅信号线之间的多个第三导电块为一组第三导电块。所述一组第三导电块在所述衬底上的正投影，均与同一个第四导电块在所述衬底上的正投影至少部分交叠。
在一些实施例中，所述的显示面板还包括转接线，所述转接线一端与所述扫描信号线的转接垫电连接，另一端与所述扫描驱动电路电连接；所述转接线与所述扫描信号线位于不同层，且所述转接线在所述衬底上的正投影与至少一条栅信号线在所述衬底上的正投影部分交叠。与所述转接线在所述衬底上的正投影部分交叠的栅信号线中，至少一条栅信号线上设有至少一个镂空区，每个镂空区在所述衬底上的正投影，与至少一条转接线在所述衬底上的正投影部分交叠；且，所述镂空区在所述第二方向上的长度，大于所述转接线在所述第二方向上的宽度。
在一些实施例中，在所述显示区的第一方向上的一侧，最靠近所述显示区的栅信号线为设定栅信号线，所述设定栅信号线在所述衬底上的正投影，与所述转接线在所述衬底上的正投影部分交叠，所述设定栅信号线上设有所述镂空区。
在一些实施例中，所述至少一条栅信号线包括栅初始化信号线、至少一条时钟信号线、第一栅电压信号线和第二栅电压信号线。由所述显示区指向周边区，第一栅电压信号线、所述第二栅电压信号线、所述至少一条时钟信号线和所述栅初始化信号线依次设置；所述设定栅信号线为第一栅电压信号线。
在一些实施例中，所述显示面板包括多个像素电路，所述多个像素电路排列为多行多列，每行像素电路与多条扫描信号线电连接。其中，与同一行像素电路电连接的多条扫描信号线为一组扫描信号线，与一组扫描信号线电连接的多条转接线为一组转接线，一组转接线在所述衬底上的正投影，均与同一个镂空区在所述衬底上的正投影部分交叠。
在一些实施例中，所述镂空区的形状大致为长条形。
在一些实施例中，所述显示面板包括多个像素电路，所述多个像素电路排列为多行多列，每行像素电路与至少一条扫描信号线电连接。与所述转接线在所述衬底上的正投影部分交叠的栅信号线中，至少一条栅信号线包括交替连接的第一走线段和第二走线段，所述第一走线段设置于一行像素电路的第一方向上的一侧；所述第一走线段包括多条并行设置的子走线段，每条子走线段的两端均与两侧相邻的第二走线段连接。所述第一走线段的多条子走线段在所述衬底上的正投影，均与至少一条转接线在所述衬底上的正投影部分交叠。
在一些实施例中，所述转接线在所述衬底上的正投影，与所述第三导电块在所述衬底上的正投影错开设置。
在一些实施例中，所述显示面板包括多个像素电路，所述多个像素电路排列为多行多列，每行像素电路与多条扫描信号线电连接。其中，与同一行像素电路电连接的多条扫描信号线为一组扫描信号线，一组扫描信号线的多个转接垫在所述衬底上的正投影，均与同一个第一导电块在所述衬底上的正投影至少部分交叠。
在一些实施例中，所述显示面板包括第一导电块、第二导电块和第四导电块，所述第一导电块、所述第二导电块和所述第四导电块的材料相同且同层设置。
在一些实施例中，沿垂直所述衬底且远离所述衬底的方向，所述显示面板依次包括遮光层、第一绝缘层、半导体层、栅绝缘层、栅导电层、层间绝缘层和源漏导电层。所述第一导电块、所述第二导电块和所述第四导电块位于所述遮光层。
在一些实施例中，所述像素电路包括驱动晶体管。所述遮光层还包括至少一个遮光块，所述遮光块在所述衬底上的正投影，与所述驱动晶体管的沟道区在所述衬底上的正投影至少部分重合。
在一些实施例中，所述显示面板还包括栅信号线和第三导电块，所述扫描信号线、所述第三导电块和所述栅信号线所述位于所述栅导电层。
在一些实施例中，所述显示面板包括第二导电块、第三导电层、第四导电块和两个扫描驱动电路。所述两个扫描驱动电路设置于所述显示区的第一方向上的相对的两侧，所述第一导电块、所述第二导电块、所述第三导电层和所述第四导电块相对于所述显示区的沿第二方向的中线对称设置；所述第二方向与所述第一方向大致垂直。
另一方面，提供一种显示装置。所述显示装置包括如上述任一实施例所述的显示面板。
又一方面，提供一种显示面板的修复方法。所述显示面板包括扫描信号线、扫描驱动电路、栅信号线和转接线，所述栅信号线与所述扫描驱动电路电连接，所述转接线一端与所述扫描信号线电连接，另一端与所述扫描驱动电路电连接。
所述扫描信号线与所述栅信号线同层设置，所述转接线与所述扫描信号线位于不同层，所述转接线在所述衬底上的正投影与所述栅信号线在所述衬底上的正投影部分交叠；所述栅信号线包括交替连接的第一走线段和第二走线段，所述第一走线段设置于一行像素电路的第一方向上的一侧；所述第一走线段包括多条并行设置的子走线段，每条子走线段的两端均与两侧相邻的第二走线段连接；所述第一走线段的多条子走线段在所述衬底上的正投影，均与所述转接线在所述衬底上的正投影部分交叠。
所述修复方法包括：在所述转接线和所述栅信号线短接时，确定目标子走线段；所述目标子走线段为所述栅信号线的第一走线段的多条子走线段中与所述转接线短接的子走线段。切割所述目标子走线段的两端，以使所述目标子走线段的两端与两侧相邻的第二走线段断开。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等 的限制。
图1为根据一些实施例的一种显示装置的结构图；
图2为根据一些实施例的一种显示面板的结构图；
图3为根据一些实施例的另一种显示面板的结构图；
图4为根据一些实施例的另一种显示面板的剖视图；
图5为根据一些实施例的子像素的电路图；
图6为图5所示的子像素的电路的时序图；
图7为根据一些实施例的一种显示面板的结构图；
图8为根据一些实施例的又一种显示面板的结构图；
图9为8所示的显示面板的电路走线图；
图10为图9中沿A-A＇处的剖视图；
图11为图9中沿B-B＇处的剖视图；
图12为根据一些实施例的显示面板的修复方法的流程图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。例如，描述 一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。这里所公开的实施例并不必然限制于本公开内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本公开中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本公开所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本公开所使用的那样，“平行”、“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本公开参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本公开示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设 备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
在一些实施例中，各晶体管的控制极为晶体管的栅极，晶体管的第一极为晶体管的源极和漏极中一者，晶体管的第二极为晶体管的源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性的，在晶体管为P型晶体管的情况下，晶体管的第一极为源极，第二极为漏极；示例性的，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
在本公开中，“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板对膜层通过一次构图工艺形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形的膜层可以是连续的也可以是不连续的，这些特定图形的膜层还可能处于不同的高度或者具有不同的厚度。
如图1所示，本公开的一些实施例提供一种显示装置1000，该显示装置1000可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。示例性地，该显示装置1000可以为电视机、笔记本电脑、平板电脑、手机、个人数字助理(Personal Digital Assistant；简称：PDA)、导航仪、可穿戴设备、虚拟现实(Virtual Reality；简称：VR)设备等任何具有显示功能的产品或者部件。
在一些实施例中，参阅图1，显示装置1000包括显示面板100。
示例性地，如图1所示，上述显示装置1000还可以包括壳体200、电路板(图1中未示意出)以及其他电子配件。其中，显示面板100和电路板可以设置在该壳体200内。
其中，上述显示面板100的类型包括多种，可以根据实际需要选择设置。
示例性地，上述显示面板100可以为：有机发光二极管(Organic Light Emitting Diode，简称：OLED)显示面板、量子点发光二极管(Quantum Dot Light Emitting Diode，简称：QLED)显示面板、微发光二极管(Micro Light Emitting Diodes，简称：Micro LED)显示面板等，本公开实施例对此不做具体限定。
下面以上述显示面板100为OLED显示面板为例，对本公开的一些实施例进行示意性说明。
在一些实施例中，如图2和图3所示，上述显示面板100具有显示区A，以及设置在显示区A的至少一侧的周边区B。图2和图3中以周边区B围 绕显示区A设置为例。
其中，如图2和图3所示，显示区A为显示图像的区域，被配置为设置多个子像素P。周边区B为不显示图像的区域，周边区B被配置为设置显示驱动电路和电路走线，例如，扫描驱动电路110、源极驱动电路120以及栅信号线170。
在一些实施例中，如图2和图3所示，显示面板100可以包括衬底10、扫描驱动电路110和至少一条栅信号线170。
参阅图2和图3，扫描驱动电路110和栅信号线170设置于衬底10上，栅信号线170与扫描驱动电路110电连接，且栅信号线170被配置为向扫描驱动电路110提供控制信号。该控制信号包括第一栅电压信号VGL、第二控制信号VGH、初始化信号STV和时钟信号中的至少一种。
其中，上述衬底10的类型包括多种，可以根据实际需要选择设置。
示例性地，衬底10可以为刚性衬底。例如，该刚性衬底可以为玻璃衬底或PMMA(Polymethyl Methacrylate，聚甲基丙烯酸甲酯)衬底等。
示例性地，衬底10可以为柔性衬底。例如，该柔性衬底可以为聚对苯二甲酸乙二醇酯(Polyethylene Terephthalate，简称：PET)衬底、聚萘二甲酸乙二醇酯(Polyethylene Naphthalate Two Formic Acid Glycol Ester，简称：PEN)衬底或聚酰亚胺(Polyimide，简称：PI)衬底等。
在一些实施例中，如图2和图3所示，上述显示面板100还可以包括多个子像素P，多个子像素P与扫描驱动电路110设置于衬底10的同一侧，且位于显示区A。具体的，子像素P所包括的部件可以参照图4和图5所示。
参阅图4和图5，每个子像素P可以包括设置在衬底10上的像素电路130及与该像素电路130电连接的发光器件140。
如图4和图5所示，像素电路130包括多个晶体管131。晶体管131包括有源层1311、源极1312、漏极1313和栅极1314，源极1312和漏极1313分别与有源层1311接触。
如图4和图5所示，发光器件140包括第一电极层141、发光功能层142以及第二电极层143，第一电极层141和多个晶体管131中作为驱动晶体管的晶体管131的源极1312或漏极1313电连接。图4中以第一电极层141和晶体管131的漏极1313电连接进行示意。
需要说明的是，上述源极1212和漏极1213可以互换，即图4中的1312表示漏极，图4中的1313表示源极。
其中，参阅图2和图3，多个子像素P可以排列为多行多列，每行包括 沿第一方向X排列的多个子像素P，每列包括沿第二方向Y排列的多个子像素P，第一方向X和第二方向Y大致垂直。
在此基础上，如图2和图3所示，上述显示面板100还可以包括大致沿第一方向X延伸的至少一条扫描信号线150，以及大致沿第二方向Y延伸的至少一条数据线160。其中，扫描信号线150与扫描驱动电路110电连接，数据线160与源极驱动电路120电连接。
此时，如图2、图3和图5所示，同一行子像素P的像素电路130可以与大致沿第一方向X延伸的扫描信号线150电连接，同一列子像素P的像素电路130可以与一条数据线160电连接。
在一些实施例中，参阅图7和图8，扫描驱动电路110仅包括栅极驱动电路111，扫描信号线150仅包括栅扫描信号线GL，栅扫描信号线GL被配置为传输扫描信号Gate和/或复位信号Reset。
在另一些实施例中，扫描驱动电路110除包括栅极驱动电路111，还包括发光驱动电路；此时，扫描信号线150除包括栅扫描信号线GL外，还包括使能信号线，使能信号线被配置为传输使能信号Em。
应理解，像素电路130的结构包括多种，可以根据实际需要选择设置。例如，像素电路130的结构可以包括“2T1C”、“3T1C”、“6T1C”、“7T1C”、“8T1C”、“6T2C”或“7T2C”等结构。其中，“T”表示为晶体管，位于“T”前面的数字表示为晶体管的数量，“C”表示为存储电容器，位于“C”前面的数字表示为存储电容器的数量。
此外，在显示面板100使用的过程中，像素电路130中的晶体管及发光器件140的稳定性可能会下降(例如驱动晶体管的阈值电压漂移)，影响显示面板100的显示效果，这样便需要对子像素P进行补偿。
对子像素P进行补偿的方式可以包括多种，可以根据实际需要选择设置。例如，可以在子像素P中设置像素补偿电路，以利用该像素补偿电路对子像素P进行内部补偿。又如，可以通过子像素P内部的晶体管对驱动晶体管或发光器件进行感测，并将感测到的数据传输到外部感应电路，以利用该外部感应电路计算需要补偿的驱动电压值并进行反馈，从而实现对子像素P的外部补偿。
本公开以采用外部补偿的方式(对驱动晶体管进行感测)，且像素电路采用“3T1C”的结构为例，对子像素P的结构及工作过程进行示意性说明。并且，在下面的描述中，像素电路130为位于第N行子像素P中的像素电路130中的任一个；其中，N为正整数。
在这种情况下，如图6和图7所示，扫描驱动电路110仅包括栅极驱动电路111，上述扫描信号线150仅包括栅扫描信号线GL。在不同的时段，栅扫描信号线GL可以分别传输扫描信号Gate和复位信号Reset，具体可以参考下文。
如图5所示，在3T1C像素电路130中，像素电路130可以包括：第一晶体管T1、第二晶体管T2、第三晶体管T3和存储电容器Cst。
如图5所示，第一晶体管T1的控制极与第一扫描信号端G1电连接，第一晶体管T1的第一极与数据信号端DATA电连接，第一晶体管T1的第二极与第一节点N1电连接。其中，第一晶体管T1被配置为，响应于在第一扫描信号端G1处接收的第一扫描信号，将在数据信号端DATA处接收的数据信号传输至第一节点N1。
此处，数据信号例如可以包括检测数据信号和显示数据信号。其中，检测数据信号用在消隐时段，显示数据信号用在显示时段。关于显示时段和消隐时段，可以参照下面一些实施例中的说明，此处不再赘述。
如图5所示，第二晶体管T2的控制极与第一节点N1电连接，第二晶体管T2的第一极与第一电压信号端ELVDD电连接，第二晶体管T2的第二极与第二节点N2电连接。其中，第二晶体管T2被配置为，在第一节点N1的电压的控制下，将在第一电压信号端ELVDD处接收的电压信号传输至第二节点N2。
如图5所示，存储电容器Cst的第一端与第一节点N1电连接，存储电容器Cst的第二端与第二节点N2电连接。其中，第一晶体管T1在对第一节点N1进行充电的过程中，同时对存储电容器Cst进行充电。
如图5所示，发光器件140的阳极与第二节点N2电连接，发光器件140的阴极与第二电压信号端ELVSS电连接。发光器件140被配置为，在来自第二节点N2处的电压信号和第二电压信号端ELVSS所传输的电压信号的相互配合下，进行发光。
如图5所示，第三晶体管T3的控制极与第二扫描信号端G2电连接，第三晶体管T3的第一极与感测信号端SENSE电连接，第三晶体管T3的第二极与第二节点N2电连接。其中，第三晶体管T3被配置为，响应于在第二扫描信号端G2处接收的第二扫描信号，检测第二晶体管T2的电特性以实现外部补偿。该电特性可以包括第二晶体管T2的阈值电压和/或载流子迁移率。
此处，感测信号端SENSE可以提供复位信号或获取感测信号，其中， 复位信号用于对第二节点N2进行复位，感测信号用于获取第二晶体管T2的阈值电压。
需要说明的是，图5所示的电路中，节点N1和N2并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点，也就是说，这些节点是由电路图中相关电连接的汇合点等效而成的节点。
基于上述像素电路130的结构，一个帧周期可以包括依次进行的显示时段和消隐时段。在显示时段，子像素P进行图像显示。在消隐时段，子像素P进行外部补偿。下面仅对其中的显示时段进行示意性说明。
在显示时段，如图5和图6所示，子像素P的工作过程例如可以包括复位阶段P1、数据写入阶段P2和发光阶段P3。
在复位阶段P1中，第二扫描信号端G2所提供的第二扫描信号的电平为高电平，感测信号端SENSE提供复位信号(该复位信号的电平例如为低电平)。第三晶体管T3在第二扫描信号的控制下导通，接收复位信号，并将该复位信号传输至第二节点N2，对第二节点N2进行复位。
在数据写入阶段P2中，第一扫描信号端G1所提供的第一扫描信号的电平为高电平，数据信号端DATA所提供的显示数据信号的电平为高电平。第一晶体管T1在第一扫描信号的控制下导通，接收显示数据信号，并将该显示数据信号传输至第一节点N1，同时对存储电容器Cst进行充电。
在发光阶段P3中，第一扫描信号端G1所提供的第一扫描信号的电平为低电平，第二扫描信号端G2所提供的第二扫描信号的电平为低电平，第一电压信号端ELVDD所提供的电压信号的电平为高电平。
此时，第一晶体管T1在第一扫描信号的控制下关断，第三晶体管T3在第二扫描信号的控制下关断。存储电容器Cst开始放电，使得第一节点N1的电压保持为高电平。第二晶体管T2在第一节点N1的电压的控制下导通，接收来自第一电压信号端ELVDD的电压信号，并将该电压信号传输至第二节点N2，使得发光器件140在第二节点N2的电压信号和第二电压信号端ELVSS的电压信号的相互配合下，进行发光。
基于上述像素电路130的结构及第一扫描信号和第二扫描信号的时序，参阅图2和图5，同一行子像素P中的多个像素电路130可以与同一条扫描信号线150电连接，参阅图3和图5，同一行子像素P中的多个像素电路130也可以与两条扫描信号线150电连接。
示例性地，如图5和图7所示，同一行子像素P中的多个像素电路130与两条栅扫描信号线GL，两条栅扫描信号线GL可以包括第一栅扫描信号 线GL1和第二栅扫描信号线GL2。
参阅图5和图7，第一栅扫描信号线GL1与第N行的子像素P中的多个像素电路130的第一扫描信号端G1电连接，即与第一晶体管T1的控制极电连接；第一栅扫描信号线GL1被配置为，传输第一扫描信号。
参阅图5和图7，第二栅扫描信号线GL2与第N行的子像素P中的多个像素电路130的第二扫描信号端G2电连接，即与第三晶体管T3的控制极电连接；第二栅扫描信号线GL2被配置为，传输第二扫描信号。
但是，相关技术中，在制作显示面板的过程中，电荷会在扫描信号线聚集，形成静电。当电荷积累到一定程度，就会形成放电，即静电放电(Electro Static Discharge，简称为ESD)。其中，放电的过程会将绝缘膜层击穿，导致不同层的导电层之间产生短接。例如，扫描信号线与周边区的栅信号线(第一栅电压信号线或第二栅电压信号线等)短接，从而造成显示面板上产生横向暗线；又例如，扫描信号线与晶体管的沟道区短接，从而造成显示面板上产生竖向暗线。
需要说明的是，参阅图4，晶体管131的沟道区可以是，晶体管131的有源层1311中，有源层1311在衬底10上的正投影与晶体管131的栅极1314在衬底10上的正投影交叠的部分。
基于此，如图8、图9和图10所示，本公开的一些实施例提供一种显示面板100，还包括至少一个第一导电块30，第一导电块30与扫描信号线150位于不同层，且与扫描信号线150电绝缘。
其中，如图8和图9所示，扫描信号线150包括走线主体151和至少一个转接垫152，转接垫152设置于走线主体151的端部。这里，转接垫152可以被配置为，连接位于其他膜层的转接线180，并通过该转接线180与扫描驱动电路110电连接。
示例性地，参阅图8、图9和图10，扫描信号线150与上述栅信号线170同层设置，扫描信号线大致沿第一方向X延伸，栅信号线170大致沿第二方向Y延伸，且至少一条栅信号线170位于扫描驱动电路110靠近显示区A的一侧。
此时，显示面板100还包括转接线180，转接线180一端与扫描信号线150的转接垫152电连接，另一端与扫描驱动电路110电连接，以使得扫描信号线150与扫描驱动电路110电连接。其中，转接线180与扫描信号线150位于不同层，且转接线180在衬底10上的正投影与至少一条栅信号线170在衬底10上的正投影部分交叠。
在此基础上，如图9所示，上述走线主体151大致沿第一方向X延伸，转接垫152在第二方向Y的尺寸，可以大于走线主体151的宽度，以便于转接线180与转接垫152的连接。
其中，转接垫152的数量，取决于扫描信号线150采用单侧驱动或双侧的方式。
示例性地，如图9所示，在扫描信号线150采用图7所示的单侧驱动的方式的情况下，扫描信号线150包括走线主体151(参见图9)和一个转接垫152(参见图9)，转接垫152(参见图9)设置于走线主体151(参见图9)靠近扫描驱动电路110的一端，并通过转接线180与扫描驱动电路110电连接。以这种方式设置，可以缩减显示面板100的周边区B的尺寸以及减小显示面板100的制备成本。
需要说明的是，扫描信号线150采用单侧驱动的方式指的是，显示面板100包括一个扫描驱动电路110，扫描驱动电路110设置于显示区A的第一方向(扫描信号线150的延伸方向)上的一侧，逐行依次驱动各扫描信号线150。
示例性地，参阅图9，在扫描信号线150采用如图8所示的双侧驱动的方式的情况下，扫描信号线150包括走线主体151和两个转接垫152，两个转接垫152分别设置于走线主体151相对的两端，且分别通过转接线180与对应的扫描驱动电路110电连接。以这种方式设置，可以提高同一行的像素电路130中各个像素电路130，接收的来自扫描信号线150的信号的准确性，减小扫描信号线150的长度所带来的压降的影响。
需要说明的是，扫描信号线150采用双侧驱动的方式指的是，显示面板100包括两个扫描驱动电路110，两个扫描驱动电路110分别设置于显示区A的第一方向(扫描信号线150的延伸方向)上的相对的两侧，通过两个扫描驱动电路110同时从两侧逐行依次驱动各扫描信号线150。
其中，第一导电块30在衬底10上的正投影，与转接垫152在衬底10上的正投影至少部分交叠。
例如，如图9和图10所示，转接垫152在衬底10上的正投影，位于第一导电块30在衬底10上的正投影内，以使得转接垫152与第一导电块30的正对面积最大，进而使得转接垫152与第一导电块30形成的第一电容器的所能存储的电荷量最大。
在这种情况下，第一导电块30与转接垫152相对的部分形成第一电容器。由于第一电容器能够存储电荷，因此，第一电容器能够降低扫描信号线 150的延伸方向的一端或者两端的转接垫152处静电释放的风险，进而降低转接垫152处静电释放导致不同层的导电层之间短接的风险，例如降低扫描信号线150与周边区B的栅信号线170短接的风险，从而降低显示面板100上产生横向暗线的风险。
此外，参阅图8、图9和图10，本公开的一些实施例提供的显示面板100还可以包括至少一个第二导电块40，第二导电块40与晶体管131的栅极1314位于不同层，且与晶体管131的栅极1314电绝缘。
其中，第二导电块40在衬底10上的正投影，与像素电路130中的至少一个晶体管131的栅极1314在衬底10上的正投影至少部分交叠。
示例性地，如图9和图10所示，像素电路130中的至少一个晶体管131的栅极1314在衬底10上的正投影，位于第二导电块40在衬底10上的正投影内，以使得栅极1314与第二导电块40的正对面积最大，进而使得栅极1314与第二导电块40形成的第二电容器的所能存储的电荷量最大。
在这种情况下，第二导电块40与晶体管131的栅极1314相对的部分形成第二电容器。由于第二电容器能够存储电荷，因此，第二电容器能够降低晶体管131的栅极1314静电释放的风险，进而降低晶体管131的栅极1314静电释放导致不同层的导电层之间短接的风险，例如降低晶体管131的栅极1314与晶体管131的沟道区短接的风险，从而降低显示面板100上产生竖向暗线的风险。
需要说明的是，晶体管131的栅极1314可以与扫描信号线150一体设置。
示例性地，参阅图5、图9和图10，像素电路130包括开关晶体管(图5中的T1)，第二导电块40在衬底10上的正投影，与开关晶体管的栅极1314在衬底10上的正投影至少部分交叠。
例如，如图9和图10所示，开关晶体管的栅极1314在衬底10位于第二导电块40在衬底10的正投影内。以使得开关晶体管的栅极1314与第二导电块40的正对面积最大，进而使得开关晶体管的栅极1314与第二导电块40形成的第二电容器的所能存储的电荷量最大，降低开关晶体管的栅极1314与沟道区短接的风险。
其中，开关晶体管的栅极1314可以与扫描信号线150一体设置。
示例性地，如图8、图9和图10所示，在上述3T1C的像素电路130结构中，第一晶体管T1为开关晶体管。其中，扫描信号线150包括第一栅扫描信号线GL1，第一栅扫描信号线GL1与像素电路130的第一扫描信号端 G1电连接，即第一栅扫描信号线GL1位于第一晶体管T1的有源层1311上方的部分，可以直接作为第一晶体管T1的栅极1314。此时，第一晶体管T1的栅极1314与第一栅扫描信号线GL1一体设置。
在一些实施例中，参阅图5、图8和图9，像素电路130采用外部补偿的方式，即像素电路130还包括感测晶体管(图5中的T3)，第二导电块40在衬底10上的正投影，与感测晶体管的栅极1314在衬底10上的正投影至少部分交叠。
例如，如图9和图10所示，感测晶体管的栅极1314在衬底10位于第二导电块40在衬底10的正投影内。以使得感测晶体管的栅极1314与第二导电块40的正对面积最大，进而使得感测晶体管的栅极1314与第二导电块40形成的第二电容器的所能存储的电荷量最大，降低感测晶体管的栅极1314与沟道区短接的风险。
其中，感测晶体管的栅极1314可以与扫描信号线150一体设置。
示例性地，如图5、图8和图9所示，在上述3T1C的像素电路130结构中，第三晶体管T3为感测晶体管。其中，扫描信号线150包括第二栅扫描信号线GL2，第二栅扫描信号线GL2与像素电路130的第二扫描信号端G2电连接，即第二栅扫描信号线GL2位于第三晶体管T3的有源层1311上方的部分，可以直接作为第三晶体管T3的栅极1314。此时，第三晶体管T3的栅极1314与第二栅扫描信号线GL2一体设置。
在一些实施例中，参阅图8、图9和图10，上述显示面板100还可以包括至少一个第三导电块50，第三导电块50与扫描信号线150同层设置，且位于栅信号线170与扫描信号线150之间。
示例性地，如图8和图9和图10所示，显示面板100还包括多个第三导电块50，每条扫描信号线150与栅信号线170之间均对应设置有一个第三导电块50。
在这种情况下，栅信号线170与扫描信号线150之间均设有一个第三导电块50，且第三导电块50并未与其他电路形成连接，即第三导电块50处于浮空状态。这样的话，扫描信号线150或转接线180与栅信号线170短接至少需要经过两次静电释放，因此，可以降低栅信号线170与扫描信号线150短接的风险。
需要说明是，第一次静电释放可以为，扫描信号线150的转接垫152处静电释放，导致扫描信号线150或转接线180与第三导电块50电连接；第二次静电释放可以为，第三导电块50处静电释放，导致第三导电块50与栅 信号线170短接，进而导致扫描信号线150或转接线180与栅信号线170短接。
在一些实施例中，参阅图9和图10，上述转接线180在衬底10上的正投影，与第三导电块50在衬底10上的正投影错开设置，以降低转接线180与第三导电块50短接的风险。
此外，参阅图8、图9和图10，显示面板100还可以包括至少一个第四导电块60，第四导电块60与第三导电块50位于不同层，且与第三导电块50电绝缘。第四导电块60在衬底10上的正投影，与至少一个第三导电块50在衬底10上的正投影至少部分交叠。
例如，如图9和图10所示，第三导电块50在衬底10上的正投影，位于第四导电块60在衬底10上的正投影内，以使得第三导电块50与第四导电块60的正对面积最大，进而使得第三导电块50与第四导电块60形成的第三电容器的所能存储的电荷量最大。
在这种情况下，第三导电块50与第四导电块60相对的部分形成第三电容器。由于第三电容器能够存储电荷，因此，第三电容器能够降低第三导电块50处静电释放的风险，也即降低产生第二次静电释放的风险，从而降低扫描信号线150与栅信号线170短接的风险。
需要说明的是，参阅图10，第一导电块30、第二导电块40和第四导电块60的材料相同且同层设置，第一导电块30、第二导电块40和第四导电块60具体所在膜层可以参考下文，本公开实施例在此不做赘述。
此外，如图8和图9所示，在扫描信号线150采用双侧驱动的方式的情况下，两个扫描驱动电路110设置于显示区A的第一方向X上的相对的两侧，第一导电块30、第二导电块40、第三导电块50和第四导电块60相对于显示区A的沿第二方向Y的中线L对称设置。
可以理解的是，基于像素电路130的结构，参阅图2、图3和图5，同一行子像素P中的多个像素电路130可以与一条扫描信号线150电连接，也可以与多条扫描信号线150电连接。
示例性地，参阅图3、图8和图9，每行像素电路130与多条扫描信号线150电连接。其中，与同一行像素电路130电连接的多条扫描信号线150为一组扫描信号线150，位于一组扫描信号线150与栅信号线170之间的多个第三导电块50为一组第三导电块50。
例如，如图8和图9所示，在上述3T1C的像素电路130中，同一行子像素P中的多个像素电路130与两条扫描信号线150电连接。也就是说，一 组扫描信号线150包括两条扫描信号线150，一组第三导电块50包括两个第三导电块50。
其中，如图9和图10所示，一组第三导电块50在衬底10上的正投影，均与同一个第四导电块60在衬底10上的正投影至少部分交叠。以这种方式设置，一组第三导电块50可以共用一块第四导电块60，便于制作，成本较低。
此外，如图9和图10所示，一组扫描信号线150的多个转接垫152在衬底10上的正投影，均与同一个第一导电块30在衬底10上的正投影至少部分交叠。以这种方式设置，一组扫描信号线150的多个转接垫152可以共用一块第一导电块30，便于制作，成本较低。
在一些实施例中，参阅图8、图9和图10，与转接线180在衬底10上的正投影部分交叠的栅信号线170中，至少一条栅信号线170上设有至少一个镂空区H。每个镂空区H在衬底10上的正投影，与至少一条转接线180在衬底10上的正投影部分交叠；且，镂空区H在第二方向Y上的长度，大于转接线180在第二方向Y上的宽度。其中，上述镂空区H的形状可以大致为长条形。
也就是说，如图9和图10所示，与转接线180在衬底10上的正投影部分交叠的栅信号线170中，至少一条栅信号线170包括交替连接的第一走线段171和第二走线段172，第一走线段171设置于一行像素电路130的第一方向X上的一侧。第一走线段171包括多条并行设置的子走线段1710，每条子走线段1710的两端均与两侧相邻的第二走线段172连接。其中，第一走线段171的多条子走线段1710在衬底10上的正投影，均与至少一条转接线180在衬底10上的正投影部分交叠。
示例性地，参阅图8和图9，在显示区A的第一方向X上的一侧，最靠近显示区A的栅信号线170为设定栅信号线173，设定栅信号线173在衬底10上的正投影，与转接线180在衬底10(参见图10)上的正投影部分交叠，设定栅信号线173上设有镂空区H。也即设定栅信号线173包括交替连接的第一走线段171和第二走线段172。
例如，如图7、图8和图9所示，至少一条栅信号线170包括栅初始化信号线SL、至少一条时钟信号线CL、第一栅电压信号线VL1和第二栅电压信号线VL2。图7、图8和图9中以两条时钟信号线CL为例进行示意。
其中，由显示区A指向周边区B，第一栅电压信号线VL1、第二栅电压信号线VL2、至少一条时钟信号线CL和栅初始化信号线SL依次设置。 此时，设定栅信号线173为第一栅电压信号线VL1。
在这种情况下，在转接线180与多条子走线段1710中的一条短接后，可以通过切割短路的子走线段1710，即可解决转接线180与栅信号线170短路问题，利于维修。
其中，参阅图8和图9，与一组扫描信号线150电连接的多条转接线180为一组转接线180。一组转接线180在衬底10上的正投影，均与同一个镂空区H在衬底10上的正投影部分交叠，也即与同一个第一走线段171在衬底10上的正投影部分交叠。
示例性地，如图8和图9所示，在上述3T1C的像素电路130中，同一行子像素P中的多个像素电路130与两条扫描信号线150电连接。也就是说，一组扫描信号线150包括两条扫描信号线150，一组转接线180包括两条转接线180。
此时，一组转接线180中的两条转接线180在衬底10(参见图10)上的正投影，均与同一个镂空区H在衬底10(参见图10)上的正投影部分交叠，也即与同一个第一走线段171在衬底10(参见图10)上的正投影部分交叠。以这种方式设置，一组转接线180可以共用一个第一走线段171进行维修，便于制作，成本较低。
在一些实施例中，参阅图8、图9和图10，沿垂直衬底10且远离衬底10的方向，显示面板100依次包括遮光层11、第一绝缘层12、半导体层13、栅绝缘层14、栅导电层15、层间绝缘层16和源漏导电层17。
这里，像素电路130的晶体管的有源层可以位于半导体层13；像素电路130的晶体管的栅极、扫描信号线150、第三导电块50和栅信号线170可以位于栅导电层15；第一导电块30、第二导电块40和第四导电块60可以位于遮光层11。
需要说明的是，半导体层13的材料包括金属氧化物半导体材料，例如，铟镓锌氧化物，这样可以以低生产成本实现高的电荷迁移率、稳定性和可扩展性。
在此基础上，参阅图9和图11，上述遮光层11还可以包括至少一个遮光块70，遮光块70在衬底10上的正投影，与像素电路中130的驱动晶体管(图5中的T2)的沟道区在衬底10上的正投影至少部分重合，以遮挡驱动晶体管(图5中的T2)的沟道区，避免光线直接照射到驱动晶体管(图5中的T2)的沟道区，而导致驱动晶体管的阈值电压产生漂移。
需要说明的是，如图4、图10和图11所示，显示面板100还可以包括 缓冲层BF、钝化层PVX、平坦层PLN、像素界定层PDL和封装层20。
其中，缓冲层BF设置于遮光层11和衬底10之间，钝化层PVX设置于源漏导电层17远离衬底10的一侧，平坦层PLN设置于钝化层PVX远离衬底10的一侧，像素界定层PDL设置于平坦层PLN远离衬底10的一侧，封装层20设置于像素界定层PDL远离衬底10的一侧。
需要说明的是，像素界定层PDL设置又多个开口，以限定发光器件的发光区。封装层20用于封装像素电路130及发光器件140，该封装层20可以为封装薄膜也可以为封装基板，本公开实施例不做具体限定。
本公开的一些实施例提供一种显示面板的修复方法，该显示面板100包括扫描信号线150、扫描驱动电路110、栅信号线170和转接线180，栅信号线170与扫描驱动电路110电连接，转接线180一端与扫描信号线150电连接，另一端与扫描驱动电路110电连接。
其中，扫描信号线150与栅信号线170同层设置，转接线180与扫描信号线150位于不同层，转接线180在衬底10上的正投影与栅信号线170在衬底10上的正投影部分交叠。
这里，栅信号线170包括交替连接的第一走线段171和第二走线段172，第一走线段171设置于一行像素电路130的第一方向X上的一侧。第一走线段171包括多条并行设置的子走线段1710，每条子走线段1710的两端均与两侧相邻的第二走线段172连接；第一走线段171的多条子走线段1710在衬底10上的正投影，均与转接线180在衬底10上的正投影部分交叠。
基于上述显示面板100的结构，参阅图12，该修复方法包括S1～S2。
S1：在转接线180和栅信号线170短接时，确定目标子走线段。
上述步骤中，目标子走线段为栅信号线170的第一走线段171的多条子走线段1710中与转接线180短接的子走线段1710。
S2：切割目标子走线段的两端，以使目标子走线段的两端与两侧相邻的第二走线段172断开。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (24)

  1. 一种显示面板，包括：
    衬底；
    扫描信号线，设置于所述衬底上；所述扫描信号线包括走线主体和至少一个转接垫，所述转接垫设置于所述走线主体的端部；
    至少一个第一导电块，与所述扫描信号线位于不同层，且与所述扫描信号线电绝缘；所述第一导电块在所述衬底上的正投影，与所述转接垫在所述衬底上的正投影至少部分交叠。
  2. 根据权利要求1所述的显示面板，其中，所述走线主体大致沿第一方向延伸，所述转接垫在第二方向的尺寸，大于所述走线主体的宽度；所述第二方向与所述第一方向大致垂直。
  3. 根据权利要求1或2所述的显示面板，还包括：
    像素电路，设置与所述衬底上；所述像素电路包括多个晶体管，所述晶体管包括栅极；
    至少一个第二导电块，与所述晶体管的栅极位于不同层，且与所述晶体管的栅极电绝缘；所述第二导电块在所述衬底上的正投影，与所述像素电路中的至少一个晶体管的栅极在所述衬底上的正投影至少部分交叠。
  4. 根据权利要求3所述的显示面板，其中，所述像素电路包括开关晶体管，所述第二导电块在所述衬底上的正投影，与所述开关晶体管的栅极在所述衬底上的正投影至少部分交叠。
  5. 根据权利要求3或4所述的显示面板，其中，所述像素电路包括感测晶体管，所述第二导电块在所述衬底上的正投影，与所述感测晶体管的栅极在所述衬底上的正投影至少部分交叠。
  6. 根据权利要求3～5中任一项所述的显示面板，其中，所述晶体管的栅极与所述扫描信号线一体设置。
  7. 根据权利要求1～6中任一项所述的显示面板，具有显示区和至少部分环绕所述显示区的周边区，所述扫描信号线位于所述显示区；其中，所述显示面板还包括：
    扫描驱动电路，设置于所述衬底上，且位于所述周边区；
    至少一条栅信号线，与所述扫描信号线同层设置，且位于所述周边区；所述至少一条栅信号线沿第二方向延伸，且与所述扫描驱动电路电连接；所述第二方向与所述扫描信号线的延伸方向大致垂直；
    第三导电块，与所述扫描信号线同层设置，且位于所述至少一条栅信号线与所述扫描信号线之间。
  8. 根据权利要求7所述的显示面板，还包括：
    至少一个第四导电块，与所述第三导电块位于不同层，且与所述第三导电块电绝缘；所述第四导电块在所述衬底上的正投影，与至少一个第三导电块在所述衬底上的正投影至少部分交叠。
  9. 根据权利要求8所述的显示面板，其中，每条所述扫描信号线与所述至少一条栅信号线均设有一个所述第三导电块；所述显示面板还包括多个像素电路，所述多个像素电路排列为多行多列，每行像素电路与多条扫描信号线电连接；
    与同一行像素电路电连接的多条扫描信号线为一组扫描信号线，位于一组扫描信号线与所述至少一条栅信号线之间的多个第三导电块为一组第三导电块；
    所述一组第三导电块在所述衬底上的正投影，均与同一个第四导电块在所述衬底上的正投影至少部分交叠。
  10. 根据权利要求7～9中任一项所述的显示面板，还包括：
    转接线，所述转接线一端与所述扫描信号线的转接垫电连接，另一端与所述扫描驱动电路电连接；所述转接线与所述扫描信号线位于不同层，且所述转接线在所述衬底上的正投影与至少一条栅信号线在所述衬底上的正投影部分交叠；
    与所述转接线在所述衬底上的正投影部分交叠的栅信号线中，至少一条栅信号线上设有至少一个镂空区，每个镂空区在所述衬底上的正投影，与至少一条转接线在所述衬底上的正投影部分交叠；且，所述镂空区在所述第二方向上的长度，大于所述转接线在所述第二方向上的宽度。
  11. 根据权利要求10所述的显示面板，其中，在所述显示区的第一方向上的一侧，最靠近所述显示区的栅信号线为设定栅信号线，所述设定栅信号线在所述衬底上的正投影，与所述转接线在所述衬底上的正投影部分交叠，所述设定栅信号线上设有所述镂空区。
  12. 根据权利要求11所述的显示面板，其中，所述至少一条栅信号线包括栅初始化信号线、至少一条时钟信号线、第一栅电压信号线和第二栅电压信号线；
    由所述显示区指向周边区，第一栅电压信号线、所述第二栅电压信号线、所述至少一条时钟信号线和所述栅初始化信号线依次设置；所述设定栅信号线为第一栅电压信号线。
  13. 根据权利要求10～12中任一项所述的显示面板，包括多个像素电路， 所述多个像素电路排列为多行多列，每行像素电路与多条扫描信号线电连接；
    其中，与同一行像素电路电连接的多条扫描信号线为一组扫描信号线，与一组扫描信号线电连接的多条转接线为一组转接线，一组转接线在所述衬底上的正投影，均与同一个镂空区在所述衬底上的正投影部分交叠。
  14. 根据权利要求10～13中任一项所述的显示面板，其中，所述镂空区的形状大致为长条形。
  15. 根据权利要求10～14中任一项所述的显示面板，包括多个像素电路，所述多个像素电路排列为多行多列，每行像素电路与至少一条扫描信号线电连接；
    与所述转接线在所述衬底上的正投影部分交叠的栅信号线中，至少一条栅信号线包括交替连接的第一走线段和第二走线段，所述第一走线段设置于一行像素电路的第一方向上的一侧；所述第一走线段包括多条并行设置的子走线段，每条子走线段的两端均与两侧相邻的第二走线段连接；
    所述第一走线段的多条子走线段在所述衬底上的正投影，均与至少一条转接线在所述衬底上的正投影部分交叠。
  16. 根据权利要求9～15中任一项所述的显示面板，其中，所述转接线在所述衬底上的正投影，与所述第三导电块在所述衬底上的正投影错开设置。
  17. 根据权利要求1～11中任一项所述的显示面板，包括多个像素电路，所述多个像素电路排列为多行多列，每行像素电路与多条扫描信号线电连接；
    其中，与同一行像素电路电连接的多条扫描信号线为一组扫描信号线，一组扫描信号线的多个转接垫在所述衬底上的正投影，均与同一个第一导电块在所述衬底上的正投影至少部分交叠。
  18. 根据权利要求1～17中任一项所述的显示面板，包括第一导电块、第二导电块和第四导电块，所述第一导电块、所述第二导电块和所述第四导电块的材料相同且同层设置。
  19. 根据权利要求18所述的显示面板，其中，沿垂直所述衬底且远离所述衬底的方向，所述显示面板依次包括遮光层、第一绝缘层、半导体层、栅绝缘层、栅导电层、层间绝缘层和源漏导电层；
    所述第一导电块、所述第二导电块和所述第四导电块位于所述遮光层。
  20. 根据权利要求19所述的显示面板，其中，所述像素电路包括驱动 晶体管；
    所述遮光层还包括：
    至少一个遮光块，所述遮光块在所述衬底上的正投影，与所述驱动晶体管的沟道区在所述衬底上的正投影至少部分重合。
  21. 根据权利要求19或20所述的显示面板，还包括栅信号线和第三导电块，所述扫描信号线、所述第三导电块和所述栅信号线所述位于所述栅导电层。
  22. 根据权利要求1～21中任一项所述的显示面板，包括第二导电块、第三导电层、第四导电块和两个扫描驱动电路；
    所述两个扫描驱动电路设置于所述显示区的第一方向上的相对的两侧，所述第一导电块、所述第二导电块、所述第三导电层和所述第四导电块相对于所述显示区的沿第二方向的中线对称设置；所述第二方向与所述第一方向大致垂直。
  23. 一种显示装置，包括如权利要求1～22中任一项所述的显示面板。
  24. 一种显示面板的修复方法，其中，所述显示面板包括扫描信号线、扫描驱动电路、栅信号线和转接线，所述栅信号线与所述扫描驱动电路电连接，所述转接线一端与所述扫描信号线电连接，另一端与所述扫描驱动电路电连接；
    所述扫描信号线与所述栅信号线同层设置，所述转接线与所述扫描信号线位于不同层，所述转接线在所述衬底上的正投影与所述栅信号线在所述衬底上的正投影部分交叠；所述栅信号线包括交替连接的第一走线段和第二走线段，所述第一走线段设置于一行像素电路的第一方向上的一侧；所述第一走线段包括多条并行设置的子走线段，每条子走线段的两端均与两侧相邻的第二走线段连接；所述第一走线段的多条子走线段在所述衬底上的正投影，均与所述转接线在所述衬底上的正投影部分交叠；
    所述修复方法包括：
    在所述转接线和所述栅信号线短接时，确定目标子走线段；所述目标子走线段为所述栅信号线的第一走线段的多条子走线段中与所述转接线短接的子走线段；
    切割所述目标子走线段的两端，以使所述目标子走线段的两端与两侧相邻的第二走线段断开。
PCT/CN2022/098244 2022-06-10 2022-06-10 显示面板及其修复方法、显示装置 WO2023236210A1 (zh)

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US20040188681A1 (en) * 2003-03-31 2004-09-30 Han-Chung Lai [pixel structure]
CN108281468A (zh) * 2018-01-23 2018-07-13 京东方科技集团股份有限公司 一种显示基板的制造方法、显示基板、显示装置
CN110928091A (zh) * 2019-12-12 2020-03-27 Tcl华星光电技术有限公司 显示面板及其修复方法、显示装置
CN112614871A (zh) * 2020-11-30 2021-04-06 武汉天马微电子有限公司 显示面板和显示装置
CN114446260A (zh) * 2022-03-24 2022-05-06 北京京东方显示技术有限公司 一种阵列基板及显示装置

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US20040188681A1 (en) * 2003-03-31 2004-09-30 Han-Chung Lai [pixel structure]
CN108281468A (zh) * 2018-01-23 2018-07-13 京东方科技集团股份有限公司 一种显示基板的制造方法、显示基板、显示装置
CN110928091A (zh) * 2019-12-12 2020-03-27 Tcl华星光电技术有限公司 显示面板及其修复方法、显示装置
CN112614871A (zh) * 2020-11-30 2021-04-06 武汉天马微电子有限公司 显示面板和显示装置
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