WO2023115331A9 - 移位寄存器、扫描驱动电路及显示基板 - Google Patents

移位寄存器、扫描驱动电路及显示基板 Download PDF

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Publication number
WO2023115331A9
WO2023115331A9 PCT/CN2021/140079 CN2021140079W WO2023115331A9 WO 2023115331 A9 WO2023115331 A9 WO 2023115331A9 CN 2021140079 W CN2021140079 W CN 2021140079W WO 2023115331 A9 WO2023115331 A9 WO 2023115331A9
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WIPO (PCT)
Prior art keywords
electrically connected
active layer
transistor
signal terminal
electrode
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PCT/CN2021/140079
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English (en)
French (fr)
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WO2023115331A1 (zh
Inventor
杨慧娟
廖茂颖
张波
舒晓青
魏立恒
李灵通
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/140079 priority Critical patent/WO2023115331A1/zh
Priority to CN202180004086.3A priority patent/CN116635939A/zh
Publication of WO2023115331A1 publication Critical patent/WO2023115331A1/zh
Publication of WO2023115331A9 publication Critical patent/WO2023115331A9/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a shift register, a scan driving circuit and a display substrate.
  • OLED Organic Light Emitting Diode
  • a shift register is provided, which is applied to a display substrate.
  • the display substrate includes multiple rows of sub-pixels.
  • the shift register is electrically connected to one row of sub-pixels, and is configured to transmit a scanning signal and a reset signal to the one row of sub-pixels.
  • the shift register includes: a scanning circuit electrically connected to the first input signal terminal, the first clock signal terminal, the second clock signal terminal, the first voltage signal terminal and the second voltage signal terminal;
  • the scanning circuit is It is configured such that the first input signal transmitted by the first input signal terminal, the first clock signal transmitted by the first clock signal terminal, the second clock signal transmitted by the second clock signal terminal, the The scan signal is outputted under the cooperation of the first voltage signal transmitted by the first voltage signal terminal and the second voltage signal transmitted by the second voltage signal terminal; and, the reset circuit and the second input signal terminal , the third clock signal terminal, the fourth clock signal terminal, the third voltage signal terminal and the fourth voltage signal terminal are electrically connected;
  • the reset circuit is configured to: the second input signal transmitted at the second input signal terminal , the third clock signal transmitted by the third clock signal terminal, the fourth clock signal transmitted by the fourth clock signal terminal, the third voltage signal transmitted by the third voltage signal terminal and the fourth With the cooperation of the fourth voltage signal transmitted from the voltage signal terminal, the reset signal is output.
  • the scan circuit includes a first output transistor.
  • the first pole of the first output transistor is electrically connected to the second voltage signal terminal, and the second pole of the first output transistor is electrically connected to the scan signal output terminal.
  • the reset circuit includes: a second output transistor.
  • the first pole of the second output transistor is electrically connected to the fourth voltage signal terminal, and the second pole of the second output transistor is electrically connected to the reset signal output terminal.
  • the channel width of the first output transistor is greater than or equal to the channel width of the second output transistor.
  • the ratio of the channel width of the first output transistor to the channel width of the second output transistor ranges from 1:1 to 20:1.
  • the scan circuit includes: a third output transistor.
  • the first pole of the third output transistor is electrically connected to the second clock signal terminal, and the second pole of the third output transistor is electrically connected to the scan signal output terminal.
  • the reset circuit includes: a fourth output transistor.
  • the first pole of the fourth output transistor is electrically connected to the fourth clock signal terminal, and the second pole of the fourth output transistor is electrically connected to the reset signal output terminal.
  • the channel width of the third output transistor is greater than or equal to the channel width of the fourth output transistor.
  • the ratio of the channel width of the third output transistor to the channel width of the fourth output transistor ranges from 1:1 to 20:1.
  • the scanning circuit and the reset circuit are arranged in parallel along the row direction; or, the scanning circuit and the reset circuit are arranged in a staggered manner along the row direction.
  • the reset circuit is closer to the row of sub-pixels than the scan circuit.
  • the scanning circuit includes: a first input transistor, a second input transistor, a first control transistor, a second control transistor, a third control transistor, a fourth control transistor, a first output transistor, and a third output transistor, first capacitor and second capacitor.
  • the control electrode of the first input transistor is electrically connected to the first clock signal terminal
  • the first electrode of the first input transistor is electrically connected to the first voltage signal terminal
  • the second terminal of the first input transistor is electrically connected to the first clock signal terminal.
  • the pole is electrically connected to the second node.
  • the control electrode of the second input transistor is electrically connected to the first clock signal terminal, the first electrode of the second input transistor is electrically connected to the first input signal terminal, and the second terminal of the second input transistor is electrically connected to the first clock signal terminal.
  • the pole is electrically connected to the first node.
  • the control electrode of the first control transistor is electrically connected to the first node, the first electrode of the first control transistor is electrically connected to the first clock signal terminal, and the second electrode of the first control transistor is electrically connected to The second node is electrically connected.
  • the control electrode of the second control transistor is electrically connected to the second node, the first electrode of the second control transistor is electrically connected to the second voltage signal terminal, and the second electrode of the second control transistor is electrically connected to the second node.
  • the third node is electrically connected.
  • the control electrode of the third control transistor is electrically connected to the second clock signal terminal, the first electrode of the third control transistor is electrically connected to the third node, and the second electrode of the third control transistor is electrically connected to The first node is electrically connected.
  • the control electrode of the fourth control transistor is electrically connected to the first voltage signal terminal, the first electrode of the fourth control transistor is electrically connected to the first node, and the second electrode of the third control transistor is electrically connected to The fourth node is electrically connected.
  • the control electrode of the first output transistor is electrically connected to the second node, the first electrode of the first output transistor is electrically connected to the second voltage signal terminal, and the second electrode of the first output transistor is electrically connected to the second node.
  • the scanning signal output terminal is electrically connected.
  • the control electrode of the third output transistor is electrically connected to the fourth node, the first electrode of the third output transistor is electrically connected to the second clock signal terminal, and the second electrode of the third output transistor is electrically connected to The scanning signal output terminal is electrically connected.
  • the first plate of the first capacitor is electrically connected to the second voltage signal terminal, and the second plate of the first capacitor is electrically connected to the second node.
  • the first plate of the second capacitor is electrically connected to the scan signal output terminal, and the second plate of the second capacitor is electrically connected to the fourth node.
  • the reset circuit includes: a third input transistor, a fourth input transistor, a fifth control transistor, a sixth control transistor, a seventh control transistor, an eighth control transistor, a second output transistor, a fourth output transistor, third capacitor and fourth capacitor.
  • the control electrode of the third input transistor is electrically connected to the third clock signal terminal, the first electrode of the third input transistor is electrically connected to the third voltage signal terminal, and the second electrode of the third input transistor is electrically connected to the third clock signal terminal.
  • the pole is electrically connected to the sixth node.
  • the control electrode of the fourth input transistor is electrically connected to the third clock signal terminal, the first electrode of the fourth input transistor is electrically connected to the second input signal terminal, and the second terminal of the fourth input transistor is electrically connected to the third clock signal terminal.
  • the pole is electrically connected to the fifth node.
  • the control electrode of the fifth control transistor is electrically connected to the fifth node, the first electrode of the fifth control transistor is electrically connected to the third clock signal terminal, and the second electrode of the fifth control transistor is electrically connected to The sixth node is electrically connected.
  • the control electrode of the sixth control transistor is electrically connected to the sixth node, the first electrode of the sixth control transistor is electrically connected to the fourth voltage signal terminal, and the second electrode of the sixth control transistor is electrically connected to The seventh node is electrically connected.
  • the control electrode of the seventh control transistor is electrically connected to the fourth clock signal terminal, the first electrode of the seventh control transistor is electrically connected to the seventh node, and the second electrode of the seventh control transistor is electrically connected to The fifth node is electrically connected.
  • the control electrode of the eighth control transistor is electrically connected to the third voltage signal terminal, the first electrode of the eighth control transistor is electrically connected to the fifth node, and the second electrode of the eighth control transistor is electrically connected to The eighth node is electrically connected.
  • the control electrode of the second output transistor is electrically connected to the sixth node, the first electrode of the second output transistor is electrically connected to the fourth voltage signal terminal, and the second electrode of the second output transistor is electrically connected to The reset signal output terminal is electrically connected.
  • the control electrode of the fourth output transistor is electrically connected to the eighth node, the first electrode of the fourth output transistor is electrically connected to the fourth clock signal terminal, and the second electrode of the fourth output transistor is electrically connected to The reset signal output terminal is electrically connected.
  • the first plate of the third capacitor is electrically connected to the fourth voltage signal terminal, and the second plate of the third capacitor is electrically connected to the sixth node.
  • the first plate of the fourth capacitor is electrically connected to the reset signal output terminal, and the second plate of the fourth capacitor is electrically connected to the eighth node.
  • a scan driving circuit including: a plurality of shift registers as described in any of the above embodiments.
  • the scanning circuits in the shift registers are arranged in sequence along the column direction; the reset circuits in the shift registers are arranged in the column direction in sequence.
  • the scan driving circuit further includes: a first voltage signal line extending along the column direction and electrically connected to the first voltage signal terminal of the scanning circuit; and a first voltage signal line extending along the column direction.
  • the second voltage signal line is electrically connected to the second voltage signal terminal of the scanning circuit;
  • the third voltage signal line extending along the column direction is electrically connected to the third voltage signal terminal of the reset circuit; and, along the The fourth voltage signal line extending in the column direction is electrically connected to the fourth voltage signal terminal of the reset circuit.
  • the scanning circuit is provided between the first voltage signal line and the second voltage signal line
  • the reset circuit is provided between the third voltage signal line and the fourth voltage signal line.
  • the second voltage signal line and the third voltage signal line are provided between the scan circuit and the reset circuit.
  • the scan driving circuit further includes: a first clock signal line extending along the column direction, and a first clock signal end of the 2m-1th scan circuit and the 2mth scan circuit.
  • the second clock signal terminal of The signal terminal is electrically connected;
  • the third clock signal line extending along the column direction is electrically connected to the third clock signal terminal of the 2m-1th reset circuit and the fourth clock signal terminal of the 2mth reset circuit.
  • the fourth clock signal line extending along the column direction is electrically connected to the fourth clock signal terminal of the 2m-1th reset circuit and the third clock signal terminal of the 2mth reset circuit;
  • m is positive integer.
  • the first clock signal line and the second clock signal line are provided on a side of the scanning circuit away from the reset circuit;
  • the third clock signal line and the fourth clock signal line are provided on On the side of the reset circuit close to the scanning circuit.
  • the scan driving circuit further includes: a first initial signal line extending along the column direction, and a first input of the scan circuit of the first n shift registers in the plurality of shift registers.
  • the signal terminal is electrically connected; n is a positive integer; the second initial signal line extending along the column direction is electrically connected to the second input signal terminal of the reset circuit of the first i shift registers in the plurality of shift registers; i is a positive integer.
  • the first initial signal line is provided on a side of the scanning circuit away from the reset circuit; the second initial signal line is provided on a side of the reset circuit close to the scanning circuit.
  • a display substrate including: a substrate; a plurality of rows of sub-pixels provided on the substrate; and at least one of the sub-pixels provided on the substrate as described in any of the above embodiments.
  • a scan driver circuit in the scan driving circuit, each shift register is electrically connected to one row of sub-pixels, and is configured to transmit a scan signal and a reset signal to the one row of sub-pixels.
  • the number of the scan driving circuits is two; the two scan driving circuits are respectively located on opposite sides of the multiple rows of sub-pixels.
  • the display substrate further includes: a semiconductor layer disposed on the substrate.
  • the first output transistor of the scanning circuit includes: a first active layer; and the first active layer includes a first channel portion.
  • the second output transistor of the reset circuit includes: a second active layer; and the second active layer includes a second channel portion.
  • the first active layer and the second active layer are both located in the semiconductor layer; the channel width of the first channel part is greater than or equal to the channel width of the second channel part. .
  • the channel width direction of the first channel portion and the channel width direction of the second channel portion are both arranged along the row direction.
  • the third output transistor of the scanning circuit includes: a third active layer; and the third active layer includes a third channel portion.
  • the fourth output transistor of the reset circuit includes: a fourth active layer; the fourth active layer includes a fourth channel portion.
  • the third active layer and the fourth active layer are both located in the semiconductor layer; the channel width of the third channel part is greater than or equal to the channel width of the fourth channel part. .
  • the channel width direction of the third channel portion and the channel width direction of the fourth channel portion are both arranged along the row direction.
  • the first active layer and the third active layer are arranged in sequence along the column direction; and/or the second active layer and the fourth active layer are arranged in sequence along the column direction. set up.
  • the first active layer and the third active layer have an integrated structure; and/or the second active layer and the fourth active layer have an integrated structure.
  • the display substrate further includes: a second gate conductive layer and a source-drain conductive layer that are disposed on a side of the semiconductor layer away from the substrate and stacked in sequence.
  • the second plate of the second capacitor of the scanning circuit is located on the second gate conductive layer; the second pole of the first output transistor and the second pole of the third output transistor of the scanning circuit form an integrated structure, and are located on the source-drain conductive layer; the second electrode of the first output transistor is electrically connected to the first plate of the second capacitor; the scan signal output end of the scan circuit is connected to the second electrode of the second capacitor.
  • the first pole plate has an integrated structure.
  • the second plate of the fourth capacitor of the reset circuit is located on the second gate conductive layer; the second electrode of the second output transistor is connected to the third electrode of the fourth output transistor of the reset circuit.
  • the two poles have an integrated structure and are both located on the source-drain conductive layer; the second pole of the second output transistor is electrically connected to the first plate of the fourth capacitor; the reset signal output end of the reset circuit is connected to the first plate of the fourth capacitor.
  • the first plate of the fourth capacitor has an integrated structure.
  • the first input transistor of the scanning circuit includes: a fifth active layer disposed on a side of the first active layer away from the plurality of rows of sub-pixels.
  • the first control transistor of the scanning circuit includes: a sixth active layer disposed on a side of the first active layer away from the plurality of rows of sub-pixels.
  • the second control transistor of the scanning circuit includes: a seventh active layer disposed between the fifth active layer and the first active layer.
  • the third control transistor of the scanning circuit includes an eighth active layer disposed between the fifth active layer and the first active layer.
  • the fourth control transistor of the scanning circuit includes: a ninth active layer disposed between the fifth active layer and the eighth active layer.
  • the fifth active layer, the sixth active layer, the seventh active layer, the eighth active layer, and the ninth active layer are all located on the semiconductor layer.
  • the channel length direction of the fifth active layer, the channel length direction of the sixth active layer, the channel length direction of the seventh active layer, the channel length of the eighth active layer The direction and the channel length direction of the ninth active layer are both arranged along the column direction.
  • the fifth active layer and the sixth active layer are arranged sequentially along the column direction to form an integrated structure; and/or the seventh active layer and the eighth active layer
  • the source layers are arranged sequentially along the column direction to form an integrated structure.
  • the third input transistor of the reset circuit includes: a tenth active layer disposed on a side of the second active layer away from the plurality of rows of sub-pixels.
  • the fifth control transistor of the reset circuit includes: an eleventh active layer disposed on a side of the second active layer away from the plurality of rows of sub-pixels.
  • the sixth control transistor of the reset circuit includes: a twelfth active layer disposed between the tenth active layer and the second active layer.
  • the seventh control transistor of the reset circuit includes: a thirteenth active layer disposed between the tenth active layer and the second active layer.
  • the eighth control transistor of the reset circuit includes: a fourteenth active layer disposed between the tenth active layer and the thirteenth active layer.
  • the tenth active layer, the eleventh active layer, the twelfth active layer, the thirteenth active layer, and the fourteenth active layer are all located on the semiconductor layer; the channel length direction of the tenth active layer, the channel length direction of the eleventh active layer, the channel length direction of the twelfth active layer, the thirteenth active layer The channel length direction of the layer and the channel length direction of the fourteenth active layer are both arranged along the column direction.
  • the tenth active layer and the eleventh active layer are arranged sequentially along the column direction to form an integrated structure; and/or the twelfth active layer and the Thirteen active layers are arranged sequentially along the column direction, forming an integrated structure.
  • Figure 1 is a structural diagram of a display substrate according to an implementation manner
  • Figure 2 is a structural diagram of a display substrate according to some embodiments of the present disclosure.
  • Figure 3 is a structural diagram of another display substrate according to some embodiments of the present disclosure.
  • Figure 4 is a structural diagram of a sub-pixel according to some embodiments of the present disclosure.
  • Figure 5 is a structural diagram of a scan driving circuit according to some embodiments of the present disclosure.
  • Figure 6 is a structural diagram of a shift register according to some embodiments of the present disclosure.
  • Figure 7 is an equivalent structural diagram of a scanning circuit according to some embodiments of the present disclosure.
  • Figure 8 is a driving timing diagram of a scanning circuit according to some embodiments of the present disclosure.
  • Figure 9 is an equivalent structural diagram of a reset circuit according to some embodiments of the present disclosure.
  • Figure 10 is a top view of some film layers of a scanning circuit according to some embodiments of the present disclosure.
  • Figure 11 is a cross-sectional view along the A-A’ direction of the top view shown in Figure 10;
  • Figure 12 is a cross-sectional view along the B-B' direction of the top view shown in Figure 10;
  • Figure 13 is a top view of other film layers of the scanning circuit according to some embodiments of the present disclosure.
  • Figure 14 is a top view of some further film layers of the scanning circuit according to some embodiments of the present disclosure.
  • Figure 15 is a top view of further film layers of the scanning circuit according to some embodiments of the present disclosure.
  • Figure 16 is a top view of further film layers of the scanning circuit according to some embodiments of the present disclosure.
  • Figure 17 is a top view of further film layers of the scanning circuit according to some embodiments of the present disclosure.
  • Figure 18 is a top view of some film layers of a reset circuit according to some embodiments of the present disclosure.
  • Figure 19 is a cross-sectional view along the C-C' direction of the top view shown in Figure 18;
  • Figure 20 is a top view of other film layers of the reset circuit according to some embodiments of the present disclosure.
  • Figure 21 is a top view of further film layers of the reset circuit according to some embodiments of the present disclosure.
  • Figure 22 is a top view of further film layers of the reset circuit according to some embodiments of the present disclosure.
  • Figure 23 is a top view of further film layers of the reset circuit according to some embodiments of the present disclosure.
  • Figure 24 is a top view of further film layers of a reset circuit according to some embodiments of the present disclosure.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C” and includes the following combinations of A, B and C: A only, B only, C only, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” is optionally interpreted to mean “when” or “in response to” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrase “if it is determined" or “if [stated condition or event] is detected” is optionally interpreted to mean “when it is determined" or “in response to the determination" or “on detection of [stated condition or event]” or “in response to detection of [stated condition or event]”.
  • parallel includes absolutely parallel and approximately parallel, and the acceptable deviation range of approximately parallel may be, for example, a deviation within 5°;
  • perpendicular includes absolutely vertical and approximately vertical, and the acceptable deviation range of approximately vertical may also be, for example, Deviation within 5°.
  • equal includes absolute equality and approximate equality, wherein the difference between the two that may be equal within the acceptable deviation range of approximately equal is less than or equal to 5% of either one, for example.
  • Example embodiments are described herein with reference to cross-sectional illustrations and/or plan views that are idealized illustrations.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
  • the transistors used in the shift register can be thin film transistors (Thin Film Transistor, TFT for short) or field effect transistors (Metal Oxide Semiconductor). (referred to as MOS) or other switching devices with the same characteristics.
  • thin film transistors are used as examples for description.
  • the control electrode of each transistor used is a gate electrode
  • the first electrode of the transistor is one of the source electrode and the drain electrode
  • the second electrode of the transistor is the other of the source electrode and the drain electrode.
  • the transistor when the transistor is a P-type transistor, the first electrode of the transistor is the source electrode, and the second electrode is the drain electrode; for example, when the transistor is an N-type transistor, the first electrode of the transistor is the drain electrode, The second pole is the source.
  • the capacitor may be a capacitive device manufactured separately through a process, for example, by manufacturing special capacitive electrodes.
  • Each capacitive electrode of the capacitor may be formed by a metal layer or a semiconductor layer (such as doped polysilicon). ) and so on.
  • the capacitor can also be the parasitic capacitance between transistors, or it can be realized by the transistor itself and other devices and circuits, or it can be realized by using the parasitic capacitance between the circuit's own circuits.
  • nodes such as the first node and the second node do not represent actual existing components, but represent the meeting points of relevant electrical connections in the circuit diagram. That is to say, these nodes are formed by the relevant electrical connections in the circuit diagram. A node that is equivalent to the intersection of electrical connections.
  • the transistors included in the circuit structure provided in the embodiments of the present disclosure may all be N-type transistors, or may all be P-type transistors, or some may be N-type transistors and the other may be P-type transistors.
  • an "effective level" refers to a level that enables a transistor to turn on. Among them, P-type transistors can be turned on under the control of low-level signals, and N-type transistors can be turned on under the control of high-level signals.
  • Some embodiments of the present disclosure provide a shift register, a scan drive circuit and a display substrate.
  • the shift register, scan drive circuit and display substrate are introduced respectively below.
  • the display substrate device 1000 may be any display substrate that displays images, whether moving (eg, video) or fixed (eg, still images), and whether text or text. More specifically, it is contemplated that the display substrates of the embodiments may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants, (PDA), handheld or portable computer, GPS receiver/navigator, camera, MP4 video player, video camera, game console, watch, clock, calculator, TV monitor, flat panel display, computer monitor, automotive monitor (e.g., odometer display, etc.), navigator, cockpit controller and/or display, display of camera view (e.g., display of rear view camera in vehicle), electronic photo, electronic billboard or sign, projector, construction Structure, packaging and aesthetic structure (for example, for the display of an image of a piece of jewelry) etc.
  • electronic devices such as (but not limited to) mobile phones, wireless devices, personal data assistants, (PDA), handheld or portable computer, GPS receiver/navigator,
  • the above-mentioned display substrate 1000 can be, for example, an organic light emitting diode (OLED) display substrate, a quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, QLED) display substrate, or a micro light emitting diode (Micro Light Emitting Diodes, OLED for short). Micro LED) display substrate or Mini Light Emitting Diodes (Mini LED for short) display substrate, etc. This disclosure does not specifically limit this.
  • OLED organic light emitting diode
  • QLED Quantum Dot Light Emitting Diodes
  • micro light emitting diode Micro Light Emitting Diodes, OLED for short
  • Micro LED display substrate or Mini Light Emitting Diodes (Mini LED for short) display substrate, etc. This disclosure does not specifically limit this.
  • the display substrate 1000 includes: a substrate 200 ; multiple rows of sub-pixels Row disposed on the substrate 200 ; and at least one scan driving circuit 100 disposed on the substrate 200 .
  • the display substrate 1000 may include 2480 rows of sub-pixels Row.
  • the 1st row of sub-pixels, the 2nd row of sub-pixels...the 2479th row of sub-pixels, and the 2480th row of sub-pixels can be represented by Row_1, Row_2...Row_2479, and Row_2480 respectively.
  • Each row of sub-pixels Row may include multiple sub-pixels 300 .
  • the above-mentioned substrate 200 may be a flexible substrate or a rigid substrate.
  • the material of the substrate 200 may be dimethylsiloxane, PI (Polyimide, polyimide), PET (Polyethylene terephthalate, polyterephthalate). Ethylene glycol ester) and other highly elastic materials.
  • the material of the substrate 200 may be glass or the like.
  • the sub-pixel 300 includes a pixel driving circuit and a light-emitting device.
  • the above-mentioned pixel driving circuit has a variety of structures, which can be selected and set according to actual needs.
  • the structure of the pixel driving circuit may include a "4T1C”, “6T1C”, “7T1C”, “6T2C”, “7T2C” or “8T2C” structure.
  • T represents the transistor
  • the number in front of “T” represents the number of transistors
  • C represents the storage capacitor
  • the number in front of "C” represents the number of storage capacitors.
  • the light-emitting device may include an anode, a light-emitting layer and a cathode arranged in a stack in sequence.
  • the light-emitting device may further include, for example, a hole injection layer and/or a hole transport layer disposed between the anode and the light-emitting layer, and may further include, for example, an electron transport layer and/or an electron injection layer disposed between the light-emitting layer and the cathode. layer.
  • the pixel driving circuit is electrically connected to the anode of the light-emitting device, for example.
  • the structure of the sub-pixel will be schematically explained below with reference to Figure 4, taking the structure of the pixel driving circuit as "7T1C" as an example. It should be noted that there may also be other electrical connection relationships between the seven transistors and one storage capacitor included in the pixel driving circuit, and are not limited to the electrical connection relationship shown in this example.
  • the pixel driving circuit includes: a first reset transistor M1, a switching transistor M4, a driving transistor M3, a compensation transistor M2, and a second reset transistor M5.
  • the control electrode of the first reset transistor M1 is electrically connected to the reset signal terminal Reset, the first electrode of the first reset transistor M1 is electrically connected to the initial signal terminal Vinit, and the first electrode of the first reset transistor M1 is electrically connected to the initial signal terminal Vinit.
  • the second pole is electrically connected to the first pixel node Q1.
  • the first reset transistor M1 is configured to be turned on under the control of the reset signal transmitted by the reset signal terminal Reset, and transmit the initial signal received from the initial signal terminal Vinit to the first pixel node Q1, to the first pixel Node Q1 is reset.
  • the control electrode of the second reset transistor M5 is electrically connected to the scan signal terminal Gate
  • the first electrode of the second reset transistor M5 is electrically connected to the initial signal terminal Vinit
  • the second electrode of the second reset transistor M5 is electrically connected to the initial signal terminal Vinit.
  • the diode is electrically connected to the anode of the light emitting device.
  • the second reset transistor M5 is configured to be turned on under the control of the scanning signal transmitted by the scanning signal terminal Gate, and transmit the initial signal received from the initial signal terminal Vinit to the anode of the light-emitting device, and to the anode of the light-emitting device. Perform a reset.
  • control electrode of the switching transistor M4 is electrically connected to the scanning signal terminal Gate
  • first electrode of the switching transistor M4 is electrically connected to the data signal terminal Data
  • second electrode of the switching transistor M4 is electrically connected to the second pixel.
  • Node Q2 is electrically connected.
  • the switching transistor M4 is configured to be turned on under the control of the scanning signal transmitted by the scanning signal terminal Gate, and transmit the data signal transmitted by the data signal terminal Data to the second pixel node Q2.
  • the control electrode of the driving transistor M3 is electrically connected to the first pixel node Q1, the first electrode of the driving transistor M3 is electrically connected to the second pixel node Q2, and the second electrode of the driving transistor M3 is electrically connected to the second pixel node Q2.
  • Three-pixel node Q3 is electrically connected.
  • the driving transistor M3 is configured to be turned on under the control of the voltage of the first pixel node Q1 and transmit the signal (eg, a data signal) from the second pixel node Q2 to the third pixel node Q3.
  • the control electrode of the compensation transistor M2 is electrically connected to the scanning signal terminal Gate
  • the first electrode of the compensation transistor M2 is electrically connected to the third pixel node Q3
  • the second electrode of the compensation transistor M2 is electrically connected to the first pixel node Q3.
  • Pixel node Q1 is electrically connected.
  • the compensation transistor M2 is configured to be turned on under the control of the scan signal transmitted by the scan signal terminal Gate, and transmit the signal (for example, a data signal) from the third pixel node Q3 to the first pixel node Q1, for driving Transistor M3 performs threshold voltage compensation.
  • the switching transistor M4 and the compensation transistor M2 can be turned on at the same time under the control of the scanning signal, and the data signal terminal
  • the data signal transmitted by Data is sequentially transmitted to the first pixel node Q1 through the switching transistor M4, the driving transistor M3 and the compensation transistor M2, until the driving transistor M3 is in the off state, completing the compensation of the threshold voltage of the driving transistor M3.
  • the second reset transistor M5 can also be turned on under the control of the scan signal, receive and transmit the initial signal to the anode of the light-emitting device, and reset the anode of the light-emitting device.
  • the sub-pixel driving method includes a reset phase and a data writing and compensation phase performed in sequence.
  • the first reset transistor M1 is turned on, transmits the initial signal to the first pixel node Q1, and resets the first pixel node Q1.
  • the second reset transistor M5 is turned on under the control of the scan signal, transmits the initial signal to the anode of the light-emitting device, and resets the anode of the light-emitting device.
  • the switching transistor M4 is turned on under the control of the scan signal, transmits the data signal to the second pixel node Q2, and completes the writing of the data signal;
  • the driving transistor M3 is turned on under the control of the first pixel node Q1, and transmits the data signal from the second pixel node Q2 to the second pixel node Q2.
  • the signal from node Q2 (for example, a data signal) is transmitted to the third pixel node Q3; the compensation transistor M2 is turned on under the control of the scan signal to transmit the signal (for example, a data signal) from the third pixel node Q3 to the first pixel.
  • Node Q1 performs threshold voltage compensation on the driving transistor M3; until the driving transistor M3 is in the cut-off state, the compensation on the threshold voltage of the driving transistor M3 is completed.
  • the above-mentioned scan driving circuit 100 may include multiple shift registers 10 .
  • the scanning signal transmitted by the scanning signal terminal Gate and the reset signal transmitted by the reset signal terminal Reset of the sub-pixel 300 are provided by the shift register 10 .
  • the shift register can be represented by GR, for example, GR0, GR1, GR2... GR2479, GR2480 can represent the first shift register, the second shift register, the second shift register, etc. 3 shift registers...the 2480th shift register, the 2481st shift register.
  • Each shift register is electrically connected to two adjacent rows of sub-pixels Row.
  • Each shift register has an output signal terminal.
  • the second shift register GR2 is electrically connected to the first row of sub-pixels Row_1 and the second row of sub-pixels Row_2.
  • the signal output by the second shift register GR2 can be transmitted to the first row of sub-pixels Row_1 and used as the reset signal transmitted by each reset signal terminal of the first row of sub-pixels Row_1; at the same time, it can be transmitted to the second row of sub-pixels Row_2, and serve as the scanning signals transmitted by each scanning signal terminal of the second row sub-pixel Row_2.
  • the same shift register GR needs to be electrically connected to two rows of sub-pixels Row and drive the two rows of sub-pixels Row at the same time.
  • the load of the shift register GR is larger, which reduces the accuracy of the signal output by the shift register GR, thereby reducing the reset time, data writing and compensation time of the sub-pixel, and affecting the display effect of the display substrate.
  • the shift register 10 provided in some embodiments of the present disclosure includes a scanning circuit 11 and a reset circuit 12 . Wherein, the shift register 10 is applied to the above-mentioned display substrate 1000.
  • the above-mentioned scanning circuit 11 is connected with the first input signal terminal GI, the first clock signal terminal CK1, the second clock signal terminal CB1, the first voltage signal terminal VL1 and the second voltage signal terminal. VH1 electrical connection.
  • the scanning circuit 11 is configured such that the first input signal transmitted by the first input signal terminal GI, the first clock signal transmitted by the first clock signal terminal CK1, the second clock signal transmitted by the second clock signal terminal CB1, Under the cooperation of the first voltage signal transmitted by the first voltage signal terminal VL1 and the second voltage signal transmitted by the second voltage signal terminal VH1, the scanning signal Gate is output.
  • the above-mentioned reset circuit 12 is connected with the second input signal terminal RI, the third clock signal terminal CK2, the fourth clock signal terminal CB2, the third voltage signal terminal VL2 and the fourth voltage signal terminal. VH2 electrical connection.
  • the reset circuit 12 is configured to receive the second input signal transmitted by the second input signal terminal RI, the third clock signal transmitted by the third clock signal terminal CK2, the fourth clock signal transmitted by the fourth clock signal terminal CB2, Under the cooperation of the third voltage signal transmitted by the third voltage signal terminal VL2 and the fourth voltage signal transmitted by the fourth voltage signal terminal VH2, a reset signal Reset is output.
  • the first voltage signal terminal VL1 is configured to transmit a first DC low-level signal (for example, lower than or equal to the low-level part of the clock signal).
  • the first DC low-level signal is called a first voltage signal.
  • the third voltage signal terminal VL2 is configured to transmit a third DC low-level signal (for example, lower than or equal to the low-level part of the clock signal).
  • the third DC low-level signal is called a third voltage signal.
  • the level of the first voltage signal and the level of the third voltage signal may be the same.
  • the second voltage signal terminal VH1 is configured to transmit a second DC high-level signal (for example, higher than or equal to the high-level part of the clock signal).
  • the second DC high-level signal is called a second voltage signal.
  • the fourth voltage signal terminal VH2 is configured to transmit a fourth DC high-level signal (for example, higher than or equal to the high-level part of the clock signal).
  • the fourth DC high-level signal is called a fourth voltage signal.
  • the level of the second voltage signal and the level of the fourth voltage signal may be the same.
  • the first clock signal terminal CK1 is configured to transmit the first clock signal (for example, having a low level part and a high level part).
  • the second clock signal terminal CB1 is configured to transmit a second clock signal (for example, having a low level part and a high level part).
  • the waveform of the first clock signal and the waveform of the second clock signal may be the same, and the effective level of the first clock signal and the effective level of the second clock signal do not coincide in time.
  • the third clock signal terminal CK2 is configured to transmit a third clock signal (for example, having a low level part and a high level part).
  • the fourth clock signal terminal CB2 is configured to transmit a fourth clock signal (for example, having a low level part and a high level part).
  • the waveform of the third clock signal and the waveform of the fourth clock signal may be the same, and the effective level of the third clock signal and the effective level of the fourth clock signal do not coincide in time.
  • the scan circuit 11 and the reset circuit 12 output signals independently of each other.
  • the scanning circuit 11 and the reset circuit 12 are designed independently of each other and output scanning signals and reset signals respectively.
  • the waveform of the scanning signal and the waveform of the reset signal may be the same, but the time of the effective level of the scanning signal and the effective level of the reset signal do not coincide.
  • the above-mentioned shift register 10 is electrically connected to a row of sub-pixels Row, and is configured to transmit the scanning signal Gate and the reset signal Reset to the above-mentioned row of sub-pixels Row. That is, the scanning circuit 11 and the reset circuit 12 in the shift register 10 are electrically connected to a row of sub-pixels Row at the same time, and respectively transmit the scanning signal Gate and the reset signal Reset to the row of sub-pixels Row, so as to utilize the reset signal Reset to the row of sub-pixels Row.
  • the row sub-pixel Row is reset, and the scanning signal Gate is used to write data and compensate for the row sub-pixel Row.
  • the shift register 10 in this disclosure is only electrically connected to one row of sub-pixels Row, and transmits the scanning signal Gate and the reset signal Reset to the one row of sub-pixels Row.
  • the shift register 10 only drives one row of sub-pixels Row to realize the row of sub-pixels Row. reset, data writing and compensation, thereby reducing the load of the shift register 10, thereby reducing the load of the scan driver circuit 100, improving the accuracy of the scan signal Gate and the reset signal Reset transmitted to the sub-pixels, thereby improving the display Display effect of substrate 1000.
  • the above-mentioned scanning circuit 11 includes: a first output transistor T4.
  • the first pole of the first output transistor T4 is electrically connected to the second voltage signal terminal VH1, and the second pole of the first output transistor T4 is electrically connected to the scan signal output terminal GO.
  • the scanning circuit 11 further includes: a third output transistor T5.
  • the first pole of the third output transistor T5 is electrically connected to the second clock signal terminal CB1, and the second pole of the third output transistor T5 is electrically connected to the scan signal output terminal GO.
  • the first output transistor T4 and the third output transistor T5 are respectively turned on in different time periods.
  • the first output transistor T4 can receive and transmit the second voltage signal to the scan signal output terminal GO, and output the second voltage signal as the scan signal Gate from the scan signal output terminal GO.
  • the third output transistor T5 can receive and transmit the second clock signal to the scan signal output terminal GO, and output the second clock signal as the scan signal Gate from the scan signal output terminal GO.
  • the scanning signal Gate is composed of a combination of the second voltage signal and the second clock signal.
  • the effective level part of the scanning signal Gate is composed of the second clock signal.
  • the above-mentioned reset circuit 12 includes: a second output transistor R4.
  • the first pole of the second output transistor R4 is electrically connected to the fourth voltage signal terminal VH2, and the second pole of the second output transistor R4 is electrically connected to the reset signal output terminal RO.
  • the reset circuit 12 further includes: a fourth output transistor R5.
  • the first pole of the fourth output transistor R5 is electrically connected to the fourth clock signal terminal CB2, and the second pole of the fourth output transistor R5 is electrically connected to the reset signal output terminal RO.
  • the second output transistor R4 and the fourth output transistor R5 are respectively turned on in different time periods.
  • the second output transistor R4 can receive and transmit the fourth voltage signal to the reset signal output terminal RO, and output the fourth voltage signal as the reset signal Reset from the reset signal output terminal RO.
  • the fourth output transistor R5 can receive and transmit the fourth clock signal to the reset signal output terminal RO, and output the fourth clock signal as the reset signal Reset from the reset signal output terminal RO.
  • the reset signal Reset is composed of a fourth voltage signal and a fourth clock signal.
  • the effective level part of the reset signal Reset is composed of the fourth clock signal.
  • the channel width of the first output transistor T4 is greater than or equal to the channel width of the second output transistor R4.
  • the channel width of the thin film transistor affects the switching characteristics of the thin film transistor.
  • the width-to-length ratio (W/L) needs to be increased, for example, the channel width W can be increased or the channel length L can be reduced.
  • the channel length L is basically the minimum spacing that can be guaranteed by the process level without short-circuiting the source and drain. Therefore, higher operating current can be obtained by increasing the channel width of the thin film transistor.
  • the increase in the operating current represents an enhancement of the writing ability and retention ability, which can reduce the power consumption of the thin film transistor and thereby reduce the cost of the display substrate. power consumption.
  • the channel width of the first output transistor T4 is equal to the channel width of the second output transistor R4. Therefore, the power consumption of the first output transistor T4 of the scanning circuit 11 and the power consumption of the second output transistor R4 of the reset circuit 12 are the same.
  • the channel width of the first output transistor T4 is greater than the channel width of the second output transistor R4. Therefore, the power consumption of the first output transistor T4 of the scanning circuit 11 is less than the power consumption of the second output transistor R4 of the reset circuit 12, and the power consumption of the display substrate 1000 can be reduced.
  • the ratio of the channel width of the first output transistor T4 to the channel width of the second output transistor R4 ranges from 1:1 to 20:1.
  • the ratio of the channel width of the first output transistor T4 to the channel width of the second output transistor R4 may be 1:1, 2:1, 3:1, 4:1, 10:1, or 20:1.
  • the channel width of the third output transistor T5 is greater than or equal to the channel width of the fourth output transistor R5.
  • the channel width of the third output transistor T5 is equal to the channel width of the fourth output transistor R5.
  • the channel width of the third output transistor T5 is greater than the channel width of the fourth output transistor R5. Therefore, the power consumption of the third output transistor T5 of the scanning circuit 11 is less than the power consumption of the fourth output transistor R5 of the reset circuit 12 , which can improve the driving capability of the scan driving circuit 10 for the sub-pixel 300 , thereby reducing the power consumption of the display substrate 1000 .
  • the ratio of the channel width of the third output transistor T5 to the channel width of the fourth output transistor R5 ranges from 1:1 to 20:1.
  • the ratio of the channel width of the third output transistor T5 to the channel width of the fourth output transistor R5 may be 1:1, 2:1, 3:1, 4:1, 10:1, or 20:1.
  • the channel width of the output transistor of the shift register in one implementation, the channel width of the output transistor of the reset circuit 11 in the present disclosure, and the channel width of the output transistor of the scan circuit 12 in the present disclosure are respectively set.
  • the channel width of the output transistor of the shift register in one implementation, the channel width of the output transistor of the reset circuit in the present disclosure, and the channel width of the output transistor of the scan circuit in the present disclosure are set as follows: As shown in Table 1. It can be seen from Table 1 that the ratio of the channel width of the first output transistor to the channel width of the second output transistor is 3:1, and the ratio of the channel width of the third output transistor to the channel width of the fourth output transistor is 3 :1.
  • the detection results of the signal output by the shift register in one implementation, the reset signal output by the reset circuit in the present disclosure, and the scan signal output by the scan circuit in the present disclosure are as shown in Table 2.
  • Tr represents the rising edge time of the signal
  • Tf represents the falling edge time of the signal. The smaller the value of Tr, the shorter the rising edge time of the signal. The smaller the value of Tf, the shorter the falling edge time of the signal. If the values of Tr and Tf are both relatively small, it means that the waveform of the signal is more regular and the accuracy of the signal is higher.
  • the Tr of the reset signal is smaller than the Tr of the reset signal in one implementation, and the Tr of the reset signal is reduced by 4.9% compared to the Tr of the reset signal in one implementation; reset The Tf of the signal is smaller than the Tf of the reset signal in one implementation, and the Tf of the reset signal is reduced by 0.4% compared to the Tf of the reset signal in one implementation.
  • the Tr of the scanning signal is smaller than the Tr of the scanning signal in one implementation, and the Tr of the scanning signal is reduced by 12.1% compared to the Tr of the scanning signal in one implementation; the Tf of the scanning signal is less than one The Tf of the scanning signal in one implementation is reduced by 10.1% compared to the Tf of the scanning signal in one implementation.
  • the reset signal and the scanning signal provided by the shift register are the same signal and are output by the same signal output terminal.
  • the shift register needs to drive one row of sub-pixels to reset and drive another row.
  • the reset signal needs to drive the first reset transistor M1 of the above-mentioned row of sub-pixels
  • the scan signal needs to drive the switching transistor M4, second reset transistor M5 and compensation transistor M2 of the above-mentioned other row of sub-pixels. , therefore, the measured Tf of the scanning signal is different from the Tf of the reset signal, and the Tr of the scanning signal is different from the Tr of the reset signal.
  • the first output in the scanning circuit 11 The channel width of the transistor T4 is greater than or equal to the channel width of the second output transistor R4 in the reset circuit 12 , and the channel width of the third output transistor T5 in the scan circuit 11 is greater than or equal to the channel width of the fourth output transistor R5 in the reset circuit 12 .
  • the channel width can not only reduce Tr and Tf of the scanning signal Gate output by the scanning circuit 11, but also reduce Tr and Tf of the reset signal Reset output by the reset circuit 12.
  • the present disclosure adopts the above setting method to reduce the load of the shift register 10 and reduce the loss of the scanning signal Gate and the reset signal Reset in the process of transmission to the sub-pixel 300, thereby improving the scanning signal Gate and the reset signal.
  • the accuracy of Reset further improves the time for resetting, data writing and compensation of the sub-pixel 300, thereby helping to reduce the power consumption of the display substrate 1000 and improve the display quality of the display substrate 1000.
  • the scanning circuit 11 and the reset circuit 12 can be arranged in various ways, which can be selected according to the actual situation.
  • the scan circuit 11 and the reset circuit 12 are arranged in parallel along the row direction X.
  • the scanning circuit 11 and the reset circuit 12 may be arranged in parallel with a row of sub-pixels Row electrically connected thereto.
  • the scanning circuit 11 and the reset circuit 12 are arranged in a relatively regular manner, which facilitates wiring layout and can reduce the area occupied by the shift register 10.
  • the scanning circuit 11 and the reset circuit 12 are staggered along the row direction X.
  • the scanning circuit 11 may be disposed in the same row as a row of sub-pixels Row electrically connected thereto, and the reset circuit 12 may be disposed in the same row as another row of sub-pixels Row adjacent to the above-mentioned row of sub-pixels Row.
  • the scanning circuit 11 may be located between two adjacent reset circuits 12 .
  • the above arrangement can facilitate the wiring connection between the scanning circuit 11 or the reset circuit 12 and the corresponding row of sub-pixels Row.
  • the reset circuit 12 is closer to the row of sub-pixels Row to which it is electrically connected than the scanning circuit 11 .
  • the length of the wiring electrically connecting the reset signal output terminal RO of the reset circuit 12 and the corresponding row of sub-pixels Row is short, and the loss of the reset signal Reset is small, which is beneficial to improving the transmission rate of the reset circuit 12 to the sub-pixels.
  • the reset signal Reset provided by 300 is accurate and stable.
  • the scanning circuit 10 includes: a first input transistor T3, a second input transistor T1, a first control transistor T2, a second control transistor T6, a third Control transistor T7, fourth control transistor T8, first output transistor T4, third output transistor T5, first capacitor C1 and second capacitor C2.
  • control electrode of the first input transistor T3 is electrically connected to the first clock signal terminal CK1
  • first electrode of the first input transistor T3 is electrically connected to the first voltage signal terminal VL1
  • first The second pole of the input transistor T3 is electrically connected to the second node N2.
  • the first input transistor T3 is configured to be turned on under the control of the first clock signal to transmit the first voltage signal to the second node N2.
  • control electrode of the second input transistor T1 is electrically connected to the first clock signal terminal CK1
  • first electrode of the second input transistor T1 is electrically connected to the first input signal terminal GI
  • second input transistor T1 is electrically connected to the first input signal terminal GI.
  • the second pole of the input transistor T1 is electrically connected to the first node N1.
  • the second input transistor T1 is configured to be turned on under the control of the first clock signal to transmit the first input signal to the first node N1.
  • the control electrode of the first control transistor T2 is electrically connected to the first node N1
  • the first electrode of the first control transistor T2 is electrically connected to the first clock signal terminal CK1
  • the first control transistor T2 is electrically connected to the first clock signal terminal CK1 .
  • the second pole of T2 is electrically connected to the second node N2.
  • the first control transistor T2 is configured to be turned on under the control of the first node N1 to transmit the first clock signal to the second node N2.
  • control electrode of the second control transistor T6 is electrically connected to the second node N2
  • first electrode of the second control transistor T6 is electrically connected to the second voltage signal terminal VH1
  • second control transistor T6 is electrically connected to the second voltage signal terminal VH1.
  • the second pole of T6 is electrically connected to the third node N3.
  • the first control transistor T2 is configured to be turned on under the control of the first node N1 to transmit the first clock signal to the second node N2.
  • control electrode of the third control transistor T7 is electrically connected to the second clock signal terminal CB1
  • first electrode of the third control transistor T7 is electrically connected to the third node N3
  • third control transistor T7 is electrically connected to the third node N3
  • the second pole of T7 is electrically connected to the first node N1.
  • the third control transistor T7 is configured to be turned on under the control of the second clock signal to transmit the signal of the third node N3 (for example, the second voltage signal) to the first node N1.
  • control electrode of the fourth control transistor T8 is electrically connected to the first voltage signal terminal VL1
  • first electrode of the fourth control transistor T8 is electrically connected to the first node N1
  • fourth control transistor T8 is electrically connected to the first node N1
  • the second pole of T8 is electrically connected to the fourth node N4.
  • the fourth control transistor T8 is configured to be turned on under the control of the first voltage signal to transmit the signal of the first node N1 (for example, the first input signal) to the fourth node N4.
  • the control electrode of the first output transistor T4 is electrically connected to the second node N2, the first electrode of the first output transistor T4 is electrically connected to the second voltage signal terminal VH1, and the first output transistor T4 is electrically connected to the second voltage signal terminal VH1.
  • the second pole of T4 is electrically connected to the scanning signal output terminal GO.
  • the first plate of the first capacitor C1 is electrically connected to the second voltage signal terminal VGH1, and the second plate of the first capacitor C1 is electrically connected to the second node N2.
  • the first output transistor T4 is configured to be turned on under the control of the voltage of the second node N2, and transmit the second voltage signal to the scan signal output terminal GO.
  • the first capacitor C1 is configured to maintain the voltage of the second node N2.
  • the control electrode of the third output transistor T5 is electrically connected to the fourth node N4, the first electrode of the third output transistor T5 is electrically connected to the second clock signal terminal CB1, and the third output transistor T5 is electrically connected to the second clock signal terminal CB1.
  • the second pole of T5 is electrically connected to the scanning signal output terminal GO.
  • the first plate of the second capacitor C2 is electrically connected to the scan signal output terminal GO, and the second plate of the second capacitor C2 is electrically connected to the fourth node N4.
  • the third output transistor T5 is configured to be turned on under the control of the voltage of the fourth node N4 to transmit the second clock signal to the scan signal output terminal GO.
  • the second capacitor C2 is configured to maintain the voltage of the fourth node N4.
  • GI represents the first input signal transmitted by the first input signal terminal
  • CK1 represents the first clock signal transmitted by the first clock signal terminal
  • CB1 represents the second clock signal transmitted by the second clock signal terminal
  • GO Represents the scanning signal transmitted by the scanning signal output terminal
  • N4 represents the voltage of the fourth node.
  • the working process of the scanning circuit 11 includes: input stage P1, output stage P2 and buffer stage P3.
  • the level of the first clock signal is low level; the level of the second clock signal is high level.
  • the second The voltage value of the clock signal is equal to the voltage value of the second voltage signal; the level of the first input signal is low level, and its voltage value can be represented by Vin.
  • the voltage value of the first input signal is equal to the voltage value of the second voltage signal.
  • the voltage values of a voltage signal are equal.
  • the second input transistor T1 is turned on under the control of the first clock signal to transmit the input signal to the first node N1. Since the second input transistor T1 has a threshold loss when transmitting the first input signal, the voltage of the first node N1 is Vin-Vth1, that is, VL-Vth1, where Vth1 represents the threshold voltage of the second input transistor T1.
  • the fourth control transistor T8 is turned on under the control of the first voltage signal to transmit the voltage VL-Vth1 of the first node N1 to the fourth node N4. For example, the threshold voltage of the fourth control transistor T8 is Vth8.
  • the fourth control transistor T8 since the fourth control transistor T8 has a threshold loss during signal transmission, the voltage of the fourth node N4 is VL-VthNl, where VthNl is Vth1 and The smaller one in Vth8.
  • the third output transistor T5 may be turned on under the control of the voltage of the fourth node N4, and transmit the second clock signal to the scan signal output terminal GO as an output signal.
  • the first input transistor T3 is turned on under the control of the first clock signal to transmit the first voltage signal VL1 to the second node N2. Since the voltage of the first node N1 is VL-Vth1, the first control transistor T2 is turned on under the control of the voltage of the first node N1, and transmits the first clock signal to the second node N2.
  • the threshold voltage of the first control transistor T2 is Vth2, and the threshold voltage of the first input transistor T3 is Vth3. If Vth3 ⁇ Vth2+Vth1, then the voltage of the second node N2 is VL-Vth1-Vth2; if Vth3>Vth1+ Vth2, then the voltage of the second node N2 is VL-Vth3.
  • both the first output transistor T4 and the first control transistor T6 are turned on under the control of the voltage of the second node N2.
  • the third control transistor T7 is turned off under the control of the second clock signal.
  • the level of the second clock signal is high level and the level of the second voltage signal is high level, in the input stage P1, the level of the scanning signal is high level and the voltage is VH.
  • the level of the first clock signal is high level; the level of the second clock signal is low level.
  • the second The voltage value of the clock signal is equal to the voltage value of the first voltage signal.
  • the second input transistor T1 and the first input transistor T3 are both turned off under the control of the first clock signal.
  • the voltage of the first node N1 is still VL-VthNl.
  • the first control transistor T2 is turned on under the voltage control of the first node N1 and transmits the first clock signal to the second node N2, that is, the voltage of the second node N2 is VH.
  • the first output transistor T4 and the second control transistor T6 are both turned off under the control of the voltage of the second node N2.
  • the third output transistor T5 is turned on under the control of the voltage of the fourth node N4, and transmits the second clock signal to the scan signal output terminal GO as an output signal.
  • the voltage of the first plate of the second capacitor C2 is VH
  • the voltage of the second pole of the second capacitor C2 is VL-VthNl
  • the voltage of the first pole of the second capacitor C2 becomes VL. Due to the bootstrap effect of the second capacitor C2, the voltage of the second pole of the second capacitor C2 becomes 2VL-VthNl-VH, that is, the voltage of the fourth node N4 becomes 2VL-VthNl-VH.
  • the fourth control transistor T8 is turned off, and the third output transistor T5 can be better turned on under the control of the voltage of the fourth node N4, and the voltage of the scanning signal is VL.
  • the level of the first clock signal is high level; the level of the second clock signal is high level.
  • the level of the first input signal is high level.
  • the third output transistor T5 is turned on under the control of the voltage of the fourth node N4, and transmits the second clock signal to the scan signal output terminal GO as the output signal.
  • the voltage of the scan signal is VH. Due to the bootstrapping effect of the second capacitor C2, the voltage of the fourth node N4 becomes VL-VthNl.
  • the second input transistor T1 and the first input transistor T3 are both turned off under the control of the voltage of the first clock signal.
  • the voltage of the fourth node N4 becomes VL-VthNl.
  • the fourth control transistor T8 is turned on under the control of the first voltage signal.
  • the voltage of the first node N1 is also VL-VthNl.
  • the first control transistor T2 is on.
  • the first node N1 is turned on under the control of the second node N1 to transmit the first clock signal to the second node N2, that is, the voltage of the second node N2 is VH. Therefore, the first output transistor T4 and the first control transistor T6 are connected at the second node N2. are cut off under the control of voltage.
  • the reset circuit 12 includes: a third input transistor R3, a fourth input transistor R1, a fifth control transistor R2, a sixth control transistor R6, a seventh control transistor R7, an eighth control transistor Transistor R8, second output transistor R4, fourth output transistor R5, third capacitor C10 and fourth capacitor C20.
  • control electrode of the third input transistor R3 is electrically connected to the third clock signal terminal CK2
  • first electrode of the third input transistor R3 is electrically connected to the third voltage signal terminal VL2
  • the third input transistor R3 is electrically connected to the third voltage signal terminal VL2.
  • the second pole of the input transistor R3 is electrically connected to the sixth node N6.
  • the third input transistor R3 is configured to be turned on under the control of the third clock signal to transmit the third voltage signal to the sixth node N6.
  • the control electrode of the fourth input transistor R1 is electrically connected to the third clock signal terminal CK2
  • the first electrode of the fourth input transistor R1 is electrically connected to the second input signal terminal RI
  • the fourth input transistor R1 is electrically connected to the second input signal terminal RI.
  • the second pole of the input transistor R1 is electrically connected to the fifth node N5.
  • the fourth input transistor R1 is configured to be turned on under the control of the third clock signal to transmit the second input signal to the fifth node N5.
  • control electrode of the fifth control transistor R2 is electrically connected to the fifth node N5
  • first electrode of the fifth control transistor R2 is electrically connected to the third clock signal terminal CK2
  • the fifth control transistor R2 is electrically connected to the third clock signal terminal CK2
  • the second pole of R2 is electrically connected to the sixth node N6.
  • the fifth control transistor R2 is configured to be turned on under the control of the third clock signal, and transmit the third clock signal to the sixth node N6.
  • control electrode of the sixth control transistor R6 is electrically connected to the sixth node N6, the first electrode of the sixth control transistor R6 is electrically connected to the fourth voltage signal terminal VH2, and the sixth control transistor R6 The second pole of R6 is electrically connected to the seventh node N7.
  • the sixth control transistor R6 is configured to be turned on under the control of the sixth node N6 to transmit the fourth voltage signal to the seventh node N7.
  • control electrode of the seventh control transistor R7 is electrically connected to the fourth clock signal terminal CB2
  • first electrode of the seventh control transistor R7 is electrically connected to the seventh node N7
  • the seventh control transistor R7 The second pole of R7 is electrically connected to the fifth node N5.
  • the seventh control transistor R7 is configured to be turned on under the control of the fourth clock signal to transmit the voltage of the seventh node N7 to the fifth node N5.
  • control electrode of the eighth control transistor R8 is electrically connected to the third voltage signal terminal VL2
  • first electrode of the eighth control transistor R8 is electrically connected to the fifth node N5
  • eighth control transistor R8 The second pole of R8 is electrically connected to the eighth node N8.
  • the eighth control transistor R8 is configured to be turned on under the control of the third voltage signal to transmit the voltage of the fifth node N5 to the eighth node N8.
  • the control electrode of the second output transistor R4 is electrically connected to the sixth node N6
  • the first electrode of the second output transistor R4 is electrically connected to the fourth voltage signal terminal VH2
  • the second output transistor R4 is electrically connected to the fourth voltage signal terminal VH2
  • the second pole of R4 is electrically connected to the reset signal output terminal RO.
  • the first plate of the third capacitor C10 is electrically connected to the fourth voltage signal terminal VH2, and the second plate of the third capacitor C10 is electrically connected to the sixth node N6.
  • the second output transistor R4 is configured to be turned on under the control of the sixth node N6 to transmit the fourth voltage signal to the reset signal output terminal RO.
  • the third capacitor C10 is configured to maintain the voltage of the sixth node N6.
  • control electrode of the fourth output transistor R5 is electrically connected to the eighth node N8
  • first electrode of the fourth output transistor R5 is electrically connected to the fourth clock signal terminal CB2
  • fourth output transistor R5 The second pole of R5 is electrically connected to the reset signal output terminal RO.
  • the first plate of the fourth capacitor C20 is electrically connected to the reset signal output terminal RO
  • the second plate of the fourth capacitor C20 is electrically connected to the eighth node N8.
  • the fourth output transistor R5 is configured to be turned on under the control of the eighth node N8 to transmit the fourth clock signal to the reset signal output terminal RO.
  • the fourth capacitor C20 is configured to maintain the voltage of the eighth node N8.
  • the structure of the reset circuit 12 is the same as that of the scan circuit 11 , and the working principle of the reset circuit 12 is the same as or similar to that of the reset circuit 12 .
  • the working principle of the reset circuit 12 can be referred to the working principle of the scanning circuit 11 in the above embodiment, and will not be described again here.
  • Some embodiments of the present disclosure also provide a scan driving circuit 100, as shown in FIG. 5, including a plurality of shift registers 10 as described in the above embodiments.
  • the scan circuits 11 in multiple shift registers 10 are cascaded with each other, and the reset circuits 12 in multiple shift registers 10 are cascaded with each other. There is no cascade relationship between the scanning circuit 11 and the reset circuit 12 .
  • the scanning signal output terminal GO of the scanning circuit 11 of the a-th shift register is electrically connected to the first input signal terminal GI of the scanning circuit 11 of the a+1-th shift register. That is, the scanning signal output terminal GO of the scanning circuit 11 of the a-th shift register is electrically connected.
  • the scanning signal output by the scanning circuit 11 of the bit register can be used as the first input signal of the scanning circuit 11 of the a+1th shift register.
  • a is a positive integer.
  • the reset signal output terminal RO of the reset circuit 12 of the a-th shift register is electrically connected to the second input signal terminal RI of the reset circuit 12 of the a+1-th shift register, that is, the a-th
  • the reset signal output by the reset circuit 12 of the shift register can be used as the second input signal of the reset circuit 12 of the a+1th shift register.
  • the scanning circuits 11 in the multiple shift registers 10 are arranged sequentially along the column direction Y, for example, in a row.
  • Each reset circuit 12 in the plurality of shift registers 10 is arranged sequentially along the column direction, for example, in a row.
  • the scan circuit 11 and the reset circuit 12 can be arranged in a regular manner, which facilitates wiring layout and helps reduce the area occupied by the shift register 10 and the scan drive circuit 100 .
  • the scan driving circuit further includes: a first voltage signal line VGL1, a second voltage signal line VGH1, a third voltage signal line VGL2 and a fourth voltage signal line VGH2.
  • the first voltage signal line VGL1 extends along the column direction Y and is electrically connected to the first voltage signal terminal VL1 of the scanning circuit 11.
  • the first voltage signal line VGL1 provides a first voltage signal to the first voltage signal terminal VL1 of the scanning circuit 11 .
  • the second voltage signal line VGH1 extends along the column direction Y and is electrically connected to the second voltage signal terminal VH1 of the scanning circuit 11 .
  • the second voltage signal line VGH1 provides a second voltage signal to the second voltage signal terminal VH1 of the scanning circuit 11 .
  • the third voltage signal line VGL2 extends along the column direction Y and is electrically connected to the third voltage signal terminal VL2 of the reset circuit 12 .
  • the third voltage signal line VGL2 provides a third voltage signal to the third voltage signal terminal VL2 of the reset circuit 12 .
  • the fourth voltage signal line VGH2 extends along the column direction Y and is electrically connected to the fourth voltage signal terminal VH2 of the reset circuit 12 .
  • the fourth voltage signal line VGH2 provides a fourth voltage signal to the fourth voltage signal terminal VH2 of the reset circuit 12 .
  • the first voltage signal line VGL1, the second voltage signal line VGH1, the third voltage signal line VGL2 and the fourth voltage signal line VGH2 all extend along the column direction Y, which can save the area and space occupied by the scan driving circuit 100 in the display substrate 1000. , which is beneficial to the narrow frame design of the display substrate 1000.
  • the scan circuit 11 is provided between the first voltage signal line VGL1 and the second voltage signal line VGH1
  • the reset circuit 12 is provided between the third voltage signal line VGL2 and the second voltage signal line VGL2. between the four voltage signal lines VGH2.
  • the first voltage signal line VGL1 and the second voltage signal line VGH1 are arranged on both sides of the scanning circuit 11 , and arranging the third voltage signal line VGL2 and the fourth voltage signal line VGH2 on both sides of the reset circuit 12 , not only can avoid A parasitic capacitance is formed between the first voltage signal line VGL1 and the second voltage signal line VGH1 to avoid the parasitic capacitance between the third voltage signal line VGL2 and the fourth voltage signal line VGH2, and the first voltage signal line VGL1 , the second voltage signal line VGH1, the third voltage signal line VGL2, and the fourth voltage signal line VGH2 are arranged relatively closely, which is conducive to saving wiring space, facilitating signal transmission, and is conducive to the narrow frame design of the display substrate 1000.
  • the second voltage signal line VGH1 and the third voltage signal line VGL2 are provided between the scan circuit 11 and the reset circuit 12 .
  • the first voltage signal line VGL1 is provided on the side of the scanning circuit 11 away from the multiple rows of sub-pixels
  • the fourth voltage signal line VGH2 is provided on the side of the reset circuit 12 close to the multiple rows of sub-pixels.
  • the distance between the second voltage signal line VGH1 and the first pole of the first output transistor T4 in the scanning circuit 11 can be shortened, and the distance between the third voltage signal line VGL2 and the third input transistor R3 in the reset circuit 12 can be shortened.
  • the distance between the first pole of the first voltage signal line VGL1 and the first pole of the first input transistor T3 in the scanning circuit 11 can be shortened, and the distance between the fourth voltage signal line VGH2 and the reset circuit 12 can be shortened.
  • the distance between the first poles of the second output transistor R4 not only helps to simplify the wiring difficulty, but also saves the area and space occupied by the scan driving circuit 100 in the row direction X, which is beneficial to realizing the narrow frame design of the display substrate 1000 .
  • the scan driving circuit 100 further includes: a first clock signal line CKL1, a second clock signal line CBL1, a third clock signal line CKL2, and a fourth clock signal line CBL2.
  • the first clock signal line CKL1 extends along the column direction Y and is electrically connected to the first clock signal terminal CK1 of the 2m-1th scanning circuit 11 and the second clock signal terminal CB1 of the 2mth scanning circuit 12, m is a positive integer.
  • the second clock signal line CBL1 extends along the column direction Y and is electrically connected to the second clock signal terminal CB1 of the 2m-1th scanning circuit and the first clock signal terminal CK1 of the 2mth scanning circuit, m is positive. integer.
  • the third clock signal line CKL2 extends along the column direction Y and is electrically connected to the third clock signal terminal CK2 of the 2m-1th reset circuit 12 and the fourth clock signal terminal CB2 of the 2mth reset circuit 12, m is a positive integer.
  • the fourth clock signal line CBL2 extends along the column direction Y and is electrically connected to the fourth clock signal terminal CB2 of the 2m-1th reset circuit 12 and the third clock signal terminal CK2 of the 2mth reset circuit 12, m is a positive integer.
  • the first clock signal line CKL1, the second clock signal line CBL1, the third clock signal line CKL2 and the fourth clock signal line CBL2 all extend along the column direction Y, which is beneficial to reducing the size of the scan driving circuit.
  • the area and space occupied by the display substrate 100 are beneficial to the narrow frame design of the display substrate 1000 .
  • the first clock signal line CKL1 and the second clock signal line CBL1 are provided on a side of the scanning circuit 11 away from the reset circuit 12 .
  • the third clock signal line CKL2 and the fourth clock signal line CBL2 are provided on the side of the reset circuit 12 close to the scanning circuit 11 .
  • the first clock signal line CKL1 , the second clock signal line CBL1 and the first voltage signal line VGL1 are provided on the same side of the scanning circuit 12 , for example, the first voltage signal line
  • the line VGL1 can be located between the first clock signal line CKL1 and the scanning circuit 12, and is closer to the scanning circuit 12, so that the control electrode of the first control transistor T2 and the control electrode of the first input transistor T3 can be shortened to the first clock
  • the length of the connection line of the signal line CKL1 can be shortened from the control electrode of the third control transistor T7 to the second clock signal line CBL1, and the length of the connection line from the first electrode of the first input transistor T3 to the first voltage signal can be shortened.
  • the length of the connection line of the line VGL1 can thereby reduce the area and space occupied by the scanning circuit 11, thereby reducing the area and space occupied by the scanning driving circuit 100 on the display substrate 1000, thereby achieving a narrow frame design of the display substrate 1000;
  • the third clock The signal line CKL2, the fourth clock signal line CBL2 and the third voltage signal line VGL2 are provided on the same side of the reset circuit 12.
  • the third voltage signal line VGL2 may be located between the third clock signal line CKL2 and the reset circuit 12, and It is closer to the reset circuit 12, so that the control electrode of the fifth control transistor R2 and the length of the connection line from the control electrode of the third input transistor R3 to the third clock signal line CKL2 can be shortened, and the length of the third input transistor R3 can be shortened.
  • the length of the connection line from one pole to the third voltage signal line VGL2 can save the area and space occupied by the reset circuit 12, thereby reducing the area and space occupied by the scan driving circuit 100 on the display substrate 1000, and realizing the display substrate 1000. Narrow bezel design.
  • the scan driving circuit 100 further includes: a first initial signal line GSTV and a second initial signal line RSTV.
  • the first initial signal line GSTV extends along the column direction Y and is electrically connected to the first input signal terminal GI of the scanning circuit 11 of the first n shift registers 10 among the plurality of shift registers 10; n is a positive integer.
  • the first initial signal line GSTV is electrically connected to the first input signal terminal GI of the scanning circuit 11 of the first shift register among the plurality of shift registers 10 .
  • the first initial signal transmitted by the first initial signal line GSTV can be used as the first input signal of the scanning circuit 11 of the first shift register.
  • the second initial signal line RSTV extends along the column direction Y and is electrically connected to the second input signal terminal RI of the reset circuit 12 of the first i shift register 10 among the plurality of shift registers; i is a positive integer.
  • the second initial signal line RSTV is electrically connected to the second input signal terminal RI of the reset circuit 12 of the first shift register 10 among the plurality of shift registers 10 .
  • the second initial signal transmitted by the second initial signal line RSTV can be used as the second input signal of the reset circuit 12 of the first shift register.
  • the first initial signal line GSTV is provided on the side of the scanning circuit 11 away from the reset circuit 12; the second initial signal line RSTV is provided on the side of the reset circuit 12 close to the scanning circuit. 11 side.
  • the distance between the first pole of the second input transistor T1 of the scanning circuit 11 and the first initial signal line GSTV is small, and the distance between the first pole of the second input transistor T1 and the first initial signal line GSTV can be shortened.
  • the length of the connecting line between them; the distance between the first pole of the fourth input transistor R1 of the reset circuit 12 and the second initial signal line RSTV is small, and the distance from the first pole of the fourth input transistor R1 to the second initial signal line RSTV can be shortened.
  • the length of the connection line between the signal lines RSTV is small, which can reduce the area and space occupied by the scan driving circuit 100 on the display substrate 1000 and achieve a narrow frame design of the display substrate 1000 .
  • the number of scan driving circuits 100 in the display substrate 1000 may be one. At this time, the scan driving circuit 100 is located on one side of the display substrate.
  • the number of scan driving circuits 100 in the display substrate 1000 is two.
  • the two scan driving circuits 100 are respectively located on opposite sides of the multiple rows of sub-pixels Row. Based on this, the two scan drive circuits 100 can work alternately and alternately provide scan signals and reset signals to sub-pixels, which is beneficial to reducing the load of the scan drive circuit 100 and extending the working life of the scan drive circuit 100 .
  • the scan driving circuit 100 may be composed of multiple laminated film layers. Each film layer has a pattern.
  • the display substrate 1000 further includes: a semiconductor layer Poly disposed on the substrate 200 , and a semiconductor layer Poly disposed on a side away from the substrate 200 The first gate conductive layer Gate1.
  • the material of the semiconductor layer Poly may include amorphous silicon, single crystal silicon, polycrystalline silicon or metal oxide semiconductor materials.
  • the first output transistor T4 of the scanning circuit 11 includes: a first active layer t4; the first active layer t4 includes a first channel portion t42.
  • the second output transistor R4 of the reset circuit includes: a second active layer r4; the second active layer r4 includes a second channel portion r42.
  • the first active layer t4 and the second active layer r4 are both located on the semiconductor layer Poly. That is, the first active layer t4 and the second active layer r4 are arranged on the same layer.
  • the "same layer” mentioned in this disclosure refers to a layer structure formed by using the same film formation process to form a film layer for forming a specific pattern, and then using the same mask to form a patterning process.
  • a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights. Or have different thicknesses.
  • the first active layer t4 and the second active layer r4 can be manufactured at the same time, which is beneficial to simplifying the manufacturing process of the display substrate 1000 .
  • the orthographic projection of the semiconductor layer Poly on the substrate 200 overlaps with the orthographic projection of the first gate conductive layer Gate1 on the substrate 200 .
  • the part of the semiconductor layer Poly covered by the first gate conductive layer Gate1 constitutes the channel part of each transistor
  • the part of the semiconductor layer Poly not covered by the first gate conductive layer Gate1 is the conductive part and constitutes the third channel part of each transistor.
  • the channel portion has a channel length and a channel width.
  • the channel length of the channel portion refers to the spacing dimension between the first electrode and the second electrode of the transistor.
  • the channel width of the channel portion refers to the size of the channel portion in a direction perpendicular to the first pole of the transistor and toward the second pole.
  • the channel width of the first channel portion t42 is greater than or equal to the channel width of the second channel portion r42.
  • the channel width of the first channel portion t42 may be greater than the channel width of the second channel portion r42 .
  • the size of the first channel portion t42 along the row direction X is larger than the size of the second channel portion r42 along the row direction X.
  • a higher operating current can be obtained by increasing the channel width of the first output transistor T4, and the increase in the operating current represents an enhancement of the writing capability and retention capability, thereby reducing the power consumption of the display substrate.
  • the channel width of the first channel portion t42 may also be equal to the channel width of the second channel portion r42.
  • the third output transistor T5 of the scanning circuit 11 includes: a third active layer t5.
  • the third active layer t5 includes a third channel portion (t52, t54, and t56 shown in FIG. 13).
  • the fourth output transistor R5 of the reset circuit 12 includes: a fourth active layer r5; the fourth active layer r5 includes a fourth channel portion (r42, r44, and r46 shown in FIG. 20).
  • the third active layer t5 and the fourth active layer r5 are both located on the semiconductor layer Poly, that is, the third active layer t5 and the fourth active layer r5 are arranged on the same layer. In this way, the third active layer t5 and the fourth active layer r5 can be manufactured at the same time, which is beneficial to simplifying the manufacturing process of the display substrate 1000 .
  • the channel width of the third channel part is greater than or equal to the channel width of the fourth channel part.
  • the channel width of the third channel portion may be greater than the channel width of the fourth channel portion. What is meant here is that the size of the third channel portion along the row direction X is larger than the size of the fourth channel portion along the row direction X.
  • a higher operating current can be obtained by increasing the channel width of the third output transistor T5, and the increase in the operating current represents an enhancement of the writing capability and retention capability, thereby reducing the power consumption of the display substrate.
  • the width of the fourth channel portion may be equal to the width of the third channel portion.
  • the channel width direction of the third channel portion and the fourth channel portion can be set in various situations and can be set according to actual conditions.
  • the first active layer t4 and the third active layer t5 are sequentially arranged along the column direction Y.
  • the above arrangement can effectively reduce the distance between the first active layer t4 and the third active layer t5 in the column direction Y, reduce the area occupied by the scan driving circuit 100 on the display substrate 1000, and is conducive to realizing the display substrate 1000. narrow bezel design.
  • the first active layer t4 and the third active layer t5 have an integrated structure.
  • the first active layer t4 may be composed of a plurality of rectangular blocks spaced at a certain distance
  • the third active layer t5 may also be composed of a plurality of rectangular blocks spaced at a certain distance
  • the first active layer t4 may be composed of a plurality of rectangular blocks spaced at a certain distance.
  • the rectangular block of layer t4 is correspondingly integrated with the rectangular block of the third active layer t5 to form a new rectangular block.
  • the size of the first active layer t4 and the third active layer t5 in the column direction Y can be reduced, thereby reducing the size of the first active layer t4 and the third active layer t5.
  • the area occupied by the scan driving circuit 100 on the display substrate 1000 can be further reduced, which is beneficial to realizing a narrow frame design of the display substrate 1000 .
  • the second active layer r4 and the fourth active layer r5 are arranged sequentially along the column direction Y.
  • the above arrangement can effectively reduce the distance between the second active layer r4 and the fourth active layer r5 on Y, reduce the area occupied by the scan driving circuit 100 on the display substrate 1000, and is conducive to realizing a narrow display substrate 1000. Border design.
  • the second active layer r4 and the fourth active layer r5 have an integrated structure.
  • the second active layer r4 can be composed of multiple rectangular blocks spaced at a certain distance
  • the fourth active layer r5 can also be composed of multiple rectangular blocks spaced at a certain distance.
  • the rectangular block of layer r4 is correspondingly integrated with the rectangular block of the fourth active layer r5 to form a new rectangular block.
  • the first input transistor T3 of the scanning circuit 11 includes: a fifth active layer t3 .
  • the fifth active layer t3 is disposed on a side of the first active layer t4 away from the multiple rows of sub-pixels.
  • the first control transistor T2 of the scanning circuit 11 includes: a sixth active layer t2.
  • the sixth active layer t2 is disposed on a side of the first active layer t4 away from the multiple rows of sub-pixels.
  • the second control transistor T6 of the scanning circuit 11 includes: a seventh active layer t6.
  • the seventh active layer t6 is provided between the fifth active layer t3 and the first active layer t4.
  • the third control transistor T7 of the scanning circuit 11 includes: an eighth active layer t7.
  • the eighth active layer t7 is provided between the fifth active layer t3 and the first active layer t4.
  • the fourth control transistor T8 of the scanning circuit 11 includes: a ninth active layer t8.
  • the ninth active layer t8 is provided between the fifth active layer t3 and the eighth active layer t7.
  • the fifth active layer t3, the sixth active layer t2, the seventh active layer t6, the eighth active layer t7, and the ninth active layer t8 are all located on the semiconductor layer Poly.
  • the fifth active layer t3, the sixth active layer t2, the seventh active layer t6, the eighth active layer t7 and the ninth active layer t8 are in the same layer and have the same material, which facilitates reduction of process flow.
  • the channel length direction of the fifth active layer t3, the channel length direction of the sixth active layer t2, the channel length direction of the seventh active layer t6, and the channel length of the eighth active layer t7 direction and the channel length direction of the ninth active layer t8 are both arranged along the column direction Y.
  • the above arrangement can reduce the area occupied by each channel portion in the row direction
  • the fifth active layer t3 and the sixth active layer t2 are sequentially arranged along the column direction Y to form an integrated structure.
  • the fifth active layer t3 and the sixth active layer t2 are arranged sequentially along the column direction Y, which can reduce the size and area occupied by the fifth active layer t3 and the sixth active layer t2 in the row direction X.
  • the fifth active layer t3 and the sixth active layer t2 have an integrated structure, so that there is no gap between the fifth active layer t3 and the sixth active layer t2, which can reduce the number of the fifth active layer t3 and the sixth active layer t2.
  • the size and area occupied by the active layer t2 in the column direction Y can further reduce the area ratio of the scan driving circuit 100 on the display substrate 1000, thereby enabling a narrow frame design of the display substrate 1000 and simplifying the display substrate 1000.
  • the seventh active layer t6 and the eighth active layer t7 are sequentially arranged along the column direction Y to form an integrated structure.
  • the seventh active layer t6 and the eighth active layer t7 are arranged sequentially along the column direction Y, which can reduce the size and area occupied by the seventh active layer t6 and the eighth active layer t7 in the row direction X.
  • the seventh active layer t6 and the eighth active layer t7 have an integrated structure, so that there is no gap between the seventh active layer t6 and the eighth active layer t7, which can reduce the number of the seventh active layer t6 and the eighth active layer t7.
  • the size and area occupied by the active layer t7 in the column direction Y can further reduce the area ratio of the scan driving circuit 100 on the display substrate 1000, thereby enabling a narrow frame design of the display substrate 1000 and simplifying the display substrate 1000.
  • the third input transistor R3 of the reset circuit 12 includes: a tenth active layer r3.
  • the tenth active layer r3 is disposed on a side of the second active layer r4 away from the multiple rows of sub-pixels.
  • the fifth control transistor R2 of the reset circuit 12 includes: an eleventh active layer r2.
  • the eleventh active layer r2 is disposed on a side of the second active layer r4 away from the multiple rows of sub-pixels.
  • the sixth control transistor R6 of the reset circuit 12 includes: a twelfth active layer r6.
  • the twelfth active layer r6 is provided between the tenth active layer r3 and the second active layer r4.
  • the seventh control transistor R7 of the reset circuit 12 includes: a thirteenth active layer r7.
  • the thirteenth active layer r7 is provided between the tenth active layer r3 and the second active layer r4.
  • the eighth control transistor R8 of the reset circuit 12 includes: a fourteenth active layer r8.
  • the fourteenth active layer r8 is provided between the tenth active layer r3 and the thirteenth active layer r7.
  • the tenth active layer r3, the eleventh active layer r2, the twelfth active layer r6, the thirteenth active layer r7, and the fourteenth active layer r8 are all located on the semiconductor layer Poly. Therefore, each of the above-mentioned active layers can be prepared at the same time, simplifying the preparation process of the display substrate 1000 .
  • the channel length direction of the tenth active layer r3, the channel length direction of the eleventh active layer r2, the channel length direction of the twelfth active layer r6, and the channel length direction of the thirteenth active layer r7 are both arranged along the column direction Y. Therefore, the width occupied by the active layer in the row direction X can be reduced, which is beneficial to the narrow frame design of the display substrate 1000 .
  • the tenth active layer r3 and the eleventh active layer r2 are arranged sequentially along the column direction Y to form an integrated structure.
  • the tenth active layer r3 and the eleventh active layer r2 are arranged sequentially along the column direction Y, which can reduce the size occupied by the tenth active layer r3 and the eleventh active layer r2 in the row direction X. and area, and the tenth active layer r3 and the eleventh active layer r2 have an integrated structure, so that there is no gap between the tenth active layer r3 and the eleventh active layer r2, which can reduce the tenth active layer
  • the size and area occupied by r3 and the eleventh active layer r2 in the column direction Y can further reduce the area ratio of the scan driving circuit 100 on the display substrate 1000, thereby enabling a narrow frame design of the display substrate 1000.
  • the preparation process of the display substrate 1000 is simplified.
  • the twelfth active layer r6 and the thirteenth active layer r7 are arranged sequentially along the column direction Y to form an integrated structure.
  • the twelfth active layer r6 and the thirteenth active layer r7 are arranged sequentially along the column direction Y, which can reduce the occupation of the twelfth active layer r6 and the thirteenth active layer r7 in the row direction X
  • the size and area of the twelfth active layer r6 and the thirteenth active layer r7 have an integrated structure, so that there is no gap between the twelfth active layer r6 and the thirteenth active layer r7, which can reduce the
  • the size and area occupied by the twelve active layers r6 and the thirteenth active layer r7 in the column direction Y can further reduce the area ratio of the scan driving circuit 100 on the display substrate 1000, thereby realizing the display substrate 1000.
  • the narrow frame design also simplifies the preparation process of the display substrate 1000.
  • the overlapping portions of the first gate conductive layer Gate1 and the semiconductor layer Poly form the control electrode of the first input transistor T3, the control electrode of the second input transistor T1, the control electrode of the first control transistor T2, and the second control electrode respectively.
  • the first gate conductive layer Gate1 forms the second electrode of the first capacitor C1, the second electrode of the second capacitor C2, the second electrode of the third capacitor C10 and the second electrode of the fourth capacitor C20.
  • the material of the first gate conductive layer Gate1 includes conductive metal.
  • the conductive metal may include at least one of aluminum, copper, and molybdenum, and the present disclosure is not limited thereto.
  • a first gate insulating layer is disposed between the semiconductor layer Poly and the first gate conductive layer Gate1, and the first gate insulating layer is used to electrically insulate the semiconductor layer Poly and the first gate conductive layer Gate1.
  • the material of the first gate insulating layer includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide.
  • the material of the first gate insulating layer may include silicon dioxide, and the present disclosure is not limited thereto.
  • the display substrate 1000 includes: a second gate conductive layer Gate2 disposed on a side of the semiconductor layer Poly away from the substrate 200 .
  • the second gate conductive layer Gate2 may be made of the same material as the first gate conductive layer Gate1.
  • the first plate of the second capacitor C2 of the scanning circuit 11 is located on the second gate conductive layer Gate2.
  • the first plate of the fourth capacitor C20 of the reset circuit 12 is located on the second gate conductive layer Gate2.
  • the first plates of the first capacitor C1, the second capacitor C2, the third capacitor C10, and the fourth capacitor C20 may all be located on the second gate conductive layer Gate2. Therefore, the manufacturing process flow of the display substrate 1000 can be simplified.
  • the scanning signal output terminal GO of the scanning circuit 11 and the first plate of the second capacitor C2 form an integrated structure. Therefore, the manufacturing process of the scanning circuit 11 can be simplified, thereby simplifying the manufacturing process of the display substrate 1000 .
  • the reset signal output terminal RO of the reset circuit 12 and the first plate of the fourth capacitor C20 form an integrated structure. Therefore, the manufacturing process of the reset circuit 12 can be simplified, thereby simplifying the manufacturing process of the display substrate 1000 .
  • the display substrate 1000 further includes: a source-drain conductive layer SD disposed on a side of the second gate conductive layer Gate2 away from the substrate 200 .
  • the second electrode of the first output transistor T4 and the second electrode of the third output transistor T5 have an integrated structure, and both are located on the source-drain conductive layer SD. Therefore, the manufacturing process of the scanning circuit 11 can be simplified, thereby simplifying the manufacturing process of the display substrate 1000 .
  • the second electrode of the second output transistor R4 and the second electrode of the fourth output transistor R5 have an integrated structure, and both are located on the source-drain conductive layer SD. Therefore, the manufacturing process of the reset circuit 12 can be simplified, thereby simplifying the manufacturing process of the display substrate 1000 .
  • the second pole of the first output transistor T4 is electrically connected to the first plate of the second capacitor C2.
  • the scanning signal output terminal GO of the scanning circuit 11 and the first plate of the second capacitor C2 form an integrated structure.
  • the second electrode of the first output transistor T4 is electrically connected to the first plate of the second capacitor C2 through a via hole. Since the scanning signal output terminal GO and the first plate of the second capacitor C2 have an integrated structure, the second pole of the first output transistor T4 can be electrically connected to the scanning signal output terminal GO.
  • the second pole of the second output transistor R4 is electrically connected to the first plate of the fourth capacitor C20.
  • the reset signal output terminal RO of the reset circuit 12 and the first plate of the fourth capacitor C20 form an integrated structure.
  • the second electrode of the second output transistor R4 is electrically connected to the first plate of the fourth capacitor C20 through a via hole. Since the reset signal output terminal RO of the reset circuit 12 and the first plate of the fourth capacitor C20 have an integrated structure, the second pole of the second output transistor R4 can be electrically connected to the reset signal output terminal RO.
  • a second gate insulating layer is disposed between the second gate conductive layer Gate2 and the first gate conductive layer Gate1.
  • the second gate insulating layer is used to electrically insulate the second gate conductive layer Gate2 and the first gate conductive layer Gate1.
  • the material of the second gate insulating layer Gate2 includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide.
  • the material of the second gate insulating layer may include silicon dioxide, and the present disclosure is not limited thereto.
  • a third gate insulating layer is disposed between the second gate conductive layer Gate2 and the source-drain conductive layer SD.
  • the third gate insulation layer is used to electrically insulate the second gate conductive layer Gate2 and the source-drain conductive layer SD.
  • the material of the third gate insulating layer includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide.
  • the material of the third gate insulating layer may include silicon dioxide, and the present disclosure is not limited thereto.
  • the source-drain conductive layer SD can be connected to the conductive portion of each active layer provided on the semiconductor layer Poly through via holes on the third gate insulating layer, the second gate insulating layer, and the first gate insulating layer, The first and second poles of each transistor are formed.
  • FIG. 11 shows a partial cross-sectional view of the film layer of the display panel 1000 after being cut along the A-A' direction in FIG. 10 .
  • the second input transistor T1 has a double-gate structure, that is, the second input transistor T1 includes two gates g1.
  • the active layer t1 of the second input transistor T1 includes two channel portions ( t12 and t14).
  • FIG. 12 shows a partial cross-sectional view of the film layer of the display panel 1000 after being cut along the B-B′ direction in FIG. 11 .
  • the control electrode g6 of the second control transistor T6 is electrically connected to one end of the first transfer part e1, and the other end of the first connection part e1 is electrically connected to the first electrode d3 of the first input transistor T3, thereby realizing the second control transistor
  • the control electrode g6 of T6 is electrically connected to the first electrode d3 of the first input transistor T3.
  • the above-mentioned first transfer part e1 may be located on the source-drain conductive layer SD, and the electrical connection between one end of the first transfer part e1 and the control electrode g6 of the second control transistor T6 may be realized through a via hole.
  • FIG. 19 shows a partial cross-sectional view of the film layer of the display panel 1000 after being cut along the C-C' direction in FIG. 18 .
  • the control electrode rg6 of the sixth control transistor R6 is electrically connected to one end of the second switching part e2, and the other end of the second switching part e2 is electrically connected to the first pole rd3 of the third input transistor R3, thereby realizing connection with the third switching part e2.
  • the second transfer part e2 can be divided into three parts.
  • the first part of the second transfer part e2 is located on the source-drain conductive layer SD, and one end of this part is electrically connected to the control electrode rg6 of the sixth control transistor R6 through a via hole;
  • the second part of the second transfer part e2 is located on the second gate conductive layer Gate2, and one end of the second part is electrically connected to the other end of the first part of the second transfer part e2 through a via hole; the second part of the second transfer part e2
  • the three parts are located in the source-drain conductive layer SD. One end of this part is electrically connected to the other end of the second part of the second transfer part e2 through a via hole, and the other end of this part is electrically connected to the first pole rd3 of the third input transistor R3. connect.
  • the control electrode of the second control transistor T6 and the first electrode d3 of the first input transistor T3 can also be electrically connected by the control electrode of the sixth control transistor R6 and the third electrode of the third input transistor R3 shown in FIG. 19 .
  • One pole rd3 way of electrical connection.
  • the control electrode of the sixth control transistor R6 and the first electrode rd3 of the third input transistor R3 can also be electrically connected by using the control electrode of the second control transistor T6 and the third electrode of the first input transistor T3 shown in FIG. 12 .
  • One pole d3 is electrically connected.

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Abstract

一种移位寄存器，应用于显示基板，显示基板包括多行子像素；移位寄存器，与至少一行子像素电连接，且被配置为向至少一行子像素传输扫描信号和复位信号；其中，移位寄存器包括：扫描电路，以及，复位电路。扫描电路被配置为，在第一输入信号、第一时钟信号、第二时钟信号、第一电压信号及第二电压信号的配合作用下，输出扫描信号；复位电路被配置为，在第二输入信号、第三时钟信号、第四时钟信号、第三电压信号及第四电压信号的配合作用下，输出复位信号；其中，扫描电路和复位电路之间相互独立输出信号。

Description

移位寄存器、扫描驱动电路及显示基板 技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器、扫描驱动电路及显示基板。
背景技术
随着显示技术的进步，作为显示基板核心的半导体元件技术也随之得到了很大的进步。有机发光二极管(Organic Light Emitting Diode，OLED)作为一种电流型发光器件，因其所具有的自发光、快速响应、宽视角和可制作在柔性衬底上等特点，而越来越多地被应用于高性能显示基板当中。
发明内容
一方面，提供一种移位寄存器，应用于显示基板。所述显示基板包括多行子像素。所述移位寄存器，与一行子像素电连接，且被配置为向所述一行子像素传输扫描信号和复位信号。其中，所述移位寄存器包括：扫描电路，与第一输入信号端、第一时钟信号端、第二时钟信号端、第一电压信号端及第二电压信号端电连接；所述扫描电路被配置为，在所述第一输入信号端所传输的第一输入信号、所述第一时钟信号端所传输的第一时钟信号、所述第二时钟信号端所传输的第二时钟信号、所述第一电压信号端所传输的第一电压信号及所述第二电压信号端所传输的第二电压信号的配合作用下，输出所述扫描信号；以及，复位电路，与第二输入信号端、第三时钟信号端、第四时钟信号端、第三电压信号端及第四电压信号端电连接；所述复位电路被配置为，在所述第二输入信号端所传输的第二输入信号、所述第三时钟信号端所传输的第三时钟信号、所述第四时钟信号端所传输的第四时钟信号、所述第三电压信号端所传输的第三电压信号及所述第四电压信号端所传输的第四电压信号的配合作用下，输出所述复位信号。其中，所述扫描电路和所述复位电路之间相互独立输出信号。
在一些实施例中，所述扫描电路包括：第一输出晶体管。所述第一输出晶体管的第一极与所述第二电压信号端电连接，所述第一输出晶体管的第二极与扫描信号输出端电连接。所述复位电路包括：第二输出晶体管。所述第二输出晶体管的第一极与所述第四电压信号端电连接，所述第二输出晶体管的第二极与复位信号输出端电连接。其中，所述第一输出晶体管的沟道宽度，大于或等于所述第二输出晶体管的沟道宽度。
在一些实施例中，所述第一输出晶体管的沟道宽度与所述第二输出晶体管的沟道宽度的比例范围为1:1～20:1。
在一些实施例中，所述扫描电路包括：第三输出晶体管。所述第三输出晶体管的第一极与所述第二时钟信号端电连接，所述第三输出晶体管的第二极与扫描信号输出端电连接。所述复位电路包括：第四输出晶体管。所述第四输出晶体管的第一极与所述第四时钟信号端电连接，所述第四输出晶体管的第二极与复位信号输出端电连接。其中，所述第三输出晶体管的沟道宽度，大于或等于所述第四输出晶体管的沟道宽度。
在一些实施例中，所述第三输出晶体管的沟道宽度与所述第四输出晶体管的沟道宽度的比例范围为1:1～20:1。
在一些实施例中，所述扫描电路和所述复位电路沿行方向并列设置；或者，所述扫描电路和所述复位电路沿所述行方向交错设置。
在一些实施例中，相比于所述扫描电路，所述复位电路更靠近所述一行子像素。
在一些实施例中，所述扫描电路包括：第一输入晶体管、第二输入晶体管、第一控制晶体管、第二控制晶体管、第三控制晶体管、第四控制晶体管、第一输出晶体管、第三输出晶体管、第一电容器和第二电容器。所述第一输入晶体管的控制极与所述第一时钟信号端电连接，所述第一输入晶体管的第一极与所述第一电压信号端电连接，所述第一输入晶体管的第二极与第二节点电连接。所述第二输入晶体管的控制极与所述第一时钟信号端电连接，所述第二输入晶体管的第一极与所述第一输入信号端电连接，所述第二输入晶体管的第二极与第一节点电连接。所述第一控制晶体管的控制极与所述第一节点电连接，所述第一控制晶体管的第一极与所述第一时钟信号端电连接，所述第一控制晶体管的第二极与所述第二节点电连接。所述第二控制晶体管的控制极与所述第二节点电连接，所述第二控制晶体管的第一极与所述第二电压信号端电连接，所述第二控制晶体管的第二极与第三节点电连接。所述第三控制晶体管的控制极与所述第二时钟信号端电连接，所述第三控制晶体管的第一极与所述第三节点电连接，所述第三控制晶体管的第二极与所述第一节点电连接。所述第四控制晶体管的控制极与所述第一电压信号端电连接，所述第四控制晶体管的第一极与所述第一节点电连接，所述第三控制晶体管的第二极与第四节点电连接。所述第一输出晶体管的控制极与所述第二节点电连接，所述第一输出晶体管的第一极与所述第二电压信号端电连接，所述第一输出晶体管的第二极与所述扫描信号输出端电连接。所述第三输出晶体管的控制极与所述第四节点电连接，所述第三输出晶体管的第一极与所述第二时钟信号端电连接，所述第三输出晶体管的第二极与所述扫描信号输出端电连接。所述第一电容器器的第一极板与所述第二电压信号端电连接，所述第一电容器的第二极板与所述第二节点电连接。所述第二电容器的第一极板与所述扫描信号输出端电连接，所述第二电容器的第二极板与所述第四节点电连接。
在一些实施例中，所述复位电路包括：第三输入晶体管、第四输入晶体管、第五控制晶体管、第六控制晶体管、第七控制晶体管、第八控制晶体管、第二输出晶体管、第四输出晶体管、第三电容器和第四电容器。所述第三输入晶体管的控制极与所述第三时钟信号端电连接，所述第三输入晶体管的第一极与所述第三电压信号端电连接，所述第三输入晶体管的第二极与第六节点电连接。所述第四输入晶体管的控制极与所述第三时钟信号端电连接，所述第四输入晶体管的第一极与所述第二输入信号端电连接，所述第四输入晶体管的第二极与第五节点电连接。所述第五控制晶体管的控制极与所述第五节点电连接，所述第五控制晶体管的第一极与所述第三时钟信号端电连接，所述第五控制晶体管的第二极与所述第六节点电连接。所述第六控制晶体管的控制极与所述第六节点电连接，所述第六控制晶体管的第一极与所述第四电压信号端电连接，所述第六控制晶体管的第二极与第七节点电连接。所述第七控制晶体管的控制极与所述第四时钟信号端电连接，所述第七控制晶体管的第一极与所述第七节点电连接，所述第七控制晶体管的第二极与所述第五节点电连接。所述第八控制晶体管的控制极与所述第三电压信号端电连接，所述第八控制晶体管的第一极与所述第五节点电连接，所述第八控制晶体管的第二极与第八节点电连接。所述第二输出晶体管的控制极与所述第六节点电连接，所述第二输出晶体管的第一极与所述第四电压信号端电连接，所述第二输出晶体管的第二极与所述复位信号输出端电连接。所述第四输出晶体管的控制极与所述第八节点电连接，所述第四输出晶体管的第一极与所述第四时钟信号端电连接，所述第四输出晶体管的第二极与所述复位信号输出端电连接。所述第三电容器器的第一极板与所述第四电压信号端电连接，所述第三电容器的第二极板与所述 第六节点电连接。所述第四电容器的第一极板与所述复位信号输出端电连接，所述第四电容器的第二极板与所述第八节点电连接。
另一方面，提供一种扫描驱动电路，包括：上述任一实施例所述的多个移位寄存器。其中，所述多个移位寄存器中各扫描电路沿列方向依次排列；所述多个移位寄存器中各复位电路沿所述列方向依次排列。
在一些实施例中，所述的扫描驱动电路，还包括：沿所述列方向延伸的第一电压信号线，与所述扫描电路的第一电压信号端电连接；沿所述列方向延伸的第二电压信号线，与所述扫描电路的第二电压信号端电连接；沿所述列方向延伸的第三电压信号线，与所述复位电路的第三电压信号端电连接；以及，沿所述列方向延伸的第四电压信号线，与所述复位电路的第四电压信号端电连接。其中，所述扫描电路设置在所述第一电压信号线和所述第二电压信号线之间，所述复位电路设置在所述第三电压信号线和所述第四电压信号线之间。
在一些实施例中，所述第二电压信号线和所述第三电压信号线，设置在所述扫描电路和所述复位电路之间。
在一些实施例中，所述扫描驱动电路，还包括：沿列方向延伸的第一时钟信号线，与第2m-1个所述扫描电路的第一时钟信号端及第2m个所述扫描电路的第二时钟信号端电连接；沿所述列方向延伸的第二时钟信号线，与第2m-1个所述扫描电路的第二时钟信号端及第2m个所述扫描电路的第一时钟信号端电连接；沿所述列方向延伸的第三时钟信号线，与第2m-1个所述复位电路的第三时钟信号端及第2m个所述复位电路的第四时钟信号端电连接；沿所述列方向延伸的第四时钟信号线，与第2m-1个所述复位电路的第四时钟信号端及第2m个所述复位电路的第三时钟信号端电连接；m为正整数。其中，所述第一时钟信号线和所述第二时钟信号线，设置在所述扫描电路远离所述复位电路的一侧；所述第三时钟信号线和所述第四时钟信号线，设置在所述复位电路靠近所述扫描电路的一侧。
在一些实施例中，所述扫描驱动电路，还包括：沿所述列方向延伸的第一初始信号线，与所述多个移位寄存器中前n个移位寄存器的扫描电路的第一输入信号端电连接；n为正整数；沿所述列方向延伸的第二初始信号线，与所述多个移位寄存器中前i个移位寄存器的复位电路的第二输入信号端电连接；i为正整数。所述第一初始信号线设置在所述扫描电路远离所述复位电路的一侧；所述第二初始信号线设置在所述复位电路靠近所述扫描电路的一侧。
另一方面，提供一种显示基板，包括：衬底；设置在所述衬底上的多行子像素；以及，设置在所述衬底上的、如上述任一实施例中所述的至少一个扫描驱动电路。其中，所述扫描驱动电路中，每个移位寄存器与一行子像素电连接，且被配置为向所述一行子像素传输扫描信号和复位信号。
在一些实施例中，所述扫描驱动电路的数量为两个；两个扫描驱动电路分别位于所述多行子像素的相对两侧。
在一些实施例中，所述显示基板，还包括：设置在所述衬底上的半导体层。所述移位寄存器中，扫描电路的第一输出晶体管包括：第一有源层；所述第一有源层包括第一沟道部。所述移位寄存器中，复位电路的第二输出晶体管包括：第二有源层；所述第二有源层包括第二沟道部。其中，所述第一有源层和所述第二有源层均位于所述半导体层；所述第一沟道部的沟道宽度，大于或等于所述第二沟道部的沟道宽度。
在一些实施例中，所述第一沟道部的沟道宽度方向和所述第二沟道部的沟道宽度方向，均沿行方向设置。
在一些实施例中，所述扫描电路的第三输出晶体管包括：第三有源层；所述第三有源层包括第三沟道部。所述复位电路的第四输出晶体管包括：第四有源层；所述第四有源层包括第四沟道部。其中，所述第三有源层和所述第四有源层均位于所述半导体层；所述第三沟道部的沟道宽度，大于或等于所述第四沟道部的沟道宽度。
在一些实施例中，所述第三沟道部的沟道宽度方向和所述第四沟道部的沟道宽度方向，均沿行方向设置。
在一些实施例中，所述第一有源层和所述第三有源层沿列方向依次设置；和/或，所述第二有源层和所述第四有源层沿列方向依次设置。
在一些实施例中，所述第一有源层和所述第三有源层呈一体结构；和/或，所述第二有源层和所述第四有源层呈一体结构。
在一些实施例中，所述显示基板，还包括：设置在所述半导体层远离所述衬底的一侧、且依次层叠的第二栅导电层和源漏导电层。所述扫描电路的第二电容器的第二极板位于所述第二栅导电层；所述第一输出晶体管的第二极与所述扫描电路的第三输出晶体管的第二极呈一体结构，且均位于所述源漏导电层；所述第一输出晶体管的第二极与所述第二电容器的第一极板电连接；所述扫描电路的扫描信号输出端与所述第二电容器的第一极板呈一体结构。
在一些实施例中，所述复位电路的第四电容器的第二极板位于所述第二栅导电层；所述第二输出晶体管的第二极与所述复位电路的第四输出晶体管的第二极呈一体结构，且均位于所述源漏导电层；所述第二输出晶体管的第二极与所述第四电容器的第一极板电连接；所述复位电路的复位信号输出端与所述第四电容器的第一极板呈一体结构。
在一些实施例中，所述扫描电路的第一输入晶体管包括：设置在所述第一有源层远离所述多行子像素一侧的第五有源层。所述扫描电路的第一控制晶体管包括：设置在所述第一有源层远离所述多行子像素一侧的第六有源层。所述扫描电路的第二控制晶体管包括：设置在所述第五有源层和所述第一有源层之间的第七有源层。所述扫描电路的第三控制晶体管包括：设置在所述第五有源层和所述第一有源层之间的第八有源层。所述扫描电路的第四控制晶体管包括：设置在所述第五有源层和所述第八有源层之间的第九有源层。其中，所述第五有源层、所述第六有源层、所述第七有源层、所述第八有源层、所述第九有源层均位于所述半导体层。所述第五有源层的沟道长度方向、所述第六有源层的沟道长度方向、所述第七有源层的沟道长度方向、所述第八有源层的沟道长度方向、所述第九有源层的沟道长度方向，均沿所述列方向设置。
在一些实施例中，所述第五有源层和所述第六有源层沿所述列方向依次设置，呈一体结构；和/或，所述第七有源层和所述第八有源层沿所述列方向依次设置，呈一体结构。
在一些实施例中，所述复位电路的第三输入晶体管包括：设置在所述第二有源层远离所述多行子像素一侧的第十有源层。所述复位电路的第五控制晶体管包括：设置在所述第二有源层远离所述多行子像素一侧的第十一有源层。所述复位电路的第六控制晶体管包括：设置在所述第十有源层和所述第二有源层之间的第十二有源层。所述复位电路的第七控制晶体管包括：设置在所述第十有源层和所述第二有源层之间的第十三有源层。所述复位电路的第八控制晶体管包括：设置在所述第十有源层和所述第十三有源层之间的第十四有源 层。其中，所述第十有源层、所述第十一有源层、所述第十二有源层、所述第十三有源层、所述第十四有源层均位于所述半导体层；所述第十有源层的沟道长度方向、所述第十一有源层的沟道长度方向、所述第十二有源层的沟道长度方向、所述第十三有源层的沟道长度方向、所述第十四有源层的沟道长度方向，均沿所述列方向设置。
在一些实施例中，所述第十有源层和所述第十一有源层沿所述列方向依次设置，呈一体结构；和/或，所述第十二有源层和所述第十三有源层沿所述列方向依次设置，呈一体结构。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一种实现方式中的一种显示基板的结构图；
图2为根据本公开的一些实施例的一种显示基板的结构图；
图3为根据本公开的一些实施例的另一种显示基板的结构图；
图4为根据本公开的一些实施例的一种子像素的结构图；
图5为根据本公开的一些实施例的一种扫描驱动电路的结构图；
图6为根据本公开的一些实施例的一种移位寄存器的结构图；
图7为根据本公开的一些实施例的一种扫描电路的等效结构图；
图8为根据本公开的一些实施例的一种扫描电路的驱动时序图；
图9为根据本公开的一些实施例的一种复位电路的等效结构图；
图10为根据本公开的一些实施例的扫描电路的一些膜层的俯视图；
图11为图10所示俯视图沿A-A’向的一种剖视图；
图12为图10所示俯视图沿B-B’向的一种剖视图；
图13为根据本公开的一些实施例的扫描电路的另一些膜层的俯视图；
图14为根据本公开的一些实施例的扫描电路的又一些膜层的俯视图；
图15为根据本公开的一些实施例的扫描电路的又一些膜层的俯视图；
图16为根据本公开的一些实施例的扫描电路的又一些膜层的俯视图；
图17为根据本公开的一些实施例的扫描电路的又一些膜层的俯视图；
图18为根据本公开的一些实施例的复位电路的一些膜层的俯视图；
图19为图18所示俯视图沿C-C’向的一剖视图；
图20为根据本公开的一些实施例的复位电路的另一些膜层的俯视图；
图21为根据本公开的一些实施例的复位电路的又一些膜层的俯视图；
图22为根据本公开的一些实施例的复位电路的又一些膜层的俯视图；
图23为根据本公开的一些实施例的复位电路的又一些膜层的俯视图；
图24为根据本公开的一些实施例的复位电路的又一些膜层的俯视图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的 实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本文所使用的那样，“平行”、“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平 行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
在本公开的实施例提供的电路结构(例如移位寄存器、像素驱动电路)中，移位寄存器所采用的晶体管可以为薄膜晶体管(Thin Film Transistor，简称TFT)、场效应晶体管(Metal Oxide Semiconductor，简称MOS)或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。
在本公开的实施例提供的电路结构中，所采用的各晶体管的控制极为栅极，晶体管的第一极为源极和漏极中一者，晶体管的第二极为源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性地，在晶体管为P型晶体管的情况下，晶体管的第一极为源极，第二极为漏极；示例性地，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
在本公开的实施例中，电容器可以是通过工艺制程单独制作的电容器件，例如通过制作专门的电容电极来实现电容器件，该电容器的各个电容电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现。电容器也可以是晶体管之间的寄生电容，或者通过晶体管本身与其他器件、线路来实现，又或者利用电路自身线路之间的寄生电容来实现。
本公开的实施例提供的电路结构中，第一节点、第二节点等节点并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点，也就是说，这些节点是由电路图中相关电连接的汇合点等效而成的节点。
本公开的实施例中提供的电路结构所包括的晶体管，可以均为N型晶体管，或者可以均为P型晶体管，或者一部分为N型晶体管，另一部分为P型晶体管。在本公开中，“有效电平”指的是，能够使得晶体管导通的电平。其中，P型晶体管可以在低电平信号的控制下导通，N型晶体管可以在高电平信号的控制下导通。
下面，以本公开的实施例中提供的电路结构所包括的晶体管均为P型晶体管为例，进行示意性说明。
本公开的一些实施例提供了一种移位寄存器、扫描驱动电路及显示基板，以下对移位寄存器、扫描驱动电路及显示基板分别进行介绍。
本公开的一些实施例提供一种显示基板1000，如图2所示。该显示基板装置1000可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何显示基板中。更明确地说，预期所述实施例的显示基板可实施应用在多种电子 中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
上述显示基板1000例如可以为：有机发光二极管(Organic Light Emitting Diode，简称OLED)显示基板、量子点发光二极管(Quantum Dot Light Emitting Diodes，简称QLED)显示基板、微发光二极管(Micro Light Emitting Diodes，简称Micro LED)显示基板或迷你发光二极管(Mini Light Emitting Diodes，简称Mini LED)显示基板等，本公开对此不做具体限定。
下面以上述显示基板1000为OLED显示基板为例，对本公开的一些实施例进行示意性说明。
在一些实施例中，如图2所示，显示基板1000包括：衬底200；设置在衬底200上的多行子像素Row；以及，设置在衬底200上的至少一个扫描驱动电路100。
在一些示例中，如图2所示，显示基板1000可以包括2480行子像素Row。第1行子像素、第2行子像素……第2479行子像素、第2480行子像素，可以分别采用Row_1、Row_2……Row_2479、Row_2480表示。其中，每行子像素Row可以包括多个子像素300。
在一些示例中，上述衬底200可以为柔性衬底，也可以为刚性衬底。
示例性的，在衬底200为柔性衬底的情况下，衬底200的材料可以为二甲基硅氧烷、PI(Polyimide，聚酰亚胺)、PET(Polyethylene terephthalate，聚对苯二甲酸乙二醇酯)等具有高弹性的材料。
示例性的，在衬底200为刚性衬底的情况下，衬底200的材料可以为玻璃等。
示例性的，如图4所示，子像素300包括像素驱动电路和发光器件。
上述像素驱动电路的结构包括多种，可以根据实际需要选择设置。例如，像素驱动电路的结构可以包括“4T1C”、“6T1C”、“7T1C”、“6T2C”、“7T2C”或“8T2C”等结构。其中，“T”表示为晶体管，位于“T”前面的数字表示为晶体管的数量，“C”表示为存储电容器，位于“C”前面的数字表示为存储电容器的数量。
示例性的，发光器件可以包括依次层叠设置的阳极、发光层和阴极。此外，发光器件例如还可以包括设置在阳极和发光层之间的空穴注入层和/或空穴传输层，例如还可以包括设置在发光层和阴极之间的电子传输层和/或电子注入层。其中，像素驱动电路例如与发光器件的阳极电连接。
下面结合图4，以像素驱动电路的结构为“7T1C”的结构为例，对子像素的结构进行示意性说明。需要说明的是，像素驱动电路所包括的七个晶体管和一个存储电容器之间，还可以具有其他的电连接关系，并不局限于本示例中所示的电连接关系。
示例性的，如图4所示，像素驱动电路包括：第一复位晶体管M1、开关晶体管M4、驱动晶体管M3、补偿晶体管M2和第二复位晶体管M5。
示例性的，如图4所示，第一复位晶体管M1的控制极与复位信号端Reset电连接，第一复位晶体管M1的第一极与初始信号端Vinit电连接，第一复位晶体管M1的第二极与第一像素节点Q1电连接。其中，第一复位晶体管M1被配置为，在复位信号端Reset所传 输的复位信号的控制下导通，将从初始信号端Vinit处接收的初始信号传输至第一像素节点Q1，对第一像素节点Q1进行复位。
示例性的，如图4所示，第二复位晶体管M5的控制极与扫描信号端Gate电连接，第二复位晶体管M5的第一极与初始信号端Vinit电连接，第二复位晶体管M5的第二极与发光器件的阳极电连接。其中，第二复位晶体管M5被配置为，在扫描信号端Gate所传输的扫描信号的控制下导通，将从初始信号端Vinit处接收的初始信号传输至发光器件的阳极，对发光器件的阳极进行复位。
示例性的，如图4所示，开关晶体管M4的控制极与扫描信号端Gate电连接，开关晶体管M4的第一极与数据信号端Data电连接，开关晶体管M4的第二极与第二像素节点Q2电连接。其中，开关晶体管M4被配置为，在扫描信号端Gate所传输的扫描信号的控制下导通，将数据信号端Data所传输的数据信号传输至第二像素节点Q2。
示例性的，如图4所示，驱动晶体管M3的控制极与第一像素节点Q1电连接，驱动晶体管M3的第一极与第二像素节点Q2电连接，驱动晶体管M3的第二极与第三像素节点Q3电连接。其中，驱动晶体管M3被配置为，在第一像素节点Q1的电压的控制下导通，将来自第二像素节点Q2的信号(例如为数据信号)传输至第三像素节点Q3。
示例性的，如图4所示，补偿晶体管M2的控制极与扫描信号端Gate电连接，补偿晶体管M2的第一极与第三像素节点Q3电连接，补偿晶体管M2的第二极与第一像素节点Q1电连接。其中，补偿晶体管M2被配置为，在扫描信号端Gate所传输的扫描信号的控制下导通，将来自第三像素节点Q3的信号(例如为数据信号)传输至第一像素节点Q1，对驱动晶体管M3进行阈值电压补偿。
此处，由于开关晶体管M4的控制极和补偿晶体管M2的控制极均与扫描信号端Gate电连接，因此，开关晶体管M4和补偿晶体管M2可以同时在扫描信号的控制下导通，将数据信号端Data所传输的数据信号，依次经开关晶体管M4、驱动晶体管M3及补偿晶体管M2传输至第一像素节点Q1，直至驱动晶体管M3处于截止状态，完成对驱动晶体管M3的阈值电压的补偿。同时，第二复位晶体管M5也可以在扫描信号的控制下导通，接收并传输初始信号至发光器件的阳极，对发光器件的阳极进行复位。
示例性的，子像素的驱动方式包括依次进行的复位阶段和数据写入及补偿阶段。
例如，在复位阶段，在复位信号的控制下，第一复位晶体管M1导通，将初始信号传输至第一像素节点Q1，对第一像素节点Q1进行复位。
例如，在数据写入及补偿阶段，第二复位晶体管M5在扫描信号的控制下导通，将初始信号传输至发光器件的阳极，对发光器件的阳极进行复位。开关晶体管M4在扫描信号的控制下导通，将数据信号传输至第二像素节点Q2，完成数据信号的写入；驱动晶体管M3在第一像素节点Q1的控制下导通，将来自第二像素节点Q2的信号(例如为数据信号)传输至第三像素节点Q3；补偿晶体管M2在扫描信号的控制下导通，将来自第三像素节点Q3的信号(例如为数据信号)传输至第一像素节点Q1，对驱动晶体管M3进行阈值电压补偿；直至驱动晶体管M3处于截止状态，完成对驱动晶体管M3的阈值电压的补偿。
在一些示例中，如图5所示，上述扫描驱动电路100可以包括多个移位寄存器10。其中，子像素300的扫描信号端Gate所传输的扫描信号及复位信号端Reset所传输的复位信号，由移位寄存器10提供。
在一种实现方式中，如图1所示，移位寄存器例如可以用GR表示，GR0、GR1、GR2…… GR2479、GR2480可以分别表示第1个移位寄存器、第2个移位寄存器、第3个移位寄存器……第2480个移位寄存器、第2481个移位寄存器。其中，每个移位寄存器与相邻两行子像素Row电连接。每个移位寄存器具有一个输出信号端。
以第2个移位寄存器为例，第2个移位寄存器GR2与第一行子像素Row_1及第二行子像素Row_2电连接。第2个移位寄存器GR2所输出的信号可以传输至第一行子像素Row_1，并作为第一行子像素Row_1的各复位信号端所传输的复位信号；同时，可以传输至第二行子像素Row_2，并作为第二行子像素Row_2的各扫描信号端所传输的扫描信号。
也就是说，同一个移位寄存器GR需要与两行子像素Row电连接，同时驱动该两行子像素Row。这样，使得移位寄存器GR的负载较大，降低移位寄存器GR所输出的信号的准确度，进而减少子像素的复位的时间、数据写入及补偿的时间，影响显示基板的显示效果。
基于此，本公开的一些实施例所提供的移位寄存器10，包括扫描电路11和复位电路12。其中，该移位寄存器10应用于上述显示基板1000。
在一些示例中，如图6所示，上述扫描电路11，与第一输入信号端GI、第一时钟信号端CK1、第二时钟信号端CB1、第一电压信号端VL1及第二电压信号端VH1电连接。扫描电路11被配置为，在第一输入信号端GI所传输的第一输入信号、第一时钟信号端CK1所传输的第一时钟信号、第二时钟信号端CB1所传输的第二时钟信号、第一电压信号端VL1所传输的第一电压信号及第二电压信号端VH1所传输的第二电压信号的配合作用下，输出扫描信号Gate。
在一些示例中，如图6所示，上述复位电路12，与第二输入信号端RI、第三时钟信号端CK2、第四时钟信号端CB2、第三电压信号端VL2及第四电压信号端VH2电连接。复位电路12被配置为，在第二输入信号端RI所传输的第二输入信号、第三时钟信号端CK2所传输的第三时钟信号、第四时钟信号端CB2所传输的第四时钟信号、第三电压信号端VL2所传输的第三电压信号及第四电压信号端VH2所传输的第四电压信号的配合作用下，输出复位信号Reset。
示例性的，第一电压信号端VL1被配置为，传输第一直流低电平信号(例如低于或等于时钟信号的低电平部分)。此处，将该第一直流低电平信号称为第一电压信号。第三电压信号端VL2被配置为，传输第三直流低电平信号(例如低于或等于时钟信号的低电平部分)。此处，将该第三直流低电平信号称为第三电压信号。
例如，第一电压信号的电平和第三电压信号的电平可以相同。
示例性的，第二电压信号端VH1被配置为，传输第二直流高电平信号(例如高于或等于时钟信号的高电平部分)。此处，将该第二直流高电平信号称为第二电压信号。第四电压信号端VH2被配置为，传输第四直流高电平信号(例如高于或等于时钟信号的高电平部分)。此处，将该第四直流高电平信号称为第四电压信号。
例如，第二电压信号的电平和第四电压信号的电平可以相同。
示例性的，第一时钟信号端CK1被配置为，传输第一时钟信号(例如具有低电平部分和高电平部分)。第二时钟信号端CB1被配置为，传输第二时钟信号(例如具有低电平部分和高电平部分)。
例如，第一时钟信号的波形和第二时钟信号的波形可以相同，第一时钟信号的有效电平和第二时钟信号的有效电平的时间不重合。
示例性的，第三时钟信号端CK2被配置为，传输第三时钟信号(例如具有低电平部分和高电平部分)。第四时钟信号端CB2被配置为，传输第四时钟信号(例如具有低电平部分和高电平部分)。
例如，第三时钟信号的波形和第四时钟信号的波形可以相同，第三时钟信号的有效电平和第四时钟信号的有效电平的时间不重合。
在一些示例中，如图5所示，扫描电路11和复位电路12之间相互独立输出信号。
例如，扫描电路11和复位电路12之间未形成电连接，扫描电路11和复位电路12之间相互独立设计，分别输出扫描信号和复位信号。其中，扫描信号的波形和复位信号的波形例如可以相同，但扫描信号的有效电平和复位信号的有效电平的时间不重合。
在一些示例中，如图2所示，上述移位寄存器10与一行子像素Row电连接，且被配置为向上述一行子像素Row传输扫描信号Gate和复位信号Reset。也即，移位寄存器10中的扫描电路11和复位电路12同时与一行子像素Row电连接，并分别向该行子像素Row传输扫描信号Gate和复位信号Reset，以利用该复位信号Reset对该行子像素Row进行复位，并利用该扫描信号Gate对该行子像素Row进行数据写入及补偿。
本公开中的移位寄存器10仅与一行子像素Row电连接，并为该一行子像素Row传输扫描信号Gate和复位信号Reset，移位寄存器10仅驱动一行子像素Row，实现该行子像素Row的复位、数据写入及补偿，由此，可以降低移位寄存器10的负载，从而降低扫描驱动电路100的负载，提高传输给子像素的扫描信号Gate和复位信号Reset的准确性，从而提高显示基板1000的显示效果。
本公开提供的一种扫描驱动电路100及显示基板1000所能实现的有益效果，与移位寄存器10所能实现的有益效果相同，此处不再赘述。
在一些实施例中，如图7所示，上述扫描电路11包括：第一输出晶体管T4。第一输出晶体管T4的第一极与第二电压信号端VH1电连接，第一输出晶体管T4的第二极与扫描信号输出端GO电连接。
在一些示例中，如图7所示，扫描电路11还包括：第三输出晶体管T5。第三输出晶体管T5的第一极与第二时钟信号端CB1电连接，第三输出晶体管T5的第二极与扫描信号输出端GO电连接。
示例性的，第一输出晶体管T4和第三输出晶体管T5分别在不同的时间段内导通。在第一输出晶体管T4导通的时间段内，第一输出晶体管T4可以接收并传输第二电压信号至扫描信号输出端GO，并将第二电压信号作为扫描信号Gate从扫描信号输出端GO输出。在第三输出晶体管T5导通的时间段内，第三输出晶体管T5可以接收并传输第二时钟信号至扫描信号输出端GO，并将第二时钟信号作为扫描信号Gate从扫描信号输出端GO输出。
也就是说，扫描信号Gate是由第二电压信号和第二时钟信号组合构成的。
由于第二电压信号为直流高电平信号，而开关晶体管M4、补偿晶体管M2需要在低电平信号的控制下导通，因此，扫描信号Gate中的有效电平部分由第二时钟信号构成。
在一些示例中，如图9所示，上述复位电路12包括：第二输出晶体管R4。第二输出晶体管R4的第一极与第四电压信号端VH2电连接，第二输出晶体管R4的第二极与复位信号输出端RO电连接。
在一些示例中，如图9所示，复位电路12还包括：第四输出晶体管R5。第四输出晶体管R5的第一极与第四时钟信号端CB2电连接，第四输出晶体管R5的第二极与复位信 号输出端RO电连接。
示例性的，第二输出晶体管R4和第四输出晶体管R5分别在不同的时间段内导通。在第二输出晶体管R4导通的时间段内，第二输出晶体管R4可以接收并传输第四电压信号至复位信号输出端RO，并将第四电压信号作为复位信号Reset从复位信号输出端RO输出。在第四输出晶体管R5导通的时间段内，第四输出晶体管R5可以接收并传输第四时钟信号至复位信号输出端RO，并将第四时钟信号作为复位信号Reset从复位信号输出端RO输出。
也就是说，复位信号Reset是由第四电压信号和第四时钟信号组合构成的。
由于第四电压信号为直流高电平信号，而第一复位晶体管M1需要在低电平信号的控制下导通，因此，复位信号Reset中的有效电平部分由第四时钟信号构成。
在一些示例中，第一输出晶体管T4的沟道宽度，大于或等于第二输出晶体管R4的沟道宽度。
需要说明的是，薄膜晶体管沟道宽度的大小，影响薄膜晶体管的开关特性。为了获得更高的薄膜晶体管工作电流，需要提高宽长比(W/L)，例如可以增加沟道宽度W或降低沟道长度L。沟道长度L基本都为，工艺水平能够保证的、在源极和漏极不发生短路的基础上的最小间距。因此，可以通过提高薄膜晶体管的沟道宽度来获得更高的工作电流，而工作电流的提高，代表着写入能力和保持能力的增强，这样可以降低薄膜晶体管的功耗，进而降低显示基板的功耗。
例如，第一输出晶体管T4的沟道宽度，等于第二输出晶体管R4的沟道宽度。由此，扫描电路11第一输出晶体管T4的功耗和复位电路12第二输出晶体管R4的功耗相同。
又如，第一输出晶体管T4的沟道宽度，大于第二输出晶体管R4的沟道宽度。由此，扫描电路11第一输出晶体管T4的功耗小于复位电路12第二输出晶体管R4的功耗，可以降低显示基板1000的功耗。
在一些示例中，第一输出晶体管T4的沟道宽度与第二输出晶体管R4的沟道宽度的比例范围为1:1～20:1。
例如，第一输出晶体管T4的沟道宽度与第二输出晶体管R4的沟道宽度的比例可以为1:1、2:1、3:1、4:1、10:1或20:1。
在一些示例中，第三输出晶体管T5的沟道宽度，大于或等于第四输出晶体管R5的沟道宽度。
例如，第三输出晶体管T5的沟道宽度，等于第四输出晶体管R5的沟道宽度。
又如，第三输出晶体管T5的沟道宽度，大于第四输出晶体管R5的沟道宽度。由此，扫描电路11第三输出晶体管T5的功耗小于复位电路12第四输出晶体管R5的功耗，可以提高扫描驱动电路10对子像素300的驱动能力，从而可以降低显示基板1000的功耗。
在一些示例中，第三输出晶体管T5的沟道宽度与第四输出晶体管R5的沟道宽度的比例范围为1:1～20:1。
例如，第三输出晶体管T5的沟道宽度与第四输出晶体管R5的沟道宽度的比例可以为1:1、2:1、3:1、4:1、10:1或20:1。
下面，分别对一种实现方式中的移位寄存器的输出晶体管的沟道宽度、本公开中复位电路11的输出晶体管的沟道宽度、本公开中扫描电路12的输出晶体管的沟道宽度进行设置，并对一种实现方式中的移位寄存器所输出的信号、本公开中的复位电路所输出的复位 信号、本公开中的扫描电路所输出的扫描信号进行检测，具体结果如下表所示。
表1
Figure PCTCN2021140079-appb-000001
表2
Figure PCTCN2021140079-appb-000002
示例性的，一种实现方式中的移位寄存器的输出晶体管的沟道宽度、本公开中复位电路的输出晶体管的沟道宽度、本公开中扫描电路的输出晶体管的沟道宽度的设置方式如表1所示。由表1可知，第一输出晶体管的沟道宽度与第二输出晶体管的沟道宽度的比例为3:1，第三输出晶体管的沟道宽度与第四输出晶体管的沟道宽度的比例为3:1。
示例性的，一种实现方式中的移位寄存器所输出的信号、本公开中的复位电路所输出的复位信号、本公开中的扫描电路所输出的扫描信号的检测结果如表2所示。表2中，Tr代表信号的上升沿时间，Tf代表信号的下降沿时间。Tr的值越小，表示信号的上升沿时间越短，Tf的值越小，表示信号的下降沿时间越短。若Tr的值和Tf的值均比较小，则表示信号的波形越规则，信号的准确度越高。
由表2可知，在本公开的方案中，复位信号的Tr小于一种实现方式中复位信号的Tr，且复位信号的Tr相比于一种实现方式中复位信号的Tr降低了4.9％；复位信号的Tf小于一种实现方式中复位信号的Tf，且复位信号的Tf相比于一种实现方式中复位信号的Tf降低了0.4％。在本公开的方案中，扫描信号的Tr小于一种实现方式中扫描信号的Tr，且扫描信号的Tr相比于一种实现方式中扫描信号的Tr降低了12.1％；扫描信号的Tf小于一种实现方式中扫描信号的Tf，且扫描信号的Tf相比于一种实现方式中扫描信号的Tf降低了10.1％。
需要说明的是，一种实现方式中，移位寄存器提供的复位信号和扫描信号为同一种信号，由同一个信号输出端输出，但由于该移位寄存器需要驱动一行子像素实现复位以及驱 动另一行子像素实现扫描，复位信号所需要驱动的是上述一行子像素的第一复位晶体管M1，扫描信号所需驱动的是上述另一行子像素的开关晶体管M4、第二复位晶体管M5、补偿晶体管M2，因此，所测得的扫描信号的Tf和复位信号的Tf不同，扫描信号的Tr和复位信号的Tr不同。
由此，本公开中，通过将一个移位寄存器10与一行子像素Row电连接，并将移位寄存器10设置为相互独立的扫描电路11和复位电路11，使得扫描电路11中的第一输出晶体管T4的沟道宽度大于或等于复位电路12中第二输出晶体管R4的沟道宽度，扫描电路11中的第三输出晶体管T5的沟道宽度大于或等于复位电路12中第四输出晶体管R5的沟道宽度，不仅可以降低扫描电路11输出的扫描信号Gate的Tr和Tf，还可以降低复位电路12输出的复位信号Reset的Tr和Tf。由此，本公开采用上述设置方式，可以减小移位寄存器10的负载，减小扫描信号Gate和复位信号Reset在向子像素300传输的过程中的损耗，从而可以提高描信号Gate和复位信号Reset的准确度，进一步提高对子像素300进行复位、数据写入及补偿的时间，进而有利于降低显示基板1000的功耗，提高显示基板1000的显示品质。
同一移位寄存器10中，扫描电路11和复位电路12的排布方式有多种，可以根据实际情况进行选择。
在一些示例中，如图5所示，同一移位寄存器10中，扫描电路11和复位电路12沿行方向X并列设置。
示例性的，扫描电路11和复位电路12，可以和与其电连接的一行子像素Row同行设置。
采用上述设置方式，扫描电路11和复位电路12排列较为规整，便于走线布置，且可以减小移位寄存器10所占用的面积。
在另一些示例中，如图2所示，同一移位寄存器10中，扫描电路11和复位电路12沿行方向X交错设置。
示例性的，扫描电路11可以和与其电连接的一行子像素Row同行设置，复位电路12可以和与上述一行子像素Row相邻的另一行子像素Row同行设置。
示例性的，沿行方向X，扫描电路11可以位于相邻两个复位电路12之间。
采用上述设置方式，可以便于扫描电路11或复位电路12与相应的一行子像素Row之间的走线连接。
在一些实施例中，如图2所示，相比于扫描电路11，复位电路12更靠近其所电连接的一行子像素Row。在这种情况下，复位电路12的复位信号输出端RO与相对应的一行子像素Row电连接的走线的长度较短，复位信号Reset的损耗较小，有利于提高复位电路12向子像素300提供的复位信号Reset的准确性和稳定性。
在一些实施例中，如图7所示，上述移位寄存器10中，扫描电路10包括：第一输入晶体管T3、第二输入晶体管T1、第一控制晶体管T2、第二控制晶体管T6、第三控制晶体管T7、第四控制晶体管T8、第一输出晶体管T4、第三输出晶体管T5、第一电容器C1和第二电容器C2。
在一些示例中，如图7所示，第一输入晶体管T3的控制极与第一时钟信号端CK1电连接，第一输入晶体管T3的第一极与第一电压信号端VL1电连接，第一输入晶体管T3的第二极与第二节点N2电连接。
示例性的，第一输入晶体管T3被配置为，在第一时钟信号的控制下导通，将第一电压信号传输至第二节点N2。
在一些示例中，如图7所示，第二输入晶体管T1的控制极与第一时钟信号端CK1电连接，第二输入晶体管T1的第一极与第一输入信号端GI电连接，第二输入晶体管T1的第二极与第一节点N1电连接。
示例性的，第二输入晶体管T1被配置为，在第一时钟信号的控制下导通，将第一输入信号传输至第一节点N1。
在一些示例中，如图7所示，第一控制晶体管T2的控制极与第一节点N1电连接，第一控制晶体管T2的第一极与第一时钟信号端CK1电连接，第一控制晶体管T2的第二极与第二节点N2电连接。
示例性的，第一控制晶体管T2被配置为，在第一节点N1的控制下导通，将第一时钟信号传输至第二节点N2。
在一些示例中，如图7所示，第二控制晶体管T6的控制极与第二节点N2电连接，第二控制晶体管T6的第一极与第二电压信号端VH1电连接，第二控制晶体管T6的第二极与第三节点N3电连接。
示例性的，第一控制晶体管T2被配置为，在第一节点N1的控制下导通，将第一时钟信号传输至第二节点N2。
在一些示例中，如图7所示，第三控制晶体管T7的控制极与第二时钟信号端CB1电连接，第三控制晶体管T7的第一极与第三节点N3电连接，第三控制晶体管T7的第二极与第一节点N1电连接。
示例性的，第三控制晶体管T7被配置为，在第二时钟信号的控制下导通，将第三节点N3的信号(例如为第二电压信号)传输至第一节点N1。
在一些示例中，如图7所示，第四控制晶体管T8的控制极与第一电压信号端VL1电连接，第四控制晶体管T8的第一极与第一节点N1电连接，第四控制晶体管T8的第二极与第四节点N4电连接。
示例性的，第四控制晶体管T8被配置为，在第一电压信号的控制下导通，将第一节点N1的信号(例如为第一输入信号)传输至第四节点N4。
在一些示例中，如图7所示，第一输出晶体管T4的控制极与第二节点N2电连接，第一输出晶体管T4的第一极与第二电压信号端VH1电连接，第一输出晶体管T4的第二极与扫描信号输出端GO电连接。第一电容器C1的第一极板与第二电压信号端VGH1电连接，第一电容器C1的第二极板与第二节点N2电连接。
示例性的，第一输出晶体管T4被配置为，在第二节点N2的电压的控制下导通，将第二电压信号传输至扫描信号输出端GO。第一电容器C1被配置为，维持第二节点N2的电压。
在一些示例中，如图7所示，第三输出晶体管T5的控制极与第四节点N4电连接，第三输出晶体管T5的第一极与第二时钟信号端CB1电连接，第三输出晶体管T5的第二极与扫描信号输出端GO电连接。第二电容器C2的第一极板与扫描信号输出端GO电连接，第二电容器C2的第二极板与第四节点N4电连接。
示例性的，第三输出晶体管T5被配置为，在第四节点N4的电压的控制下导通，将第二时钟信号传输至扫描信号输出端GO。第二电容器器C2被配置为，维持第四节点N4的 电压。
下面，结合图8所示的时序图，以扫描电路11的结构为图7所示的结构为例，对扫描电路11的工作原理进行说明。图8中，GI表示第一输入信号端所传输的第一输入信号，CK1表示第一时钟信号端所传输的第一时钟信号，CB1表示第二时钟信号端所传输的第二时钟信号，GO表示扫描信号输出端所传输的扫描信号，N4表示第四节点的电压。
示例性的，如图8所示，扫描电路11的工作过程包括：输入阶段Pl、输出阶段P2和缓冲阶段P3。
示例性的，结合图7和图8所示，在输入阶段Pl，第一时钟信号的电平为低电平；第二时钟信号的电平为高电平，例如，在此阶段，第二时钟信号的压值与第二电压信号的压值相等；第一输入信号的电平为低电平，其压值可以采用Vin表示，例如，在此阶段，第一输入信号的压值与第一电压信号的压值相等。
例如，第二输入晶体管T1在第一时钟信号的控制下导通，将输入信号传输至第一节点N1。由于第二输入晶体管T1传递第一输入信号具有阈值损失，从而第一节点N1的电压为Vin-Vth1，即VL-Vth1，其中，Vth1表示第二输入晶体管T1的阈值电压。第四控制晶体管T8在第一电压信号的控制下导通，将第一节点N1的电压VL-Vth1传输至第四节点N4。例如，第四控制晶体管T8的阈值电压为Vth8，同理，由于第四控制晶体管T8传递信号的过程中具有阈值损失，因此，第四节点N4的电压为VL-VthNl，其中，VthNl为Vth1和Vth8中较小的一个。第三输出晶体管T5可以在第四节点N4的电压的控制下导通，将第二时钟信号传输至扫描信号输出端GO以作为输出信号。
例如，第一输入晶体管T3在第一时钟信号的控制下导通，将第一电压信号VL1传输至第二节点N2。由于第一节点N1的电压为VL-Vth1，第一控制晶体管T2在第一节点N1的电压的控制下导通，将第一时钟信号传输至第二节点N2。例如，第一控制晶体管T2的阈值电压为Vth2，第一输入晶体管T3的阈值电压为Vth3，若Vth3<Vth2+Vth1，则第二节点N2的电压为VL-Vth1-Vth2；若Vth3>Vth1+Vth2，则第二节点N2的电压为VL-Vth3。此时，第一输出晶体管T4和第一控制晶体管T6均在第二节点N2的电压的控制下导通。第三控制晶体管T7在第二时钟信号的控制下截止。
由于第二时钟信号的电平为高电平，且第二电压信号的电平为高电平，因此，在输入阶段Pl，扫描信号的电平为高电平，电压为VH。
示例性的，结合图7和图8所示，在输出阶段P2，第一时钟信号的电平为高电平；第二时钟信号的电平为低电平，例如，在此阶段，第二时钟信号的压值与第一电压信号的压值相等。
例如，第二输入晶体管T1和第一输入晶体管T3在第一时钟信号的控制下均截止。第一节点N1的电压仍为VL-VthNl，第一控制晶体管T2在第一节点N1的电压控制下导通，将第一时钟信号传输至第二节点N2，即第二节点N2的电压为VH，由此，第一输出晶体管T4和第二控制晶体管T6在第二节点N2的电压的控制下均截止。
例如，第三输出晶体管T5在第四节点N4的电压的控制下导通，将第二时钟信号传输至扫描信号输出端GO以作为输出信号。在输入阶段Pl，第二电容器C2的第一极板的电压为VH，第二电容器C2的第二极的电压为VL-VthNl，而在输出阶段P2，第二电容器C2的第一极的电压变为VL，由于第二电容器C2的自举作用，第二电容器C2的第二极的电压变为2VL-VthNl-VH，即第四节点N4的电压变为2VL-VthNl-VH，此时，第四控制晶体 管T8截止，第三输出晶体管T5在第四节点N4的电压的控制下，可以更好地打开，扫描信号的电压为VL。
示例性的，结合图7和图8所示，在缓冲阶段P3，第一时钟信号的电平为高电平；第二时钟信号的电平为高电平。第一输入信号的电平为高电平。
例如，第三输出晶体管T5在第四节点N4的电压的控制下导通，将第二时钟信号传输至扫描信号输出端GO以作为输出信号，此时，扫描信号的电压为VH。由于第二电容器C2的自举作用，第四节点N4的电压变为VL-VthNl。
例如，第二输入晶体管T1和第一输入晶体管T3在第一时钟信号的电压的控制下均截止。第四节点N4的电压变为VL-VthNl，此时，第四控制晶体管T8在第一电压信号的控制下导通，第一节点N1的电压也为VL-VthNl，第一控制晶体管T2在第一节点N1的控制下导通，将第一时钟信号传输至第二节点N2，即第二节点N2的电压为VH，由此，第一输出晶体管T4和第一控制晶体管T6在第二节点N2的电压的控制下均截止。
在一些实施例中，如图9所示，复位电路12包括：第三输入晶体管R3、第四输入晶体管R1、第五控制晶体管R2、第六控制晶体管R6、第七控制晶体管R7、第八控制晶体管R8、第二输出晶体管R4、第四输出晶体管R5、第三电容器C10和第四电容器C20。
在一些示例中，如图9所示，第三输入晶体管R3的控制极与第三时钟信号端CK2电连接，第三输入晶体管R3的第一极与第三电压信号端VL2电连接，第三输入晶体管R3的第二极与第六节点N6电连接。
示例性的，第三输入晶体管R3被配置为，在第三时钟信号的控制下导通，将第三电压信号传输至第六节点N6。
在一些示例中，如图9所示，第四输入晶体管R1的控制极与第三时钟信号端CK2电连接，第四输入晶体管R1的第一极与第二输入信号端RI电连接，第四输入晶体管R1的第二极与第五节点N5电连接。
示例性的，第四输入晶体管R1被配置为，在第三时钟信号的控制下导通，将第二输入信号传输至第五节点N5。
在一些示例中，如图9所示，第五控制晶体管R2的控制极与第五节点N5电连接，第五控制晶体管R2的第一极与第三时钟信号端CK2电连接，第五控制晶体管R2的第二极与第六节点N6电连接。
示例性的，第五控制晶体管R2被配置为，在第三时钟信号的控制下导通，将第三时钟信号传输至第六节点N6。
在一些示例中，如图9所示，第六控制晶体管R6的控制极与第六节点N6电连接，第六控制晶体管R6的第一极与第四电压信号端VH2电连接，第六控制晶体管R6的第二极与第七节点N7电连接。
示例性的，第六控制晶体管R6被配置为，在第六节点N6的控制下导通，将第四电压信号传输至第七节点N7。
在一些示例中，如图9所示，第七控制晶体管R7的控制极与第四时钟信号端CB2电连接，第七控制晶体管R7的第一极与第七节点N7电连接，第七控制晶体管R7的第二极与第五节点N5电连接。
示例性的，第七控制晶体管R7被配置为，在第四时钟信号的控制下导通，将第七节点N7的电压传输至第五节点N5。
在一些示例中，如图9所示，第八控制晶体管R8的控制极与第三电压信号端VL2电连接，第八控制晶体管R8的第一极与第五节点N5电连接，第八控制晶体管R8的第二极与第八节点N8电连接。
示例性的，第八控制晶体管R8被配置为，在第三电压信号的控制下导通，将第五节点N5的电压传输至第八节点N8。
在一些示例中，如图9所示，第二输出晶体管R4的控制极与第六节点N6电连接，第二输出晶体管R4的第一极与第四电压信号端VH2电连接，第二输出晶体管R4的第二极与复位信号输出端RO电连接。第三电容器C10的第一极板与第四电压信号端VH2电连接，第三电容器C10的第二极板与第六节点N6电连接。
示例性的，第二输出晶体管R4被配置为，在第六节点N6的控制下导通，将第四电压信号传输至复位信号输出端RO。第三电容器C10被配置为，维持第六节点N6的电压。
在一些示例中，如图9所示，第四输出晶体管R5的控制极与第八节点N8电连接，第四输出晶体管R5的第一极与第四时钟信号端CB2电连接，第四输出晶体管R5的第二极与复位信号输出端RO电连接。第四电容器C20的第一极板与复位信号输出端RO电连接，第四电容器C20的第二极板与第八节点N8电连接。
示例性的，第四输出晶体管R5被配置为，在第八节点N8的控制下导通，将第四时钟信号传输至复位信号输出端RO。第四电容器C20被配置为，维持第八节点N8的电压。
示例性的，复位电路12的结构与扫描电路11的结构相同，复位电路12的工作原理与复位电路12的工作原理相同或类似。复位电路12的工作原理可参考上述实施例中扫描电路11的工作原理，此处不再赘述。
本公开的一些实施例还提供了一种扫描驱动电路100，如图5所示，包括如上实施例所述的多个移位寄存器10。
在一些示例中，多个移位寄存器10中的扫描电路11相互级联，多个移位寄存器10中的复位电路12相互级联。扫描电路11和复位电路12之间无级联关系。
例如，第a个移位寄存器的扫描电路11的扫描信号输出端GO，与第a+1个移位寄存器的扫描电路11的第一输入端信号端GI电连接，也即，第a个移位寄存器的扫描电路11所输出的扫描信号，可以作为第a+1个移位寄存器的扫描电路11的第一输入信号。其中，a为正整数。
例如，第a个移位寄存器的复位电路12的复位信号输出端RO，与第a+1个移位寄存器中的复位电路12的第二输入端信号端RI电连接，也即，第a个移位寄存器的复位电路12所输出的复位信号，可以作为第a+1个移位寄存器的复位电路12的第二输入信号。
在一些示例中，如图5所示，多个移位寄存器10中各扫描电路11沿列方向Y依次排列，例如排列为一排。多个移位寄存器10中各复位电路12沿列方向依次排列，例如排列为一排。以这种设置方式，可以使得扫描电路11和复位电路12排列较为规整，便于走线布置，且有利于降低移位寄存器10及扫描驱动电路100所需占用的面积。
在一些实施例中，扫描驱动电路，还包括：第一电压信号线VGL1，第二电压信号线VGH1，第三电压信号线VGL2以及第四电压信号线VGH2。
示例性的，第一电压信号线VGL1沿列方向Y延伸，与扫描电路11的第一电压信号 端VL1电连接。第一电压信号线VGL1为扫描电路11的第一电压信号端VL1提供第一电压信号。
示例性的，第二电压信号线VGH1沿列方向Y延伸，与扫描电路11的第二电压信号端VH1电连接。第二电压信号线VGH1为扫描电路11的第二电压信号端VH1提供第二电压信号。
示例性的，第三电压信号线VGL2沿列方向Y延伸，与复位电路12的第三电压信号端VL2电连接。第三电压信号线VGL2为复位电路12的第三电压信号端VL2提供第三电压信号。
示例性的，第四电压信号线VGH2沿列方向Y延伸，与复位电路12的第四电压信号端VH2电连接。第四电压信号线VGH2为复位电路12的第四电压信号端VH2提供第四电压信号。
第一电压信号线VGL1、第二电压信号线VGH1、第三电压信号线VGL2以及第四电压信号线VGH2均沿列方向Y延伸，可以节省显示基板1000中扫描驱动电路100所占的面积和空间，有利于显示基板1000的窄边框设计。
示例性的，如图2、图10及图18所示，扫描电路11设置在第一电压信号线VGL1和第二电压信号线VGH1之间，复位电路12设置在第三电压信号线VGL2和第四电压信号线VGH2之间。
通过将第一电压信号线VGL1和第二电压信号线VGH1设置在扫描电路11的两侧，将第三电压信号线VGL2和第四电压信号线VGH2设置在复位电路12的两侧，不仅可以避免在第一电压信号线VGL1和第二电压信号线VGH1之间形成寄生电容，避免在第三电压信号线VGL2和第四电压信号线VGH2之间产生寄生电容，还可以使得第一电压信号线VGL1、第二电压信号线VGH1、第三电压信号线VGL2、第四电压信号线VGH2排列较为紧密，有利于节约布线空间、方便信号的传输，并有利于显示基板1000的窄边框设计。
在一些实施例中，如图2、图10及图18所示，第二电压信号线VGH1和第三电压信号线VGL2，设置在扫描电路11和复位电路12之间。此时，第一电压信号线VGL1设置在扫描电路11远离多行子像素的一侧，第四电压信号线VGH2设置在复位电路12靠近多行子像素的一侧。
采用上述设置方式，可以缩短第二电压信号线VGH1与扫描电路11中第一输出晶体管T4的第一极之间的距离，可以缩短第三电压信号线VGL2与复位电路12中第三输入晶体管R3的第一极之间的距离，可以缩短第一电压信号线VGL1与扫描电路11中的第一输入晶体管T3的第一极之间的距离，可以缩短第四电压信号线VGH2与复位电路12中第二输出晶体管R4的第一极之间的距离，从而不仅有利于简化布线难度，还可以节省扫描驱动电路100在行方向X所占的面积和空间，有利于实现显示基板1000的窄边框设计。
在一些实施例中，如图5所示，扫描驱动电路100还包括：第一时钟信号线CKL1、第二时钟信号线CBL1、第三时钟信号线CKL2以及第四时钟信号线CBL2。
示例性的，第一时钟信号线CKL1沿列方向Y延伸，与第2m-1个扫描电路11的第一时钟信号端CK1及第2m个扫描电路12的第二时钟信号端CB1电连接，m为正整数。
例如，如图5所示，第一时钟信号线CKL1与第1个(m＝1)扫描电路11的第一时钟信号端CK1、第3个(m＝2)扫描电路11的第一时钟信号端CK1、第5个(m＝3)扫描电路11的第一时钟信号端CK1、第7个(m＝4)扫描电路11的第一时钟信号端CK1……电 连接；第一时钟信号线CKL1与第2个(m＝1)扫描电路11的第二时钟信号端CB1、第4个(m＝2)扫描电路11的第二时钟信号端CB1、第6个(m＝3)扫描电路11的第二时钟信号端CB1、第8个(m＝4)扫描电路11的第二时钟信号端CB1……电连接。
示例性的，第二时钟信号线CBL1沿列方向Y延伸，与第2m-1个扫描电路的第二时钟信号端CB1及第2m个扫描电路的第一时钟信号端CK1电连接，m为正整数。
例如，如图5所示，第二时钟信号线CBL1与第1个(m＝1)扫描电路11的第二时钟信号端CB1、第3个(m＝2)扫描电路11的第二时钟信号端CB1、第5个(m＝3)扫描电路11的第二时钟信号端CB1、第7个(m＝4)扫描电路的第二时钟信号端CB1……电连接；第二时钟信号线CBL1与第2个(m＝1)扫描电路11的第一时钟信号端CK1、第4个(m＝2)扫描电路11的第一时钟信号端CK1、第6个(m＝3)扫描电路11的第一时钟信号端CK1、第8个(m＝4)扫描电路11的第一时钟信号端CK1……电连接。
示例性的，第三时钟信号线CKL2沿列方向Y延伸，与第2m-1个复位电路12的第三时钟信号端CK2及第2m个复位电路12的第四时钟信号端CB2电连接，m为正整数。
例如，如图5所示，第三时钟信号线CKL2与第1个(m＝1)复位电路12的第三时钟信号端CK2、第3个(m＝2)复位电路12的第三时钟信号端CK2、第5个(m＝3)复位电路12的第三时钟信号端CK2、第7个(m＝4)复位电路12的第三时钟信号端CK2……电连接；第三时钟信号线CKL2与第2个(m＝1)复位电路12的第四时钟信号端CB2、第4个(m＝2)复位电路12的第四时钟信号端CB2、第6个(m＝3)复位电路12的第四时钟信号端CB2、第8个(m＝4)复位电路12的第四时钟信号端CB2……电连接。
示例性的，第四时钟信号线CBL2沿列方向Y延伸，与第2m-1个复位电路12的第四时钟信号端CB2及第2m个复位电路12的第三时钟信号端CK2电连接，m为正整数。
例如，如图5所示，第四时钟信号线CBL2与第1个(m＝1)复位电路12的第四时钟信号端CB2、第3个(m＝2)复位电路12的第四时钟信号端CB2、第5个(m＝3)复位电路12的第四时钟信号端CB2、第7个(m＝4)复位电路12的第四时钟信号端CB2……电连接；第四时钟信号线CBL2与第2个(m＝1)复位电路12的第三时钟信号端CK2、第4个(m＝2)复位电路12的第三时钟信号端CK2、第6个(m＝3)复位电路12的第三时钟信号端CK2、第8个(m＝4)复位电路12的第三时钟信号端CK2……电连接。
如图10及图18所示，第一时钟信号线CKL1、第二时钟信号线CBL1、第三时钟信号线CKL2以及第四时钟信号线CBL2均沿列方向Y延伸，有利于减小扫描驱动电路100所占的面积和空间，进而有利于显示基板1000的窄边框设计。
在一些示例中，第一时钟信号线CKL1和第二时钟信号线CBL1，设置在扫描电路11远离复位电路12的一侧。第三时钟信号线CKL2和第四时钟信号线CBL2，设置在复位电路12靠近扫描电路11的一侧。
示例性的，如图2、图10及图18所示，第一时钟信号线CKL1、第二时钟信号线CBL1以及第一电压信号线VGL1设置在扫描电路12的同侧，例如第一电压信号线VGL1，可以位于第一时钟信号线CKL1与扫描电路12之间，距离扫描电路12较近，从而可以缩短第一控制晶体管T2的控制极，以及第一输入晶体管T3的控制极到第一时钟信号线CKL1的连接线的长度，可以缩短第三控制晶体管T7的控制极到第二时钟信号线CBL1之间的连接线的长度，可以缩短第一输入晶体管T3的第一极到第一电压信号线VGL1的连接线的长度，从而可以减少扫描电路11所占的面积和空间，进而减少扫描驱动电路100在显 示基板1000所占的面积和空间，实现显示基板1000的窄边框设计；第三时钟信号线CKL2、第四时钟信号线CBL2以及第三电压信号线VGL2设置在复位电路12的同侧，例如第三电压信号线VGL2，可以位于第三时钟信号线CKL2与复位电路12之间，且距离复位电路12较近，从而可以缩短第五控制晶体管R2的控制极，以及第三输入晶体管R3的控制极到第三时钟信号线CKL2的连接线的长度，可以缩短第三输入晶体管R3的第一极到第三电压信号线VGL2的连接线的长度，从而可以节约复位电路12所占的面积和空间，进而减少扫描驱动电路100在显示基板1000所占的面积和空间，实现显示基板1000的窄边框设计。
在一些实施例中，扫描驱动电路100还包括：第一初始信号线GSTV和第二初始信号线RSTV。
示例性的，第一初始信号线GSTV沿列方向Y延伸，与多个移位寄存器10中前n个移位寄存器10的扫描电路11的第一输入信号端GI电连接；n为正整数。
例如，n＝1，第一初始信号线GSTV与多个移位寄存器10中第一个移位寄存器的扫描电路11的第一输入信号端GI电连接。第一初始信号线GSTV所传输的第一初始信号可以作为，上述第一个移位寄存器的扫描电路11的第一输入信号。
示例性的，第二初始信号线RSTV沿列方向Y延伸，与多个移位寄存器中前i个移位寄存器10的复位电路12的第二输入信号端RI电连接；i为正整数。
例如，i＝1，第二初始信号线RSTV与多个移位寄存器10中第一个移位寄存器10的复位电路12的第二输入信号端RI电连接。第二初始信号线RSTV所传输的第二初始信号可以作为，上述第一个移位寄存器的复位电路12的第二输入信号。
在一些示例中，如图2、图10及图18所示，第一初始信号线GSTV设置在扫描电路11远离复位电路12的一侧；第二初始信号线RSTV设置在复位电路12靠近扫描电路11的一侧。
采用上述设置方式，扫描电路11的第二输入晶体管T1的第一极与第一初始信号线GSTV之间的距离较小，可以缩短第二输入晶体管T1的第一极到第一初始信号线GSTV之间的连接线的长度；复位电路12的第四输入晶体管R1的第一极与第二初始信号线RSTV之间的距离较小，可以缩短第四输入晶体管R1的第一极到第二初始信号线RSTV之间的连接线的长度较小，从而可以减少扫描驱动电路100在显示基板1000所占的面积和空间，实现显示基板1000的窄边框设计。
在一些示例中，如图3所示，显示基板1000中，扫描驱动电路100的数量可以为一个。此时，该扫描驱动电路100位于显示基板的一侧。
在另一些示例中，如图4所示，显示基板1000中，扫描驱动电路100的数量为两个。此时，该两个扫描驱动电路100分别位于多行子像素Row的相对两侧。基于此，两个扫描驱动电路100可以交替工作，交替地为子像素提供扫描信号和复位信号，这样有利于减小扫描驱动电路100的负载，提高扫描驱动电路100的工作寿命。
需要说明的是，如图10～图24所示，扫描驱动电路100可以由多层层叠的膜层构成。其中，每层膜层均具有图案。
在一些实施例中，如图13～图16及图20～图23所示，显示基板1000还包括：设置在衬底200上的半导体层Poly，以及设置在半导体层Poly远离衬底200一侧的第一栅导电层Gate1。其中，半导体层Poly的材料可以包括非晶硅、单晶硅、多晶硅 或金属氧化物半导体材料。
示例性的，移位寄存器10中，扫描电路11的第一输出晶体管T4包括：第一有源层t4；第一有源层t4包括第一沟道部t42。复位电路的第二输出晶体管R4包括：第二有源层r4；第二有源层r4包括第二沟道部r42。
示例性的，第一有源层t4和第二有源层r4均位于半导体层Poly。也即，第一有源层t4和第二有源层r4同层设置。
本公开中所提及的“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。这样一来，可以同时制作第一有源层t4和第二有源层r4，有利于简化显示基板1000的制作工艺。
需要说明的是，半导体层Poly在衬底200上的正投影，与第一栅导电层Gate1在衬底200上的正投影具有交叠。其中，半导体层Poly中被第一栅导电层Gate1覆盖的部分，构成各晶体管的沟道部，半导体层Poly中未被第一栅导电层Gate1覆盖的部分，为导电部，构成各晶体管的第一极或第二极的一部分。沟道部具有沟道长度和沟道宽度。例如，沟道部的沟道长度指的是，晶体管的第一极和第二极之间的间距尺寸。沟道部的沟道宽度指的是，在垂直于晶体管的第一极指向第二极的方向上，沟道部的尺寸。
示例性的，第一沟道部t42的沟道宽度，大于或等于第二沟道部r42的沟道宽度。
例如，如图13及图20所示，第一沟道部t42的沟道宽度可以大于第二沟道部r42的沟道宽度。此处指的是，第一沟道部t42沿行方向X的尺寸，大于第二沟道部r42沿行方向X的尺寸。
由此，可以通过提高第一输出晶体管T4的沟道宽度来获得更高的工作电流，而工作电流的提高，代表着写入能力和保持能力的增强，进而可以降低显示基板的功耗。
又如，第一沟道部t42的沟道宽度也可以等于第二沟道部r42的沟道宽度。
示例性的，扫描电路11的第三输出晶体管T5包括：第三有源层t5。第三有源层t5包括第三沟道部(如图13所示的t52、t54和t56)。复位电路12的第四输出晶体管R5包括：第四有源层r5；第四有源层r5包括第四沟道部(如图20所示的r42、r44和r46)。
示例性的，第三有源层t5和第四有源层r5均位于半导体层Poly，也即第三有源层t5和第四有源层r5同层设置。这样一来，可以同时制作第三有源层t5和第四有源层r5，有利于简化显示基板1000的制作工艺。
示例性的，第三沟道部的沟道宽度，大于或等于第四沟道部的沟道宽度。
例如，如图13及图20所示，第三沟道部的沟道宽度可以大于第四沟道部的沟道宽度。此处指的是，第三沟道部沿行方向X的尺寸，大于第四沟道部沿行方向X的尺寸。
由此，可以通过提高第三输出晶体管T5的沟道宽度来获得更高的工作电流，而工作电流的提高，代表着写入能力和保持能力的增强，进而可以降低显示基板的功耗。
又如，第四沟道部的宽度可以等于第三沟道部的宽度。
第三沟道部和第四沟道部的沟道宽度方向可以由多种情况，可以根据实际情况进行设 置。
示例性的，如图13所示，第一有源层t4和第三有源层t5沿列方向Y依次设置。上述设置可以有效的减小第一有源层t4和第三有源层t5在列方向Y上的间距，减小扫描驱动电路100在显示基板1000上所占的面积，有利于实现显示基板1000的窄边框设计。
示例性的，如图13所示，第一有源层t4和第三有源层t5呈一体结构。例如，如图13所示，第一有源层t4可以由多个间隔一定距离的矩形块组成，第三有源层t5也可以由多个间隔一定距离的矩形块组成，而第一有源层t4的矩形块相应的与第三有源层t5的矩形块呈一体，组成新的矩形块。
采用上述设置方式，使得第一有源层t4和第三有源层t5之间没有间距，可以减小第一有源层t4和第三有源层t5在列方向Y上的尺寸，从而减小第一输出晶体管T4和第三输出晶体管T5在列方向所占的面积，进一步的可以减小扫描驱动电路100在显示基板1000上所占据的面积，有利于实现显示基板1000的窄边框设计。
示例性的，第二有源层r4和第四有源层r5沿列方向Y依次设置。上述设置可以有效的减小第二有源层r4和第四有源层r5在Y上的间距，减小扫描驱动电路100在显示基板1000上所占的面积，有利于实现显示基板1000的窄边框设计。
示例性的，如图20所示，第二有源层r4和第四有源层r5呈一体结构。
例如，如图20所示，第二有源层r4可以由多个间隔一定距离的矩形块组成，第四有源层r5也可以由多个间隔一定距离的矩形块组成，而第二有源层r4的矩形块相应的与第四有源层r5的矩形块呈一体，组成新的矩形块。
采用上述设置方式，使得第二有源层r4和第四有源层r5之间没有间距，可以减小第二有源层r4和第四有源层r5在列方向Y上的尺寸，从而减小第二输出晶体管R4和第四输出晶体管R5在列方向Y所占的面积，进一步的可以减小扫描驱动电路100在显示基板1000上所占据的面积，有利于实现显示基板1000的窄边框设计。
在一些实施例中，如图14所示，显示基板1000中，扫描电路11的第一输入晶体管T3包括：第五有源层t3。第五有源层t3设置在第一有源层t4远离多行子像素的一侧。
示例性的，扫描电路11的第一控制晶体管T2包括：第六有源层t2。第六有源层t2设置在第一有源层t4远离多行子像素的一侧。
示例性的，扫描电路11的第二控制晶体管T6包括：第七有源层t6。第七有源层t6设置在第五有源层t3和第一有源层t4之间。
示例性的，扫描电路11的第三控制晶体管T7包括：第八有源层t7。第八有源层t7设置在第五有源层t3和第一有源层t4之间。
示例性的，扫描电路11的第四控制晶体管T8包括：第九有源层t8。第九有源层t8设置在第五有源层t3和第八有源层t7之间。
示例性的，第五有源层t3、第六有源层t2、第七有源层t6、第八有源层t7、第九有源层t8均位于半导体层Poly。
示例性的，第五有源层t3、第六有源层t2、第七有源层t6、第八有源层t7以及第九有源层t8同层同材料，便于减少工艺流程。
示例性的，第五有源层t3的沟道长度方向、第六有源层t2的沟道长度方向、第七有源层t6的沟道长度方向、第八有源层t7的沟道长度方向、第九有源层t8的沟道长度方向，均沿列方向Y设置。上述设置方式，可以减少各个沟道部在行方向X所占用的面积，减少 扫描驱动电路100在显示基板1000上的面积占比，进而可以实现显示基板1000的窄边框设计。
在一些示例中，第五有源层t3和第六有源层t2沿列方向Y依次设置，呈一体结构。
上述设置方式，第五有源层t3和第六有源层t2沿列方向Y依次设置，可以减少第五有源层t3和第六有源层t2在行方向X上所占用的尺寸和面积，而第五有源层t3和第六有源层t2呈一体结构，使得第五有源层t3和第六有源层t2之间不存在间隙，可以减少第五有源层t3和第六有源层t2在列方向Y上，所占用的尺寸和面积，进一步可以减少扫描驱动电路100在显示基板1000上的面积占比，进而可以实现显示基板1000的窄边框设计，同时简化显示基板1000的制备工艺流程。
在一些示例中，第七有源层t6和第八有源层t7沿列方向Y依次设置，呈一体结构。
上述设置方式，第七有源层t6和第八有源层t7沿列方向Y依次设置，可以减少第七有源层t6和第八有源层t7在行方向X上所占用的尺寸和面积，而第七有源层t6和第八有源层t7呈一体结构，使得第七有源层t6和第八有源层t7之间不存在间隙，可以减少第七有源层t6和第八有源层t7在列方向Y上，所占用的尺寸和面积，进一步可以减少扫描驱动电路100在显示基板1000上的面积占比，进而可以实现显示基板1000的窄边框设计，同时简化显示基板1000的制备工艺流程。
在一些示例中，如图21所示，复位电路12的第三输入晶体管R3包括：第十有源层r3。第十有源层r3设置在第二有源层r4远离多行子像素的一侧。
示例性的，复位电路12的第五控制晶体管R2包括：第十一有源层r2。第十一有源层r2设置在第二有源层r4远离多行子像素的一侧。
示例性的，复位电路12的第六控制晶体管R6包括：第十二有源层r6。第十二有源层r6设置在第十有源层r3和第二有源层r4之间。
示例性的，复位电路12的第七控制晶体管R7包括：第十三有源层r7。第十三有源层r7设置在第十有源层r3和第二有源层r4之间。
示例性的，复位电路12的第八控制晶体管R8包括：第十四有源层r8。第十四有源层r8设置在第十有源层r3和第十三有源层r7之间。
示例性的，第十有源层r3、第十一有源层r2、第十二有源层r6、第十三有源层r7、第十四有源层r8均位于半导体层Poly。由此，上述各有源层可以同时制备，简化显示基板1000的制备工艺。
示例性的，第十有源层r3的沟道长度方向、第十一有源层r2的沟道长度方向、第十二有源层r6的沟道长度方向、第十三有源层r7的沟道长度方向、第十四有源层r8的沟道长度方向，均沿列方向Y设置。由此，可以减小上述有源层在行方向X所占据的宽度，有利于显示基板1000的窄边框设计。
在一些示例中，第十有源层r3和第十一有源层r2沿列方向Y依次设置，呈一体结构。
上述设置方式，第十有源层r3和第十一有源层r2沿列方向Y依次设置，可以减少第十有源层r3和第十一有源层r2在行方向X上所占用的尺寸和面积，而第十有源层r3和第十一有源层r2呈一体结构，使得第十有源层r3和第十一有源层r2之间不存在间隙，可以减少第十有源层r3和第十一有源层r2在列方向Y上，所占用的尺寸和面积，进一步可以减少扫描驱动电路100在显示基板1000上的面积占比，进而可以实现显示基板1000的窄边框设计，同时简化显示基板1000的制备工艺流程。
在一些示例中，第十二有源层r6和第十三有源层r7沿列方向Y依次设置，呈一体结构。
上述设置方式，第十二有源层r6和第十三有源层r7沿列方向Y依次设置，可以减少第十二有源层r6和第十三有源层r7在行方向X上所占用的尺寸和面积，而第十二有源层r6和第十三有源层r7呈一体结构，使得第十二有源层r6和第十三有源层r7之间不存在间隙，可以减少第十二有源层r6和第十三有源层r7在列方向Y上，所占用的尺寸和面积，进一步可以减少扫描驱动电路100在显示基板1000上的面积占比，进而可以实现显示基板1000的窄边框设计，同时简化显示基板1000的制备工艺流程。
示例性的，第一栅导电层Gate1与半导体层Poly交叠部分，分别形成第一输入晶体管T3的控制极、第二输入晶体管T1的控制极、第一控制晶体管T2的控制极、第二控制晶体管T6的控制极、第三控制晶体管T7的控制极、第四控制晶体管T8的控制极以及第三输入晶体管R3的控制极、第四输入晶体管R1的控制极、第五控制晶体管R2的控制极、第六控制晶体管R6的控制极、第七控制晶体管R7的控制极、第八控制晶体管R8的控制极。第一栅导电层Gate1形成第一电容器C1的第二极、第二电容器C2的第二极、第三电容器C10的第二极和第四电容器C20的第二极。
例如，第一栅导电层Gate1的材料包括导电金属。该导电金属可以包括铝、铜、钼中的至少一种，本公开不限于此。
在一些示例中，半导体层Poly和第一栅导电层Gate1之间设置有第一栅绝缘层，第一栅绝缘层用于将半导体层Poly和第一栅导电层Gate1电绝缘。
例如，第一栅绝缘层的材料包括氮化硅、氮氧化硅和氧化硅的无机绝缘材料中的任一种。第一栅绝缘层的材料可以包括二氧化硅，本公开不限于此。
示例性的，如图15、图16、图22及图23所示，显示基板1000包括：设置在半导体层Poly远离衬底200的一侧的第二栅导电层Gate2。
例如，第二栅导电层Gate2可以与第一栅导电层Gate1材料相同。
示例性的，扫描电路11的第二电容器C2的第一极板位于第二栅导电层Gate2。
示例性的，复位电路12的第四电容器C20的第一极板位于第二栅导电层Gate2。
例如，第一电容器C1、第二电容器C2和第三电容器C10、第四电容器C20的第一极板可以均位于第二栅导电层Gate2。由此，可以简化显示基板1000的制备工艺流程。
示例性的，扫描电路11的扫描信号输出端GO与第二电容器C2的第一极板呈一体结构。由此，可以简化扫描电路11的制备流程，从而简化显示基板1000的制备工艺。
示例性的，复位电路12的复位信号输出端RO与第四电容器C20的第一极板呈一体结构。由此，可以简化复位电路12的制备流程，从而简化显示基板1000的制备工艺流程。
在一些示例中，如图17及图24所示，显示基板1000还包括：设置在第二栅导电层Gate2远离衬底200的一侧的源漏导电层SD。
示例性的，第一输出晶体管T4的第二极与第三输出晶体管T5的第二极呈一体结构，且均位于源漏导电层SD。由此，可以简化扫描电路11的制备流程，从而简化显示基板1000的制备工艺流程。
示例性的，第二输出晶体管R4的第二极与第四输出晶体管R5的第二极呈一体结构，且均位于源漏导电层SD。由此，可以简化复位电路12的制备流程，从而简化显示基板1000的制备工艺流程。
示例性的，第一输出晶体管T4的第二极与第二电容器C2的第一极板电连接。
示例性的，扫描电路11的扫描信号输出端GO与第二电容器C2的第一极板呈一体结构。
例如，第一输出晶体管T4的第二极通过过孔与第二电容器C2的第一极板电连接。而由于扫描信号输出端GO与第二电容器C2的第一极板呈一体结构，因此，第一输出晶体管T4的第二极可以与扫描信号输出端GO实现电连接。
示例性的，第二输出晶体管R4的第二极与第四电容器C20的第一极板电连接。
示例性的，复位电路12的复位信号输出端RO与第四电容器C20的第一极板呈一体结构。
例如，第二输出晶体管R4的第二极通过过孔与第四电容器C20的第一极板电连接。而由于复位电路12的复位信号输出端RO与第四电容器C20的第一极板呈一体结构，因此，第二输出晶体管R4的第二极可以与复位信号输出端RO实现电连接。
在一些示例中，第二栅导电层Gate2和第一栅导电层Gate1之间设置有第二栅绝缘层。第二栅绝缘层用于将第二栅导电层Gate2和第一栅导电层Gate1电绝缘。
例如，第二栅绝缘层Gate2的材料包括氮化硅、氮氧化硅和氧化硅的无机绝缘材料中的任一种。第二栅绝缘层的材料可以包括二氧化硅，本公开不限于此。
在一些示例中，第二栅导电层Gate2和源漏导电层SD之间设置有第三栅绝缘层。第三栅绝缘层用于将第二栅导电层Gate2和源漏导电层SD电绝缘。
例如，第三栅绝缘层的材料包括氮化硅、氮氧化硅和氧化硅的无机绝缘材料中的任一种。第三栅绝缘层的材料可以包括二氧化硅，本公开不限于此。
在一些示例中，源漏导电层SD可以通过第三栅绝缘层、第二栅绝缘层、第一栅绝缘层上的过孔，与设置在半导体层Poly上各有源层的导电部连接，形成各晶体管的第一极和第二极。
图11示出了沿图10中沿A-A’向剖开后，显示面板1000的局部膜层剖视图。图11中，第二输入晶体管T1为双栅结构，也即，第二输入晶体管T1包括两个栅极g1，结合图13，第二输入晶体管T1的有源层t1包括两个沟道部(t12和t14)。
示例性的，图12示出了图11中沿B-B’向剖开后，显示面板1000的局部膜层剖视图。第二控制晶体管T6的控制极g6，与第一转接部e1的一端电连接，第一连接部e1的另一端与第一输入晶体管T3的第一极d3电连接，从而实现第二控制晶体管T6的控制极g6与第一输入晶体管T3的第一极d3的电连接。例如，上述第一转接部e1可以位于源漏导电层SD，第一转接部e1的一端与第二控制晶体管T6的控制极g6的电连接，可以通过过孔实现。
示例性的，图19所示的为沿图18中沿C-C’向剖开后，显示面板1000的局部膜层剖视图。第六控制晶体管R6的控制极rg6，与第二转接部e2的一端电连接，第二转接部e2的另一端与第三输入晶体管R3的第一极rd3电连接，从而实现与第三输入晶体管R3的第一极rd3的电连接。例如，第二转接部e2可以分为三部分，第二转接部e2的第一部分位于源漏导电层SD，该部分一端通过过孔与第六控制晶体管R6的控制极rg6电连接；第二转接部e2的第二部分位于第二栅导电层Gate2，该第二部分的一端通过过孔与第二转接部e2的第一部分的另一端电连接；第二转接部e2的第三部分位于源漏导电层SD，该部分的一端通过过孔与第二转接部e2的第二部分的另一端电连接，该部分的另一端与第三输入 晶体管R3的第一极rd3电连接。
第二控制晶体管T6的控制极与第一输入晶体管T3的第一极d3的电连接的方式，也可以采用图19所示出的第六控制晶体管R6的控制极与第三输入晶体管R3的第一极rd3的电连接的方式。第六控制晶体管R6的控制极与第三输入晶体管R3的第一极rd3的电连接的方式，也可以采用图12所示出的第二控制晶体管T6的控制极与第一输入晶体管T3的第一极d3的电连接的方式。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (28)

  1. 一种移位寄存器，应用于显示基板，所述显示基板包括多行子像素；
    所述移位寄存器，与一行子像素电连接，且被配置为向所述一行子像素传输扫描信号和复位信号；其中，
    所述移位寄存器包括：
    扫描电路，与第一输入信号端、第一时钟信号端、第二时钟信号端、第一电压信号端及第二电压信号端电连接；所述扫描电路被配置为，在所述第一输入信号端所传输的第一输入信号、所述第一时钟信号端所传输的第一时钟信号、所述第二时钟信号端所传输的第二时钟信号、所述第一电压信号端所传输的第一电压信号及所述第二电压信号端所传输的第二电压信号的配合作用下，输出所述扫描信号；以及，
    复位电路，与第二输入信号端、第三时钟信号端、第四时钟信号端、第三电压信号端及第四电压信号端电连接；所述复位电路被配置为，在所述第二输入信号端所传输的第二输入信号、所述第三时钟信号端所传输的第三时钟信号、所述第四时钟信号端所传输的第四时钟信号、所述第三电压信号端所传输的第三电压信号及所述第四电压信号端所传输的第四电压信号的配合作用下，输出所述复位信号；
    其中，所述扫描电路和所述复位电路之间相互独立输出信号。
  2. 根据权利要求1所述的移位寄存器，其中，所述扫描电路包括：第一输出晶体管；
    所述第一输出晶体管的第一极与所述第二电压信号端电连接，所述第一输出晶体管的第二极与扫描信号输出端电连接；
    所述复位电路包括：第二输出晶体管；
    所述第二输出晶体管的第一极与所述第四电压信号端电连接，所述第二输出晶体管的第二极与复位信号输出端电连接；
    其中，所述第一输出晶体管的沟道宽度，大于或等于所述第二输出晶体管的沟道宽度。
  3. 根据权利要求2所述的移位寄存器，其中，所述第一输出晶体管的沟道宽度与所述第二输出晶体管的沟道宽度的比例范围为1:1～20:1。
  4. 根据权利要求1～3中任一项所述的移位寄存器，其中，所述扫描电路包括：第三输出晶体管；
    所述第三输出晶体管的第一极与所述第二时钟信号端电连接，所述第三输出晶体管的第二极与扫描信号输出端电连接；
    所述复位电路包括：第四输出晶体管；
    所述第四输出晶体管的第一极与所述第四时钟信号端电连接，所述第四输出晶体管的第二极与复位信号输出端电连接；
    其中，所述第三输出晶体管的沟道宽度，大于或等于所述第四输出晶体管的沟道宽度。
  5. 根据权利要求4所述的移位寄存器，其中，所述第三输出晶体管的沟道宽度与所述第四输出晶体管的沟道宽度的比例范围为1:1～20:1。
  6. 根据权利要求1～5中任一项所述的移位寄存器，其中，所述扫描电路和所述复位电路沿行方向并列设置；
    或者，所述扫描电路和所述复位电路沿所述行方向交错设置。
  7. 根据权利要求1～6中任一项所述的移位寄存器，其中，相比于所述扫描电路，所述复位电路更靠近所述一行子像素。
  8. 根据权利要求1～7中任一项所述的移位寄存器，其中，所述扫描电路包括：第一输 入晶体管、第二输入晶体管、第一控制晶体管、第二控制晶体管、第三控制晶体管、第四控制晶体管、第一输出晶体管、第三输出晶体管、第一电容器和第二电容器；
    所述第一输入晶体管的控制极与所述第一时钟信号端电连接，所述第一输入晶体管的第一极与所述第一电压信号端电连接，所述第一输入晶体管的第二极与第二节点电连接；
    所述第二输入晶体管的控制极与所述第一时钟信号端电连接，所述第二输入晶体管的第一极与所述第一输入信号端电连接，所述第二输入晶体管的第二极与第一节点电连接；
    所述第一控制晶体管的控制极与所述第一节点电连接，所述第一控制晶体管的第一极与所述第一时钟信号端电连接，所述第一控制晶体管的第二极与所述第二节点电连接；
    所述第二控制晶体管的控制极与所述第二节点电连接，所述第二控制晶体管的第一极与所述第二电压信号端电连接，所述第二控制晶体管的第二极与第三节点电连接；
    所述第三控制晶体管的控制极与所述第二时钟信号端电连接，所述第三控制晶体管的第一极与所述第三节点电连接，所述第三控制晶体管的第二极与所述第一节点电连接；
    所述第四控制晶体管的控制极与所述第一电压信号端电连接，所述第四控制晶体管的第一极与所述第一节点电连接，所述第三控制晶体管的第二极与第四节点电连接；
    所述第一输出晶体管的控制极与所述第二节点电连接，所述第一输出晶体管的第一极与所述第二电压信号端电连接，所述第一输出晶体管的第二极与扫描信号输出端电连接；
    所述第三输出晶体管的控制极与所述第四节点电连接，所述第三输出晶体管的第一极与所述第二时钟信号端电连接，所述第三输出晶体管的第二极与所述扫描信号输出端电连接；
    所述第一电容器器的第一极板与所述第二电压信号端电连接，所述第一电容器的第二极板与所述第二节点电连接；
    所述第二电容器的第一极板与所述扫描信号输出端电连接，所述第二电容器的第二极板与所述第四节点电连接。
  9. 根据权利要求1～8中任一项所述的移位寄存器，其中，所述复位电路包括：第三输入晶体管、第四输入晶体管、第五控制晶体管、第六控制晶体管、第七控制晶体管、第八控制晶体管、第二输出晶体管、第四输出晶体管、第三电容器和第四电容器；
    所述第三输入晶体管的控制极与所述第三时钟信号端电连接，所述第三输入晶体管的第一极与所述第三电压信号端电连接，所述第三输入晶体管的第二极与第六节点电连接；
    所述第四输入晶体管的控制极与所述第三时钟信号端电连接，所述第四输入晶体管的第一极与所述第二输入信号端电连接，所述第四输入晶体管的第二极与第五节点电连接；
    所述第五控制晶体管的控制极与所述第五节点N5电连接，所述第五控制晶体管的第一极与所述第三时钟信号端电连接，所述第五控制晶体管的第二极与所述第六节点电连接；
    所述第六控制晶体管的控制极与所述第六节点电连接，所述第六控制晶体管的第一极与所述第四电压信号端电连接，所述第六控制晶体管的第二极与第七节点电连接；
    所述第七控制晶体管的控制极与所述第四时钟信号端电连接，所述第七控制晶体管的第一极与所述第七节点电连接，所述第七控制晶体管的第二极与所述第五节点电连接；
    所述第八控制晶体管的控制极与所述第三电压信号端电连接，所述第八控制晶体管的第一极与所述第五节点电连接，所述第八控制晶体管的第二极与第八节点电连接；
    所述第二输出晶体管的控制极与所述第六节点电连接，所述第二输出晶体管的第一极与所述第四电压信号端电连接，所述第二输出晶体管的第二极与所述复位信号输出端电连 接；
    所述第四输出晶体管的控制极与所述第八节点电连接，所述第四输出晶体管的第一极与所述第四时钟信号端电连接，所述第四输出晶体管的第二极与所述复位信号输出端电连接；
    所述第三电容器器的第一极板与所述第四电压信号端电连接，所述第三电容器的第二极板与所述第六节点电连接；
    所述第四电容器的第一极板与所述复位信号输出端电连接，所述第四电容器的第二极板与所述第八节点电连接。
  10. 一种扫描驱动电路，包括：如权利要求1～9中任一项所述的多个移位寄存器；其中，
    所述多个移位寄存器中各扫描电路沿列方向依次排列；
    所述多个移位寄存器中各复位电路沿所述列方向依次排列。
  11. 根据权利要求10所述的扫描驱动电路，还包括：
    沿所述列方向延伸的第一电压信号线，与所述扫描电路的第一电压信号端电连接；
    沿所述列方向延伸的第二电压信号线，与所述扫描电路的第二电压信号端电连接；
    沿所述列方向延伸的第三电压信号线，与所述复位电路的第三电压信号端电连接；以及，
    沿所述列方向延伸的第四电压信号线，与所述复位电路的第四电压信号端电连接；
    其中，所述扫描电路设置在所述第一电压信号线和所述第二电压信号线之间，所述复位电路设置在所述第三电压信号线和所述第四电压信号线之间。
  12. 根据权利要求11所述的扫描驱动电路，其中，所述第二电压信号线和所述第三电压信号线，设置在所述扫描电路和所述复位电路之间。
  13. 根据权利要求11或12所述的扫描驱动电路，还包括：
    沿所述列方向延伸的第一时钟信号线，与第2m-1个所述扫描电路的第一时钟信号端及第2m个所述扫描电路的第二时钟信号端电连接；
    沿所述列方向延伸的第二时钟信号线，与第2m-1个所述扫描电路的第二时钟信号端及第2m个所述扫描电路的第一时钟信号端电连接；
    沿所述列方向延伸的第三时钟信号线，与第2m-1个所述复位电路的第三时钟信号端及第2m个所述复位电路的第四时钟信号端电连接；
    沿所述列方向延伸的第四时钟信号线，与第2m-1个所述复位电路的第四时钟信号端及第2m个所述复位电路的第三时钟信号端电连接；m为正整数；
    其中，所述第一时钟信号线和所述第二时钟信号线，设置在所述扫描电路远离所述复位电路的一侧；
    所述第三时钟信号线和所述第四时钟信号线，设置在所述复位电路靠近所述扫描电路的一侧。
  14. 根据权利要求11～13中任一项所述的扫描驱动电路，还包括：
    沿所述列方向延伸的第一初始信号线，与所述多个移位寄存器中前n个移位寄存器的扫描电路的第一输入信号端电连接；n为正整数；
    沿所述列方向延伸的第二初始信号线，与所述多个移位寄存器中前i个移位寄存器的复位电路的第二输入信号端电连接；i为正整数；
    其中，所述第一初始信号线设置在所述扫描电路远离所述复位电路的一侧；
    所述第二初始信号线设置在所述复位电路靠近所述扫描电路的一侧。
  15. 一种显示基板，包括：
    衬底；
    设置在所述衬底上的多行子像素；以及，
    设置在所述衬底上的、如权利要求10～14中任一项所述的至少一个扫描驱动电路；
    其中，所述扫描驱动电路中，每个移位寄存器与一行子像素电连接，且被配置为向所述一行子像素传输扫描信号和复位信号。
  16. 根据权利要求15所述的显示基板，其中，所述扫描驱动电路的数量为两个；两个扫描驱动电路分别位于所述多行子像素的相对两侧。
  17. 根据权利要求15或16所述的显示基板，还包括：设置在所述衬底上的半导体层；
    所述移位寄存器中，扫描电路的第一输出晶体管包括：第一有源层；所述第一有源层包括第一沟道部；
    所述移位寄存器中，复位电路的第二输出晶体管包括：第二有源层；所述第二有源层包括第二沟道部；
    其中，所述第一有源层和所述第二有源层均位于所述半导体层；所述第一沟道部的沟道宽度，大于或等于所述第二沟道部的沟道宽度。
  18. 根据权利要求17所述的显示基板，其中，所述第一沟道部的沟道宽度方向和所述第二沟道部的沟道宽度方向，均沿行方向设置。
  19. 根据权利要求17或18所述的显示基板，其中，所述扫描电路的第三输出晶体管包括：第三有源层；所述第三有源层包括第三沟道部；
    所述复位电路的第四输出晶体管包括：第四有源层；所述第四有源层包括第四沟道部；
    其中，所述第三有源层和所述第四有源层均位于所述半导体层；所述第三沟道部的沟道宽度，大于或等于所述第四沟道部的沟道宽度。
  20. 根据权利要求19所述的显示基板，其中，所述第三沟道部的沟道宽度方向和所述第四沟道部的沟道宽度方向，均沿行方向设置。
  21. 根据权利要求19或20所述的显示基板，其中，所述第一有源层和所述第三有源层沿列方向依次设置；和/或，
    所述第二有源层和所述第四有源层沿列方向依次设置。
  22. 根据权利要求19～21中任一项所述的显示基板，其中，所述第一有源层和所述第三有源层呈一体结构；和/或，
    所述第二有源层和所述第四有源层呈一体结构。
  23. 根据权利要求17～22中任一项所述的显示基板，还包括：设置在所述半导体层远离所述衬底的一侧、且依次层叠的第二栅导电层和源漏导电层；
    所述扫描电路的第二电容器的第二极板位于所述第二栅导电层；
    所述第一输出晶体管的第二极与所述扫描电路的第三输出晶体管的第二极呈一体结构，且均位于所述源漏导电层；
    所述第一输出晶体管的第二极与所述第二电容器的第一极板电连接；
    所述扫描电路的扫描信号输出端与所述第二电容器的第一极板呈一体结构。
  24. 根据权利要求23所述的显示基板，其中，所述复位电路的第四电容器的第二极板 位于所述第二栅导电层；
    所述第二输出晶体管的第二极与所述复位电路的第四输出晶体管的第二极呈一体结构，且均位于所述源漏导电层；
    所述第二输出晶体管的第二极与所述第四电容器的第一极板电连接；
    所述复位电路的复位信号输出端与所述第四电容器的第一极板呈一体结构。
  25. 根据权利要求17～24中任一项所述的显示基板，其中，所述扫描电路的第一输入晶体管包括：设置在所述第一有源层远离所述多行子像素一侧的第五有源层；
    所述扫描电路的第一控制晶体管包括：设置在所述第一有源层远离所述多行子像素一侧的第六有源层；
    所述扫描电路的第二控制晶体管包括：设置在所述第五有源层和所述第一有源层之间的第七有源层；
    所述扫描电路的第三控制晶体管包括：设置在所述第五有源层和所述第一有源层之间的第八有源层；
    所述扫描电路的第四控制晶体管包括：设置在所述第五有源层和所述第八有源层之间的第九有源层；
    其中，所述第五有源层、所述第六有源层、所述第七有源层、所述第八有源层、所述第九有源层均位于所述半导体层；
    所述第五有源层的沟道长度方向、所述第六有源层的沟道长度方向、所述第七有源层的沟道长度方向、所述第八有源层的沟道长度方向、所述第九有源层的沟道长度方向，均沿所述列方向设置。
  26. 根据权利要求25所述的显示基板，其中，所述第五有源层和所述第六有源层沿所述列方向依次设置，呈一体结构；和/或，
    所述第七有源层和所述第八有源层沿所述列方向依次设置，呈一体结构。
  27. 根据权利要求25或26所述的显示基板，其中，
    所述复位电路的第三输入晶体管包括：设置在所述第二有源层远离所述多行子像素一侧的第十有源层；
    所述复位电路的第五控制晶体管包括：设置在所述第二有源层远离所述多行子像素一侧的第十一有源层；
    所述复位电路的第六控制晶体管包括：设置在所述第十有源层和所述第二有源层之间的第十二有源层；
    所述复位电路的第七控制晶体管包括：设置在所述第十有源层和所述第二有源层之间的第十三有源层；
    所述复位电路的第八控制晶体管包括：设置在所述第十有源层和所述第十三有源层之间的第十四有源层；
    其中，所述第十有源层、所述第十一有源层、所述第十二有源层、所述第十三有源层、所述第十四有源层均位于所述半导体层；
    所述第十有源层的沟道长度方向、所述第十一有源层的沟道长度方向、所述第十二有源层的沟道长度方向、所述第十三有源层的沟道长度方向、所述第十四有源层的沟道长度方向，均沿所述列方向设置。
  28. 根据权利要求27所述的显示基板，其中，所述第十有源层和所述第十一有源层沿 所述列方向依次设置，呈一体结构；和/或，
    所述第十二有源层和所述第十三有源层沿所述列方向依次设置，呈一体结构。
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