WO2021136496A1 - 移位寄存器及其驱动方法、栅极驱动电路、显示装置 - Google Patents

移位寄存器及其驱动方法、栅极驱动电路、显示装置 Download PDF

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Publication number
WO2021136496A1
WO2021136496A1 PCT/CN2020/142087 CN2020142087W WO2021136496A1 WO 2021136496 A1 WO2021136496 A1 WO 2021136496A1 CN 2020142087 W CN2020142087 W CN 2020142087W WO 2021136496 A1 WO2021136496 A1 WO 2021136496A1
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Prior art keywords
signal terminal
electrically connected
transistor
circuit
sub
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PCT/CN2020/142087
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English (en)
French (fr)
Inventor
黄耀
孙开鹏
邱远游
周洋
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US17/614,311 priority Critical patent/US11741902B2/en
Publication of WO2021136496A1 publication Critical patent/WO2021136496A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a shift register and a driving method thereof, a gate driving circuit, and a display device.
  • the gate driving circuit is a circuit for inputting scan driving signals (or gate signals) row by row to a plurality of gate signal lines (or gate lines) in a display device. Integrating the gate driving circuit on the display panel in the display device can reduce the production cost and manufacturing process difficulty of the display panel.
  • a shift register in one aspect, includes: a first input sub-circuit electrically connected to an input signal terminal, a first voltage signal terminal, a first clock signal terminal, and a first node; the first input sub-circuit is configured to respond to The input signal received at the input signal terminal and the first voltage signal received at the first voltage signal terminal, and the first clock signal received at the first clock signal terminal is transmitted to the first node A first output sub-circuit, electrically connected to the first node, the second voltage signal terminal and the first output signal terminal; the first output sub-circuit is configured to, under the control of the voltage of the first node , Transmitting the second voltage signal received at the second voltage signal terminal to the first output signal terminal, so that the first output signal terminal outputs the first output signal; the second input sub-circuit is connected to the first output signal terminal; The input signal terminal, the first clock signal terminal, and the second node are electrically connected; the second input sub-circuit is configured to respond to the first clock signal to receive the input at the input
  • the first input sub-circuit includes: a first transistor, a second transistor, and a first capacitor.
  • the gate of the first transistor is electrically connected to the input signal terminal, the first electrode of the first transistor is electrically connected to the first voltage signal terminal, and the second electrode of the first transistor is electrically connected to the third node Electric connection.
  • the gate of the second transistor is electrically connected to the third node, the first electrode of the second transistor is electrically connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the first clock signal terminal.
  • One node is electrically connected.
  • the first terminal of the first capacitor is electrically connected to the first clock signal terminal, and the second terminal of the first capacitor is electrically connected to the third node.
  • the second input sub-circuit includes: a third transistor.
  • the gate of the third transistor is electrically connected to the first clock signal terminal, the first electrode of the third transistor is electrically connected to the input signal terminal, and the second electrode of the third transistor is electrically connected to the first clock signal terminal. Two nodes are electrically connected.
  • the first output sub-circuit includes: a fourth transistor and a second capacitor.
  • the gate of the fourth transistor is electrically connected to the first node, the first electrode of the fourth transistor is electrically connected to the second voltage signal terminal, and the second electrode of the fourth transistor is electrically connected to the first node.
  • An output signal terminal is electrically connected.
  • the first terminal of the second capacitor is electrically connected to the first node, and the second terminal of the second capacitor is electrically connected to the second voltage signal terminal.
  • the second output sub-circuit includes: a fifth transistor and a third capacitor.
  • the gate of the fifth transistor is electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the first voltage signal terminal, and the second electrode of the fifth transistor is electrically connected to the first voltage signal terminal.
  • An output signal terminal is electrically connected.
  • the first end of the third capacitor is electrically connected to the second node, and the second end of the third capacitor is electrically connected to the first output signal end.
  • the shift register further includes: a control sub-circuit.
  • the control sub-circuit is electrically connected to the first voltage signal terminal, the second node, and the first node; the control sub-circuit is configured to, under the control of the voltage of the second node, connect The first voltage signal received at the first voltage signal terminal is transmitted to the first node, so as to control the first output sub-circuit to turn off when the second output sub-circuit outputs the first output signal.
  • control sub-circuit includes: a sixth transistor.
  • the gate of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the first voltage signal terminal, and the second electrode of the sixth transistor is electrically connected to the first voltage signal terminal.
  • One node is electrically connected.
  • the shift register further includes: a level reduction sub-circuit.
  • the level reduction sub-circuit is electrically connected to the second voltage signal terminal and the first output signal terminal; the potential reduction sub-circuit is configured to be at a stage when the first output sub-circuit outputs the second voltage , Cooperate with the first output sub-circuit to reduce the level of the first output signal output by the first output signal terminal.
  • the level reduction sub-circuit includes: a seventh transistor.
  • the gate of the seventh transistor is electrically connected to the first output signal terminal, the first electrode of the seventh transistor is electrically connected to the second voltage signal terminal, and the second electrode of the seventh transistor is electrically connected to the second voltage signal terminal.
  • the first output signal terminal is electrically connected.
  • the shift register further includes: a potential stabilization sub-circuit.
  • the potential stabilization sub-circuit is electrically connected to the second voltage signal terminal, the second node, and the fourth node; the potential stabilization sub-circuit is configured to, in response to the second voltage signal, connect the first The voltage of the two nodes is transmitted to the fourth node, and the voltage of the fourth node is stabilized.
  • the second output sub-circuit is electrically connected to the fourth node, and is electrically connected to the second node through the potential stabilization sub-circuit.
  • the potential stabilization sub-circuit includes: an eighth transistor.
  • the gate of the eighth transistor is electrically connected to the second voltage signal terminal, the first electrode of the eighth transistor is electrically connected to the second node, and the second electrode of the eighth transistor is electrically connected to the second node.
  • Four-node electrical connection In the case where the second output sub-circuit includes a fifth transistor and a third capacitor, the gate of the fifth transistor is electrically connected to the fourth node, and is connected to the second node through the seventh transistor. Electrically connected; the first end of the third capacitor is electrically connected to the fourth node, and is electrically connected to the second node through the seventh transistor.
  • the shift register further includes: a first inversion sub-circuit, electrically connected to the first output signal terminal, the first voltage signal terminal, and the second output signal terminal; An inverting sub-circuit is configured to, in response to the first output signal received at the first output signal terminal, transmit the first voltage signal received at the first voltage signal terminal to the second output Signal terminal; and, a second inverting sub-circuit with the first output signal terminal, the first voltage signal terminal, the second voltage signal terminal, the second clock signal terminal, and the second output signal terminal Electrically connected; the second inverting sub-circuit is configured to respond to the first output signal received at the first output signal terminal and the second clock signal received at the second clock signal terminal to The second voltage signal received at the second voltage signal terminal is transmitted to the second output signal terminal.
  • a first inversion sub-circuit electrically connected to the first output signal terminal, the first voltage signal terminal, and the second output signal terminal
  • An inverting sub-circuit is configured to, in response to the first output signal received at the first output signal terminal, transmit the
  • the first inversion sub-circuit includes: a ninth transistor.
  • the gate of the ninth transistor is electrically connected to the first output signal terminal, the first electrode of the ninth transistor is electrically connected to the first voltage signal terminal, and the second electrode of the ninth transistor is electrically connected to the first output signal terminal.
  • the second output signal terminal is electrically connected.
  • the second inversion sub-circuit includes: a tenth transistor, an eleventh transistor, a twelfth transistor, and a fourth capacitor.
  • the gate of the tenth transistor is electrically connected to the first output signal terminal, the first electrode of the tenth transistor is electrically connected to the first voltage signal terminal, and the second electrode of the tenth transistor is electrically connected to the first output signal terminal.
  • the fifth node is electrically connected.
  • the gate of the eleventh transistor is electrically connected to the second clock signal terminal, the first electrode of the eleventh transistor is electrically connected to the second voltage signal terminal, and the second terminal of the eleventh transistor is electrically connected.
  • the pole is electrically connected to the fifth node.
  • the gate of the twelfth transistor is electrically connected to the fifth node, the first electrode of the twelfth transistor is electrically connected to the second voltage signal terminal, and the second electrode of the twelfth transistor is electrically connected to the The second output signal terminal is electrically connected.
  • the first end of the fourth capacitor is electrically connected to the fifth node, and the second end of the fourth capacitor is electrically connected to the second output signal end.
  • a method for driving a shift register as described in any of the above embodiments which includes: in the first output stage, under the control of the voltage of the first node, the first output sub-circuit is turned on, The second voltage signal received at the second voltage signal terminal is transmitted to the first output signal terminal, and the first output signal terminal outputs the second voltage signal as the first output signal; under the control of the voltage of the second node , The second output sub-circuit is turned off; in the second output stage, under the control of the voltage of the first node, the first output sub-circuit is turned off; under the control of the voltage of the second node, the The second output sub-circuit is turned on, and transmits the first voltage signal received at the first voltage signal terminal to the first output signal terminal, and the first output signal terminal outputs the first voltage signal as a first output signal .
  • a gate driving circuit in another aspect, includes a plurality of cascaded shift registers as described in any of the above embodiments.
  • a display device in another aspect, includes the gate driving circuit as described in any of the above embodiments.
  • the display device further includes: a plurality of pixel driving circuits.
  • the plurality of pixel driving circuits are arranged in a plurality of rows along the first direction, and a row of pixel driving circuits includes at least two pixel driving circuits.
  • the input signal end of a shift register is electrically connected to the first scan signal end of a row of pixel drive circuits, and the first output signal end of the shift register is connected to the first scan signal end of the row of pixel drive circuits. 2.
  • the scanning signal terminal is electrically connected.
  • Fig. 1 is a structural diagram of a display device according to some embodiments of the present disclosure
  • FIG. 2 is a structural diagram of a display panel according to some embodiments of the present disclosure.
  • FIG. 3 is a structural diagram of a pixel driving circuit according to some embodiments of the present disclosure.
  • FIG. 4 is a timing diagram of a pixel driving circuit according to some embodiments of the present disclosure.
  • Fig. 5 is a structural diagram of a shift register according to some embodiments of the present disclosure.
  • Fig. 6 is a circuit diagram of a shift register according to some embodiments of the present disclosure.
  • Fig. 7 is a structural diagram of another shift register according to some embodiments of the present disclosure.
  • Fig. 8 is a circuit diagram of another shift register according to some embodiments of the present disclosure.
  • FIG. 9 is a structural diagram of another shift register according to some embodiments of the present disclosure.
  • FIG. 10 is a circuit diagram of another shift register according to some embodiments of the present disclosure.
  • FIG. 11 is a structural diagram of another shift register according to some embodiments of the present disclosure.
  • FIG. 12 is a circuit diagram of another shift register according to some embodiments of the present disclosure.
  • FIG. 13 is a structural diagram of another shift register according to some embodiments of the present disclosure.
  • FIG. 14 is a circuit diagram of another shift register according to some embodiments of the present disclosure.
  • FIG. 15 is a structural diagram of another shift register according to some embodiments of the present disclosure.
  • FIG. 16 is a circuit diagram of another shift register according to some embodiments of the present disclosure.
  • FIG. 17 is a structural diagram of another shift register according to some embodiments of the present disclosure.
  • FIG. 18 is a circuit diagram of another shift register according to some embodiments of the present disclosure.
  • FIG. 19 is a circuit diagram of another shift register according to some embodiments of the present disclosure.
  • 20 is a circuit diagram of another shift register according to some embodiments of the present disclosure.
  • FIG. 21 is a circuit diagram of another shift register according to some embodiments of the present disclosure.
  • Fig. 22 is a timing diagram of a shift register according to some embodiments of the present disclosure.
  • FIG. 23 is a structural diagram of a gate driving circuit according to some embodiments of the present disclosure.
  • FIG. 24 is a structural diagram of another gate driving circuit according to some embodiments of the present disclosure.
  • FIG. 25 is a structural diagram of another gate driving circuit according to some embodiments of the present disclosure.
  • FIG. 26 is a structural diagram of electrical connection between a gate driving circuit and sub-pixels according to some embodiments of the present disclosure
  • FIG. 27 is a structural diagram of another gate driving circuit electrically connected to a sub-pixel in some embodiments of the present disclosure.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, “plurality” means two or more.
  • connection and its extensions may be used.
  • the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content of this document.
  • a and B are electrically connected can be expressed as a direct electrical connection between A and B, or as a C is provided between A and B, and A and B are electrically connected indirectly through C.
  • the term “if” is optionally interpreted as meaning “when” or “when” or “in response to determination” or “in response to detection.”
  • the phrase “if it is determined" or “if [the stated condition or event] is detected” is optionally interpreted to mean “when determining" or “in response to determining" Or “when [stated condition or event] is detected” or “in response to detecting [stated condition or event]”.
  • the exemplary embodiments are described herein with reference to cross-sectional views and/or plan views as idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Therefore, variations in the shape with respect to the drawings due to, for example, manufacturing technology and/or tolerances can be envisaged. Therefore, the exemplary embodiments should not be construed as being limited to the shape of the area shown herein, but include shape deviations due to, for example, manufacturing.
  • an etched area shown as a rectangle will generally have curved features. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the area of the device, and are not intended to limit the scope of the exemplary embodiments.
  • the transistors used in the circuits provided by the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • thin film transistors are used as examples for description.
  • the control pole of each transistor used in the shift register is the gate of the transistor, the first pole is one of the source and drain of the transistor, and the second pole is the other of the source and drain of the transistor.
  • the source and drain of the transistor can be symmetrical in structure, the source and drain of the transistor can be structurally indistinguishable. That is to say, the first and second electrodes of the transistor in the embodiment of the present disclosure The two poles can be indistinguishable in structure.
  • the transistor is a P-type transistor
  • the first electrode of the transistor is a source and the second electrode is a drain; for example, when the transistor is an N-type transistor, the first electrode of the transistor is a drain
  • the second pole is the source.
  • nodes do not indicate actual components, but rather indicate the junctions of related electrical connections in the circuit diagram, that is, these nodes are junctions of related electrical connections in the circuit diagram, etc. Effective node.
  • Some embodiments of the present disclosure provide a shift register 100 and a driving method thereof, a gate driving circuit 1000, and a display device 2000.
  • the following is a driving method for the shift register 100 and the shift register 100, the gate driving circuit 1000, and The display devices 2000 are introduced separately.
  • the display device may be any device that displays an image regardless of whether it is moving (for example, video) or fixed (for example, still image), and whether it is text or image. More specifically, it is expected that the described embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, and personal data assistants (PDAs).
  • PDAs personal data assistants
  • Handheld or portable computers GPS receivers/navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, TV monitors, flat panel displays, computer monitors, car monitors (e.g., Odometer display, etc.), navigator, cockpit controller and/or display, camera view display (for example, the display of a rear-view camera in a vehicle), electronic photos, electronic billboards or signs, projectors, building structures, packaging And aesthetic structure (for example, a display of the image of a piece of jewelry), etc.
  • the above-mentioned display device 2000 includes a display panel PNL.
  • the display device 2000 may also include a frame, a circuit board, a display driver IC (Integrated Circuit, integrated circuit), and other electronic accessories.
  • the display panel PNL can be set in the frame.
  • the above-mentioned display device 2000 may be, for example, an organic light emitting diode (Organic Light Emitting Diode, OLED) display device, a quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, QLED) display device, and a micro light emitting diode (Micro Light Emitting Diode, abbreviated as OLED) display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum Dot Light Emitting Diodes
  • Micro LED display devices or Mini Light Emitting Diode (Mini LED) display devices, etc. are not specifically limited in the present disclosure.
  • the above-mentioned display device 2000 is increasingly used in the field of high-performance display due to its small size, low power consumption, good display effect, no radiation, and relatively low manufacturing cost.
  • the display panel PNL included in the display device 2000 is an OLED display panel.
  • the above-mentioned display panel PNL has a display area A and a frame area B arranged beside the display area A.
  • side refers to one side, two sides, three sides, or peripheral side of the display area A, that is, the frame area B can be located on one side, two sides, or three sides of the display area A, or the frame The area B can be set around the display area A.
  • the display panel PNL may include a plurality of sub-pixels P, a plurality of gate lines GL extending in a first direction X, and a plurality of data lines DL extending in a second direction Y.
  • the above-mentioned multiple sub-pixels P may be arranged in an array.
  • the sub-pixels P arranged in a row along the first direction X may be referred to as the same row sub-pixels P
  • the sub-pixels P arranged in a row along the second direction Y may be referred to as the same row sub-pixels P.
  • the sub-pixels P in the same row may be electrically connected to at least one gate line GL
  • the sub-pixels P in the same column may be electrically connected to one data line DL.
  • the number of gate lines GL electrically connected to the sub-pixels P in the same row can be set according to the structure of the sub-pixels P.
  • the above-mentioned gate driving circuit 1000 may be disposed in the frame area B and located on one side of the extending direction of the plurality of gate lines GL.
  • the gate driving circuit 1000 may be electrically connected to the plurality of gate lines GL, and input and output signals to the plurality of gate lines GL to drive the plurality of sub-pixels P for image display.
  • the gate driving circuit 1000 can also be arranged in the display area A.
  • the aforementioned gate driving circuit 1000 may be a gate driving IC.
  • the gate driving circuit 1000 may also be a GOA (Gate Driver on Array) circuit, that is, the gate driving circuit 1000 is directly integrated in the array substrate of the display panel PNL.
  • GOA Gate Driver on Array
  • the gate driving circuit 1000 can reduce the manufacturing cost of the display panel PNL; on the other hand, it can also reduce the frame size of the display panel PNL. , To achieve a narrow frame design.
  • the following embodiments are all described by taking the gate driving circuit 1000 as a GOA circuit as an example.
  • the structure of the sub-pixel P includes multiple types, which can be selected and set according to actual needs.
  • each sub-pixel P may include, for example, a pixel driving circuit 200 and a to-be-driven element 300 electrically connected to the pixel driving circuit 200.
  • the component to be driven 300 may be a current-driven light-emitting device
  • the component to be driven 300 may be a current-type light-emitting diode.
  • the current-type light-emitting diode may be a miniature light-emitting diode, a sub-millimeter light-emitting diode, an organic electroluminescent diode, or a quantum dot light-emitting diode.
  • the structure of the aforementioned pixel driving circuit 200 may be a 7T1C structure.
  • T represents a transistor
  • C represents a storage capacitor
  • the number before “T” represents the number of transistors
  • the number before “C” represents the number of storage capacitors.
  • the area occupied by the sub-pixels of the display panel in the display device will be compressed. Since the pixel drive circuit of the 7T1C structure includes a large number of device structures (ie, transistors and storage capacitors), it is difficult to reduce the area occupied by the pixel drive circuit, which in turn leads to difficulty in improving the resolution of the display device.
  • some embodiments of the present disclosure propose a pixel driving circuit 200.
  • the structure of the pixel driving circuit 200 is different from that of the pixel driving circuit of the 7T1C structure.
  • the structure of the pixel driving circuit 200 provided by the present disclosure may be a 6T1C structure.
  • the pixel driving circuit 200 may include: a first pixel transistor (also called a driving transistor) M1, a second pixel transistor (also called a switching transistor) M2, a third pixel transistor M3, a fourth pixel transistor M4, and a fifth pixel transistor M4.
  • the gate of the driving transistor M1 is electrically connected to the node N
  • the first electrode of the driving transistor M1 is electrically connected to the second electrode of the fifth pixel transistor M5
  • the second electrode of the driving transistor M1 is electrically connected to The first electrode of the third pixel transistor M3 and the first electrode of the sixth pixel transistor M6 are electrically connected.
  • the gate of the second pixel transistor M2 is electrically connected to the second scan signal terminal Gate2
  • the first electrode of the second pixel transistor M2 is electrically connected to the data signal terminal Data
  • the second electrode of the second pixel transistor M2 is electrically connected to the first electrode of the driving transistor M1.
  • the gate of the third pixel transistor M3 is electrically connected to the first scan signal terminal Gate1, and the second electrode of the third pixel transistor M3 is connected to the node N point.
  • the gate of the fourth pixel transistor M4 is electrically connected to the first scan signal terminal Gate1, the first electrode of the fourth pixel transistor M4 is electrically connected to the reset signal terminal Vinit, and the second electrode of the fourth pixel transistor M4 is electrically connected to the device to be driven 300
  • the anode is electrically connected.
  • the gate of the fifth pixel transistor M5 is electrically connected to the first enable signal terminal EM1, and the first electrode of the fifth pixel transistor M5 is electrically connected to the power supply voltage signal terminal VDD.
  • the gate of the sixth pixel transistor M6 is electrically connected to the second enable signal terminal EM2, and the second electrode of the sixth pixel transistor M6 is electrically connected to the anode of the element 300 to be driven.
  • One end of the storage capacitor Cst is electrically connected to the power supply voltage signal terminal VDD, and the other end is electrically connected to the node N.
  • the types of the above-mentioned multiple transistors can be the same or different, and can be selected and set according to actual needs.
  • the types of the foregoing multiple transistors are different.
  • the third pixel transistor M3 and the fourth pixel transistor M4 may be N-type transistors
  • the driving transistor M1, the second pixel transistor M2, the fourth or fifth pixel transistor M5, and the transistor M6 may be P-type transistors.
  • the pixel drive circuit 200 of the 6T1C structure provided by the present disclosure Compared with the pixel driving circuit of the 7T1C structure, the size of the sub-pixel P corresponding to the pixel driving circuit 200 of the 6T1C structure can also be smaller, which can effectively improve the resolution of the display panel PNL.
  • the structure of the pixel drive circuit 200 provided by the present disclosure is different from the structure of the 7T1C, this will cause the pixel drive circuit 200 provided in the present disclosure to have a different working sequence from the pixel drive circuit of the 7T1C structure.
  • the structure of the shift register 100 matched with the pixel drive circuit 200 provided in the present disclosure and the shift register matched with the pixel drive circuit of the 7T1C structure is different.
  • the working sequence of the pixel driving circuit 200 provided in the present disclosure may be as shown in FIG. 4.
  • the level of the first scan signal provided by the first scan signal terminal Gata1 is high, and the third pixel transistor M3 and the fourth pixel transistor M4 can be turned on under the control of the first scan signal.
  • the fourth pixel transistor M4 can transmit the reset signal received at the reset signal terminal Vinit to the anode of the element to be driven 300, and reset the anode of the element to be driven 300.
  • the level of the second enable signal provided by the second enable signal terminal EM2 is low, and the sixth pixel transistor M6 can be turned on under the control of the second enable signal to receive and transmit the reset signal to the sixth pixel The first pole of transistor M6.
  • the third pixel transistor M3 may receive and transmit the reset signal to the node N.
  • the level of the first scan signal is still at a high level, and the third pixel transistor M3 remains in an on state.
  • the level of the second enable signal becomes a low level, and the sixth pixel transistor M6 is turned off under the control of the second enable signal.
  • the level of the second scan signal provided by the second scan signal terminal Gata2 is low, and the second pixel transistor M2 can be turned on under the control of the second scan signal to transmit the data signal received at the data signal terminal Data to The second pole of the second pixel transistor M2.
  • the voltage of the node N becomes low level under the action of the reset signal.
  • the driving transistor M1 can be turned on under the control of the node N, receives a data signal from the second electrode of the second pixel transistor M2, and transmits the data signal to the node N.
  • the data signal continues to be transmitted to the node N and continues to charge the storage capacitor Cst until the absolute value of Vgs (the voltage difference between the gate and the first electrode of the driving transistor M1) and Vth (the threshold value of the driving transistor M1) The difference between the absolute values of the voltage) is less than zero, so that the driving transistor M1 is turned off.
  • the threshold voltage of the driving transistor M1 is also written into the node N to achieve compensation for the threshold voltage of the driving transistor M1.
  • the level of the first scan signal becomes a low level, and the third pixel transistor M3 is turned off under the control of the first scan signal.
  • the level of the second scan signal is still low, the second pixel transistor M2 remains in the on state, and continues to transmit the data signal to the first electrode of the driving transistor M1.
  • the level of the second scan signal becomes a high level, and the second pixel transistor M2 is turned off under the control of the second scan signal.
  • the level of the first enable signal provided by the first enable signal terminal EM1 changes to a low level, and the fifth pixel transistor M5 is turned on under the control of the first enable signal to reduce the power supply voltage transmitted by the power supply voltage signal terminal VDD.
  • the signal is transmitted to the first pole of the driving transistor M1.
  • the second enable signal provided by the second enable signal terminal EM2 is at a low level, and the sixth pixel transistor M6 is turned on under the control of the second enable signal, so that the driving transistor M1 is electrically connected to the component to be driven 300 , The component to be driven 300 starts to emit light under the driving of the current provided by the driving transistor M1.
  • the first scan signal terminal Gate1 and the second scan signal terminal Gate2 in the pixel driving circuit 200 need to be provided with the first scan signal and the second scan signal having the waveforms shown in FIG. 4 .
  • the time range of the interval between the first scan signal and the second scan signal is, for example, 1H-2H, and H is the time required for the data signal provided by the data signal terminal Data to be written into a row of sub-pixels P.
  • some embodiments of the present disclosure provide a shift register 100 that can transmit the first scan signal and the second scan signal to the pixel driving circuit 200 described above.
  • each transistor as a P-type transistor as an example, the structure of the shift register 100 is schematically described.
  • each transistor may also be an N-type transistor, or partly a P-type transistor, and partly an N-type transistor, which is not limited in this application.
  • timing diagrams may also be different, so the timing diagrams in this application are not limited accordingly.
  • the shift register 100 includes: a first input sub-circuit 1, a second input sub-circuit 3, a first output sub-circuit 2 and a second output sub-circuit 4.
  • the first input sub-circuit 1 is electrically connected to the input signal terminal Input, the first voltage signal terminal VGH, the first clock signal terminal CK1, and the first node Q1.
  • the input signal terminal Input is used to receive an input signal and input the input signal to the first input sub-circuit 1.
  • the first voltage signal terminal VGH is used to receive the first voltage signal and input the first voltage signal to the first input sub-circuit 1.
  • the first clock signal terminal CK1 is used to receive the first clock signal and input the first clock signal to the first input sub-circuit 1.
  • the first input sub-circuit 1 is configured to respond to the input signal received at the input signal terminal Input and the first voltage signal received at the first voltage signal terminal VGH, to receive the first clock signal terminal CK1 A clock signal is transmitted to the first node Q1.
  • the first input sub-circuit 1 may be connected between the input signal and the first voltage.
  • the signals are turned on under common control, and the first clock signal is received and transmitted to the first node Q1.
  • the first output sub-circuit 2 is electrically connected to the first node Q1, the second voltage signal terminal VGL, and the first output signal terminal Out1.
  • the second voltage signal terminal VGL is used to receive the second voltage signal and input the second voltage signal to the first output sub-circuit 2.
  • the first output sub-circuit 2 is configured to, under the control of the voltage of the first node Q1, transmit the second voltage signal received at the second voltage signal terminal VGL to the first output signal terminal Out1, so that the first output The signal terminal Out1 outputs the first output signal.
  • the first output sub-circuit 2 may be turned on under the control of the voltage of the first node Q1, and receive and The second voltage signal is transmitted to the first output signal terminal Out1.
  • the first output signal terminal Out1 can output the second voltage signal as the first output signal.
  • the second input sub-circuit 3 is electrically connected to the input signal terminal Input, the first clock signal terminal CK1 and the second node Q2.
  • the input signal terminal Input is also used to input an input signal to the second input sub-circuit 3.
  • the first clock signal terminal CK1 is also used to input the first clock signal to the second input sub-circuit 3.
  • the second input sub-circuit 3 is configured to transmit the input signal received at the input signal terminal Input to the second node Q2 in response to the first clock signal received at the first clock signal terminal CK1.
  • the second input sub-circuit 3 may be turned on under the control of the first clock signal to receive and The input signal is transmitted to the second node Q2.
  • the second output sub-circuit 4 is electrically connected to the second node Q2, the first voltage signal terminal VGH, and the first output signal terminal Out1.
  • the first voltage signal terminal VGH is also used to input a first voltage signal to the second output sub-circuit 4.
  • the second output sub-circuit 4 is configured to transmit the first voltage signal received at the first voltage signal terminal VGH to the first output signal terminal Out1 under the control of the voltage of the second node Q2.
  • the second output sub-circuit 4 may be turned on under the control of the voltage of the second node Q2, and receive and The first voltage signal is transmitted to the first output signal terminal Out1.
  • the first output signal terminal Out1 can output the first voltage signal as the first output signal.
  • the above-mentioned first voltage signal and the second voltage signal are different.
  • the voltage value of one of the first voltage signal and the second voltage signal is greater than the reference voltage, and the voltage value of the other is less than the reference voltage.
  • the reference voltage may be, for example, the average value of the voltage value of the first voltage signal and the voltage value of the second voltage signal.
  • the first voltage signal is, for example, a gate-off voltage signal; the second voltage signal is, for example, a gate-on voltage.
  • the first voltage signal is, for example, a DC high-level signal
  • the second voltage signal is, for example, a DC low-level signal.
  • the high level and the low level in the present disclosure are relative values.
  • the high level is 15V and the low level is 5V. Therefore, the low level is not limited to a level less than or equal to 0V.
  • the voltage value of the first voltage signal may be 6V
  • the voltage value of the second voltage signal may be -6V
  • the reference voltage may be 0V
  • the shift register 100 controls the output of the first output subcircuit 2 through the first input subcircuit 1 and controls the output of the second output subcircuit 4 through the second input subcircuit 3.
  • the first output sub-circuit 2 and the second output sub-circuit 4 conduct output signals in different time periods.
  • the first output sub-circuit 2 is turned on earlier than the second output sub-circuit 4.
  • the second voltage signal (the level is low) output by the first output sub-circuit 2 can be used as the first half of the first output signal (that is, the part corresponding to the S2 and S3 stages), and the second output sub-circuit 4 outputs
  • the first voltage signal (the level is high) can be used as the second half of the first output signal (that is, the part corresponding to the S4 stage and the S5 stage), and the second voltage signal and the first voltage signal can be formed in order The first output signal.
  • the waveform of the input signal transmitted by the input signal terminal Input of the shift register 100 is the same as the waveform required by the first scan signal terminal Gate1 of the pixel driving circuit 200 described above.
  • the waveform of the first output signal output by the first output signal terminal Out1 of the shift register 100 is the same as the waveform required by the second scan signal terminal Gate2 of the pixel driving circuit 200 described above.
  • the input signal terminal Input of the shift register 100 can be connected to the pixel drive circuit 200 of the corresponding row of sub-pixels P at the same time.
  • a scan signal terminal Gate1 is electrically connected, that is, in the above-mentioned shift register 100, the input signal transmitted by the input signal terminal Input is used as the first scan signal of the corresponding pixel driving circuit 200.
  • the first output signal terminal Out1 of the shift register 100 may be electrically connected to the second scan signal terminal Gate2 of the pixel driving circuit 200 in the corresponding row of sub-pixels P, that is, in the above-mentioned shift register 100, the first output signal terminal The first output signal output by Out1 is used as the second scanning signal of the corresponding pixel driving circuit 200.
  • the shift register 100 By electrically connecting the shift register 100 to the pixel driving circuit 200 of the corresponding row of sub-pixels P, the shift register 100 can be used to provide the pixel driving circuit 200 of the corresponding row of sub-pixels P with the required working timing to drive the corresponding row of sub-pixels P.
  • the sub-pixel P performs display.
  • the first input sub-circuit 1, the second input sub-circuit 3, the first output sub-circuit 2 and the second output sub-circuit 4 are set, and the first input sub-circuit An input sub-circuit 1, a second input sub-circuit 3, a first output sub-circuit 2 and a second output sub-circuit 4 are respectively electrically connected to the corresponding signal terminals.
  • the mutual cooperation between the signal terminals can be used to make the first output
  • the sub-circuit 2 and the second output sub-circuit 4 are turned on at different time periods, and the second voltage signal output by the first output sub-circuit 2 and the first voltage signal output by the second output sub-circuit 4 together form a first output signal.
  • the waveform of the input signal transmitted by the output signal terminal Input in the shift register 100 provided by the present disclosure is the same as the waveform required by the first scanning signal terminal Gate1 of the pixel driving circuit 200, and the first output signal terminal Out1 outputs the same waveform.
  • the waveform of an output signal is the same as the waveform required by the second scan signal terminal Gate2 of the pixel drive circuit 200, so that the shift register 100 can be used to provide the pixel drive circuit 200 with the 6T1C structure with the first scan signal it needs.
  • the second scan signal to realize the display driving of the corresponding sub-pixel P. That is, the shift register 100 provided in the present disclosure can be applied to the pixel driving circuit 200 of the 6T1C structure described above.
  • first input sub-circuit 1 The structures of the first input sub-circuit 1, the first output sub-circuit 2, the second input sub-circuit 3 and the second output sub-circuit 4 will be schematically described below.
  • the first input sub-circuit 1 includes: a first transistor T1, a second transistor T2, and The first capacitor C1.
  • the gate of the first transistor T1 is electrically connected to the input signal terminal Input
  • the first electrode of the first transistor T1 is electrically connected to the first voltage signal terminal VGH
  • the second transistor T1 is electrically connected to the first voltage signal terminal VGH.
  • the pole is electrically connected to the third node Q3.
  • the input signal transmitted by the input signal terminal Input can control the turning on or turning off of the first transistor T1.
  • the first transistor T1 is configured to transmit the first voltage signal received at the first voltage signal terminal VGH to the third node Q3 under the control of the input signal.
  • the first transistor T1 may be turned on under the control of the input signal to receive and transmit the first voltage signal to the third node Q3.
  • the gate of the second transistor T2 is electrically connected to the third node Q3 (so that the second electrode of the first transistor T1 is electrically connected to the gate of the second transistor T2), and the second transistor The first electrode of T2 is electrically connected to the first clock signal terminal CK1, and the second electrode of the second transistor T2 is electrically connected to the first node Q1.
  • the second transistor T2 is configured to transmit the first clock signal received at the first clock signal terminal CK1 to the first node Q1 under the control of the voltage of the third node Q3.
  • the second transistor T2 may be turned on under the control of the voltage of the third node Q3 to receive and transmit the first clock signal to the first node Q1.
  • the first terminal of the first capacitor C1 is electrically connected to the first electrode of the second transistor T2, and the second terminal of the first capacitor C1 is electrically connected to the third node Q3.
  • the first capacitor C1 is configured such that the voltage of the third node Q3 jumps with the first clock signal.
  • the voltage of the third node Q3 may become a low level under the action of the first capacitor C1.
  • the above-mentioned first input sub-circuit 1 can control the output condition of the signal of the first output sub-circuit 2.
  • the first voltage signal output by the first transistor T1 and the first capacitor C1 can cooperate with each other to control the turning on or off of the second transistor T2, thereby controlling the first clock signal to the first output
  • the first clock signal can control the on or off of the first output sub-circuit 2, that is, control the signal output status of the first output sub-circuit 2.
  • the second input sub-circuit 3 includes a third transistor T3.
  • the gate of the third transistor T3 is electrically connected to the first clock signal terminal CK1
  • the first electrode of the third transistor T3 is electrically connected to the input signal terminal Input
  • the second electrode of the third transistor T3 is electrically connected to the input signal terminal Input.
  • the pole is electrically connected to the second node Q2.
  • the first clock signal transmitted by the first clock signal terminal CK1 can control the turning on or turning off of the third transistor T3.
  • the third transistor T3 is configured to transmit the input signal received at the input signal terminal Input to the second node Q2 under the control of the first clock signal.
  • the third transistor T3 may be turned on under the control of the first clock signal to receive and transmit the first clock signal to the second node Q2.
  • the input signal transmitted to the second node Q2 can further control the signal output condition of the second output sub-circuit 4.
  • the structures of the first input sub-circuit 1 and the second input sub-circuit 3 described above are relatively simple and easy to manufacture; moreover, it is beneficial to reduce the size of the shift register 100 and reduce the size of the frame area B, so that the display device 2000 can be narrow. Border design.
  • the first output sub-circuit 2 includes a fourth transistor T4 and a second capacitor C2.
  • the gate of the fourth transistor T4 is electrically connected to the first node Q1
  • the first electrode of the fourth transistor T4 is electrically connected to the second voltage signal terminal VGL
  • the second electrode of the fourth transistor T4 is electrically connected to the second voltage signal terminal VGL.
  • the pole is electrically connected to the first output signal terminal Out1.
  • the first input sub-circuit 1 is electrically connected to the first node Q1
  • the gate of the fourth transistor T4 is also electrically connected to the first node Q1
  • the first input sub-circuit 1 transmits the first clock signal to the first node Q1, It can be further transferred to the gate of the fourth transistor T4.
  • the fourth transistor T4 is configured to transmit the second voltage signal received at the second voltage signal terminal VGL to the first output signal terminal Out1 under the control of the voltage of the first node Q1.
  • the fourth transistor T4 may be turned on under the control of the voltage of the first node Q1 to receive the second voltage signal provided by the second voltage signal terminal VGL , And transmit the second voltage signal to the first output signal terminal Out1.
  • the first terminal of the second capacitor C2 is electrically connected to the first node Q1
  • the second terminal of the second capacitor C2 is electrically connected to the second voltage signal terminal VGL.
  • the second capacitor C2 is configured to store charges to maintain the potential of the first node Q1.
  • the second capacitor C2 is also charged. After the first input sub-circuit 1 is turned off, the second capacitor C2 can be discharged to maintain the potential of the first node Q1, thereby keeping the fourth transistor T4 in the on state.
  • the second output sub-circuit 4 includes: a fifth transistor T5 and a third capacitor C3.
  • the gate of the fifth transistor T5 is electrically connected to the second node Q2
  • the first electrode of the fifth transistor T5 is electrically connected to the first voltage signal terminal VGH
  • the second electrode of the fifth transistor T5 is electrically connected to the first voltage signal terminal VGH.
  • the pole is electrically connected to the first output signal terminal Out1.
  • the second input sub-circuit 3 is electrically connected to the second node Q2
  • the gate of the fifth transistor T5 is also electrically connected to the second node Q2
  • the input signal transmitted from the second input sub-circuit 3 to the second node Q2 can be further Transfer to the gate of the fifth transistor T5.
  • the fifth transistor T5 is configured to transmit the first voltage signal received at the first voltage signal terminal VGH to the first output signal terminal Out1 under the control of the voltage of the second node Q2.
  • the fifth transistor T5 may be turned on under the control of the voltage of the second node Q2 to receive the first voltage signal provided by the first voltage signal terminal VGH , And transmit the first voltage signal to the first output signal terminal Out1.
  • the first terminal of the third capacitor C3 is electrically connected to the second node Q2, and the second terminal of the third capacitor C3 is electrically connected to the first voltage signal terminal VGH.
  • the third capacitor C3 is configured to store charges to maintain the potential of the second node Q2.
  • the third capacitor C3 is also charged. After the second input sub-circuit 3 is turned off, the third capacitor C3 can be discharged to maintain the potential of the second node Q2, thereby keeping the fifth transistor T5 in the on state.
  • the above-mentioned shift register 100 further includes: a control sub-circuit 5.
  • control sub-circuit 5 is electrically connected to the first voltage signal terminal VGH, the second node Q2, and the first node Q1.
  • control sub-circuit 5 is configured to transmit the first voltage signal received at the first voltage signal terminal VGH to the first node Q1 under the control of the voltage of the second node Q2, so that the second output sub-circuit 4 In the stage of outputting the first output signal, control the first output sub-circuit 2 to turn off.
  • the first output sub-circuit 2 and the second output sub-circuit 4 are turned on in different periods, and the second voltage signal can be output as the first output signal during the period when the first output sub-circuit 2 is turned on; During the period when the second output sub-circuit 4 is turned on, the first voltage signal can be output as the first output signal.
  • the second output sub-circuit 4 outputs the first output signal (that is, the first voltage signal) for a relatively long time, then during the second output sub-circuit 4 outputting the first output signal, the voltage of the first node Q1 may change Decrease, which in turn causes the first output sub-circuit 2 to output a signal (that is, the second voltage signal), which will affect the accuracy of the first output signal and affect the stability of the shift register 100.
  • control sub-circuit 5 by setting the control sub-circuit 5, the control sub-circuit 5 can be used to ensure that the first output sub-circuit 2 remains in the off state and no signal is output during the stage when the second output sub-circuit 4 outputs the first output signal. In this way, the accuracy and stability of the output of the shift register 100 can be ensured, and the accuracy of the first output signal can be ensured.
  • control sub-circuit 5 The structure of the control sub-circuit 5 is schematically described below.
  • control sub-circuit 5 includes a sixth transistor T6.
  • the gate of the sixth transistor T6 is electrically connected to the second node Q2
  • the first electrode of the sixth transistor T6 is electrically connected to the first voltage signal terminal VGH
  • the second electrode of the sixth transistor T6 is electrically connected to the first voltage signal terminal VGH.
  • the pole is electrically connected to the first node Q1.
  • the sixth transistor T6 is configured to transmit the first voltage signal received at the first voltage signal terminal VGH to the first node Q1 under the control of the voltage of the second node Q2.
  • the sixth transistor T6 can be turned on under the control of the voltage of the second node Q2, and the first voltage signal provided by the first voltage signal terminal VGH Transmitted to the first node Q1. Since the first voltage signal is a DC high-level signal, the voltage of the first node Q1 can be increased under the action of the first voltage signal, and the fourth transistor T4 can be turned off under the action of the first node Q1 of the high level , So that the first output sub-circuit 2 has no signal output.
  • the working stages of the shift register 100 include: S1 stage, S2 stage, S3 stage, S4 stage, and S1 stage.
  • the sequence of the multiple working stages may be, for example, S2 stage, S3 stage, S4 stage, S5 stage, S1 stage, where the sum of the time from stage S1 to stage S5 may be equal to the time for the display panel PNL to display one frame of picture, for example.
  • the S4 stage and the S5 stage will be cycled.
  • the cycle time is related to the time of displaying a frame of picture
  • the time of displaying a frame of picture is related to the resolution of the display panel PNL.
  • the level of the input signal provided by the input signal terminal Input is high, and the first transistor T1 in the first input sub-circuit 1 is turned off under the control of the input signal.
  • the level of the first clock signal provided by the first clock signal terminal CK1 is low.
  • the voltage of the third node Q3 jumps to a low level due to the function of the first capacitor C1.
  • the second transistor T2 can be turned on under the action of the voltage of the third node Q3, and receives and transmits the first clock signal to the first node Q1, so that the voltage of the first node Q1 is reduced.
  • the fourth transistor T4 electrically connected to the first node Q1 can be turned on under the action of the first node Q1, so that the first output signal terminal Out1 outputs the second voltage signal provided by the second voltage signal terminal VGL.
  • the level of the first clock signal is low, the level of the input signal is high, and the third transistor T3 in the second input sub-circuit 3 is turned on under the control of the first clock signal to receive and transmit the input signal To the second node Q2, the voltage of the second node Q2 rises.
  • the sixth transistor T6 in the control sub-circuit 5 is turned off under the control of the voltage of the second node Q2
  • the fifth transistor T5 in the second output sub-circuit 4 is turned off under the control of the voltage of the second node Q2, so that the second The output sub-circuit 4 has no signal output.
  • the first output signal output by the first output signal terminal Out1 is equal to the second voltage signal.
  • the level of the input signal provided by the input signal terminal Input is low, and the first transistor T1 is turned on under the control of the input signal, and will be at the first voltage signal terminal VGH.
  • the first voltage signal received at is transmitted to the third node Q3, so that the voltage of the third node Q3 rises.
  • the second transistor T2 is turned off under the control of the voltage of the third node Q3, so that the first input sub-circuit 1 has no signal output.
  • the second capacitor C2 In the above-mentioned S2 stage, while the second transistor T2 is receiving and transmitting the low-level first clock signal to the first node Q1, the second capacitor C2 will also be charged. In the S3 stage, due to the discharge of the second capacitor C2, the voltage of the first node Q1 remains at the low level in the S2 stage, so that the fourth transistor T4 remains on, and the first output signal terminal Out1 outputs the second voltage The second voltage signal provided by the signal terminal VGL.
  • the level of the first clock signal changes to a high level, and the third transistor T3 is turned off under the control of the first clock signal.
  • the third capacitor C3 will also be charged.
  • the voltage of the second node Q2 remains at the high level in the S2 phase, so that the fifth transistor T5 remains in the off state, and the second output sub-circuit 4 has no signal output.
  • the first output signal output by the first output signal terminal Out1 is equal to the second voltage signal.
  • the level of the input signal provided by the input signal terminal Input is low, and the first transistor T1 is turned on under the control of the input signal, and will be at the first voltage signal terminal VGH
  • the first voltage signal received at is transmitted to the third node Q3, so that the voltage of the third node Q3 rises.
  • the second transistor T2 is turned off under the control of the voltage of the third node Q3, so that the first input sub-circuit 1 has no signal output.
  • the level of the first clock signal is low, and the third transistor T3 is turned on under the control of the first clock signal, and receives and transmits a low-level input signal to the second node Q2, so that the voltage of the second node Q2 is reduced .
  • the sixth transistor T6 is turned on under the control of the voltage of the second node Q2, and transmits the first voltage signal received at the first voltage signal terminal VGH to the first node Q1, so that the voltage of the first node Q1 rises, thereby It is ensured that the fourth transistor T4 remains in the off state, so that the first output sub-circuit 2 has no signal output.
  • the fifth transistor T5 is turned on under the control of the voltage of the second node Q2, so that the first output signal terminal Out1 outputs the first voltage signal provided by the first voltage signal terminal VGH.
  • the first output signal output by the first output signal terminal Out1 is equal to the first voltage signal.
  • the level of the input signal provided by the input signal terminal Input is low, and the first transistor T1 is turned on under the control of the input signal.
  • the first voltage signal received at is transmitted to the third node Q3, so that the voltage of the third node Q3 rises.
  • the second transistor T2 is turned off under the control of the voltage of the third node Q3, so that the first input sub-circuit 1 has no signal output.
  • the second node N2 maintains the high potential of the S4 stage, the fourth transistor T4 is turned off, and the first output sub-circuit 12 has no signal output.
  • the level of the first clock signal changes to a high level, and the third transistor T3 is turned off under the control of the first clock signal.
  • stage S4 while the sixth transistor T6 receives and transmits the high-level first voltage signal to the first node Q1, the second capacitor C2 is also charged.
  • the third transistor T3 transmits the low-level input signal to the second node Q2, the third capacitor C3 is also charged.
  • the S5 stage due to the discharge of the second capacitor C2, the voltage of the first node Q1 remains at the high level in the S4 stage, so that the fourth transistor T4 remains in the off state, and the first output sub-circuit 2 has no signal output.
  • the third capacitor C3 is discharged, the voltage of the second node Q2 remains at the low level of the S4 stage, so that the fifth transistor T5 remains in the on state, and the first output signal terminal Out1 outputs the voltage provided by the first voltage signal terminal VGH.
  • the first voltage signal is the first voltage signal.
  • the first output signal output by the first output signal terminal Out1 is equal to the first voltage signal.
  • the level of the input signal provided by the input signal terminal Input is high, and the first transistor T1 is turned off under the control of the input signal.
  • the level of the first clock signal is high. Due to the effect of the first capacitor C1, the voltage of the third node Q3 jumps to a high level, and the second transistor T2 can be turned off under the action of the voltage of the third node Q3 , So that the first input sub-circuit 1 has no signal output.
  • the voltage of the first node Q1 is maintained at the high level in the S5 stage, and the fourth transistor T4 can be turned off under the action of the voltage of the first node Q1, so that the first output sub-circuit 2 has no output signal.
  • the level of the first clock signal is high, and the third transistor T3 can be turned off under the action of the voltage of the first clock signal. Due to the action of the third capacitor C3, the voltage of the second node Q2 is maintained at the low level of the S5 stage, and the fifth transistor T5 can be turned on under the action of the voltage of the second node Q2, so that the first output signal terminal Out1 outputs the first The first voltage signal provided by the voltage signal terminal VGH.
  • the first output signal output by the first output signal terminal Out1 is equal to the first voltage signal.
  • the above-mentioned shift register 100 has a simple structure, can accurately control the first output signal terminal Out1 to output the first output signal, and is simple to manufacture and low in production cost.
  • the above-mentioned shift register 100 further includes: a level reduction sub-circuit 6.
  • the level reduction sub-circuit 6 is electrically connected to the second voltage signal terminal VGL and the first output signal terminal Out1.
  • the potential reduction sub-circuit 6 is configured to cooperate with the first output sub-circuit 2 to reduce the level of the first output signal output by the first output signal terminal Out1 during the stage when the first output sub-circuit 2 outputs the second voltage signal. Level.
  • the level reduction sub-circuit 6 can be turned on under the action of the second voltage signal, and the second voltage signal received at the second voltage signal terminal VGL is turned on.
  • the two voltage signals are transmitted to the first output signal terminal Out1, so that the first output signal output by the first output signal terminal Out1 is the second voltage signal output by the first output sub-circuit 2 and the second voltage output by the level reduction sub-circuit 6
  • the signal constitutes the signal together. Since the second voltage signal is a low-level signal, the level of the first output signal can be reduced, and the output capability of the first output signal terminal Out1 can be improved.
  • the structure of the level reduction sub-circuit 6 will be schematically described below.
  • the level reduction sub-circuit 6 includes a seventh transistor T7.
  • the gate of the seventh transistor T7 is electrically connected to the first output signal terminal Out1
  • the second electrode of the seventh transistor T7 is electrically connected to the first output signal terminal Out1
  • the gate of the seventh transistor T7 is electrically connected to the first output signal terminal Out1.
  • the first pole is electrically connected to the second voltage signal terminal VGL.
  • the seventh transistor T7 is configured to turn on under the control of the second voltage signal when the first output sub-circuit 2 outputs the second voltage signal, and to turn on the second voltage signal received at the second voltage signal terminal VGL
  • the voltage signal is transmitted to the first output signal terminal Out1, so that the first output signal terminal Out1 outputs the first output signal.
  • the fourth transistor T4 When the first output sub-circuit 2 is turned on, the fourth transistor T4 can receive and transmit the second voltage signal to the first output signal terminal Out1, and the seventh transistor T7 can be turned on under the control of the second voltage signal, The second voltage signal provided by the second voltage signal terminal VGL is transmitted to the first output signal terminal Out1.
  • the first output signal output by the first output signal terminal Out1 includes the second voltage signal output by the fourth transistor T4 and the second voltage signal output by the seventh transistor T7, so that the output signal from the first output signal terminal Out1 can be reduced.
  • the level of the first output signal improves the output capability of the first output signal terminal Out1.
  • the seventh transistor T7 transmits a second voltage signal with a negative level to the first output signal terminal Out1, the first output signal terminal Out1
  • the level of an output signal is equal to the sum of the levels of the two second voltage signals, so the level of the first output signal is reduced.
  • the above-mentioned shift register 100 further includes: a potential stabilizing sub-circuit 7.
  • the potential stabilizing sub-circuit 7 is electrically connected to the second voltage signal terminal VGL, the second node Q2, and the fourth node Q4.
  • the potential stabilization sub-circuit 7 is configured to transmit the voltage of the second node Q2 to the fourth node Q4 in response to the second voltage signal, and stabilize the voltage of the fourth node Q4.
  • the second output sub-circuit 4 is electrically connected to the fourth node Q4, and is electrically connected to the second node Q2 through the potential stabilizing sub-circuit 7. That is, the second output sub-circuit 4 and the second input sub-circuit 3 are indirectly electrically connected, and the electrical connection is achieved through the potential stabilizing sub-circuit 7.
  • the second voltage signal is a low-level signal
  • the potential stabilization sub-circuit 7 may be turned on under the control of the second voltage signal to transmit the input signal from the second input sub-circuit 3 to the second node Q2 to the first Four-node Q4.
  • the second output sub-circuit 4 may be turned on under the control of the voltage of the fourth node Q4 to output the first output signal.
  • the second input sub-circuit 3 When the second input sub-circuit 3 is turned off, the second input sub-circuit 3 has no signal output, and the second node Q2 is in a floating state.
  • the potential stabilization sub-circuit 7 By setting the potential stabilization sub-circuit 7, the voltage of the second node Q2 can be controlled , And make the voltage of the fourth node Q4 stable.
  • the potential stabilization sub-circuit 7 includes: an eighth transistor T8.
  • the gate of the eighth transistor T8 is electrically connected to the second voltage signal terminal VGL
  • the first electrode of the eighth transistor T8 is electrically connected to the second node Q2
  • the second electrode of the eighth transistor T8 is electrically connected to the second node Q2.
  • the pole is electrically connected to the fourth node Q4.
  • the eighth transistor T8 Since the gate of the eighth transistor T8 is electrically connected to the second voltage signal terminal VGL, and the second voltage signal is a low-level signal, the eighth transistor T8 is in a normally-on state.
  • the third transistor T3 in the second input sub-circuit 3 When the third transistor T3 in the second input sub-circuit 3 is turned on, the third transistor T3 can receive and transmit the input signal to the second node, and the input signal can be transmitted to the fourth node Q4 through the eighth transistor T8, The conduction state of the second output sub-circuit is controlled.
  • the eighth transistor T8 can make the voltage of the second node Q2 controllable and avoid affecting the conduction state of the sixth and transistor T6 in the control sub-circuit 5. Moreover, the eighth transistor T8 can also make the potential of the fourth node Q4 more stable, and ensure the stable working performance of the fifth transistor T5.
  • the shift register 100 further includes: a first inversion sub-circuit 8 and a second inversion sub-circuit 9.
  • the first inversion sub-circuit 8 is electrically connected to the first output signal terminal Out1, the first voltage signal terminal VGH, and the second output signal terminal Out2. Wherein, the first voltage signal terminal VGH is also used to input a first voltage signal to the first inversion sub-circuit 8.
  • the first inversion sub-circuit 8 is configured to, in response to the first output signal received at the first output signal terminal Out1, transmit the first voltage signal received at the first voltage signal terminal VGH to the second output signal terminal Out2.
  • the first inversion sub-circuit 8 may be turned on under the control of the first output signal. , Receiving and transmitting the first voltage signal to the second output signal terminal Out2.
  • the second output signal terminal Out2 outputs the first voltage signal as the second output signal.
  • the second inverting sub-circuit 9 is electrically connected to the first output signal terminal Out1, the second voltage signal terminal VGL, the second clock signal terminal CK2, and the second output signal terminal Out2. connection.
  • the second voltage signal terminal VGL is also used to input a second voltage signal to the second inversion sub-circuit 9.
  • the second clock signal terminal CK2 is used to receive a second clock signal and input the second clock signal into the second inversion sub-circuit 9.
  • the second inversion sub-circuit 9 is configured to, in response to the first output signal received at the first output signal terminal Out1 and the second clock signal received at the second clock signal terminal CK2, set the signal at the second voltage signal terminal The second voltage signal received at the VGL is transmitted to the second output signal terminal Out2.
  • the second inversion sub-circuit 9 may be turned on under the action of the first voltage signal and the second clock signal, and receive and transmit the second voltage signal to the second output signal terminal Out2.
  • the second output signal terminal Out2 outputs the second voltage signal as the second output signal.
  • the first inversion sub-circuit 8 and the second inversion sub-circuit 9 can be turned on in different periods. In this way, when the first inverting sub-circuit 8 outputs the second output signal, the second output signal only includes the first voltage signal; in the second inverting sub-circuit 9 outputting the second output signal, the second output signal is made The output signal only includes the second voltage signal, which helps to ensure the accuracy and stability of the second output signal.
  • each stage of shift register 100 may include a first inversion sub-circuit 8 And the second inverting sub-circuit 9 to convert the first output signal into a second output signal.
  • the second output signal terminal Out2 of the shift register 100 of this stage can be electrically connected to the input signal terminal Input of the next stage shift register 100. Connected, the second output signal output by the second output signal terminal Out2 of the shift register 100 of this stage is used as the input signal of the shift register 100 of the next stage, so as to realize the cascade connection of multiple shift registers 100 and complete the display Progressive scanning of the sub-pixels P of the panel PNL.
  • first inverting sub-circuit 8 and the second inverting sub-circuit 9 are schematically described below.
  • the first inversion sub-circuit 8 includes: a ninth transistor T9.
  • the gate of the ninth transistor T9 is electrically connected to the first output signal terminal Out1
  • the first electrode of the ninth transistor T9 is electrically connected to the first voltage signal terminal VGH
  • the gate of the ninth transistor T9 is electrically connected to the first voltage signal terminal VGH.
  • the second pole is electrically connected to the second output signal terminal Out2.
  • the ninth transistor T9 is configured to transmit the first voltage signal to the second output signal terminal Out2 under the control of the first output signal.
  • the ninth transistor T9 can be turned on under the action of the first output signal to receive and transmit the first voltage signal to the second output signal terminal Out2,
  • the second output signal terminal Out2 outputs the first voltage signal as the second output signal.
  • the low-level first output signal is, for example, the second voltage signal output by the first output sub-circuit 2.
  • the second inversion sub-circuit 9 includes: a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, and a fourth capacitor C4.
  • the gate of the tenth transistor T10 is electrically connected to the first output signal terminal Out1
  • the first electrode of the tenth transistor T10 is electrically connected to the first voltage signal terminal VGH
  • the gate of the tenth transistor T10 is electrically connected to the first voltage signal terminal VGH.
  • the second pole is electrically connected to the fifth node Q5.
  • the tenth transistor T10 is configured to transmit the first voltage signal to the fifth node Q5 under the control of the first output signal.
  • the tenth transistor T10 may be turned on under the action of the first output signal to receive and transmit the first voltage signal to the fifth node Q5, so that the The voltage of the five node Q5 rises.
  • the gate of the eleventh transistor T11 is electrically connected to the second clock signal terminal CK2
  • the first electrode of the eleventh transistor T11 is electrically connected to the second voltage signal terminal VGL
  • the eleventh transistor T11 is electrically connected to the second voltage signal terminal VGL.
  • the second electrode of the transistor T11 is electrically connected to the fifth node Q5.
  • the eleventh transistor T11 is configured to transmit the second voltage signal to the fifth node Q5 under the control of the second clock signal.
  • the eleventh transistor T11 can be turned on under the action of the second clock signal to receive and transmit the second voltage signal to the fifth node Q5, so that The voltage of the fifth node Q5 decreases.
  • the gate of the twelfth transistor T12 is electrically connected to the fifth node Q5, the first electrode of the twelfth transistor T12 is electrically connected to the second voltage signal terminal VGL, and the twelfth transistor T12 is electrically connected to the second voltage signal terminal VGL.
  • the second pole of is electrically connected to the second output signal terminal Out2.
  • the twelfth transistor T12 is configured to transmit the second voltage signal received at the second voltage signal terminal VGL to the second output signal terminal Out2 under the control of the voltage of the fifth node Q5.
  • the twelfth transistor T12 may be turned on under the control of the voltage of the fifth node Q5 to receive and transmit the second voltage signal to the second output signal terminal Out2 enables the second output signal terminal Out2 to output the second voltage signal as the second output signal.
  • the first end of the fourth capacitor C4 is electrically connected to the fifth node Q5, and the second end of the fourth capacitor C4 is electrically connected to the second output signal point Out2.
  • the fourth capacitor C4 is configured to maintain the potential of the fifth node Q5.
  • the fourth capacitor C4 is also charged. In this way, when the tenth transistor T10 is turned off, the fourth capacitor C4 can also be discharged, so that the potential of the fifth node Q5 is maintained at a high level.
  • the fourth capacitor C4 is also charged. In this way, when the tenth transistor T10 is turned off, the fourth capacitor C4 can also be discharged, so that the potential of the fifth node Q5 is maintained at a low level.
  • the level of the first output signal output by the first output signal terminal Out1 is low, and the ninth transistor T9 in the first inversion sub-circuit 8 can be in the first
  • the output signal is turned on under the control of the output signal, and the first voltage signal received at the first voltage signal terminal VGH is transmitted to the second output signal terminal Out2, so that the second output signal output by the second output signal terminal Out2 is equal to the first voltage signal .
  • the level of the first output signal output by the first output signal terminal Out1 is low.
  • the tenth transistor T10 can be turned on under the control of the first output signal, and will be at the first voltage.
  • the first voltage signal received at the signal terminal VGH is transmitted to the fifth node Q5, so that the voltage of the fifth node Q5 rises.
  • the twelfth transistor T12 can be turned off under the control of the voltage of the fifth node Q5.
  • the level of the second clock signal is high, and the eleventh transistor T11 can be turned off under the control of the second clock signal.
  • the second inverting sub-circuit 9 has no signal output.
  • the second output signal output by the second output signal terminal Out2 is equal to the first voltage signal.
  • the level of the first output signal output by the first output signal terminal Out1 is still at a low level, and the level of the second clock signal is still at a high level.
  • the working processes of the first inverting sub-circuit 8 and the second inverting sub-circuit 9 are the same as those in the S2 stage. For details, please refer to the description in the S2 stage, which will not be repeated here.
  • the second output signal output by the second output signal terminal Out2 is equal to the first voltage signal.
  • the ninth transistor T9 can be turned off under the control of the first output signal, and the first inversion sub-circuit 8 has no signal Output.
  • the tenth transistor T10 can also be turned off under the control of the first output signal.
  • the level of the second clock signal becomes a low level, and the eleventh transistor T11 can be turned on under the control of the second clock signal to transmit the second voltage signal received at the second voltage signal terminal VGL to the fifth node Q5 reduces the voltage of the fifth node Q5.
  • the twelfth transistor T12 may be turned on under the control of the voltage of the fifth node Q5, and transmit the second voltage signal received at the second voltage signal terminal VGL to the second output signal terminal Out2.
  • the second output signal output by the second output signal terminal Out2 is equal to the second voltage signal.
  • the level of the first output signal output by the first output signal terminal Out1 is still high, and the level of the second clock signal is still low.
  • the working process of the first inverting sub-circuit 8 and the second inverting sub-circuit 9 is the same as that of the S4 stage. For details, please refer to the description in the S4 stage, which will not be repeated here.
  • the second output signal output by the second output signal terminal Out2 is equal to the second voltage signal.
  • the level of the first output signal output by the first output signal terminal Out1 is still high, and the level of the second clock signal is still low.
  • the working process of the first inverting sub-circuit 8 and the second inverting sub-circuit 9 is the same as that of the S4 stage. For details, please refer to the description in the S4 stage, which will not be repeated here.
  • the second output signal output by the second output signal terminal Out2 is equal to the second voltage signal.
  • Some embodiments of the present disclosure also provide a gate driving circuit 1000, as shown in FIGS. 23-25.
  • the gate driving circuit 1000 includes a plurality of cascaded shift registers 100 as described above.
  • A1, A2, A3, and A4 shown in FIGS. 23 to 25 represent the shift register 100, respectively.
  • Each shift register 100 may be electrically connected to a corresponding row of sub-pixels P in the display panel PNL, and provide a required scan signal to the corresponding row of sub-pixels P to realize progressive scanning.
  • the above-mentioned gate driving circuit 1000 may have a variety of structures, which can be selected and set according to actual needs.
  • each shift register 100 includes a first input word circuit 1, a first output sub-circuit 2, a second input sub-circuit 3, and a second output sub-circuit 4.
  • first input word circuit 1 a first output sub-circuit 2
  • second input sub-circuit 3 a second output sub-circuit 4.
  • FIG. 23 taking the structure diagram of the gate driving circuit 1000 shown in FIG. 23 as an example, the signal lines in the gate driving circuit 1000 are schematically illustrated.
  • the gate driving circuit 1000 includes: a first sub-clock signal line CK_1, a second sub-clock signal line CK_2, and a third sub-clock signal line CK_3.
  • the input signal terminal Input of the first stage shift register 100 can be electrically connected to the first sub-clock signal line CK_1 to receive the start signal as an input signal (at this time, the input signal terminal Input passes the start signal
  • the terminal Init is electrically connected to the first sub-clock signal line CK_1).
  • the input signal terminal Input of the shift register 100 of the remaining stage may be electrically connected (for example, indirectly electrically connected) to the first output signal terminal Out1 of the shift register 100 of the previous stage, for example.
  • the first output signal may be inverted, for example, to reverse the inverted output signal.
  • the first output signal is used as the input signal of the shift register 100 of this stage.
  • the first clock signal terminal CK1 of the 2N-1 stage shift register 100 may be electrically connected to the second sub-clock signal line CK_2 to receive the first clock signal.
  • N is a positive integer. That is, the shift register 100 of the odd-numbered stage may be electrically connected to the same second sub-clock signal line CK_2 to receive the first clock signal.
  • the first clock signal terminal CK1 of the 2N-stage shift register 100 may be electrically connected to the third sub-clock signal line CK_3 to receive the first clock signal. That is, the shift register 100 of the even-numbered stage may be electrically connected to the same third sub-clock signal line CK_3 to receive the first clock signal.
  • the waveform of the first clock signal transmitted by the second sub-clock signal line CK_2 may be as shown in FIG. 22.
  • the phase of the first clock signal transmitted by the third sub-clock signal line CK_3 is different from the phase of the first clock signal transmitted by the second sub-clock signal line CK_2 by 1H (for example, 1H).
  • the gate driving circuit 1000 may further include: a first direct current voltage signal line and a second direct current voltage signal line.
  • the first voltage signal terminal VGH of the shift register 100 at each level may be electrically connected to the first DC voltage signal line to receive the first voltage signal.
  • the second voltage signal terminal VGL of each level of the shift register 100 may be electrically connected to the second DC voltage signal line to receive the second voltage signal.
  • each shift register 100 includes a first input word circuit 1, a first output sub-circuit 2, a second input sub-circuit 3, a second output sub-circuit 4, a first inversion sub-circuit 8 and a second Anti-rotor circuit 9.
  • FIG. 25 taking the structure diagram of the gate driving circuit 1000 shown in FIG. 25 as an example, the signal lines in the gate driving circuit 1000 are schematically illustrated.
  • the gate driving circuit 1000 includes: a first sub-clock signal line CK_1, a second sub-clock signal line CK_2, a third sub-clock signal line CK_3, a fourth sub-clock signal line CK_4, and a fifth sub-clock signal Line CK_5.
  • the input signal terminal Input of the first stage shift register 100 may be electrically connected to the first sub-clock signal line CK_1 to receive the start signal as an input signal.
  • the input signal terminal Input is electrically connected to the first sub-clock signal line CK_1 through the start signal terminal Init, and the start signal terminal Init can transmit the start signal.
  • the input signal terminal Input of the other stage shift registers 100 is electrically connected to the second output signal terminal Out2 of the previous stage shift register 100, and the second stage of the previous stage shift register 100 The second output signal output by the output signal terminal Out2 is used as the input signal of the shift register 100 of this stage.
  • the second output signal terminal Out2 may be set, or the second output signal terminal Out2 may not be set, and the second output signal terminal Out2 is set in the shift register 100 of the last stage Next, the second output signal terminal Out2 can be left empty.
  • the first clock signal terminal CK1 of the 2N-1 stage shift register may be electrically connected to the second sub-clock signal line CK_2 to receive the first clock signal.
  • the second clock signal terminal CK2 of the 2N-1 stage shift register may be electrically connected to the fourth sub-clock signal line CK_4 to receive the second clock signal. That is, the shift register 100 of the odd-numbered stage may be electrically connected to the same fourth sub-clock signal line CK_4 to receive the second clock signal.
  • the first clock signal terminal CK1 of the 2N-stage shift register may be electrically connected to the third sub-clock signal line CK_3 to receive the first clock signal.
  • the second clock signal terminal CK2 of the 2N-1 stage shift register may be electrically connected to the fifth sub-clock signal line CK_5 to receive the second clock signal. That is, the even-numbered shift register 100 may be electrically connected to the same fifth sub-clock signal line CK_5 to receive the second clock signal.
  • the waveform of the second clock signal transmitted by the fourth sub-clock signal line CK_4 may be as shown in FIG. 22.
  • the phase of the second clock signal transmitted by the fifth sub-clock signal line CK_5 is different by 2H (for example, 2H afterwards) compared to the phase of the second clock signal transmitted by the fourth sub-clock signal line CK_4.
  • the gate driving circuit 1000 may further include: a first direct current voltage signal line and a second direct current voltage signal line.
  • the first voltage signal terminal VGH of the shift register 100 at each level may be electrically connected to the first DC voltage signal line to receive the first voltage signal.
  • the second voltage signal terminal VGL of each level of the shift register 100 may be electrically connected to the second DC voltage signal line to receive the second voltage signal.
  • the above examples are only two examples of signal lines included in the gate driving circuit 100.
  • the type and number of signal lines included in the gate drive circuit 1000 are not limited to the above two examples, and the electrical connection between each signal line in the gate drive circuit 1000 and each shift register 100 is not limited to the above two examples.
  • the gate driving circuit 1000 provided by some embodiments of the present disclosure has the same beneficial effects as the above-mentioned shift register 100, so it will not be repeated.
  • Some embodiments of the present disclosure also provide a driving method of the shift register.
  • the following takes the first-stage shift register 100 in the gate driving circuit 1000 shown in FIG. 23 (which is formed by cascading the shift registers 100 shown in FIG. 6 or FIG. 8) as an example, and combined with FIG. 22
  • the timing diagram of the present disclosure schematically illustrates the driving method of the shift register 100 in an image frame.
  • the driving method of the first-stage shift register 100 in an image frame includes:
  • the first stage also called the first output stage:
  • the first output sub-circuit 2 under the control of the voltage of the first node Q1, the first output sub-circuit 2 is turned on, and the second voltage signal received at the second voltage signal terminal VGL is transmitted to the first output signal terminal Out1.
  • the first output signal terminal Out1 outputs the second voltage signal as a first output signal.
  • the second output sub-circuit 4 Under the control of the voltage of the second node Q2, the second output sub-circuit 4 is turned off, and no signal is output.
  • the first output stage includes S2 stage and S3 stage.
  • the working process of each transistor and capacitor in the shift register 100 can be referred to the description of the S2 stage and the S3 stage in some of the above examples, which will not be repeated here.
  • the second stage also called the second output stage:
  • the first output sub-circuit 2 under the control of the voltage of the first node Q1, the first output sub-circuit 2 is turned off. Under the control of the voltage of the second node Q2, the second output sub-circuit 4 is turned on, and transmits the first voltage signal received at the first voltage signal terminal VGH to the first output signal terminal Out1, and the first output signal terminal Out1 connects The first voltage signal is output as the first output signal.
  • the first output stage includes S4 stage, S5 stage and S1 stage.
  • the working process of the transistors and capacitors in the shift register 100 can be referred to the descriptions of the S4 stage, S5 stage and S1 stage in some of the above examples, which will not be repeated here.
  • connection relationship between the shift registers 100 in the gate driving circuit 1000 and the pixel driving circuit 200 in the sub-pixel P can be selected and set according to actual needs. .
  • the aforementioned sub-pixels P may be arranged in multiple rows along the first direction X.
  • a row of sub-pixels P includes at least two sub-pixels P.
  • the pixel driving circuits 200 included in the sub-pixel P may be arranged in multiple rows along the first direction X, and a row of pixel driving circuits 200 may include at least two pixel driving circuits 200.
  • P1, P2, P3, and P4 may represent the first row of subpixels P, the second row of subpixels P, the second row of subpixels P, and the second row of subpixels P, respectively.
  • the first-stage shift register 100 in the gate driving circuit 1000 may be electrically connected to a row of sub-pixels P, that is, the first-stage shift register 100 in the gate driving circuit 1000
  • the shift register 100 may be electrically connected to the pixel driving circuit 200 in a row of sub-pixels P.
  • the connection relationship may be: the input signal terminal Input of a shift register 100 may be electrically connected to the first scan signal terminal Gate1 of a row of pixel driving circuit 200, and the first output signal terminal Out1 of the shift register 100 may be connected to the row of pixels.
  • the second scanning signal terminal Gate2 of the driving circuit 200 is electrically connected.
  • one shift register 100 may be electrically connected to a row of pixel driving circuits 200 through two gate lines GL.
  • the input signal terminal Input of the shift register 100 may be electrically connected to the first scanning signal terminal Gate1 of the corresponding row of pixel driving circuit 200 through a gate line GL, and the input signal terminal Input not only transmits the input signal to the shift register 100 ,
  • the input signal is also transmitted to the first scanning signal terminal Gate1 of the corresponding row of pixel driving circuit 200 as the first scanning signal to drive the corresponding row of pixel driving circuit 200.
  • the first output signal terminal Out1 of the shift register 100 may be electrically connected to the second scan signal terminal Gate2 of the corresponding row of pixel driving circuit 200 through another gate line GL, and the first output signal output by the first output signal terminal Out1 As the second scan signal of the corresponding row of pixel driving circuit 200, the corresponding row of pixel driving circuit 200 is driven.

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Abstract

一种移位寄存器（100），包括：第一输入子电路（1），被配置为，响应于输入信号和第一电压信号，将第一时钟信号传输至第一节点；第一输出子电路（2），被配置为，在第一节点的电压的控制下，将第二电压信号传输至第一输出信号端，以使第一输出信号端输出第一输出信号；第二输入子电路（3），被配置为，响应于第一时钟信号，将输入信号传输至第二节点；以及，第二输出子电路（4），被配置为，在第二节点的电压的控制下，将第一电压信号传输至第一输出信号端，以使第一输出信号端输出第一输出信号；其中，第一电压信号和第二电压信号中的一者的电压值大于参考电压，另一者的电压值小于参考电压。

Description

移位寄存器及其驱动方法、栅极驱动电路、显示装置
本申请要求于2020年01月02日提交的、申请号为202020004881.5的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器及其驱动方法、栅极驱动电路、显示装置。
背景技术
栅极驱动电路是一种用于向显示装置中的多条栅极信号线(或称为栅线)逐行输入扫描驱动信号(或称栅信号)的一种电路。将栅极驱动电路集成在显示装置中的显示面板上，可以降低显示面板的生产成本和制作工艺的难度。
发明内容
一方面，提供一种移位寄存器。所述移位寄存器包括：第一输入子电路，与输入信号端、第一电压信号端、第一时钟信号端及第一节点电连接；所述第一输入子电路被配置为，响应于在所述输入信号端处接收的输入信号和在所述第一电压信号端处接收的第一电压信号，将在所述第一时钟信号端处接收的第一时钟信号传输至所述第一节点；第一输出子电路，与所述第一节点、第二电压信号端及第一输出信号端电连接；所述第一输出子电路被配置为，在所述第一节点的电压的控制下，将在所述第二电压信号端处接收的第二电压信号传输至所述第一输出信号端，以使所述第一输出信号端输出第一输出信号；第二输入子电路，与所述输入信号端、所述第一时钟信号端及第二节点电连接；所述第二输入子电路被配置为，响应于所述第一时钟信号，将在所述输入信号端处接收的输入信号传输至所述第二节点；以及，第二输出子电路，与所述第二节点、所述第一电压信号端及所述第一输出信号端电连接；所述第二输出子电路被配置为，在所述第二节点的电压的控制下，将在所述第一电压信号端处接收的第一电压信号传输至所述第一输出信号端，以使所述第一输出信号端输出第一输出信号；其中，所述第一电压信号和所述第二电压信号中的一者的电压值大于参考电压，另一者的电压值小于所述参考电压。
在一些实施例中，所述第一输入子电路包括：第一晶体管、第二晶体管和第一电容器。所述第一晶体管的栅极与所述输入信号端电连接，所述第一晶体管的第一极与所述第一电压信号端电连接，所述第一晶体管的第二极与第三节点电连接。所述第二晶体管的栅极与所述第三节点电连接，所述第二晶体管的第一极与所述第一时钟信号端电连接，所述第二晶体管的第二极与所述第一节点电连接。所述第一电容器的第一端与所述第一时钟信号端电连接，所述第一电容器的第二端与所述第三节点电连接。所述第二输入子电路包括：第三晶体管。所述第三晶体管的栅极与所述第一时钟信号端电连接，所述第三晶体管的第一极与所述输入信号端电连接，所述第三晶体管的第二极与所述第二节点电连接。
在一些实施例中，所述第一输出子电路包括：第四晶体管和第二电容器。所述第四晶体管的栅极与所述第一节点电连接，所述第四晶体管的第一极与所述第二电压信号端电连接，所述第四晶体管的第二极与所述第一输出信号端电连接。所述第二电容器的第一端与所述第一节点电连接，所述第二电容器的第二端与所述第二电压信号端电连接。所述第二输出子电路包括：第五晶体管和第三电容器。所述第五晶体管的栅极与所述第二节点电连接，所述第五晶体管的第一极与所述第一电压信号端电连接，所述第五晶体管的第二极与 所述第一输出信号端电连接。所述第三电容器的第一端与所述第二节点电连接，所述第三电容器的第二端与所述第一输出信号端电连接。
在一些实施例中，所述移位寄存器，还包括：控制子电路。所述控制子电路与所述第一电压信号端、所述第二节点及所述第一节点电连接；所述控制子电路被配置为，在所述第二节点的电压的控制下，将在所述第一电压信号端处接收的第一电压信号传输至所述第一节点，以在所述第二输出子电路输出第一输出信号的阶段，控制所述第一输出子电路关断。
在一些实施例中，所述控制子电路包括：第六晶体管。所述第六晶体管的栅极与所述第二节点电连接，所述第六晶体管的第一极与所述第一电压信号端电连接，所述第六晶体管的第二极与所述第一节点电连接。
在一些实施例中，所述移位寄存器，还包括：电平降低子电路。所述电平降低子电路与所述第二电压信号端及所述第一输出信号端电连接；所述电位降低子电路被配置为，在所述第一输出子电路输出第二电压的阶段，与所述第一输出子电路相配合，降低所述第一输出信号端输出的第一输出信号的电平。
在一些实施例中，所述电平降低子电路包括：第七晶体管。所述第七晶体管的栅极与所述第一输出信号端电连接，所述第七晶体管的第一极与所述第二电压信号端电连接，所述第七晶体管的第二极与所述第一输出信号端电连接。
在一些实施例中，所述移位寄存器，还包括：电位稳定子电路。所述电位稳定子电路与所述第二电压信号端、所述第二节点及第四节点电连接；所述电位稳定子电路被配置为，响应于所述第二电压信号，将所述第二节点的电压传输至所述第四节点，并稳定所述第四节点的电压。其中，所述第二输出子电路与所述第四节点电连接，并通过所述电位稳定子电路与所述第二节点电连接。
在一些实施例中，所述电位稳定子电路包括：第八晶体管。所述第八晶体管的栅极与所述第二电压信号端电连接，所述第八晶体管的第一极与所述第二节点电连接，所述第八晶体管的第二极与所述第四节点电连接。在所述第二输出子电路包括第五晶体管和第三电容器的情况下，所述第五晶体管的栅极与所述第四节点电连接，并通过所述第七晶体管与所述第二节点电连接；所述第三电容器的第一端与所述第四节点电连接，并通过所述第七晶体管与所述第二节点电连接。
在一些实施例中，所述移位寄存器，还包括：第一反转子电路，与所述第一输出信号端、所述第一电压信号端及第二输出信号端电连接；所述第一反转子电路被配置为，响应于在所述第一输出信号端处接收的第一输出信号，将在所述第一电压信号端处接收的第一电压信号传输至所述第二输出信号端；以及，第二反转子电路，与所述第一输出信号端、所述第一电压信号端、所述第二电压信号端、第二时钟信号端及所述第二输出信号端电连接；所述第二反转子电路被配置为，响应于在所述第一输出信号端处接收的第一输出信号、在所述第二时钟信号端处接收的第二时钟信号，将在所述第二电压信号端处接收的第二电压信号传输至所述第二输出信号端。
在一些实施例中，所述第一反转子电路包括：第九晶体管。所述第九晶体管的栅极与所述第一输出信号端电连接，所述第九晶体管的第一极与所述第一电压信号端电连接，所述第九晶体管的第二极与所述第二输出信号端电连接。所述第二反转子电路包括：第十晶体管、第十一晶体管、第十二晶体管和第四电容器。所述第十晶体管的栅极与所述第一输 出信号端电连接，所述第十晶体管的第一极与所述第一电压信号端电连接，所述第十晶体管的第二极与所述第五节点电连接。所述第十一晶体管的栅极与所述第二时钟信号端电连接，所述第十一晶体管的第一极与所述第二电压信号端电连接，所述第十一晶体管的第二极与所述第五节点电连接。所述第十二晶体管的栅极与所述第五节点电连接，所述第十二晶体管的第一极与所述第二电压信号端电连接，所述第十二晶体管的第二极与所述第二输出信号端电连接。所述第四电容器的第一端与所述第五节点电连接，所述第四电容器的第二端与所述第二输出信号端电连接。
另一方面，提供一种如上述任一实施例所述的移位寄存器的驱动方法，包括：在第一输出阶段，在第一节点的电压的控制下，第一输出子电路开启，将在第二电压信号端处接收的第二电压信号传输至第一输出信号端，所述第一输出信号端将所述第二电压信号作为第一输出信号输出；在第二节点的电压的控制下，第二输出子电路关断；在第二输出阶段，在所述第一节点的电压的控制下，所述第一输出子电路关断；在所述第二节点的电压的控制下，所述第二输出子电路开启，将在第一电压信号端处接收的第一电压信号传输至第一输出信号端，所述第一输出信号端将所述第一电压信号作为第一输出信号输出。
又一方面，提供一种栅极驱动电路。所述栅极驱动电路，包括：多个级联的如上述任一实施例所述的移位寄存器。
又一方面，提供一种显示装置。所述显示装置包括：如上述任一实施例所述的栅极驱动电路。
在一些实施例中，所述显示装置，还包括：多个像素驱动电路。所述多个像素驱动电路沿第一方向排列为多行，一行像素驱动电路包括至少两个像素驱动电路。所述栅极驱动电路中，一个移位寄存器的输入信号端与一行像素驱动电路的第一扫描信号端电连接，所述移位寄存器的第一输出信号端与所述一行像素驱动电路的第二扫描信号端电连接。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据本公开一些实施例中的一种显示装置的结构图；
图2为根据本公开一些实施例中的一种显示面板的结构图；
图3为根据本公开一些实施例中的一种像素驱动电路的结构图；
图4为根据本公开一些实施例中的一种像素驱动电路的时序图；
图5为根据本公开一些实施例中的一种移位寄存器的结构图；
图6为根据本公开一些实施例中的一种移位寄存器的电路图；
图7为根据本公开一些实施例中的另一种移位寄存器的结构图；
图8为根据本公开一些实施例中的另一种移位寄存器的电路图；
图9为根据本公开一些实施例中的又一种移位寄存器的结构图；
图10为根据本公开一些实施例中的又一种移位寄存器的电路图；
图11为根据本公开一些实施例中的又一种移位寄存器的结构图；
图12为根据本公开一些实施例中的又一种移位寄存器的电路图；
图13为根据本公开一些实施例中的又一种移位寄存器的结构图；
图14为根据本公开一些实施例中的又一种移位寄存器的电路图；
图15为根据本公开一些实施例中的又一种移位寄存器的结构图；
图16为根据本公开一些实施例中的又一种移位寄存器的电路图；
图17为根据本公开一些实施例中的又一种移位寄存器的结构图；
图18为根据本公开一些实施例中的又一种移位寄存器的电路图；
图19为根据本公开一些实施例中的又一种移位寄存器的电路图；
图20为根据本公开一些实施例中的又一种移位寄存器的电路图；
图21为根据本公开一些实施例中的又一种移位寄存器的电路图；
图22为根据本公开一些实施例中的一种移位寄存器的时序图；
图23为根据本公开一些实施例中的一种栅极驱动电路的结构图；
图24为根据本公开一些实施例中的另一种栅极驱动电路的结构图；
图25为根据本公开一些实施例中的又一种栅极驱动电路的结构图；
图26为根据本公开一些实施例中的一种栅极驱动电路与亚像素电连接的结构图；
图27为根据本公开一些实施例中的另一种栅极驱动电路与亚像素电连接的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。这里所公开的实施例并不必然限制于本文内容。
在描述一些实施例时，“A和B电连接”，可以表示为A和B之间直接电连接，也可以表示为A和B之间设置有C，A和B通过C间接电连接。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时” 或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本公开的实施例提供的电路中所采用的晶体管可以为薄膜晶体管、场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。
在一些实施例中，移位寄存器所采用的各晶体管的控制极为晶体管的栅极，第一极为晶体管的源极和漏极中一者，第二极为晶体管的源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性的，在晶体管为P型晶体管的情况下，晶体管的第一极为源极，第二极为漏极；示例性的，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
在本公开的实施例提供的电路中，“节点”并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点，也就是说，这些节点是由电路图中相关电连接的汇合点等效而成的节点。
本公开的一些实施例提供了一种移位寄存器100及其驱动方法、栅极驱动电路1000、显示装置2000，以下对移位寄存器100、移位寄存器100的驱动方法、栅极驱动电路1000及显示装置2000分别进行介绍。
本公开的一些实施例提供了一种显示装置2000，如图1所示。该显示装置可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
在一些示例中，上述显示装置2000包括显示面板PNL。当然，该显示装置2000还可以包括框架、电路板、显示驱动IC(Integrated Circuit，集成电路)以及其他电子配件等。其中，显示面板PNL可以设置在框架内。
上述显示装置2000例如可以为：有机发光二极管(Organic Light Emitting Diode，简称OLED)显示装置、量子点发光二极管(Quantum Dot Light Emitting Diodes，简称QLED)显示装置、微型发光二极管(Micro Light Emitting Diode，简称Micro LED)显示装置或者次毫米发光二极管(Mini Light Emitting Diode，简称Mini LED)显示装置等，本公开对此不做具体限定。其中，上述显示装置2000因具有体积小、功耗低、显示效果好、无辐射以及制作成本相对较低等特点，而越来越多地被应用于高性能显示领域当中。
下面以上述显示装置2000为OLED显示装置为例，对本公开的一些实施例进行示意性说明。基于此，显示装置2000所包括的显示面板PNL则为OLED显示面板。
在一些实施例中，如图2所示，上述显示面板PNL具有显示区A，以及设置在显示区A旁侧的边框区B。其中，“旁侧”指的是显示区A的一侧、两侧、三侧或者周侧等，也即，边框区B可以位于显示区A的一侧、两侧或三侧，或者，边框区B可以围绕显示区A设置。
在一些示例中，如图2所示，该显示面板PNL可以包括：多个亚像素P，沿第一方向X延伸的多条栅线GL以及沿第二方向Y延伸的多条数据线DL。
如图2所示，在显示面板2中，上述多个亚像素P可以呈阵列分布。
示例性的，可以将沿第一方向X排列成一排的亚像素P称为同一行亚像素P，将沿第二方向Y排列成一排的亚像素P称为同一列亚像素P。同一行亚像素P可以与至少一条栅线GL电连接，同一列亚像素P可以与一条数据线DL电连接。其中，与同一行亚像素P电连接的栅线GL的数量，可以根据亚像素P的结构设置。
在一些示例中，如图2所示，上述栅极驱动电路1000可以设置在边框区B内，并位于多条栅线GL的延伸方向的一侧。栅极驱动电路1000可以与上述多条栅线GL电连接，并向该多条栅线GL输入输出信号，以驱动上述多个亚像素P进行图像显示。当然，栅极驱动电路1000也可以设置在显示区A内。
示例性的，上述栅极驱动电路1000可以为栅极驱动IC。
示例性的，上述栅极驱动电路1000还可以为GOA(Gate Driver on Array)电路，也即将上述栅极驱动电路1000直接集成在显示面板PNL的阵列基板中。其中，将栅极驱动电路1000设置为GOA电路相比于设置为栅极驱动IC而言，一方面，可以降低显示面板PNL的制作成本；另一方面，还可以减小显示面板PNL的边框尺寸，实现窄边框设计。
如图2所示，以下实施例均是以栅极驱动电路1000为GOA电路为例进行说明。
在一些示例中，亚像素P的结构包括多种，可以根据实际需要选择设置。
示例性的，如图2和图3所示，每个亚像素P例如可以包括像素驱动电路200以及与该像素驱动电路200电连接的待驱动元件300。其中，待驱动元件300可以为电流驱动型的发光器件，
进一步地，待驱动元件300可以为电流型发光二极管，例如，该电流型发光二 极管可以为微型发光二极管、次毫米发光二极管、有机电致发光二极管或量子点发光二极管等。
在一种实现方式中，上述像素驱动电路200的结构可以为7T1C的结构。其中，“T”表示为晶体管，“C”表示为存储电容器，“T”前面的数字表示为晶体管的数量，“C”前面的数字表示为存储电容器的数量。
随着显示装置的分辨率的提高，显示装置中显示面板的亚像素所占据的面积会被压缩。由于7T1C结构的像素驱动电路所包括的器件结构(也即晶体管和存储电容器)的数量较多，会难以减小该像素驱动电路所占据的面积，进而导致显示装置的分辨率难以提高。
基于此，如图3所示，本公开的一些实施例提出了一种像素驱动电路200。该像素驱动电路200与7T1C结构的像素驱动电路的结构不同。
在一些示例中，如图3所示，本公开所提供的像素驱动电路200的结构可以为6T1C的结构。该像素驱动电路200可以包括：第一像素晶体管(也可称为驱动晶体管)M1、第二像素晶体管(也可称为开关晶体管)M2、第三像素晶体管M3、第四像素晶体管M4、第五像素晶体管M5、第六像素晶体管M6和存储电容器Cst。
示例性的，如图3所示，驱动晶体管M1的栅极与节点N电连接，驱动晶体管M1的第一极与第五像素晶体管M5的第二极电连接，驱动晶体管M1的第二极与第三像素晶体管M3的第一极以及第六像素晶体管M6的第一极电连接。第二像素晶体管M2的栅极与第二扫描信号端Gate2电连接，第二像素晶体管M2的第一极与数据信号端Data电连接，第二像素晶体管M2的第二极与驱动晶体管M1的第一极电连接。第三像素晶体管M3的栅极与第一扫描信号端Gate1电连接，第三像素晶体管M3的第二极与节点N点连接。第四像素晶体管M4的栅极与第一扫描信号端Gate1电连接，第四像素晶体管M4的第一极与复位信号端Vinit电连接，第四像素晶体管M4的第二极与待驱动元件300的阳极电连接。第五像素晶体管M5的栅极与第一使能信号端EM1电连接，第五像素晶体管M5的第一极与电源电压信号端VDD电连接。第六像素晶体管M6的栅极与第二使能信号端EM2电连接，第六像素晶体管M6的第二极与待驱动元件300的阳极电连接。存储电容器Cst的一端与电源电压信号端VDD电连接，另一端与节点N电连接。
上述多个晶体管的类型可以相同，也可以不同，具体可以根据实际需要选择设置。
示例性的，上述多个晶体管的类型不同。例如，第三像素晶体管M3和第四像素晶体管M4可以为N型晶体管，驱动晶体管M1、第二像素晶体管M2、四五像素晶体管M5和晶体管M6可以为P型晶体管。
由于本公开所提供的像素驱动电路200的结构相比于上述7T1C结构的像素驱动电路更为简单，所包括的器件结构的数量更少，因此，本公开所提供的6T1C结构的像素驱动电路200的尺寸相比于7T1C结构的像素驱动电路可以更小，相应的，与6T1C结构的像素驱动电路200对应的亚像素P的尺寸也可以更小，这样可以有效提高显示面板PNL的分辨率。
由于本公开所提供的像素驱动电路200的结构不同于7T1C的结构，这样会使得本公开所提供的像素驱动电路200所需的工作时序与7T1C结构的像素驱动电路 所需的工作时序不同，进而使得与本公开所提供的像素驱动电路200所匹配的移位寄存器100以及与7T1C结构的像素驱动电路所匹配的移位寄存器的结构不同。
经本公开的发明人研究，适用于本公开所提供的像素驱动电路200的工作时序可以如图4所示。
下面结合图3和图4，对本公开所提供的像素驱动电路200的工作过程进行示意性说明。
在S1阶段，第一扫描信号端Gata1提供的第一扫描信号的电平为高电平，第三像素晶体管M3和第四像素晶体管M4可以在该第一扫描信号的控制下开启。其中，第四像素晶体管M4可以将在复位信号端Vinit处接收的复位信号传输至待驱动元件300的阳极，对待驱动元件300的阳极进行复位。
此外，第二使能信号端EM2提供的第二使能信号的电平为低电平，第六像素晶体管M6可以在第二使能信号的控制下开启，接收并传输复位信号至第六像素晶体管M6的第一极。第三像素晶体管M3可以接收并传输复位信号至节点N。
在S2阶段，第一扫描信号的电平仍为高电平，第三像素晶体管M3保持开启状态。第二使能信号的电平变为低电平，第六像素晶体管M6在该第二使能信号的控制下关闭。
第二扫描信号端Gata2提供的第二扫描信号的电平为低电平，第二像素晶体管M2可以在该第二扫描信号的控制下开启，将在数据信号端Data处接收的数据信号传输至第二像素晶体管M2的第二极。
节点N的电压在复位信号的作用下变为低电平。驱动晶体管M1可以在节点N的控制下导通，从第二像素晶体管M2的第二极接收数据信号，并将数据信号传输至节点N。
在此阶段，数据信号持续传输至节点N，并持续对存储电容器Cst充电，直至Vgs(驱动晶体管M1中栅极与第一极之间的电压差)的绝对值与Vth(驱动晶体管M1的阈值电压)的绝对值之间的差值小于零，使得驱动晶体管M1关断。此时，也便将驱动晶体管M1的阈值电压写入节点N实现对驱动晶体管M1的阈值电压的补偿。
在S3阶段，第一扫描信号的电平变为低电平，第三像素晶体管M3在第一扫描信号的控制下关闭。第二扫描信号的电平仍为低电平，第二像素晶体管M2保持开启状态，并继续向驱动晶体管M1的第一极传输数据信号。
在S4阶段，第二扫描信号的电平变为高电平，第二像素晶体管M2在第二扫描信号的控制下关闭。
第一使能信号端EM1提供的第一使能信号的电平变为低电平，第五像素晶体管M5在第一使能信号的控制下开启，将电源电压信号端VDD所传输的电源电压信号传输至驱动晶体管M1的第一极。
在S5阶段，第二使能信号端EM2提供的第二使能信号为低电平，第六像素晶体管M6在第二使能信号的控制下开启，使得驱动晶体管M1与待驱动元件300电连接，待驱动元件300在驱动晶体管M1所提供的电流的驱动下开始发光。
在上述驱动待驱动元件300发光的过程中，需要向像素驱动电路200中的第一扫描信号端Gate1和第二扫描信号端Gate2提供如图4所示波形的第一扫描信号和 第二扫描信号。其中，第一扫描信号和第二扫描信号间隔的时间范围例如为1H～2H，H为数据信号端Data提供的数据信号写入一行亚像素P所需的时间。
基于上述，本公开的一些实施例提供了一种可以向上述像素驱动电路200传输第一扫描信号和第二扫描信号的移位寄存器100。
下面，在本公开的实施例提供的电路中，以各晶体管均为P型晶体管为例，对移位寄存器100的结构进行示意性说明。当然，各晶体管也可以均为N型晶体管，或者部分为P型晶体管，部分为N型晶体管，本申请在此不做限定。
而本领域技术人员可以理解到，当各晶体管的类型不同时，对应的时序图也可能不同，所以本申请中的时序图并不因此而限定。
在一些实施例中，如图5～图21所示，该移位寄存器100包括：第一输入子电路1、第二输入子电路3、第一输出子电路2和第二输出子电路4。
在一些示例中，如图5～图21所示，上述第一输入子电路1与输入信号端Input、第一电压信号端VGH、第一时钟信号端CK1及第一节点Q1电连接。其中，输入信号端Input用于接收输入信号，并向该第一输入子电路1输入该输入信号。第一电压信号端VGH用于接收第一电压信号，并向该第一输入子电路1输入第一电压信号。第一时钟信号端CK1用于接收第一时钟信号，并向该第一输入子电路1输入第一时钟信号。第一输入子电路1被配置为，响应于在输入信号端Input处接收的输入信号和在第一电压信号端VGH处接收的第一电压信号，将在第一时钟信号端CK1处接收的第一时钟信号传输至第一节点Q1。
示例性的，在输入信号的电平和第一电压信号的电平为第一输入子电路1导通所需的电平的情况下，第一输入子电路1可以在该输入信号和第一电压信号的共同控制下导通，接收并传输第一时钟信号至第一节点Q1。
在一些示例中，如图5～图21所示，上述第一输出子电路2与第一节点Q1、第二电压信号端VGL及第一输出信号端Out1电连接。其中，第二电压信号端VGL用于接收第二电压信号，并向该第一输出子电路2输入第二电压信号。第一输出子电路2被配置为，在第一节点Q1的电压的控制下，将在第二电压信号端VGL处接收的第二电压信号传输至第一输出信号端Out1，以使第一输出信号端Out1输出第一输出信号。
示例性的，在第一节点Q1的电压为第一输出子电路2导通所需的电压的情况下，第一输出子电路2可以在第一节点Q1的电压的控制下导通，接收并传输第二电压信号至第一输出信号端Out1。
在第一输出子电路2导通的时段，第一输出信号端Out1可以将第二电压信号作为第一输出信号输出。
在一些示例中，如图5～图21所示，第二输入子电路3与输入信号端Input、第一时钟信号端CK1和第二节点Q2电连接。其中，输入信号端Input还用于向该第二输入子电路3输入输入信号。第一时钟信号端CK1还用于向该第二输入子电路3输入第一时钟信号。第二输入子电路3被配置为，响应于在第一时钟信号端CK1处接收的第一时钟信号，将在输入信号端Input处接收的输入信号传输至第二节点Q2。
示例性的，在第一时钟信号的电平为第二输入子电路3导通所需的电平的情况 下，第二输入子电路3可以在第一时钟信号的控制下导通，接收并传输输入信号至第二节点Q2。
在一些示例中，如图5～图21所示，第二输出子电路4与第二节点Q2、第一电压信号端VGH及第一输出信号端Out1电连接。其中，第一电压信号端VGH还用于向该第二输出子电路4输入第一电压信号。第二输出子电路4被配置为，在第二节点Q2的电压的控制下，将在第一电压信号端VGH处接收的第一电压信号传输至第一输出信号端Out1。
示例性的，在第二节点Q2的电压为第二输出子电路4导通所需的电压的情况下，第二输出子电路4可以在第二节点Q2的电压的控制下导通，接收并传输第一电压信号至第一输出信号端Out1。
在第二输出子电路4导通的时段，第一输出信号端Out1可以将第一电压信号作为第一输出信号输出。
在一些示例中，上述的第一电压信号和第二电压信号是不同的。第一电压信号和第二电压信号中的一者的电压值大于参考电压，另一者的电压值小于参考电压。其中，该参考电压例如可以为第一电压信号的电压值和第二电压信号的电压值的平均值。
示例性的，第一电压信号例如为栅极关断电压信号；第二电压信号例如为栅极开启电压。其中，在移位寄存器100所包括的晶体管均为P型管的情况下，第一电压信号例如为直流高电平信号，第二电压信号例如为直流低电平信号。
本公开中的高电平和低电平为相对值，例如高电平为15V，低电平为5V，并不因此而限定了低电平为小于等于0V的电平。
例如，第一电压信号的电压值可以为6V，第二电压信号的电压值可以为-6V，参考电压可以为0V。
如图5和图6所示，移位寄存器100通过第一输入子电路1控制第一输出子电路2的输出，以及通过第二输入子电路3控制第二输出子电路4的输出。其中，第一输出子电路2和第二输出子电路4在不同的时段导通输出信号。
例如，如图22所示，第一输出子电路2相比于第二输出子电路4在先导通。第一输出子电路2输出的第二电压信号(电平为低电平)可以作为第一输出信号的前半部分(也即与S2阶段和S3阶段对应的部分)，第二输出子电路4输出的第一电压信号(电平为高电平)可以作为第一输出信号的后半部分(也即与S4阶段和S5阶段对应的部分)，第二电压信号和第一电压信号可以按次序构成第一输出信号。
在一些示例中，移位寄存器100的输入信号端Input所传输的输入信号的波形，与上述像素驱动电路200的第一扫描信号端Gate1所需的波形相同。移位寄存器100的第一输出信号端Out1所输出的第一输出信号的波形，与上述像素驱动电路200的第二扫描信号端Gate2所需的波形相同。
在将移位寄存器100与显示面板PNL中相应一行亚像素P的像素驱动电路200电连接时，移位寄存器100的输入信号端Input同时可以与该相应一行亚像素P中像素驱动电路200的第一扫描信号端Gate1电连接，也即，在上述的移位寄存器100中，输入信号端Input所传输的输入信号即作为相应的像素驱动电路200的第一扫描信号。移位寄存器100的第一输出信号端Out1可以与相应一行亚像素P中像素驱动电路200的第二扫描信号端Gate2电连接，也即，在上述的移位寄存器100中， 第一输出信号端Out1所输出的第一输出信号即作为相应的像素驱动电路200的第二扫描信号。
通过将移位寄存器100与相应一行亚像素P的像素驱动电路200电连接，便可以利用移位寄存器100向该相应一行亚像素P的像素驱动电路200提供所需的工作时序，驱动该相应一行亚像素P进行显示。
由此，本公开的一些实施例所提供的移位寄存器100，通过设置第一输入子电路1、第二输入子电路3、第一输出子电路2和第二输出子电路4，并将第一输入子电路1、第二输入子电路3、第一输出子电路2和第二输出子电路4分别与相应的信号端电连接，可以利用各信号端之间的相互配合，使得第一输出子电路2和第二输出子电路4在不同的时段导通，并使得第一输出子电路2所输出的第二电压信号和第二输出子电路4所输出的第一电压信号共同构成第一输出信号。
本公开所提供的移位寄存器100中输出信号端Input所传输的输入信号的波形与上述像素驱动电路200的第一扫描信号端Gate1所需的波形相同，第一输出信号端Out1所输出的第一输出信号的波形与上述像素驱动电路200的第二扫描信号端Gate2所需的波形相同，这样可以利用该移位寄存器100向上述6T1C结构的像素驱动电路200提供其所需的第一扫描信号和第二扫描信号，实现对相应亚像素P的显示驱动。也即，本公开所提供的移位寄存器100可以适用于上述6T1C结构的像素驱动电路200。
下面对第一输入子电路1、第一输出子电路2、第二输入子电路3和第二输出子电路4的结构进行示意性说明。
在一些示例中，如图6、图8、图10、图12、图14、图16和图18～图21所示，第一输入子电路1包括：第一晶体管T1、第二晶体管T2和第一电容器C1。
示例性的，如图6所示，第一晶体管T1的栅极与输入信号端Input电连接，第一晶体管T1的第一极与第一电压信号端VGH电连接，第一晶体管T1的第二极与第三节点Q3电连接。其中，输入信号端Input所传输的输入信号可以控制第一晶体管T1的开启或关断。第一晶体管T1被配置为，在输入信号的控制下，将在第一电压信号端VGH处接收的第一电压信号传输至第三节点Q3。
例如，在输入信号的电平为低电平的情况下，第一晶体管T1可以在该输入信号的控制下导通，接收并传输第一电压信号至第三节点Q3。
示例性的，如图6所示，第二晶体管T2的栅极与第三节点Q3电连接(这样使得第一晶体管T1的第二极与第二晶体管T2的栅极电连接)，第二晶体管T2的第一极与第一时钟信号端CK1电连接，第二晶体管T2的第二极与第一节点Q1电连接。其中，第二晶体管T2被配置为，在第三节点Q3的电压的控制下，将在第一时钟信号端CK1处接收的第一时钟信号传输至第一节点Q1。
例如，在第三节点Q3的电压为低电平的情况下，第二晶体管T2可以在该第三节点Q3的电压的控制下导通，接收并传输第一时钟信号至第一节点Q1。
示例性的，如图6所示，第一电容器C1的第一端与第二晶体管T2的第一极电连接，第一电容器C1的第二端与第三节点Q3电连接。其中，第一电容器C1被配置为，使得第三节点Q3的电压随第一时钟信号发生跳变。
例如，在第一时钟信号的电平为低电平的情况下，第三节点Q3的电压可以在 第一电容器C1的作用下变为低电平。
此处，上述第一输入子电路1可以控制第一输出子电路2的信号的输出状况。例如，第一输入子电路1中，第一晶体管T1输出的第一电压信号和第一电容器C1可以相互配合，控制第二晶体管T2的开启或关断，进而控制第一时钟信号向第一输出子电路2的传输，该第一时钟信号可以控制第一输出子电路2的导通或关断，也即，控制第一输出子电路2的信号输出状况。
在一些示例中，如图6、图8、图10、图12、图14、图16和图18～图21所示，第二输入子电路3包括：第三晶体管T3。
示例性的，如图6所示，第三晶体管T3的栅极与第一时钟信号端CK1电连接，第三晶体管T3的第一极与输入信号端Input电连接，第三晶体管T3的第二极与第二节点Q2电连接。其中，第一时钟信号端CK1所传输的第一时钟信号可以控制第三晶体管T3的开启或关断。第三晶体管T3被配置为，在第一时钟信号的控制下，将在输入信号端Input处接收的输入信号传输至第二节点Q2。
例如，在第一时钟信号的电平为低电平的情况下，第三晶体管T3可以在该第一时钟信号的控制下导通，接收并传输第一时钟信号至第二节点Q2。其中，传输至第二节点Q2的输入信号进一步可以控制第二输出子电路4的信号输出状况。
上述第一输入子电路1和第二输入子电路3的结构较为简单，便于制作；而且，有利于减小移位寄存器100的尺寸，减小边框区B的尺寸，使得显示装置2000能够实现窄边框设计。
在一些示例中，如图6、图8、图10、图12、图14、图16和图18～图21所示，第一输出子电路2包括：第四晶体管T4和第二电容器C2。
示例性的，如图6所示，第四晶体管T4的栅极与第一节点Q1电连接，第四晶体管T4的第一极与第二电压信号端VGL电连接，第四晶体管T4的第二极与第一输出信号端Out1电连接。其中，第一输入子电路1与第一节点Q1电连接，第四晶体管T4的栅极也与第一节点Q1电连接，第一输入子电路1传输至第一节点Q1的第一时钟信号，可以进一步传输至第四晶体管T4的栅极。第四晶体管T4被配置为，在第一节点Q1的电压的控制下，将在第二电压信号端VGL处接收的第二电压信号传输至第一输出信号端Out1。
例如，在第一节点Q1的电压为低电平的情况下，第四晶体管T4可以在该第一节点Q1的电压的控制下导通，接收第二电压信号端VGL所提供的第二电压信号，并将该第二电压信号传输至第一输出信号端Out1。
示例性的，如图6所示，第二电容器C2的第一端与第一节点Q1电连接，第二电容器C2的第二端与第二电压信号端VGL电连接。其中，第二电容器C2被配置为，存储电荷以保持第一节点Q1的电位。
例如，在第一输入子电路1传输第一时钟信号至第一节点Q1以使得第四晶体管T4导通的过程中，还会对第二电容器C2进行充电。在第一输入子电路1关断后，第二电容器C2可以放电以保持第一节点Q1的电位，进而使得第四晶体管T4保持导通状态。
在一些示例中，如图6、图8、图10、图12、图14、图16和图18～图21所示，第二输出子电路4包括：第五晶体管T5和第三电容C3。
示例性的，如图6所示，第五晶体管T5的栅极与第二节点Q2电连接，第五晶体管T5的第一极与第一电压信号端VGH电连接，第五晶体管T5的第二极与第一输出信号端Out1电连接。其中，第二输入子电路3与第二节点Q2电连接，第五晶体管T5的栅极也与第二节点Q2电连接，第二输入子电路3传输至第二节点Q2的输入信号，可以进一步传输至第五晶体管T5的栅极。第五晶体管T5被配置为，在第二节点Q2的电压的控制下，将在第一电压信号端VGH处接收的第一电压信号传输至第一输出信号端Out1。
例如，在第二节点Q2的电压为低电平的情况下，第五晶体管T5可以在该第二节点Q2的电压的控制下导通，接收第一电压信号端VGH所提供的第一电压信号，并将该第一电压信号传输至第一输出信号端Out1。
示例性的，如图6所示，第三电容器C3的第一端与第二节点Q2电连接，第三电容器C3的第二端与第一电压信号端VGH电连接。其中，第三电容器C3被配置为，存储电荷以保持第二节点Q2的电位。
例如，在第二输入子电路3传输输入信号至第二节点Q2以使得第五晶体管T5导通的过程中，还会对第三电容器C3进行充电。在第二输入子电路3关断后，第三电容器C3可以放电以保持第二节点Q2的电位，进而使得第五晶体管T5保持导通状态。
在一些实施例中，如图7～图14和图17～图21所示，上述移位寄存器100还包括：控制子电路5。
在一些示例中，如图7～图14和图17～图21所示，控制子电路5与第一电压信号端VGH、第二节点Q2及第一节点Q1电连接。其中，控制子电路5被配置为，在第二节点Q2的电压的控制下，将在第一电压信号端VGH处接收的第一电压信号传输至第一节点Q1，以在第二输出子电路4输出第一输出信号的阶段，控制第一输出子电路2关断。
由上述可知，第一输出子电路2和第二输出子电路4在不同的时段导通，在第一输出子电路2导通的时段，可以将第二电压信号作为第一输出信号输出；在第二输出子电路4导通的时段，可以将第一电压信号作为第一输出信号输出。如果第二输出子电路4输出第一输出信号(也即第一电压信号)的时间比较长，那么在第二输出子电路4输出第一输出信号的过程中，第一节点Q1的电压可能会降低，进而导致第一输出子电路2有信号(也即第二电压信号)输出，这样会影响第一输出信号的准确性，影响移位寄存器100的稳定性。
本公开通过设置控制子电路5，可以在第二输出子电路4输出第一输出信号的阶段，利用控制子电路5确保第一输出子电路2保持关断状态，无信号输出。这样可以保证移位寄存器100输出的准确性和稳定性，确保第一输出信号的准确性。
下面对控制子电路5的结构进行示意性说明。
在一些示例中，如图8、图10、图12、图14和图18～图21所示，控制子电路5包括：第六晶体管T6。
示例性的，如图8所示，第六晶体管T6的栅极与第二节点Q2电连接，第六晶体管T6的第一极与第一电压信号端VGH电连接，第六晶体管T6的第二极与第一节点Q1电连接。其中，第六晶体管T6被配置为，在第二节点Q2的电压的控制下， 将在第一电压信号端VGH处接收的第一电压信号传输至第一节点Q1。
例如，在第二节点Q2的电压为低电平的情况下，第六晶体管T6可以在该第二节点Q2的电压的控制下导通，将第一电压信号端VGH所提供的第一电压信号传输至第一节点Q1。由于第一电压信号为直流高电平信号，第一节点Q1的电压可以在第一电压信号的作用下升高，第四晶体管T4可以在该高电平的第一节点Q1的作用下关断，使得第一输出子电路2无信号输出。
下面结合图8和图22，对本公开中移位寄存器100所包括的第一输入字电路1、第一输出子电路2、第二输入子电路3、第二输出子电路4和控制子电路5的工作原理的过程进行示意性说明。
如图22所示，移位寄存器100工作阶段包括：S1阶段、S2阶段、S3阶段、S4阶段和S1阶段。该多个工作阶段的顺序依次例如可以是S2阶段、S3阶段、S4阶段、S5阶段、S1阶段，其中，S1阶段至S5阶段的时间之和例如可以等于显示面板PNL显示一帧画面的时间。其中，S4阶段和S5阶段会进行循环，循环的时间与显示一帧画面的时间有关，而显示一帧画面的时间与显示面板PNL的分辨率相关。
在S2阶段，如图8和图22所示，输入信号端Input提供的输入信号的电平为高电平，第一输入子电路1中的第一晶体管T1在输入信号的控制下关断。第一时钟信号端CK1提供的第一时钟信号的电平为低电平，在第一输入子电路1中，由于第一电容器C1的作用，第三节点Q3的电压跳变为低电平，第二晶体管T2可以在第三节点Q3的电压的作用下导通，接收并传输第一时钟信号至第一节点Q1，使得第一节点Q1的电压降低。与第一节点Q1电连接的第四晶体管T4可以在第一节点Q1的作用下导通，使得第一输出信号端Out1输出第二电压信号端VGL所提供的第二电压信号。
第一时钟信号的电平为低电平，输入信号的电平为高电平，第二输入子电路3中的第三晶体管T3在第一时钟信号的控制下导通，接收并传输输入信号至第二节点Q2，使得第二节点Q2的电压升高。控制子电路5中的第六晶体管T6在第二节点Q2的电压的控制下关断，第二输出子电路4中第五晶体管T5在第二节点Q2的电压的控制下关断，使得第二输出子电路4无信号输出。
从而，在S2阶段，第一输出信号端Out1输出的第一输出信号等于第二电压信号。
在S3阶段，如图8和图22所示，输入信号端Input提供的输入信号的电平为低电平，第一晶体管T1在输入信号的控制下导通，将在第一电压信号端VGH处接收的第一电压信号传输至第三节点Q3，使得第三节点Q3的电压升高。第二晶体管T2在第三节点Q3的电压的控制下关断，使得第一输入子电路1无信号输出。
在上述S2阶段中，在第二晶体管T2在接收并传输低电平的第一时钟信号至第一节点Q1的过程中，还会对第二电容器C2进行充电。在S3阶段阶段，由于第二电容器C2进行放电，第一节点Q1的电压保持为S2阶段中的低电平使得第四晶体管T4保持导通状态，进而使得第一输出信号端Out1输出第二电压信号端VGL提供的第二电压信号。
第一时钟信号的电平变为高电平，第三晶体管T3在第一时钟信号的控制下关断。
在上述S2阶段中，在第三晶体管T3接收并传输高电平的输入信号至第二节点Q2的过程中，还会对第三电容器C3进行充电。在S3阶段阶段，由于第三电容器C3进行放电，第二节点Q2的电压保持为S2阶段中的高电平，使得第五晶体管T5保持关断状态，进而第二输出子电路4无信号输出。
从而，在S3阶段，第一输出信号端Out1输出的第一输出信号等于第二电压信号。
在S4阶段，如图8和图22所示，输入信号端Input提供的输入信号的电平为低电平，第一晶体管T1在输入信号的控制下导通，将在第一电压信号端VGH处接收的第一电压信号传输至第三节点Q3，使得第三节点Q3的电压升高。第二晶体管T2在第三节点Q3的电压的控制下关断，使得第一输入子电路1无信号输出。
第一时钟信号的电平为低电平，第三晶体管T3在第一时钟信号的控制下导通，接收并传输低电平的输入信号至第二节点Q2，使得第二节点Q2的电压降低。第六晶体管T6在第二节点Q2的电压的控制下导通，将在第一电压信号端VGH处接收的第一电压信号传输至第一节点Q1，使得第一节点Q1的电压升高，进而确保第四晶体管T4保持关断状态，使得第一输出子电路2无信号输出。第五晶体管T5在第二节点Q2的电压的控制下导通，使得第一输出信号端Out1输出第一电压信号端VGH所提供的第一电压信号。
从而，在S4阶段，第一输出信号端Out1输出的第一输出信号等于第一电压信号。
在S5阶段，如图8和图22所示，输入信号端Input提供的输入信号的电平为低电平，第一晶体管T1在输入信号的控制下导通，将在第一电压信号端VGH处接收的第一电压信号传输至第三节点Q3，使得第三节点Q3的电压升高。第二晶体管T2在第三节点Q3的电压的控制下关断，使得第一输入子电路1无信号输出。
由于第二电容C2的作用，第二节点N2保持S4阶段的高电位，第四晶体管T4关断，第一输出子电路12无信号输出。
第一时钟信号的电平变为高电平，第三晶体管T3在第一时钟信号的控制下关断。
在上述S4阶段中，在第六晶体管T6接收并传输高电平的第一电压信号至第一节点Q1的过程中，还会对第二电容器C2进行充电。在第三晶体管T3传输低电平的输入信号至第二节点Q2的过程中，还会对第三电容器C3进行充电。在S5阶段，由于第二电容器C2进行放电，第一节点Q1的电压保持为S4阶段中的高电平，使得第四晶体管T4保持关断状态，进而第一输出子电路2无信号输出。由于第三电容C3进行放电，第二节点Q2的电压保持为S4阶段的低电平，使得第五晶体管T5保持导通状态，进而使得第一输出信号端Out1输出第一电压信号端VGH所提供的第一电压信号。
从而，在S5阶段，第一输出信号端Out1输出的第一输出信号等于第一电压信号。
在S1阶段，输入信号端Input提供的输入信号的电平为高电平，第一晶体管T1在输入信号的控制下关断。第一时钟信号的电平为高电平，由于第一电容器C1的作用，第三节点Q3的电压跳变为高电平，第二晶体管T2可以在第三节点Q3的 电压的作用下关断，使得第一输入子电路1无信号输出。
第一节点Q1的电压保持为S5阶段中的高电平，第四晶体管T4可以在第一节点Q1的电压的作用下关断，使得第一输出子电路2无输出信号。
第一时钟信号的电平为高电平，第三晶体管T3可以在第一时钟信号的电压的作用下关断。由于第三电容器C3的作用，第二节点Q2的电压保持为S5阶段的低电平，第五晶体管T5可以在第二节点Q2的电压的作用下开启，使得第一输出信号端Out1输出第一电压信号端VGH提供的第一电压信号。
从而，在S1阶段，第一输出信号端Out1输出的第一输出信号等于第一电压信号。
上述移位寄存器100的结构简单，且能够准确控制第一输出信号端Out1输出第一输出信号，制作简单、生产成本较低。
在一些实施例中，如图9、图10、图13、图14、图19和图21所示，上述移位寄存器100还包括：电平降低子电路6。
在一些示例中，如图9、图10、图13、图14、图19和图21所示，电平降低子电路6与第二电压信号端VGL及第一输出信号端Out1电连接。其中，电位降低子电路6被配置为，在第一输出子电路2输出第二电压信号的阶段，与第一输出子电路2相配合，降低第一输出信号端Out1输出的第一输出信号的电平。
示例性的，在第一输出子电路2输出第二电压信号的阶段，电平降低子电路6可以在该第二电压信号的作用下导通，将在第二电压信号端VGL处接收的第二电压信号传输至第一输出信号端Out1，使得第一输出信号端Out1所输出的第一输出信号为第一输出子电路2输出第二电压信号和电平降低子电路6输出的第二电压信号共同构成的信号。由于第二电压信号为低电平信号，这样可以降低第一输出信号的电平，提高第一输出信号端Out1的输出能力。
下面对电平降低子电路6的结构进行示意性说明。
在一些示例中，如图9、图10、图13、图14、图19和图21所示，电平降低子电路6包括：第七晶体管T7。
示例性的，如图9所示，第七晶体管T7的栅极与第一输出信号端Out1电连接，第七晶体管T7的第二极与第一输出信号端Out1电连接，第七晶体管T7的第一极与第二电压信号端VGL电连接。其中，第七晶体管T7被配置为，在第一输出子电路2输出第二电压信号的阶段，在第二电压信号的控制下导通，并将在第二电压信号端VGL处接收的第二电压信号传输至第一输出信号端Out1，使得第一输出信号端Out1输出第一输出信号。
在第一输出子电路2导通的情况下，第四晶体管T4可以接收并传输第二电压信号至第一输出信号端Out1，第七晶体管T7可以在该第二电压信号的控制下导通，将第二电压信号端VGL锁提供的第二电压信号传输至第一输出信号端Out1。此时，第一输出信号端Out1输出的第一输出信号包括第四晶体管T4输出的第二电压信号以及第七晶体管T7输出的第二电压信号，这样可以减小第一输出信号端Out1输出的第一输出信号的电平，提高第一输出信号端Out1的输出能力。
需要说明的是，例如第二电压信号的电平为一负值电压，当第七晶体管T7再将一个电平为负值的第二电压信号传输至第一输出信号端Out1的情况下，第一输 出信号的电平等于两个第二电压信号的电平之和，所以第一输出信号的电平是减小的。
在一些实施例中，如图11～图14、图20和图21所示，上述移位寄存器100还包括：电位稳定子电路7。
在一些示例中，如图11～图14、图20和图21所示，电位稳定子电路7与第二电压信号端VGL、第二节点Q2及第四节点Q4电连接。电位稳定子电路7被配置为，响应于第二电压信号，将第二节点Q2的电压传输至第四节点Q4，并稳定第四节点Q4的电压。其中，第二输出子电路4与第四节点Q4电连接，并通过电位稳定子电路7与第二节点Q2电连接。也即，第二输出子电路4和第二输入子电路3之间间接电连接，并通过电位稳定子电路7实现电连接。
示例性的，第二电压信号为低电平信号，电位稳定子电路7可以在第二电压信号的控制下导通，将第二输入子电路3传输至第二节点Q2的输入信号传输至第四节点Q4。在传输至第四节点Q4的输入信号的电平为低电平的情况下，第二输出子电路4可以在第四节点Q4的电压的控制下导通，输出第一输出信号。
在第二输入子电路3关断的情况下，第二输入子电路3无信号输出，第二节点Q2处于悬浮状态，通过设置电位稳定子电路7，可以使得第二节点Q2的电压是可控的，并且使得第四节点Q4的电压是稳定的。
下面对电位稳定子电路7的结构进行示意性说明。
在一些示例中，如图12、图14、图20和图21所示，电位稳定子电路7包括：第八晶体管T8。
示例性的，如图12所示，第八晶体管T8的栅极与第二电压信号端VGL电连接，第八晶体管T8的第一极与第二节点Q2电连接，第八晶体管T8的第二极与第四节点Q4电连接。
由于第八晶体管T8的栅极与第二电压信号端VGL电连接，且第二电压信号为低电平信号，所以第八晶体管T8处于常开状态。
在第二输入子电路3中的第三晶体管T3导通的情况下，第三晶体管T3可以接收并传输输入信号至第二节点，该输入信号可以经过第八晶体管T8传输至第四节点Q4，对第二输出子电路的导通状态进行控制。
在第三晶体管T3关断的情况下，第三晶体管T3无信号输出。第八晶体管T8可以使得第二节点Q2的电压是可控的，避免影响控制子电路5中第六与晶体管T6的导通状态。而且，第八晶体管T8还可以使得第四节点Q4的电位更为稳定，保证第五晶体管T5的工作性能稳定。
在一些实施例中，如图15～图21所示，移位寄存器100还包括：第一反转子电路8和第二反转子电路9。
在一些示例中，如图15～图21所示，第一反转子电路8与第一输出信号端Out1、第一电压信号端VGH及第二输出信号端Out2电连接。其中，第一电压信号端VGH还用于向第一反转子电路8输入第一电压信号。第一反转子电路8被配置为，响应于在第一输出信号端Out1处接收的第一输出信号，将在第一电压信号端VGH处接收的第一电压信号传输至第二输出信号端Out2。
示例性的，在第一输出信号的电平为第一反转子电路8导通所需的电平的情况 下，第一反转子电路8可以在该第一输出信号的控制下导通，接收并传输第一电压信号至第二输出信号端Out2。
在第一反转子电路8导通的时段，第二输出信号端Out2将第一电压信号作为第二输出信号进行输出。
在一些示例中，如图15～图21所示，第二反转子电路9与第一输出信号端Out1、第二电压信号端VGL、第二时钟信号端CK2及第二输出信号端Out2电连接。其中，第二电压信号端VGL还用于向第二反转子电路9输入第二电压信号。第二时钟信号端CK2用于接收第二时钟信号，并将该第二时钟信号输入第二反转子电路9。第二反转子电路9被配置为，响应于在第一输出信号端Out1处接收的第一输出信号、在第二时钟信号端CK2处接收的第二时钟信号，将在第二电压信号端VGL处接收的第二电压信号传输至第二输出信号端Out2。
示例性的，第二反转子电路9可以在第一电压信号和第二时钟信号的作用下导通，接收并传输第二电压信号至第二输出信号端Out2。
在第二反转子电路9导通的时段，第二输出信号端Out2将第二电压信号作为第二输出信号进行输出。
需要说明的是，在第一输出信号和第二时钟信号的相互配合下，第一反转子电路8和第二反转子电路9可以在不同的时段导通。这样在第一反转子电路8输出第二输出信号的过程中，使得第二输出信号仅包括第一电压信号；在第二反转子电路9输出第二输出信号的过程中，使得第二输出信号仅包括第二电压信号，有利于确保第二输出信号的准确性和稳定性。
在一些示例中，在将多个移位寄存器100级联构成栅极驱动电路1000的情况下，除最后一级移位寄存器100以外，每级移位寄存器100可以包括第一反转子电路8和第二反转子电路9，以将第一输出信号转换为第二输出信号，该级移位寄存器100的第二输出信号端Out2可以与下一级移位寄存器100的输入信号端Input电连接，将该级移位寄存器100的第二输出信号端Out2输出的第二输出信号作为下一级移位寄存器100的输入信号，从而实现多个移位寄存器100的级联，能够完成对显示面板PNL的亚像素P的逐行扫描。
下面对第一反转子电路8和第二反转子电路9的结构进行示意性说明。
在一些示例中，如图16和图18～图21所示，第一反转子电路8包括：第九晶体管T9。
示例性的，如图16所示，第九晶体管T9的栅极与第一输出信号端Out1电连接，第九晶体管T9的第一极与第一电压信号端VGH电连接，第九晶体管T9的第二极与第二输出信号端Out2电连接。其中，第九晶体管T9被配置为，在第一输出信号的控制下，将第一电压信号传输至第二输出信号端Out2。
例如，在第一输出信号的电平为低电平的情况下，第九晶体管T9可以在该第一输出信号的作用下导通，接收并传输第一电压信号至第二输出信号端Out2，使得第二输出信号端Out2将第一电压信号作为第二输出信号输出。
在此情况下，低电平的第一输出信号例如为第一输出子电路2输出的第二电压信号。
在一些示例中，如图16和图18～图21所示，第二反转子电路9包括：第十晶 体管T10、第十一晶体管T11、第十二晶体管T12和第四电容器C4。
示例性的，如图16所示，第十晶体管T10的栅极与第一输出信号端Out1电连接，第十晶体管T10的第一极与第一电压信号端VGH电连接，第十晶体管T10的第二极与第五节点Q5电连接。其中，第十晶体管T10被配置为，在第一输出信号的控制下，将第一电压信号传输至第五节点Q5。
例如，在第一输出信号的电平为低电平的情况下，第十晶体管T10可以在该第一输出信号的作用下导通，接收并传输第一电压信号至第五节点Q5，使得第五节点Q5的电压升高。
示例性的，如图16所示，第十一晶体管T11的栅极与第二时钟信号端CK2电连接，第十一晶体管T11的第一极与第二电压信号端VGL电连接，第十一晶体管T11的第二极与第五节点Q5电连接。其中，第十一晶体管T11被配置为，在第二时钟信号的控制下，将第二电压信号传输至第五节点Q5。
例如，在第二时钟信号的电平为低电平的情况下，第十一晶体管T11可以在该第二时钟信号的作用下导通，接收并传输第二电压信号至第五节点Q5，使得第五节点Q5的电压降低。
示例性的，如图16所示，第十二晶体管T12的栅极与第五节点Q5电连接，第十二晶体管T12的第一极与第二电压信号端VGL电连接，第十二晶体管T12的第二极与第二输出信号端Out2电连接。其中，第十二晶体管T12被配置为，在第五节点Q5的电压的控制下，将在第二电压信号端VGL处接收的第二电压信号传输至第二输出信号端Out2。
例如，在第五节点Q5的电压为低电平的情况下，第十二晶体管T12可以在该第五节点Q5的电压的控制下导通，接收并传输第二电压信号至第二输出信号端Out2，使得第二输出信号端Out2将第二电压信号作为第二输出信号输出。
示例性的，如图16所示，第四电容器C4的第一端与第五节点Q5电连接，第四电容器C4的第二端与第二输出信号点Out2电连接。其中，第四电容器C4被配置为，保持第五节点Q5的电位。
例如，在第十晶体管T10导通，并将第一电压信号传输至第五节点Q5的情况下，还会对第四电容器C4进行充电。这样在第十晶体管T10关断的情况下，第四电容器C4还可以进行放电，使得第五节点Q5的电位保持为高电平。
在第十一晶体管M11导通，并将第二电压信号传输至第五节点Q5的情况下，还会对第四电容器C4进行充电。这样在第十晶体管T10关断的情况下，第四电容器C4还可以进行放电，使得第五节点Q5的电位保持为低电平。
下面结合图16和图22，对第一反转子电路8和第二反转子电路9的工作过程进行示意性说明。
在S2阶段，如图16和图22所示，第一输出信号端Out1输出的第一输出信号的电平为低电平，第一反转子电路8中的第九晶体管T9可以在第一输出信号的控制下导通，将在第一电压信号端VGH处接收的第一电压信号传输至第二输出信号端Out2，使得第二输出信号端Out2输出的第二输出信号等于第一电压信号。
第一输出信号端Out1输出的第一输出信号的电平为低电平，第二反转子电路9中，第十晶体管T10可以在第一输出信号的控制下导通，将在第一电压信号端VGH 处接收的第一电压信号传输至第五节点Q5，使得第五节点Q5的电压升高。第十二晶体管T12可以在第五节点Q5的电压的控制下关断。第二时钟信号的电平为高电平，第十一晶体管T11可以在第二时钟信号的控制下关断。第二反转子电路9无信号输出。
从而，在S2阶段，第二输出信号端Out2输出的第二输出信号等于第一电压信号。
在S3阶段，第一输出信号端Out1输出的第一输出信号的电平仍为低电平，第二时钟信号的电平仍为高电平。第一反转子电路8和第二反转子电路9的工作过程与S2阶段相同，具体可以参照S2阶段中的说明，此处不再赘述。
从而，在S3阶段，第二输出信号端Out2输出的第二输出信号等于第一电压信号。
在S4阶段，第一输出信号端Out1输出的第一输出信号的电平变为高电平，第九晶体管T9可以在第一输出信号的控制下关断，第一反转子电路8无信号输出。
第十晶体管T10也可以在第一输出信号的控制下关断。
第二时钟信号的电平变为低电平，第十一晶体管T11可以在第二时钟信号的控制下导通，将在第二电压信号端VGL处接收的第二电压信号传输至第五节点Q5，使得第五节点Q5的电压降低。第十二晶体管T12可以在第五节点Q5的电压的控制下导通，将在第二电压信号端VGL处接收的第二电压信号传输至第二输出信号端Out2。
从而，在S4阶段，第二输出信号端Out2输出的第二输出信号等于第二电压信号。
在S5阶段，第一输出信号端Out1输出的第一输出信号的电平仍为高电平，第二时钟信号的电平仍为低电平。第一反转子电路8和第二反转子电路9的工作过程与S4阶段相同，具体可以参照S4阶段中的说明，此处不再赘述。
从而，在S5阶段，第二输出信号端Out2输出的第二输出信号等于第二电压信号。
在S1阶段，第一输出信号端Out1输出的第一输出信号的电平仍为高电平，第二时钟信号的电平仍为低电平。第一反转子电路8和第二反转子电路9的工作过程与S4阶段相同，具体可以参照S4阶段中的说明，此处不再赘述。
从而，在S1阶段，第二输出信号端Out2输出的第二输出信号等于第二电压信号。
本公开的一些实施例还提供了一种栅极驱动电路1000，如图23～图25所示。该栅极驱动电路1000包括：多个级联的如上所述的移位寄存器100。
其中，图23～图25中所示的A1、A2、A3、A4分别表示移位寄存器100。各移位寄存器100可以分别与显示面板PNL中相应的一行亚像素P电连接，并向相应的一行亚像素P提供所需的扫描信号，以实现逐行扫描。
上述栅极驱动电路1000可以有多种结构，具体可以根据实际需要选择设置。
在一些示例中，各移位寄存器100包括第一输入字电路1、第一输出子电路2、第二输入子电路3和第二输出子电路4。如图23所示，以如图23所示的栅极驱动电路1000的结构图为例，对栅极驱动电路1000中的信号线进行示意性说明。
如图23所示，栅极驱动电路1000包括：第一子时钟信号线CK_1、第二子时钟信号线CK_2和第三子钟信号线CK_3。
如图23所示，第一级移位寄存器100的输入信号端Input可以与第一子时钟信号线CK_1电连接，以接收起始信号作为输入信号(此时，输入信号端Input通过起始信号端Init与第一子时钟信号线CK_1电连接)。其余级移位寄存器100的输入信号端Input例如可以与上一级移位寄存器100的第一输出信号端Out1电连接(例如间接电连接)。其中，在该级移位寄存器100接收上一级移位寄存器100的第一输出信号端Out1输出的第一输出信号之前，例如可以对该第一输出信号进行反转，以将反转后的第一输出信号作为该级移位寄存器100的输入信号。
如图23所示，第2N-1级移位寄存器100的第一时钟信号端CK1可以与第二子时钟信号线CK_2电连接，以接收第一时钟信号。其中，N为正整数。也即，奇数级的移位寄存器100可以与同一条第二子时钟信号线CK_2电连接，接收第一时钟信号。
如图23所示，第2N级移位寄存器100的第一时钟信号端CK1可以与第三子时钟信号线CK_3电连接，以接收第一时钟信号。也即，偶数级的移位寄存器100可以与同一条第三子时钟信号线CK_3电连接，接收第一时钟信号。
此处，第二子时钟信号线CK_2所传输的第一时钟信号的波形可以如图22所示。第三子时钟信号线CK_3所传输的第一时钟信号的相位，相比于第二子时钟信号线CK_2所传输的第一时钟信号的相位，相差1H(例如后置1H)。
此外，栅极驱动电路1000还可以包括：第一直流电压信号线和第二直流电压信号线。
其中，各级移位寄存器100的第一电压信号端VGH可以和第一直流电压信号线电连接，以接收第一电压信号。各级移位寄存器100的第二电压信号端VGL可以与第二直流电压信号线电连接，以接收第二电压信号。
在另一些示例中，各移位寄存器100包括第一输入字电路1、第一输出子电路2、第二输入子电路3、第二输出子电路4、第一反转子电路8和第二反转子电路9。如图25所示，以如图25所示的栅极驱动电路1000的结构图为例，对栅极驱动电路1000中的信号线进行示意性说明。
如图25所示，栅极驱动电路1000包括：第一子时钟信号线CK_1、第二子时钟信号线CK_2、第三子钟信号线CK_3、第四子钟信号线CK_4和第五子钟信号线CK_5。
如图25所示，第一级移位寄存器100的输入信号端Input可以与第一子时钟信号线CK_1电连接，以接收起始信号作为输入信号。此时，输入信号端Input通过起始信号端Init与第一子时钟信号线CK_1电连接，起始信号端Init可以传输起始信号。除了第一级移位寄存器100以外，其余级移位寄存器100的输入信号端Input与上一级移位寄存器100的第二输出信号端Out2电连接，将上一级移位寄存器100的第二输出信号端Out2输出的第二输出信号作为该级移位寄存器100的输入信号。
其中，对于最后一级移位寄存器100，其可以设置第二输出信号端Out2，也可以不设置第二输出信号端Out2，在最后一级移位寄存器100设置了第二输出信号端Out2的情况下，该第二输出信号端Out2可以空置。
如图25所示，第2N-1级移位寄存器的第一时钟信号端CK1可以与第二子时钟信号线CK_2电连接，以接收第一时钟信号。第2N-1级移位寄存器的第二时钟信号端CK2可以与第四子时钟信号线CK_4电连接，以接收第二时钟信号。也即，奇数级的移位寄存器100可以与同一条第四子时钟信号线CK_4电连接，接收第二时钟信号。
如图25所示，第2N级移位寄存器的第一时钟信号端CK1可以与第三子时钟信号线CK_3电连接，以接收第一时钟信号。第2N-1级移位寄存器的第二时钟信号端CK2可以与第五子时钟信号线CK_5电连接，以接收第二时钟信号。也即，偶数级的移位寄存器100可以与同一条第五子时钟信号线CK_5电连接，接收第二时钟信号。
此处，第四子时钟信号线CK_4所传输的第二时钟信号的波形可以如图22所示。第五子时钟信号线CK_5所传输的第二时钟信号的相位，相比于第四子时钟信号线CK_4所传输的第二时钟信号的相位，相差2H(例如后置2H)。
此外，栅极驱动电路1000还可以包括：第一直流电压信号线和第二直流电压信号线。
其中，各级移位寄存器100的第一电压信号端VGH可以和第一直流电压信号线电连接，以接收第一电压信号。各级移位寄存器100的第二电压信号端VGL可以与第二直流电压信号线电连接，以接收第二电压信号。
当然，上述示例仅为栅极驱动电路100所包括的信号线的两种示例。栅极驱动电路1000所包括的信号线的种类及数量并不局限于上述两种示例，栅极驱动电路1000中各信号线与各移位寄存器100之间的电连接方式也不局限于上述两种示例。
本公开的一些实施例所提供的栅极驱动电路1000，具有与上述的移位寄存器100相同的有益效果，因此不再赘述。
本公开的一些实施例还提供了一种移位寄存器的驱动方法。以下以如图23中示出的栅极驱动电路1000(由图6或图8所示的移位寄存器100级联而成)中的第一级移位寄存器100为例，并结合图22中的时序图，对本公开的移位寄存器100在一图像帧内的驱动方法进行示意性说明。
在一些示例中，上述第一级移位寄存器100在一图像帧内的驱动方法包括：
第一阶段(也可称为第一输出阶段)：
在第一输出阶段，在第一节点Q1的电压的控制下，第一输出子电路2开启，将在第二电压信号端VGL处接收的第二电压信号传输至第一输出信号端Out1，该第一输出信号端Out1将所述第二电压信号作为第一输出信号输出。在第二节点Q2的电压的控制下，第二输出子电路4关断，无信号输出。
其中，第一输出阶段包括S2阶段和S3阶段。在第一输出阶段中，移位寄存器100中各晶体管和电容器的工作过程，可以参照上述一些示例中关于S2阶段和S3阶段的说明，此处不再赘述。
第二阶段(也可称为第二输出阶段)：
在第二输出阶段，在第一节点Q1的电压的控制下，第一输出子电路2关断。在第二节点Q2的电压的控制下，第二输出子电路4开启，将在第一电压信号端VGH处接收的第一电压信号传输至第一输出信号端Out1，第一输出信号端Out1将第一电压信号作为第一 输出信号输出。
其中，第一输出阶段包括S4阶段、S5阶段和S1阶段。在第一输出阶段中，移位寄存器100中各晶体管和电容器的工作过程，可以参照上述一些示例中关于S4阶段、S5阶段和S1阶段的说明，此处不再赘述。
在一些实施例中，在本公开所提供的显示装置2000中，栅极驱动电路1000中的各级移位寄存器100和亚像素P中的像素驱动电路200的连接关系，可以根据实际需要选择设置。
在一些示例中，如图2所示，上述亚像素P可以沿第一方向X排列为多行。一行亚像素P包括至少两个亚像素P。相应的，亚像素P所包括的像素驱动电路200则可以沿第一方向X排列为多行，一行像素驱动电路200可以包括至少两个像素驱动电路200。
如图26和图27所示，P1、P2、P3、P4可以分别表示第一行亚像素P、第二行亚像素P、第二行亚像素P、第二行亚像素P。
在一些示例中，如图26和图27所示，栅极驱动电路中1000中的一级移位寄存器100可以与一行亚像素P对应电连接，也即，栅极驱动电路1000中的一级移位寄存器100可以与一行亚像素P中的像素驱动电路200电连接。其连接关系可以为：一个移位寄存器100的输入信号端Input可以与一行像素驱动电路200的第一扫描信号端Gate1电连接，该移位寄存器100的第一输出信号端Out1可以与该行像素驱动电路200的第二扫描信号端Gate2电连接。
示例性的，一个移位寄存器100可以通过两条栅线GL与一行像素驱动电路200电连接。其中，该移位寄存器100的输入信号端Input可以通过一条栅线GL与相应的一行像素驱动电路200的第一扫描信号端Gate1电连接，输入信号端Input不仅传输输入信号至该移位寄存器100，还传输输入信号至该相应的一行像素驱动电路200的第一扫描信号端Gate1，作为第一扫描信号，对该相应的一行像素驱动电路200进行驱动。该移位寄存器100的第一输出信号端Out1可以通过另一条栅线GL与该相应的一行像素驱动电路200的第二扫描信号端Gate2电连接，第一输出信号端Out1输出的第一输出信号作为该相应的一行像素驱动电路200的第二扫描信号，对该相应的一行像素驱动电路200进行驱动。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种移位寄存器，包括：
    第一输入子电路，与输入信号端、第一电压信号端、第一时钟信号端及第一节点电连接；所述第一输入子电路被配置为，响应于在所述输入信号端处接收的输入信号和在所述第一电压信号端处接收的第一电压信号，将在所述第一时钟信号端处接收的第一时钟信号传输至所述第一节点；
    第一输出子电路，与所述第一节点、第二电压信号端及第一输出信号端电连接；所述第一输出子电路被配置为，在所述第一节点的电压的控制下，将在所述第二电压信号端处接收的第二电压信号传输至所述第一输出信号端，以使所述第一输出信号端输出第一输出信号；
    第二输入子电路，与所述输入信号端、所述第一时钟信号端及第二节点电连接；所述第二输入子电路被配置为，响应于所述第一时钟信号，将在所述输入信号端处接收的输入信号传输至所述第二节点；以及，
    第二输出子电路，与所述第二节点、所述第一电压信号端及所述第一输出信号端电连接；所述第二输出子电路被配置为，在所述第二节点的电压的控制下，将在所述第一电压信号端处接收的第一电压信号传输至所述第一输出信号端，以使所述第一输出信号端输出第一输出信号；其中，所述第一电压信号和所述第二电压信号中的一者的电压值大于参考电压，另一者的电压值小于所述参考电压。
  2. 根据权利要求1所述的移位寄存器，其中，所述第一输入子电路包括：第一晶体管、第二晶体管和第一电容器；
    所述第一晶体管的栅极与所述输入信号端电连接，所述第一晶体管的第一极与所述第一电压信号端电连接，所述第一晶体管的第二极与第三节点电连接；
    所述第二晶体管的栅极与所述第三节点电连接，所述第二晶体管的第一极与所述第一时钟信号端电连接，所述第二晶体管的第二极与所述第一节点电连接；
    所述第一电容器的第一端与所述第一时钟信号端电连接，所述第一电容器的第二端与所述第三节点电连接；
    所述第二输入子电路包括：第三晶体管；
    所述第三晶体管的栅极与所述第一时钟信号端电连接，所述第三晶体管的第一极与所述输入信号端电连接，所述第三晶体管的第二极与所述第二节点电连接。
  3. 根据权利要求1或2所述的移位寄存器，其中，所述第一输出子电路包括：第四晶体管和第二电容器；
    所述第四晶体管的栅极与所述第一节点电连接，所述第四晶体管的第一极与所述第二电压信号端电连接，所述第四晶体管的第二极与所述第一输出信号端电连接；
    所述第二电容器的第一端与所述第一节点电连接，所述第二电容器的第二端与所述第二电压信号端电连接；
    所述第二输出子电路包括：第五晶体管和第三电容器；
    所述第五晶体管的栅极与所述第二节点电连接，所述第五晶体管的第一极与所述第一电压信号端电连接，所述第五晶体管的第二极与所述第一输出信号端电连接；
    所述第三电容器的第一端与所述第二节点电连接，所述第三电容器的第二端与所述第一输出信号端电连接。
  4. 根据权利要求1～3中任一项所述的移位寄存器，还包括：控制子电路；
    所述控制子电路与所述第一电压信号端、所述第二节点及所述第一节点电连接；所述控制子电路被配置为，在所述第二节点的电压的控制下，将在所述第一电压信号端处接收的第一电压信号传输至所述第一节点，以在所述第二输出子电路输出第一输出信号的阶段，控制所述第一输出子电路关断。
  5. 根据权利要求4所述的移位寄存器，其中，所述控制子电路包括：第六晶体管；
    所述第六晶体管的栅极与所述第二节点电连接，所述第六晶体管的第一极与所述第一电压信号端电连接，所述第六晶体管的第二极与所述第一节点电连接。
  6. 根据权利要求1～5中任一项所述的移位寄存器，还包括：电平降低子电路；
    所述电平降低子电路与所述第二电压信号端及所述第一输出信号端电连接；所述电位降低子电路被配置为，在所述第一输出子电路输出第二电压的阶段，与所述第一输出子电路相配合，降低所述第一输出信号端输出的第一输出信号的电平。
  7. 根据权利要求6所述的移位寄存器，其中，所述电平降低子电路包括：第七晶体管；
    所述第七晶体管的栅极与所述第一输出信号端电连接，所述第七晶体管的第一极与所述第二电压信号端电连接，所述第七晶体管的第二极与所述第一输出信号端电连接。
  8. 根据权利要求1～7中任一项所述的移位寄存器，还包括：电位稳定子电路；
    所述电位稳定子电路与所述第二电压信号端、所述第二节点及第四节点电连接；所述电位稳定子电路被配置为，响应于所述第二电压信号，将所述第二节点的电压传输至所述第四节点，并稳定所述第四节点的电压；
    其中，所述第二输出子电路与所述第四节点电连接，并通过所述电位稳定子电路与所述第二节点电连接。
  9. 根据权利要求8所述的移位寄存器，其中，所述电位稳定子电路包括：第八晶体管；
    所述第八晶体管的栅极与所述第二电压信号端电连接，所述第八晶体管的第一极与所述第二节点电连接，所述第八晶体管的第二极与所述第四节点电连接；
    在所述第二输出子电路包括第五晶体管和第三电容器的情况下，
    所述第五晶体管的栅极与所述第四节点电连接，并通过所述第七晶体管与所述第二节点电连接；
    所述第三电容器的第一端与所述第四节点电连接，并通过所述第七晶体管与所述第二节点电连接。
  10. 根据权利要求1～9中任一项所述的移位寄存器，还包括：
    第一反转子电路，与所述第一输出信号端、所述第一电压信号端及第二输出信号端电连接；所述第一反转子电路被配置为，响应于在所述第一输出信号端处接收的第一输出信号，将在所述第一电压信号端处接收的第一电压信号传输至所述第二输出信号端；以及，
    第二反转子电路，与所述第一输出信号端、所述第一电压信号端、所述第二电压信号端、第二时钟信号端及所述第二输出信号端电连接；所述第二反转子电路被配置为，响应于在所述第一输出信号端处接收的第一输出信号、在所述第二时钟信号端处接收的第二时钟信号，将在所述第二电压信号端处接收的第二电压信号传输至所述第二输出信号端。
  11. 根据权利要求10所述的移位寄存器，其中，所述第一反转子电路包括：第九晶体管；
    所述第九晶体管的栅极与所述第一输出信号端电连接，所述第九晶体管的第一极与所述第一电压信号端电连接，所述第九晶体管的第二极与所述第二输出信号端电连接；
    所述第二反转子电路包括：第十晶体管、第十一晶体管、第十二晶体管和第四电容器；
    所述第十晶体管的栅极与所述第一输出信号端电连接，所述第十晶体管的第一极与所述第一电压信号端电连接，所述第十晶体管的第二极与所述第五节点电连接；
    所述第十一晶体管的栅极与所述第二时钟信号端电连接，所述第十一晶体管的第一极与所述第二电压信号端电连接，所述第十一晶体管的第二极与所述第五节点电连接；
    所述第十二晶体管的栅极与所述第五节点电连接，所述第十二晶体管的第一极与所述第二电压信号端电连接，所述第十二晶体管的第二极与所述第二输出信号端电连接；
    所述第四电容器的第一端与所述第五节点电连接，所述第四电容器的第二端与所述第二输出信号端电连接。
  12. 一种如权利要求1～11中任一项所述的移位寄存器的驱动方法，包括：
    在第一输出阶段，在第一节点的电压的控制下，第一输出子电路开启，将在第二电压信号端处接收的第二电压信号传输至第一输出信号端，所述第一输出信号端将所述第二电压信号作为第一输出信号输出；在第二节点的电压的控制下，第二输出子电路关断；
    在第二输出阶段，在所述第一节点的电压的控制下，所述第一输出子电路关断；在所述第二节点的电压的控制下，所述第二输出子电路开启，将在第一电压信号端处接收的第一电压信号传输至第一输出信号端，所述第一输出信号端将所述第一电压信号作为第一输出信号输出。
  13. 一种栅极驱动电路，包括：多个级联的如权利要求1～11中任一项所述的移位寄存器。
  14. 一种显示装置，包括：如权利要求13所述的栅极驱动电路。
  15. 根据权利要求14所述的显示装置，还包括：多个像素驱动电路；
    所述多个像素驱动电路沿第一方向排列为多行，一行像素驱动电路包括至少两个像素驱动电路；
    所述栅极驱动电路中，一个移位寄存器的输入信号端与一行像素驱动电路的第一扫描信号端电连接，所述移位寄存器的第一输出信号端与所述一行像素驱动电路的第二扫描信号端电连接。
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