WO2021223579A1 - 像素驱动电路及驱动方法、移位寄存器电路、显示装置 - Google Patents

像素驱动电路及驱动方法、移位寄存器电路、显示装置 Download PDF

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WO2021223579A1
WO2021223579A1 PCT/CN2021/086875 CN2021086875W WO2021223579A1 WO 2021223579 A1 WO2021223579 A1 WO 2021223579A1 CN 2021086875 W CN2021086875 W CN 2021086875W WO 2021223579 A1 WO2021223579 A1 WO 2021223579A1
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circuit
coupled
terminal
sub
transistor
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PCT/CN2021/086875
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English (en)
French (fr)
Inventor
李永谦
冯雪欢
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京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Priority to US17/763,818 priority Critical patent/US11869426B2/en
Publication of WO2021223579A1 publication Critical patent/WO2021223579A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel driving circuit and a driving method, a shift register circuit, and a display device.
  • OLED Organic Light Emitting Diode
  • a pixel driving circuit includes a data writing sub-circuit, a driving sub-circuit and a time control sub-circuit.
  • the data writing sub-circuit is coupled to at least a first scan signal terminal, a data signal terminal, and a first node; the data writing sub-circuit is configured to receive a first scan at the first scan signal terminal Under the control of the signal, the data signal received at the data signal terminal is written into the first node.
  • the driving sub-circuit is coupled to the first node, the second node, and a first power supply voltage signal terminal; the driving sub-circuit is configured to have a voltage at the first node and a voltage at the first power supply Under the control of the first power voltage signal received at the signal terminal, the light-emitting device coupled to the second node is driven to work.
  • the time control sub-circuit is coupled to the first node, the second scan signal terminal and the control signal terminal; the time control sub-circuit is configured to, after the light emitting device operates for a preset time, in the first Under the control of the second scan signal received at the second scan signal terminal, the control signal received at the control signal terminal is transmitted to the first node to turn off the driving sub-circuit to control the light emitting device stop working.
  • the time control sub-circuit includes a first transistor.
  • the control electrode of the first transistor is coupled to the second scan signal terminal, the first electrode of the first transistor is coupled to the control signal terminal, and the second electrode of the first transistor is coupled to the second scan signal terminal.
  • the driver sub-circuit includes a second transistor.
  • the control electrode of the second transistor is coupled to the first node, the first electrode of the second transistor is coupled to the second node, and the second electrode of the second transistor is coupled to the first power supply The voltage signal terminal is coupled.
  • the data writing sub-circuit is also coupled to the second node.
  • the data writing sub-circuit includes: a third transistor and a storage capacitor.
  • the control electrode of the third transistor is coupled to the first scan signal terminal, the first electrode of the third transistor is coupled to the data signal terminal, and the second electrode of the third transistor is coupled to the first scan signal terminal.
  • the first pole of the storage capacitor is coupled to the first node, and the second pole of the storage capacitor is coupled to the second node.
  • the pixel driving sub-circuit further includes a sensing sub-circuit.
  • the sensing sub-circuit is coupled to a third scan signal terminal, the second node, and a sensing signal terminal; the sensing sub-circuit is configured to receive a third scan at the third scan signal terminal Under the control of the signal, the sensing signal received at the sensing signal terminal is transmitted to the second node.
  • the sensing sub-circuit includes a fourth transistor.
  • the control electrode of the fourth transistor is coupled to the third scan signal terminal, the first electrode of the fourth transistor is coupled to the sensing signal terminal, and the second electrode of the fourth transistor is coupled to the The second node is coupled.
  • control signal terminal and the sensing signal terminal are the same signal terminal.
  • the first scan signal terminal and the third scan signal terminal are the same signal terminal.
  • a shift register circuit is provided.
  • the shift register circuit is applied to the pixel driving circuit described in any of the above embodiments.
  • the shift register circuit includes: a first input sub-circuit, a first output sub-circuit, a second input sub-circuit, and a second output sub-circuit.
  • the first input sub-circuit is coupled to at least the pull-up node and the first signal input terminal; the first input sub-circuit is configured to, before the pixel driving circuit receives the first scan signal, the The signal received at the first signal input terminal is transmitted to the pull-up node.
  • the first output sub-circuit is coupled to the first clock signal terminal, the pull-up node, and the first signal output terminal; the first output sub-circuit is configured to, under the control of the voltage of the pull-up node , Transmitting the first clock signal received at the first clock signal terminal to the first signal output terminal, so as to transmit the first scan signal to the first scan signal terminal of the pixel driving circuit.
  • the second input sub-circuit is at least coupled to the pull-up node and the second signal input terminal; the second input sub-circuit is configured to, after the pixel driving circuit drives the light-emitting device for a preset time, The signal received at the second signal input terminal is transmitted to the pull-up node.
  • the second output sub-circuit is coupled to a second clock signal terminal, the pull-up node, and a second signal output terminal; the second output sub-circuit is configured to, under the control of the voltage of the pull-up node , Transmitting the second clock signal received at the second clock signal terminal to the second signal output terminal, so that after the pixel driving circuit drives the light-emitting device for a preset time, the second clock signal is transmitted to the pixel driving circuit
  • the second scan signal terminal transmits the second scan signal.
  • the first output sub-circuit includes a fifth transistor and a first capacitor.
  • the control electrode of the fifth transistor is coupled to the pull-up node, the first electrode of the fifth transistor is coupled to the first clock signal terminal, and the second electrode of the fifth transistor is coupled to the first clock signal terminal.
  • a signal output terminal is coupled.
  • the first pole of the first capacitor is coupled to the pull-up node, and the second pole of the first capacitor is coupled to the first signal output terminal.
  • the second output sub-circuit includes a sixth transistor and a second capacitor.
  • the control electrode of the sixth transistor is coupled to the pull-up node, the first electrode of the sixth transistor is coupled to the second clock signal terminal, and the second electrode of the sixth transistor is coupled to the second clock signal terminal.
  • the two signal output terminals are coupled.
  • the first pole of the second capacitor is coupled to the pull-up node, and the second pole of the second capacitor is coupled to the second signal output terminal.
  • the shift register circuit when the pixel driving circuit includes a sensing sub-circuit, the shift register circuit further includes a third output sub-circuit.
  • the third output sub-circuit is coupled to a third clock signal terminal, the pull-up node, and a third signal output terminal; the third output sub-circuit is configured to, under the control of the voltage of the pull-up node , Transmitting the third clock signal received at the third clock signal terminal to the third signal output terminal, so as to transmit the third scan signal to the third scan signal terminal of the pixel driving circuit.
  • the third output sub-circuit includes a seventh transistor and a third capacitor.
  • the control electrode of the seventh transistor is coupled to the pull-up node, the first electrode of the seventh transistor is coupled to the third clock signal terminal, and the second electrode of the seventh transistor is coupled to the third clock signal terminal.
  • the three signal output ends are coupled.
  • the first pole of the third capacitor is coupled to the pull-up node, and the second pole of the third capacitor is coupled to the third signal output terminal.
  • the shift register circuit further includes a shift signal output sub-circuit.
  • the shift signal output sub-circuit is coupled to the fourth clock signal terminal, the pull-up node, and the shift signal output terminal; the shift signal output sub-circuit is configured to change the voltage of the pull-up node Under control, the fourth clock signal received at the fourth clock signal terminal is transmitted to the shift signal output terminal.
  • the shift signal output sub-circuit includes an eighth transistor.
  • the control electrode of the eighth transistor is coupled to the pull-up node, the first electrode of the eighth transistor is coupled to the fourth clock signal terminal, and the second electrode of the eighth transistor is coupled to the shifter.
  • the bit signal output terminal is coupled.
  • the shift register circuit further includes a first noise reduction sub-circuit and a second noise reduction sub-circuit.
  • the first noise reduction sub-circuit is coupled to a first pull-down node, the first signal output terminal, and a first voltage terminal; the first noise reduction sub-circuit is configured to be at the first pull-down node Under the control of the voltage of, the voltage of the first voltage terminal is transmitted to the first signal output terminal.
  • the first noise reduction sub-circuit is coupled to a first pull-down node, the first signal output terminal, and a first voltage terminal; the first noise reduction sub-circuit is configured to be at the first pull-down node Under the control of the voltage of, the voltage of the first voltage terminal is transmitted to the first signal output terminal.
  • the shift register circuit further includes a third noise reduction sub-circuit.
  • the third noise reduction sub-circuit is coupled to the first pull-down node, the third signal output terminal, and the first voltage terminal; the third noise reduction sub-circuit is configured to be at the first pull-down node Under the control of the voltage of, the voltage of the first voltage terminal is transmitted to the third signal output terminal.
  • the shift register circuit further includes a fourth noise reduction sub-circuit.
  • the fourth noise reduction sub-circuit is coupled to the first pull-down node, the shift signal output terminal, and the second voltage terminal; the fourth noise reduction sub-circuit is configured to be at the first pull-down node Under the control of the voltage of, the voltage of the second voltage terminal is transmitted to the shift signal output terminal.
  • the first noise reduction sub-circuit includes a ninth transistor.
  • the control electrode of the ninth transistor is coupled to the first pull-down node, the first electrode of the ninth transistor is coupled to the third voltage terminal, and the second electrode of the ninth transistor is coupled to the The first signal output terminal is coupled.
  • the second noise reduction sub-circuit includes a tenth transistor.
  • the control electrode of the tenth transistor is coupled to the first pull-down node, the first electrode of the tenth transistor is coupled to the third voltage terminal, and the second electrode of the tenth transistor is coupled to the The second signal output terminal is coupled.
  • the third noise reduction sub-circuit includes an eleventh transistor.
  • the control electrode of the eleventh transistor is coupled to the first pull-down node, the first electrode of the eleventh transistor is coupled to the first voltage terminal, and the second electrode of the eleventh transistor is It is coupled to the third signal output terminal.
  • the fourth noise reduction sub-circuit includes a twelfth transistor.
  • the control electrode of the twelfth transistor is coupled to the first pull-down node, the first electrode of the twelfth transistor is coupled to the second voltage terminal, and the second electrode of the twelfth transistor is Coupled with the shift signal output terminal.
  • the shift register circuit further includes a fifth noise reduction sub-circuit and a sixth noise reduction sub-circuit.
  • the fifth noise reduction sub-circuit is coupled to the second pull-down node, the first signal output terminal, and the first voltage terminal; the fifth noise reduction sub-circuit is configured such that the voltage at the second pull-down node Under the control of, the voltage of the first voltage terminal is transmitted to the first signal output terminal.
  • the sixth noise reduction sub-circuit is coupled to the second pull-down node, the second signal output terminal and the third voltage terminal; the sixth noise reduction sub-circuit is configured to: Under the control of the voltage of the pull-down node, the voltage of the third voltage terminal is transmitted to the second signal output terminal.
  • the shift register circuit further includes a seventh noise reduction sub-circuit.
  • the seventh noise reduction sub-circuit is coupled to the second pull-down node, the third signal output terminal, and the first voltage terminal; the seventh noise reduction sub-circuit is configured to be at the second pull-down node Under the control of the voltage of, the voltage of the first voltage terminal is transmitted to the third signal output terminal.
  • the shift register circuit further includes an eighth noise reduction sub-circuit.
  • the eighth noise reduction sub-circuit is coupled to the second pull-down node, the shift signal output terminal, and the second voltage terminal; the eighth noise reduction sub-circuit is configured such that the voltage at the second pull-down node Under the control of, the voltage of the second voltage terminal is transmitted to the shift signal output terminal.
  • the fifth noise reduction sub-circuit includes a thirteenth transistor.
  • the control electrode of the thirteenth transistor is coupled to the second pull-down node, the first electrode of the thirteenth transistor is coupled to the first voltage terminal, and the second electrode of the thirteenth transistor is coupled to the The first signal output terminal is coupled.
  • the sixth noise reduction sub-circuit includes a fourteenth transistor.
  • the control electrode of the fourteenth transistor is coupled to the second pull-down node, the first electrode of the fourteenth transistor is coupled to the third voltage terminal, and the second electrode of the fourteenth transistor is coupled to the The second signal output terminal is coupled.
  • the seventh noise reduction sub-circuit includes a fifteenth transistor.
  • the control electrode of the fifteenth transistor is coupled to the second pull-down node, the first electrode of the fifteenth transistor is coupled to the first voltage terminal, and the second electrode of the fifteenth transistor is coupled to the The third signal output terminal is coupled.
  • the eighth noise reduction sub-circuit includes a sixteenth transistor.
  • the control electrode of the sixteenth transistor is coupled to the second pull-down node, the first electrode of the sixteenth transistor is coupled to the second voltage terminal, and the second electrode of the sixteenth transistor is coupled to the The shift signal output terminal is coupled.
  • a gate driving circuit in another aspect, includes a plurality of cascaded shift register circuits as described in any of the above embodiments.
  • a display device in another aspect, includes a plurality of pixel driving circuits as described in any of the above embodiments, a plurality of light emitting devices, and a gate driving circuit as described in the above embodiments.
  • One of the pixel driving circuits is coupled to at least one light-emitting device.
  • the gate driving circuit is coupled to each of the pixel driving circuits.
  • a method for driving a pixel driving circuit including: under the control of a first scan signal received by a data writing sub-circuit at a first scan signal terminal, the data The data signal received at the signal terminal is written into the first node; the driving sub-circuit, under the control of the voltage of the first node and the first power supply voltage signal received at the first power supply voltage signal terminal, drives the light emitting coupled to the second node The device works; the time control sub-circuit transmits the control signal received at the control signal terminal to the first scan signal under the control of the second scan signal received at the second scan signal terminal after the light emitting device operates for a preset time A node that disconnects the driving sub-circuit to control the light-emitting device to stop working.
  • the driving method when the pixel driving circuit includes a sensing sub-circuit, the driving method further includes:
  • the sensing sub-circuit While the data writing sub-circuit writes the data signal into the first node, the sensing sub-circuit under the control of the third scan signal received at the third scan signal terminal will The sensing signal received at the signal terminal is transmitted to the second node.
  • FIG. 1 is a structural diagram of a display panel according to some embodiments
  • FIG. 2 is a structural diagram of a pixel driving circuit according to some embodiments.
  • FIG. 3 is another structural diagram of a pixel driving circuit according to some embodiments.
  • FIG. 4 is another structural diagram of a pixel driving circuit according to some embodiments.
  • FIG. 5 is another structural diagram of a pixel driving circuit according to some embodiments.
  • Fig. 6 is a structural diagram of a shift register circuit according to some embodiments.
  • Fig. 7 is another structural diagram of a shift register circuit according to some embodiments.
  • FIG. 8 is another structural diagram of a shift register circuit according to some embodiments.
  • FIG. 9 is a timing diagram of a driving signal of a pixel driving circuit according to some embodiments.
  • FIG. 10 is a timing diagram of a driving signal of a shift register circuit according to some embodiments.
  • FIG. 11 is a structural diagram of a gate driving circuit according to some embodiments.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, “plurality” means two or more.
  • the expressions “coupled” and “connected” and their extensions may be used.
  • the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content of this document.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and the combination of A and B.
  • the term “if” is optionally interpreted as meaning “when” or “when” or “in response to determination” or “in response to detection.”
  • the phrase “if it is determined" or “if [the stated condition or event] is detected” is optionally interpreted to mean “when determining" or “in response to determining" Or “when [stated condition or event] is detected” or “in response to detecting [stated condition or event]”.
  • An embodiment of the present disclosure provides a display device.
  • the above-mentioned display device includes a display panel 100 as shown in FIG. 1.
  • the display panel 100 has a display area (Active Area, AA) and a peripheral area S at least on one side of the AA area.
  • AA Active Area
  • the display panel 100 includes a plurality of sub-pixels P arranged in the AA area.
  • the foregoing multiple sub-pixels P are arranged in an array of n rows and m columns as an example for illustration, but the embodiment of the present invention is not limited to this, and the foregoing multiple sub-pixels P may also be implemented in other ways. Arrangement. Among them, the sub-pixels P arranged in a row along the horizontal direction X are called sub-pixels in the same row, and the sub-pixels P arranged in a row along the vertical direction Y are called sub-pixels in the same column.
  • a pixel driving circuit 20 is provided in the sub-pixel P.
  • one pixel driving circuit 20 is coupled to at least one light emitting device L, and the pixel driving circuit 20 is used to drive the light emitting device L to emit light.
  • the light emitting device L is also electrically connected to the second power supply voltage signal terminal VSS.
  • the second power supply voltage signal terminal VSS transmits a DC low-level signal.
  • the light emitting device L may be an OLED or a light emitting diode (Light Emitting Diode, LED).
  • the working time described in the text can be understood as the light-emitting time of the light-emitting device L; the first pole and the second pole of the light-emitting device L are the anode and the cathode of the light-emitting diode, respectively.
  • the display image of one image frame is switched to the display pattern of the next image frame.
  • the display of one image frame causes image smear (also called dynamic image smear) to appear, which reduces the display effect.
  • Some embodiments of the present disclosure provide a pixel driving circuit 20, as shown in FIG. 2, including: a data writing sub-circuit 201, a driving sub-circuit 202, and a time control sub-circuit 203.
  • the data writing sub-circuit 201 is at least coupled to the first scan signal terminal G1, the data signal terminal DATA and the first node N1.
  • the driving sub-circuit 202 is coupled to the first node N1, the second node N2 and the first power supply voltage signal terminal VDD.
  • the time control sub-circuit 203 is coupled to the first node N1, the second scan signal terminal G2 and the control signal terminal DB.
  • the data writing sub-circuit 201 is configured to write the data signal received at the data signal terminal DATA into the first node N1 under the control of the first scan signal received at the first scan signal terminal G1.
  • the driving sub-circuit 202 is configured to drive the light emitting device L coupled to the second node N2 to operate under the control of the voltage of the first node N1 and the first power supply voltage signal received at the first power supply voltage signal terminal VDD.
  • the first power supply voltage signal is a DC high-level signal.
  • the time control sub-circuit 203 is configured to transmit the control signal received at the control signal terminal DB to the second scan signal under the control of the second scan signal received at the second scan signal terminal G2 after the light emitting device L operates for a preset time.
  • a node N1 turns off the driving sub-circuit 202 to control the light-emitting device L to stop working.
  • the preset working time of the light-emitting device L refers to the time during which the light-emitting device L normally emits light so that the display device displays a normal image.
  • the light-emitting device L stops working the light-emitting device L does not emit light, and the display device presents a black screen.
  • the length of the preset time for the light emitting device L to work can be set according to the actual need of the display device to display a normal image, which is not limited here.
  • control signal received at the control signal terminal DB may be a fixed potential signal, for example, a DC low-level signal; or, the control signal may also be a signal whose potential changes within a set voltage range, for example, a black insertion signal , The signal whose potential is within the set voltage range can control the light-emitting device L to stop working.
  • the light emitting device L continues to work before the next image frame arrives, and the light emitting device L stops working after the light emitting device L in the embodiment of the present disclosure operates for a preset time. That is, the light-emitting device L stops emitting light, which shortens the working time of the light-emitting device L, so that the display device can present a black picture for a period of time before the next image frame arrives, and the dynamic picture response time is prolonged, thereby avoiding the continuous operation of the light-emitting device L As a result, dynamic smear appears in the process of image frame switching, which improves the display effect.
  • the time control sub-circuit 203 transmits the control signal received at the control signal terminal DB to the first node N1 after the light emitting device L operates for a preset time, so that the driver The circuit 202 is disconnected, the light-emitting device L is controlled to stop working, and the light-emitting device L stops emitting light. Compared with the process of switching between image frames, the light emitting device L continues to work before the arrival of the next image frame.
  • the embodiments of the present disclosure shorten the working time of the light emitting device L, so that the display device can be used for a period of time before the next image frame arrives.
  • a black picture is presented within a period of time, which prolongs the motion picture response time (MPRT), thereby avoiding the occurrence of dynamic smear during the image frame switching process due to the continuous operation of the light emitting device L, and improving the display effect.
  • MPRT motion picture response time
  • the higher the refresh frequency of the display device the longer the response time of the dynamic picture, and the smaller the influence of smear on the display effect.
  • the time control sub-circuit 203 includes: a first transistor T1.
  • control electrode of the first transistor T1 is coupled to the second scan signal terminal G2, the first electrode of the first transistor T1 is coupled to the control signal terminal DB, and the second electrode of the first transistor T1 is coupled to the first node N1 .
  • the driving sub-circuit 202 includes: a second transistor T2.
  • control electrode of the second transistor T2 is coupled to the first node N1
  • first electrode of the second transistor T2 is coupled to the second node N2
  • second electrode of the second transistor T2 is coupled to the first power voltage signal terminal VDD catch.
  • the data writing sub-circuit 201 is also coupled to the second node N2.
  • the data writing sub-circuit 201 includes a third transistor T3 and a storage capacitor Cst.
  • control electrode of the third transistor T3 is coupled to the first scan signal terminal G1
  • first electrode of the third transistor T3 is coupled to the data signal terminal DATA
  • second electrode of the third transistor T3 is coupled to the first node N1 .
  • the first pole of the storage capacitor Cst is coupled to the first node N1, and the second pole of the storage capacitor Cst is coupled to the second node N2.
  • the pixel driving sub-circuit 20 further includes a sensing sub-circuit 204.
  • the sensing sub-circuit 204 is coupled to the third scan signal terminal G3, the second node N2 and the sensing signal terminal SE.
  • the sensing sub-circuit 204 is configured to transmit the sensing signal received at the sensing signal terminal SE to the second node N2 under the control of the third scanning signal received at the third scanning signal terminal G3.
  • the display panel 100 further includes a sensing signal line (not shown in the figure).
  • the sensing signal line is coupled to the sensing signal terminal SE.
  • the sensing signal line provides a sensing signal to the sensing signal terminal SE.
  • the display device also includes an external compensation circuit (not shown in the figure).
  • the sensing signal line is coupled with the external compensation circuit.
  • the sensing sub-circuit 204 is further configured to transmit the signal of the second node N2 to the sensing signal terminal SE under the control of the third scan signal received at the third scan signal terminal G3 during the period when the light emitting device L is not working. Voltage.
  • the sensing signal line transmits the voltage of the second node N2 to the external compensation circuit, and the external compensation circuit adjusts the data signal received at the data signal terminal DATA in the subsequent display process according to the voltage of the second node N2.
  • the threshold voltage of the second transistor T2 in the driving sub-circuit 202 can be compensated by means of external compensation, avoiding the difference in the driving current provided by the driving sub-circuit 202 to the light-emitting device L, and improving the uniformity of the brightness of the display device. sex.
  • the sensing sub-circuit 204 includes a fourth transistor T4.
  • control electrode of the fourth transistor T4 is coupled to the third scan signal terminal G3, the first electrode of the fourth transistor T4 is coupled to the sensing signal terminal SE, and the second electrode of the fourth transistor T4 is coupled to the second node N2 catch.
  • control signal terminal DB and the sensing signal terminal SE are the same signal terminal.
  • the time control sub-circuit 203 includes the first transistor T1
  • the first pole of the first transistor T1 is coupled to the sensing signal terminal SE.
  • the number of signal terminals of the pixel driving circuit 20 can be reduced, the number of signal lines correspondingly coupled to the signal terminals can be reduced, and the wiring space of the display panel 100 can be enlarged.
  • the first scan signal terminal G1 and the third scan signal terminal G3 are the same signal terminal.
  • the sensing sub-circuit 204 includes the fourth transistor T4
  • the control electrode of the fourth transistor T4 is coupled to the first scan signal terminal G1.
  • the number of signal terminals of the pixel driving circuit 20 is reduced, the number of signal lines corresponding to the signal terminals is reduced, and the wiring space of the display panel 100 is enlarged.
  • the embodiment of the present disclosure provides a shift register circuit RS.
  • the shift register circuit RS is applied to the pixel driving circuit 20 in any of the above-mentioned embodiments.
  • the shift register circuit RS includes: a first input sub-circuit 301, a first output sub-circuit 302, a second input sub-circuit 303, and a second output sub-circuit 304.
  • the first input sub-circuit 301 is coupled to at least the pull-up node PU and the first signal input terminal IN1.
  • the first output sub-circuit 302 is coupled to the first clock signal terminal CLKA, the pull-up node PU and the first signal output terminal OUT1.
  • the second input sub-circuit 303 is coupled to at least the pull-up node PU and the second signal input terminal IN2.
  • the second output sub-circuit 304 is coupled to the second clock signal terminal CLKB, the pull-up node PU and the second signal output terminal OUT2.
  • the first input sub-circuit 301 is configured to transmit the signal received at the first signal input terminal IN1 to the pull-up node PU before the pixel driving circuit 20 receives the first scan signal.
  • the first output sub-circuit 302 is configured to transmit the first clock signal received at the first clock signal terminal CLKA to the first signal output terminal OUT1 under the control of the voltage of the pull-up node PU, so as to transmit to the pixel driving circuit 20
  • the first scan signal terminal G1 transmits the first scan signal.
  • the second input sub-circuit 303 is configured to transmit the signal received at the second signal input terminal IN2 to the pull-up node PU after the pixel driving circuit 20 drives the light emitting device L for a preset time.
  • the second output sub-circuit 304 is configured to transmit the second clock signal received at the second clock signal terminal CLKB to the second signal output terminal OUT2 under the control of the voltage of the pull-up node PU, so as to transmit the second clock signal to the second signal output terminal OUT2.
  • the second scan signal is transmitted to the second scan signal terminal G2 of the pixel driving circuit 20.
  • the first signal input terminal IN1 and the second signal input terminal IN2 are the same signal terminal.
  • the first output sub-circuit 302 includes a fifth transistor T5 and a first capacitor C1.
  • the control electrode of the fifth transistor T5 is coupled to the pull-up node PU, the first electrode of the fifth transistor T5 is coupled to the first clock signal terminal CLKA, and the second electrode of the fifth transistor T5 is coupled to the first signal output terminal OUT1. Coupling.
  • the first pole of the first capacitor C1 is coupled to the pull-up node PU, and the second pole of the first capacitor C1 is coupled to the first signal output terminal OUT1.
  • the second output sub-circuit 304 includes a sixth transistor T6 and a second capacitor C2.
  • the control electrode of the sixth transistor T6 is coupled to the pull-up node PU, the first electrode of the sixth transistor T6 is coupled to the second clock signal terminal CLKB, and the second electrode of the sixth transistor T6 is coupled to the second signal output terminal OUT2 .
  • the first pole of the second capacitor C2 is coupled to the pull-up node PU, and the second pole of the second capacitor C2 is coupled to the second signal output terminal OUT2.
  • first input sub-circuit 301 and the second input sub-circuit 303 are set, and any circuit or module capable of realizing corresponding functions in the field can be used. In practical applications, technicians can make selections according to the situation, and the present disclosure is not limited herein.
  • the shift register circuit RS when the pixel driving circuit 20 includes a sensing sub-circuit 204, as shown in FIG. 6, the shift register circuit RS further includes: a third output sub-circuit 305.
  • the third output sub-circuit 305 is coupled to the third clock signal terminal CLKC, the pull-up node PU and the third signal output terminal OUT3.
  • the third output sub-circuit 305 is configured to transmit the third clock signal received at the third clock signal terminal CLKC to the third signal output terminal OUT3 under the control of the voltage of the pull-up node PU, so as to transmit to the pixel driving circuit 20
  • the third scan signal terminal G3 transmits the third scan signal.
  • the third output sub-circuit 305 includes a seventh transistor T7 and a third capacitor C3.
  • the control electrode of the seventh transistor T7 is coupled to the pull-up node PU, the first electrode of the seventh transistor T7 is coupled to the third clock signal terminal CLKC, and the second electrode of the seventh transistor T7 is coupled to the third signal output terminal OUT3 .
  • the first pole of the third capacitor C3 is coupled to the pull-up node PU, and the second pole of the third capacitor C3 is coupled to the third signal output terminal OUT3.
  • the shift register circuit RS further includes a shift signal output sub-circuit 306.
  • the shift signal output sub-circuit 306 is coupled to the fourth clock signal terminal CLKD, the pull-up node PU and the shift signal output terminal CR.
  • the shift signal output sub-circuit 306 is configured to transmit the fourth clock signal received at the fourth clock signal terminal CLKD to the shift signal output terminal CR under the control of the voltage of the pull-up node PU.
  • the shift signal output sub-circuit 306 includes an eighth transistor T8.
  • the control electrode of the eighth transistor T8 is coupled to the pull-up node PU, the first electrode of the eighth transistor T8 is coupled to the fourth clock signal terminal CLKD, and the second electrode of the eighth transistor T8 is coupled to the shift signal output terminal CR .
  • the shift register circuit RS further includes: a first noise reduction sub-circuit 307 and a second noise reduction sub-circuit 308.
  • the first noise reduction sub-circuit 307 is coupled to the first pull-down node PD1, the first signal output terminal OUT1 and the first voltage terminal V1.
  • the second noise reduction sub-circuit 308 is coupled to the first pull-down node PD1, the second signal output terminal OUT2, and the first voltage terminal V1.
  • the first noise reduction sub-circuit 307 is configured to transmit the voltage of the first voltage terminal V1 to the first signal output terminal OUT1 under the control of the voltage of the first pull-down node PD1, so that the shift register circuit RS does not transmit the voltage to the pixel
  • the first scan signal terminal G1 of the driving circuit 20 reduces the noise of the first signal output terminal OUT1 in the stage when the first scan signal is transmitted.
  • the second noise reduction sub-circuit 308 is configured to transmit the voltage of the first voltage terminal V1 to the second signal output terminal OUT2 under the control of the voltage of the first pull-down node PD1, so that the shift register circuit RS does not transmit the voltage to the pixel
  • the second scan signal terminal G2 of the driving circuit 20 performs noise reduction on the second signal output terminal OUT2 when the second scan signal is transmitted.
  • the first voltage terminal V1 is configured to transmit a DC low-level signal.
  • the first noise reduction sub-circuit 307 includes: a ninth transistor T9.
  • the control electrode of the ninth transistor T9 is coupled to the first pull-down node PD1, the first electrode of the ninth transistor T9 is coupled to the first voltage terminal V1, and the second electrode of the ninth transistor T9 is coupled to the first signal output terminal OUT1 catch.
  • the second noise reduction sub-circuit 308 includes: a tenth transistor T10.
  • the control electrode of the tenth transistor T10 is coupled to the first pull-down node PD1, the first electrode of the tenth transistor T10 is coupled to the first voltage terminal V1, and the second electrode of the tenth transistor T10 is coupled to the second signal output terminal OUT2 catch.
  • the shift register circuit RS when the shift register circuit RS includes a third output sub-circuit 305, as shown in FIG. 6, the shift register circuit RS further includes a third noise reduction sub-circuit 309.
  • the third noise reduction sub-circuit 309 is coupled to the first pull-down node PD1, the third signal output terminal OUT3, and the first voltage terminal V1.
  • the third noise reduction sub-circuit 309 is configured to transmit the voltage of the first voltage terminal V1 to the third signal output terminal OUT3 under the control of the voltage of the first pull-down node PD1, so that the shift register circuit RS does not transmit the voltage to the pixel
  • the third signal output terminal OUT3 is reduced in noise during the third scanning signal terminal G3 of the driving circuit 20 when the third scanning signal is transmitted.
  • the third noise reduction sub-circuit 309 includes an eleventh transistor T11.
  • the control electrode of the eleventh transistor T11 is coupled to the first pull-down node PD1, the first electrode of the eleventh transistor T11 is coupled to the first voltage terminal V1, and the second electrode of the eleventh transistor T11 is coupled to the third signal output The terminal OUT3 is coupled.
  • the shift register circuit RS when the shift register circuit RS includes a shift signal output sub-circuit 306, as shown in FIG. 6, the shift register circuit RS further includes a fourth noise reduction sub-circuit 310.
  • the fourth noise reduction sub-circuit 310 is coupled to the first pull-down node PD1, the shift signal output terminal CR, and the second voltage terminal V2.
  • the fourth noise reduction sub-circuit 310 is configured to transmit the voltage of the second voltage terminal V2 to the shift signal output terminal CR under the control of the voltage of the first pull-down node PD1, so that the shift register circuit RS does not output scanning
  • the signal stage reduces noise at the shift signal output terminal CR.
  • the second voltage terminal V2 is configured to transmit a DC low-level signal.
  • the potential of the DC low-level signal transmitted by the second voltage terminal V2 is lower than the potential of the DC low-level signal transmitted by the first voltage terminal V1.
  • the fourth noise reduction sub-circuit 310 includes: a twelfth transistor T12.
  • the control electrode of the twelfth transistor T12 is coupled to the first pull-down node PD1, the first electrode of the twelfth transistor T12 is coupled to the second voltage terminal V2, and the second electrode of the twelfth transistor T12 is coupled to the shift signal output
  • the terminal CR is coupled.
  • the shift register circuit RS further includes: a fifth noise reduction sub-circuit 311 and a sixth noise reduction sub-circuit 312.
  • the fifth noise reduction sub-circuit 311 is coupled to the second pull-down node PD2, the first signal output terminal OUT1 and the first voltage terminal V1.
  • the sixth noise reduction sub-circuit 312 is coupled to the second pull-down node PD2, the second signal output terminal OUT2, and the first voltage terminal V1.
  • the fifth noise reduction sub-circuit 311 is configured to transmit the voltage of the first voltage terminal V1 to the first signal output terminal OUT1 under the control of the voltage of the second pull-down node PD2, so that the shift register circuit RS does not drive the pixel
  • the first scan signal terminal G1 of the circuit 20 transmits the first scan signal at the stage when the first signal output terminal OUT1 is noise-reduced.
  • the sixth noise reduction sub-circuit 312 is configured to transmit the voltage of the first voltage terminal V1 to the second signal output terminal OUT2 under the control of the voltage of the second pull-down node PD2, so that the shift register circuit RS does not drive the pixel
  • the second scan signal terminal G2 of the circuit 20 transmits the second scan signal at the stage when the second signal output terminal OUT2 is noise-reduced.
  • the fifth noise reduction sub-circuit 311 includes: a thirteenth transistor T13.
  • the control electrode of the thirteenth transistor T13 is coupled to the second pull-down node PD2, the first electrode of the thirteenth transistor T13 is coupled to the first voltage terminal V1, and the second electrode of the thirteenth transistor T13 is coupled to the first signal output terminal OUT1 is coupled.
  • the sixth noise reduction sub-circuit 312 includes a fourteenth transistor T14.
  • the control electrode of the fourteenth transistor T14 is coupled to the second pull-down node PD2, the first electrode of the fourteenth transistor T14 is coupled to the first voltage terminal V1, and the second electrode of the fourteenth transistor T14 is coupled to the second signal output terminal OUT2 is coupled.
  • the shift register circuit RS when the shift register circuit RS includes the third output sub-circuit 305, as shown in FIG. 6, the shift register circuit RS further includes: a seventh noise reduction sub-circuit 313.
  • the seventh noise reduction sub-circuit 313 is coupled to the second pull-down node PD2, the third signal output terminal OUT3 and the first voltage terminal V1.
  • the seventh noise reduction sub-circuit 313 is configured to transmit the voltage of the first voltage terminal V1 to the third signal output terminal OUT3 under the control of the voltage of the second pull-down node PD2, so that the shift register circuit RS does not drive the pixel
  • the third scan signal terminal G3 of the circuit 20 transmits the third scan signal at the stage when the third signal output terminal OUT3 is noise-reduced.
  • the seventh noise reduction sub-circuit 313 includes: a fifteenth transistor T15.
  • the control electrode of the fifteenth transistor T15 is coupled to the second pull-down node PD2, the first electrode of the fifteenth transistor T15 is coupled to the first voltage terminal V1, and the second electrode of the fifteenth transistor T15 is coupled to the third signal output terminal OUT3 is coupled.
  • the shift register circuit RS when the shift register circuit RS includes a shift signal output sub-circuit 306, as shown in FIG. 6, the shift register circuit RS further includes an eighth noise reduction sub-circuit 314.
  • the eighth noise reduction sub-circuit 314 is coupled to the second pull-down node PD2, the shift signal output terminal CR, and the second voltage terminal V2.
  • the eighth noise reduction sub-circuit 314 is configured to transmit the voltage of the second voltage terminal V2 to the shift signal output terminal CR under the control of the voltage of the second pull-down node PD2, so as not to output the scan signal in the shift register circuit RS The stage of noise reduction is performed on the shift signal output terminal CR.
  • the eighth noise reduction sub-circuit 314 includes: a sixteenth transistor T16.
  • the control electrode of the sixteenth transistor T16 is coupled to the second pull-down node PD2, the first electrode of the sixteenth transistor T16 is coupled to the second voltage terminal V2, and the second electrode of the sixteenth transistor T16 is coupled to the shift signal output terminal CR coupling.
  • the first signal output terminal OUT1 of the shift register circuit RS It is the same signal terminal as the third signal output terminal OUT3.
  • the shift register circuit RS controls the output signal of the third signal output terminal OUT3 by controlling the first output sub-circuit 302, the first noise reduction sub-circuit 307, and the fifth noise reduction sub-circuit 311 to provide the pixel
  • the third scan signal terminal G3 of the driving circuit 20 transmits the third scan signal. In this way, the circuit structure of the shift register circuit RS can be simplified, and the size of the shift register circuit RS can be reduced.
  • the shift register circuit RS also includes other sub-circuits to make the shift register circuit RS work normally.
  • the other sub-circuits include a sub-circuit for controlling the voltage of the first pull-down node PD1 and a sub-circuit for controlling the first pull-down node PD1.
  • the embodiments of the present disclosure do not describe other sub-circuits in the shift register circuit RS, and any circuit or module capable of realizing corresponding functions in the field can be used. In practical applications, technicians can make selections according to the situation, and the present disclosure is not limited herein.
  • the transistors used in the pixel driving circuit 20 and the shift register circuit RS provided in the embodiments of the present disclosure may be thin film transistors (TFT), field effect transistors (Field Effect Transistor, FET), or Other switching devices with the same characteristics are not limited in the embodiments of the present disclosure.
  • the control electrode of each transistor used in the pixel driving circuit 20 and the shift register circuit RS is the gate of the transistor, one of the source and drain of the transistor in the first electrode, and the source of the transistor in the second electrode. And the other in the drain. Since the source and drain of the transistor can be symmetrical in structure, the source and drain of the transistor can be structurally indistinguishable. That is to say, the first electrode and the second electrode of the transistor in the embodiment of the present disclosure The two poles can be indistinguishable in structure.
  • the first electrode of the transistor is a source and the second electrode is a drain; for example, when the transistor is an N-type transistor, the first electrode of the transistor is a drain, The second pole is the source.
  • the first node N1, the second node N2, the pull-up node PU, the first pull-down node PD1, and the second pull-down node PD2 do not represent actual components, but rather represent components in the circuit diagram.
  • the junction of related electrical connections, that is, these nodes are equivalent to the junction of related electrical connections in the circuit diagram.
  • each sub-circuit is not limited to the manner described above, and they can be implemented arbitrarily, such as those skilled in the art.
  • the well-known conventional connection method only needs to ensure that the corresponding function is realized.
  • the above examples cannot limit the protection scope of the present disclosure.
  • the skilled person can choose to use or not apply one or more of the above-mentioned circuits according to the situation.
  • Various combinations and modifications based on the aforementioned circuits do not deviate from the principle of the present disclosure, and will not be repeated here.
  • the voltage at the first voltage terminal V1 is a DC low-level voltage
  • the voltage at the second voltage terminal V2 is a DC low-level voltage
  • control signal received at the control signal terminal DB and the sensing signal received at the sensing signal terminal SE are both represented by a DC low-level signal Vref (as shown in Fig. 9).
  • each noise reduction sub-circuit is taken as an example for description.
  • first signal input terminal IN1 and the second signal input terminal IN2 are the same signal terminal, that is, the signal timings transmitted by the first signal input terminal IN1 and the second signal input terminal IN2 are the same.
  • the shift register circuit RS in the first stage (Q1) in an image frame (1F) as shown in FIG. 10, before the pixel driving circuit 20 receives the first scan signal, referring to FIG. 6, the first input sub The circuit 301 transmits the signal received at the first signal input terminal IN1 to the pull-up node PU, and charges the pull-up node PU.
  • the first input sub-circuit 301 transmits the high-level signal received at the first signal input terminal IN1 to the pull-up node PU, Charge the pull-up node PU. At the same time, the first capacitor C1 and the second capacitor C2 are charged.
  • the fifth transistor T5 transmits the low-level first clock signal to the first signal output terminal OUT1
  • the sixth transistor T6 transmits the low-level second clock signal to the second signal output terminal OUT2.
  • the shift register circuit RS includes the third output sub-circuit 305
  • the third capacitor C3 is also charged.
  • the seventh transistor T7 transmits the low-level third clock signal to the third signal output terminal OUT3.
  • the first output sub-circuit 302 is turned on and will receive at the first clock signal terminal CLKA The first clock signal of is transmitted to the first signal output terminal OUT1 to transmit the first scan signal to the first scan signal terminal G1 of the pixel driving circuit 20.
  • the shift register circuit RS includes the third output sub-circuit 305
  • the third output sub-circuit 305 under the control of the high-level voltage of the pull-up node PU, the third output sub-circuit 305 is turned on and will receive at the third clock signal terminal CLKC.
  • the third clock signal of is transmitted to the third signal output terminal OUT3 to transmit the third scan signal to the third scan signal terminal G3 of the pixel driving circuit 20.
  • the shift register circuit RS includes the shift signal output sub-circuit 306, under the control of the high-level voltage of the pull-up node PU, the shift signal output sub-circuit 306 is turned on, and the fourth clock signal terminal CLKD The fourth clock signal received at is transmitted to the shift signal output terminal CR.
  • the voltage of the pull-up node PU is at a high level, and due to the bootstrap action of the first capacitor C1 and the second capacitor C2, the potential of the pull-up node PU is further raised.
  • the fifth transistor T5 is turned on to transmit the high-level first clock signal received at the first clock signal terminal CLKA to the first signal output terminal OUT1.
  • the third capacitor C3 releases the stored charge to the pull-up node PU. Due to the bootstrap action, the potential of the pull-up node PU is raised, and the seventh transistor T7 is turned on. On, the high-level third clock signal is transmitted to the third signal output terminal OUT3.
  • the shift register circuit RS includes the shift signal output sub-circuit 306
  • the eighth transistor T8 under the control of the high-level voltage of the pull-up node PU, the eighth transistor T8 is turned on and will receive at the fourth clock signal terminal CLKD.
  • the high-level fourth clock signal is transmitted to the shift signal output terminal CR.
  • waveforms of the signals received at the first clock signal terminal CLKA and the third clock signal terminal CLKC are the same, but it does not mean that the two are the same signal.
  • the sixth transistor T6 in the second output sub-circuit 304 is turned on, and transmits the low-level second clock signal to the second signal output terminal OUT2 to transmit a low signal to the second scan signal terminal G2 of the pixel driving circuit 20. Level of the second scan signal.
  • the data signal terminal DATA is connected to the first node N1, and the data writing sub-circuit 201 writes the data signal received at the data signal terminal DATA into the first node N1.
  • the sensing sub-circuit 204 under the control of the third scanning signal received at the third scanning signal terminal G3, the sensing sub-circuit 204 will sense the sensing signal received at the sensing signal terminal SE. The signal is transmitted to the second node N2.
  • the third transistor T3 is turned on, and transmits the low-level data signal received at the data signal terminal DATA to the first node N1, and resets the first node N1.
  • the fourth transistor T4 When the third scan signal received at the third scan signal terminal G3 is a high-level signal, the fourth transistor T4 is turned on to transmit the low-level sensing signal received at the sensing signal terminal SE to the first The second node N2 resets the second node N2.
  • the first scan signal is still a high-level signal
  • the third transistor T3 is in a conducting state, and the high voltage received at the data signal terminal DATA
  • the flat data signal is written into the first node N1 and charges the storage capacitor Cst.
  • the first noise reduction sub-circuit 307 turns the first voltage terminal The voltage of V1 is transmitted to the first signal output terminal OUT1, and the noise of the first signal output terminal OUT1 is reduced.
  • the second noise reduction sub-circuit 308 transmits the voltage of the first voltage terminal V1 to the second signal output terminal OUT2, and performs noise reduction on the second signal output terminal OUT2.
  • the ninth transistor T9 is turned on to transmit the low-level voltage of the first voltage terminal V1 to the first signal output terminal OUT1, at this time, the signal of the first signal output terminal OUT1 is a low-level signal.
  • the tenth transistor T10 is turned on to transmit the low-level voltage of the first voltage terminal V1 to the second signal output terminal OUT2. At this time, the second signal output terminal The signal of OUT2 is a low-level signal.
  • the third noise reduction sub-circuit 309 transmits the voltage of the first voltage terminal V1 to the third signal output terminal OUT3, and reduces the third signal output terminal OUT3. noise.
  • the eleventh transistor T11 is turned on to transmit the low-level voltage of the first voltage terminal V1 to the third signal output At this time, the signal of the third signal output terminal OUT3 is a low-level signal.
  • the shift signal output sub-circuit 306 transmits the voltage of the second voltage terminal V2 to the shift signal output terminal CR, and performs the operation on the shift signal output terminal CR. Noise reduction.
  • the twelfth transistor T12 is turned on to transmit the low-level voltage of the second voltage terminal V2 to the shift signal output Terminal CR, at this time, the potential of the shift signal output terminal CR is low, which reduces noise on the shift signal output terminal CR.
  • the noise reduction sub-circuits coupled to the first pull-down node PD1 and the noise reduction sub-circuits coupled to the second pull-down node PD2 alternately work in a certain period. Workers in this field can design the cycle duration according to actual conditions, which is not limited here. Wherein, in an image frame as shown in FIG. 10, the electric potential of the first pull-down node PD1 is not a fixed low level, and the electric potential of the second pull-down node PD2 is a fixed low level, that is, the same as the first pull-down node PD1 The coupled noise reduction sub-circuits work, and the noise reduction sub-circuits coupled to the second pull-down node PD2 do not work.
  • the noise reduction sub-circuits coupled to the first pull-down node PD1 do not work, and the noise reduction sub-circuits coupled to the second pull-down node PD2 work, refer to FIG. 6,
  • the first noise reduction sub-circuit 307 transmits the voltage of the first voltage terminal V1 to the first signal output terminal OUT1 to reduce noise on the first signal output terminal OUT1.
  • the second noise reduction sub-circuit 308 transmits the voltage of the first voltage terminal V1 to the second signal output terminal OUT2, and performs noise reduction on the second signal output terminal OUT2.
  • the thirteenth transistor T13 is turned on to transmit the low-level voltage of the first voltage terminal V1 to the first signal output terminal OUT1, at this time, the signal of the first signal output terminal OUT1 is a low-level signal.
  • the fourteenth transistor T14 is turned on to transmit the low-level voltage of the first voltage terminal V1 to the second signal output terminal OUT2.
  • the second signal output terminal The signal of OUT2 is a low-level signal.
  • the third noise reduction sub-circuit 309 transmits the voltage of the first voltage terminal V1 to the third signal output terminal OUT3, and reduces the third signal output terminal OUT3. noise.
  • the fifteenth transistor T15 is turned on to transmit the low-level voltage of the first voltage terminal V1 to the third signal output terminal OUT3.
  • the signal of the third signal output terminal OUT3 is a low-level signal.
  • the shift signal output sub-circuit 306 transmits the voltage of the second voltage terminal V2 to the shift signal output terminal CR, and performs the operation on the shift signal output terminal CR. Noise reduction.
  • the sixteenth transistor T16 is turned on to transmit the low-level voltage of the second voltage terminal V2 to the shift signal output terminal CR: At this time, the potential of the shift signal output terminal CR is low, which reduces noise on the shift signal output terminal CR.
  • the first signal output terminal OUT1, the second signal output terminal OUT2, the third signal output terminal OUT3, and the shift signal output terminal CR all transmit low-level signals. Therefore, the first scan signal terminal G1, the second scan signal terminal G2, and the third scan signal terminal G3 of the pixel driving circuit 20 all receive low-level signals.
  • the data signal terminal DATA is connected to the first scan signal terminal G1.
  • the connection of the node N1 is disconnected, and under the control of the third scan signal received at the third scan signal terminal G3, the sensing sub-circuit 204 is disconnected.
  • the driving sub-circuit 202 is turned on under the control of the voltage of the first node N1, and under the control of the first power supply voltage signal received at the first power supply voltage signal terminal VDD, the driving sub-circuit 202 outputs a driving current to drive the second The light emitting device L coupled to the node N2 emits light.
  • the third transistor T3 under the control of the low-level first scan signal received at the first scan signal terminal G1, the third transistor T3 is turned off, and the low voltage received at the third scan signal terminal G3 is Under the control of the flat third scan signal, the fourth transistor T4 is turned off.
  • the second transistor T2 Under the control of the high-level voltage of the first node N1, the second transistor T2 is turned on, and the first power supply voltage signal of the first power supply voltage signal terminal VDD is transmitted to the second node N2, so that the potential of the second node N2 rises .
  • the voltage difference between the first electrode and the second electrode of the storage capacitor Cst does not change suddenly. Therefore, the potential of the first node N1 rises further, so that the second transistor T2 is continuously turned on.
  • the second transistor T2 Under the control of the first power supply voltage signal of the first power supply voltage signal terminal VDD, the second transistor T2 outputs a driving current to drive the light emitting device L to work (that is, to emit light normally).
  • the second input sub-circuit 303 After the pixel driving circuit 20 drives the light-emitting device for a preset time, for the shift register circuit RS, in the first period (q1) in the fourth stage (Q4) as shown in FIG. 10, the second input sub-circuit 303 will The signal received at the second signal input terminal IN2 is transmitted to the pull-up node PU.
  • the second input sub-circuit 303 transmits the high-level signal received at the second signal input terminal IN2 to the pull-up node PU, so that the potential of the pull-up node PU is a high-level potential.
  • the second output sub-circuit 304 is turned on under the control of the voltage of the pull-up node PU, and transmits the second clock signal received at the second clock signal terminal CLKB To the second signal output terminal OUT2 to transmit the second scan signal to the second scan signal terminal G2 of the pixel driving circuit 20.
  • the sixth transistor T6 is turned on to transmit the high-level second clock signal to the second signal output terminal OUT2 to transmit the signal to the pixel drive circuit 20.
  • the second scan signal terminal G2 transmits a high-level second scan signal.
  • the time control sub-circuit 202 is turned on under the control of the second scan signal received at the second scan signal terminal G2, and The control signal received at the control signal terminal DB is transmitted to the first node N1.
  • the driving sub-circuit 202 Under the control of the voltage of the first node N1, the driving sub-circuit 202 is disconnected, so that no driving current flows in the light-emitting device L, and the light-emitting device L stops working, which shortens the working time of the light-emitting device L and increases the dynamic picture response time. Avoid smearing during dynamic picture switching.
  • the first transistor T1 under the control of the high-level second scan signal received at the second scan signal terminal G2, the first transistor T1 is turned on, and the low voltage received at the control signal terminal DB is turned on.
  • the flat control signal is transmitted to the first node N1.
  • the first node N1 has a low-level voltage.
  • the second transistor T2 Under the control of the low-level voltage of the first node N1, the second transistor T2 is turned off, and the second transistor T2 stops driving the light-emitting device L to work, thereby shortening the working time of the light-emitting device L.
  • the light-emitting device L stops working, which shortens the light-emitting time of the light-emitting device L, that is, the light-emitting device L stops emitting light, and the display device can present a black screen for a period of time.
  • the response time of the dynamic picture is prolonged, thereby avoiding the occurrence of dynamic smear in the process of image frame switching due to the continuous operation of the light-emitting device L, and improving the display effect.
  • the eighth transistor T8 in the shift signal output sub-circuit 306 is turned on, and the high-level fourth clock received at the fourth clock signal terminal CLKD The signal is transmitted to the shift signal output terminal CR.
  • the fifth transistor T5 in the first output sub-circuit 302 is turned on, and the low-level first clock signal received at the first clock signal terminal CLKA
  • the seventh transistor T7 in the third output sub-circuit 305 is turned on, and the low-level third clock signal received at the third clock signal terminal CLKC is sent to the third signal output terminal OUT3.
  • the first scan signal terminal G1 and the third scan signal terminal G3 of the pixel drive circuit 20 both transmit low-level signals, and the data is written into the third transistor T3 in the sub-circuit 201 and the third transistor T3 in the sensing sub-circuit 204.
  • the fourth transistors T4 are all off.
  • the second input sub-circuit 303 transmits the high-level signal received at the second signal input terminal IN2 to the pull-up node PU, so that the potential of the pull-up node PU is High level potential.
  • the first pull-down node PD1 in the shift register circuit RS is coupled to the first pull-down node PD1.
  • a noise reduction sub-circuit 307, a second noise reduction sub-circuit 308, a third noise reduction sub-circuit 309, and a fourth noise reduction sub-circuit 310 work, respectively to the first signal output terminal OUT1, the second signal output terminal OUT2, and the third signal output terminal OUT2.
  • the noise reduction of the signal output terminal OUT3 and the shift signal output terminal CR, the specific working mode is similar to the working mode in the third stage (Q3), and will not be repeated here.
  • the second input sub-circuit 303 transmits the high-level signal received at the second signal input terminal IN2 to the pull-up node PU to Make the potential of the pull-up node PU a high-level potential.
  • the first output sub-circuit 302 is turned on, and the first clock signal received at the first clock signal terminal CLKA It is transmitted to the first signal output terminal OUT1 to transmit the first scan signal to the first scan signal terminal G1 of the pixel driving circuit 20.
  • the fifth transistor T5 is turned on to transmit the high-level first clock signal received at the first clock signal terminal CLKA to the first signal output terminal OUT1 .
  • the shift register circuit RS includes the third output sub-circuit 305
  • the third output sub-circuit 305 under the control of the high-level voltage of the pull-up node PU, the third output sub-circuit 305 is turned on and will receive at the third clock signal terminal CLKC.
  • the third clock signal of is transmitted to the third signal output terminal OUT3 to transmit the third scan signal to the third scan signal terminal G3 of the pixel driving circuit 20.
  • the seventh transistor T7 is turned on to transmit the high-level third clock signal received at the third clock signal terminal CLKC to the third signal output ⁇ OUT3.
  • the data is written
  • the sub-circuit 201 writes the data signal received at the data signal terminal DATA into the first node N1.
  • the third transistor T3 under the control of the third scan signal of high level received at the third scan signal terminal G3, the third transistor T3 is turned on, and the high voltage received at the data signal terminal DATA is turned on.
  • a flat data signal is written into the first node N1, and the potential of the first node N1 gradually rises. Accordingly, the potential of the second node N2 will synchronously change with the potential of the first node N1.
  • the sensing sub-circuit 204 is turned on to transmit the voltage of the second node N2 to the sensing signal terminal SE.
  • the fourth transistor T4 is turned on to transmit the voltage of the second node N2 to the sensing signal terminal SE.
  • the sensing signal line coupled to the sensing signal terminal SE transmits the voltage of the second node N2 to the external compensation circuit, and the external compensation circuit adjusts the data in the subsequent display process according to the voltage of the second node N2 The data signal received at the signal terminal DATA.
  • the threshold voltage of the second transistor T2 in the driving sub-circuit 202 can be compensated by means of external compensation, avoiding the difference in the driving current provided by the driving sub-circuit 202 to the light-emitting device L, and improving the uniformity of the brightness of the display device. sex.
  • the eighth transistor T8 in the shift signal output sub-circuit 306 is turned on, and the high-level fourth clock received at the fourth clock signal terminal CLKD The signal is transmitted to the shift signal output terminal CR.
  • the first pull-down node PD1 in the shift register circuit RS is coupled to the first pull-down node PD1.
  • a noise reduction sub-circuit 307, a second noise reduction sub-circuit 308, a third noise reduction sub-circuit 309, and a fourth noise reduction sub-circuit 310 work, respectively to the first signal output terminal OUT1, the second signal output terminal OUT2, and the third signal output terminal OUT2.
  • the noise reduction of the signal output terminal OUT3 and the shift signal output terminal CR, the specific working mode is similar to the working mode in the third stage (Q3), and will not be repeated here.
  • the embodiment of the present disclosure provides a gate driving circuit 10, as shown in FIG. 11, which includes a plurality of cascaded shift register circuits RS in any of the above embodiments.
  • the first signal input terminal IN1 of the first-stage shift register circuit RS(1) is coupled to the start signal line STU.
  • the start signal line STU is configured to transmit a start signal
  • the first stage shift register circuit RS(1) of the gate driving circuit 10 starts to work after receiving the start signal.
  • the first signal input terminal IN1 of each stage shift register circuit is coupled to the shift signal output terminal CR of the previous stage shift register circuit.
  • each stage of shift register unit is also coupled to the reset signal terminal of the shift signal output terminal CR of the next stage of shift register circuit (not shown in the figure) To reset.
  • FIG. 11 only shows the case where the first signal input terminal IN1 and the second signal input terminal IN2 of the shift register circuit RS are the same signal terminal.
  • the second signal input terminal IN2 may be coupled to a signal line (not shown in the figure).
  • the signal transmitted by the signal line to the second signal input terminal IN2 can enable the second input sub-circuit 303 to implement corresponding functions.
  • any two adjacent cascaded shift register circuits RS are coupled to different first clock signal lines, second clock signal lines, third clock signal lines, and fourth clock signal lines.
  • the first clock signal terminal CLKA in the odd-numbered shift register circuit is coupled to the first first clock signal line CLKA1
  • the second clock signal terminal CLKB is coupled to the first second clock signal line CLKB1
  • the third clock signal terminal CLKB is coupled to the first second clock signal line CLKB1.
  • the clock signal terminal CLKC is coupled to the first third clock signal line CLKC1 and the fourth clock signal terminal CLKD is coupled to the first fourth clock signal line CLKD1, the first clock signal terminal CLKA in the even-numbered shift register circuit Is coupled to the second first clock signal line CLKA2, the second clock signal terminal CLKB is coupled to the second second clock signal line CLKB2, and the third clock signal terminal CLKC is coupled to the second third clock signal line CLKC2 And the fourth clock signal terminal CLKD is coupled to the second fourth clock signal line CLKD2.
  • the signal transmitted by the first first clock signal line CLKA1 and the signal transmitted by the second first clock signal line CLKA2, the signal transmitted by the first second clock signal line CLKB1 and the second second clock signal line CLKB2 The signal transmitted, the signal transmitted by the first third clock signal line CLKC1 and the signal transmitted by the second third clock signal line CLKC2, the signal transmitted by the first fourth clock signal line CLKD1, and the second fourth clock signal
  • the signals transmitted by the line CLKD2 have a certain phase difference.
  • the display panel 100 is provided with a plurality of first scan signal lines GL1(1) to GL1(n), a plurality of second scan signal lines GL2(1) to GL2(n), and a plurality of second scan signal lines GL2(1) to GL2(n).
  • the first scan signal line GL1, the second scan signal line GL2, and the third scan signal line GL3 extend in the horizontal direction X
  • the data line DL extends in the vertical direction Y.
  • a shift register circuit RS is coupled to a first scan signal line GL1 to transmit the first scan signal to the first scan signal line GL1, and is coupled to a second scan signal line GL2 to transmit the first scan signal to the first scan signal line GL1.
  • the two scan signal lines GL2 transmit the second scan signal and are coupled to one third scan signal line GL3 to transmit the third scan signal to the third scan signal line GL3.
  • FIG. 1 is only schematic, so that single-side driving is adopted (that is, the gate driving circuit 10 is provided on a single side of the peripheral area S of the display panel 100, and the gate driving circuit 10 is set from a single side.
  • the row-sequential driving of the first scan signal line GL1 and the second scan signal line GL2) will be described as an example.
  • dual-side simultaneous driving may be used (that is, gates are respectively provided along two sides in the extension direction of the first scan signal line GL1 and the second scan signal line GL2 in the peripheral area S of the display panel 100.
  • the pole driving circuit 10 simultaneously drives the first scan signal line GL1 and the second scan signal line GL2 row by row from both sides at the same time through the two gate drive circuits 10).
  • the display panel 100 may adopt double-sided cross driving (that is, two side edges along the extension direction of the first scan signal line GL1 and the second scan signal line GL2 in the peripheral area S of the display panel 100).
  • the gate drive circuits 10 are respectively provided, and the first scan signal line GL1 and the second scan signal line GL2 are sequentially driven row by row through the two gate drive circuits 10 alternately from both sides).
  • the embodiment of the present disclosure takes single-side driving as an example to describe the gate driving circuit 10 provided in the embodiment.
  • a multi-clock signal mode can be adopted for each clock signal terminal in the shift register circuit RS.
  • it may be a 2-clock signal model, a 4-clock signal model, a 6-clock signal model, an 8-clock signal model, or a 10-clock signal model, which is not limited in the present disclosure.
  • the embodiment of the present disclosure takes the 2-clock signal model as an example to describe the gate driving circuit 10 provided in the embodiment.
  • An embodiment of the present disclosure provides a display device.
  • the display device includes a plurality of pixel driving circuits 20 as in any of the above-mentioned embodiments and gate driving circuits 10 as in any of the above-mentioned embodiments.
  • the gate driving circuit 10 is coupled to each pixel driving circuit 20.
  • the gate drive circuit 10 transmits the first scan signal, the second scan signal, and the first scan signal to the pixel drive circuit 20.
  • the display device may be any device that displays images whether in motion (for example, video) or fixed (for example, still images), and regardless of text or images. More specifically, it is expected that the described embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs) , Handheld or portable computers, GPS receivers/navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, TV monitors, flat panel displays, computer monitors, car monitors (e.g., Odometer display, etc.), navigator, cockpit controller and/or display, camera view display (for example, the display of a rear-view camera in a vehicle), electronic photos, electronic billboards or signs, projectors, building structures, packaging And aesthetic structure (for example, a display of the image of a piece of jewelry), etc.
  • PDAs personal data assistants
  • Handheld or portable computers GPS receivers/navigators, cameras
  • MP4 video players
  • the embodiment of the present disclosure provides a driving method of the pixel driving circuit 20 as in any of the above-mentioned embodiments, including:
  • the data writing sub-circuit 201 writes the data signal received at the data signal terminal DATA into the first node N1 under the control of the first scan signal received at the first scan signal terminal G1.
  • the driving sub-circuit 202 drives the light emitting device L coupled to the second node N2 to operate under the control of the voltage of the first node N1 and the first power supply voltage signal received at the first power supply voltage signal terminal VDD.
  • the time control sub-circuit 203 transmits the control signal received at the control signal terminal DB to the first node N1 under the control of the second scan signal received at the second scan signal terminal G2 after the light emitting device L operates for a preset time. , The driving sub-circuit 202 is turned off to control the light-emitting device L to stop working.
  • the driving method of the pixel driving circuit 20 further includes:
  • the sensing sub-circuit 204 While the data writing sub-circuit 301 writes the data signal into the first node N1, the sensing sub-circuit 204, under the control of the third scan signal received at the third scan signal terminal G3, will operate at the sensing signal terminal DB. The received sensing signal is transmitted to the second node N2.
  • the above-mentioned driving method of the pixel driving circuit 20 has the same beneficial effects as the above-mentioned pixel driving circuit 20, so it will not be repeated here.

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Abstract

一种像素驱动电路（20），包括：数据写入子电路（201）、驱动子电路（202）和时间控制子电路（203）；数据写入子电路（201）在第一扫描信号端（G1）处接收的第一扫描信号的控制下，将在数据信号端（DATA）处接收的数据信号写入第一节点（N1）；驱动子电路（202）在第一节点（N1）的电压和在第一电源电压信号端（VDD）处接收的第一电源电压信号的控制下，驱动与第二节点（N2）耦接的发光器件（L）工作；时间控制子电路（203）在发光器件（L）工作预设时间之后，在第二扫描信号端（G2）处接收的第二扫描信号的控制下，将在控制信号端（DB）处接收的控制信号传输至第一节点（N1），使驱动子电路（202）断开，以控制发光器件（L）停止工作。

Description

像素驱动电路及驱动方法、移位寄存器电路、显示装置
本申请要求于2020年05月06日提交的、申请号为202010372715.5的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素驱动电路及驱动方法、移位寄存器电路、显示装置。
背景技术
目前，显示装置大多追求高分辨率、高画质等特性。其中，有机电致发光二极管(Organic Light Emitting Diode，OLED)，具有低能耗、生产成本低、自发光、宽视角及相应速度快等优点，是目前研究领域的热点之一。
发明内容
一方面，提供一种像素驱动电路。所述像素驱动电路包括数据写入子电路、驱动子电路和时间控制子电路。所述数据写入子电路至少与第一扫描信号端、数据信号端和第一节点耦接；所述数据写入子电路被配置为，在所述第一扫描信号端处接收的第一扫描信号的控制下，将在所述数据信号端处接收的数据信号写入所述第一节点。所述驱动子电路与所述第一节点、第二节点和第一电源电压信号端耦接；所述驱动子电路被配置为，在所述第一节点的电压和在所述第一电源电压信号端处接收的第一电源电压信号的控制下，驱动与所述第二节点耦接的发光器件工作。所述时间控制子电路与所述第一节点、第二扫描信号端和控制信号端耦接；所述时间控制子电路被配置为，在所述发光器件工作预设时间之后，在所述第二扫描信号端处接收的第二扫描信号的控制下，将在所述控制信号端处接收的控制信号传输至所述第一节点，使所述驱动子电路断开，以控制所述发光器件停止工作。
在一些实施例中，所述时间控制子电路包括第一晶体管。所述第一晶体管的控制极与所述第二扫描信号端耦接，所述第一晶体管的第一极与所述控制信号端耦接，所述第一晶体管的第二极与所述第一节点耦接。
在一些实施例中，所述驱动子电路包括第二晶体管。所述第二晶体管的控制极与所述第一节点耦接，所述第二晶体管的第一极与所述第二节点耦接，所述第二晶体管的第二极与所述第一电源电压信号端耦接。
在一些实施例中，所述数据写入子电路还与所述第二节点耦接。所述数据写入子电路包括：第三晶体管和存储电容。所述第三晶体管的控制极与所述第一扫描信号端耦接，所述第三晶体管的第一极与所述数据信号端耦接， 所述第三晶体管的第二极与所述第一节点耦接。所述存储电容的第一极与所述第一节点耦接，所述存储电容的第二极与所述第二节点耦接。
在一些实施例中，所述像素驱动子电路还包括感测子电路。所述感测子电路与第三扫描信号端、所述第二节点和感测信号端耦接；所述感测子电路被配置为，在所述第三扫描信号端处接收的第三扫描信号的控制下，将在所述感测信号端处接收的感测信号传输至所述第二节点。
在一些实施例中，所述感测子电路包括第四晶体管。所述第四晶体管的控制极与所述第三扫描信号端耦接，所述第四晶体管的第一极与所述感测信号端耦接，所述第四晶体管的第二极与所述第二节点耦接。
在一些实施例中，所述控制信号端与所述感测信号端为同一信号端。
在一些实施例中，所述第一扫描信号端与所述第三扫描信号端为同一信号端。
另一方面，提供一种移位寄存器电路。所述移位寄存器电路应用于上述任一实施例所述的像素驱动电路。所述移位寄存器电路包括：第一输入子电路、第一输出子电路、第二输入子电路和第二输出子电路。所述第一输入子电路至少与上拉节点和第一信号输入端耦接；所述第一输入子电路被配置为，在所述像素驱动电路接收到第一扫描信号之前，将在所述第一信号输入端处接收的信号传输至所述上拉节点。所述第一输出子电路与第一时钟信号端、所述上拉节点和第一信号输出端耦接；所述第一输出子电路被配置为，在所述上拉节点的电压的控制下，将在所述第一时钟信号端处接收的第一时钟信号传输至所述第一信号输出端，以向所述像素驱动电路的第一扫描信号端传输第一扫描信号。所述第二输入子电路至少与所述上拉节点和第二信号输入端耦接；所述第二输入子电路被配置为，在所述像素驱动电路驱动发光器件工作预设时间之后，将在所述第二信号输入端处接收的信号传输至所述上拉节点。所述第二输出子电路与第二时钟信号端、所述上拉节点和第二信号输出端耦接；所述第二输出子电路被配置为，在所述上拉节点的电压的控制下，将在所述第二时钟信号端处接收的第二时钟信号传输至所述第二信号输出端，以在所述像素驱动电路驱动发光器件工作预设时间之后，向所述像素驱动电路的第二扫描信号端传输第二扫描信号。
在一些实施例中，所述第一输出子电路包括第五晶体管和第一电容。所述第五晶体管的控制极与所述上拉节点耦接，所述第五晶体管的第一极与所述第一时钟信号端耦接，所述第五晶体管的第二极与所述第一信号输出端耦接。所述第一电容的第一极与所述上拉节点耦接，所述第一电容的第二极与 所述第一信号输出端耦接。
所述第二输出子电路包括第六晶体管和第二电容。所述第六晶体管的控制极与所述上拉节点耦接，所述第六晶体管的第一极与所述第二时钟信号端耦接，所述第六晶体管的第二极与所述第二信号输出端耦接。所述第二电容的第一极与所述上拉节点耦接，所述第二电容的第二极与所述第二信号输出端耦接。
在一些实施例中，在所述像素驱动电路包括感测子电路的情况下，所述移位寄存器电路还包括第三输出子电路。所述第三输出子电路与第三时钟信号端、所述上拉节点和第三信号输出端耦接；所述第三输出子电路被配置为，在所述上拉节点的电压的控制下，将在所述第三时钟信号端处接收的第三时钟信号传输至所述第三信号输出端，以向所述像素驱动电路的第三扫描信号端传输第三扫描信号。
在一些实施例中，所述第三输出子电路包括第七晶体管和第三电容。所述第七晶体管的控制极与所述上拉节点耦接，所述第七晶体管的第一极与所述第三时钟信号端耦接，所述第七晶体管的第二极与所述第三信号输出端耦接。所述第三电容的第一极与所述上拉节点耦接，所述第三电容的第二极与所述第三信号输出端耦接。
在一些实施例中，所述移位寄存器电路还包括移位信号输出子电路。所述移位信号输出子电路与第四时钟信号端、所述上拉节点和移位信号输出端耦接；所述移位信号输出子电路被配置为，在所述上拉节点的电压的控制下，将在所述第四时钟信号端处接收的第四时钟信号传输至所述移位信号输出端。
在一些实施例中，所述移位信号输出子电路包括第八晶体管。所述第八晶体管的控制极与所述上拉节点耦接，所述第八晶体管的第一极与所述第四时钟信号端耦接，所述第八晶体管的第二极与所述移位信号输出端耦接。
在一些实施例中，所述移位寄存器电路还包括第一降噪子电路和第二降噪子电路。所述第一降噪子电路与第一下拉节点、所述第一信号输出端和第一电压端耦接；所述第一降噪子电路被配置为，在所述第一下拉节点的电压的控制下，将所述第一电压端的电压传输至所述第一信号输出端。所述第一降噪子电路与第一下拉节点、所述第一信号输出端和第一电压端耦接；所述第一降噪子电路被配置为，在所述第一下拉节点的电压的控制下，将所述第一电压端的电压传输至所述第一信号输出端。
在所述移位寄存器电路包括第三输出子电路的情况下，所述移位寄存器 电路还包括第三降噪子电路。所述第三降噪子电路与所述第一下拉节点、第三信号输出端和第一电压端耦接；所述第三降噪子电路被配置为，在所述第一下拉节点的电压的控制下，将所述第一电压端的电压传输至所述第三信号输出端。
在所述移位寄存器电路包括移位信号输出子电路的情况下，所述移位寄存器电路还包括第四降噪子电路。所述第四降噪子电路与所述第一下拉节点、移位信号输出端和第二电压端耦接；所述第四降噪子电路被配置为，在所述第一下拉节点的电压的控制下，将所述第二电压端的电压传输至所述移位信号输出端。
在一些实施例中，所述第一降噪子电路包括第九晶体管。所述第九晶体管的控制极与所述第一下拉节点耦接，所述第九晶体管的第一极与所述第三电压端耦接，所述第九晶体管的第二极与所述第一信号输出端耦接。
所述第二降噪子电路包括第十晶体管。所述第十晶体管的控制极与所述第一下拉节点耦接，所述第十晶体管的第一极与所述第三电压端耦接，所述第十晶体管的第二极与所述第二信号输出端耦接。
在所述移位寄存器电路包括第三降噪子电路的情况下，所述第三降噪子电路包括第十一晶体管。所述第十一晶体管的控制极与所述第一下拉节点耦接，所述第十一晶体管的第一极与所述第一电压端耦接，所述第十一晶体管的第二极与所述第三信号输出端耦接。
在所述移位寄存器电路包括第四降噪子电路的情况下，所述第四降噪子电路包括第十二晶体管。所述第十二晶体管的控制极与所述第一下拉节点耦接，所述第十二晶体管的第一极与所述第二电压端耦接，所述第十二晶体管的第二极与所述移位信号输出端耦接。
在一些实施例中，所述移位寄存器电路还包括第五降噪子电路和第六降噪子电路。所述第五降噪子电路与第二下拉节点、所述第一信号输出端和第一电压端耦接；所述第五降噪子电路被配置为，在所述第二下拉节点的电压的控制下，将所述第一电压端的电压传输至所述第一信号输出端。所述第六降噪子电路与所述第二下拉节点、所述第二信号输出端和所述第三电压端耦接；所述第六降噪子电路被配置为，在所述第二下拉节点的电压的控制下，将所述第三电压端的电压传输至所述第二信号输出端。
在所述移位寄存器电路包括第三输出子电路的情况下，所述移位寄存器电路还包括第七降噪子电路。所述第七降噪子电路与所述第二下拉节点、第三信号输出端和所述第一电压端耦接；所述第七降噪子电路被配置为，在所 述第二下拉节点的电压的控制下，将所述第一电压端的电压传输至所述第三信号输出端。
在所述移位寄存器电路包括移位信号输出子电路的情况下，所述移位寄存器电路还包括第八降噪子电路。所述第八降噪子电路与所述第二下拉节点、移位信号输出端和第二电压端耦接；所述第八降噪子电路被配置为，在所述第二下拉节点的电压的控制下，将所述第二电压端的电压传输至所述移位信号输出端。
在一些实施例中，所述第五降噪子电路包括第十三晶体管。所述第十三晶体管的控制极与所述第二下拉节点耦接，所述第十三晶体管的第一极与所述第一电压端耦接，所述第十三晶体管的第二极与所述第一信号输出端耦接。
所述第六降噪子电路包括第十四晶体管。所述第十四晶体管的控制极与所述第二下拉节点耦接，所述第十四晶体管的第一极与所述第三电压端耦接，所述第十四晶体管的第二极与所述第二信号输出端耦接。
在所述移位寄存器电路包括第七降噪子电路的情况下，所述第七降噪子电路包括第十五晶体管。所述第十五晶体管的控制极与所述第二下拉节点耦接，所述第十五晶体管的第一极与所述第一电压端耦接，所述第十五晶体管的第二极与所述第三信号输出端耦接。
在所述移位寄存器电路包括第八降噪子电路的情况下，所述第八降噪子电路包括第十六晶体管。所述第十六晶体管的控制极与所述第二下拉节点耦接，所述第十六晶体管的第一极与所述第二电压端耦接，所述第十六晶体管的第二极与所述移位信号输出端耦接。
又一方面，提供一种栅极驱动电路。所述栅极驱动电路包括多个级联的如上述任一实施例所述的移位寄存器电路。
再一方面，提供一种显示装置。所述显示装置包括多个如上述任一实施例所述的像素驱动电路、多个发光器件和如上述实施例所述的栅极驱动电路。一个所述像素驱动电路与至少一个发光器件耦接。所述栅极驱动电路与各所述像素驱动电路耦接。
又一方面，提供一种如上述任一实施例所述的像素驱动电路的驱动方法，包括：数据写入子电路在第一扫描信号端处接收的第一扫描信号的控制下，将在数据信号端处接收的数据信号写入第一节点；驱动子电路在第一节点的电压和第一电源电压信号端处接收的第一电源电压信号的控制下，驱动与第二节点耦接的发光器件工作；时间控制子电路在所述发光器件工作预设时间之后，在第二扫描信号端处接收的第二扫描信号的控制下，将在控制信号端 处接收的控制信号传输至所述第一节点，使所述驱动子电路断开，以控制所述发光器件停止工作。
在一些实施例中，在所述像素驱动电路包括感测子电路的情况下，所述驱动方法还包括：
在所述数据写入子电路将所述数据信号写入所述第一节点的同时，所述感测子电路在第三扫描信号端处接收的第三扫描信号的控制下，将在感测信号端处接收的感测信号传输至所述第二节点。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的显示面板的一种结构图；
图2为根据一些实施例的像素驱动电路的一种结构图；
图3为根据一些实施例的像素驱动电路的另一种结构图；
图4为根据一些实施例的像素驱动电路的又一种结构图；
图5为根据一些实施例的像素驱动电路的又一种结构图；
图6为根据一些实施例的移位寄存器电路的一种结构图；
图7为根据一些实施例的移位寄存器电路的另一种结构图；
图8为根据一些实施例的移位寄存器电路的又一种结构图；
图9为根据一些实施例的像素驱动电路的一种驱动信号时序图；
图10为根据一些实施例的移位寄存器电路的一种驱动信号时序图；
图11为根据一些实施例的栅极驱动电路的一种结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包 含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
本公开的实施例提供一种显示装置。
上述的显示装置包括如图1所示的显示面板100。显示面板100具有显示区(Active Area，AA)和至少位于AA区一侧的周边区S。
如图1所示，显示面板100包括设置于AA区中的多个亚像素P。
需要说明的是，图1中以上述多个亚像素P呈n行m列的阵列形式排列为例进行示意，但本发明实施例不限于此，上述多个亚像素P还可以以其他方式进行排布。其中，沿水平方向X排列成一排的亚像素P称为同一行亚像素，沿竖直方向Y排列成一排的亚像素P称为同一列亚像素。
在一些实施例中，如图1所示，亚像素P内设置有像素驱动电路20。
如图2所示，一个像素驱动电路20与至少一个发光器件L耦接，像素驱动电路20用于驱动发光器件L发光。
其中，该发光器件L还与第二电源电压信号端VSS电连接。
示例性地，第二电源电压信号端VSS传输直流低电平信号。
示例性地，发光器件L可以采用OLED或者发光二极管(Light Emitting Diode，LED)。在这种情况下，文中所述的工作时长可以被理解为发光器件L的发光时长；发光器件L的第一极和第二极分别为发光二极管的阳极和阴极。
在动态画面切换过程中，如果发光器件L工作时间较长，在一图像帧的显示图像切换至下一图像帧的显示图案的过程中，上一图像帧的显示画面会出现拖影，影响下一图像帧的显示画面，导致出现图像拖影(也称动态图像拖影)，降低显示效果。
本公开的一些实施例提供一种像素驱动电路20，如图2所示，包括：数据写入子电路201、驱动子电路202和时间控制子电路203。
数据写入子电路201至少与第一扫描信号端G1、数据信号端DATA和第一节点N1耦接。
驱动子电路202与第一节点N1、第二节点N2和第一电源电压信号端VDD耦接。
时间控制子电路203与第一节点N1、第二扫描信号端G2和控制信号端DB耦接。
其中，数据写入子电路201被配置为在第一扫描信号端G1处接收的第一扫描信号的控制下，将在数据信号端DATA处接收的数据信号写入第一节点N1。
驱动子电路202被配置为在第一节点N1的电压和在第一电源电压信号端VDD处接收的第一电源电压信号的控制下，驱动与第二节点N2耦接的发光器件L工作。
示例性地，第一电源电压信号为直流高电平信号。
时间控制子电路203被配置为在发光器件L工作预设时间之后，在第二 扫描信号端G2处接收的第二扫描信号的控制下，将在控制信号端DB处接收的控制信号传输至第一节点N1，使驱动子电路202断开，以控制发光器件L停止工作。
其中，发光器件L工作预设时间指的是发光器件L正常发光，以使显示装置显示正常图像的时间。在发光器件L停止工作的情况下，发光器件L不发光，显示装置呈现黑画面。
需要说明的是，可以根据显示装置实际显示正常图像的需要，设定发光器件L工作预设时间的时长，在此不做限定。
并且，本领域技术人员可以在保证发光器件L工作预设时间之后，显示装置切换成黑画面的情况下，对控制信号的电压大小进行设定。示例性地，控制信号端DB处接收的控制信号可以为固定电位信号，例如，直流低电平信号；或者，控制信号也可以为电位在设定电压范围内变化的信号，例如，插黑信号，该电位在设定电压范围内的信号可以控制发光器件L停止工作。
在此情况下，相比于在图像帧切换的过程中，发光器件L在下一图像帧到来之前持续工作，本公开的实施例中的发光器件L工作预设时间之后，发光器件L停止工作，即发光器件L停止发光，缩短了发光器件L的工作时长，使得在下一图像帧到来之前，显示装置可以在一段时间内呈现黑画面，延长了动态画面响应时间，从而避免由于发光器件L持续工作而导致在图像帧切换的过程中出现动态拖影，提高显示效果。
因此，本公开的实施例提供的像素驱动电路20，时间控制子电路203在发光器件L工作预设时间之后，将在控制信号端DB处接收的控制信号传输至第一节点N1，使驱动子电路202断开，控制发光器件L停止工作，发光器件L停止发光。相比于在图像帧切换的过程中，发光器件L在下一图像帧到来之前持续工作，本公开的实施例缩短了发光器件L的工作时长，使得在下一图像帧到来之前，显示装置可以在一段时间内呈现黑画面，延长了动态画面响应时间(Motion Picture Response Time，MPRT)，从而避免由于发光器件L持续工作而导致在图像帧切换的过程中出现动态拖影，提高了显示效果。并且，显示装置的刷新频率越高，动态画面响应时间越长，拖影对显示效果的影响越小。
示例性地，如图3所示，时间控制子电路203包括：第一晶体管T1。
其中，第一晶体管T1的控制极与第二扫描信号端G2耦接，第一晶体管T1的第一极与控制信号端DB耦接，第一晶体管T1的第二极与第一节点N1耦接。
示例性地，如图3所示，驱动子电路202包括：第二晶体管T2。
其中，第二晶体管T2的控制极与第一节点N1耦接，第二晶体管T2的第一极与第二节点N2耦接，第二晶体管T2的第二极与第一电源电压信号端VDD耦接。
示例性地，如图3所示，数据写入子电路201还与第二节点N2耦接。数据写入子电路201包括：第三晶体管T3和存储电容Cst。
其中，第三晶体管T3的控制极与第一扫描信号端G1耦接，第三晶体管T3的第一极与数据信号端DATA耦接，第三晶体管T3的第二极与第一节点N1耦接。
存储电容Cst的第一极与第一节点N1耦接，存储电容Cst的第二极与第二节点N2耦接。
在一些实施例中，如图2所示，像素驱动子电路20还包括感测子电路204。
感测子电路204与第三扫描信号端G3、第二节点N2和感测信号端SE耦接。
感测子电路204被配置为在第三扫描信号端G3处接收的第三扫描信号的控制下，将在感测信号端SE处接收的感测信号传输至第二节点N2。
在此情况下，显示面板100还包括感测信号线(图中未示出)。感测信号线与感测信号端SE耦接。感测信号线向感测信号端SE提供感测信号。
此外，显示装置还包括外部补偿电路(图中未示出)。感测信号线与外部补偿电路耦接。感测子电路204还被配置为，在发光器件L不工作的时间段，在第三扫描信号端G3处接收的第三扫描信号的控制下，向感测信号端SE传输第二节点N2的电压。
在此情况下，感测信号线将第二节点N2的电压传输至外部补偿电路，外部补偿电路根据第二节点N2的电压，调整在后续显示过程中数据信号端DATA处接收的数据信号。这样，可以通过外部补偿的方式，对驱动子电路202中的第二晶体管T2的阈值电压进行补偿，避免了驱动子电路202向发光器件L提供的驱动电流的差异，提高了显示装置的亮度均一性。
示例性地，如图3所示，感测子电路204包括第四晶体管T4。
其中，第四晶体管T4的控制极与第三扫描信号端G3耦接，第四晶体管T4的第一极与感测信号端SE耦接，第四晶体管T4的第二极与第二节点N2耦接。
在一些实施例中，控制信号端DB与感测信号端SE为同一信号端。
示例性地，如图4所示，在时间控制子电路203包括第一晶体管T1的情 况下，第一晶体管T1的第一极与感测信号端SE耦接。
在此情况下，可以减少了像素驱动电路20的信号端的数量，减少了与信号端对应耦接的信号线的数量，扩大了显示面板100的布线空间。
在一些实施例中，第一扫描信号端G1和第三扫描信号端G3为同一信号端。
可以理解的是，数据写入子电路201和感测子电路204同步开启。
示例性地，如图5所示，在感测子电路204包括第四晶体管T4的情况下，第四晶体管T4的控制极与第一扫描信号端G1耦接。
在此情况下，减少了像素驱动电路20的信号端的数量，减少了与信号端对应耦接的信号线的数量，扩大了显示面板100的布线空间。
本公开的实施例提供一种移位寄存器电路RS。移位寄存器电路RS应用于上述任一实施例中的像素驱动电路20。
如图6所示，移位寄存器电路RS包括：第一输入子电路301、第一输出子电路302、第二输入子电路303和第二输出子电路304。
第一输入子电路301至少与上拉节点PU和第一信号输入端IN1耦接。
第一输出子电路302与第一时钟信号端CLKA、上拉节点PU和第一信号输出端OUT1耦接。
第二输入子电路303至少与上拉节点PU和第二信号输入端IN2耦接。
第二输出子电路304与第二时钟信号端CLKB、上拉节点PU和第二信号输出端OUT2耦接。
其中，第一输入子电路301被配置为在像素驱动电路20接收到第一扫描信号之前，将在第一信号输入端IN1处接收的信号传输至上拉节点PU。
第一输出子电路302被配置为在上拉节点PU的电压的控制下，将在第一时钟信号端CLKA处接收的第一时钟信号传输至第一信号输出端OUT1，以向像素驱动电路20的第一扫描信号端G1传输第一扫描信号。
第二输入子电路303被配置为在像素驱动电路20驱动发光器件L工作预设时间之后，将在第二信号输入端IN2处接收的信号传输至上拉节点PU。
第二输出子电路304被配置为在上拉节点PU的电压的控制下，将在第二时钟信号端CLKB处接收的第二时钟信号传输至第二信号输出端OUT2，以在像素驱动电路20驱动发光器件L工作预设时间之后，向像素驱动电路20的第二扫描信号端G2传输第二扫描信号。
在一些实施例中，第一信号输入端IN1与第二信号输入端IN2为同一信号端。
示例性地，如图7所示，第一输出子电路302包括第五晶体管T5和第一电容C1。
其中，第五晶体管T5的控制极与上拉节点PU耦接，第五晶体管T5的第一极与第一时钟信号端CLKA耦接，第五晶体管T5的第二极与第一信号输出端OUT1耦接。
第一电容C1的第一极与上拉节点PU耦接，第一电容C1的第二极与第一信号输出端OUT1耦接。
示例性地，如图7所示，第二输出子电路304包括第六晶体管T6和第二电容C2。
第六晶体管T6的控制极与上拉节点PU耦接，第六晶体管T6的第一极与第二时钟信号端CLKB耦接，第六晶体管T6的第二极与第二信号输出端OUT2耦接。
第二电容C2的第一极与上拉节点PU耦接，第二电容C2的第二极与第二信号输出端OUT2耦接。
需要说明的是，第一输入子电路301和第二输入子电路303的具体结构进行设定，可以采用领域内任何能够实现相应功能的电路或模块。在实际应用中，技术人员可以根据情况进行选择，本公开在此不作限定。
在一些实施例中，在像素驱动电路20包括感测子电路204的情况下，如图6所示，移位寄存器电路RS还包括：第三输出子电路305。
第三输出子电路305与第三时钟信号端CLKC、上拉节点PU和第三信号输出端OUT3耦接。
第三输出子电路305被配置为在上拉节点PU的电压的控制下，将在第三时钟信号端CLKC处接收的第三时钟信号传输至第三信号输出端OUT3，以向像素驱动电路20的第三扫描信号端G3传输第三扫描信号。
示例性地，如图7所示，第三输出子电路305包括第七晶体管T7和第三电容C3。
第七晶体管T7的控制极与上拉节点PU耦接，第七晶体管T7的第一极与第三时钟信号端CLKC耦接，第七晶体管T7的第二极与第三信号输出端OUT3耦接。
第三电容C3的第一极与上拉节点PU耦接，第三电容C3的第二极与第三信号输出端OUT3耦接。
在一些实施例中，如图6所示，移位寄存器电路RS还包括移位信号输出子电路306。
移位信号输出子电路306与第四时钟信号端CLKD、上拉节点PU和移位信号输出端CR耦接。
移位信号输出子电路306被配置为在上拉节点PU的电压的控制下，将在第四时钟信号端CLKD处接收的第四时钟信号传输至移位信号输出端CR。
示例性地，如图7所示，移位信号输出子电路306包括第八晶体管T8。
第八晶体管T8的控制极与上拉节点PU耦接，第八晶体管T8的第一极与第四时钟信号端CLKD耦接，第八晶体管T8的第二极与移位信号输出端CR耦接。
在一些实施例中，如图6所示，移位寄存器电路RS还包括：第一降噪子电路307和第二降噪子电路308。
第一降噪子电路307与第一下拉节点PD1、第一信号输出端OUT1和第一电压端V1耦接。
第二降噪子电路308与第一下拉节点PD1、第二信号输出端OUT2和第一电压端V1耦接。
第一降噪子电路307被配置为在第一下拉节点PD1的电压的控制下，将第一电压端V1的电压传输至第一信号输出端OUT1，以在移位寄存器电路RS不向像素驱动电路20的第一扫描信号端G1传输第一扫描信号的阶段对第一信号输出端OUT1进行降噪。
第二降噪子电路308被配置为在第一下拉节点PD1的电压的控制下，将第一电压端V1的电压传输至第二信号输出端OUT2，以在移位寄存器电路RS不向像素驱动电路20的第二扫描信号端G2传输第二扫描信号的阶段对第二信号输出端OUT2进行降噪。
其中，第一电压端V1被配置为传输直流低电平信号。
示例性地，如图7所示，第一降噪子电路307包括：第九晶体管T9。
第九晶体管T9的控制极与第一下拉节点PD1耦接，第九晶体管T9的第一极与第一电压端V1耦接，第九晶体管T9的第二极与第一信号输出端OUT1耦接。
示例性地，如图7所示，第二降噪子电路308包括：第十晶体管T10。
第十晶体管T10的控制极与第一下拉节点PD1耦接，第十晶体管T10的第一极与第一电压端V1耦接，第十晶体管T10的第二极与第二信号输出端OUT2耦接。
在一些实施例中，在移位寄存器电路RS包括第三输出子电路305的情况下，如图6所示，移位寄存器电路RS还包括：第三降噪子电路309。
第三降噪子电路309与第一下拉节点PD1、第三信号输出端OUT3和第一电压端V1耦接。
第三降噪子电路309被配置为在第一下拉节点PD1的电压的控制下，将第一电压端V1的电压传输至第三信号输出端OUT3，以在移位寄存器电路RS不向像素驱动电路20的第三扫描信号端G3传输第三扫描信号的阶段对第三信号输出端OUT3进行降噪。
示例性地，如图7所示，第三降噪子电路309包括第十一晶体管T11。
第十一晶体管T11的控制极与第一下拉节点PD1耦接，第十一晶体管T11的第一极与第一电压端V1耦接，第十一晶体管T11的第二极与第三信号输出端OUT3耦接。
在一些实施例中，在移位寄存器电路RS包括移位信号输出子电路306的情况下，如图6所示，移位寄存器电路RS还包括：第四降噪子电路310。
第四降噪子电路310与第一下拉节点PD1、移位信号输出端CR和第二电压端V2耦接。
第四降噪子电路310被配置为在第一下拉节点PD1的电压的控制下，将第二电压端V2的电压传输至移位信号输出端CR，以在移位寄存器电路RS不输出扫描信号的阶段对移位信号输出端CR进行降噪。
其中，第二电压端V2被配置为传输直流低电平信号。
第二电压端V2传输的直流低电平信号的电位低于第一电压端V1传输的直流低电平信号的电位。
示例性地，如图7所示，第四降噪子电路310包括：第十二晶体管T12。
第十二晶体管T12的控制极与第一下拉节点PD1耦接，第十二晶体管T12的第一极与第二电压端V2耦接，第十二晶体管T12的第二极与移位信号输出端CR耦接。
在一些实施例中，如图6所示，移位寄存器电路RS还包括：第五降噪子电路311和第六降噪子电路312。
第五降噪子电路311与第二下拉节点PD2、第一信号输出端OUT1和第一电压端V1耦接。
第六降噪子电路312与第二下拉节点PD2、第二信号输出端OUT2和第一电压端V1耦接。
第五降噪子电路311被配置为在第二下拉节点PD2的电压的控制下，将第一电压端V1的电压传输至第一信号输出端OUT1，以在移位寄存器电路RS不向像素驱动电路20的第一扫描信号端G1传输第一扫描信号的阶段对第 一信号输出端OUT1进行降噪。
第六降噪子电路312被配置为在第二下拉节点PD2的电压的控制下，将第一电压端V1的电压传输至第二信号输出端OUT2，以在移位寄存器电路RS不向像素驱动电路20的第二扫描信号端G2传输第二扫描信号的阶段对第二信号输出端OUT2进行降噪。
示例性地，如图7所示，第五降噪子电路311包括：第十三晶体管T13。
第十三晶体管T13的控制极与第二下拉节点PD2耦接，第十三晶体管T13的第一极与第一电压端V1耦接，第十三晶体管T13的第二极与第一信号输出端OUT1耦接。
示例性地，如图7所示，第六降噪子电路312包括第十四晶体管T14。
第十四晶体管T14的控制极与第二下拉节点PD2耦接，第十四晶体管T14的第一极与第一电压端V1耦接，第十四晶体管T14的第二极与第二信号输出端OUT2耦接。
在一些实施例中，在移位寄存器电路RS包括第三输出子电路305的情况下，如图6所示，移位寄存器电路RS还包括：第七降噪子电路313。
第七降噪子电路313与第二下拉节点PD2、第三信号输出端OUT3和第一电压端V1耦接。
第七降噪子电路313被配置为在第二下拉节点PD2的电压的控制下，将第一电压端V1的电压传输至第三信号输出端OUT3，以在移位寄存器电路RS不向像素驱动电路20的第三扫描信号端G3传输第三扫描信号的阶段对第三信号输出端OUT3进行降噪。
示例性地，如图7所示，第七降噪子电路313包括：第十五晶体管T15。
第十五晶体管T15的控制极与第二下拉节点PD2耦接，第十五晶体管T15的第一极与第一电压端V1耦接，第十五晶体管T15的第二极与第三信号输出端OUT3耦接。
在一些实施例中，在移位寄存器电路RS包括移位信号输出子电路306的情况下，如图6所示，移位寄存器电路RS还包括：第八降噪子电路314。
第八降噪子电路314与第二下拉节点PD2、移位信号输出端CR和第二电压端V2耦接。
第八降噪子电路314被配置为在第二下拉节点PD2的电压的控制下，将第二电压端V2的电压传输至移位信号输出端CR，以在移位寄存器电路RS不输出扫描信号的阶段对移位信号输出端CR进行降噪。
示例性地，如图7所示，第八降噪子电路314包括：第十六晶体管T16。
第十六晶体管T16的控制极与第二下拉节点PD2耦接，第十六晶体管T16的第一极与第二电压端V2耦接，第十六晶体管T16的第二极与移位信号输出端CR耦接。
在一些实施例中，在像素驱动电路20的第一扫描信号端G1和第三扫描信号端G3为同一信号端的情况下，如图8所示，移位寄存器电路RS的第一信号输出端OUT1和第三信号输出端OUT3为同一信号端。
在此情况下，移位寄存器电路RS通过控制第一输出子电路302、第一降噪子电路307和第五降噪子电路311，来控制第三信号输出端OUT3的输出信号，以向像素驱动电路20的第三扫描信号端G3传输第三扫描信号。这样，可以简化移位寄存器电路RS的电路结构，减小移位寄存器电路RS的尺寸。
需要说明的是，移位寄存器电路RS还包括其他子电路，以使移位寄存器电路RS正常工作，例如其他子电路包括用于控制第一下拉节点PD1的电压的子电路和用于控制第二下拉节点PD2的电压的子电路等。本公开的实施例未对移位寄存器电路RS中的其他子电路进行描述，可以采用领域内任何能够实现相应功能的电路或模块。在实际应用中，技术人员可以根据情况进行选择，本公开在此不作限定。
需要说明的是，本公开的实施例提供的像素驱动电路20和移位寄存器电路RS中所采用的晶体管可以为薄膜晶体管(Thin Film Transistor，TFT)、场效应晶体管(Field Effect Transistor，FET)或其他特性相同的开关器件，本公开的实施例对此并不设限。
在一些实施例中，像素驱动电路20和移位寄存器电路RS所采用的各晶体管的控制极为晶体管的栅极，第一极为晶体管的源极和漏极中一者，第二极为晶体管的源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性的，在晶体管为P型晶体管的情况下，晶体管的第一极为源极，第二极为漏极；示例性的，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
在本公开的实施例提供的电路中，第一节点N1、第二节点N2、上拉节点PU、第一下拉节点PD1和第二下拉节点PD2并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点，也就是说，这些节点是由电路图中相关电连接的汇合点等效而成的节点。
在本公开的实施例提供的像素驱动电路20和移位寄存器电路RS中，各 个子电路的具体实现方式不局限于上面描述的方式，其可以为任意使用的实现方式，例如为本领域技术人员熟知的常规连接方式，只需保证实现相应功能即可。上述示例并不能限制本公开的保护范围。在实际应用中，技术人员可以根据情况选择使用或不适用上述各电路中的一个或多个，基于前述各电路的各种组合变型均不脱离本公开的原理，对此不再赘述。
以下，以上述各个晶体管均为N型晶体管为例，对像素驱动电路20和应用于上述的像素驱动电路20的移位寄存器电路RS中的各个晶体管在不同的阶段的工作情况进行详细地举例说明。
其中，第一电压端V1的电压为直流低电平电压，第二电压端V2的电压为直流低电平电压。
需要说明的是，为了描述方便，对于像素驱动电路20，在控制信号端DB处接收的控制信号和在感测信号端SE处接收的感测信号均以直流低电平信号Vref表示(如图9所示)。
为了描述方便，移位寄存器电路RS各工作阶段(如图10所示的Q1～Q5)，与第一下拉节点PD1耦接的各降噪子电路的工作，与第二下拉节点PD2耦接的各降噪子电路的不工作的情况为例进行说明。
并且，以第一信号输入端IN1与第二信号输入端IN2为同一信号端进行说明，即，第一信号输入端IN1与第二信号输入端IN2传输的信号时序相同。
对于移位寄存器电路RS，在如图10所示的一图像帧(1F)中的第一阶段(Q1)，在像素驱动电路20接收到第一扫描信号之前，参考图6，第一输入子电路301将在第一信号输入端IN1处接收的信号传输至上拉节点PU，对上拉节点PU充电。
示例性地，在像素驱动电路20接收到第一扫描信号之前，如图7所示，第一输入子电路301将在第一信号输入端IN1处接收的高电平信号传输至上拉节点PU，对上拉节点PU充电。同时，对第一电容C1和第二电容C2充电。第五晶体管T5将低电平的第一时钟信号传输至第一信号输出端OUT1，第六晶体管T6将低电平的第二时钟信号传输至第二信号输出端OUT2。
在移位寄存器电路RS包括第三输出子电路305的情况下，在上拉节点PU充电的同时，还对第三电容C3充电。此时，第七晶体管T7将低电平的第三时钟信号传输至第三信号输出端OUT3。
对于移位寄存器电路RS，在如图10所示的第二阶段(Q2)，在上拉节点PU的电压的控制下，第一输出子电路302开启，将在第一时钟信号端CLKA处接收的第一时钟信号传输至第一信号输出端OUT1，以向像素驱动电路20 的第一扫描信号端G1传输第一扫描信号。
在移位寄存器电路RS包括第三输出子电路305的情况下，在上拉节点PU的高电平的电压的控制下，第三输出子电路305开启，将在第三时钟信号端CLKC处接收的第三时钟信号传输至第三信号输出端OUT3，以向像素驱动电路20的第三扫描信号端G3传输第三扫描信号。
在移位寄存器电路RS包括移位信号输出子电路306的情况下，在上拉节点PU的高电平的电压的控制下，移位信号输出子电路306开启，将在第四时钟信号端CLKD处接收的第四时钟信号传输至移位信号输出端CR。
示例性地，如图7所示，上拉节点PU的电压为高电平，并且，由于第一电容C1和第二电容C2的自举作用，上拉节点PU的电位被进一步抬高，在上拉节点PU的高电平电压的控制下，第五晶体管T5导通，将在第一时钟信号端CLKA处接收的高电平的第一时钟信号传输至第一信号输出端OUT1。
在移位寄存器电路RS包括第三输出子电路305的情况下，第三电容C3将存储的电荷释放至上拉节点PU，由于自举作用将上拉节点PU的电位抬高，第七晶体管T7导通，将高电平的第三时钟信号传输至第三信号输出端OUT3。
在移位寄存器电路RS包括移位信号输出子电路306的情况下，在上拉节点PU的高电平的电压的控制下，第八晶体管T8导通，将在第四时钟信号端CLKD处接收的高电平的第四时钟信号传输至移位信号输出端CR。
需要说明的是，第一时钟信号端CLKA和第三时钟信号端CLKC处接收的信号的波形相同，但是不代表两者为同一信号。
另外，第二输出子电路304中的第六晶体管T6导通，将低电平的第二时钟信号传输至第二信号输出端OUT2，以向像素驱动电路20的第二扫描信号端G2传输低电平的第二扫描信号。
在此情况下，对于像素驱动电路20，在如图9所示的一图像帧(1F)中的第一阶段(P1)，参考图2，在第一扫描信号端G1处接收的第一扫描信号的控制下，数据信号端DATA与第一节点N1的连接，数据写入子电路201将在数据信号端DATA处接收的数据信号写入第一节点N1。
在像素驱动电路20包括感测子电路204的情况下，在第三扫描信号端G3处接收的第三扫描信号的控制下，感测子电路204将在感测信号端SE处接收的感测信号传输至第二节点N2。
示例性地，在图9中的第一阶段(P1)的第一时段(t1)，如图4所示，在第一扫描信号端G1处接收的第一扫描信号为高电平信号的情况下，第三晶体管T3导通，将在数据信号端DATA处接收的低电平的数据信号传输至第一节点 N1，对第一节点N1复位。
在第三扫描信号端G3处接收的第三扫描信号为高电平信号的情况下，第四晶体管T4导通，将在感测信号端SE处接收的低电平的感测信号传输至第二节点N2，对第二节点N2复位。
在图9中的第一阶段(P1)的第二时段(t2)，第一扫描信号仍为高电平信号，第三晶体管T3处于导通状态，将在数据信号端DATA处接收的高电平的数据信号写入第一节点N1，并对存储电容Cst充电。
对于移位寄存器电路RS，在如图10所示的第三阶段(Q3)，参考图6，在第一下拉节点PD1的电压的控制下，第一降噪子电路307将第一电压端V1的电压传输至第一信号输出端OUT1，对第一信号输出端OUT1进行降噪。第二降噪子电路308将第一电压端V1的电压传输至第二信号输出端OUT2，对第二信号输出端OUT2进行降噪。
示例性地，如图7所示，在第一下拉节点PD1的高电平电压的控制下，第九晶体管T9开启，将第一电压端V1的低电平电压传输至第一信号输出端OUT1，此时，第一信号输出端OUT1的信号为低电平信号。在第一下拉节点PD1的高电平电压的控制下，第十晶体管T10开启，将第一电压端V1的低电平电压传输至第二信号输出端OUT2，此时，第二信号输出端OUT2的信号为低电平信号。
在移位寄存器电路RS包括第三输出子电路305的情况下，第三降噪子电路309将第一电压端V1的电压传输至第三信号输出端OUT3，对第三信号输出端OUT3进行降噪。
示例性地，如图7所示，在第一下拉节点PD1的高电平电压的控制下，第十一晶体管T11开启，将第一电压端V1的低电平电压传输至第三信号输出端OUT3，此时，第三信号输出端OUT3的信号为低电平信号。
在移位寄存器电路RS包括移位信号输出子电路306的情况下，移位信号输出子电路306将第二电压端V2的电压传输至移位信号输出端CR，对移位信号输出端CR进行降噪。
示例性地，如图7所示，在第一下拉节点PD1的高电平电压的控制下，第十二晶体管T12开启，将第二电压端V2的低电平电压传输至移位信号输出端CR，此时，移位信号输出端CR的电位为低电平，对移位信号输出端CR降噪。
需要说明的是，与第一下拉节点PD1耦接的各降噪子电路，和与第二下拉节点PD2耦接的各降噪子电路，以一定的周期交替工作。本领域工作人员 可以根据实际情况下，对周期时长进行设计，在此不作限定。其中，在如图10所示的一图像帧内，第一下拉节点PD1的电位非固定低电平，第二下拉节点PD2的电位为固定低电平，即，与第一下拉节点PD1耦接的各降噪子电路工作，与第二下拉节点PD2耦接的各降噪子电路不工作。
此外，在一些实施例中，在与第一下拉节点PD1耦接的各降噪子电路不工作，与第二下拉节点PD2耦接的各降噪子电路工作的情况下，参考图6，在第二下拉节点PD2的电压的控制下，第一降噪子电路307将第一电压端V1的电压传输至第一信号输出端OUT1，对第一信号输出端OUT1进行降噪。第二降噪子电路308将第一电压端V1的电压传输至第二信号输出端OUT2，对第二信号输出端OUT2进行降噪。
示例性地，如图7所示，在第二下拉节点PD2的高电平电压的控制下，第十三晶体管T13开启，将第一电压端V1的低电平电压传输至第一信号输出端OUT1，此时，第一信号输出端OUT1的信号为低电平信号。在第二下拉节点PD2的高电平电压的控制下，第十四晶体管T14开启，将第一电压端V1的低电平电压传输至第二信号输出端OUT2，此时，第二信号输出端OUT2的信号为低电平信号。
在移位寄存器电路RS包括第三输出子电路305的情况下，第三降噪子电路309将第一电压端V1的电压传输至第三信号输出端OUT3，对第三信号输出端OUT3进行降噪。
示例性地，如图7所示，在第二下拉节点PD2的高电平电压的控制下，第十五晶体管T15开启，将第一电压端V1的低电平电压传输至第三信号输出端OUT3，此时，第三信号输出端OUT3的信号为低电平信号。
在移位寄存器电路RS包括移位信号输出子电路306的情况下，移位信号输出子电路306将第二电压端V2的电压传输至移位信号输出端CR，对移位信号输出端CR进行降噪。
示例性地，如图7所示，在第二下拉节点PD2的高电平电压的控制下，第十六晶体管T16开启，将第二电压端V2的低电平电压传输至移位信号输出端CR，此时，移位信号输出端CR的电位为低电平，对移位信号输出端CR降噪。
因此，在移位寄存器电路RS工作的第三阶段(Q3)，第一信号输出端OUT1、第二信号输出端OUT2、第三信号输出端OUT3和移位信号输出端CR均传输低电平信号，因此，像素驱动电路20的第一扫描信号端G1、第二扫描信号端G2和第三扫描信号端G3均接收低电平信号。
在此情况下，对于像素驱动电路20，在如图9所示的第二阶段(P2)，在第一扫描信号端G1处接收的第一扫描信号的控制下，数据信号端DATA与第一节点N1的连接断开，在第三扫描信号端G3处接收的第三扫描信号的控制下，感测子电路204断开。
驱动子电路202在第一节点N1的电压的控制下开启，并在第一电源电压信号端VDD处接收的第一电源电压信号的控制下，驱动子电路202输出驱动电流，以驱动与第二节点N2耦接的发光器件L发光。
示例性地，如图4所示，在第一扫描信号端G1处接收的低电平的第一扫描信号的控制下，第三晶体管T3截止，在第三扫描信号端G3处接收的低电平的第三扫描信号的控制下，第四晶体管T4截止。
在第一节点N1的高电平的电压的控制下，第二晶体管T2导通，第一电源电压信号端VDD的第一电源电压信号传输至第二节点N2，使得第二节点N2的电位上升。并且，由于存储电容Cst的自举作用，存储电容Cst的第一极和第二极的电压差不会发生突变，因此，第一节点N1的电位进一步抬升，使得第二晶体管T2持续导通。在此情况下，在第一电源电压信号端VDD的第一电源电压信号的控制下，第二晶体管T2输出驱动电流，驱动发光器件L工作(即正常发光)。
在像素驱动电路20驱动发光器件工作预设时间之后，对于移位寄存器电路RS，在如图10所示的第四阶段(Q4)中的第一时段(q1)，第二输入子电路303将在第二信号输入端IN2处接收的信号传输至上拉节点PU。
示例性地，第二输入子电路303将在第二信号输入端IN2处接收的高电平信号传输至上拉节点PU，以使上拉节点PU的电位为高电平电位。
在第四阶段(Q4)中的第二时段(q2)，第二输出子电路304在上拉节点PU的电压的控制下开启，将在第二时钟信号端CLKB处接收的第二时钟信号传输至第二信号输出端OUT2，以向像素驱动电路20的第二扫描信号端G2传输第二扫描信号。示例性地，在上拉节点PU的高电平电压的控制下，第六晶体管T6导通，将高电平的第二时钟信号传输至第二信号输出端OUT2，以向像素驱动电路20的第二扫描信号端G2传输高电平的第二扫描信号。
在此情况下，对于像素驱动电路20，在如图9所示的第三阶段(P3)，时间控制子电路202在第二扫描信号端G2处接收的第二扫描信号的控制下开启，将在控制信号端DB处接收的控制信号传输至第一节点N1。
在第一节点N1的电压的控制下，驱动子电路202断开，使得发光器件L中无驱动电流流过，发光器件L停止工作，缩短了发光器件L工作时长，增 加了动态画面响应时间，避免在动态画面切换过程中出现拖影。
示例性地，如图4所示，在第二扫描信号端G2处接收的高电平的第二扫描信号的控制下，第一晶体管T1导通，将在控制信号端DB处接收的低电平的控制信号传输至第一节点N1，此时，第一节点N1为低电平电压。
在第一节点N1的低电平电压的控制下，第二晶体管T2截止，第二晶体管T2停止驱动发光器件L工作，从而缩短了发光器件L的工作时长。
这样，在图像帧切换的过程中，在下一图像帧到来之前，发光器件L停止工作，缩短了发光器件L的发光时长，即发光器件L停止发光，显示装置可以在一段时间内呈现黑画面，延长了动态画面响应时间，从而避免由于发光器件L持续工作而导致在图像帧切换的过程中出现动态拖影，提高了显示效果。
此外，在上拉节点PU的高电平电压的控制下，移位信号输出子电路306中的第八晶体管T8导通，将在第四时钟信号端CLKD处接收的高电平的第四时钟信号传输至移位信号输出端CR。并且，在上拉节点PU的高电平电压的控制下，第一输出子电路302中的第五晶体管T5导通，将在第一时钟信号端CLKA处接收的低电平的第一时钟信号传输至第一信号输出端OUT1，第三输出子电路305中的第七晶体管T7导通，将第三时钟信号端CLKC处接收的低电平的第三时钟信号在第三信号输出端OUT3。在此情况下，像素驱动电路20的第一扫描信号端G1和第三扫描信号端G3均传输低电平信号，数据写入子电路201中的第三晶体管T3和感测子电路204中的第四晶体管T4均截止。
在如图10所示的第五阶段(Q5)，第二输入子电路303将在第二信号输入端IN2处接收的高电平信号传输至上拉节点PU，以使上拉节点PU的电位为高电平电位。
在第四阶段(Q4)中的第三时段(q3)，在第一下拉节点PD1为高电平电位的控制下，移位寄存器电路RS中的与第一下拉节点PD1耦接的第一降噪子电路307、第二降噪子电路308、第三降噪子电路309和第四降噪子电路310工作，分别对第一信号输出端OUT1、第二信号输出端OUT2、第三信号输出端OUT3和移位信号输出端CR降噪，具体工作方式与在第三阶段(Q3)的工作方式类似，在此不再赘述。
在如图10所示的第五阶段(Q5)中的第四时段(q4)，第二输入子电路303将在第二信号输入端IN2处接收的高电平信号传输至上拉节点PU，以使上拉节点PU的电位为高电平电位。
在第五阶段(Q5)中的第五时段(q5)，在上拉节点PU的电压的控制下，第 一输出子电路302开启，将在第一时钟信号端CLKA处接收的第一时钟信号传输至第一信号输出端OUT1，以向像素驱动电路20的第一扫描信号端G1传输第一扫描信号。
例如，在上拉节点PU的高电平电压的控制下，第五晶体管T5导通，将在第一时钟信号端CLKA处接收的高电平的第一时钟信号传输至第一信号输出端OUT1。
在移位寄存器电路RS包括第三输出子电路305的情况下，在上拉节点PU的高电平的电压的控制下，第三输出子电路305开启，将在第三时钟信号端CLKC处接收的第三时钟信号传输至第三信号输出端OUT3，以向像素驱动电路20的第三扫描信号端G3传输第三扫描信号。
示例性地，在上拉节点PU的高电平电压的控制下，第七晶体管T7导通，将在第三时钟信号端CLKC处接收的高电平的第三时钟信号传输至第三信号输出端OUT3。
在此情况下，对于像素驱动电路20，在如图9所示的第四阶段(P4)，参考图2，在第一扫描信号端G1处接收的第一扫描信号的控制下，数据写入子电路201将在数据信号端DATA处接收的数据信号写入第一节点N1。
示例性地，如图4所示，在第三扫描信号端G3处接收的高电平的第三扫描信号的控制下，第三晶体管T3导通，将在数据信号端DATA处接收的高电平的数据信号写入第一节点N1，第一节点N1的电位逐渐升高，相应的，第二节点N2的电位会随着第一节点N1的电位的同步变化。
在第三扫描信号端G3处接收的第三扫描信号的控制下，感测子电路204开启，将第二节点N2的电压传输至感测信号端SE。示例性地，在第三扫描信号端G3处接收的高电平的第三扫描信号的控制下，第四晶体管T4导通，将第二节点N2的电压传输至感测信号端SE。
在此情况下，与感测信号端SE耦接的感测信号线，将第二节点N2的电压传输至外部补偿电路，外部补偿电路根据第二节点N2的电压，调整在后续显示过程中数据信号端DATA处接收的数据信号。这样，可以通过外部补偿的方式，对驱动子电路202中的第二晶体管T2的阈值电压进行补偿，避免了驱动子电路202向发光器件L提供的驱动电流的差异，提高了显示装置的亮度均一性。
此外，在上拉节点PU的高电平电压的控制下，移位信号输出子电路306中的第八晶体管T8导通，将在第四时钟信号端CLKD处接收的高电平的第四时钟信号传输至移位信号输出端CR。
在第五阶段(Q5)中的第六时段(q6)，在第一下拉节点PD1为高电平电位的控制下，移位寄存器电路RS中的与第一下拉节点PD1耦接的第一降噪子电路307、第二降噪子电路308、第三降噪子电路309和第四降噪子电路310工作，分别对第一信号输出端OUT1、第二信号输出端OUT2、第三信号输出端OUT3和移位信号输出端CR降噪，具体工作方式与在第三阶段(Q3)的工作方式类似，在此不再赘述。
本公开的实施例提供一种栅极驱动电路10，如图11所示，包括多个级联的上述任一实施例中的移位寄存器电路RS。
示例性地，如图11所示，第1级移位寄存器电路RS(1)的第一信号输入端IN1与起始信号线STU耦接。起始信号线STU被配置为传输起始信号，该栅极驱动电路10的第1级移位寄存器电路RS(1)在接收到上述起始信号后开始工作。除了第1级移位寄存器电路RS(1)以外，每一级移位寄存器电路的第一信号输入端IN1与其上一级移位寄存器电路的移位信号输出端CR耦接。
除了最后一级移位寄存器电路RS(N)以外，每一级移位寄存器单元还与其下一级移位寄存器电路的移位信号输出端CR的复位信号端耦接(图中未示出)，以进行复位。
需要说明的是，为了方便描述，图11仅示出了移位寄存器电路RS的第一信号输入端IN1和第二信号输入端IN2为同一信号端的情况。在移位寄存器电路RS的第一信号输入端IN1和第二信号输入端IN2为不同信号端的情况下，第二信号输入端IN2可以与一根信号线耦接(图中未示出)，该信号线传输至第二信号输入端IN2的信号可以使第二输入子电路303实现相应的功能。需要说明的是，任意相邻的两个级联的移位寄存器电路RS耦接不同的第一时钟信号线、第二时钟信号线、第三时钟信号线和第四时钟信号线。
例如，奇数级移位寄存器电路中的第一时钟信号端CLKA与第一个第一时钟信号线CLKA1耦接、第二时钟信号端CLKB与第一个第二时钟信号线CLKB1耦接、第三时钟信号端CLKC与第一个第三时钟信号线CLKC1耦接和第四时钟信号端CLKD与第一个第四时钟信号线CLKD1耦接，偶数级移位寄存器电路中的第一时钟信号端CLKA与第二个第一时钟信号线CLKA2耦接、第二时钟信号端CLKB与第二个第二时钟信号线CLKB2耦接、第三时钟信号端CLKC与第二个第三时钟信号线CLKC2耦接和第四时钟信号端CLKD与第二个第四时钟信号线CLKD2耦接。
其中，第一个第一时钟信号线CLKA1传输的信号与第二个第一时钟信号线CLKA2传输的信号、第一个第二时钟信号线CLKB1传输的信号与第二个 第二时钟信号线CLKB2传输的信号、第一个第三时钟信号线CLKC1传输的信号与第二个第三时钟信号线CLKC2传输的信号、第一个第四时钟信号线CLKD1传输的信号与第二个第四时钟信号线CLKD2传输的信号，分别具有一定的相位差。
需要说明的是，为了描述方便，本公开的实施例将一些信号端、一些信号端传输的信号、以及一些信号端所耦接的信号线均采用相同符号表示，但各自的属性不相同。
如图1所示，显示面板100中设置有中多条第一扫描信号线GL1(1)～GL1(n)、多条第二扫描信号线GL2(1)～GL2(n)、多条第三扫描信号线GL3(1)～GL3(n)和多条数据线DL(1)～DL(m)。
例如，第一扫描信号线GL1、第二扫描信号线GL2和第三扫描信号线GL3沿水平方向X延伸，数据线DL沿竖直方向Y延伸。
在此情况下，一个移位寄存器电路RS与一条第一扫描信号线GL1耦接，以向第一扫描信号线GL1传输第一扫描信号，与一条第二扫描信号线GL2耦接，以向第二扫描信号线GL2传输第二扫描信号，与一条第三扫描信号线GL3耦接，以向第三扫描信号线GL3传输第三扫描信号。
需要说明的是，对于栅极驱动电路10而言，图1仅是示意的，以采用单侧驱动(即在显示面板100的周边区S的单侧设置栅极驱动电路10，从单侧逐行依次驱动第一扫描信号线GL1和第二扫描信号线GL2)为例进行说明的。在另一些实施例中，可以采用双侧同时驱动(即在显示面板100的周边区S中沿第一扫描信号线GL1和第二扫描信号线GL2的延伸方向上的两个侧边分别设置栅极驱动电路10，通过两个栅极驱动电路10同时从两侧逐行依次驱动第一扫描信号线GL1和第二扫描信号线GL2)。在另一些实施例中，显示面板100可以采用双侧交叉驱动(即在显示面板100的周边区S中沿第一扫描信号线GL1和第二扫描信号线GL2的延伸方向上的两个侧边分别设置栅极驱动电路10，通过两个栅极驱动电路10交替从两侧，逐行依次驱动第一扫描信号线GL1和第二扫描信号线GL2)。
需要说明的是，本公开的实施例是以单侧驱动为例，对实施例中提供的栅极驱动电路10进行说明的。
另外，在栅极驱动电路10中，对于移位寄存器电路RS中各时钟信号端而言，可以采用多时钟信号模式。例如可以是2时钟信号模型、4时钟信号模型、6时钟信号模型、8时钟信号模型或者10时钟信号模型等，本公开对此不做限定。本公开的实施例是以2时钟信号模型为例，对实施例中提供的栅 极驱动电路10进行说明的。
本公开的实施例提供一种显示装置。该显示装置包括多个如上述任一实施例中的像素驱动电路20和如上述任一实施例中的栅极驱动电路10。
其中，栅极驱动电路10与各像素驱动电路20耦接。
在像素驱动电路20包括数据写入子电路201、时间控制子电路203和感测子电路204的情况下，栅极驱动电路10向像素驱动电路20传输第一扫描信号、第二扫描信号和第三扫描信号。
示例性地，该显示装置可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
本公开的实施例提供一种如上述任一实施例中的像素驱动电路20的驱动方法，包括：
参考图2，数据写入子电路201在第一扫描信号端G1处接收的第一扫描信号的控制下，将在数据信号端DATA处接收的数据信号写入第一节点N1。
驱动子电路202在第一节点N1的电压和在第一电源电压信号端VDD处接收的第一电源电压信号的控制下，驱动与第二节点N2耦接的发光器件L工作。
时间控制子电路203在发光器件L工作预设时间之后，在第二扫描信号端G2处接收的第二扫描信号的控制下，将在控制信号端DB处接收的控制信号传输至第一节点N1，使驱动子电路202断开，以控制发光器件L停止工作。
在一些实施例中，参考图2，在像素驱动电路20包括感测子电路204的情况下，像素驱动电路20的驱动方法还包括：
在数据写入子电路301将数据信号写入第一节点N1的同时，感测子电路204在第三扫描信号端G3处接收的第三扫描信号的控制下，将在感测信号端DB处接收的感测信号传输至第二节点N2。
上述的像素驱动电路20的驱动方法具有与上述的像素驱动电路20相同 的有益效果，因此不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (22)

  1. 一种像素驱动电路，包括：
    数据写入子电路，至少与第一扫描信号端、数据信号端和第一节点耦接；所述数据写入子电路被配置为，在所述第一扫描信号端处接收的第一扫描信号的控制下，将在所述数据信号端处接收的数据信号写入所述第一节点；
    驱动子电路，与所述第一节点、第二节点和第一电源电压信号端耦接；所述驱动子电路被配置为，在所述第一节点的电压和在所述第一电源电压信号端处接收的第一电源电压信号的控制下，驱动与所述第二节点耦接的发光器件工作；
    时间控制子电路，与所述第一节点、第二扫描信号端和控制信号端耦接；所述时间控制子电路被配置为，在所述发光器件工作预设时间之后，在所述第二扫描信号端处接收的第二扫描信号的控制下，将在所述控制信号端处接收的控制信号传输至所述第一节点，使所述驱动子电路断开，以控制所述发光器件停止工作。
  2. 根据权利要求1所述的像素驱动电路，其中，所述时间控制子电路包括：
    第一晶体管；所述第一晶体管的控制极与所述第二扫描信号端耦接，所述第一晶体管的第一极与所述控制信号端耦接，所述第一晶体管的第二极与所述第一节点耦接。
  3. 根据权利要求1或2所述的像素驱动电路，其中，所述驱动子电路包括：
    第二晶体管；所述第二晶体管的控制极与所述第一节点耦接，所述第二晶体管的第一极与所述第二节点耦接，所述第二晶体管的第二极与所述第一电源电压信号端耦接。
  4. 根据权利要求1～3中任一项所述的像素驱动电路，其中，所述数据写入子电路还与所述第二节点耦接；
    所述数据写入子电路包括：
    第三晶体管；所述第三晶体管的控制极与所述第一扫描信号端耦接，所述第三晶体管的第一极与所述数据信号端耦接，所述第三晶体管的第二极与所述第一节点耦接；
    存储电容；所述存储电容的第一极与所述第一节点耦接，所述存储电容的第二极与所述第二节点耦接。
  5. 根据权利要求1～4中任一项所述的像素驱动电路，还包括：
    感测子电路，与第三扫描信号端、所述第二节点和感测信号端耦接；所述感测子电路被配置为，在所述第三扫描信号端处接收的第三扫描信号的控制下，将在所述感测信号端处接收的感测信号传输至所述第二节点。
  6. 根据权利要求5所述的像素驱动电路，其中，所述感测子电路包括：
    第四晶体管；所述第四晶体管的控制极与所述第三扫描信号端耦接，所述第四晶体管的第一极与所述感测信号端耦接，所述第四晶体管的第二极与所述第二节点耦接。
  7. 根据权利要求5或6所述的像素驱动电路，其中，所述控制信号端与所述感测信号端为同一信号端。
  8. 根据权利要求5～7中任一项所述的像素驱动电路，其中，所述第一扫描信号端与所述第三扫描信号端为同一信号端。
  9. 一种移位寄存器电路，应用于如权利要求1～8中任一项所述的像素驱动电路；所述移位寄存器电路包括：
    第一输入子电路，至少与上拉节点和第一信号输入端耦接；所述第一输入子电路被配置为，在所述像素驱动电路接收到第一扫描信号之前，将在所述第一信号输入端处接收的信号传输至所述上拉节点；
    第一输出子电路，与第一时钟信号端、所述上拉节点和第一信号输出端耦接；所述第一输出子电路被配置为，在所述上拉节点的电压的控制下，将在所述第一时钟信号端处接收的第一时钟信号传输至所述第一信号输出端，以向所述像素驱动电路的第一扫描信号端传输第一扫描信号；
    第二输入子电路，至少与所述上拉节点和第二信号输入端耦接；所述第二输入子电路被配置为，在所述像素驱动电路驱动发光器件工作预设时间之后，将在所述第二信号输入端处接收的信号传输至所述上拉节点；
    第二输出子电路，与第二时钟信号端、所述上拉节点和第二信号输出端耦接；所述第二输出子电路被配置为，在所述上拉节点的电压的控制下，将在所述第二时钟信号端处接收的第二时钟信号传输至所述第二信号输出端，以在所述像素驱动电路驱动发光器件工作预设时间之后，向所述像素驱动电路的第二扫描信号端传输第二扫描信号。
  10. 根据权利要求9所述的移位寄存器电路，其中，所述第一输出子电路包括：
    第五晶体管；所述第五晶体管的控制极与所述上拉节点耦接，所述第五晶体管的第一极与所述第一时钟信号端耦接，所述第五晶体管的第二极与所述第一信号输出端耦接；
    第一电容；所述第一电容的第一极与所述上拉节点耦接，所述第一电容的第二极与所述第一信号输出端耦接；
    所述第二输出子电路包括：
    第六晶体管；所述第六晶体管的控制极与所述上拉节点耦接，所述第六晶体管的第一极与所述第二时钟信号端耦接，所述第六晶体管的第二极与所述第二信号输出端耦接；
    第二电容；所述第二电容的第一极与所述上拉节点耦接，所述第二电容的第二极与所述第二信号输出端耦接。
  11. 根据权利要求9或10所述的移位寄存器电路，其中，在所述像素驱动电路包括感测子电路的情况下，所述移位寄存器电路还包括：
    第三输出子电路，与第三时钟信号端、所述上拉节点和第三信号输出端耦接；所述第三输出子电路被配置为，在所述上拉节点的电压的控制下，将在所述第三时钟信号端处接收的第三时钟信号传输至所述第三信号输出端，以向所述像素驱动电路的第三扫描信号端传输第三扫描信号。
  12. 根据权利要求11所述的移位寄存器电路，其中，所述第三输出子电路包括：
    第七晶体管；所述第七晶体管的控制极与所述上拉节点耦接，所述第七晶体管的第一极与所述第三时钟信号端耦接，所述第七晶体管的第二极与所述第三信号输出端耦接；
    第三电容；所述第三电容的第一极与所述上拉节点耦接，所述第三电容的第二极与所述第三信号输出端耦接。
  13. 根据权利要求9～12中任一项所述的移位寄存器电路，还包括：
    移位信号输出子电路，与第四时钟信号端、所述上拉节点和移位信号输出端耦接；所述移位信号输出子电路被配置为，在所述上拉节点的电压的控制下，将在所述第四时钟信号端处接收的第四时钟信号传输至所述移位信号输出端。
  14. 根据权利要求13所述的移位寄存器电路，其中，所述移位信号输出子电路包括：
    第八晶体管；所述第八晶体管的控制极与所述上拉节点耦接，所述第八晶体管的第一极与所述第四时钟信号端耦接，所述第八晶体管的第二极与所述移位信号输出端耦接。
  15. 根据权利要求9～14中任一项所述的移位寄存器电路，还包括：
    第一降噪子电路，与第一下拉节点、所述第一信号输出端和第一电压端 耦接；所述第一降噪子电路被配置为，在所述第一下拉节点的电压的控制下，将所述第一电压端的电压传输至所述第一信号输出端；
    第二降噪子电路，与所述第一下拉节点、所述第二信号输出端和所述第一电压端耦接；所述第二降噪子电路被配置为，在所述第一下拉节点的电压的控制下，将所述第一电压端的电压传输至所述第二信号输出端；
    在所述移位寄存器电路包括第三输出子电路的情况下，所述移位寄存器电路还包括：
    第三降噪子电路，与所述第一下拉节点、第三信号输出端和第一电压端耦接；所述第三降噪子电路被配置为，在所述第一下拉节点的电压的控制下，将所述第一电压端的电压传输至所述第三信号输出端；
    在所述移位寄存器电路包括移位信号输出子电路的情况下，所述移位寄存器电路还包括：
    第四降噪子电路，与所述第一下拉节点、移位信号输出端和第二电压端耦接；所述第四降噪子电路被配置为，在所述第一下拉节点的电压的控制下，将所述第二电压端的电压传输至所述移位信号输出端。
  16. 根据权利要求15所述的移位寄存器电路，其中，
    所述第一降噪子电路包括：
    第九晶体管；所述第九晶体管的控制极与所述第一下拉节点耦接，所述第九晶体管的第一极与所述第三电压端耦接，所述第九晶体管的第二极与所述第一信号输出端耦接；
    所述第二降噪子电路包括：
    第十晶体管；所述第十晶体管的控制极与所述第一下拉节点耦接，所述第十晶体管的第一极与所述第三电压端耦接，所述第十晶体管的第二极与所述第二信号输出端耦接；
    在所述移位寄存器电路包括第三降噪子电路的情况下，所述第三降噪子电路包括：
    第十一晶体管；所述第十一晶体管的控制极与所述第一下拉节点耦接，所述第十一晶体管的第一极与所述第一电压端耦接，所述第十一晶体管的第二极与所述第三信号输出端耦接；
    在所述移位寄存器电路包括第四降噪子电路的情况下，所述第四降噪子电路包括：
    第十二晶体管；所述第十二晶体管的控制极与所述第一下拉节点耦接，所述第十二晶体管的第一极与所述第二电压端耦接，所述第十二晶体管的第 二极与所述移位信号输出端耦接。
  17. 根据权利要求9～16中任一项所述的移位寄存器电路，还包括：
    第五降噪子电路，与第二下拉节点、所述第一信号输出端和第一电压端耦接；所述第五降噪子电路被配置为，在所述第二下拉节点的电压的控制下，将所述第一电压端的电压传输至所述第一信号输出端；
    第六降噪子电路，与所述第二下拉节点、所述第二信号输出端和所述第三电压端耦接；所述第六降噪子电路被配置为，在所述第二下拉节点的电压的控制下，将所述第三电压端的电压传输至所述第二信号输出端；
    在所述移位寄存器电路包括第三输出子电路的情况下，所述移位寄存器电路还包括：
    第七降噪子电路，与所述第二下拉节点、第三信号输出端和所述第一电压端耦接；所述第七降噪子电路被配置为，在所述第二下拉节点的电压的控制下，将所述第一电压端的电压传输至所述第三信号输出端；
    在所述移位寄存器电路包括移位信号输出子电路的情况下，所述移位寄存器电路还包括：
    第八降噪子电路，与所述第二下拉节点、移位信号输出端和第二电压端耦接；所述第八降噪子电路被配置为，在所述第二下拉节点的电压的控制下，将所述第二电压端的电压传输至所述移位信号输出端。
  18. 根据权利要求17所述的移位寄存器电路，其中，
    所述第五降噪子电路包括：
    第十三晶体管，所述第十三晶体管的控制极与所述第二下拉节点耦接，所述第十三晶体管的第一极与所述第一电压端耦接，所述第十三晶体管的第二极与所述第一信号输出端耦接；
    所述第六降噪子电路包括：
    第十四晶体管，所述第十四晶体管的控制极与所述第二下拉节点耦接，所述第十四晶体管的第一极与所述第三电压端耦接，所述第十四晶体管的第二极与所述第二信号输出端耦接；
    在所述移位寄存器电路包括第七降噪子电路的情况下，所述第七降噪子电路包括：
    第十五晶体管，所述第十五晶体管的控制极与所述第二下拉节点耦接，所述第十五晶体管的第一极与所述第一电压端耦接，所述第十五晶体管的第二极与所述第三信号输出端耦接；
    在所述移位寄存器电路包括第八降噪子电路的情况下，所述第八降噪子 电路包括：
    第十六晶体管，所述第十六晶体管的控制极与所述第二下拉节点耦接，所述第十六晶体管的第一极与所述第二电压端耦接，所述第十六晶体管的第二极与所述移位信号输出端耦接。
  19. 一种栅极驱动电路，包括：多个级联的如权利要求9～18中任一项所述的移位寄存器电路。
  20. 一种显示装置，包括：
    多个如权利要求1～8中任一项所述的像素驱动电路；
    多个发光器件，一个像素驱动电路与至少一个发光器件耦接；
    如权利要求19所述的栅极驱动电路，所述栅极驱动电路与各所述像素驱动电路耦接。
  21. 一种如权利要求1～8中任一项所述的像素驱动电路的驱动方法，包括：
    数据写入子电路在第一扫描信号端处接收的第一扫描信号的控制下，将在数据信号端处接收的数据信号写入第一节点；
    驱动子电路在第一节点的电压和第一电源电压信号端处接收的第一电源电压信号的控制下，驱动与第二节点耦接的发光器件工作；
    时间控制子电路在所述发光器件工作预设时间之后，在第二扫描信号端处接收的第二扫描信号的控制下，将在控制信号端处接收的控制信号传输至所述第一节点，使所述驱动子电路断开，以控制所述发光器件停止工作。
  22. 根据权利要求21所述的像素驱动电路的驱动方法，其中，在所述像素驱动电路包括感测子电路的情况下，所述驱动方法还包括：
    在所述数据写入子电路将所述数据信号写入所述第一节点的同时，所述感测子电路在第三扫描信号端处接收的第三扫描信号的控制下，将在感测信号端处接收的感测信号传输至所述第二节点。
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