WO2022193281A1 - 移位寄存器单元及驱动方法、栅极驱动电路、显示装置 - Google Patents

移位寄存器单元及驱动方法、栅极驱动电路、显示装置 Download PDF

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Publication number
WO2022193281A1
WO2022193281A1 PCT/CN2021/081786 CN2021081786W WO2022193281A1 WO 2022193281 A1 WO2022193281 A1 WO 2022193281A1 CN 2021081786 W CN2021081786 W CN 2021081786W WO 2022193281 A1 WO2022193281 A1 WO 2022193281A1
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Prior art keywords
transistor
node
pole
clock signal
terminal
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PCT/CN2021/081786
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English (en)
French (fr)
Inventor
商广良
郑灿
卢江楠
钱昱翰
王丽
刘利宾
史世明
王大巍
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180000518.3A priority Critical patent/CN115380323A/zh
Priority to US17/630,634 priority patent/US11900883B2/en
Priority to PCT/CN2021/081786 priority patent/WO2022193281A1/zh
Priority to EP21930873.1A priority patent/EP4131243A4/en
Publication of WO2022193281A1 publication Critical patent/WO2022193281A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • Embodiments of the present disclosure relate to a shift register unit and a driving method, a gate driving circuit, and a display device.
  • OLED display panels are thin, light, wide viewing angle, active light-emitting, continuously adjustable light-emitting color, low cost, fast response speed, low energy consumption, low driving voltage, and wide operating temperature range ,
  • the advantages of simple production process, high luminous efficiency and flexible display, etc., are more and more widely used in display fields such as mobile phones, tablet computers, and digital cameras.
  • a pixel array of an organic light emitting diode display panel generally includes multiple rows of gate lines and multiple columns of data lines staggered therewith.
  • the driving of the gate lines can be realized by a bonded integrated driving circuit.
  • the gate driver circuit can also be directly integrated on the thin film transistor array substrate to form GOA (Gate driver On Array) to drive the gate lines. .
  • a GOA composed of a plurality of cascaded shift register units can be used to provide on-off voltage signals (scanning signals) for a plurality of rows of gate lines of a pixel array, so as to control the plurality of rows of gate lines to be turned on in sequence, and at the same time, by data
  • the lines provide data signals to the pixel units in the corresponding row in the pixel array, so as to form the grayscale voltages required for displaying each grayscale of the image in each pixel unit, and then display a frame of image.
  • Current display panels increasingly use GOA technology to drive gate lines.
  • the GOA technology helps to realize the narrow frame design of the display panel, and can reduce the production cost of the display panel.
  • the shift register unit includes: a first shift register circuit module and a second shift register circuit module.
  • the first shift register circuit module is configured to output a first output signal at a first output and provide an on control signal to the second shift register circuit module according to an input signal received at the input.
  • the second shift register circuit module includes an output circuit, a de-noising circuit, a first de-noising control circuit, and a second de-noising control circuit, the output circuit being configured to respond to the turn-on control signal at a second output
  • the terminal outputs a second output signal
  • the de-noising circuit is configured to de-noise the second output terminal under the control of the level of the first de-noising control node
  • the first de-noising control circuit is configured to In response to the first output signal, the level of the first de-noising control node is controlled to turn off the de-noising circuit
  • the second de-noising control circuit being configured to operate between the first clock signal and the second clock Under the control of the signal, the level of the first denoising control node is adjusted to turn on the denoising circuit.
  • the second denoising control circuit includes a first control circuit, a first coupling circuit, a second coupling circuit, a transmission circuit and a storage circuit, and the first control circuit is configured to, under the control of the first clock signal, convert the first A voltage is transmitted to a second denoising control node, the first coupling circuit is configured to store the level of the second denoising control node, and adjust the second denoising control under the control of a second clock signal the level of the node, the second coupling circuit is configured to store the level of the second denoising control node, and reduce the adjustment amount by which the first coupling circuit adjusts the level of the second denoising control node , the transmission circuit is configured to connect the first denoising control node and the second denoising control node to balance the level of the first denoising control node and the power level of the second denoising control node level, the storage circuit is configured to store the level of the first denoising control node.
  • the first control circuit includes a first transistor, the first coupling circuit includes a first capacitor, and the second coupling circuit includes a second capacitor, so
  • the transmission circuit includes a second transistor, the storage circuit includes a third capacitor; the gate of the first transistor is connected to the first clock signal terminal to receive the first clock signal, and the first pole of the first transistor connected to the first voltage terminal to receive the first voltage, the second pole of the first transistor is connected to the second denoising control node; the first end of the first capacitor is connected to the second denoising control node connection, the second end of the first capacitor is connected to the second clock signal end to receive the second clock signal; the first end of the second capacitor is connected to the second denoising control node, the first The second terminal of the second capacitor is connected to the first voltage terminal; the gate of the second transistor is connected to the second denoising control node, and the first pole of the second transistor is connected to the first denoising node The control node is connected, the second pole of
  • the second denoising control circuit further includes a second control circuit, and the second control circuit is configured so that the level of the second output terminal varies Under control, the second clock signal is transmitted to the first coupling circuit.
  • the second control circuit includes a third transistor, and the second end of the first capacitor passes through the third transistor and the second clock signal end connected, the gate of the third transistor is connected to the second output terminal, the first pole of the third transistor is connected to the second clock signal terminal, and the second pole of the third transistor is connected to the second output terminal The second end of the first capacitor is connected.
  • the denoising circuit is configured to transmit the first voltage to the a second output terminal for denoising the second output terminal.
  • the denoising circuit includes a fourth transistor, a gate of the fourth transistor is connected to the first denoising control node, and the fourth transistor The first pole of the transistor is connected to the first voltage terminal to receive the first voltage, and the second pole of the fourth transistor is connected to the first output terminal.
  • the difference between the level of the first de-noising control node and the first voltage is n times the threshold voltage of the denoising circuit, where 1 ⁇ n ⁇ 10.
  • the first de-noising control circuit is further configured to control the level of the second de-noising control node in response to the first output signal.
  • the first denoising control circuit includes a fifth transistor and a sixth transistor; the gate of the fifth transistor is connected to the first output terminal to To receive the first output signal, a first pole of the fifth transistor is connected to a first signal terminal to receive a first signal level, and a second pole of the fifth transistor is connected to the first denoising control node ; the gate of the sixth transistor is connected to the first output terminal to receive the first output signal, and the first pole of the sixth transistor is connected to the first signal terminal to receive the first signal level, the second pole of the sixth transistor is connected to the second denoising control node.
  • the first signal terminal is a second voltage terminal for providing a second voltage, and the first signal level is the second voltage; or , the first signal terminal is connected to the first node in the first shift register circuit module, and the first signal level is the level of the first node.
  • the output circuit includes a seventh transistor, and the gate of the seventh transistor is connected to the second signal terminal to receive the turn-on control signal, and the seventh transistor The first pole of the seven transistors is connected to the third clock signal terminal to receive the third clock signal, and the second pole of the seventh transistor is connected to the second output terminal.
  • the second signal terminal is connected to the second node in the first shift register circuit module.
  • the first shift register circuit module includes: a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor, and a fifth switch transistor, a sixth switch transistor, a seventh switch transistor, an eighth switch transistor, a fourth capacitor and a fifth capacitor; the gate of the first switch transistor is connected to a fourth clock signal terminal to receive a fourth clock signal, the The first pole of the first switch transistor is connected to the third node, the second pole of the first switch transistor is connected to the input terminal; the gate of the second switch transistor is connected to the third node, and the second switch transistor is connected to the third node.
  • the first pole of the switch transistor is connected to the first node, the second pole of the second switch transistor is connected to the fourth clock signal terminal to receive the fourth clock signal;
  • the gate of the third switch transistor is connected to The fourth clock signal terminal is connected to receive the fourth clock signal, the first pole of the third switch transistor is connected to the first node, and the second pole of the third switch transistor is connected to the first voltage terminal connected to receive the first voltage;
  • the gate of the fourth switch transistor is connected to the first node, the first pole of the fourth switch transistor is connected to the second voltage terminal to receive the second voltage, the fourth The second pole of the switching transistor is connected to the first output terminal;
  • the first terminal of the fourth capacitor is connected to the first node, and the second terminal of the fourth capacitor is connected to the second voltage terminal;
  • the gate of the fifth switch transistor is connected to the second node, the first pole of the fifth switch transistor is connected to the fifth clock signal terminal to receive the fifth clock signal, and the second pole of the fifth switch transistor is connected to the fifth clock signal terminal.
  • the first output terminal is connected; the first terminal of the fifth capacitor is connected to the second node, and the second terminal of the fifth capacitor is connected to the first output terminal;
  • the gate is connected to the first node, the first pole of the sixth switch transistor is connected to the second voltage terminal to receive the second voltage, and the second pole of the sixth switch transistor is connected to the fourth node connected;
  • the gate of the seventh switch transistor is connected to the fifth clock signal terminal to receive the fifth clock signal, the first pole of the seventh switch transistor is connected to the third node, and the first pole of the seventh switch transistor is connected to the third node.
  • the second pole of the seven switch transistor is connected to the fourth node; the gate of the eighth switch transistor is connected to the first voltage terminal to receive the first voltage, and the first pole of the eighth switch transistor connected to the second node, and the second pole of the eighth switching transistor is connected to the third node.
  • the first shift register circuit module includes: an eleventh switch transistor, a twelfth switch transistor, a thirteenth switch transistor, and a fourteenth switch transistor , the fifteenth switch transistor, the sixteenth switch transistor, the seventeenth switch transistor, the eighteenth switch transistor, the nineteenth switch transistor, the twentieth switch transistor, the sixth capacitor and the seventh capacitor; the eleventh The gate of the switch transistor is connected to the second clock signal terminal to receive the second clock signal, the second pole of the eleventh switch transistor is connected to the input terminal to receive the input signal, and the eleventh switch transistor is connected to the input terminal to receive the input signal.
  • the first pole of the switch transistor is connected to the third node; the gate of the twelfth switch transistor is connected to the second clock signal terminal to receive the second clock signal, and the second pole of the twelfth switch transistor is connected to the second clock signal terminal.
  • the pole is connected to the third node, the first pole of the twelfth switch transistor is connected to the second node; the gate of the thirteenth switch transistor is connected to the second node, and the thirteenth switch transistor is connected to the second node.
  • the first pole of the switch transistor is connected to the sixth clock signal terminal to receive the sixth clock signal, the second pole of the thirteenth switch transistor is connected to the first output terminal; the first terminal of the seventh capacitor is connected to the The second node is connected, the second end of the seventh capacitor is connected to the first output end; the gate of the fourteenth switch transistor is connected to the first node, and the fourth end of the fourteenth switch transistor is connected to the first node.
  • One pole is connected to the second voltage terminal to receive the second voltage
  • the second pole of the fourteenth switch transistor is connected to the first output terminal
  • the first terminal of the sixth capacitor is connected to the first node
  • the second terminal of the sixth capacitor is connected to the second voltage terminal
  • the gate of the fifteenth switch transistor is connected to the first clock signal terminal to receive the first clock signal
  • the fifteenth switch transistor The first pole of the switch transistor is connected to the first node
  • the second pole of the fifteenth switch transistor is connected to the first voltage terminal to receive the first voltage
  • the gate of the sixteenth switch transistor is connected to the first voltage terminal.
  • the first pole of the sixteenth switch transistor is connected to the second voltage terminal to receive the second voltage, the second pole of the sixteenth switch transistor is connected to the fourth node; the first The gate of the seventeenth switch transistor is connected to the first node, the first pole of the seventeenth switch transistor is connected to the fourth node, and the second pole of the seventeenth switch transistor M17 is connected to the first node.
  • Two nodes are connected; the gate of the eighteenth switch transistor is connected to the second node, the first pole of the eighteenth switch transistor is connected to the fourth node, and the first pole of the eighteenth switch transistor is connected to the fourth node.
  • One pole is connected to the first voltage terminal to receive the first voltage; the gate of the nineteenth switch transistor is connected to the input terminal to receive the input signal, and the first terminal of the nineteenth switch transistor One pole is connected to the second voltage terminal to receive the second voltage, the second pole of the nineteenth switch transistor is connected to the first node; the gate of the twentieth switch transistor is connected to the The first output is connected to receive the first output signal, so The first pole of the twentieth switch transistor is connected to the sixth clock signal terminal to receive the sixth clock signal, and the second pole of the twentieth switch transistor is connected to the third node.
  • At least some embodiments of the present disclosure further provide a gate driving circuit, including: a plurality of cascaded shift register units provided in any embodiment of the present disclosure.
  • the input terminals of the other stage shift register units are connected to the first output terminal of the previous stage shift register unit.
  • At least some embodiments of the present disclosure further provide a display device including the gate driving circuit provided by any embodiment of the present disclosure.
  • the display device provided by some embodiments of the present disclosure further includes: a plurality of gate lines, wherein the second output terminal of the shift register unit of each stage is connected to at least one gate line of the plurality of gate lines.
  • At least some embodiments of the present disclosure further provide a method for driving a shift register unit, comprising: a holding phase, wherein, in the holding phase, the first clock signal and the second clock signal are alternately input, and the The second de-noising control circuit adjusts the level of the first de-noising control node to turn on the de-noising circuit, so that the de-noising circuit de-noises the second output terminal.
  • 1 is a schematic structural diagram of a display panel
  • Fig. 2 is the circuit structure diagram of a kind of shift register unit
  • Fig. 3 is the signal timing diagram when the shift register unit shown in Fig. 2 works;
  • Fig. 4 is the output noise figure when the shift register unit shown in Fig. 2 works;
  • FIG. 5 is a schematic block diagram of a shift register unit according to some embodiments of the present disclosure.
  • FIG. 6 is a schematic block diagram of a second shift register circuit module according to some embodiments of the present disclosure.
  • FIG. 7 is a schematic block diagram of another second shift register circuit module provided by some embodiments of the present disclosure.
  • FIG. 8 is a schematic diagram of a circuit structure of a specific implementation example of the second shift register circuit module shown in FIG. 6;
  • FIG. 9 is a schematic diagram of a circuit structure of a specific implementation example of the second shift register circuit module shown in FIG. 7;
  • FIG. 10 is a schematic diagram of a circuit structure of a specific implementation example of a shift register unit provided by some embodiments of the present disclosure
  • FIG. 11 is a schematic diagram of a circuit structure of another specific implementation example of a shift register unit provided by some embodiments of the present disclosure.
  • Fig. 12 is the signal timing diagram when the shift register unit shown in Fig. 10 is working;
  • FIG. 13 is a signal timing diagram when the shift register unit shown in FIG. 11 operates.
  • FIG. 1 is a schematic structural diagram of a display panel.
  • the display panel 01 includes a display area AA and a peripheral area BB located on at least one side of the display area AA.
  • a plurality of sub-pixels P arranged in an array are arranged in the display area AA; for example, the plurality of sub-pixels P usually include sub-pixels of multiple colors, and the sub-pixels of multiple colors usually include sub-pixels of a first color, a sub-pixel of a second color, and a sub-pixel of a second color.
  • the third color sub-element for example, the first color, the second color and the third color may be three primary colors (eg, red, green and blue), but is not limited thereto.
  • the plurality of sub-pixels P in FIG. 1 are arranged in a matrix form as an example for description.
  • the sub-pixels P arranged in a row in the horizontal direction are referred to as a row of sub-pixels
  • the sub-pixels P arranged in a row in the vertical direction are referred to as a column of sub-pixels.
  • each sub-pixel P is provided with a pixel circuit S.
  • the pixel circuit S generally includes a plurality of transistors (shown as including two transistors in FIG. 1 ) and a capacitor.
  • the pixel circuit S is coupled to the light-emitting element L for driving the light-emitting element L to emit light.
  • the light-emitting element L in each color sub-pixel can emit light of the corresponding color, that is, the light-emitting element L in the first color sub-pixel can emit the first color (eg red light), and the second color sub-pixel
  • the light-emitting element L in the pixel may emit light of a second color (eg, green light), and the light-emitting element L in the sub-pixel of the third color may emit light of a third color (eg, blue light).
  • the pixel circuits S located in the same row are connected to the same gate line GL (Gate Line, as shown by G_1, G_2, ..., G_N, etc.
  • N is a positive integer
  • the pixel circuits S located in the same column The same data line DL (Data Line, shown as D_1, D_2, ..., D_M, etc. in Figure 1, where M is a positive integer) is connected.
  • the transistors included in the pixel circuit S may be either N-type transistors or P-type transistors, and may also include both N-type and P-type transistors, which can be set according to actual needs.
  • the transistors included in the pixel circuit S may be all low temperature polysilicon (Low Temperature Poly-silicon, LTPS for short) transistors, may also be oxide (Oxide) transistors, and may also include both LTPS and oxide transistors.
  • LTPS Low Temperature Poly-silicon
  • the voltage for controlling the brightness of sub-pixels will vary with time due to the leakage of transistors in the pixel circuit S. Therefore, in order to keep the fluctuation of pixel brightness within a reasonable range, data still needs to be refreshed when displaying a static image. In order to reduce the power consumption when displaying a static image, it is an effective method to reduce the refresh frequency. At the same time, in order to maintain the display quality, it is also necessary to reduce the leakage speed of the transistors in the pixel circuit S.
  • the transistors in the pixel circuit S can be set as oxide transistors; at the same time, in order to ensure the charging speed of sub-pixels and small parasitic capacitance, the advantages of LTPS and Oxide can be combined, A low temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide, LTPO for short) process is adopted, so that the pixel circuit S includes two transistors, LTPS and Oxide.
  • the pixel circuit S may include a P-type LTPS transistor and an N-type Oxide transistor.
  • the peripheral area BB of the display panel 01 is provided with a gate driving circuit and a data driving circuit.
  • the gate driving circuit can be arranged on the side along the extension direction of the gate line, and the data driving circuit can be arranged on the side along the extension direction of the data line DL to drive the pixel circuit S in the display panel, and then drive the light-emitting element L emits light to cause the corresponding sub-pixel P to display.
  • the gate drive circuit can be implemented by a bound integrated circuit drive chip, or the gate drive circuit can be directly integrated on the display panel to form a GOA.
  • the data driving circuit can be implemented by a bonded integrated circuit driving chip.
  • FIG. 1 is exemplary.
  • a gate driving circuit is provided on one side of the peripheral area BB of the display panel 01 to sequentially drive each gate line row by row from one side, that is, one side driving.
  • gate driving circuits may also be provided on the two sides along the extending direction of the gate lines in the peripheral area BB of the display panel 01, respectively, and the gate driving circuits can simultaneously drive each gate line by line from both sides through the two gate driving circuits. line, that is, double-sided drive.
  • gate driving circuits may also be provided on two sides along the extending direction of the gate lines in the peripheral area BB of the display panel 01, and the gate driving circuits may alternately drive the gates row by row from both sides through the two gate driving circuits. line, i.e. cross drive.
  • single-side driving is taken as an example for description.
  • the gate driving circuit includes N cascaded shift register units RS (as shown by RS_1 , RS_2 , . . . , RS_N in FIG. 1 ), and the N cascaded shift register units are connected to
  • the N gate lines (as shown by G_1, G_2, . . . , G_N in FIG. 1 ) are connected in one-to-one correspondence.
  • each stage of the shift register unit RS includes a signal input terminal IN, a scan signal output terminal OUT and a cascaded signal output terminal GP.
  • the signal input terminal IN of the first stage shift register unit RS_1 may be configured to receive the trigger signal STV.
  • each stage of the shift register unit RS provides a scan signal to the gate line connected thereto through the scan signal output terminal OUT.
  • the circuit structures of the shift register units RS of all levels in the gate driving circuit shown in FIG. 1 are generally the same.
  • the cascaded signal output terminal GP may also be connected to the P-type transistor in the pixel circuit S through, for example, a gate line, so as to connect the P-type transistor to the P-type transistor.
  • a control signal is transmitted to control the P-type transistor to be turned on or off.
  • each gate line needs to be driven row by row by the gate driving circuit.
  • the shift register unit In the driving process of each row of gate lines, after the shift register unit outputs the scan signal, the shift register unit should output a non-operating voltage to the gate line coupled to it to ensure that the transistor coupled to the gate line is turned off, This phase is called the hold phase.
  • the hold phase In the hold stage, the noise of the scan signal output terminal OUT coupled to the gate line in the shift register unit is relatively large, which may cause the image displayed by the display device to be unstable.
  • FIG. 2 is a circuit structure diagram of a shift register unit.
  • the shift register unit includes 12 transistors M1-M12 and 4 capacitors (C01-C04).
  • the gate of the transistor M1 is connected to the clock signal terminal CK to receive the clock signal CK
  • the second pole of the transistor M1 is connected to the signal input terminal IN
  • the first pole of the transistor M1 is connected to the node PD_in
  • the gate of the transistor M2 is connected to the node PD_in
  • the second pole of the transistor M2 is connected to the clock signal terminal CK to receive the clock signal CK
  • the first pole of the transistor M2 is connected to the node PU
  • the gate of the transistor M3 is connected to the clock signal terminal CK to receive the clock signal CK
  • the gate of the transistor M3 is connected to the clock signal terminal CK.
  • the second electrode is connected to the first power supply line VSS to receive the first voltage VSS (for example, the first voltage VSS is at a low level), the first electrode of the transistor M3 is connected to the node PU; the gate of the transistor M4 is connected to the node PU, The first pole of the transistor M4 is connected to the second power line VDD to receive the second voltage VDD (for example, the second voltage VDD is at a high level), the second pole of the transistor M4 is connected to the output terminal GP; the first terminal of the capacitor C01 It is connected to the node PU, the second end of the capacitor C01 is connected to the second power supply line VDD; the gate of the transistor M5 is connected to the node PD_out, the first pole of the transistor M5 is connected to the clock signal terminal CB to receive the clock signal CB, and the The second pole is connected to the cascaded signal output terminal GP; the first terminal of the capacitor C02 is connected to the node PD_out, and the second terminal of the capacitor C02 is connected
  • One pole is connected to the node PD_in, the second pole of the transistor M7 is connected to the node PD_f; the gate of the transistor M8 is connected to the first power supply line VSS to receive the first voltage VSS, the second pole of the transistor M8 is connected to the node PD_in, and the transistor M8
  • the first pole of the transistor M9 is connected to the node PD_out; the gate of the transistor M9 is connected to the cascade signal output terminal GP, the first pole of the transistor M9 is connected to the second power supply line VDD to receive the second voltage VDD, and the second pole of the transistor M9 and
  • the node PD_ox is connected; the gate of the transistor M10 is connected to the clock signal terminal CK to receive the clock signal CK, the second pole of the transistor M10 is connected to the first power supply line VSS to receive the first voltage VSS, and the first pole of the transistor M10 is connected to the node PD_ox connection; the gate of the transistor M11 is connected to the cas
  • the transistors in the shift register unit shown in FIG. 2 are all described by taking P-type transistors as an example, that is, each transistor is turned on when the gate is connected to a low level (that is, a low level is an effective power supply). level), and is turned off when a high level is connected (ie, the high level is an inactive level).
  • the first electrode of the transistor may be the source electrode
  • the second electrode of the transistor may be the drain electrode.
  • FIG. 3 is a signal timing diagram when the shift register unit shown in FIG. 2 operates.
  • the working principle of the shift register unit shown in FIG. 2 is briefly described below with reference to the signal timing diagram shown in FIG. 3 .
  • the working process of the shift register unit shown in FIG. 2 includes three stages, namely the first stage t1 (also called the input stage), the second stage t2 (also called the output stage) and the holding stage stage (including the third stage t3, the fourth stage t4, the fifth stage t5, ... etc.).
  • Figure 3 shows the timing waveforms of the various signals in each stage.
  • the clock signal CK is at a low level
  • the clock signal CB is at a high level
  • the signal input terminal IN is at a low level (that is, the signal input terminal IN receives a low-level input signal) , so that the transistors M1, M3, and M10 are turned on, and the transistor M7 is turned off.
  • the turned-on transistor M1 transmits a low-level input signal to the node PD_in, so that the level of the node PD_in becomes a low level, so that the transistor M2 is turned on; since the transistor M8 is always in response to the first voltage VSS (low level) is in the on state, so the level of the node PD_out is the same as the level of the node PD_in, that is, the low level, so the low level is stored in the capacitor C02, and the transistor M5 is turned on; the turned-on transistor M3 will A voltage VSS (low level) is transmitted to the node PU, and the turned-on transistor M2 transmits the low level of the clock signal CK to the node PU, so that the level of the node PU becomes a low level and is stored in the capacitor C01 ; The transistor M4 is turned on in response to the low level of the node PU, and outputs the second voltage VDD (high level) to the cascade signal output terminal GP, and at the same
  • the clock signal CK is at a high level
  • the clock signal CB is at a low level
  • the signal input terminal IN is at a high level, so that the transistors M1, M3, and M10 are turned off, and the transistor M7 is turned on. Pass.
  • the node PD_in and the node PD_out can continue to maintain the low level of the previous stage, so that the transistors M2 and M5 are turned on; the turned-on transistor M2 transmits the high level of the clock signal CK to the node PU, thereby The level of the node PU is changed to a high level; the transistor M4 is turned off in response to the high level of the node PU, so as to avoid outputting the second voltage VDD (high level) to the cascade signal output terminal GP; the turned-on transistor M5 will The low level of the clock signal CB is transmitted to the cascade signal output terminal GP, so that at this stage, the cascade signal output terminal GP of the shift register unit outputs a low level, for example, the low level can be used as the next stage shift
  • the input signal of the bit register unit can of course also be used to control the operation of the P-type transistor in the pixel circuit S shown in FIG.
  • the two voltages VDD (high level) are transmitted to the node PD_ox, so that the level of the node PD_ox becomes a high level, correspondingly, the transistor M12 is turned off; the transistor M11 is turned on in response to the low level of the cascade signal output terminal GP,
  • the second voltage VDD (high level) is output to the scan signal output terminal OUT, so that at this stage, the scan signal output terminal OUT of the shift register unit outputs a high level, for example, the high level can be used to control the map
  • the N-type transistors in the pixel circuit S shown in 1 operate.
  • the clock signal CK is at a low level
  • the clock signal CB is at a high level
  • the signal input terminal IN is at a high level, so that the transistors M1, M3, and M10 conduct On, the transistor M7 is turned off.
  • the turned-on transistor M1 transmits the high level of the signal input terminal IN to the node PD_in and the node PD_out (the transistor M8 is always on), so that the level of the node PD_in and the node PD_out becomes a high level, correspondingly,
  • the transistors M2 and M5 are turned off;
  • the turned-on transistor M3 transmits the first voltage VSS (low level) to the node PU, so that the level of the node PU becomes a low level and is stored in the capacitor C01;
  • the transistor M4 responds to The low level of the node PU is turned on, and the second voltage VDD (high level) is output to the cascade signal output terminal GP, so that at this stage, the cascade signal output terminal GP of the shift register unit outputs a high level,
  • the transistors M9 and M11 are turned off in response to the high level of the cascade signal output terminal GP; in addition, the turned-on transistor M10 transmits the first voltage VSS
  • the clock signal CK is at a high level
  • the clock signal CB is at a low level
  • the signal input terminal IN is at a high level, so that the transistors M1, M3, and M10 are turned off,
  • the transistor M7 is turned on.
  • the node PD_in and the node PD_out can continue to maintain the high level of the previous stage, so that the transistors M2 and M5 are turned off; due to the storage function of the capacitor C01, the node PU continues to maintain the low level of the previous stage, thus The transistors M4 and M6 are kept on; the second voltage VDD (high level) is transmitted to the node PD_in and the node PD_out through the turned on transistor M6 and the turned on transistor M7, so that the node PD_in and the node PD_out remain high level, effectively preventing the transistor M5 from being turned on, thereby avoiding false output; at the same time, the turned-on transistor M4 outputs the second voltage VDD (high level) to the cascaded signal output terminal GP, so that at this stage, the shift The cascade signal output terminal GP of the bit register unit outputs a high level, and accordingly, the transistors M9 and M11 are turned off in response to the high
  • the clock signal CK is at a low level
  • the clock signal CB is at a high level
  • the signal input terminal IN is at a high level, so that the transistors M1 and M3 are turned on, Transistor M7 is turned off.
  • the turned-on transistor M1 transmits the high level of the signal input terminal IN to the node PD_in and the node PD_out (the transistor M8 is always on), so that the levels of the node PD_in and the node PD_out are kept at a high level, and accordingly,
  • the transistors M2 and M5 are turned off;
  • the turned-on transistor M3 transmits the first voltage VSS (low level) to the node PU, so that the level of the node PU remains at a low level, so that the transistors M4 and M6 remain on;
  • the second voltage VDD (high level) is transmitted to the node PD_in and the node PD_out through the turned-on transistor M6 and the turned-on transistor M7, so that the node PD_in and the node PD_out remain at a high level, effectively preventing the transistor M5 from being turned on, Thus, false output is avoided; at the same time, the turned-on transistor M4 outputs the second voltage VDD (
  • the level of the clock signal CK is low, and the level of the node PD_ox is also low. Since the threshold voltage Vth of the P-type transistor is generally negative, the gate-source voltage difference of the transistor M10 is Vgs>Vth, since the P-type transistor is turned on when Vgs ⁇ Vth, the transistor M10 is turned off at this time; since the transistors M9 and M11 are also turned off, the node PD-ox and the scan signal output terminal OUT are floating (floating ) state; the level of the clock signal CB becomes a high level, due to the bootstrap effect of the capacitor C03, the level of the node PD_ox will be slightly pulled up, so that the transistor M12 is turned off, and the first voltage VSS (low level) cannot be continuously ) is output to the scan signal output terminal OUT, that is, at this stage, the continuous denoising of the scan signal output terminal OUT cannot be achieved.
  • At least some embodiments of the present disclosure provide a shift register unit including a first shift register circuit module and a second shift register circuit module.
  • the first shift register circuit block is configured to output a first output signal at a first output and provide a turn-on control signal to the second shift register circuit block according to an input signal received at the input.
  • the second shift register circuit module includes an output circuit, a de-noising circuit, a first de-noising control circuit and a second de-noising control circuit; the output circuit is configured to output the second output signal at the second output terminal in response to the turn-on control signal the de-noising circuit is configured to de-noise the second output under the control of the level of the first de-noising control node; the first de-noising control circuit is configured to control the first de-noising in response to the first output signal the level of the control node to turn off the denoising circuit; the second denoising control circuit is configured to adjust the level of the first denoising control node to turn on the denoising under the control of the first clock signal and the second clock signal circuit.
  • the second denoising control circuit includes a first control circuit, a first coupling circuit, a second coupling circuit, a transmission circuit and a storage circuit;
  • the first control circuit is configured to transmit the first voltage to a second denoising control node;
  • the first coupling circuit is configured to store the level of the second denoising control node and adjust the level of the second denoising control node under the control of the second clock signal;
  • the second coupling circuit is is configured to store the level of the second denoising control node, and reduce the adjustment amount by which the first coupling circuit adjusts the level of the second denoising control node;
  • the transmission circuit is configured to connect the first denoising control node and the second denoising control node a control node to balance the level of the first denoising control node and the level of the second denoising control node;
  • the storage circuit is configured to store the level of the first denoising control node.
  • Some embodiments of the present disclosure also provide a gate driving circuit, a display device, and a driving method corresponding to the above-mentioned shift register unit.
  • the shift register unit by introducing a charge pump structure formed by a first control circuit, a first coupling circuit, a second coupling circuit, a transmission circuit, and a storage circuit into the second denoising control circuit, using The adjustment effect of the charge pump structure on the voltage can adjust the level of the first denoising control node; thus, on the one hand, it ensures that the denoising circuit is continuously turned on in the hold phase to remove noise interference in time, and on the other hand, reduces the first denoising The level of the control node has a biasing effect on the denoising circuit, and prolongs the working life of the shift register unit.
  • FIG. 5 is a schematic block diagram of a shift register unit according to some embodiments of the present disclosure.
  • the shift register unit 100 includes a first shift register circuit module 110 and a second shift register circuit module 120 (as shown by the dotted box in FIG. 5 ).
  • the signals respectively output the first output signal at the first output terminal GP and the second output signal at the second output terminal OUT.
  • a gate driving circuit can be obtained by cascading a plurality of the shift register units 100 (for example, refer to the gate driving circuit shown in FIG. 1 ), and the gate driving circuit can be used to drive, for example, a liquid crystal display panel, Organic Light Emitting Diode Display Panel, etc.
  • the first shift register circuit module 110 is configured to output a first output signal (eg, a low level signal) at the first output terminal GP and to the second output terminal GP according to the input signal received by the input terminal IN
  • the shift register circuit block 120 provides the turn-on control signal.
  • the first shift register circuit module 110 may include a second node PD_o (described later), which may provide the second shift register circuit module 120 through the second node PD_o Turn on the control signal.
  • PD_o described later
  • the first output terminal of the shift register unit 100 of the current stage may be connected to the signal input terminal IN of the shift register unit 100 of the next stage, that is, the shift register unit 100 of the current stage
  • the first output signal of the register unit 100 can be used as the input signal of the shift register unit 100 of the next stage.
  • the first output terminal GP may also be connected to a P-type transistor in the pixel circuit through, for example, a gate line, so as to transmit a control signal to the P-type transistor to control the P-type transistor to be turned on or off.
  • the second shift register circuit module 120 includes an output circuit 121 , a denoising circuit 122 , a first denoising control circuit 123 and a second denoising control circuit 124 .
  • the output circuit 121 is configured to output a second output signal (eg, a high-level signal) at the second output terminal OUT in response to the turn-on control signal.
  • a second output signal eg, a high-level signal
  • the output circuit 121 is connected to the second node PD_o, the third clock signal terminal CK2 and the second output terminal OUT, and is configured to turn on the control signal (by the second node The level change of PD_o is turned on under the control of the turn-on control signal), so that the third clock signal CK2 provided by the third clock signal terminal CK2 is transmitted to the second output terminal OUT, and is used as the second output signal at the second output terminal.
  • OUT output e.g, a high-level signal
  • the output circuit 121 may be connected to the first output terminal GP, the third clock signal terminal CK2 and the second output terminal OUT, and is configured to turn on the control signal (the first output terminal GP provided by the first output terminal GP). An output signal is turned on under the control of the turn-on control signal), so that the third clock signal CK2 provided by the third clock signal terminal CK2 is transmitted to the second output terminal OUT, and is output at the second output terminal OUT as a second output signal .
  • the denoising circuit 122 is configured to denoise the second output terminal OUT under the control of the level of the first denoising control node PD_ox.
  • the de-noising circuit 122 is connected to the first de-noising control node PD_ox, the first voltage terminal VSS and the second output terminal OUT, and is configured to operate at the first de-noising control node.
  • the node PD_ox is turned on under the control of the level of the node PD_ox, thereby transmitting the first voltage VSS provided by the first voltage terminal VSS (for example, the first voltage VSS may be at a low level, but not limited thereto) to the second output terminal OUT, to denoise the second output terminal OUT.
  • the first voltage VSS for example, the first voltage VSS may be at a low level, but not limited thereto
  • the first denoising control circuit 123 is configured to control the level of the first denoising control node PD_ox to turn off the denoising circuit 122 in response to the first output signal.
  • the first denoising control circuit 123 is connected to the first output terminal GP, the first signal terminal VDD/PU and the first denoising control node PD_ox, and is configured to respond to The first output signal provided by the first output terminal GP transmits the first signal level of the first signal terminal VDD/PU to the first de-noising control node PD_ox to control (eg, pull up) the first de-noising control The level of the node PD_ox, and then the denoising circuit 122 is turned off.
  • the first signal terminal VDD/PU may be the second voltage terminal VDD that provides the second voltage VDD (eg, the second voltage VDD may be at a high level, but not limited thereto).
  • the first shift register circuit module 110 may include a first node PU (described later); as shown in FIG.
  • the node PU is connected, so that the first denoising control circuit 123 can transmit the level (eg, high level) of the first node PU to the first denoising control in response to the first output signal provided by the first output terminal GP
  • the node PD_ox is used to control (eg, pull up) the level of the first denoising control node PD_ox, thereby turning off the denoising circuit 122 .
  • the second denoising control circuit 124 is configured to adjust the level of the first denoising control node PD_ox under the control of the first clock signal CK1 and the second clock signal CB1 to turn on the denoising circuit.
  • the second denoising control circuit 124 is connected to the first clock signal terminal CK1 , the second clock signal terminal CB1 , the first voltage terminal VSS and the first denoising control node PD_ox , and is configured to be under the control of the first clock signal CK1 provided by the first clock signal terminal CK1 and the second clock signal CB1 provided by the second clock signal terminal CB1, based on the first voltage VSS provided by the first voltage terminal VSS.
  • the level of the first denoising control node PD_ox is adjusted to turn on the denoising circuit.
  • FIG. 6 is a schematic block diagram of a second shift register circuit module 120 according to some embodiments of the present disclosure.
  • the second denoising control circuit 124 may include a first control circuit 1241, a first coupling circuit 1242, a second coupling circuit 1243, a transmission circuit 1244 and Storage circuit 1245.
  • the first control circuit 1241 is configured to transmit the first voltage VSS to the second denoising control node PD_ox_i under the control of the first clock signal CK1.
  • the first control circuit 1241 is connected to the first clock signal terminal CK1 , the first voltage terminal VSS and the second denoising control node PD_ox_i, and is configured to operate at the first clock Under the control of the first clock signal CK1 provided by the signal terminal CK1, the first voltage VSS provided by the first voltage terminal VSS is transmitted to the second de-noising control node PD_ox_i.
  • the first coupling circuit 1242 is configured to store the level of the second denoising control node PD_ox_i, and adjust the level of the second denoising control node PD_ox_i under the control of the second clock signal CB1.
  • the first coupling circuit 1242 is connected to the second denoising control node PD_ox_i and the second clock signal terminal CB1 .
  • the second denoising control node PD_ox_i when the level of the second clock signal CB1 provided by the second clock signal terminal CB1 changes, due to the coupling effect of the first coupling circuit 1242 (eg, the bootstrap effect), the second denoising control node PD_ox_i The level also changes accordingly, so that the first coupling circuit 1242 can adjust the level of the second denoising control node PD_ox_i under the control of the second clock signal CB1.
  • the second coupling circuit 1243 is configured to store the level of the second denoising control node PD_ox_i, and reduce the adjustment amount by which the first coupling circuit 1242 adjusts the level of the second denoising control node PD_ox_i.
  • the second coupling circuit 1243 is connected to the second denoising control node PD_ox_i and the first voltage terminal VSS.
  • the second coupling circuit 1243 also has a coupling effect, when the level of the second clock signal CB1 provided by the second clock signal terminal CB1 changes, the coupling effect of the second coupling circuit 1243 is the same as that of the first coupling
  • the coupling function of the circuit 1242 works simultaneously, and further, the adjustment amount of the first coupling circuit 1242 to adjust the level of the second denoising control node PD_ox_i can be reduced.
  • the transmission circuit 1244 is configured to connect the first denoising control node PD_ox and the second denoising control node PD_ox_i to balance the level of the first denoising control node PD_ox and the level of the second denoising control node PD_ox_i.
  • the transfer circuit 1244 may store the second denoising control node PD_ox_i by transferring charges (the first coupling circuit 1242 and the second coupling circuit 1243 store the charges by storing the charges).
  • the subsequent storage circuit 1245 stores the level of the first de-noising control node PD_ox by storing charges) to balance the level of the first de-noising control node PD_ox and the level of the second de-noising control node PD_ox_i.
  • the storage circuit 1245 is configured to store the level of the first denoising control node PD_ox.
  • the storage circuit 1245 is connected to the first denoising control node PD_ox and the first voltage terminal VSS.
  • the above-mentioned first control circuit 1241, first coupling circuit 1242, second coupling circuit 1243, transmission circuit 1244, and storage circuit 1245 form a charge pump structure.
  • the second de-noising control circuit 124 can adjust the level of the first de-noising control node PD_ox by using the charge pump structure to adjust the voltage; thus, on the one hand, it is ensured that the de-noising circuit 122 is continuously turned on in the hold phase, and noise interference is removed in time On the other hand, the bias effect of the level of the first denoising control node PD_ox on the denoising circuit 122 is reduced, so as to prolong the working life of the shift register unit 100 .
  • the difference between the level of the first denoising control node PD_ox and the first voltage VSS is n times the threshold voltage of the denoising circuit 122, wherein , 1 ⁇ n ⁇ 10.
  • FIG. 7 is a schematic block diagram of another second shift register circuit module 120 provided by some embodiments of the present disclosure.
  • the second denoising control circuit 124 may further include a second control circuit 1246 based on the circuit structure shown in FIG. 6 .
  • other circuit structures of the second shift register circuit module 120 shown in FIG. 7 are basically the same as those of the second shift register circuit module 120 shown in FIG. 6 , and details are not repeated here.
  • the second control circuit 1246 is configured to transmit the second clock signal CB1 to the first coupling circuit 1242 under the control of the level of the second output terminal OUT.
  • the second control circuit 1246 is connected to the second output terminal OUT, the first clock signal terminal CB1 and the first coupling circuit 1242 .
  • the second control circuit when the second output terminal OUT outputs the second output signal, the second control circuit is turned off in response to the second output signal, so that the second clock signal CB1 cannot be transmitted to the first coupling circuit 1242 , thereby reducing the unfavorable coupling of the second clock signal terminal CB1 and reducing power consumption at the same time; when the denoising circuit 122 performs denoising on the second output terminal OUT, the level of the second output terminal OUT can make the second control circuit 1246 is turned on, so that the first clock signal CB1 can be transmitted to the first coupling circuit 1242 through the second control circuit 1246 that is turned on.
  • the first denoising control circuit 123 may also be connected to the second denoising control node PD_ox_i, and is further configured to control the second denoising control node PD_ox_i in response to the first output signal. 2.
  • the first de-noising control circuit 123 is further configured to, in response to the first output signal provided by the first output terminal GP, change the first signal level of the first signal terminal VDD/PU (eg, high level) is transmitted to the second denoising control node PD_ox_i to control (eg, pull up) the level of the second denoising control node PD_ox_i.
  • change the first signal level of the first signal terminal VDD/PU eg, high level
  • control eg, pull up
  • FIG. 8 is a schematic diagram of a circuit structure of a specific implementation example of the second shift register circuit module 120 shown in FIG. 6 .
  • the second shift register circuit module 120 includes a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and further includes a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7 A capacitor C1, a second capacitor C2, and a third capacitor C3.
  • each transistor is a P-type transistor as an example for description, but this does not constitute a limitation to the embodiments of the present disclosure.
  • the first control circuit 1241 may be implemented as the first transistor T1 shown in FIG. 8 .
  • the gate of the first transistor T1 is connected to the first clock signal terminal CK1 to receive the first clock signal CK1
  • the first electrode of the first transistor T1 is connected to the first voltage terminal VSS to receive the first voltage VSS
  • the second pole of the first transistor T1 is connected to the second denoising control node PD_ox_i.
  • the first transistor T1 when the first clock signal CK1 is at an active level (eg, a low level), the first transistor T1 is turned on, connecting the second de-noising control node PD_ox_i and the first voltage terminal VSS, so that the second de-noising control node PD_ox_i is connected to the first voltage terminal VSS.
  • the level of the control node PD_ox_i is the same as the level of the first voltage VSS (both are low levels).
  • the first coupling circuit 1242 may be implemented as the first capacitor C1 shown in FIG. 8 .
  • the first terminal of the first capacitor C1 is connected to the second denoising control node PD_ox_i, and the second terminal of the first capacitor C1 is connected to the second clock signal terminal CB1 to receive the second clock signal CB1.
  • the first capacitor C1 is used to store the level of the second de-noising control node PD_ox_i; at the same time, the first capacitor C1 has a coupling effect, and when the level of the second clock signal CB1 provided by the second clock signal terminal CB1 changes , due to the coupling effect of the first capacitor C1 (eg, the bootstrap effect), the level of the second denoising control node PD_ox_i will also change accordingly, so that the first capacitor C1 can be adjusted under the control of the second clock signal CB1
  • the second denoising controls the level of the node PD_ox_i.
  • the second coupling circuit 1243 may be implemented as the second capacitor C2 shown in FIG. 8 .
  • the first terminal of the second capacitor C2 is connected to the second denoising control node PD_ox_i, and the second terminal of the second capacitor C2 is connected to the first voltage terminal VSS to receive the first voltage VSS.
  • the second capacitor C2 is also used to store the level of the second de-noising control node PD_ox_i; at the same time, the second capacitor C2 also has a coupling effect, so that the level of the second clock signal CB1 provided by the second clock signal terminal CB1 generates In the case of change, the coupling effect of the second capacitor C2 and the coupling effect of the first capacitor C1 work simultaneously, and further, the adjustment amount of the first capacitor C1 to adjust the level of the second denoising control node PD_ox_i can be reduced.
  • the transmission circuit 1244 may be implemented as the second transistor T2 shown in FIG. 8 .
  • the gate of the second transistor T2 is connected to the second denoising control node PD_ox_i
  • the first pole of the second transistor T2 is connected to the first denoising control node PD_ox
  • the second pole of the second transistor T2 is connected to the first denoising control node PD_ox
  • the second denoising control node PD_ox_i is connected.
  • the second transistor T2 is turned on, connecting the first denoising control node PD_ox and the second denoising control node PD_ox_i, so that The level of the first de-noising control node PD_ox is the same as the level of the second de-noising control node PD_ox_i (both are low levels).
  • the storage circuit 1245 may be implemented as the third capacitor C3 shown in FIG. 8 .
  • the first terminal of the third capacitor C3 is connected to the first denoising control node PD_ox
  • the second terminal of the third capacitor C3 is connected to the first voltage terminal VSS to receive the first voltage VSS.
  • the third capacitor C3 is used to store the level of the first denoising control node PD_ox, and is used to control the fourth transistor T4 to be turned on or off in a subsequent stage.
  • the second denoising control circuit 124 may be implemented as the first transistor T1 , the second transistor T2 , the first capacitor C1 , the second capacitor C2 , and the third capacitor C3 shown in FIG. 8 .
  • the first transistor T1 , the second transistor T2 , the first capacitor C1 , the second capacitor C2 , and the third capacitor C3 shown in FIG. 8 form a charge pump structure, and the voltage regulation effect of the charge pump structure can be used to adjust the first to The level of the noise control node PD_ox; thus, on the one hand, it is ensured that the fourth transistor T4 is continuously turned on in the holding phase, and the noise interference is removed in time; The bias effect prolongs the working life of the shift register unit 100 .
  • the first de-noising control by reasonably setting the capacitance values of the first capacitor C1 and the second capacitor C2, under the adjustment of the above-mentioned charge pump structure (ie, the second de-noising control circuit 124), the first de-noising control
  • the difference between the level of the node PD_ox and the first voltage VSS is n times the threshold voltage of the denoising circuit 122 , where 1 ⁇ n ⁇ 10.
  • the denoising circuit 122 may be implemented as the fourth transistor T4 shown in FIG. 8 .
  • the gate of the fourth transistor T4 is connected to the first denoising control node PD_ox
  • the first electrode of the fourth transistor T4 is connected to the first voltage terminal VSS to receive the first voltage VSS
  • the The second pole is connected to the second output terminal OUT.
  • the fourth transistor T4 is turned on to connect the second output terminal OUT with the first voltage terminal VSS, so as to connect the first voltage
  • the first voltage VSS provided by the terminal VSS is output at the second output terminal OUT, so as to denoise the second output terminal OUT1.
  • the first denoising control circuit 123 may be implemented as the fifth transistor T5 and the sixth transistor T6 shown in FIG. 8 .
  • the gate of the fifth transistor T5 is connected to the first output terminal GP to receive the first output signal
  • the first pole of the fifth transistor T5 is connected to the first signal terminal VDD/PU to receive the first signal power
  • the second pole of the fifth transistor T5 is connected to the first denoising control node PD_ox
  • the gate of the sixth transistor T6 is connected to the first output terminal GP to receive the first output signal
  • the first pole of the sixth transistor T6 is connected to the first output terminal GP.
  • the first signal terminal VDD/PU is connected to receive the first signal level, and the second pole of the sixth transistor T6 is connected to the second denoising control node PD_ox_i.
  • the first signal terminal VDD/PU may be the second voltage terminal VDD for providing the second voltage VDD (for example, the second voltage VDD may be at a high level, but not limited thereto).
  • the first signal level is the second voltage VDD; for example, in other embodiments, the first signal terminal VDD/PU may be connected to the first node PU in the first shift register circuit module 110, and the In this case, the first signal level is the level (eg, high level) of the first node PU; it should be noted that the present disclosure includes but is not limited to the above situations.
  • the first output signal of the first output terminal GP is at an active level (eg, a low level)
  • the fifth transistor T5 and the sixth transistor T6 are turned on at the same time; the turned-on fifth transistor T5 turns the second transistor T5 on.
  • the denoising control node PD_ox_i and the first signal terminal VDD/PU are used to transmit the first signal level (eg, high level) provided by the first signal terminal VDD/PU to the second denoising control node PD_ox_i, so as to realize the Control of the level of the second de-noising control node PD_ox_i; the turned-on sixth transistor T6 connects the first de-noising control node PD_ox and the first signal terminal VDD/PU to connect the first signal terminal VDD/PU to the first signal terminal VDD/PU.
  • the first signal level eg, high level
  • the signal level (for example, a high level) is transmitted to the first de-noising control node PD_ox, so as to control the level of the first de-noising control node PD_ox, and then the fourth transistor T4 can be turned on (ie, the de-noising circuit is turned off) 122).
  • the output circuit 121 may be implemented as the seventh transistor T7 shown in FIG. 8 .
  • the gate of the seventh transistor T7 is connected to the second signal terminal to receive the turn-on control signal
  • the first pole of the seventh transistor T7 is connected to the third clock signal terminal CK2 to receive the third clock signal CK2
  • the second terminal of the seventh transistor T7 The pole is connected to the second output terminal OUT.
  • the second signal terminal may be connected to the second node PD_o in the first shift register circuit module 110 , in this case, the level change of the second node PD_o forms the turn-on control signal.
  • the seventh transistor T7 When the turn-on control signal is at an active level (eg, a low level), the seventh transistor T7 is turned on, connecting the third clock signal terminal CK2 and the second output terminal OUT, so as to connect the third clock signal terminal CK2 to the second output terminal OUT.
  • the three clock signal CK2 is output to the second output terminal OUT as the second output signal.
  • Fig. 9 is a schematic diagram of a circuit structure of a specific implementation example of the second shift register circuit module 120 shown in Fig. 7 . As shown in FIG. 9 , based on the circuit structure shown in FIG. 8 , the second shift register circuit module 120 further includes a third transistor T3 for implementing the second control circuit 1246 . It should be noted that other circuit structures of the second shift register circuit module 120 shown in FIG. 9 are basically the same as those of the second shift register circuit module 120 shown in FIG. 8 , and details are not repeated here.
  • the second terminal of the first capacitor C1 is connected to the second clock signal terminal CB1 through the third transistor T3.
  • the gate of the third transistor T3 is connected to the second output terminal OUT
  • the first pole of the third transistor T3 is connected to the second clock signal terminal CB1
  • the second pole of the third transistor T3 is connected to the second terminal of the first capacitor C1 .
  • the third transistor T3 is turned off in response to the second output signal, thereby cutting off the second clock signal terminal CB1 and the first clock signal terminal CB1
  • the connection between the capacitors C1 makes the potential change of the second clock signal CB1 not affect the first capacitor C1, thereby eliminating the unfavorable coupling of the first capacitor C1 under the potential change of the second clock signal CB1.
  • the level of the second output terminal OUT (eg, low level) can turn on the third transistor T3, so that the second clock signal CB1 can be transmitted to the first capacitor C1 through the turned on third transistor T3.
  • FIG. 10 is a schematic diagram of a circuit structure of a specific implementation example of a shift register unit provided by some embodiments of the present disclosure.
  • the second shift register circuit module 120 in the shift register unit may be implemented as the second shift register circuit module 120 shown in FIG. 8 ; it should be understood that the shift register shown in FIG. 10
  • the second shift register circuit module 120 in the register unit can also be implemented as the second shift register circuit module 120 shown in FIG. 9 ; this is not limited in the embodiment of the present disclosure.
  • the first shift register circuit module 110 in the shift register unit may include first to eighth switch transistors M1 ⁇ M8 and a fourth capacitor C4 and a fifth capacitor C5 .
  • the gate of the first switch transistor M1 is connected to the fourth clock signal terminal CK3 to receive the fourth clock signal CK3, the second pole of the first switch transistor M1 is connected to the input terminal IN, and the first pole of the first switch transistor M1 is connected to the first switch transistor M1.
  • the three nodes PD_in are connected; the gate of the second switch transistor M2 is connected to the third node PD_in, the second pole of the second switch transistor M2 is connected to the fourth clock signal terminal CK3 to receive the fourth clock signal CK3, and the second switch transistor M2
  • the first pole of the third switch transistor M3 is connected to the first node PU; the gate of the third switch transistor M3 is connected to the fourth clock signal terminal CK3 to receive the fourth clock signal CK3, and the second pole of the third switch transistor M3 is connected to the first voltage terminal VSS connected to receive the first voltage VSS (for example, the first voltage VSS is at a low level), the first pole of the third switch transistor M3 is connected to the first node PU; the gate of the fourth switch transistor M4 is connected to the first node PU , the first pole of the fourth switch transistor M4 is connected to the second voltage terminal VDD to receive the second voltage VDD (for example, the second voltage VDD is at a high level), and the second pole of the fourth switch
  • FIG. 12 is a signal timing diagram when the shift register unit shown in FIG. 10 operates.
  • the operation principle of the shift register unit shown in FIG. 10 is briefly described below with reference to the signal timing diagram shown in FIG. 12 .
  • the working process of the shift register unit shown in FIG. 10 includes three stages, namely the first stage P1 (also called the input stage), the second stage P2 (also called the output stage) and the holding stage Phase P3 (including the first holding phase P31, the second holding phase P32, etc.).
  • Figure 12 shows the timing waveforms of the respective signals in each stage.
  • the potential levels of the signal timing diagram shown in FIG. 12 are only schematic and do not represent real potential values or relative proportions.
  • the low-level signal corresponds to the P-type
  • the turn-on signal of the transistor and the high-level signal corresponds to the turn-off signal of the P-type transistor.
  • the first clock signal CK1, the third clock signal CK2 and the fourth clock signal CK3 are at a low level
  • the second clock signal CB1 and the fifth clock signal CB3 are at a high level
  • the input terminal IN is at a low level (ie, the input terminal IN receives a low-level input signal), so that the first transistor T1 is turned on, the switching transistors M1 and M3 are turned on, and the switching transistor M7 is turned off.
  • the turned-on switch transistor M1 transmits a low-level input signal to the third node PD_in, so that the level of the third node PD_in becomes a low level, so that the switch transistor M2 is turned on; since the switch transistor M8 responds to the first voltage VSS (low level) is always in the on state, so the level of the second node PD_o is the same as the level of the third node PD_in, that is, the low level, so the low level is stored in the fifth capacitor C5, And the switch transistor M5 is turned on; the turned-on switch transistor M3 transmits the first voltage VSS (low level) to the first node PU, and the turned-on switch transistor M2 transmits the low level of the fourth clock signal CK3 to the first node PU.
  • the switching transistor M4 is turned on in response to the low level of the first node PU, and the second voltage VDD (high level) is output to the first output terminal GP, at the same time, the switching transistor M5 is turned on in response to the low level of the second node PD_o, and transmits the high level of the fifth clock signal CB3 to the first output terminal GP, so that at At this stage, the first output terminal GP of the shift register unit outputs a high level, and accordingly, the fifth transistor T5 and the sixth transistor T6 are turned off in response to the high level of the first output terminal GP;
  • the transistor T1 transmits the first voltage VSS (low level) to the second denoising control node PD_ox_i, so that the level of the second denoising control node PD_ox_i becomes a low level, and is stored in the first capacitor C1 and the second denoising control no
  • the first clock signal CK1, the third clock signal CK2 and the fourth clock signal CK3 are at high level
  • the second clock signal CB1 and the fifth clock signal CB3 are at low level
  • the input terminal IN is at a high level, so that the first transistor T1 is turned off, the switching transistors M1 and M3 are turned off, and the switching transistor M7 is turned on.
  • the third node PD_in and the second node PD_o can continue to maintain the low level of the previous stage, so that the switching transistors M2 and M5 are turned on; the turned-on transistor M2 turns on the fourth clock signal CK3
  • the high level is transmitted to the first node PU, so that the level of the first node PU becomes a high level; the switching transistor M4 is turned off in response to the high level of the first node PU, avoiding the second voltage VDD (high level).
  • the turned-on switching transistor M5 transmits the low level of the fifth clock signal CB3 to the first output terminal GP, so that at this stage, the first output terminal GP of the shift register unit outputs Low level, that is to output the first output signal, for example, the first output signal can be used as the input signal of the next stage shift register unit, and of course can also be used to control the pixel circuit S shown in FIG.
  • the fifth transistor T5 and the sixth transistor T6 are turned on in response to the low level of the first output terminal GP, and transmit the second voltage VDD (high level) to the second denoising control nodes PD_ox_i and PD_ox_i respectively.
  • the first de-noising control node PD_ox so that the levels of the second de-noising control node PD_ox_i and the first de-noising control node PD_ox become high level, correspondingly, the fourth transistor T4 is turned off; the seventh transistor T7 responds to the The low level of the two nodes PD_o is turned on, and the high level of the third clock signal CK2 is transmitted to the second output terminal OUT; thus, at this stage, the second output terminal OUT of the shift register unit outputs a high level, that is, A second output signal is output, for example, the second output signal can be used to control the operation of an N-type transistor in, for example, the pixel circuit S shown in FIG. 1 .
  • the first clock signal CK1, the third clock signal CK2 and the fourth clock signal CK3 are at low level, the second clock signal CB1 and the fifth clock signal CB3
  • the first transistor T1 is turned on, the switching transistors M1 and M3 are turned on, and the switching transistor M7 is turned off.
  • the turned-on switching transistor M1 transmits the high level of the input terminal IN to the third node PD_in and the second node PD_o (the transistor M8 is always on), so that the levels of the third node PD_in and the second node PD_o change.
  • the switch transistors M2 and M5 are turned off;
  • the switched transistor M3 that is turned on transmits the first voltage VSS (low level) to the first node PU, so that the level of the first node PU becomes low voltage level, and stored in the fourth capacitor C4;
  • the switching transistor M4 is turned on in response to the low level of the first node PU, and outputs the second voltage VDD (high level) to the first output terminal GP, thus, here
  • the first output terminal GP of the shift register unit outputs a high level, and accordingly, the fifth transistor T5 and the sixth transistor T6 are turned off in response to the high level of the first output terminal GP;
  • T1 transmits the first voltage VSS (low level) to the second denoising control node PD_ox_i, so that the level of the second denoising control node PD_ox_i becomes a low level, and is stored in the first capacitor C1 and the second capacitor In C2;
  • the second transistor T2 is turned on under the
  • the first clock signal CK1, the third clock signal CK2 and the fourth clock signal CK3 are at high level, the second clock signal CB1 and the fifth clock signal CB3
  • the first transistor T1 is turned off, the switching transistors M1 and M3 are turned off, and the switching transistor M7 is turned on.
  • the third node PD_in and the second node PD_o can continue to maintain the high level of the previous stage, so that the switching transistors M2 and M5 are turned off; due to the storage function of the fourth capacitor C4, the first node PU Continue to maintain the low level of the previous stage, so that the switch transistors M4 and M6 remain on; the second voltage VDD (high level) is transmitted to the third node PD_in through the on-off switch transistor M6 and the on-off switch transistor M7 and the second node PD_o, so that the third node PD_in and the second node PD_o continue to maintain a high level, effectively preventing the switch transistor M5 from being turned on, thereby avoiding false output; at the same time, the turned-on switch transistor M4 will The two voltages VDD (high level) are output to the first output terminal GP, so at this stage, the first output terminal GP of the shift register unit outputs a high level, and accordingly, the fifth transistor
  • the level change of the second denoising control node PD_ox_i and the level change of the first denoising control node PD_ox in the holding phase P3 will be described in detail below.
  • the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are always kept in an off state. Therefore, the level of the second de-noising control node PD_ox_i and the level of the first de-noising control node PD_ox It is only affected by the first transistor T1 , the second transistor T2 , the first capacitor C1 , the second capacitor C2 , and the third capacitor C3 , that is, only by the second denoising control circuit 124 .
  • the influence of the threshold voltage of the first transistor T1 and the threshold voltage of the second transistor T2 is ignored.
  • the first transistor T1 is turned on, the level of the second denoising control node PD_ox_i is VSS, and the level of the end of the first capacitor C1 connected to the second clock signal terminal CB1 is high ( If it is set to a high level VDD), the second transistor T2 is turned on, and the level of the first denoising control node PD_ox is also VSS.
  • the first holding phase P31 and the second holding phase P32 will appear alternately;
  • the noise control node PD_ox and the second de-noise control node PD_ox_i will be coupled multiple times until the level of the first de-noise control node PD_ox is stabilized near VSS+(VSS-VDD)*C1/C PD_ox_i , thereby making the first de-noise control node PD_ox stable.
  • the four transistors T4 are continuously turned on in the holding phase P3, and the second output terminal OUT is continuously de-noised; at the same time, by properly setting the capacitance values of the first capacitor C1 and the second capacitor C2, the voltage of the first de-noising control node PD_ox can be reduced.
  • the biasing effect on the fourth transistor T4 is reduced to prolong the working life of the shift register unit 100 .
  • the influence of the threshold voltage of the first transistor T1 and the threshold voltage of the second transistor T2 is considered.
  • the first transistor T1 is turned on, the level of the second denoising control node PD_ox_i is VSS+
  • the first holding phase P31 and the second holding phase P32 will appear alternately; Coupling is performed between the noise control node PD_ox and the second noise removal control node PD_ox_i multiple times until the level of the first noise removal control node PD_ox stabilizes at VSS+
  • the fourth transistor T4 is continuously turned on in the holding phase P3, and the second output terminal OUT is continuously de-noised; at the same time, by reasonably setting the capacitance values of the first capacitor C1 and the second capacitor C2, the first noise reduction can be reduced.
  • the level of the noise control node PD_ox acts on the bias of the fourth transistor T4 to prolong the working life of the shift register unit 100 .
  • the timing waveforms of the respective clock signals shown in FIG. 12 are schematic.
  • the first clock signal CK1 and the fourth clock signal CK3 may be the same, and the second clock signal CB1 and the fifth clock signal CB3 may be the same; in this case, the first clock signal terminal CK1 may be complexed It is used as the fourth clock signal terminal CK3, and the second clock signal terminal CB1 is multiplexed as the fifth clock signal terminal CB3. It should be noted that the embodiments of the present disclosure do not limit this.
  • FIG. 11 is a schematic diagram of a circuit structure of another specific implementation example of a shift register unit provided by some embodiments of the present disclosure.
  • the second shift register circuit module 120 in the shift register unit can be implemented as the second shift register circuit module 120 shown in FIG. 8 .
  • the clock signal terminals GCK3, GCK1 and GCKO respectively correspond to the first clock signal terminal CK1, the second clock signal terminal CB1, and the third clock signal terminal CK2 in FIG. 8, that is, the clock signal terminal GCK3 is the first clock signal terminal, and the clock signal terminal GCK1 is
  • the second clock signal terminal, the clock signal terminal GCKO is the third clock signal terminal; it should be understood that the second shift register circuit module 120 in the shift register unit shown in FIG. 11 can of course also be implemented as shown in FIG. 9 .
  • the second shift register circuit module 120 the embodiment of the present disclosure does not limit this.
  • the first shift register circuit module 110 in the shift register unit may include eleventh to twentieth switch transistors M11 ⁇ M20 and a sixth capacitor C6 and a seventh capacitor C7 .
  • the gate of the eleventh switch transistor M11 is connected to the second clock signal terminal GCK1 to receive the second clock signal GCK1, the second pole of the eleventh switch transistor M11 is connected to the input terminal IN to receive the input signal, and the eleventh switch transistor
  • the first pole of M11 is connected to the third node PD_in;
  • the gate of the twelfth switch transistor M2 is connected to the second clock signal terminal GCK1 to receive the second clock signal GCK1, and the second pole of the twelfth switch transistor M12 is connected to the third
  • the node PD_in is connected, the first pole of the twelfth switch transistor M12 is connected to the second node PD_o; the gate of the thirteenth switch transistor M13 is connected to the second node PD_o, and the first pole of the thirteenth switch transistor M13 is connected
  • the six clock signal terminals GCK2 are connected to receive the sixth clock signal GCK2, the second pole of the thirteenth switching transistor M13 is connected to the first output terminal GP; the first terminal of the seventh capacitor C7 is connected to the second node PD_o, and the seventh capacitor
  • the second terminal of C7 is connected to the first output terminal GP;
  • the gate of the fourteenth switch transistor M14 is connected to the first node PU, and the first pole of the fourteenth switch transistor M14 is connected to the second voltage terminal VDD to receive the second voltage VDD (for example, the second voltage VDD is at a high level), the second pole of the fourteenth switch transistor M14 is connected to the first output terminal GP;
  • the first terminal of the sixth capacitor C6 is connected to the first node PU, and the sixth The second terminal of the capacitor C6 is connected to the second voltage terminal VDD;
  • the gate of the fifteenth switch transistor M15 is connected to the first clock signal terminal GCK3 to receive the first clock signal, and the first pole of the fifteenth switch transistor M
  • a node PU is connected, and the second pole of the fifteenth switch transistor M15 is connected to the first voltage terminal VSS to receive the first voltage VSS (for example, the first voltage VSS is at a low level); the gate of the sixteenth switch transistor M16 connected to the first node PU, the first pole of the sixteenth switch transistor M16 is connected to the second voltage terminal VDD to receive the second voltage VDD, the second pole of the sixteenth switch transistor M16 is connected to the fourth node PD_f; the tenth The gate of the seventeenth switch transistor M17 is connected to the first node PU, the first pole of the seventeenth switch transistor M17 is connected to the fourth node PD_f, and the second pole of the seventeenth switch transistor M17 is connected to the second node PD_o; The gate of the eighteenth switch transistor M18 is connected to the second node PD_o, the first pole of the eighteenth switch transistor M18 is connected to the fourth node PD_f, and the first pole of the eighteenth switch transistor
  • FIG. 13 is a signal timing diagram when the shift register unit shown in FIG. 11 operates.
  • the working principle of the shift register unit shown in FIG. 11 is briefly described below with reference to the signal timing diagram shown in FIG. 13 .
  • the working process of the shift register unit shown in FIG. 11 includes three stages, namely the first stage P1 (also called the input stage), the second stage P2 (also called the output stage) and the hold The phases include a first holding phase P31, a second holding phase P32, etc.).
  • Figure 13 shows the timing waveforms of the respective signals in each stage.
  • the level of the potential in the signal timing diagram shown in FIG. 13 is only schematic and does not represent the actual potential value or relative ratio.
  • the low level signal corresponds to the P-type
  • the turn-on signal of the transistor and the high-level signal corresponds to the turn-off signal of the P-type transistor.
  • the first clock signal GCK3 is at a high level
  • the second clock signal GCK1 is at a low level
  • the third clock signal GCKO is at a low level
  • the sixth clock signal GCK2 is at a high level
  • the input terminal IN is at a low level (ie the input terminal IN receives a low level input signal), so the first transistor T1 is turned off, the switching transistors M11, M12 and M19 are turned on, and the switching transistor M15 is turned off.
  • the turned-on switching transistor M19 transmits the second voltage VDD (high level) to the first node PU, so that the level of the first node PU becomes a high level, and is stored in the sixth capacitor C6, accordingly, the switch The transistors M14, M16, and M17 are turned off; the turned-on switching transistors M11 and M12 transmit the low-level input signal IN to the second node PD_o, so that the level of the second node PD_o becomes a low level, and is stored in the seventh In the capacitor C7; the switching transistor M13 is turned on in response to the low level of the second node PD_o, and transmits the high level of the sixth clock signal GCK2 to the first output terminal GP, so that at this stage, the first An output terminal GP outputs a high level, correspondingly, the switching transistor M20, the fifth transistor T5 and the sixth transistor T6 are turned off in response to the high level of the first output terminal GP; in addition, the seventh transistor M7 responds to the second node
  • the first clock signal GCK3 is at a high level
  • the second clock signal GCK1 is at a high level
  • the third clock signal GCKO is at a high level
  • the sixth clock signal GCK2 is at a low level If the input terminal IN is at a high level, the first transistor T1 is turned off, and the switching transistors M11, M12, M15, and M19 are turned off.
  • the first node PU can continue to maintain the high level of the previous stage, so that the switching transistors M14, M16 and M17 are still turned off; due to the storage function of the seventh capacitor C7, the second node PD_o can continue to The low level of the previous stage is maintained, so that the switching transistor M13 is still turned on; the turned-on switching transistor M13 transmits the low level of the sixth clock signal GCK2 to the first output terminal GP, so that, in this stage, the shift The first output terminal GP of the register unit outputs a low level, that is, the first output signal is output.
  • the first output signal can be used as the input signal of the next-stage shift register unit, and of course, it can also be used to control, for example, as shown in FIG. 1 .
  • the P-type transistor in the shown pixel circuit S works; the switching transistor M20 is turned on in response to the low level of the first output terminal GP (ie, the first output signal), and transmits the low level of the sixth clock signal GCK2 to the first output terminal GP.
  • the fourth transistor T4 Turn off; the seventh transistor T7 is still turned on under the control of the low level of the second node PD_o, and transmits the high level of the third clock signal GCKO to the second output terminal OUT; thus, at this stage, the shift register
  • the second output terminal OUT of the unit outputs a high level, that is, outputs a second output signal, for example, the second output signal can be used to control the operation of the N-type transistor in the pixel circuit S shown in FIG.
  • the pulse width of the high pulse of the third clock signal GCKO is smaller than the pulse width of the low pulse of the clock signal GCK1/2/3, so the pulses (including the rising edge and the falling edge) of the third clock signal GCKO can be all transmitted to the second output terminal OUT.
  • the first clock signal GCK3 is at a low level
  • the second clock signal GCK1 is at a high level
  • the third clock signal GCKO is at a low level
  • the sixth clock signal is at a low level GCK2 is at a high level
  • the input terminal IN is at a high level, so that the first transistor T1 is turned on, the switching transistors M11 , M12 and M19 are turned off, and the switching transistor M15 is turned on.
  • the turned-on switching transistor M15 transmits the first voltage VSS (low level) to the first node PU, so that the level of the first node PU becomes a low level, and is stored in the sixth capacitor C6, correspondingly,
  • the switch transistors M14, M16, and M17 are turned on; the turned-on switch transistors M16 and M17 transmit the second voltage VDD (high level) to the second node PD_o, so that the level of the second node PD_o becomes a high level, and stored in the seventh capacitor C7, correspondingly, the switch transistor M13 is turned off; the switch transistor M14 that is turned on outputs the second voltage VDD (high level) to the first output terminal GP, so that at this stage, the shift register
  • the first output terminal GP of the unit outputs a high level, and accordingly, the switching transistor M20, the fifth transistor T5 and the sixth transistor T6 are turned off in response to the high level of the first output terminal GP; in addition, the turned-on first transistor T1
  • the first clock signal GCK3 is at a high level
  • the second clock signal GCK1 is at a low level
  • the third clock signal GCKO is at a low level
  • the sixth clock signal is at a low level GCK2 is at a high level
  • the input terminal IN is at a high level, so that the first transistor T1 is turned on, and the switching transistors M11 , M12 , M15 , and M19 are turned off.
  • the first node PU can continue to maintain the low level of the previous stage, and accordingly, the switching transistors M14, M16, and M17 remain on; VDD (high level) is transmitted to the second node PD_o, so that the level of the second node PD_o is kept at a high level, correspondingly, the switching transistor M13 is turned off; level) is output to the first output terminal GP, so that at this stage, the first output terminal GP of the shift register unit outputs a high level, and accordingly, the switching transistor M20, the fifth transistor T5 and the sixth transistor T6 respond to the first The high level of an output terminal GP is turned off; in addition, the second clock signal GCK1 changes from high level to low level, due to the bootstrap effect of the first capacitor C1, the power supply of the second denoising control node PD_ox_i in the floating state The level is further pulled down, and at the same time, due to the coupling effect of the second capacitor C2, the level change of
  • the level of the first node PU is kept at a low level, and the level of the second node PD_o is kept at a high level. Accordingly, the first output terminal GP keeps outputting a high level, and the first The five transistors T5, the sixth transistor T6, and the seventh transistor T7 are always in the off state. Therefore, the level of the second de-noising control node PD_ox_i and the level of the first de-noising control node PD_ox are only affected by the first transistor T1, the second transistor T2 , the first capacitor C1 , the second capacitor C2 , and the third capacitor C3 are only affected by the second denoising control circuit 124 .
  • the level change of the second denoising control node PD_ox_i and the level change of the first denoising control node PD_ox in the holding phase P3 of the shift register unit shown in FIG. 11 can refer to the shift register shown in FIG. 10 .
  • the related description of the level change of the second denoising control node PD_ox_i and the level change of the first denoising control node PD_ox in the holding phase P3 will not be repeated here.
  • timing waveforms of each clock signal shown in FIG. 13 are schematic, and are not limited by the embodiments of the present disclosure.
  • the first shift register circuit module 110 in the shift register unit 100 provided by the embodiments of the present disclosure is not limited to the circuit structure of the first shift register circuit module 110 shown in FIG. 10 and FIG. 11 . As long as it can output the first output signal at the first output terminal GP according to the input signal received by the input terminal and provide the turn-on control signal to the second shift register circuit module 120, the embodiment of the present disclosure does not limit this.
  • the “active level” of the shift register unit refers to a level that can make the operated transistors included in the shift register unit turned on, and correspondingly, the “inactive level” refers to the A level at which the operated transistor it includes cannot be turned on (ie, the transistor is turned off).
  • the active level may be higher or lower than the inactive level depending on factors such as the type of transistors (N-type or P-type) in the circuit structure of the shift register unit. For example, in the embodiment of the present disclosure, when each transistor is a P-type transistor, the active level is a low level, and the inactive level is a high level.
  • the capacitor may be a capacitor device fabricated by a technological process, for example, the capacitor device may be realized by fabricating a special capacitor electrode, and each electrode of the capacitor may be made of a metal layer, a semiconductor layer (eg, a doped electrode).
  • the capacitance can also be a parasitic capacitance between various devices, which can be realized by the transistor itself and other devices and lines.
  • the connection mode of the capacitor is not limited to the above-described mode, and can also be other applicable connection modes, as long as the level of the corresponding node can be stored.
  • each node does not represent an actual component, but represents a junction of related electrical connections in a circuit diagram.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors, field effect transistors, or other switching devices with the same characteristics, and the thin film transistors are used as examples for description in the embodiments of the present disclosure.
  • the source and drain of the transistor used here may be symmetrical in structure, so the source and drain of the transistor may be indistinguishable in structure.
  • one pole is directly described as the first pole, and the other pole is the second pole.
  • the transistors in the embodiments of the present disclosure are all described by taking a P-type transistor as an example.
  • the first electrode of the transistor is the source electrode
  • the second electrode is the drain electrode.
  • the present disclosure includes but is not limited to this.
  • one or more transistors in the shift register unit 100 provided by the embodiments of the present disclosure may also adopt N-type transistors.
  • the first electrode of the transistor is the drain electrode
  • the second electrode is the source electrode.
  • Each pole of a transistor of a certain type is connected correspondingly with reference to each pole of the corresponding transistor in the embodiment of the present disclosure, and the corresponding high voltage or low voltage may be provided at the corresponding voltage terminal.
  • Indium Gallium Zinc Oxide (IGZO) can be used as the active layer of the thin film transistor. As the active layer of the thin film transistor, it can effectively reduce the size of the transistor and prevent leakage current.
  • IGZO Indium Gallium Zinc Oxide
  • the shift register unit by introducing a charge pump structure formed by a first control circuit, a first coupling circuit, a second coupling circuit, a transmission circuit, and a storage circuit into the second denoising control circuit, using The adjustment effect of the charge pump structure on the voltage can adjust the level of the first denoising control node; thus, on the one hand, it ensures that the denoising circuit is continuously turned on in the hold phase to remove noise interference in time, and on the other hand, reduces the first denoising The level of the control node has a biasing effect on the denoising circuit, and prolongs the working life of the shift register unit.
  • the gate driving circuit includes a plurality of cascaded shift register units RS (as shown by RS_1 , RS_2 , .
  • the register unit RS may adopt the structure of the shift register unit 100 provided by any embodiment of the present disclosure or a modification thereof, for example, the shift register unit 100 shown in FIG. 10 or FIG. 11 may be adopted.
  • the gate driving circuit can be directly integrated on the array substrate of the display device using the same semiconductor manufacturing process as the thin film transistor, so as to realize the progressive or interlaced scanning driving function.
  • the input terminal IN of the other stage shift register units and the first output terminal of the previous stage shift register unit GP connection may be configured to receive the trigger signal STV.
  • the working principle of each stage of the shift register unit in the gate driving circuit reference may be made to the corresponding description of the working principle of the shift register unit provided in the embodiments of the present disclosure, which will not be repeated here.
  • the display device may include the gate driving circuit provided by any embodiment of the present disclosure.
  • the display device may further include a display panel 01 , the display panel 01 includes a plurality of sub-pixels P arranged in an array, and each sub-pixel P includes a pixel circuit S.
  • the display panel 01 further includes a plurality of gate lines GL (as shown by G_1 , G_2 , .
  • the second output terminal OUT of the bit register unit RS is connected to at least one gate line of the plurality of gate lines GL, so as to provide scan signals to the pixel circuits S of the corresponding row respectively.
  • the display device may further include a data driving circuit.
  • the data driving circuit is connected to the pixel circuit S through the data line DL (Data Line, as shown in D_1, D_2, . to the pixel array.
  • the display device in this embodiment can be any product or component with a display function, such as a display, an OLED panel, an OLED TV, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, etc.
  • a display such as a display, an OLED panel, an OLED TV, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, etc.
  • the embodiments of the present disclosure do not limit this.
  • At least one embodiment of the present disclosure further provides a method for driving a shift register unit, which can be used to drive the shift register unit 100 provided by the embodiment of the present disclosure.
  • the driving method includes a hold phase; wherein, in the hold phase, the first clock signal CK1 and the second clock signal CB1 are alternately input, and the level of the first denoising control node PD_ox is adjusted by the second denoising control circuit 124, The denoising circuit 122 is turned on, so that the denoising circuit 122 denoises the second output terminal OUT.
  • the driving method includes a hold phase; wherein, in the hold phase, the first clock signal CK1 and the second clock signal CB1 are alternately input, and the level of the first denoising control node PD_ox is adjusted by the second denoising control circuit 124, The denoising circuit 122 is turned on, so that the denoising circuit 122 denoises the second output terminal OUT.

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Abstract

一种移位寄存器单元及驱动方法、栅极驱动电路和显示装置。该移位寄存器单元包括：第二去噪控制电路，被配置为调节第一去噪控制节点的电平，以开启去噪电路。第二去噪控制电路包括：第一控制电路，被配置为在第一时钟信号的控制下，将第一电压传输至第二去噪控制节点；第一耦合电路，被配置为存储第二去噪控制节点的电平，以及在第二时钟信号的控制下调节第二去噪控制节点的电平；第二耦合电路，被配置为降低第一耦合电路调节第二去噪控制节点的电平的调节量；传输电路，被配置为连接第一去噪控制节点和第二去噪控制节点，以平衡第一去噪控制节点的电平和第二去噪控制节点的电平；存储电路，被配置为存储第一去噪控制节点的电平。

Description

移位寄存器单元及驱动方法、栅极驱动电路、显示装置 技术领域
本公开的实施例涉及一种移位寄存器单元及驱动方法、栅极驱动电路和显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板具有薄、轻、宽视角、主动发光、发光颜色连续可调、成本低、响应速度快、能耗小、驱动电压低、工作温度范围宽、生产工艺简单、发光效率高及可柔性显示等优点，在手机、平板电脑、数码相机等显示领域的应用越来越广泛。
有机发光二极管显示面板的像素阵列通常包括多行栅线和与之交错的多列数据线。对栅线的驱动可以通过绑定的集成驱动电路实现。近几年随着非晶硅薄膜晶体管或氧化物薄膜晶体管制备工艺的不断提高，也可以将栅极驱动电路直接集成在薄膜晶体管阵列基板上构成GOA(Gate driver On Array)来对栅线进行驱动。例如，可以采用由多个级联的移位寄存器单元构成的GOA为像素阵列的多行栅线提供开关态电压信号(扫描信号)，从而例如控制多行栅线依序打开，并且同时由数据线向像素阵列中对应行的像素单元提供数据信号，以在各像素单元形成显示图像的各灰阶所需要的灰度电压，进而显示一帧图像。目前的显示面板越来越多地采用GOA技术来对栅线进行驱动。GOA技术有助于实现显示面板的窄边框设计，并且可以降低显示面板的生产成本。
发明内容
本公开至少一些实施例提供一种移位寄存器单元。该移位寄存器单元包括：第一移位寄存器电路模块和第二移位寄存器电路模块。所述第一移位寄存器电路模块被配置为根据输入端接收的输入信号在第一输出端输出第一输出信号以及向所述第二移位寄存器电路模块提供开启控制信号。所述第二移位寄存器电路模块包括输出电路、去噪电路、第一去噪控制电路和第二去噪控制电路，所述输出电路被配置为响应于所述开启控制信号，在第二输出端输出第二输出信号，所述去噪电路被配置为在第一去噪控制节点的电平的控制下，对所述第二输出端去噪，所述第一去噪控制电路被配置为响应于所述第一输出信号，控制所述第一去噪控制节点的电平，以关闭所述去噪电路，所述第二去噪控制电路被配置为在第一时钟信号和第二时钟信号的控制下，调节所述第一去噪控制节点的电平，以开启所述去噪电路。所述第二去噪控制电路包括第一控制电路、第一耦合电路、第二耦合电路、传输电路和存储电路，所述第一控制电路被配置为在第一时钟信号的控制下，将第一电压传输至第二去噪控制节点，所述第一耦合电路被配置为存储所述第二去噪控制节点的电平，以及在第二时钟信号的控制下调节所述第二去噪控制节点的电平，所述第二耦合电路被配置为存储所述第二去噪控制节点的电平，以及降低所述第一耦合电路调节所述第二去噪控 制节点的电平的调节量，所述传输电路被配置为连接所述第一去噪控制节点和所述第二去噪控制节点，以平衡所述第一去噪控制节点的电平和所述第二去噪控制节点的电平，所述存储电路被配置为存储所述第一去噪控制节点的电平。
例如，在本公开一些实施例提供的移位寄存器单元中，所述第一控制电路包括第一晶体管，所述第一耦合电路包括第一电容，所述第二耦合电路包括第二电容，所述传输电路包括第二晶体管，所述存储电路包括第三电容；所述第一晶体管的栅极与第一时钟信号端连接以接收所述第一时钟信号，所述第一晶体管的第一极与第一电压端连接以接收所述第一电压，所述第一晶体管的第二极与第二去噪控制节点连接；所述第一电容的第一端与所述第二去噪控制节点连接，所述第一电容的第二端与第二时钟信号端连接以接收所述第二时钟信号；所述第二电容的第一端与所述第二去噪控制节点连接，所述第二电容的第二端与所述第一电压端连接；所述第二晶体管的栅极与所述第二去噪控制节点连接，所述第二晶体管的第一极与所述第一去噪控制节点连接，所述第二晶体管的第二极与所述第二去噪控制节点连接；所述第三电容的第一端与所述第一去噪控制节点连接，所述第三电容的第二端与所述第一电压端连接。
例如，在本公开一些实施例提供的移位寄存器单元中，所述第二去噪控制电路还包括第二控制电路，所述第二控制电路被配置为在所述第二输出端的电平的控制下，将所述第二时钟信号传输至所述第一耦合电路。
例如，在本公开一些实施例提供的移位寄存器单元中，所述第二控制电路包括第三晶体管，所述第一电容的第二端通过所述第三晶体管与所述第二时钟信号端连接，所述第三晶体管的栅极与所述第二输出端连接，所述第三晶体管的第一极与所述第二时钟信号端连接，所述第三晶体管的第二极与所述第一电容的第二端连接。
例如，在本公开一些实施例提供的移位寄存器单元中，所述去噪电路被配置为在所述第一去噪控制节点的电平的控制下，将所述第一电压传输至所述第二输出端，以对所述第二输出端去噪。
例如，在本公开一些实施例提供的移位寄存器单元中，所述去噪电路包括第四晶体管，所述第四晶体管的栅极与所述第一去噪控制节点连接，所述第四晶体管的第一极与第一电压端连接以接收所述第一电压，所述第四晶体管的第二极与所述第一输出端连接。
例如，在本公开一些实施例提供的移位寄存器单元中，在所述第二去噪控制电路的调节下，所述第一去噪控制节点的电平与所述第一电压的差为所述去噪电路的阈值电压的n倍，其中，1≤n≤10。
例如，在本公开一些实施例提供的移位寄存器单元中，所述第一去噪控制电路还被配置为响应于所述第一输出信号，控制所述第二去噪控制节点的电平。
例如，在本公开一些实施例提供的移位寄存器单元中，所述第一去噪控制电路包括第五晶体管和第六晶体管；所述第五晶体管的栅极与所述第一输出端连接以接收所述第一输出信号，所述第五晶体管的第一极与第一信号端连接以接收第一信号电平，所述第五晶体 管的第二极与所述第一去噪控制节点连接；所述第六晶体管的栅极与所述第一输出端连接以接收所述第一输出信号，所述第六晶体管的第一极与所述第一信号端连接以接收所述第一信号电平，所述第六晶体管的第二极与所述第二去噪控制节点连接。
例如，在本公开一些实施例提供的移位寄存器单元中，所述第一信号端为用于提供第二电压的第二电压端，所述第一信号电平为所述第二电压；或者，所述第一信号端与所述第一移位寄存器电路模块中的第一节点连接，所述第一信号电平为所述第一节点的电平。
例如，在本公开一些实施例提供的移位寄存器单元中，所述输出电路包括第七晶体管，所述第七晶体管的栅极与第二信号端连接以接收所述开启控制信号，所述第七晶体管的第一极与第三时钟信号端连接以接收第三时钟信号，所述第七晶体管的第二极与所述第二输出端连接。
例如，在本公开一些实施例提供的移位寄存器单元中，所述第二信号端与所述第一移位寄存器电路模块中的第二节点连接。
例如，在本公开一些实施例提供的移位寄存器单元中，所述第一移位寄存器电路模块包括：第一开关晶体管、第二开关晶体管、第三开关晶体管、第四开关晶体管、第五开关晶体管、第六开关晶体管、第七开关晶体管、第八开关晶体管、第四电容和第五电容；所述第一开关晶体管的栅极与第四时钟信号端连接以接收第四时钟信号，所述第一开关晶体管的第一极与第三节点连接，所述第一开关晶体管的第二极与所述输入端连接；所述第二开关晶体管的栅极与第三节点连接，所述第二开关晶体管的第一极与第一节点连接，所述第二开关晶体管的第二极与所述第四时钟信号端连接以接收所述第四时钟信号；所述第三开关晶体管的栅极与所述第四时钟信号端连接以接收所述第四时钟信号，所述第三开关晶体管的第一极与所述第一节点连接，所述第三开关晶体管的第二极与第一电压端连接以接收第一电压；所述第四开关晶体管的栅极与所述第一节点连接，所述第四开关晶体管的第一极与第二电压端连接以接收第二电压，所述第四开关晶体管的第二极与所述第一输出端连接；所述第四电容的第一端与所述第一节点连接，所述第四电容的第二端与所述第二电压端连接；所述第五开关晶体管的栅极与第二节点连接，所述第五开关晶体管的第一极与第五时钟信号端连接以接收第五时钟信号，所述第五开关晶体管的第二极与所述第一输出端连接；所述第五电容的第一端与所述第二节点连接，所述第五电容的第二端与所述第一输出端连接；所述第六开关晶体管的栅极与所述第一节点连接，所述第六开关晶体管的第一极与所述第二电压端连接以接收所述第二电压，所述第六开关晶体管的第二极与第四节点连接；所述第七开关晶体管的栅极与所述第五时钟信号端连接以接收所述第五时钟信号，所述第七开关晶体管的第一极与所述第三节点连接，所述第七开关晶体管的第二极与所述第四节点连接；所述第八开关晶体管的栅极与所述第一电压端连接以接收所述第一电压，所述第八开关晶体管的第一极与所述第二节点连接，所述第八开关晶体管的第二极与所述第三节点连接。
例如，在本公开一些实施例提供的移位寄存器单元中，所述第一移位寄存器电路模块 包括：第十一开关晶体管、第十二开关晶体管、第十三开关晶体管、第十四开关晶体管、第十五开关晶体管、第十六开关晶体管、第十七开关晶体管、第十八开关晶体管、第十九开关晶体管、第二十开关晶体管、第六电容和第七电容；所述第十一开关晶体管的栅极与第二时钟信号端连接以接收所述第二时钟信号，所述第十一开关晶体管的第二极与所述输入端连接以接收所述输入信号，所述第十一开关晶体管的第一极与第三节点连接；所述第十二开关晶体管的栅极与所述第二时钟信号端连接以接收所述第二时钟信号，所述第十二开关晶体管的第二极与所述第三节点连接，所述第十二开关晶体管的第一极与与第二节点连接；所述第十三开关晶体管的栅极与所述第二节点连接，所述第十三开关晶体管的第一极与第六时钟信号端连接以接收第六时钟信号，所述第十三开关晶体管的第二极与所述第一输出端连接；所述第七电容的第一端与所述第二节点连接，所述第七电容的第二端与所述第一输出端连接；所述第十四开关晶体管的栅极与第一节点连接，所述第十四开关晶体管的第一极与第二电压端连接以接收第二电压，所述第十四开关晶体管的第二极与所述第一输出端连接；所述第六电容的第一端与所述第一节点连接，所述第六电容的第二端与第二电压端连接；所述第十五开关晶体管的栅极与第一时钟信号端连接以接收所述第一时钟信号，所述第十五开关晶体管的第一极与所述第一节点连接，所述第十五开关晶体管的第二极与第一电压端连接以接收第一电压；所述第十六开关晶体管的栅极与所述第一节点连接，所述第十六开关晶体管的第一极与所述第二电压端连接以接收所述第二电压，所述第十六开关晶体管的第二极与第四节点连接；所述第十七开关晶体管的栅极与所述第一节点连接，所述第十七开关晶体管的第一极与所述第四节点连接，所述第十七开关晶体管M17的第二极与所述第二节点连接；所述第十八开关晶体管的栅极与所述第二节点连接，所述第十八开关晶体管的第一极与所述第四节点连接，所述第十八开关晶体管的第一极与所述第一电压端连接以接收所述第一电压；所述第十九开关晶体管的栅极与所述输入端连接以接收所述输入信号，所述第十九开关晶体管的第一极与所述第二电压端连接以接收所述第二电压，所述第十九开关晶体管的第二极与所述第一节点连接；所述第二十开关晶体管的栅极与所述第一输出端连接以接收所述第一输出信号，所述第二十开关晶体管的第一极与所述第六时钟信号端连接以接收所述第六时钟信号，所述第二十开关晶体管的第二极与所述第三节点连接。
本公开至少一些实施例还提供一种栅极驱动电路，包括：多个级联的本公开任一实施例提供的移位寄存器单元。
例如，在本公开一些实施例提供的栅极驱动电路中，除第一级移位寄存器单元外，其余各级移位寄存器单元的输入端和上一级移位寄存器单元的第一输出端连接。
本公开至少一些实施例还提供一种显示装置，包括本公开任一实施例提供的栅极驱动电路。
例如，本公开一些实施例提供的显示装置，还包括：多条栅线，其中，各级移位寄存器单元的第二输出端与所述多条栅线中的至少一条栅线连接。
本公开至少一些实施例还提供一种移位寄存器单元的驱动方法，包括：保持阶段，其中，在所述保持阶段，交替地输入所述第一时钟信号和所述第二时钟信号，通过所述第二去噪控制电路调节所述第一去噪控制节点的电平，以开启所述去噪电路，使所述去噪电路对所述第二输出端去噪。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种显示面板的结构示意图；
图2为一种移位寄存器单元的电路结构图；
图3为图2所示的移位寄存器单元工作时的信号时序图；
图4为图2所示的移位寄存器单元工作时的输出噪声图；
图5为本公开一些实施例提供的一种移位寄存器单元的示意框图；
图6为本公开一些实施例提供的一种第二移位寄存器电路模块的示意框图；
图7为本公开一些实施例提供的另一种第二移位寄存器电路模块的示意框图；
图8为图6中所示的第二移位寄存器电路模块的一种具体实现示例的电路结构示意图；
图9为图7中所示的第二移位寄存器电路模块的一种具体实现示例的电路结构示意图；
图10为本公开一些实施例提供的移位寄存器单元的一种具体实现示例的电路结构示意图；
图11为本公开一些实施例提供的移位寄存器单元的另一种具体实现示例的电路结构示意图；
图12为图10所示的移位寄存器单元工作时的信号时序图；
图13为图11所示的移位寄存器单元工作时的信号时序图。
具体实施方式
为了使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连 接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1为一种显示面板的结构示意图。如图1所示，该显示面板01包括显示区AA和位于显示区AA至少一侧的周边区BB。显示区AA中设置有阵列排布的多个子像素P；例如，该多个子像素P通常包括多种颜色子像素，该多种颜色子像素通常包括第一颜色子像素、第二颜色子像素和第三颜色子项素，例如，第一颜色、第二颜色和第三颜色可以为三基色(例如，红色、绿色和蓝色)，但不限于此。为了便于说明，图1中的多个子像素P以矩阵形式排列为例进行说明。在此情况下，沿水平方向排列成一排的子像素P称为一行子像素，沿竖直方向排列成一排的子像素P称为一列子像素。
如图1所示，每一子像素P中均设置有像素电路S。像素电路S通常包括多个晶体管(图1中以包括两个晶体管进行示意)以及电容。像素电路S与发光元件L耦接，用于驱动发光元件L发光。例如，每种颜色子像素中的发光元件L可以发出相应颜色的光，也就是说，第一颜色子像素中的发光元件L可以发出第一颜色的光(例如红光)，第二颜色子像素中的发光元件L可以发出第二颜色的光(例如绿光)，第三颜色子像素中的发光元件L可以发出第三颜色的光(例如蓝光)。位于同一行的像素电路S与同一条栅线GL(Gate Line，如图1中的G_1、G_2、……、G_N等所示，其中N为正整数)连接，位于同一列的像素电路S与同一条数据线DL(Data Line，如图1中的D_1、D_2、……、D_M等所示，其中M为正整数)连接。像素电路S中所包括的晶体管可以均为N型晶体管，也可以均为P型晶体管，还可以包括N型和P型两种晶体管，可根据实际需要及进行设置。另外，像素电路S中所包括的晶体管可以均为低温多晶硅(Low Temperature Poly-silicon，简称LTPS)晶体管，也可以均为氧化物(Oxide)晶体管，还可以包括LTPS和氧化物两种晶体管。
在实际应用中，控制子像素亮度的电压会由于像素电路S中的晶体管漏电而随时间变化，因此，为了使像素亮度波动保持在合理的范围内，在显示静态画面时仍然需要刷新数据。为了降低显示静态画面时的功耗，降低刷新频率是比较有效的方法，同时为了保持显示质量，还需要减少像素电路S中晶体管的漏电速度。由于氧化物半导体具有超低漏电的特性，因此可将像素电路S中的晶体管设置为氧化物晶体管；同时，为了保证子像素的充电速度和较小的寄生电容，可以结合LTPS和Oxide的优势，采用低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)工艺，从而，像素电路S中包括LTPS和Oxide两种晶体管。例如，像素电路S中可以包括P型的LTPS晶体管和N型的Oxide晶体管。
如图1所示，显示面板01的周边区BB设置有栅极驱动电路和数据驱动电路。栅极驱动电路可以设置在沿栅线的延伸方向上的侧边，数据驱动电路可以设置在沿数据线DL的延伸方向上的侧边，以驱动显示面板中的像素电路S，进而驱动发光元件L发光，使相应子像素P进行显示。例如，栅极驱动电路可以通过绑定的集成电路驱动芯片实现，也可以将栅 极驱动电路直接集成在显示面板上构成GOA。例如，数据驱动电路可以通过绑定的集成电路驱动芯片实现。
需要说明的是的，图1是示例性的，在显示面板01的周边区BB的单侧设置栅极驱动电路，从单侧逐行依次驱动各栅线，即单侧驱动。例如，也可以在显示面板01的周边区BB中沿栅线的延伸方向上的两个侧边分别设置栅极驱动电路，并通过两个栅极驱动电路同时从两侧逐行依次驱动各栅线，即双侧驱动。例如，还可以在显示面板01的周边区BB中沿栅线的延伸方向上的两个侧边分别设置栅极驱动电路，并通过两个栅极驱动电路交替从两侧逐行依次驱动各栅线，即交叉驱动。需要说明的是，本公开均是以单侧驱动为例进行说明的。
如图1所示，栅极驱动电路包括N级级联的移位寄存器单元RS(如图1中的RS_1、RS_2、……、RS_N所示)，该N级级联的移位寄存器单元与N条栅线(如图1中的G_1、G_2、……、G_N所示)一一对应连接。
如图1所示，每级移位寄存器单元RS包括信号输入端IN、扫描信号输出端OUT和级联信号输出端GP。在图1所示的栅极驱动电路中，除第一级移位寄存器单元RS_1外，其余各级移位寄存器单元的信号输入端IN和上一级移位寄存器单元的级联信号输出端GP连接；第一级移位寄存器单元RS_1的信号输入端IN可以被配置为接收触发信号STV。另外，每级移位寄存器单元RS通过扫描信号输出端OUT向与其连接的栅线提供扫描信号。
应当理解的是，图1所示的栅极驱动电路中的各级移位寄存器单元RS的电路结构通常是相同的。另外，在像素电路S中包括P型的LTPS晶体管和N型的Oxide晶体管的情况下，级联信号输出端GP还可以通过例如栅线连接像素电路S中的P型晶体管，以向P型晶体管传输控制信号，控制P型晶体管导通或截止。
在一帧图像的显示周期中，需要通过栅极驱动电路逐行依次驱动各栅线。在每行栅线的驱动过程中，在移位寄存器单元输出扫描信号之后，移位寄存器单元应当向与其耦接的栅线输出非工作电压，以保证与该栅线所耦接的晶体管截止，此阶段称为保持阶段。然而，在保持阶段，移位寄存器单元中与栅线耦接的扫描信号输出端OUT的噪声较大，可能会导致显示装置所显示的画面不稳定。
图2为一种移位寄存器单元的电路结构图。如图2所示，该移位寄存器单元包括12个晶体管M1～M12以及4个电容(C01～C04)。晶体管M1的栅极和时钟信号端CK连接以接收时钟信号CK，晶体管M1的第二极和信号输入端IN连接，晶体管M1的第一极和节点PD_in连接；晶体管M2的栅极和节点PD_in连接，晶体管M2的第二极和时钟信号端CK连接以接收时钟信号CK，晶体管M2的第一极和节点PU连接；晶体管M3的栅极和时钟信号端CK连接以接收时钟信号CK，晶体管M3的第二极和第一电源线VSS连接以接收第一电压VSS(例如，第一电压VSS为低电平)，晶体管M3的第一极和节点PU连接；晶体管M4的栅极和节点PU连接，晶体管M4的第一极和第二电源线VDD连接以接收第二电压VDD(例如，第二电压VDD为高电平)，晶体管M4的第二极和输出端GP连接； 电容C01的第一端和节点PU连接，电容C01的第二端和第二电源线VDD连接；晶体管M5的栅极和节点PD_out连接，晶体管M5的第一极和时钟信号端CB连接以接收时钟信号CB，晶体管M5的第二极和级联信号输出端GP连接；电容C02的第一端和节点PD_out连接，电容C02的第二端和级联信号输出端GP连接；晶体管M6的栅极和节点PU连接，晶体管M6的第一极和第二电源线VDD连接以接收第二电压VDD，晶体管M6的第二极和节点PD_f连接；晶体管M7的栅极和时钟信号端CB连接以接收时钟信号CB，晶体管M7的第一极和节点PD_in连接，晶体管M7的第二极和节点PD_f连接；晶体管M8的栅极和第一电源线VSS连接以接收第一电压VSS，晶体管M8的第二极和节点PD_in连接，晶体管M8的第一极和节点PD_out连接；晶体管M9的栅极和级联信号输出端GP连接，晶体管M9的第一极和第二电源线VDD连接以接收第二电压VDD，晶体管M9的第二极和节点PD_ox连接；晶体管M10的栅极和时钟信号端CK连接以接收时钟信号CK，晶体管M10的第二极和第一电源线VSS连接以接收第一电压VSS，晶体管M10的第一极和节点PD_ox连接；晶体管M11的栅极和级联信号输出端GP连接，晶体管M11的第一极和第二电源线VDD连接以接收第二电压VDD，晶体管M11的第二极和扫描信号输出端OUT连接；晶体管M12的栅极和节点PD_ox连接，晶体管M12的第二极和第一电源线VSS连接以接收第一电压VSS，晶体管M12的第一极扫描信号输出端OUT连接；电容C03的第一端和节点PD_ox连接，电容C03的第二端和时钟信号端CB连接；电容C04的第一端和节点PD_ox连接，电容C04的第二端和扫描信号输出端OUT连接。
需要说明的是，图2所示的移位寄存器单元中的晶体管均是以P型晶体管为例进行说明的，即各个晶体管在栅极接入低电平时导通(即低电平为有效电平)，而在接入高电平时截止(即高电平为无效电平)。此时，晶体管的第一极可以是源极，晶体管的第二极可以是漏极。
图3为图2所示的移位寄存器单元工作时的信号时序图。下面结合图3所示的信号时序图，对图2所示的移位寄存器单元的工作原理进行简要说明。如图3所示，图2所示的移位寄存器单元的工作过程包括3个阶段，分别为第一阶段t1(也称为输入阶段)、第二阶段t2(也称为输出阶段)和保持阶段(包括第三阶段t3、第四阶段t4、第五阶段t5、……等等)。图3示出了每个阶段中各个信号的时序波形。
在第一阶段t1，如图3所示，时钟信号CK为低电平，时钟信号CB为高电平，信号输入端IN处于低电平(即信号输入端IN接收低电平的输入信号)，从而，晶体管M1、M3、M10导通，晶体管M7截止。导通的晶体管M1将低电平的输入信号传输至节点PD_in，使得节点PD_in的电平变为低电平，从而晶体管M2导通；由于晶体管M8响应于第一电压VSS(低电平)一直处于导通状态，所以节点PD_out的电平与节点PD_in的电平相同，即为低电平，从而，该低电平存储至电容C02中，且晶体管M5导通；导通的晶体管M3将第一电压VSS(低电平)传输至节点PU，导通的晶体管M2将时钟信号CK的低电平传输至节点PU，从而使得节点PU的电平变为低电平，并存储在电容C01中；晶体管M4响应于 节点PU的低电平导通，将第二电压VDD(高电平)输出至级联信号输出端GP，同时，晶体管M5响应于节点PD_out的低电平导通，将时钟信号CB的高电平传输至级联信号输出端GP，从而，在此阶段，移位寄存器单元的级联信号输出端GP输出高电平，相应地，晶体管M9和M11响应于级联信号输出端GP的高电平截止；另外，导通的晶体管M10将第一电压VSS(低电平)传输至节点PD_ox，从而使得节点PD_ox的电平变为低电平，并存储在电容C03和C04中；晶体管M12响应于节点PD_ox的低电平导通，将第一电压VSS(低电平)输出至扫描信号输出端OUT，从而，在此阶段，移位寄存器单元的扫描信号输出端OUT输出低电平。
在第二阶段t2，如图3所示，时钟信号CK为高电平，时钟信号CB为低电平，信号输入端IN处于高电平，从而，晶体管M1、M3、M10截止，晶体管M7导通。由于电容C02的存储作用，节点PD_in和节点PD_out可以继续保持上一阶段的低电平，从而晶体管M2、M5导通；导通的晶体管M2将时钟信号CK的高电平传输至节点PU，从而使得节点PU的电平变为高电平；晶体管M4响应于节点PU的高电平截止，避免将第二电压VDD(高电平)输出至级联信号输出端GP；导通的晶体管M5将时钟信号CB的低电平传输至级联信号输出端GP，从而，在此阶段，移位寄存器单元的级联信号输出端GP输出低电平，例如，该低电平可以作为下一级移位寄存器单元的输入信号，当然也可以用于控制图1中所示的像素电路S中的P型晶体管工作；另外，晶体管M9响应于级联信号输出端GP的低电平导通，将第二电压VDD(高电平)传输至节点PD_ox，从而使得节点PD_ox的电平变为高电平，相应地，晶体管M12截止；晶体管M11响应于级联信号输出端GP的低电平导通，将第二电压VDD(高电平)输出至扫描信号输出端OUT，从而，在此阶段，移位寄存器单元的扫描信号输出端OUT输出高电平，例如，该高电平可以用于控制图1中所示的像素电路S中的N型晶体管工作。
在保持阶段中的第三阶段t3，如图3所示，时钟信号CK为低电平，时钟信号CB为高电平，信号输入端IN处于高电平，从而，晶体管M1、M3、M10导通，晶体管M7截止。导通的晶体管M1将信号输入端IN的高电平传输至节点PD_in和节点PD_out(晶体管M8一直处于导通状态)，从而使得节点PD_in和节点PD_out的电平变为高电平，相应地，晶体管M2、M5截止；导通的晶体管M3将第一电压VSS(低电平)传输至节点PU，从而使得节点PU的电平变为低电平，并存储在电容C01中；晶体管M4响应于节点PU的低电平导通，将第二电压VDD(高电平)输出至级联信号输出端GP，从而，在此阶段，移位寄存器单元的级联信号输出端GP输出高电平，相应地，晶体管M9和M11响应于级联信号输出端GP的高电平截止；另外，导通的晶体管M10将第一电压VSS(低电平)传输至节点PD_ox，从而使得节点PD_ox的电平变为低电平，并存储在电容C03和电容C04中；晶体管M12响应于节点PD_ox的低电平导通，将第一电压VSS(低电平)输出至扫描信号输出端OUT，从而，在此阶段，移位寄存器单元的扫描信号输出端OUT输出低电平。
在保持阶段中的第四阶段t4，如图3所示，时钟信号CK为高电平，时钟信号CB为低 电平，信号输入端IN处于高电平，从而晶体管M1、M3、M10截止，晶体管M7导通。由于电容C02的存储作用，节点PD_in和节点PD_out可以继续保持上一阶段的高电平，从而晶体管M2、M5截止；由于电容C01的存储作用，节点PU继续保持上一阶段的低电平，从而晶体管M4、M6保持导通；第二电压VDD(高电平)通过导通的晶体管M6以及导通的晶体管M7被传输至节点PD_in和节点PD_out，从而使得节点PD_in和节点PD_out继续保持为高电平，有效地防止了晶体管M5导通，从而避免了误输出；同时，导通的晶体管M4将第二电压VDD(高电平)输出至级联信号输出端GP，从而，在此阶段，移位寄存器单元的级联信号输出端GP输出高电平，相应地，晶体管M9和M11响应于级联信号输出端GP的高电平截止；另外，时钟信号CB从高电平变为低电平，由于电容C03的自举效应，节点PD_ox的电平被进一步拉低，从而，晶体管M12进一步导通，将第一电压VSS(低电平)输出至扫描信号输出端OUT，从而，在此阶段，移位寄存器单元的扫描信号输出端OUT输出低电平，即实现了对扫描信号输出端OUT的去噪。
在保持阶段中的第五阶段t5，如图3所示，时钟信号CK为低电平，时钟信号CB为高电平，信号输入端IN处于高电平，从而，晶体管M1、M3导通，晶体管M7截止。导通的晶体管M1将信号输入端IN的高电平传输至节点PD_in和节点PD_out(晶体管M8一直处于导通状态)，从而使得节点PD_in和节点PD_out的电平保持为高电平，相应地，晶体管M2、M5截止；导通的晶体管M3将第一电压VSS(低电平)传输至节点PU，使得节点PU的电平保持为低电平，从而晶体管M4、M6保持导通；第二电压VDD(高电平)通过导通的晶体管M6以及导通的晶体管M7被传输至节点PD_in和节点PD_out，从而使得节点PD_in和节点PD_out继续保持为高电平，有效地防止了晶体管M5导通，从而避免了误输出；同时，导通的晶体管M4将第二电压VDD(高电平)输出至级联信号输出端GP，从而，在此阶段，移位寄存器单元的级联信号输出端GP输出高电平，相应地，晶体管M9和M11响应于级联信号输出端GP的高电平保持截止。另外，时钟信号CK的电平为低电平，而节点PD_ox的电平也为低电平，由于P型晶体管的阈值电压Vth一般为负值，因此对于晶体管M10而言，其栅源电压差Vgs>Vth，由于P型晶体管是在Vgs<Vth的情况下才会导通，此时晶体管M10截止；由于晶体管M9和M11也截止，因此节点PD-ox和扫描信号输出端OUT处于悬浮(floating)状态；时钟信号CB的电平变为高电平，由于电容C03的自举效应，节点PD_ox的电平会被略微拉高，从而晶体管M12截止，不能持续将第一电压VSS(低电平)输出至扫描信号输出端OUT，也即，在此阶段，无法实现对扫描信号输出端OUT的持续去噪。
综合上述可知，由于时钟信号CK和时钟信号CB交替为高电平和低电平，因此此后保持阶段的第四阶段t4和第五阶段t5会交替出现，从而在保持阶段，晶体管M10有将近一半的时间(即保持阶段中的第五阶段t5)不能对扫描信号输出端OUT去噪，这导致受到外界干扰的情况下，移位寄存器单元在保持阶段不能及时去噪，扫描信号输出端OUT可能会产生较大噪声。如图5所示，经过模拟测试，在保持阶段，扫描信号输出端OUT的输出噪声 可达2V。
本公开至少一些实施例提供一种移位寄存器单元，包括第一移位寄存器电路模块和第二移位寄存器电路模块。第一移位寄存器电路模块被配置为根据输入端接收的输入信号在第一输出端输出第一输出信号以及向第二移位寄存器电路模块提供开启控制信号。第二移位寄存器电路模块包括输出电路、去噪电路、第一去噪控制电路和第二去噪控制电路；输出电路被配置为响应于开启控制信号，在第二输出端输出第二输出信号；去噪电路被配置为在第一去噪控制节点的电平的控制下，对第二输出端去噪；第一去噪控制电路被配置为响应于第一输出信号，控制第一去噪控制节点的电平，以关闭去噪电路；第二去噪控制电路被配置为在第一时钟信号和第二时钟信号的控制下，调节第一去噪控制节点的电平，以开启去噪电路。第二去噪控制电路包括第一控制电路、第一耦合电路、第二耦合电路、传输电路和存储电路；第一控制电路被配置为在第一时钟信号的控制下，将第一电压传输至第二去噪控制节点；第一耦合电路被配置为存储第二去噪控制节点的电平，以及在第二时钟信号的控制下调节第二去噪控制节点的电平；第二耦合电路被配置为存储第二去噪控制节点的电平，以及降低第一耦合电路调节第二去噪控制节点的电平的调节量；传输电路被配置为连接第一去噪控制节点和第二去噪控制节点，以平衡第一去噪控制节点的电平和第二去噪控制节点的电平；存储电路被配置为存储所述第一去噪控制节点的电平。
本公开的一些实施例还提供对应于上述移位寄存器单元的栅极驱动电路、显示装置及驱动方法。
本公开一些实施例提供的移位寄存器单元，通过在第二去噪控制电路中引入由第一控制电路、第一耦合电路、第二耦合电路、传输电路和存储电路形成的电荷泵结构，利用电荷泵结构对电压的调节作用，可以调节第一去噪控制节点的电平；从而，一方面，确保去噪电路在保持阶段持续开启，及时去除噪声干扰，另一方面，降低第一去噪控制节点的电平对去噪电路的偏置作用，延长移位寄存器单元的工作寿命。
下面结合附图对本公开的几个实施例进行详细说明。需要说明的是，为了保持本公开实施例的说明的清楚和简要，可省略已知功能和已知部(元)件的详细说明。当本公开实施例的任一部(元)件在一个以上的附图中出现时，该部(元)件在每个附图中由相同或类似的参考标号表示。
图5为本公开一些实施例提供的一种移位寄存器单元的示意框图。如图5所示，该移位寄存器单元100包括第一移位寄存器电路模块110和第二移位寄存器电路模块120(如图5中的虚线框所示)，可以根据输入端IN接收的输入信号分别在第一输出端GP输出第一输出信号以及在第二输出端OUT输出第二输出信号。
例如，通过级联多个该移位寄存器单元100可以得到栅极驱动电路(例如，可以参考图1中所示的栅极驱动电路)，该栅极驱动电路可以用于驱动例如液晶显示面板、有机发光二极管显示面板等。
例如，如图5所示，第一移位寄存器电路模块110被配置为根据输入端IN接收的输入 信号在第一输出端GP输出第一输出信号(例如，低电平信号)以及向第二移位寄存器电路模块120提供开启控制信号。例如，在一些实施例中，如图5所示，第一移位寄存器电路模块110可以包括第二节点PD_o(后续介绍)，其可以通过第二节点PD_o向第二移位寄存器电路模块120提供开启控制信号。例如，在一些实施例中，参考图1所示，当前级的移位寄存器单元100的第一输出端可以与下一级移位寄存器单元100的信号输入端IN连接，即当前级的移位寄存器单元100的第一输出信号可以作为下一级移位寄存器单元100的输入信号。例如，在一些实施例中，第一输出端GP还可以通过例如栅线连接像素电路中的P型晶体管，以向P型晶体管传输控制信号，控制P型晶体管导通或截止。
例如，如图5所示，第二移位寄存器电路模块120包括输出电路121、去噪电路122、第一去噪控制电路123和第二去噪控制电路124。
例如，输出电路121被配置为响应于开启控制信号，在第二输出端OUT输出第二输出信号(例如，高电平信号)。例如，在一些实施例中，如图5所示，输出电路121与第二节点PD_o、第三时钟信号端CK2以及第二输出端OUT连接，且被配置为在开启控制信号(由第二节点PD_o的电平变化形成开启控制信号)的控制下导通，从而将第三时钟信号端CK2提供的第三时钟信号CK2传输至第二输出端OUT，并作为第二输出信号在第二输出端OUT输出。例如，在一些实施例中，输出电路121可以与第一输出端GP、第三时钟信号端CK2以及第二输出端OUT连接，且被配置为在开启控制信号(第一输出端GP提供的第一输出信号作为开启控制信号)的控制下导通，从而将第三时钟信号端CK2提供的第三时钟信号CK2传输至第二输出端OUT，并作为第二输出信号在第二输出端OUT输出。
例如，去噪电路122被配置为在第一去噪控制节点PD_ox的电平的控制下，对第二输出端OUT去噪。例如，在一些实施例中，如图5所示，去噪电路122与第一去噪控制节点PD_ox、第一电压端VSS以及第二输出端OUT连接，且被配置为在第一去噪控制节点PD_ox的电平的控制下导通，从而将第一电压端VSS提供的第一电压VSS(例如，第一电压VSS可以为低电平，但不限于此)传输至第二输出端OUT，以对第二输出端OUT去噪。
例如，第一去噪控制电路123被配置为响应于第一输出信号，控制第一去噪控制节点PD_ox的电平，以关闭去噪电路122。例如，在一些实施例中，如图5所示，第一去噪控制电路123与第一输出端GP、第一信号端VDD/PU以及第一去噪控制节点PD_ox连接，且被配置为响应于第一输出端GP提供的第一输出信号，将第一信号端VDD/PU的第一信号电平传输至第一去噪控制节点PD_ox，以控制(例如，拉高)第一去噪控制节点PD_ox的电平，进而关闭去噪电路122。例如，在一些实施例中，第一信号端VDD/PU可以为提供第二电压VDD(例如，第二电压VDD可以为高电平，但不限于此)的第二电压端VDD。例如，在一些实施例中，第一移位寄存器电路模块110可以包括第一节点PU(后续介绍)；如图5所示，第一信号端与第一移位寄存器电路模块110中的第一节点PU连接，从而，第一去噪控制电路123可以响应于第一输出端GP提供的第一输出信号，将第一节点PU的电平(例如，高电平)传输至第一去噪控制节点PD_ox，以控制(例如，拉高)第一去噪控 制节点PD_ox的电平，进而关闭去噪电路122。
例如，第二去噪控制电路124被配置为在第一时钟信号CK1和第二时钟信号CB1的控制下，调节第一去噪控制节点PD_ox的电平，以开启去噪电路。例如，在一些实施例中，如图5所示，第二去噪控制电路124与第一时钟信号端CK1、第二时钟信号端CB1、第一电压端VSS以及第一去噪控制节点PD_ox连接，且被配置为在第一时钟信号端CK1提供的第一时钟信号CK1和第二时钟信号端CB1提供的第二时钟信号CB1的控制下，基于第一电压端VSS提供的第一电压VSS对第一去噪控制节点PD_ox的电平进行调节，以开启去噪电路。
图6为本公开一些实施例提供的一种第二移位寄存器电路模块120的示意框图。例如，如图6所示，在第二移位寄存器电路模块120中，第二去噪控制电路124可以包括第一控制电路1241、第一耦合电路1242、第二耦合电路1243、传输电路1244和存储电路1245。
例如，第一控制电路1241被配置为在第一时钟信号CK1的控制下，将第一电压VSS传输至第二去噪控制节点PD_ox_i。例如，在一些实施例中，如图6所示，第一控制电路1241与第一时钟信号端CK1、第一电压端VSS以及第二去噪控制节点PD_ox_i连接，且被配置为在第一时钟信号端CK1提供的第一时钟信号CK1的控制下，将第一电压端VSS提供的第一电压VSS传输至第二去噪控制节点PD_ox_i。
例如，第一耦合电路1242被配置为存储第二去噪控制节点PD_ox_i的电平，以及在第二时钟信号CB1的控制下调节第二去噪控制节点PD_ox_i的电平。例如，在一些实施例中，如图6所示，第一耦合电路1242与第二去噪控制节点PD_ox_i以及第二时钟信号端CB1连接。例如，在第二时钟信号端CB1提供的第二时钟信号CB1的电平发生变化的情况下，由于第一耦合电路1242的耦合作用(例如，自举效应)，第二去噪控制节点PD_ox_i的电平也会相应发生变化，从而，第一耦合电路1242可以在第二时钟信号CB1的控制下调节第二去噪控制节点PD_ox_i的电平。
例如，第二耦合电路1243被配置为存储第二去噪控制节点PD_ox_i的电平，以及降低第一耦合电路1242调节第二去噪控制节点PD_ox_i的电平的调节量。例如，在一些实施例中，如图6所示，第二耦合电路1243与第二去噪控制节点PD_ox_i以及第一电压端VSS连接。例如，由于第二耦合电路1243也具有耦合作用，从而，在第二时钟信号端CB1提供的第二时钟信号CB1的电平发生变化的情况下，第二耦合电路1243的耦合作用与第一耦合电路1242的耦合作用同时起作用，进而，可以降低第一耦合电路1242调节第二去噪控制节点PD_ox_i的电平的调节量。
例如，传输电路1244被配置为连接第一去噪控制节点PD_ox和第二去噪控制节点PD_ox_i，以平衡第一去噪控制节点PD_ox的电平和第二去噪控制节点PD_ox_i的电平。例如，在第二去噪控制节点PD_ox_i的电平发生变化的情况下，传输电路1244可以通过传输电荷(第一耦合电路1242和第二耦合电路1243通过存储电荷而存储第二去噪控制节点PD_ox_i的电平，后续的存储电路1245通过存储电荷而存储第一去噪控制节点PD_ox的电 平)平衡第一去噪控制节点PD_ox的电平和第二去噪控制节点PD_ox_i的电平。
例如，存储电路1245被配置为存储第一去噪控制节点PD_ox的电平。例如，在一些实施例中，如图6所示，存储电路1245与第一去噪控制节点PD_ox以及第一电压端VSS连接。
例如，上述第一控制电路1241、第一耦合电路1242、第二耦合电路1243、传输电路1244和存储电路1245形成电荷泵结构。第二去噪控制电路124利用电荷泵结构对电压的调节作用，可以调节第一去噪控制节点PD_ox的电平；从而，一方面，确保去噪电路122在保持阶段持续开启，及时去除噪声干扰，另一方面，降低第一去噪控制节点PD_ox的电平对去噪电路122的偏置作用，延长移位寄存器单元100的工作寿命。例如，在一些实施例中，在第二去噪控制电路124的调节下，第一去噪控制节点PD_ox的电平与第一电压VSS的差为去噪电路122的阈值电压的n倍，其中，1≤n≤10。
图7为本公开一些实施例提供的另一种第二移位寄存器电路模块120的示意框图。例如，如图7所示，在第二移位寄存器电路模块120中，第二去噪控制电路124在图6所示的电路结构的基础上还可以包括第二控制电路1246。需要说明的是，图7所示的第二移位寄存器电路模块120的其他电路结构与图6所示的第二移位寄存器电路模块120基本相同，在此重复之处不再赘述。
例如，第二控制电路1246被配置为在第二输出端OUT的电平的控制下，将第二时钟信号CB1传输至第一耦合电路1242。例如，如图6所示，第二控制电路1246与第二输出端OUT、第一时钟信号端CB1以及第一耦合电路1242连接。例如，在一些实施例中，在第二输出端OUT输出第二输出信号的情况下，第二控制电路响应于第二输出信号而关闭，使得第二时钟信号CB1无法传输至第一耦合电路1242，从而减少第二时钟信号端CB1的不利耦合，同时降低功耗；在去噪电路122对第二输出端OUT进行去噪的情况下，第二输出端OUT的电平可以使得第二控制电路1246开启，从而，第一时钟信号CB1可以通过开启的第二控制电路1246传输至第一耦合电路1242。
例如，在一些实施例中，如图6和图7所示，第一去噪控制电路123还可以与第二去噪控制节点PD_ox_i连接，且还被配置为响应于第一输出信号，控制第二去噪控制节点PD_ox_i的电平。例如，在一些实施例中，第一去噪控制电路123还被配置为响应于第一输出端GP提供的第一输出信号，将第一信号端VDD/PU的第一信号电平(例如，高电平)传输至第二去噪控制节点PD_ox_i，以控制(例如，拉高)第二去噪控制节点PD_ox_i的电平。
图8为图6中所示的第二移位寄存器电路模块120的一种具体实现示例的电路结构示意图。如图8所示，该第二移位寄存器电路模块120包括第一晶体管T1、第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7，以及还包括第一电容C1、第二电容C2、第三电容C3。需要说明的是，在下面的说明中以各晶体管为P型晶体管为例进行说明，但这并不构成对本公开实施例的限制。
例如，第一控制电路1241可以实现为图8中所示的第一晶体管T1。如图8所示，第一 晶体管T1的栅极与第一时钟信号端CK1连接以接收第一时钟信号CK1，第一晶体管T1的第一极与第一电压端VSS连接以接收第一电压VSS，第一晶体管T1的第二极与第二去噪控制节点PD_ox_i连接。一般地，当第一时钟信号CK1处于有效电平(例如，低电平)时，第一晶体管T1导通，将第二去噪控制节点PD_ox_i和第一电压端VSS连接，使得第二去噪控制节点PD_ox_i的电平与第一电压VSS的电平一致(同为低电平)。
例如，第一耦合电路1242可以实现为图8中所示的第一电容C1。如图8所示，第一电容C1的第一端与第二去噪控制节点PD_ox_i连接，第一电容C1的第二端与第二时钟信号端CB1连接以接收第二时钟信号CB1。第一电容C1用于存储第二去噪控制节点PD_ox_i的电平；同时，第一电容C1具有耦合作用，在第二时钟信号端CB1提供的第二时钟信号CB1的电平发生变化的情况下，由于第一电容C1的耦合作用(例如，自举效应)，第二去噪控制节点PD_ox_i的电平也会相应发生变化，从而，第一电容C1可以在第二时钟信号CB1的控制下调节第二去噪控制节点PD_ox_i的电平。
例如，第二耦合电路1243可以实现为图8中所示的第二电容C2。如图8所示，第二电容C2的第一端与第二去噪控制节点PD_ox_i连接，第二电容C2的第二端与第一电压端VSS连接以接收第一电压VSS。第二电容C2也用于存储第二去噪控制节点PD_ox_i的电平；同时，第二电容C2也具有耦合作用，从而，在第二时钟信号端CB1提供的第二时钟信号CB1的电平发生变化的情况下，第二电容C2的耦合作用与第一电容C1的耦合作用同时起作用，进而，可以降低第一电容C1调节第二去噪控制节点PD_ox_i的电平的调节量。
例如，传输电路1244可以实现为图8中所示的第二晶体管T2。如图8所示，第二晶体管T2的栅极与第二去噪控制节点PD_ox_i连接，第二晶体管T2的第一极与第一去噪控制节点PD_ox连接，第二晶体管T2的第二极与第二去噪控制节点PD_ox_i连接。一般地，当第二去噪控制节点PD_ox_i处于有效电平(例如，低电平)时，第二晶体管T2导通，将第一去噪控制节点PD_ox和第二去噪控制节点PD_ox_i连接，使得第一去噪控制节点PD_ox的电平与第二去噪控制节点PD_ox_i的电平一致(同为低电平)。
例如，存储电路1245可以实现为图8中所示的第三电容C3。如图8所示，第三电容C3的第一端与第一去噪控制节点PD_ox连接，第三电容C3的第二端与第一电压端VSS连接以接收第一电压VSS。第三电容C3用于存储第一去噪控制节点PD_ox的电平，用于在后续阶段控制第四晶体管T4保持导通或截止。
也就是说，第二去噪控制电路124可以实现为图8中所示的第一晶体管T1、第二晶体管T2、第一电容C1、第二电容C2、第三电容C3。图8中所示的第一晶体管T1、第二晶体管T2、第一电容C1、第二电容C2、第三电容C3形成电荷泵结构，利用电荷泵结构对电压的调节作用，可以调节第一去噪控制节点PD_ox的电平；从而，一方面，确保第四晶体管T4在保持阶段持续开启，及时去除噪声干扰，另一方面，降低第一去噪控制节点PD_ox的电平对第四晶体管T4的偏置作用，延长移位寄存器单元100的工作寿命。例如，在一些实施例中，通过合理设置第一电容C1和第二电容C2的电容值，可以使得在上述电荷泵结 构(即第二去噪控制电路124)的调节下，第一去噪控制节点PD_ox的电平与第一电压VSS的差为去噪电路122的阈值电压的n倍，其中，1≤n≤10。
例如，去噪电路122可以实现为图8中所示的第四晶体管T4。如图8所示，第四晶体管T4的栅极与第一去噪控制节点PD_ox连接，第四晶体管T4的第一极与第一电压端VSS连接以接收第一电压VSS，第四晶体管T4的第二极与第二输出端OUT连接。一般地，当第一去噪控制节点PD_ox处于有效电平(例如，低电平)时，第四晶体管T4导通，将第二输出端OUT与第一电压端VSS连接，以将第一电压端VSS提供的第一电压VSS在第二输出端OUT输出，从而对第二输出端OUT1进行去噪。
例如，第一去噪控制电路123可以实现为图8中所示的第五晶体管T5和第六晶体管T6。如图8所示，第五晶体管T5的栅极与第一输出端GP连接以接收第一输出信号，第五晶体管T5的第一极与第一信号端VDD/PU连接以接收第一信号电平，第五晶体管T5的第二极与第一去噪控制节点PD_ox连接；第六晶体管T6的栅极与第一输出端GP连接以接收第一输出信号，第六晶体管T6的第一极与第一信号端VDD/PU连接以接收第一信号电平，第六晶体管T6的第二极与第二去噪控制节点PD_ox_i连接。例如，在一些实施例中，第一信号端VDD/PU可以为用于提供第二电压VDD(例如，第二电压VDD可以为高电平，但不限于此)的第二电压端VDD，在此情况下，第一信号电平为第二电压VDD；例如，在另一些实施例中，第一信号端VDD/PU可以与第一移位寄存器电路模块110中的第一节点PU连接，在此情况下，第一信号电平为第一节点PU的电平(例如，高电平)；需要说明的是，本公开包括但不限于以上情形。一般地，当第一输出端GP的第一输出信号处于有效电平(例如，低电平)时，第五晶体管T5和第六晶体管T6同时导通；导通的第五晶体管T5将第二去噪控制节点PD_ox_i与第一信号端VDD/PU，以将第一信号端VDD/PU提供的第一信号电平(例如，高电平)传输到第二去噪控制节点PD_ox_i，从而实现对第二去噪控制节点PD_ox_i的电平的控制；导通的第六晶体管T6将第一去噪控制节点PD_ox与第一信号端VDD/PU，以将第一信号端VDD/PU提供的第一信号电平(例如，高电平)传输到第一去噪控制节点PD_ox，从而实现对第一去噪控制节点PD_ox的电平的控制，进而可以导通第四晶体管T4(即关闭去噪电路122)。
例如，输出电路121可以实现为图8中所示的第七晶体管T7。如图8所示。第七晶体管T7的栅极与第二信号端连接以接收开启控制信号，第七晶体管T7的第一极与第三时钟信号端CK2连接以接收第三时钟信号CK2，第七晶体管T7的第二极与第二输出端OUT连接。例如，在一些实施例中，第二信号端可以与第一移位寄存器电路模块110中的第二节点PD_o连接，在此情况下，第二节点PD_o的电平变化形成开启控制信号。当开启控制信号处于有效电平(例如，低电平)时，第七晶体管T7导通，将第三时钟信号端CK2和第二输出端OUT连接，从而将第三时钟信号端CK2提供的第三时钟信号CK2作为第二输出信号输出到第二输出端OUT。
图9为图7中所示的第二移位寄存器电路模块120的一种具体实现示例的电路结构示 意图。如图9所示，在图8所示的电路结构的基础上，第二移位寄存器电路模块120还包括用于实现第二控制电路1246的第三晶体管T3。需要说明的是，图9所示的第二移位寄存器电路模块120的其他电路结构与图8所示的第二移位寄存器电路模块120基本相同，在此重复之处不再赘述。
如图9所示，第一电容C1的第二端通过第三晶体管T3与第二时钟信号端CB1连接。第三晶体管T3的栅极与第二输出端OUT连接，第三晶体管T3的第一极与第二时钟信号端CB1连接，第三晶体管T3的第二极与第一电容C1的第二端连接。例如，在第二输出端OUT输出第二输出信号(例如，高电平信号)的情况下，第三晶体管T3响应于第二输出信号而截止，从而切断了第二时钟信号端CB1与第一电容C1之间的连接，使得第二时钟信号CB1的电位变化不会影响第一电容C1，进而消除了第一电容C1在第二时钟信号CB1的电位变化下的不利耦合，也就消除了由此对第二去噪控制节点PD_ox_i的电位的影响，并降低了功耗；在第四晶体管T4对第二输出端OUT进行去噪的情况下，第二输出端OUT的电平(例如，低电平)可以导通第三晶体管T3，从而，第二时钟信号CB1可以通过导通的第三晶体管T3传输至第一电容C1。
图10为本公开一些实施例提供的移位寄存器单元的一种具体实现示例的电路结构示意图。如图10所示，该移位寄存器单元中的第二移位寄存器电路模块120可以实现为图8所示的第二移位寄存器电路模块120；应当理解的是，图10所示的移位寄存器单元中的第二移位寄存器电路模块120也当然可以实现为图9所示的第二移位寄存器电路模块120；本公开的实施例对此不作限制。
如图10所示，该移位寄存器单元中的第一移位寄存器电路模块110可以包括第一开关晶体管至第八开关晶体管M1～M8以及第四电容C4和第五电容C5。第一开关晶体管M1的栅极与第四时钟信号端CK3连接以接收第四时钟信号CK3，第一开关晶体管M1的第二极与输入端IN连接，第一开关晶体管M1的第一极与第三节点PD_in连接；第二开关晶体管M2的栅极与第三节点PD_in连接，第二开关晶体管M2的第二极与第四时钟信号端CK3连接以接收第四时钟信号CK3，第二开关晶体管M2的第一极与第一节点PU连接；第三开关晶体管M3的栅极与第四时钟信号端CK3连接以接收第四时钟信号CK3，第三开关晶体管M3的第二极与第一电压端VSS连接以接收第一电压VSS(例如，第一电压VSS为低电平)，第三开关晶体管M3的第一极与第一节点PU连接；第四开关晶体管M4的栅极与第一节点PU连接，第四开关晶体管M4的第一极与第二电压端VDD连接以接收第二电压VDD(例如，第二电压VDD为高电平)，第四开关晶体管M4的第二极与第一输出端GP连接；第四电容C4的第一端与第一节点PU连接，第四电容C4的第二端与第二电压端VDD连接；第五开关晶体管M5的栅极与第二节点PD_o连接，第五开关晶体管M5的第一极与第五时钟信号端CB3连接以接收第五时钟信号CB3，第五开关晶体管M5的第二极与第一输出端GP连接；第五电容C5的第一端与第二节点PD_o连接，第五电容C5的第二端与第一输出端GP连接；第六开关晶体管M6的栅极与第一节点PU连接，第六开关晶体管M6的第一 极与第二电压端VDD连接以接收第二电压VDD，第六开关晶体管M6的第二极与第四节点PD_f连接；第七开关晶体管M7的栅极与第五时钟信号端CB3连接以接收第五时钟信号CB3，第七开关晶体管M7的第一极与第三节点PD_in连接，第七开关晶体管M7的第二极与第四节点PD_f连接；第八开关晶体管M8的栅极与第一电压端VSS连接以接收第一电压VSS，第八开关晶体管M8的第二极与第三节点PD_in连接，第八开关晶体管M8的第一极与第二节点PD_o连接。
图12为图10所示的移位寄存器单元工作时的信号时序图。下面结合图12所示的信号时序图，对图10所示的移位寄存器单元的工作原理进行简要说明。如图12所示，图10所示的移位寄存器单元的工作过程包括3个阶段，分别为第一阶段P1(也称为输入阶段)、第二阶段P2(也称为输出阶段)和保持阶段P3(包括第一保持阶段P31、第二保持阶段P32等等)。图12示出了每个阶段中各个信号的时序波形。需要说明的是，图12中所示的信号时序图的电位的高低仅是示意性的，不代表真实电位值或相对比例，对于本公开的实施例而言，低电平信号对应于P型晶体管的开启信号，而高电平信号对应于P型晶体管的截止信号。
在第一阶段P1，如图12所示，第一时钟信号CK1、第三时钟信号CK2和第四时钟信号CK3为低电平，第二时钟信号CB1和第五时钟信号CB3为高电平，输入端IN处于低电平(即输入端IN接收低电平的输入信号)，从而，第一晶体管T1导通，开关晶体管M1、M3导通，开关晶体管M7截止。导通的开关晶体管M1将低电平的输入信号传输至第三节点PD_in，使得第三节点PD_in的电平变为低电平，从而开关晶体管M2导通；由于开关晶体管M8响应于第一电压VSS(低电平)一直处于导通状态，所以第二节点PD_o的电平与第三节点PD_in的电平相同，即为低电平，从而，该低电平存储至第五电容C5中，且开关晶体管M5导通；导通的开关晶体管M3将第一电压VSS(低电平)传输至第一节点PU，导通的开关晶体管M2将第四时钟信号CK3的低电平传输至第一节点PU，从而使得第一节点PU的电平变为低电平，并存储在第四电容C4中；开关晶体管M4响应于第一节点PU的低电平导通，将第二电压VDD(高电平)输出至第一输出端GP，同时，开关晶体管M5响应于第二节点PD_o的低电平导通，将第五时钟信号CB3的高电平传输至第一输出端GP，从而，在此阶段，移位寄存器单元的第一输出端GP输出高电平，相应地，第五晶体管T5和第六晶体管T6响应于第一输出端GP的高电平截止；另外，导通的第一晶体管T1将第一电压VSS(低电平)传输至第二去噪控制节点PD_ox_i，从而使得第二去噪控制节点PD_ox_i的电平变为低电平，并存储在第一电容C1和第二电容C2中；第二晶体管T2在第二去噪控制节点PD_ox_i的低电平控制下导通，从而第一去噪控制节点PD_ox的电平也变为低电平，并存储在第三电容C3中；第四晶体管T4响应于第一去噪控制节点PD_ox的低电平导通，将第一电压VSS(低电平)传输至第二输出端OUT；第七晶体管T7响应于第二节点PD_o的低电平导通，将第三时钟信号CK2的低电平传输至第二输出端OUT；从而，在此阶段，移位寄存器单元的第二输出端OUT输出低电平，即实现了对第二输出端OUT 的去噪。
在第二阶段P2，如图12所示，第一时钟信号CK1、第三时钟信号CK2和第四时钟信号CK3为高电平，第二时钟信号CB1和第五时钟信号CB3为低电平，输入端IN处于高电平，从而，第一晶体管T1截止，开关晶体管M1、M3截止，开关晶体管M7导通。由于第五电容C5的存储作用，第三节点PD_in和第二节点PD_o可以继续保持上一阶段的低电平，从而开关晶体管M2、M5导通；导通的晶体管M2将第四时钟信号CK3的高电平传输至第一节点PU，从而使得第一节点PU的电平变为高电平；开关晶体管M4响应于第一节点PU的高电平截止，避免将第二电压VDD(高电平)输出至第一输出端GP；导通的开关晶体管M5将第五时钟信号CB3的低电平传输至第一输出端GP，从而，在此阶段，移位寄存器单元的第一输出端GP输出低电平，即输出第一输出信号，例如，该第一输出信号可以作为下一级移位寄存器单元的输入信号，当然也可以用于控制例如图1中所示的像素电路S中的P型晶体管工作；另外，第五晶体管T5和第六晶体管T6响应于第一输出端GP的低电平导通，将第二电压VDD(高电平)分别传输至第二去噪控制节点PD_ox_i和第一去噪控制节点PD_ox，从而使得第二去噪控制节点PD_ox_i和第一去噪控制节点PD_ox的电平均变为高电平，相应地，第四晶体管T4截止；第七晶体管T7响应于第二节点PD_o的低电平导通，将第三时钟信号CK2的高电平传输至第二输出端OUT；从而，在此阶段，移位寄存器单元的第二输出端OUT输出高电平，即输出第二输出信号，例如，该第二输出信号可以用于控制例如图1中所示的像素电路S中的N型晶体管工作。
在保持阶段P3的第一保持阶段P31，如图12所示，第一时钟信号CK1、第三时钟信号CK2和第四时钟信号CK3为低电平，第二时钟信号CB1和第五时钟信号CB3为高电平，输入端IN处于高电平，从而，第一晶体管T1导通，开关晶体管M1、M3导通，开关晶体管M7截止。导通的开关晶体管M1将输入端IN的高电平传输至第三节点PD_in和第二节点PD_o(晶体管M8一直处于导通状态)，从而使得第三节点PD_in和第二节点PD_o的电平变为高电平，相应地，开关晶体管M2、M5截止；导通的开关晶体管M3将第一电压VSS(低电平)传输至第一节点PU，从而使得第一节点PU的电平变为低电平，并存储在第四电容C4中；开关晶体管M4响应于第一节点PU的低电平导通，将第二电压VDD(高电平)输出至第一输出端GP，从而，在此阶段，移位寄存器单元的第一输出端GP输出高电平，相应地，第五晶体管T5和第六晶体管T6响应于第一输出端GP的高电平截止；另外，导通的第一晶体管T1将第一电压VSS(低电平)传输至第二去噪控制节点PD_ox_i，从而使得第二去噪控制节点PD_ox_i的电平变为低电平，并存储在第一电容C1和第二电容C2中；第二晶体管T2在第二去噪控制节点PD_ox_i的低电平控制下导通，从而第一去噪控制节点PD_ox的电平也变为低电平，并存储在第三电容C3中；第四晶体管T4响应于第一去噪控制节点PD_ox的低电平导通，将第一电压VSS(低电平)传输至第二输出端OUT；第七晶体管T7响应于第二节点PD_o的高电平截止；从而，在此阶段，移位寄存器单元的第二输出端OUT输出低电平，即实现了对第二输出端OUT的去噪。
在保持阶段P3的第二保持阶段P32，如图12所示，第一时钟信号CK1、第三时钟信号CK2和第四时钟信号CK3为高电平，第二时钟信号CB1和第五时钟信号CB3为低电平，输入端IN处于高电平，从而，第一晶体管T1截止，开关晶体管M1、M3截止，开关晶体管M7导通。由于第五电容C5的存储作用，第三节点PD_in和第二节点PD_o可以继续保持上一阶段的高电平，从而开关晶体管M2、M5截止；由于第四电容C4的存储作用，第一节点PU继续保持上一阶段的低电平，从而开关晶体管M4、M6保持导通；第二电压VDD(高电平)通过导通的开关晶体管M6以及导通的开关晶体管M7被传输至第三节点PD_in和第二节点PD_o，从而使得第三节点PD_in和第二节点PD_o继续保持为高电平，有效地防止了开关晶体管M5导通，从而避免了误输出；同时，导通的开关晶体管M4将第二电压VDD(高电平)输出至第一输出端GP，从而，在此阶段，移位寄存器单元的第一输出端GP输出高电平，相应地，第五晶体管T5和第六晶体管T6响应于第一输出端GP的高电平截止；另外，第二时钟信号CB1从高电平变为低电平，由于第一电容C1的自举效应，处于悬浮状态的第二去噪控制节点PD_ox_i的电平被进一步拉低，同时，由于第二电容C2的耦合作用，第二去噪控制节点PD_ox_i的电平变化小于第二时钟信号CB1的电平变化，即第二电容C2降低了第一电容C1调节第二去噪控制节点PD_ox_i的电平的调节量；第二晶体管T2在第二去噪控制节点PD_ox_i的低电平控制下导通，从而第一去噪控制节点PD_ox的电平也被进一步拉低；第四晶体管T4响应于第一去噪控制节点PD_ox的低电平导通，将第一电压VSS(低电平)传输至第二输出端OUT；第七晶体管T7响应于第二节点PD_o的高电平截止；从而，在此阶段，移位寄存器单元的第二输出端OUT仍然输出低电平，即实现了对第二输出端OUT的持续去噪。
以下对保持阶段P3中第二去噪控制节点PD_ox_i的电平变化和第一去噪控制节点PD_ox的电平变化进行详细说明。如上所述，在保持阶段P3，第五晶体管T5、第六晶体管T6、第七晶体管T7始终保持截止状态，因此，第二去噪控制节点PD_ox_i的电平和第一去噪控制节点PD_ox的电平仅受第一晶体管T1、第二晶体管T2、第一电容C1、第二电容C2、第三电容C3的影响，也即仅受第二去噪控制电路124的影响。
例如，忽略第一晶体管T1的阈值电压和第二晶体管T2的阈值电压的影响。在第一保持阶段P31，第一晶体管T1导通，第二去噪控制节点PD_ox_i的电平为VSS，第一电容C1的与第二时钟信号端CB1连接的一端的电平为高电平(不防设为高电平VDD)，第二晶体管T2导通，第一去噪控制节点PD_ox的电平也为VSS。在第二保持阶段P32，第一晶体管T1截止，第一电容C1的与第二时钟信号端CB1连接的一端的电平变为低电平(不防设为低电平VSS)；由于第一电容C1的自举效应，第二去噪控制节点PD_ox_i的电平相应发生变化，变化量为(VSS-VDD)*C1/C PD_ox_i，其中，C PD_ox_i＝C1+C2+C T1+C T2+C T5，C PD_ox_i表示第二去噪控制节点PD_ox_i所连接的各器件(包括第一晶体管T1、第二晶体管T2、第五晶体管T5、第一电容C1和第二电容C2)的总电容，C T1、C T2、C T5分别表示第一晶体管T1、第二晶体管T2、第五晶体管T5的与第二去噪控制节点PD_ox_i相关的寄生电容；从 而，第二去噪控制节点PD_ox_i的电平被拉低至VSS+(VSS-VDD)*C1/C PD_ox_i，同时，由于第一去噪控制节点PD_ox的电平为VSS，第二晶体管T2导通，部分电荷由第一去噪控制节点PD_ox流入第二去噪控制节点PD_ox_i，也即，第一去噪控制节点PD_ox的电平被拉低至某一大于VSS+(VSS-VDD)*C1/C PD_ox_i而小于VSS的电平。此后，由于第一时钟信号CK1和第二时钟信号CB1交替为高电平和低电平，因此，在保持阶段P3，第一保持阶段P31和第二保持阶段P32会交替出现；从而，第一去噪控制节点PD_ox和第二去噪控制节点PD_ox_i之间会进行多次耦合，直到第一去噪控制节点PD_ox的电平稳定在VSS+(VSS-VDD)*C1/C PD_ox_i附近为止，进而使得第四晶体管T4在保持阶段P3持续导通，对第二输出端OUT持续去噪；同时，通过合理设置第一电容C1和第二电容C2的电容值，可以降低第一去噪控制节点PD_ox的电平对第四晶体管T4的偏置作用，延长移位寄存器单元100的工作寿命。
例如，考虑第一晶体管T1的阈值电压和第二晶体管T2的阈值电压的影响。在第一保持阶段P31，第一晶体管T1导通，第二去噪控制节点PD_ox_i的电平为VSS+|Vth_T1|，第一电容C1的与第二时钟信号端CB1连接的一端的电平为高电平(不防设为高电平VDD)，第二晶体管T2导通，第一去噪控制节点PD_ox的电平也为VSS+|Vth_T1|+|Vth_T2|，其中，Vth_T1表示第一晶体管T1的阈值电压，Vth_T2表示第二晶体管T2的阈值电压。在第二保持阶段P31，第一晶体管截止，第一电容C1的与第二时钟信号端CB1连接的一端的电平变为低电平(不防设为低电平VSS)；由于第一电容C1的自举效应，第二去噪控制节点PD_ox_i的电平相应发生变化，变化量为(VSS-VDD)*C1/C PD_ox_i，其中，C PD_ox_i＝C1+C2+C T1+C T2+C T5，C PD_ox_i表示第二去噪控制节点PD_ox_i所连接的各器件(包括第一晶体管T1、第二晶体管T2、第五晶体管T5、第一电容C1和第二电容C2)的总电容，C T1、C T2、C T5分别表示第一晶体管T1、第二晶体管T2、第五晶体管T5的与第二去噪控制节点PD_ox_i相关的寄生电容；从而，第二去噪控制节点PD_ox_i的电平被拉低至VSS+|Vth_T1|+(VSS-VDD)*C1/C PD_ox_i，同时，由于第一去噪控制节点PD_ox的电平为VSS+|Vth_T1|+|Vth_T2|，第二晶体管T2导通，部分电荷由第一去噪控制节点PD_ox流入第二去噪控制节点PD_ox_i，也即，第一去噪控制节点电平被拉低至某一小于VSS+|Vth_T1|+|Vth_T2|而大于VSS+|Vth_T1|+(VSS-VDD)*C1/C PD_ox_i的电平。此后，由于第一时钟信号CK1和第二时钟信号CB1交替为高电平和低电平，因此，在保持阶段P3，第一保持阶段P31和第二保持阶段P32会交替出现；从而，第一去噪控制节点PD_ox和第二去噪控制节点PD_ox_i之间进行多次耦合，直到第一去噪控制节点PD_ox的电平稳定在VSS+|Vth_T1|+|Vth_T2|(VSS-VDD)*C1/C PD_ox_i附近为止，进而使得第四晶体管T4在保持阶段P3持续导通，对第二输出端OUT持续去噪；同时，通过合理设置第一电容C1和第二电容C2的电容值，可以降低第一去噪控制节点PD_ox的电平对第四晶体管T4的偏置作用，延长移位寄存器单元100的工作寿命。
应当理解的是，图12中所示的各时钟信号的时序波形是示意性的。例如，在一些实施 例中，第一时钟信号CK1与第四时钟信号CK3可以相同，第二时钟信号CB1与第五时钟信号CB3可以相同；在此情况下，可以将第一时钟信号端CK1复用作第四时钟信号端CK3，将第二时钟信号端CB1复用作第五时钟信号端CB3。需要说明的是，本公开的实施例对此不作限制。
图11为本公开一些实施例提供的移位寄存器单元的另一种具体实现示例的电路结构示意图。如图11所示，该移位寄存器单元中的第二移位寄存器电路模块120可以实现为图8所示的第二移位寄存器电路模块120，此时，图11中的时钟信号端GCK3、GCK1、GCKO分别对应于图8中的第一时钟信号端CK1、第二时钟信号端CB1、第三时钟信号端CK2，也即，时钟信号端GCK3为第一时钟信号端，时钟信号端GCK1为第二时钟信号端，时钟信号端GCKO为第三时钟信号端；应当理解的是，图11所示的移位寄存器单元中的第二移位寄存器电路模块120也当然可以实现为图9所示的第二移位寄存器电路模块120；本公开的实施例对此不作限制。
如图11所示，该移位寄存器单元中的第一移位寄存器电路模块110可以包括第十一开关晶体管至第二十开关晶体管M11～M20以及第六电容C6和第七电容C7。第十一开关晶体管M11的栅极与第二时钟信号端GCK1连接以接收第二时钟信号GCK1，第十一开关晶体管M11的第二极与输入端IN连接以接收输入信号，第十一开关晶体管M11的第一极与第三节点PD_in连接；第十二开关晶体管M2的栅极与第二时钟信号端GCK1连接以接收第二时钟信号GCK1，第十二开关晶体管M12的第二极与第三节点PD_in连接，第十二开关晶体管M12的第一极与与第二节点PD_o连接；第十三开关晶体管M13的栅极与第二节点PD_o连接，第十三开关晶体管M13的第一极与第六时钟信号端GCK2连接以接收第六时钟信号GCK2，第十三开关晶体管M13的第二极与第一输出端GP连接；第七电容C7的第一端与第二节点PD_o连接，第七电容C7的第二端与第一输出端GP连接；第十四开关晶体管M14的栅极与第一节点PU连接，第十四开关晶体管M14的第一极与第二电压端VDD连接以接收第二电压VDD(例如，第二电压VDD为高电平)，第十四开关晶体管M14的第二极与第一输出端GP连接；第六电容C6的第一端与第一节点PU连接，第六电容C6的第二端与第二电压端VDD连接；第十五开关晶体管M15的栅极与第一时钟信号端GCK3连接以接收第一时钟信号，第十五开关晶体管M15的第一极与第一节点PU连接，第十五开关晶体管M15的第二极与第一电压端VSS连接以接收第一电压VSS(例如，第一电压VSS为低电平)；第十六开关晶体管M16的栅极与第一节点PU连接，第十六开关晶体管M16的第一极与第二电压端VDD连接以接收第二电压VDD，第十六开关晶体管M16的第二极与第四节点PD_f连接；第十七开关晶体管M17的栅极与第一节点PU连接，第十七开关晶体管M17的第一极与第四节点PD_f连接，第十七开关晶体管M17的第二极与第二节点PD_o连接；第十八开关晶体管M18的栅极与第二节点PD_o连接，第十八开关晶体管M18的第一极与第四节点PD_f连接，第十八开关晶体管M18的第一极与第一电压端VSS连接以接收第一电压VSS；第十九开关晶体管M19的栅极与输入端IN连接以接收输入信 号，第十九开关晶体管M19的第一极与第二电压端VDD连接以接收第二电压VDD，第十九开关晶体管M19的第二极与第一节点PU连接；第二十开关晶体管M20的栅极与第一输出端GP连接以接收第一输出信号，第二十开关晶体管M20的第一极与第六时钟信号端GCK2连接以接收第二时钟信号GCK2，第二十开关晶体管M20的第二极与第三节点PD_in连接。
图13为图11所示的移位寄存器单元工作时的信号时序图。下面结合图13所示的信号时序图，对图11所示的移位寄存器单元的工作原理进行简要说明。如图13所示，图11所示的移位寄存器单元的工作过程包括3个阶段，分别为第一阶段P1(也称为输入阶段)、第二阶段P2(也称为输出阶段)和保持阶段包括第一保持阶段P31、第二保持阶段P32等等)。图13示出了每个阶段中各个信号的时序波形。需要说明的是，图13中所示的信号时序图的电位的高低仅是示意性的，不代表真实电位值或相对比例，对于本公开的实施例而言，低电平信号对应于P型晶体管的开启信号，而高电平信号对应于P型晶体管的截止信号。
在第一阶段P1，如图13所示，第一时钟信号GCK3为高电平，第二时钟信号GCK1为低电平，第三时钟信号GCKO为低电平，第六时钟信号GCK2为高电平，输入端IN为低电平(即输入端IN接收低电平的输入信号)，从而，第一晶体管T1截止，开关晶体管M11、M12、M19导通，开关晶体管M15截止。导通的开关晶体管M19将第二电压VDD(高电平)传输至第一节点PU，使得第一节点PU的电平变为高电平，并存储在第六电容C6中，相应地，开关晶体管M14、M16、M17截止；导通的开关晶体管M11和M12将低电平的输入信号IN传输至第二节点PD_o，使得第二节点PD_o的电平变为低电平，并存储在第七电容C7中；开关晶体管M13响应于第二节点PD_o的低电平导通，将第六时钟信号GCK2的高电平传输至第一输出端GP，从而，在此阶段，移位寄存器单元的第一输出端GP输出高电平，相应地，开关晶体管M20、第五晶体管T5和第六晶体管T6响应于第一输出端GP的高电平截止；另外，第七晶体管M7响应于第二节点PD_o的低电平导通，将第三时钟信号GCKO的低电平传输至第二输出端OUT；从而，在此阶段，移位寄存器单元的第二输出端OUT输出低电平，即实现了对第二输出端OUT的去噪。
在第二阶段P2，如图13所示，第一时钟信号GCK3为高电平，第二时钟信号GCK1为高电平，第三时钟信号GCKO为高电平，第六时钟信号GCK2为低电平，输入端IN为高电平，从而，第一晶体管T1截止，开关晶体管M11、M12、M15、M19截止。由于第六电容C6的存储作用，第一节点PU可以继续保持上一阶段的高电平，从而开关晶体管M14、M16、M17仍然截止；由于第七电容C7的存储作用，第二节点PD_o可以继续保持上一阶段的低电平，从而，开关晶体管M13仍然导通；导通的开关晶体管M13将第六时钟信号GCK2的低电平传输至第一输出端GP，从而，在此阶段，移位寄存器单元的第一输出端GP输出低电平，即输出第一输出信号，例如，该第一输出信号可以作为下一级移位寄存器单元的输入信号，当然也可以用于控制例如图1中所示的像素电路S中的P型晶体管工作； 开关晶体管M20响应于第一输出端GP的低电平(即第一输出信号)导通，将第六时钟信号GCK2的低电平传输至第三节点PD_in，从而可以减少第二节点PD_o漏电；另外，第五晶体管T5和第六晶体管T6响应于第一输出端GP的低电平导通，将第二电压VDD(高电平)分别传输至第二去噪控制节点PD_ox_i和第一去噪控制节点PD_ox，从而使得第二去噪控制节点PD_ox_i和第一去噪控制节点PD_ox的电平均变为高电平，相应地，第四晶体管T4截止；第七晶体管T7仍然在第二节点PD_o的低电平的控制下保持导通，将第三时钟信号GCKO的高电平传输至第二输出端OUT；从而，在此阶段，移位寄存器单元的第二输出端OUT输出高电平，即输出第二输出信号，例如，该第二输出信号可以用于控制例如图1中所示的像素电路S中的N型晶体管工作。例如，如图13所示，第三时钟信号GCKO的高脉冲脉宽小于时钟信号GCK1/2/3的低脉冲脉宽，因此第三时钟信号GCKO的脉冲(包括上升沿和下降沿)可全部传输到第二输出端OUT。
在保持阶段的第一保持阶段P31，如图13所示，第一时钟信号GCK3为低电平，第二时钟信号GCK1为高电平，第三时钟信号GCKO为低电平，第六时钟信号GCK2为高电平，输入端IN为高电平，从而，第一晶体管T1导通，开关晶体管M11、M12、M19截止，开关晶体管M15导通。导通的开关晶体管M15将第一电压VSS(低电平)传输至第一节点PU，从而使得第一节点PU的电平变为低电平，并存储在第六电容C6中，相应地，开关晶体管M14、M16、M17导通；导通的开关晶体管M16和M17将第二电压VDD(高电平)传输至第二节点PD_o，从而使得第二节点PD_o的电平变为高电平，并存储在第七电容C7中，相应地，开关晶体管M13截止；导通的开关晶体管M14将第二电压VDD(高电平)输出至第一输出端GP，从而，在此阶段，移位寄存器单元的第一输出端GP输出高电平，相应地，开关晶体管M20、第五晶体管T5和第六晶体管T6响应于第一输出端GP的高电平截止；另外，导通的第一晶体管T1将第一电压VSS(低电平)传输至第二去噪控制节点PD_ox_i，从而使得第二去噪控制节点PD_ox_i的电平变为低电平，并存储在第一电容C1和第二电容C2中；第二晶体管T2在第二去噪控制节点PD_ox_i的低电平控制下导通，从而第一去噪控制节点PD_ox的电平也变为低电平，并存储在第三电容C3中；第四晶体管T4响应于第一去噪控制节点PD_ox的低电平导通，将第一电压VSS(低电平)传输至第二输出端OUT；第七晶体管T7响应于第二节点PD_o的高电平截止；从而，在此阶段，移位寄存器单元的第二输出端OUT输出低电平，即实现了对第二输出端OUT的去噪。
在保持阶段的第二保持阶段P32，如图13所示，第一时钟信号GCK3为高电平，第二时钟信号GCK1为低电平，第三时钟信号GCKO为低电平，第六时钟信号GCK2为高电平，输入端IN为高电平，从而，第一晶体管T1导通，开关晶体管M11、M12、M15、M19截止。由于第六电容C6的存储作用，第一节点PU可以继续保持上一阶段的低电平，相应地，开关晶体管M14、M16、M17保持导通；导通的开关晶体管M16和M17将第二电压VDD(高电平)传输至第二节点PD_o，从而使得第二节点PD_o的电平保持为高电平，相应地，开关晶体管M13截止；导通的开关晶体管M14将第二电压VDD(高电平)输出至第一输 出端GP，从而，在此阶段，移位寄存器单元的第一输出端GP输出高电平，相应地，开关晶体管M20、第五晶体管T5和第六晶体管T6响应于第一输出端GP的高电平截止；另外，第二时钟信号GCK1从高电平变为低电平，由于第一电容C1的自举效应，处于悬浮状态的第二去噪控制节点PD_ox_i的电平被进一步拉低，同时，由于第二电容C2的耦合作用，第二去噪控制节点PD_ox_i的电平变化小于第二时钟信号GCK1的电平变化，即第二电容C2降低了第一电容C1调节第二去噪控制节点PD_ox_i的电平的调节量；第二晶体管T2在第二去噪控制节点PD_ox_i的低电平控制下导通，从而第一去噪控制节点PD_ox的电平也被进一步拉低；第四晶体管T4响应于第一去噪控制节点PD_ox的低电平导通，将第一电压VSS(低电平)传输至第二输出端OUT；第七晶体管T7响应于第二节点PD_o的高电平截止；从而，在此阶段，移位寄存器单元的第二输出端OUT仍然输出低电平，即实现了对第二输出端OUT的持续去噪。
如上所述，在保持阶段P3，第一节点PU的电平保持为低电平，第二节点PD_o的电平保持为高电平，相应地，第一输出端GP保持输出高电平，第五晶体管T5、第六晶体管T6、第七晶体管T7始终保持截止状态，因此，第二去噪控制节点PD_ox_i的电平和第一去噪控制节点PD_ox的电平仅受第一晶体管T1、第二晶体管T2、第一电容C1、第二电容C2、第三电容C3的影响，也即仅受第二去噪控制电路124的影响。因此，图11所示的移位寄存器单元在保持阶段P3中的第二去噪控制节点PD_ox_i的电平变化和第一去噪控制节点PD_ox的电平变化可以参考图10所示的移位寄存器单元在保持阶段P3中的第二去噪控制节点PD_ox_i的电平变化和第一去噪控制节点PD_ox的电平变化的相关描述，在此不再重复赘述。
应当理解的是，图13中所示的各时钟信号的时序波形是示意性的，本公开的实施例对此不作限制。
需要说明的是，本公开的实施例提供的移位寄存器单元100中的第一移位寄存器电路模块110不限于上述图10和图11所示的第一移位寄存器电路模块110的电路结构，只要其能够满足根据输入端接收的输入信号在第一输出端GP输出第一输出信号以及向第二移位寄存器电路模块120提供开启控制信号即可，本公开的实施例对此不作限制。
需要说明的是，本公开实施例中提供的移位寄存器单元的“有效电平”指的是能够使得其包括的被操作晶体管被导通的电平，相应地“无效电平”指的是不能使得其包括的被操作晶体管被导通(即，该晶体管被截止)的电平。根据移位寄存器单元的电路结构中的晶体管的类型(N型或P型)等因素，有效电平可以比无效电平高或者低。例如，在本公开实施例中，当各个晶体管均为P型晶体管时，有效电平为低电平，无效电平为高电平。
需要说明的是，在本公开的实施例中，电容可以是通过工艺制程制作的电容器件，例如通过制作专门的电容电极来实现电容器件，电容的各个电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现，并且，电容也可以是各个器件之间的寄生电容，可以通过晶体管本身与其他器件、线路来实现。电容的连接方式不局限于上面描述的方式，也可以为 其他适用的连接方式，只要能存储相应节点的电平即可。
需要注意的是，在本公开的各个实施例的说明中，各个节点并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
另外，在本公开的实施例中的晶体管均以P型晶体管为例进行说明，此时，晶体管的第一极是源极，第二极是漏极。需要说明的是，本公开包括但不限于此。例如，本公开的实施例提供的移位寄存器单元100中的一个或多个晶体管也可以采用N型晶体管，此时，晶体管第一极是漏极，第二极是源极，只需将选定类型的晶体管的各极参照本公开的实施例中的相应晶体管的各极相应连接，并且使相应的电压端提供对应的高电压或低电压即可。当采用N型晶体管时，可以采用氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)作为薄膜晶体管的有源层，相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及防止漏电流。
本公开一些实施例提供的移位寄存器单元，通过在第二去噪控制电路中引入由第一控制电路、第一耦合电路、第二耦合电路、传输电路和存储电路形成的电荷泵结构，利用电荷泵结构对电压的调节作用，可以调节第一去噪控制节点的电平；从而，一方面，确保去噪电路在保持阶段持续开启，及时去除噪声干扰，另一方面，降低第一去噪控制节点的电平对去噪电路的偏置作用，延长移位寄存器单元的工作寿命。
本公开至少一个实施例还提供一种栅极驱动电路。例如，参考图1所示，该栅极驱动电路包括多个级联的移位寄存器单元RS(如图1中的RS_1、RS_2、……、RS_N所示)，其中任意一个或多个移位寄存器单元RS可以采用本公开任一实施例提供的移位寄存器单元100的结构或其变型，例如，可以采用图10或图11中所示的移位寄存器单元100。
例如，该栅极驱动电路可以采用与薄膜晶体管同样的半导体制程的工艺直接集成在显示装置的阵列基板上，以实现逐行或隔行扫描驱动功能。例如，如图1所示，在该栅极驱动电路中，除第一级移位寄存器单元外，其余各级移位寄存器单元的输入端IN和上一级移位寄存器单元的第一输出端GP连接。例如，如图1所示，第一级移位寄存器单元的输入端IN可以被配置为接收触发信号STV。例如，该栅极驱动电路中的每一级移位寄存器单元的工作原理可以参考本公开的实施例提供的移位寄存器单元的工作原理的相应描述，在此不再重复赘述。例如，该栅极驱动电路的更多细节可以参考前述图1的相关描述，在此不再重复赘述。
本公开的实施例提供的栅极驱动电路的技术效果可以参考上述实施例中关于移位寄存器单元100的相应描述，在此不再重复赘述。
本公开至少一个实施例还提供一种显示装置。例如，参考图1所示，该显示装置可以包括本公开任一实施例提供的栅极驱动电路。例如，参考图1所示，该显示装置还可以包括显示面板01，显示面板01包括阵列排布的多个多个子像素P，每个子像素P包括像素电路S。例如，参考图1所示，显示面板01还包括多条栅线GL(如图1中的G_1、G_2、……、G_N所示，其中N为正整数)，移位寄存器中的各级移位寄存器单元RS的第二输出端OUT与该多条栅线GL中的至少一条栅线连接，从而可以分别向相应行的像素电路S提供扫描信号。
例如，参考图1所示，该显示装置还可以包括数据驱动电路。数据驱动电路通过显示面板01上的数据线DL(Data Line，如图1中的D_1、D_2、……、D_M等所示，其中M为正整数)与像素电路S连接，用于提供数据信号给像素阵列。
需要说明的是，本实施例中的显示装置可以为显示器、OLED面板、OLED电视、电子纸显示装置、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开的实施例对此不作限定。
需要说明的是，为表示清楚、简洁，并没有给出该显示装置1的全部结构。为实现显示装置的必要功能，本领域技术人员可以根据具体应用场景进行设置其他未示出的结构，本公开的实施例对此不做限制。
本公开的实施例提供的显示装置的技术效果可以参考上述实施例中关于栅极驱动电路的相应描述，这里不再赘述。
本公开至少一个实施例还提供一种移位寄存器单元的驱动方法，可以用于驱动本公开的实施例提供的移位寄存器单元100。例如，该驱动方法包括保持阶段；其中，在保持阶段，交替地输入第一时钟信号CK1和第二时钟信号CB1，通过第二去噪控制电路124调节第一去噪控制节点PD_ox的电平，以开启去噪电路122，使去噪电路122对第二输出端OUT去噪。例如，该驱动方法的具体细节可以参考图10和图11所示的移位寄存器单元的工作原理的相关描述，在此不再重复赘述。
本公开的实施例提供的移位寄存器单元的驱动方法的技术效果可以参考上述实施例中关于移位寄存器单元100的相应描述，在此不再重复赘述。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种移位寄存器单元，包括：第一移位寄存器电路模块和第二移位寄存器电路模块；其中，
    所述第一移位寄存器电路模块被配置为根据输入端接收的输入信号在第一输出端输出第一输出信号以及向所述第二移位寄存器电路模块提供开启控制信号；
    所述第二移位寄存器电路模块包括输出电路、去噪电路、第一去噪控制电路和第二去噪控制电路，
    所述输出电路被配置为响应于所述开启控制信号，在第二输出端输出第二输出信号，
    所述去噪电路被配置为在第一去噪控制节点的电平的控制下，对所述第二输出端去噪，
    所述第一去噪控制电路被配置为响应于所述第一输出信号，控制所述第一去噪控制节点的电平，以关闭所述去噪电路，
    所述第二去噪控制电路被配置为在第一时钟信号和第二时钟信号的控制下，调节所述第一去噪控制节点的电平，以开启所述去噪电路；
    其中，所述第二去噪控制电路包括第一控制电路、第一耦合电路、第二耦合电路、传输电路和存储电路，
    所述第一控制电路被配置为在第一时钟信号的控制下，将第一电压传输至第二去噪控制节点，
    所述第一耦合电路被配置为存储所述第二去噪控制节点的电平，以及在第二时钟信号的控制下调节所述第二去噪控制节点的电平，
    所述第二耦合电路被配置为存储所述第二去噪控制节点的电平，以及降低所述第一耦合电路调节所述第二去噪控制节点的电平的调节量，
    所述传输电路被配置为连接所述第一去噪控制节点和所述第二去噪控制节点，以平衡所述第一去噪控制节点的电平和所述第二去噪控制节点的电平，
    所述存储电路被配置为存储所述第一去噪控制节点的电平。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述第一控制电路包括第一晶体管，所述第一耦合电路包括第一电容，所述第二耦合电路包括第二电容，所述传输电路包括第二晶体管，所述存储电路包括第三电容；
    所述第一晶体管的栅极与第一时钟信号端连接以接收所述第一时钟信号，所述第一晶体管的第一极与第一电压端连接以接收所述第一电压，所述第一晶体管的第二极与第二去噪控制节点连接；
    所述第一电容的第一端与所述第二去噪控制节点连接，所述第一电容的第二端与第二时钟信号端连接以接收所述第二时钟信号；
    所述第二电容的第一端与所述第二去噪控制节点连接，所述第二电容的第二端与所述第一电压端连接；
    所述第二晶体管的栅极与所述第二去噪控制节点连接，所述第二晶体管的第一极与所 述第一去噪控制节点连接，所述第二晶体管的第二极与所述第二去噪控制节点连接；
    所述第三电容的第一端与所述第一去噪控制节点连接，所述第三电容的第二端与所述第一电压端连接。
  3. 根据权利要求1或2所述的移位寄存器单元，其中，所述第二去噪控制电路还包括第二控制电路，
    所述第二控制电路被配置为在所述第二输出端的电平的控制下，将所述第二时钟信号传输至所述第一耦合电路。
  4. 根据权利要求3所述的移位寄存器单元，其中，所述第二控制电路包括第三晶体管，所述第一电容的第二端通过所述第三晶体管与所述第二时钟信号端连接，
    所述第三晶体管的栅极与所述第二输出端连接，所述第三晶体管的第一极与所述第二时钟信号端连接，所述第三晶体管的第二极与所述第一电容的第二端连接。
  5. 根据权利要求1-4任一项所述的移位寄存器单元，其中，
    所述去噪电路被配置为在所述第一去噪控制节点的电平的控制下，将所述第一电压传输至所述第二输出端，以对所述第二输出端去噪。
  6. 根据权利要求5所述的移位寄存器单元，其中，所述去噪电路包括第四晶体管，
    所述第四晶体管的栅极与所述第一去噪控制节点连接，所述第四晶体管的第一极与第一电压端连接以接收所述第一电压，所述第四晶体管的第二极与所述第一输出端连接。
  7. 根据权利要求5或6所述的移位寄存器单元，其中，在所述第二去噪控制电路的调节下，所述第一去噪控制节点的电平与所述第一电压的差为所述去噪电路的阈值电压的n倍，其中，1≤n≤10。
  8. 根据权利要求1-7任一项所述的移位寄存器单元，其中，所述第一去噪控制电路还被配置为响应于所述第一输出信号，控制所述第二去噪控制节点的电平。
  9. 根据权利要求8所述的移位寄存器单元，其中，所述第一去噪控制电路包括第五晶体管和第六晶体管；
    所述第五晶体管的栅极与所述第一输出端连接以接收所述第一输出信号，所述第五晶体管的第一极与第一信号端连接以接收第一信号电平，所述第五晶体管的第二极与所述第一去噪控制节点连接；
    所述第六晶体管的栅极与所述第一输出端连接以接收所述第一输出信号，所述第六晶体管的第一极与所述第一信号端连接以接收所述第一信号电平，所述第六晶体管的第二极与所述第二去噪控制节点连接。
  10. 根据权利要9所述的移位寄存器单元，其中，
    所述第一信号端为用于提供第二电压的第二电压端，所述第一信号电平为所述第二电压；或者，
    所述第一信号端与所述第一移位寄存器电路模块中的第一节点连接，所述第一信号电平为所述第一节点的电平。
  11. 根据权利要求1-10任一项所述的移位寄存器单元，其中，所述输出电路包括第七晶体管，
    所述第七晶体管的栅极与第二信号端连接以接收所述开启控制信号，所述第七晶体管的第一极与第三时钟信号端连接以接收第三时钟信号，所述第七晶体管的第二极与所述第二输出端连接。
  12. 根据权利要求11所述的移位寄存器单元，其中，
    所述第二信号端与所述第一移位寄存器电路模块中的第二节点连接。
  13. 根据权利要求1-12任一项所述的移位寄存器单元，其中，所述第一移位寄存器电路模块包括：第一开关晶体管、第二开关晶体管、第三开关晶体管、第四开关晶体管、第五开关晶体管、第六开关晶体管、第七开关晶体管、第八开关晶体管、第四电容和第五电容；
    所述第一开关晶体管的栅极与第四时钟信号端连接以接收第四时钟信号，所述第一开关晶体管的第一极与第三节点连接，所述第一开关晶体管的第二极与所述输入端连接；
    所述第二开关晶体管的栅极与第三节点连接，所述第二开关晶体管的第一极与第一节点连接，所述第二开关晶体管的第二极与所述第四时钟信号端连接以接收所述第四时钟信号；
    所述第三开关晶体管的栅极与所述第四时钟信号端连接以接收所述第四时钟信号，所述第三开关晶体管的第一极与所述第一节点连接，所述第三开关晶体管的第二极与第一电压端连接以接收第一电压；
    所述第四开关晶体管的栅极与所述第一节点连接，所述第四开关晶体管的第一极与第二电压端连接以接收第二电压，所述第四开关晶体管的第二极与所述第一输出端连接；
    所述第四电容的第一端与所述第一节点连接，所述第四电容的第二端与所述第二电压端连接；
    所述第五开关晶体管的栅极与第二节点连接，所述第五开关晶体管的第一极与第五时钟信号端连接以接收第五时钟信号，所述第五开关晶体管的第二极与所述第一输出端连接；
    所述第五电容的第一端与所述第二节点连接，所述第五电容的第二端与所述第一输出端连接；
    所述第六开关晶体管的栅极与所述第一节点连接，所述第六开关晶体管的第一极与所述第二电压端连接以接收所述第二电压，所述第六开关晶体管的第二极与第四节点连接；
    所述第七开关晶体管的栅极与所述第五时钟信号端连接以接收所述第五时钟信号，所述第七开关晶体管的第一极与所述第三节点连接，所述第七开关晶体管的第二极与所述第四节点连接；
    所述第八开关晶体管的栅极与所述第一电压端连接以接收所述第一电压，所述第八开关晶体管的第一极与所述第二节点连接，所述第八开关晶体管的第二极与所述第三节点连接。
  14. 根据权利要求1-12任一项所述的移位寄存器单元，其中，所述第一移位寄存器电路模块包括：第十一开关晶体管、第十二开关晶体管、第十三开关晶体管、第十四开关晶体管、第十五开关晶体管、第十六开关晶体管、第十七开关晶体管、第十八开关晶体管、第十九开关晶体管、第二十开关晶体管、第六电容和第七电容；
    所述第十一开关晶体管的栅极与第二时钟信号端连接以接收所述第二时钟信号，所述第十一开关晶体管的第二极与所述输入端连接以接收所述输入信号，所述第十一开关晶体管的第一极与第三节点连接；
    所述第十二开关晶体管的栅极与所述第二时钟信号端连接以接收所述第二时钟信号，所述第十二开关晶体管的第二极与所述第三节点连接，所述第十二开关晶体管的第一极与与第二节点连接；
    所述第十三开关晶体管的栅极与所述第二节点连接，所述第十三开关晶体管的第一极与第六时钟信号端连接以接收第六时钟信号，所述第十三开关晶体管的第二极与所述第一输出端连接；
    所述第七电容的第一端与所述第二节点连接，所述第七电容的第二端与所述第一输出端连接；
    所述第十四开关晶体管的栅极与第一节点连接，所述第十四开关晶体管的第一极与第二电压端连接以接收第二电压，所述第十四开关晶体管的第二极与所述第一输出端连接；
    所述第六电容的第一端与所述第一节点连接，所述第六电容的第二端与第二电压端连接；
    所述第十五开关晶体管的栅极与第一时钟信号端连接以接收所述第一时钟信号，所述第十五开关晶体管的第一极与所述第一节点连接，所述第十五开关晶体管的第二极与第一电压端连接以接收第一电压；
    所述第十六开关晶体管的栅极与所述第一节点连接，所述第十六开关晶体管的第一极与所述第二电压端连接以接收所述第二电压，所述第十六开关晶体管的第二极与第四节点连接；
    所述第十七开关晶体管的栅极与所述第一节点连接，所述第十七开关晶体管的第一极与所述第四节点连接，所述第十七开关晶体管M17的第二极与所述第二节点连接；
    所述第十八开关晶体管的栅极与所述第二节点连接，所述第十八开关晶体管的第一极与所述第四节点连接，所述第十八开关晶体管的第一极与所述第一电压端连接以接收所述第一电压；
    所述第十九开关晶体管的栅极与所述输入端连接以接收所述输入信号，所述第十九开关晶体管的第一极与所述第二电压端连接以接收所述第二电压，所述第十九开关晶体管的第二极与所述第一节点连接；
    所述第二十开关晶体管的栅极与所述第一输出端连接以接收所述第一输出信号，所述第二十开关晶体管的第一极与所述第六时钟信号端连接以接收所述第六时钟信号，所述第 二十开关晶体管的第二极与所述第三节点连接。
  15. 一种栅极驱动电路，包括：多个级联的根据权利要求1-14任一所述的移位寄存器单元。
  16. 根据权利要求15所述的栅极驱动电路，其中，除第一级移位寄存器单元外，其余各级移位寄存器单元的输入端和上一级移位寄存器单元的第一输出端连接。
  17. 一种显示装置，包括根据权利要求15或16所述的栅极驱动电路。
  18. 根据权利要求17所述的显示装置，还包括：多条栅线，其中，各级移位寄存器单元的第二输出端与所述多条栅线中的至少一条栅线连接。
  19. 一种根据权利要求1-14任一项所述的移位寄存器单元的驱动方法，包括：保持阶段，其中，
    在所述保持阶段，交替地输入所述第一时钟信号和所述第二时钟信号，通过所述第二去噪控制电路调节所述第一去噪控制节点的电平，以开启所述去噪电路，使所述去噪电路对所述第二输出端去噪。
PCT/CN2021/081786 2021-03-19 2021-03-19 移位寄存器单元及驱动方法、栅极驱动电路、显示装置 WO2022193281A1 (zh)

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US20230360608A1 (en) 2023-11-09

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