WO2020173229A1 - 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置 - Google Patents

移位寄存器单元及其驱动方法、栅极驱动电路、显示装置 Download PDF

Info

Publication number
WO2020173229A1
WO2020173229A1 PCT/CN2020/070866 CN2020070866W WO2020173229A1 WO 2020173229 A1 WO2020173229 A1 WO 2020173229A1 CN 2020070866 W CN2020070866 W CN 2020070866W WO 2020173229 A1 WO2020173229 A1 WO 2020173229A1
Authority
WO
WIPO (PCT)
Prior art keywords
node
transistor
output
signal
terminal
Prior art date
Application number
PCT/CN2020/070866
Other languages
English (en)
French (fr)
Inventor
冯雪欢
李永谦
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP20763467.6A priority Critical patent/EP3933817A4/en
Priority to US16/765,565 priority patent/US11328672B2/en
Publication of WO2020173229A1 publication Critical patent/WO2020173229A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the embodiments of the present disclosure relate to a shift register unit and a driving method thereof, a gate driving circuit, and a display device.
  • a display panel such as a liquid crystal display (LCD) or an organic light emitting diode (OLED) display panel, includes multiple gate lines and multiple data lines.
  • the gate line can be driven by a gate drive circuit.
  • the gate drive circuit is usually integrated in the gate drive chip (Gate Integrated Circuit).
  • the gate drive chip Gate Integrated Circuit
  • Some embodiments of the present disclosure provide a shift register unit including: a first input circuit, a second input circuit, an output circuit, and a compensation circuit.
  • the first input circuit is connected to a first node and is configured to respond to a first control. Signal writes a first input signal to the first node;
  • the second input circuit is connected to the first node and the second node, and is configured to input a second input signal to the The second node, and transmits the level of the second node to the first node in response to a second control signal;
  • the compensation circuit is connected to the second node and is configured to Level compensation;
  • the output circuit is connected to the first node and the output terminal, and is configured to output a composite output signal to the output terminal under the control of the level of the first node.
  • the compensation circuit includes a first compensation sub-circuit, a second compensation sub-circuit, and a storage sub-circuit, and the first compensation sub-circuit is connected to the first compensation sub-circuit.
  • Two nodes and a third node and are configured to write the first clock signal into the third node under the control of the level of the second node;
  • the storage sub-circuit is connected to the second node respectively And the third node, and is configured to compensate the level of the second node based on the first clock signal written to the third node;
  • the second compensation sub-circuit is connected to the
  • the third node is configured to perform noise reduction on the third node under the control of the compensation noise reduction signal.
  • the second compensation sub-circuit is further connected to a fourth node to receive the voltage of the fourth node as the compensation noise reduction signal.
  • the first compensation sub-circuit includes a first compensation transistor
  • the second compensation sub-circuit includes a second compensation transistor
  • the storage sub-circuit includes a first compensation transistor.
  • Capacitor the first pole of the first compensation transistor is connected to the first clock signal terminal to receive the first clock signal
  • the second pole of the first compensation transistor is connected to the third node
  • the first The gate of the compensation transistor is connected to the second node
  • the first terminal of the first capacitor is connected to the second node
  • the second terminal of the first capacitor is connected to the third node.
  • the first pole of the two compensation transistors is connected to the third node
  • the second pole of the second compensation transistor is connected to the first voltage terminal
  • the gate of the second compensation transistor is connected to the fourth node.
  • the first clock signal and the second control signal are the same.
  • the second input circuit includes a charging sub-circuit and an isolating sub-circuit, and the charging sub-circuit is configured to respond to the detection control signal to The second input signal is input to the second node; the isolation sub-circuit is respectively connected to the first node and the second node, and is configured to, under the control of the second control signal, connect the second The level of the node is transmitted to the first node.
  • the charging sub-circuit includes a first transistor, and the gate of the first transistor is configured to receive the detection control signal.
  • the first pole is configured to receive the second input signal, the second pole of the first transistor is connected to the second node;
  • the isolation sub-circuit includes a second transistor, and the gate of the second transistor is configured To receive the second control signal, the first electrode of the second transistor is connected to the second node, and the first electrode of the second transistor is connected to the first node.
  • the first input circuit includes a third transistor, and the gate of the third transistor is connected to the first control signal terminal to receive the first control signal
  • the first pole of the third transistor is configured to receive the first input signal
  • the second pole of the third transistor is connected to the first node.
  • the output terminal includes a shift signal output terminal and a first scan signal output terminal
  • the output circuit includes a first output transistor, a second output transistor, and a first output transistor.
  • Two capacitors the gate of the first output transistor is connected to the first node, the first pole of the first output transistor is connected to the first output clock signal terminal to receive the first output clock signal, the first The second pole of the output transistor is connected to the shift signal output terminal; the gate of the second output transistor is connected to the first node, and the first pole of the second output transistor is connected to the first output clock
  • the signal terminal is connected to receive the first output clock signal, the second pole of the second output transistor is connected to the first scan signal output terminal; the first terminal of the second capacitor is connected to the first node , The second terminal of the second capacitor is connected to the second terminal of the second output transistor; the first output clock signal is transmitted to the shift signal output terminal via the first output transistor to serve as a first Output signal, the first output clock signal is transmitted
  • the output terminal further includes a second scan signal output terminal
  • the output circuit further includes a third output transistor and a third capacitor
  • the third output transistor The gate of the third output transistor is connected to the first node, the first electrode of the third output transistor is connected to the second output clock signal terminal to receive the second output clock signal, and the second electrode of the third output transistor is connected to the The second scan signal output end is connected, the first end of the third capacitor is connected to the first node, the second end of the third capacitor is connected to the second electrode of the third output transistor, and the first The second output clock signal is transmitted to the second scan signal output terminal via the third output transistor as a third output signal, and the composite output signal further includes the third output signal.
  • the shift register unit provided by some embodiments of the present disclosure further includes a noise reduction circuit and a first control circuit
  • the noise reduction circuit is connected to the first node, the fourth node and the output terminal, and is configured to Under the control of the level of the fourth node, the first node and the output terminal are simultaneously noise-reduced
  • the first control circuit is connected to the first node and the fourth node, and is configured to Under the control of the level of the first node, the level of the fourth node is controlled.
  • the shift register unit provided by some embodiments of the present disclosure further includes a second control circuit connected to the fourth node and configured to respond to the level of the fourth node in response to the third control signal.
  • the third control signal includes a first clock signal and a voltage value of the second node.
  • the shift register unit provided by some embodiments of the present disclosure further includes a third control circuit connected to the fourth node and configured to respond to the level of the fourth node on the fourth control signal. Take control.
  • the shift register unit provided by some embodiments of the present disclosure further includes: a first reset circuit and a second reset circuit, the first reset circuit is connected to the first node and is configured to respond to a first reset control signal The first node is reset; the second reset circuit is connected to the first node and is configured to reset the first node in response to a second reset control signal.
  • the shift register unit provided by some embodiments of the present disclosure further includes: a noise reduction circuit, a first control circuit, a second control circuit, a third control circuit, a first reset circuit, and a second reset circuit
  • the compensation circuit includes The first compensation transistor, the second compensation transistor and the first capacitor, the first pole of the first compensation transistor is connected to the first clock signal terminal to receive the first clock signal, and the second pole of the first compensation transistor is connected to At the third node, the gate of the first compensation transistor is connected to the second node, the first terminal of the first capacitor is connected to the second node, and the second terminal of the first capacitor is connected to the second node.
  • the third node, the first pole of the second compensation transistor is connected to the third node, the second pole of the second compensation transistor is connected to the first voltage terminal, and the gate of the second compensation transistor is connected To the fourth node, to receive the voltage of the fourth node as a compensation noise reduction signal;
  • the second input circuit includes a charging sub-circuit and an isolating sub-circuit, the charging sub-circuit includes a first transistor, the first transistor The gate of the first transistor is configured to receive the detection control signal, the first electrode of the first transistor is configured to receive the second input signal, and the second electrode of the first transistor is connected to the second node,
  • the isolating sub-circuit includes a second transistor, the gate of the second transistor is configured to receive the second control signal, the first pole of the second transistor is connected to the second node, and the second transistor The first electrode of the third transistor is connected to the first node;
  • the first input circuit includes a third transistor, and the gate of the third transistor is configured to receive the first control signal.
  • the electrode is configured to receive the first input signal, the second electrode of the third transistor is connected to the first node;
  • the output circuit includes a first output transistor, a second output transistor, a third output transistor, and a Two capacitors and a third capacitor, the output terminal includes a shift signal output terminal, a first scan signal output terminal and a second scan signal output terminal, the gate of the first output transistor is connected to the first node, so The first pole of the first output transistor is connected to the first output clock signal terminal to receive the first output clock signal, the second pole of the first output transistor is connected to the shift signal output terminal, and the second output The gate of the transistor is connected to the first node, the first electrode of the second output transistor is connected to the first output clock signal terminal to receive the first output clock signal, and the second output transistor has a The two electrodes are connected to the first scan signal output terminal, the first terminal of the second capacitor is connected to the first node, and the second terminal of the second capacitor is connected to the second electrode of the first output transistor.
  • the gate of the third output transistor is connected to the first node, the first pole of the third output transistor is connected to the second output clock signal terminal to receive the second output clock signal, the third output
  • the second electrode of the transistor is connected to the second scan signal output terminal, the first terminal of the third capacitor is connected to the first node, and the second terminal of the third capacitor is connected to the third output transistor.
  • the second pole of the body tube is connected, the first output clock signal is transmitted to the shift signal output terminal via the first output transistor as a first output signal, and the first output clock signal is passed through the second
  • the output transistor is transmitted to the first scan signal output terminal as a second output signal, and the second output clock signal is transmitted to the second scan signal output terminal through the third output transistor as a third output signal
  • the composite output signal includes the first output signal, the second output signal, and the third output signal
  • the noise reduction circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor, so
  • the gate of the fourth transistor is connected to the fourth node, the first electrode of the fourth transistor is connected to the first node, and the second electrode of the fourth transistor is connected to the first voltage terminal,
  • the gate of the fifth transistor is connected to the fourth node, the first electrode of the fifth transistor is connected to the shift signal output terminal, and the second electrode of the fifth transistor is connected to the first voltage
  • the gate of the sixth transistor is connected to the fourth node, the
  • Some embodiments of the present disclosure further provide a gate driving circuit, including a plurality of shift register units, the plurality of shift register units are cascaded, and each of the plurality of shift register units is such as The shift register unit described in any of the above embodiments.
  • the gate drive circuit further includes a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line.
  • the shift register unit includes a first output In the case of the clock signal terminal, the first output clock signal terminal of the 4n 1 -3th stage shift register unit of the multiple shift register units is connected to the first clock signal line; the multiple shift register units a first output terminal of the first clock signal 4n 1 -2-stage shift register unit is connected to the second clock signal line; a first plurality of said first shift register unit 4n 1 -1 stage shift register unit The output clock signal terminal is connected to the third clock signal line; the first output clock signal terminal of the 4n 1 -th stage shift register unit of the plurality of shift register units is connected to the fourth clock signal line; n 1 Is an integer greater than 0.
  • the gate drive circuit provided by some embodiments of the present disclosure further includes a fifth clock signal line, a sixth clock signal line, a seventh clock signal line, and an eighth clock signal line
  • the shift register unit includes a second output
  • the second output clock signal terminal of the 4n 1 -3th stage shift register unit is connected to the fifth clock signal line; the second output clock signal terminal of the 4n 1 -2th stage shift register unit
  • the output clock signal terminal is connected to the sixth clock signal line;
  • the second output clock signal terminal of the 4n 1 -1 stage shift register unit is connected to the seventh clock signal line;
  • the 4n 1 stage shifter The second output clock signal terminal of the bit register unit is connected to the eighth clock signal line.
  • the shift register unit includes a shift signal output terminal and a first control signal terminal
  • the n 2 th The first control signal terminal of the + 3 -stage shift register unit is connected to the shift signal output terminal of the n2-th stage shift register unit among the plurality of shift register units, and n 2 is an integer greater than 0.
  • the signal of the shift signal output terminal of the first n-stage shift register means as the output of the n-stage shift register unit 2 of +2 Two input signals.
  • the shift register unit further comprises a first reset control signal terminal
  • the first reset an n-stage shift register unit control signal Terminal is connected to the shift signal output terminal of the n 2 +3 stage shift register unit.
  • Some embodiments of the present disclosure also provide a display device including the gate driving circuit described in any of the above embodiments.
  • Some embodiments of the present disclosure further provide a method for driving the shift register unit as described in any of the above embodiments, wherein one frame includes a display period and a blanking period, and the display period includes a first input stage and a first In the output stage, the blanking period includes a second input stage and a second output stage, and the driving method includes: in the first input stage, in response to the first control signal, the first input circuit The first input signal is written to the first node; in the first output stage, under the control of the level of the first node, the output circuit outputs the composite output signal to the output In the second input stage, the compensation circuit compensates for the level of the second node, and the second input circuit responds to the second control signal to convert the second node The level is transmitted to the first node; in the second output stage, the output circuit outputs the composite output signal to the output terminal under the control of the level of the first node.
  • FIG. 1 is a schematic block diagram of a shift register unit provided by some embodiments of the present disclosure
  • 2A is a schematic block diagram of another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 2B is a schematic block diagram of yet another shift register unit provided by some embodiments of the present disclosure.
  • 3A is a schematic block diagram of a shift register unit provided by other embodiments of the present disclosure.
  • 3B is a schematic block diagram of another shift register unit provided by other embodiments of the present disclosure.
  • 3C is a schematic block diagram of another shift register unit provided by other embodiments of the present disclosure.
  • 3D is a schematic block diagram of still another shift register unit provided by other embodiments of the present disclosure.
  • 4A is a circuit structure diagram of the shift register unit shown in FIG. 3D;
  • 4B is another circuit structure diagram of the shift register unit shown in FIG. 3D;
  • FIG. 5 is a signal timing diagram of a shift register unit provided by some embodiments of the present disclosure.
  • FIG. 6 is a schematic block diagram of a gate driving circuit provided by some embodiments of the present disclosure.
  • FIG. 7 is a signal timing diagram of a gate driving circuit provided by some embodiments of the present disclosure.
  • FIG. 8 is a schematic block diagram of a display device provided by some embodiments of the present disclosure.
  • FIG. 9 is a flowchart of a driving method of a shift register unit provided by some embodiments of the present disclosure.
  • the pixel circuit includes a data writing transistor, a driving transistor, a storage capacitor, a sensing transistor, and a sensing line.
  • the threshold voltage of the driving transistor or the pixel circuit is sensed through the sensing transistor and the sensing line. Power supply voltage drop, etc., and compensate based on the sensing data on the sensing line.
  • the duty cycle of the pixel circuit also includes a display period and a sensing period (or blanking period).
  • the gate drive circuit When performing external compensation, during the display period of one frame (Display), the gate drive circuit needs to provide the display output signal for the data writing transistor, and during the blank period of one frame (Blank), the gate drive circuit needs to provide Used to sense the blanking output signal of the transistor.
  • the shift register unit of the gate drive circuit includes a detection sub-circuit, a display scanning sub-circuit, and a connection sub-circuit (OR gate circuit or Hiz circuit) that outputs the composite pulse of the two. ), at this time, the shift register unit can output a composite waveform output pulse composed of two waveforms with different widths and timings, so as to provide display output signals and blanking for the data writing transistor and the sensing transistor in the pixel circuit, respectively output signal.
  • the structure of the shift register unit is very complicated and the size is large, which is not conducive to achieving high resolution and narrow frame, and also not conducive to reducing chip area and cost.
  • the blanking output signal output by the gate drive circuit is sequentially scanned line by line.
  • the blanking output signal for the pixel unit of the first row in the display panel is output in the blanking period of the first frame
  • the blanking period of the frame outputs blanking output signals for the pixel units in the second row of the display panel, and so on, so as to complete the line-by-line sequential compensation of the display panel.
  • Long-term progressive compensation will bring two serious problems: one is that there will be a scan line that moves line by line during multi-frame scanning and display, and the other is due to the difference in compensation time on the display panel. The brightness of different areas varies greatly.
  • the shift register unit of the gate driving circuit includes a plurality of thin film transistors. Because the signal output by the thin film transistors has threshold loss, the pulse signal output by the shift register unit is inaccurate, which affects the display effect and reduces the display quality.
  • the shift register unit includes a first input circuit, a second input circuit, an output circuit, and a compensation circuit.
  • the first input circuit is connected to the first node and is configured to write the first input signal to the first node in response to the first control signal;
  • the second input circuit is connected to the first node and the second node and is configured to respond to detection control
  • the signal inputs the second input signal to the second node, and transmits the level of the second node to the first node in response to the second control signal;
  • the compensation circuit is connected to the second node and is configured to perform the level of the second node Compensation;
  • the output circuit is connected to the first node and the output terminal, and is configured to output the composite output signal to the output terminal under the control of the level of the first node.
  • the shift register unit has a simple circuit structure and can compensate for the threshold voltage loss of the level written to the first node during the blanking period, thereby preventing the threshold voltage loss of the transistor from affecting the output signal and enhancing the reliability of the circuit.
  • the shift register unit can also achieve random compensation, avoiding the deviation of the brightness of the scan line and the panel caused by the line-by-line sequential compensation, improving the display uniformity, and improving the display effect.
  • random compensation refers to an external compensation method that is different from line-by-line sequential compensation.
  • the output can be randomly output during the blanking period of a certain frame.
  • the following embodiments are the same, and will not be repeated.
  • “one frame”, “every frame” or “a certain frame” includes a display period and a blanking period that are sequentially performed.
  • the gate driving circuit outputs a plurality of Display output signals.
  • the multiple display output signals can drive the display panel from the first line to the last line to complete the scanning and display of a complete image.
  • the gate drive circuit outputs a blanking output signal.
  • the output signal can be used to drive the sensing transistors in a row of pixel units in the display panel to complete the external compensation of the row of pixel units.
  • FIG. 1 is a schematic block diagram of a shift register unit provided by some embodiments of the present disclosure
  • FIG. 2A is a schematic block diagram of another shift register unit provided by some embodiments of the present disclosure
  • FIG. 2B is a schematic block diagram of another shift register unit provided by some embodiments of the present disclosure.
  • the shift register unit 10 may include a first input circuit 100, a second input circuit 200, an output circuit 300, and a compensation circuit 400.
  • a gate driving circuit By cascading a plurality of the shift register units 10, a gate driving circuit can be obtained.
  • the gate driving circuit is used to drive the display panel and sequentially provide scanning signals for the plurality of gate lines of the display panel to display one frame on the display panel.
  • the period of the screen is progressive or interlaced.
  • the first input circuit 100 is connected to the first node Q, and is configured to write the first input signal to the first node Q in response to the first control signal (for example, the first node Q here is Pull up the node).
  • the first input circuit 100 is connected to the first input signal terminal DP, the first control signal terminal STU2, and the first node Q. Under the control of the first control signal provided by the first control signal terminal STU2, When the first input circuit 100 is turned on, the first input signal terminal DP is connected to the first node Q, so that the first input signal provided by the first input signal terminal DP is written to the first node Q, thereby controlling the first node Q.
  • the level of the node Q for example, pulls up the potential of the first node Q to the working potential.
  • the second input circuit 200 is connected to the first node Q and the second node H, is configured to input the second input signal to the second node H in response to the detection control signal, and to input the second node H in response to the second control signal
  • the level of H is transmitted to the first node Q.
  • the second input circuit 200 is connected to the second input signal terminal BP, the second control signal terminal STU1, and the detection control signal terminal OE, and is configured to be connected to the detection control signal provided by the detection control signal terminal OE.
  • the second input circuit 200 may use the second input signal to charge the second node H in the display period of the Nth frame, and in the blanking period of the Nth frame, the power of the second node H may be charged according to the second control signal. Ping is transmitted to the first node Q.
  • the second input circuit 200 may also use the second input signal to charge the second node H during the blanking period of the Nth frame, and the second control signal to charge the second node H during the blanking period of the N+1th frame
  • the level of H is transmitted to the first node Q.
  • the embodiment of the present disclosure does not limit this.
  • the output circuit 300 is connected to the first node Q and the output terminal OP, and is configured to output the composite output signal to the output terminal OP under the control of the level of the first node Q.
  • the output circuit 300 may also be connected to the first output clock signal terminal CLKD.
  • the first output clock signal terminal CLKD Under the control of the level of the first node Q, when the output circuit 300 is turned on, the first output clock signal terminal CLKD
  • the provided first output clock signal is respectively output to the output terminal OP through different transistors as the first output signal and the second output signal.
  • the composite output signal includes a first output signal and a second output signal, and the first output signal and the second output signal are the same.
  • the second output signal can be used to drive pixel units in the display panel for display or to achieve external compensation.
  • the first output signal can be used for scanning shift of the upper and lower shift register units.
  • the compensation circuit 400 is connected to the second node H and is configured to compensate the level of the second node H.
  • the compensation circuit 400 may compensate for the level of the second node H during the blanking period of the Nth frame to compensate for the influence of factors such as threshold voltage loss on the level of the second node H, thereby improving the H level control.
  • the compensation circuit 400 includes a first compensation sub-circuit 401, a second compensation sub-circuit 402, and a storage sub-circuit 403.
  • the first compensation sub-circuit 401 is respectively connected to the second node H and the third node N, and is configured to write the first clock signal to the third node N under the control of the level of the second node H;
  • the storage sub-circuit 403 is respectively connected to the second node H and the third node N, and is configured to compensate the level of the second node H based on the first clock signal written to the third node N;
  • the second compensation sub-circuit 402 is connected to
  • the third node N is configured to perform noise reduction on the third node N under the control of the compensation noise reduction signal CM.
  • the second compensation sub-circuit 402 is also connected to the fourth node QB to receive the voltage of the fourth node QB as the compensation noise reduction signal CM.
  • the second compensation sub-circuit 402 can reduce the noise of the third node N. Therefore, there is no need to separately provide a signal line for the second compensation sub-circuit 402 for providing the compensation noise reduction signal CM, which saves the number of signal lines.
  • the second compensation sub-circuit 402 may also be connected to a separately provided compensation noise reduction signal terminal, and the compensation noise reduction signal terminal is configured to output the compensation noise reduction signal CM.
  • the present disclosure does not specifically limit this.
  • the first compensation sub-circuit 401 is also connected to the first clock signal terminal CLKA. Under the control of the level of the second node H, when the first compensation sub-circuit 401 is turned on, the first clock signal The first clock signal provided by the terminal CLKA can be written into the third node N.
  • the second compensation sub-circuit 402 is also connected to the first voltage terminal VGL1. Under the control of the compensation noise reduction signal CM (that is, the level of the fourth node QB), when the second compensation sub-circuit 402 is turned on, the first voltage terminal The first voltage provided by VGL1 can be written into the third node N to achieve noise reduction on the third node N.
  • the shift register unit does not include the compensation circuit 400
  • the transistor since the transistor has a threshold voltage loss, when the second input signal is input to the second node H through the second input circuit 200, there is a threshold voltage loss problem, resulting in the first
  • the signal of the second node H is not equal to the second input signal; then, when the level of the second node H is written to the first node Q, there is still a problem of threshold voltage loss, that is, after two threshold voltage losses, finally
  • the second input signal is transmitted to the first node Q, resulting in a large difference between the level of the first node Q and the second input signal, and the high level written to the first node Q will be lower than the predetermined value, thereby affecting the output The composite output signal output by the terminal OP.
  • the shift register unit 10 provided by the embodiment of the present disclosure includes a compensation circuit 400, and the compensation circuit 400 can compensate the level of the second node H in a blanking period of one frame, thereby solving the threshold voltage at the second node H
  • the problem of loss is that the signal at the second node H is greater than or equal to the second input signal. Therefore, after the second input circuit 200 writes the level of the second node H into the first node Q, the signal at the first node Q The level can reach a predetermined value, which solves the problem that the high level at the first node Q will be lower than the predetermined value due to the threshold voltage loss. Therefore, it can prevent the threshold voltage loss of the transistor from affecting the quality of the output signal and enhance the circuit Reliability.
  • the first input circuit 100 (implemented as a display scanning sub-circuit), the output circuit 300 (implemented as a connecting sub-circuit), and the second input circuit 200 (implemented as a In order to integrate the detection sub-circuit)
  • the gate drive circuit obtained by cascading a plurality of the shift register units 10 is used to drive the display panel
  • the blanking output signal and the display period of the blanking period of one frame of picture can be used
  • the display output signal is output through the same output circuit, thereby simplifying the circuit structure of the shift register unit and the resulting gate drive circuit, and reducing the size of the shift register unit and the gate drive circuit including the shift register unit.
  • the output circuit 300 can also be connected to the second output clock signal terminal CLKE. Under the control of the level of the first node Q, when the output circuit 300 is turned on, the second output The second output clock signal provided by the clock signal terminal CLKE is output to the output terminal OP as a third output signal.
  • the composite output signal also includes a third output signal.
  • the second output signal and the third output signal may be two independent waveforms with different widths and timings.
  • the first input circuit 100 is configured to pull up the potential of the first node Q to the working potential during the display phase of one frame
  • the second input circuit 200 is configured to increase the potential of the first node Q during the blanking phase of one frame.
  • the potential is pulled up to the working potential.
  • the output circuit 300 outputs the second output signal and the third output signal via the output terminal OP under the control of the level of the first node Q, so as to drive the corresponding pixel unit through the gate line connected thereto.
  • the output circuit 300 outputs the second output signal and/or the third output signal through the output terminal OP under the control of the level of the first node Q to drive
  • the sensing transistor in the pixel unit is used for compensation detection.
  • the second input circuit 200 may include a charging sub-circuit 210 and an isolating sub-circuit 220.
  • the charging sub-circuit 210 is configured to input the second input signal to the second node H in response to the detection control signal.
  • the charging sub-circuit 210 is connected to the second node H, the detection control signal terminal OE, and the second input signal terminal BP.
  • the second input signal terminal BP Under the control of the detection control signal provided by the detection control signal terminal OE, when the charging sub-circuit 210 When turned on, the second input signal terminal BP is connected to the second node H, so that the second input signal is written into the second node H.
  • the second input signal may be at a high level to charge the second node H.
  • the detection control signal may be a random signal.
  • the detection control signal terminal OE is connected to an external control circuit, and the external control circuit may provide a detection control signal to the detection control signal terminal OE, and the detection control signal is a random signal.
  • the external control circuit may be implemented by, for example, a Field Programmable Gate Array (FPGA) or other signal generation circuit, thereby outputting a suitable type of random signal as the detection control signal.
  • the external control circuit may be configured to output a random signal to the detection control signal terminal OE during the display period of one frame.
  • the external control circuit can be connected to the shift signal output terminals of all stages of shift register units. According to actual needs, the external control circuit can randomly select a shift register unit for one frame of display period. The signal at the signal output terminal is transmitted to the detection control signal terminal OE in all shift register units.
  • the output terminal OP may include a shift signal output terminal.
  • the second input signal terminal BP of the i+2 stage shift register unit may be connected to the shift signal output terminal of the i-th stage shift register unit Therefore, the signal output from the shift signal output terminal of the i-th stage shift register unit can be used as the second input signal of the i+2 stage shift register unit.
  • the external control circuit is used to transmit the signal output from the shift signal output terminal of the shift register unit of the i stage
  • the detection control signal terminal OE to the shift register unit of all stages that is, the detection control signal of the shift register unit of all stages can be the same as the waveform pulse width and timing of the signal output from the shift signal output terminal of the i-th stage shift register unit
  • the waveforms of the output signals do not overlap, under the control of the detection control signal terminal OE, only the charging sub-circuit 210 in the shift register unit of the i+2 stage can transmit the high-level second input signal to the second node H, so that the second node H is charged to a high level.
  • the high-level signal of the second node H of the i+2th stage shift register unit can be transmitted to the first node Q, so that the i+2th stage shift register
  • the output circuit 300 of the unit may output a blanking output signal for driving the sensing transistor in the pixel unit of the i+2th row. i is a positive integer.
  • the shift register unit provided by some embodiments of the present disclosure may also implement sequential compensation row by row.
  • the second input signal terminal BP of the shift register unit of this stage can be connected to the shift signal output terminal CR of the shift register unit of this stage, and all stages of shift register units
  • the detection control signal terminal OE receives the signal from the shift signal output terminal CR of the first stage shift register unit during the display period of the first frame, and the detection control signal terminal OE of all stages of shift register units displays the display in the second frame During the period, the signal from the shift signal output terminal CR of the second-stage shift register unit is received, and so on, so that during the display period of the first frame, the second node H of the first-stage shift register unit can be charged to high During the display period of the second frame, the second node H of the second-stage shift register unit can be charged to a high level, so that the display panel can achieve sequential compensation line by line.
  • the isolation sub-circuit 220 is respectively connected to the first node Q and the second node H, and is configured to transmit the level of the second node H to the first node Q under the control of the second control signal.
  • the isolation sub-circuit 220 is provided between the first node Q and the second node H to prevent the first node Q and the second node H from interacting with each other.
  • the isolation sub-circuit 220 may disconnect the electrical connection between the first node Q and the second node H.
  • the isolation sub-circuit 220 is connected to the first node Q, the second node H, and the second control signal terminal STU1, and is configured to conduct under the control of the second control signal provided by the second control signal terminal STU1. Connect the first node Q and the second node H to transmit the level of the second node H to the first node Q.
  • the isolating sub-circuit 220 is turned on under the control of the second control signal, the level of the second node H is high, thereby pulling the potential of the first node Q up to the working potential.
  • the first clock signal and the second control signal are the same, and the first clock signal terminal CLKA is equivalent to the aforementioned second control signal terminal STU1, that is, the second control signal terminal STU1 and the first clock signal terminal CLKA It is the same signal terminal.
  • the isolating sub-circuit 220 and the first compensation sub-circuit 401 are connected to the same signal terminal, such as the first clock signal terminal CLKA, so that the isolating sub-circuit 220 can be controlled by the first clock signal provided by the first clock signal terminal CLKA.
  • the level of the second node H is transmitted to the first node Q; at the same time, the first compensation sub-circuit 401 can write the first clock signal to the third node N.
  • the second input circuit 200 may include any applicable sub-circuits, and is not limited to the charging sub-circuit 210 and the isolating sub-circuit 220, as long as the corresponding functions can be realized.
  • other circuit structures of the shift register unit 10 shown in FIG. 2A and FIG. 2B are basically the same as the shift register unit 10 shown in FIG.
  • FIG. 3A is a schematic block diagram of a shift register unit provided by other embodiments of the present disclosure
  • FIG. 3B is a schematic block diagram of another shift register unit provided by other embodiments of the present disclosure
  • FIG. 3C is another schematic block diagram of a shift register unit provided by other embodiments of the present disclosure The embodiment provides a schematic block diagram of another shift register unit
  • FIG. 3D is a schematic block diagram of still another shift register unit provided in other embodiments of the present disclosure.
  • the shift register unit further includes a noise reduction circuit 500 (here, a pull-down circuit) and a first control circuit 600.
  • the noise reduction circuit 500 is connected to the first node Q, the fourth node QB (here the fourth node QB is a pull-down node) and the output terminal OP, and is configured to control the level of the fourth node QB while simultaneously A node Q and output terminal OP perform noise reduction.
  • the noise reduction circuit 500 is connected to the first node Q, the fourth node QB, the output terminal OP, and the first voltage terminal VGL1. Under the control of the level of the fourth node QB, when the noise reduction circuit 500 is turned on, the first node Q and the output terminal OP are both connected to the first voltage terminal VGL1, thereby connecting the first node Q and the output terminal OP through the first voltage terminal VGL1. The output terminal OP is pulled down to a non-operating potential to achieve noise reduction.
  • the first voltage terminal VGL1 may be configured to provide a DC low-level signal, for example, the following embodiments are the same as this, and will not be repeated.
  • the first control circuit 600 is configured to control the level of the fourth node QB under the control of the level of the first node Q.
  • the first control circuit 600 is connected to both the first node Q and the fourth node QB, and is configured to pull down the level of the fourth node QB to a low level when the first node Q is at a high level. When Q is low, the fourth node QB is pulled up to high.
  • the first control circuit 600 may be an inverter circuit.
  • the shift register unit 10 further includes a second control circuit 610.
  • the second control circuit 610 is configured to control the level of the fourth node QB in response to the third control signal.
  • the second control circuit 610 is connected to the fourth node QB, the third control signal terminal Con1 and the first voltage terminal VGL1.
  • the fourth node QB is connected to the first voltage terminal VGL1 through The first voltage terminal VGL1 pulls down the level of the fourth node QB to the non-operating potential, thereby ensuring that the fourth node QB is at a low level during the blanking period, reducing the influence of the fourth node QB on the first node Q, The high level of the first node Q reaches the predetermined value, so that the threshold voltage of the transistor can be prevented from affecting the output signal after drifting, and the reliability of the circuit can be enhanced.
  • the third control signal includes the first clock signal, that is, in this example, the first clock signal terminal CLKA for providing the first clock signal is equivalent to the aforementioned third control signal terminal Con1, namely The third control signal terminal Con1 and the first clock signal terminal CLKA are the same signal terminal.
  • the third control signal includes the first clock signal and the voltage value of the second node H, so that the second control circuit 610 is also connected to the second node H. Therefore, in the blanking period of one frame, under the control of the voltage of the second node H and the first clock signal, the second control circuit 610 is turned on to pull down the fourth node QB to ensure that the fourth node QB is at low power. level.
  • the shift register unit 10 further includes a third control circuit 620.
  • the third control circuit 620 is configured to control the level of the fourth node QB in response to the fourth control signal.
  • the third control circuit 620 is connected to the fourth control signal terminal Con2, the fourth node QB and the first voltage terminal VGL1.
  • the fourth node QB is connected to the first voltage terminal VGL1 through the first voltage
  • the terminal VGL1 pulls down the level of the fourth node QB to the non-operating potential, thereby reducing the influence of the fourth node QB on the first node Q during the display period, so that the high level of the first node Q reaches a predetermined value, Prevent the threshold voltage of the transistor from affecting the output signal after drifting, and enhance the reliability of the circuit.
  • the shift register unit 10 may also include a second control circuit 610 and a third control circuit 620.
  • the fourth node QB is connected to the first voltage terminal VGL1 through the first The voltage terminal VGL1 pulls down the level of the fourth node QB to the non-operating potential.
  • the third control circuit 620 is configured to be turned on under the control of the fourth control signal provided by the fourth control signal terminal Con2, and the fourth node QB is connected to the first voltage terminal VGL1 through the first voltage terminal.
  • VGL1 pulls down the level of the fourth node QB to the non-operating potential.
  • the shift register unit 10 further includes a first reset circuit 700 (here, a display reset circuit) and a second reset circuit 800 (here, a blanking reset circuit).
  • a first reset circuit 700 here, a display reset circuit
  • a second reset circuit 800 here, a blanking reset circuit
  • the first reset circuit 700 is configured to reset the first node Q in response to the first reset control signal.
  • the first reset circuit 700 is connected to the first reset control signal terminal Re1, the first node Q, and the first voltage terminal VGL1.
  • the first reset control signal provided by the first reset control signal terminal Re1
  • the first reset circuit 700 is turned on, the first node Q is connected to the first voltage terminal VGL1, thereby using the first voltage terminal VGL1
  • a voltage resets the first node Q.
  • the output circuit 300 outputs signals (for example, the first output signal, the second output signal, and the third output signal)
  • the first voltage of the first voltage terminal VGL1 is used to generate the first node Q Reset.
  • the second reset circuit 800 is configured to reset the first node Q in response to the second reset control signal.
  • the second reset circuit 800 is connected to the second reset control signal terminal Re2, the first node Q, and the first voltage terminal VGL1.
  • the first node Q is connected to the first voltage terminal VGL1, thereby utilizing the first voltage terminal VGL1 A voltage resets the first node Q.
  • the first voltage at the first voltage terminal VGL1 is used to A node Q is reset; for another example, before the display period of one frame, the second reset circuit 800 can be turned on in response to the second reset control signal, so that the first voltage of the first voltage terminal VGL1 can be used to affect the first node Q Perform a reset.
  • signal output signals for example, the first output signal, the second output signal, and the third output signal
  • the first control circuit 600, the second control circuit 610, the third control circuit 620, the first reset circuit 700, and the second reset circuit 800 are all connected to the first
  • the power supply voltage VGL1 is used to receive a DC low-level signal, but is not limited to this.
  • the first control circuit 600, the second control circuit 610, the third control circuit 620, the first reset circuit 700, and the second reset circuit 800 may also be connected to Different power supply voltage terminals can receive different low-level signals, as long as the corresponding functions can be realized, which is not specifically limited in the present disclosure.
  • each transistor is an N-type transistor as an example, but this does not constitute a limitation to the embodiment of the present disclosure.
  • the first compensation sub-circuit 401 includes a first compensation transistor M15
  • the second compensation sub-circuit 402 includes a second compensation transistor M16
  • the storage sub-circuit 403 includes a first capacitor C1.
  • the first pole of the first compensation transistor M15 is connected to the first clock signal terminal CLKA to receive the first clock signal
  • the second pole of the first compensation transistor M15 is connected to To the third node N
  • the gate of the first compensation transistor M15 is connected to the second node H.
  • the first terminal of the first capacitor C1 is connected to the second node H
  • the second terminal of the first capacitor C1 is connected to the third node N.
  • the first pole of the second compensation transistor M16 is connected to the third node N
  • the second pole of the second compensation transistor M16 is connected to the first voltage terminal VGL1
  • the gate of the second compensation transistor M16 is configured to receive the compensation noise reduction signal CM .
  • the gate of the second compensation transistor M16 is connected to the fourth node QB to receive the voltage of the fourth node QB as the compensation noise reduction signal CM.
  • the second compensation transistor M16 is an N-type transistor, when the level of the fourth node QB is high, the second compensation transistor M16 is turned on to transfer the first voltage of the first voltage terminal VGL1 to the third Node N, thereby reducing noise on the third node N; when the level of the fourth node QB is low, the second compensation transistor M16 is turned off.
  • the first voltage terminal VGL1 is configured to provide a first voltage.
  • the first voltage may be a DC low-level signal.
  • the following embodiments are the same as this and will not be repeated. It should be noted that in other examples, when all the transistors in the shift register unit are P-type transistors, the first voltage may also be a DC high-level signal.
  • the charging sub-circuit 210 includes a first transistor M1
  • the isolation sub-circuit 220 includes a second transistor M2.
  • the gate of the first transistor M1 is configured to receive the detection control signal OE
  • the first pole of the first transistor M1 is configured to receive the second input signal
  • the second pole of the first transistor M1 is connected to the second node H.
  • the first electrode of the first transistor M1 is connected to the second input signal terminal BP
  • the second input signal terminal BP is used to provide the second input signal.
  • the gate of the second transistor M2 is configured to receive the second control signal
  • the first electrode of the second transistor M2 is connected to the second node H
  • the first electrode of the second transistor M2 is connected to the first node Q.
  • the gate of the second transistor M2 is connected to the first clock signal terminal CLKA to receive the first clock signal as the second control signal, that is, the first clock signal and the second control signal are the same.
  • the embodiments of the present disclosure are not limited thereto, and in another example, the first clock signal and the second control signal may also be different.
  • V H Vin2-Vth1
  • Vin2 the second input signal
  • Vth1 the threshold voltage of the first transistor M1.
  • the first compensation transistor M15 when the first compensation transistor M15 is turned on, the first clock signal provided by the first clock signal terminal CLKA is written into the third
  • the node N can compensate the voltage of the second node H based on the bootstrap effect of the first capacitor C1.
  • the voltage of node H V 'H Vin2 is greater than the second input signal, whereby, after the level of the second node the first node Q H is written, the level of the first node Q can reach the predetermined value .
  • the shift register unit 10 further includes a first control signal terminal STU2.
  • the first input circuit 100 includes a third transistor M3.
  • the gate of the third transistor M3 is connected to the first control signal terminal STU2 to receive the first control signal
  • the first electrode of the third transistor M3 is configured to receive the first input signal
  • the second electrode of the third transistor M3 is connected to the first Node Q is connected.
  • the first pole of the third transistor M3 is connected to the fourth voltage terminal VDD
  • the fourth voltage terminal VDD is equivalent to the aforementioned first input signal terminal DP
  • the fourth voltage provided by the fourth voltage terminal VDD serves as The first input signal.
  • the third transistor M3 is turned on to connect the fourth voltage terminal VDD with the first node Q, thereby connecting the fourth voltage Write the first node Q to pull up the potential of the first node Q to the working potential.
  • n 2 is an integer greater than zero.
  • the embodiment of the present disclosure is not limited to this, and the first control signal terminal STU2 may also be connected to a separately provided signal line.
  • the fourth voltage may be a DC high-level signal (for example, higher than or equal to the high-level portion of the clock signal), and the following embodiments are the same, and will not be repeated.
  • the output terminal OP includes a shift signal output terminal CR and a first scan signal output terminal OT1.
  • the output circuit 300 includes a first output transistor M18, a second output transistor M19, and a second capacitor C2.
  • the gate of the first output transistor M18 is connected to the first node Q
  • the first pole of the first output transistor M18 is connected to the first output clock signal terminal CLKD to receive the first output clock signal
  • the first output transistor M18 The two poles are connected to the shift signal output terminal CR.
  • the gate of the second output transistor M19 is connected to the first node Q
  • the first pole of the second output transistor M19 is connected to the first output clock signal terminal CLKD to receive the first output clock signal
  • the second output transistor M19 The two poles are connected to the first scan signal output terminal OT1; the first terminal of the second capacitor C2 is connected to the first node Q, and the second terminal of the second capacitor C2 is connected to the second electrode of the second output transistor M19.
  • the first output transistor M18 and the second output transistor M19 are both turned on, so that the first output clock signal is transmitted to the shifter via the first output transistor M18.
  • the signal output terminal CR serves as the first output signal, and the first output clock signal is transmitted to the first scan signal output terminal OT1 via the second output transistor M19 as the second output signal.
  • the composite output signal includes a first output signal and a second output signal, and the first output signal and the second output signal are the same.
  • the second output signal includes the aforementioned display output signal and blanking output signal, that is, during the display period, the signal output by the first scan signal output terminal OT1 is the display output signal; during the blanking period, the first scan signal output terminal OT1 outputs The signal is the blanking output signal.
  • the output terminal OP further includes a second scanning signal output terminal OT2
  • the output circuit 300 further includes a third output transistor M20 and a third capacitor C3.
  • the gate of the third output transistor M20 is connected to the first node Q
  • the first pole of the third output transistor M20 is connected to the second output clock signal terminal CLKE to receive the second output clock signal
  • the third output transistor M20 The two poles are connected to the second scanning signal output terminal OT2.
  • the first terminal of the third capacitor C3 is connected to the first node Q
  • the second terminal of the third capacitor C3 is connected to the second electrode of the third output transistor M20.
  • the composite output signal also includes a third output signal.
  • the clock signals provided by the first output clock signal terminal CLKD and the second output clock signal terminal CLKE are the same, therefore, the second output signal output by the first scan signal output terminal OT1 and the second scan signal output terminal
  • the third output signal output by OT2 is the same.
  • the first output clock signal terminal CLKD and the second output clock signal terminal CLKE provide different signals, so that the second output signal output by the first scan signal output terminal OT1 and the second scan signal output terminal
  • the third output signal output by the OT2 is different, so as to provide multiple driving signals for the pixel unit.
  • the low level of the first output clock signal may be the same as the low level of the first voltage output from the first voltage terminal VGL1.
  • the low level of the second output clock signal may also be the same as the low level of the first voltage output from the first voltage terminal VGL1.
  • the high level of the first output clock signal is the same as the high level of the second output clock signal.
  • the output circuit 300 further includes a fourth capacitor C4, the first end of the fourth capacitor C4 is connected to the first node Q, and the second end of the fourth capacitor C4 is connected to the first node Q.
  • the second pole of an output transistor M18 is connected.
  • the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 may be capacitive devices manufactured by a process, for example, by manufacturing special capacitor electrodes.
  • each electrode of the capacitor can be realized by a metal layer, a semiconductor layer (such as doped polysilicon), etc.
  • the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 can also be transistors
  • the parasitic capacitance between the transistors can be realized by the transistor itself and other devices and circuits.
  • the first capacitor C1 can maintain the level of the second node H, and can achieve a bootstrap function when the high level of the first clock signal is transmitted to the third node N.
  • the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 can all maintain the level of the first node Q.
  • the second capacitor C2 can achieve a bootstrap function.
  • the third capacitor C3 can achieve a bootstrap effect, and when the shift signal output terminal CR outputs a signal, the fourth capacitor C4 can achieve a bootstrap effect.
  • the noise reduction circuit 500 includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7.
  • the gate of the fourth transistor M4 is connected to the fourth node QB, the first electrode of the fourth transistor M4 is connected to the first node Q, and the second electrode of the fourth transistor M4 is connected to the first voltage terminal VGL1 to receive the first Voltage.
  • the gate of the fifth transistor M5 is connected to the fourth node QB, the first electrode of the fifth transistor M5 is connected to the shift signal output terminal CR, and the second electrode of the fifth transistor M5 is connected to the first voltage terminal VGL1 to receive First voltage.
  • the gate of the sixth transistor M6 is connected to the fourth node QB, the first electrode of the sixth transistor M6 is connected to the first scan signal output terminal OT1, and the second electrode of the sixth transistor M6 is connected to the second voltage terminal VGL2 to Receive the second voltage.
  • the gate of the seventh transistor M7 is connected to the fourth node QB, the first electrode of the seventh transistor M7 is connected to the second scan signal output terminal OT2, and the second electrode of the seventh transistor M7 is connected to the second voltage terminal VGL2 to Receive the second voltage.
  • the second voltage terminal VGL2 is configured to provide a second voltage
  • the second voltage is a DC low-level signal (for example, lower than or equal to the low level of the clock signal).
  • the second voltage terminal VGL2 may be grounded.
  • Each embodiment is the same as this, and will not be repeated here.
  • the second voltage provided by the second voltage terminal VGL2 is higher than the first voltage provided by the first voltage terminal VGL1, for example, the first voltage is -10V and the second voltage is -6V; in another example
  • the second voltage of the second voltage terminal VGL2 is equal to the first voltage of the first voltage terminal VGL1, so the shift register unit 10 may not be provided with the second voltage terminal VGL2, but connect the second electrode of the sixth transistor M6 to the The second poles of the seven transistors M7 are all connected to the first voltage terminal VGL1.
  • the first voltage and the second voltage can be the same or different, which can be determined according to actual requirements. The embodiment of the present disclosure does not limit this.
  • the noise reduction circuit 500 may not be provided with the seventh transistor M7.
  • the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are all turned on, and the first node Q and the shift The signal output terminals CR are both connected to the first voltage terminal VGL1, so that the potential of the first node Q and the potential of the shift signal output terminal CR are pulled down to a low potential through the first voltage terminal VGL1.
  • the first scan signal output terminal OT1 and the first The two scan signal output terminals OT2 are both connected to the second voltage terminal VGL2, so that the potentials of the first scan signal output terminal OT1 and the second scan signal output terminal OT2 are pulled down to a low level through the second voltage terminal VGL2, thereby reducing the first Noise of a node Q, shift signal output terminal CR, first scan signal output terminal OT1 and second scan signal output terminal OT2.
  • the noise reduction circuit 500 also includes multiple shift signal output terminals.
  • the bit signal output terminal and/or the plurality of first scan signal output terminals are connected in a one-to-one correspondence with a plurality of transistors to reduce noise of the plurality of shift signal output terminals and/or the plurality of first scan signal output terminals.
  • the first control circuit 600 includes an eighth transistor M8 and a ninth transistor M9.
  • the gate of the eighth transistor M8 is connected to the first electrode and configured to be connected to the third voltage terminal VDD_A to receive the third voltage, and the second electrode of the eighth transistor M8 is connected to the fourth node QB.
  • the gate of the ninth transistor M9 is connected to the first node Q, the first electrode of the ninth transistor M9 is connected to the fourth node QB, and the second electrode of the ninth transistor M9 is connected to the first voltage terminal VGL1 to receive the first voltage.
  • the first control circuit 600 further includes a seventeenth transistor M17.
  • the gate of the seventeenth transistor M17 is connected to the first pole and is configured to be connected to the fifth voltage terminal VDD_B to receive the fifth voltage, and the second pole of the seventeenth transistor M17 is connected to the fourth node QB.
  • the third voltage terminal VDD_A is configured to provide a DC low-level signal
  • the fifth voltage terminal VDD_B is configured to provide a DC high-level signal. Therefore, the eighth transistor M8 is always off, and the seventeenth transistor M17 is always on.
  • the third voltage terminal VDD_A and the fifth voltage terminal VDD_B are configured to alternately provide a DC high-level signal, so that the eighth transistor M8 and the seventeenth transistor M17 are turned on alternately to avoid long-term transistors. Performance drift caused by conduction.
  • the eighth transistor M8 when the third voltage terminal VDD_A provides a high-level signal and the fifth voltage terminal VDD_B provides a low-level signal, the eighth transistor M8 is turned on and the seventeenth transistor M17 is turned off; when the fifth voltage terminal VDD_B provides a high In the case of a level signal, the third voltage terminal VDD_A provides a low level signal. At this time, the seventeenth transistor M17 is turned on and the eighth transistor M8 is turned off.
  • the ninth transistor M9 when the first node Q is at an active level (for example, a high level), the ninth transistor M9 is turned on.
  • the channel width to length ratio of the ninth transistor M9 and the channel of the turned-on eighth transistor M8 The aspect ratio or the ratio of the channel aspect ratio of the turned-on seventeenth transistor M17, for example, the channel aspect ratio of the ninth transistor M9 is greater than the channel aspect ratio of the eighth transistor M8 and the seventeenth transistor Any one of the channel width to length ratios of M17, thereby, the potential of the fourth node QB can be pulled down to a low level.
  • the ninth transistor M9 is turned off.
  • the eighth transistor M8 If the eighth transistor M8 is turned on and the seventeenth transistor M17 is turned off, the third voltage (high) provided by the third voltage terminal VDD_A is transmitted through the eighth transistor M8. Level) is written to the fourth node QB to pull up the potential of the fourth node QB to a high level; if the eighth transistor M8 is turned off and the seventeenth transistor M17 is turned on, the fifth voltage is transferred through the seventeenth transistor M17 The fifth voltage (high level) raised by the terminal VDD_B is written into the fourth node QB to pull up the potential of the fourth node QB to a high level.
  • the first reset circuit 700 includes a tenth transistor M10.
  • the gate of the tenth transistor M10 is connected to the first reset control signal terminal Re1 to receive the first reset control signal
  • the first electrode of the tenth transistor M10 is connected to the first node Q
  • the second electrode of the tenth transistor M10 is connected to the first node Q.
  • the tenth transistor M10 is turned on, the first node Q is connected to the first voltage terminal VGL1, and the first voltage terminal The first voltage provided by VGL1 is written into the first node Q, so that the first node Q is reset.
  • n 2 is an integer greater than zero.
  • the embodiment of the present disclosure is not limited to this, and the first reset control signal terminal Re1 may also be connected to a separately provided signal line.
  • the second reset circuit 800 includes an eleventh transistor M11.
  • the gate of the eleventh transistor M11 is connected to the second reset control signal terminal Re2 to receive the second reset control signal, the first electrode of the eleventh transistor M11 is connected to the first node Q, and the second electrode of the eleventh transistor M11 Connected to the first voltage terminal VGL1 to receive the first voltage.
  • the eleventh transistor M11 is turned on, the first node Q is connected to the first voltage terminal VGL1, and the first The first voltage provided by the voltage terminal VGL1 is written into the first node Q, so that the first node Q is reset.
  • the second control circuit 610 includes a twelfth transistor M12 and a thirteenth transistor M13.
  • the third control signal includes the first clock signal and the voltage value of the second node H.
  • the gate of the twelfth transistor M12 is configured to be connected to the first clock signal terminal CLKA to receive the first clock signal
  • the first pole of the twelfth transistor M12 is configured to be connected to the fourth node QB
  • the twelfth transistor M12 The second electrode of the thirteenth transistor M13 is connected to the first electrode
  • the gate of the thirteenth transistor M13 is connected to the second node H
  • the second electrode of the thirteenth transistor M13 is connected to the first voltage terminal VGL1 to receive the One voltage.
  • the twelfth transistor M12 and the thirteenth transistor M13 are turned on,
  • the fourth node QB is connected to the first voltage terminal VGL1, and the first voltage provided by the first voltage terminal VGL1 is written into the fourth node QB, so that the fourth node QB is pulled down to a low level.
  • the second control circuit 610 may only include the twelfth transistor M12
  • the third control signal may only include the first clock signal
  • the gate of the twelfth transistor M12 is configured to be connected to the A clock signal terminal CLKA to receive the first clock signal
  • the first pole of the twelfth transistor M12 is configured to connect to the fourth node QB
  • the second pole of the twelfth transistor M12 is connected to the first voltage terminal VGL1 to receive the first Voltage.
  • the third control circuit 620 includes a fourteenth transistor M14.
  • the gate of the fourteenth transistor M14 is configured to be connected to the fourth control signal terminal Con2 to receive the fourth control signal
  • the first electrode of the fourteenth transistor M14 is connected to the fourth node QB
  • the second electrode of the fourteenth transistor M14 The pole is connected to the first voltage terminal VGL1 to receive the first voltage.
  • the fourteenth transistor M14 when the fourth control signal is at an effective level (for example, a high level), the fourteenth transistor M14 is turned on, the fourth node QB is connected to the first voltage terminal VGL1, and the first voltage The first voltage provided by the terminal VGL1 is written into the fourth node QB, so that the fourth node QB is pulled down to a low level.
  • an effective level for example, a high level
  • the shift signal output terminal CR of the m2-th stage shift register unit 10 and the fourth stage of the m2+3-th shift register unit 10 The control signal terminal Con2 is connected to use the output signal of the shift signal output terminal CR of the m2 stage shift register unit 10 as the fourth control signal of the m2+3 stage shift register unit 10.
  • m2 is an integer greater than zero.
  • the embodiment of the present disclosure is not limited to this, and the fourth control signal terminal Con2 may also be connected to a separately provided signal line.
  • the first input circuit 100, the second input circuit 200, the output circuit 300, the compensation circuit 400, the noise reduction circuit 500, and the first control circuit 600 The specific implementation manners of the second control circuit 610, the third control circuit 620, the first reset circuit 700, and the second reset circuit 800 are not limited to the above-described manners, and may be any applicable implementation manners, for example, in the field
  • the conventional connection method familiar to the technicians only needs to ensure that the corresponding function is realized.
  • the above examples do not limit the protection scope of the present disclosure. In practical applications, the skilled person can choose to use or not use one or more of the above-mentioned circuits according to the situation.
  • the shift register unit provided according to the embodiments of the present disclosure may have an anti-leakage function.
  • one or more transistors in the shift register unit 10 may be selected to add an anti-leakage circuit according to actual conditions. structure.
  • the first node Q, the second node H, the third node N, the fourth node QB, etc. do not represent actual components, but represent the junction of related connections in the circuit diagram. .
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • thin film transistors are used as examples for description.
  • the transistors in the embodiments of the present disclosure are all described by taking an N-type transistor as an example.
  • the first electrode of the transistor is the drain and the second electrode is the source.
  • the present disclosure includes but is not limited to this.
  • one or more transistors in the shift register unit 10 provided by the embodiments of the present disclosure may also be P-type transistors. In this case, the first electrode of the transistor is the source and the second electrode is the drain.
  • the poles of the selected type of transistor are connected correspondingly with reference to the poles of the corresponding transistors in the embodiments of the present disclosure, and the corresponding voltage terminals provide corresponding high or low voltages.
  • indium gallium zinc oxide Indium Gallium Zinc Oxide, IGZO
  • LTPS low temperature polysilicon
  • amorphous silicon such as hydrogenated non-crystalline silicon
  • FIG. 5 is a signal timing diagram of a shift register unit provided by some embodiments of the disclosure.
  • the working principle of the shift register unit 10 shown in FIG. 4B will be described below in conjunction with the signal timing diagram shown in FIG. 5, and the description will be given here by taking each transistor as an N-type transistor, but the embodiments of the present disclosure are not limited to this.
  • 1F and 2F indicate the timing of the first frame, the second frame, the third frame, and the fourth frame, respectively.
  • DS represents the display period of one frame
  • BL represents the blanking period of one frame.
  • STU1, STU2, Con1, Con2, VDD_A, VDD_B, CLKA, CLKD, CLKE, OT1, OT2, CR, etc. are used to represent the corresponding signal terminals as well as the corresponding signals. The following embodiments are the same and will not be repeated here.
  • the second reset signal Re2 is high, the eleventh transistor M11 is turned on, and the first voltage of the first voltage terminal VGL1 is passed through the eleventh transistor M11. Write to the first node Q to reset the first node Q.
  • the third voltage VDD_A is a low and high level signal, and the fifth voltage VDD_B is a high level signal.
  • the eighth transistor M8 is turned off, the seventeenth transistor M17 is turned on, and the fifth voltage VDD_B is written via the seventeenth transistor M17 Entering the fourth node QB, the potential of the fourth node QB is pulled up to a high level, so that the fourth transistor M4 is turned on, thereby assisting the pull-down of the first node Q, so that the potential of the first node Q is low. Since the level of the fourth node QB is high, the second compensation transistor M16 is also turned on, and thus the third node N is also reset.
  • the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are all turned on, so that the shift signal output terminal CR and the first scan signal output terminal are all turned on.
  • OT1 and the second scan signal output terminal OT2 perform noise reduction, so that the potentials of the shift signal output terminal CR, the first scan signal output terminal OT1 and the second scan signal output terminal OT2 are low.
  • the first control signal terminal STU2 is at a high level
  • the third transistor M3 is turned on
  • the first input signal (for example, the high level provided by the fourth voltage terminal VDD)
  • the fourth voltage is written into the first node Q through the third transistor M3, and is stored by the fourth capacitor C4.
  • the detection control signal OE is at a high level, so that the first transistor M1 is turned on, and the second input signal (for example, a high-level signal) is written into the second node H via the first transistor M1, and is stored by the first capacitor C1, At this time, the level of the second node H is high.
  • the first capacitor C1 can store the high-level second input signal and keep it until the end of the display period of one frame for use in the blanking period.
  • the first clock signal CLKA is a low-level signal, and the second transistor M2 is turned off.
  • the first output transistor M18, the second output transistor M19, and the third output transistor M20 are all turned on, and the first output clock signal CLKD is passed through the first output transistor M18 and the second output transistor M19. They are respectively output to the shift signal output terminal CR and the first scan signal output terminal OT1, and the second output clock signal CLKE is output to the second scan signal output terminal OT2 via the third output transistor M20.
  • the first output clock signal CLKD and the second output clock signal CLKE are both low-level signals, that is, the shift signal output terminal CR, the first scan signal output terminal OT1 and the second scan signal output terminal OT2 all output low level signal.
  • the ninth transistor M9 is turned on, thereby pulling down the potential of the fourth node QB to a low level.
  • the first node Q is maintained at a high level
  • the first output transistor M18, the second output transistor M19, and the third output transistor M20 are kept on, and the first An output clock signal CLKD and a second output clock signal CLKE both become high level, so the shift signal output terminal CR, the first scan signal output terminal OT1 and the second scan signal output terminal OT2 all output high level signals, Due to the bootstrap effect of the second capacitor C2, the third capacitor C3, and the fourth capacitor C4, the potential of the first node Q is further pulled up, and the first output transistor M18, the second output transistor M19, and the third output transistor M20 are more adequate Conduction.
  • the high-level signal output by the shift signal output terminal CR can be used for the scan shift of the upper and lower stage shift register units, and the high-level signal output from the first scan signal output terminal OT1 and the second scan signal output terminal OT2 It can be used to drive the pixel unit in the display panel for display.
  • the shift signal output terminal CR and the first scan signal output terminal OT1 both can be discharged through the first output clock signal terminal CLKD to complete the resetting of the shift signal output terminal CR and the first scan signal output terminal OT1; the second scan signal output terminal OT2 is discharged through the second output clock signal terminal CLKE to complete the reset Reset of the second scan signal output terminal OT2.
  • the shift signal output terminal CR, the first scan signal output terminal OT1, and the second scan signal output terminal OT2 all output low-level signals, due to the bootstrap of the second capacitor C2, the third capacitor C3, and the fourth capacitor C4.
  • the potential of the first node Q is reduced but still maintains a high level
  • the first output transistor M18, the second output transistor M19, and the third output transistor M20 still remain conductive
  • the first output clock signal terminal CLKD has a low voltage
  • the level is output to the shift signal output terminal CR and the first scan signal output terminal OT1
  • the low level of the second output clock signal terminal CLKE is output to the second scan signal output terminal OT2, thereby realizing the reset of the output terminal OP.
  • the first reset signal Re1 (not shown in the figure) is a high-level signal, and the tenth transistor M10 is turned on, so that the voltage of the first voltage terminal VGL1
  • the first voltage is written to the first node Q to reset the first node Q.
  • the level of the first node Q becomes a low level, so that the ninth transistor M9 is turned off, the third voltage VDD_A is a high-level signal, and the fifth voltage VDD_B is a low-level signal.
  • the eighth transistor M8 is turned off, and the The seventeenth transistor M17 is turned on, so that the fifth voltage VDD_B is written into the fourth node QB via the seventeenth transistor M17, and the fourth node QB is pulled up to a high level, so that the fourth transistor M4 is turned on to further One node Q performs noise reduction.
  • the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are also turned on under the control of the high level of the first node QB, so that the shift signal output terminal CR, the first scan signal output terminal OT1 and the second scan The signal output terminal OT2 performs noise reduction.
  • the second compensation transistor M16 is turned off.
  • the fourth stage 4 because the fourth node QB is pulled up to a high level, the second compensation transistor M16 is turned on, thereby reducing the noise of the third node N, and making the level of the third node N low. level.
  • the second transistor M2 is in the off state, thereby isolating the second node H and the first node Q to avoid the
  • the level of the second node H affects the output signal during the display period.
  • the level of the first node Q presents a tower-shaped waveform
  • the pull-up and reset of the output signal of the shift signal output terminal CR are realized through the first output transistor M18
  • the output of the first scan signal output terminal OT1 Both the pull-up and reset of the signal are realized by the second output transistor M19.
  • the pull-up and reset of the output signal of the second scan signal output terminal OT2 are both realized by the third output transistor M20.
  • the fifth transistor M5 is connected to the shift signal output terminal CR.
  • the output signal of the sixth transistor M6 plays an auxiliary pull-down role for the output signal of the first scan signal output terminal OT1
  • the seventh transistor M7 plays an auxiliary pull-down role for the output signal of the second scan signal output terminal OT2. Therefore, the volume of the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 can be reduced, which is beneficial to reducing the area of the circuit layout.
  • the second node H is still maintained at a high level, and the first compensation transistor M15 is turned on .
  • the first clock signal CLKA is a high-level signal, and the first clock signal CLKA can charge the third node N so that the level of the third node N becomes high. Due to the bootstrap effect of the first capacitor C1, The potential of the second node H is further pulled up, thereby realizing the compensation operation for the second node H. At this time, the first compensation transistor M15 is more fully turned on, so that the level of the third node N can reach the high level of the first clock signal CLKA.
  • the second transistor M2 since the first clock signal CLKA is a high-level signal, the second transistor M2 is turned on, and the level of the second node H is transmitted to the first node Q to pull the first node Q up to a high potential.
  • the ninth transistor M9 is turned on under the control of the first node Q, and the fourth node QB is pulled down to a low level. Since the level of the first node Q is high, the first output transistor M18, the second output transistor M19, and the third output transistor M20 are all turned on, and the first output clock signal CLKD passes through the first output transistor M18 and the second output transistor.
  • the transistor M19 is respectively output to the shift signal output terminal CR and the first scan signal output terminal OT1, and the second output clock signal CLKE is output to the second scan signal output terminal OT2 via the third output transistor M20.
  • the first output clock signal CLKD and the second output clock signal CLKE are both low-level signals, that is, the shift signal output terminal CR, the first scan signal output terminal OT1 and the second scan signal output terminal OT2 all output low level signal.
  • the first clock signal CLKA becomes a low level and the second transistor M2 is turned off, so that the first node Q does not leak through the second transistor M2.
  • the first node Q remains at a high level, the first output transistor M18, the second output transistor M19, and the third output transistor M20 remain on, and the first output clock signal CLKD becomes high level, thereby shifting the signal output terminal CR and the first scanning signal output terminal OT1 both output high-level signals.
  • the signal output from the first scan signal output terminal OT1 can be used to drive the sensing transistor in the pixel unit of the display panel to achieve external compensation. Since the second output clock signal CLKE outputs a pulse signal, the second scan signal output terminal OT2 also outputs a pulse signal. It should be noted that in the sixth stage 6, the signal output by the second scan signal output terminal OT2 can be designed according to actual applications, which is not limited in the present disclosure.
  • the first clock signal CLKA becomes low, so that the level of the third node N becomes low. Due to the bootstrap effect of the first capacitor C1, the potential of the second node H is Reduced but still maintains the high level.
  • the shift signal output terminal CR and the first scan signal output terminal OT1 Both can be discharged through the first output clock signal terminal CLKD to complete the reset of the shift signal output terminal CR and the first scan signal output terminal OT1; the second scan signal output terminal OT2 is discharged through the second output clock signal terminal CLKE to complete the reset Reset of the second scan signal output terminal OT2.
  • the shift signal output terminal CR, the first scan signal output terminal OT1, and the second scan signal output terminal OT2 all output low-level signals, due to the bootstrap of the second capacitor C2, the third capacitor C3, and the fourth capacitor C4.
  • the potential of the first node Q is reduced but still maintains a high level, the first output transistor M18, the second output transistor M19, and the third output transistor M20 still remain conductive, and the first output clock signal terminal CLKD has a low voltage
  • the level is output to the shift signal output terminal CR and the first scan signal output terminal OT1
  • the low level of the second output clock signal terminal CLKE is output to the second scan signal output terminal OT2, thereby realizing the reset of the output terminal OP.
  • the second reset signal Re2 is at a high level
  • the eleventh transistor M11 is turned on
  • the first voltage of the first voltage terminal VGL1 passes through the eleventh transistor M11. Is written to the first node Q to reset the first node Q.
  • the detection control signal OE is at a high level
  • the first transistor M1 is also turned on.
  • the second input signal BP is a low level signal
  • the second input signal BP is written into the second node H via the first transistor M1.
  • This second node H is also reset. In this way, the second node H can be kept at a high level for a short time, so as to reduce the risk of threshold voltage drift (for example, positive drift) of the transistor connected to the second node H, and help improve the reliability of the circuit.
  • threshold voltage drift for example, positive drift
  • the shift register unit includes two scanning signal output terminals (ie, the first scanning signal output terminal OT1 and the second scanning signal output terminal).
  • the terminal OT2) is taken as an example, but not limited to this.
  • the shift register unit may only include one scanning signal output terminal (for example, the first scanning signal output terminal OT1).
  • the working process of the shift register unit is similar to the above-mentioned working process, as long as the related description about the second scan signal output terminal OT2 is omitted, it will not be here. Repeat it again.
  • pulse-up means to charge a node or an electrode of a transistor, so that the node or the electrode The absolute value of the level rises to achieve the operation of the corresponding transistor (such as turning on); “pull-down” means to discharge a node or an electrode of a transistor to make the absolute value of the level of the node or the electrode Lowering, so as to achieve the operation of the corresponding transistor (for example, cut off).
  • working potential means that the node is at a high potential, so that when the gate of a transistor is connected to the node, the transistor is turned on; the term “non-working potential” means that the node is at a low potential, so that when the gate of a transistor is When connected to this node, the transistor is off.
  • pulse-up means discharging a node or an electrode of a transistor, so that the absolute value of the level of the node or the electrode is reduced, thereby realizing the corresponding transistor Operation (for example, turn on);
  • pulse down means to charge a node or an electrode of a transistor, so that the absolute value of the level of the node or the electrode is increased, thereby realizing the operation of the corresponding transistor (for example, turning off) .
  • operating potential means that the node is at a low potential, so that when the gate of a transistor is connected to the node, the transistor is turned on; the term “non-operating potential” means that the node is at a high potential, so that when the gate of a transistor is When connected to this node, the transistor is off.
  • FIG. 6 is a schematic block diagram of a gate driving circuit provided by some embodiments of the disclosure.
  • the gate driving circuit 20 includes a plurality of shift register units (for example, A1, A2, A3, A4, etc.). Multiple shift register units are arranged in cascade. The number of multiple shift register units is not limited and can be determined according to actual needs.
  • the shift register unit adopts the shift register unit 10 described in any embodiment of the present disclosure.
  • the gate drive circuit has a simple circuit structure and can compensate for the threshold voltage loss of the level written to the first node during the blanking period, thereby preventing the threshold voltage loss of the transistor from affecting the output signal and enhancing the reliability of the circuit.
  • the shift register unit can realize random compensation, avoid the brightness deviation of the scan line and the panel caused by the line-by-line sequential compensation, improve the display uniformity, and improve the display effect.
  • the gate driving circuit 20 can be directly integrated on the array substrate of the display device using the same manufacturing process as the thin film transistor to realize the progressive scan driving function.
  • the first scan signal output terminals OT1 of these shift register units are respectively connected to a plurality of first gate lines (for example, G11, G21, G31, G41, etc.) in a one-to-one correspondence;
  • the second scan signal output terminals of these shift register units OT2 is connected to a plurality of second gate lines (for example, G12, G22, G32, G42, etc.) in a one-to-one correspondence.
  • each shift register unit includes a first control signal terminal STU2, a first clock signal terminal CLKA (the first clock signal terminal CLKA is also the second control signal terminal STU1), a detection control signal terminal OE, and a first output clock signal terminal.
  • the gate driving circuit 20 further includes a first clock signal line CLK_1, a second clock signal line CLK_2, a third clock signal line CLK_3, and a fourth clock signal line CLK_4.
  • the connection modes of the shift register units at various levels and the above-mentioned clock signal lines are as follows and so on.
  • the 4n 1 -3th stage shift register unit of the plurality of shift register units (for example, the first stage shift register unit The first output clock signal terminal CLKD of A1) is connected to the first clock signal line CLK_1; the 4n 1 -2th stage shift register unit of the multiple shift register units (for example, the second stage shift register unit A2) An output clock signal terminal CLKD is connected to the second clock signal line CLK_2; the first output clock signal of the 4n 1 -1th stage shift register unit (for example, the third stage shift register unit A3) of the multiple shift register units CLKD end of the third clock signal line connected CLK_3; a plurality of first-stage shift register unit shift register unit 4n 1 (e.g., the fourth-stage shift register unit A4) of the first clock signal output terminal and the fourth clock CLKD
  • the signal line CLK_4 is connected; n 1 is an integer greater than zero.
  • the gate driving circuit 20 further includes a fifth clock signal line CLK_5, a sixth clock signal line CLK_6, a seventh clock signal line CLK_7, and an eighth clock signal line CLK_8.
  • the connection modes of the shift register units at various levels and the above-mentioned clock signal lines are as follows and so on.
  • the shift register unit includes the second output clock signal terminal
  • the second output clock of the 4n 1 -3th stage shift register unit (for example, the first stage shift register unit A1)
  • the signal terminal CLKE is connected to the fifth clock signal line CLK_5
  • the second output clock signal terminal CLKE of the 4n 1 -2th stage shift register unit (for example, the second stage shift register unit A2) is connected to the sixth clock signal line CLK_6
  • the second output clock signal terminal CLKE of the 4n 1 -1 stage shift register unit (for example, the third stage shift register unit A3) is connected to the seventh clock signal line CLK_7
  • the 4n 1 stage shift register unit (for example, ,
  • the second output clock signal terminal CLKE of the fourth stage shift register unit A4) is connected to the eighth clock signal line CLK_8.
  • the gate driving circuit 20 further includes a ninth clock signal line CLK_9 and a tenth clock signal line CLK_10.
  • the ninth clock signal line CLK_9 is configured to be connected to the shift register units of each stage (for example, the first stage shift register unit A1, the second stage shift register unit A2, the third stage shift register unit A3, and the fourth stage shift register unit A3).
  • the first clock signal terminal CLKA (that is, the second control signal terminal STU1) of the bit register unit A4) is connected.
  • the tenth clock signal line CLK_10 is configured to be connected to the shift register units of each stage (for example, the first stage shift register unit A1, the second stage shift register unit A2, the third stage shift register unit A3, and the fourth stage shift register unit A3).
  • the second reset control signal terminal Re2 of the bit register unit A4) is connected.
  • the shift register unit includes a shift signal output terminal and a first control signal terminal STU2
  • the first control signal terminal of the first stage shift register unit A1 STU2 and the fourth control signal terminal Con2 the first control signal terminal STU2 and the fourth control signal terminal Con2 of the second-stage shift register unit A2
  • the first control signal terminal STU2 and the first control signal terminal of the third-stage shift register unit A3 The four control signal terminals Con2 are all connected to the control signal line STU, for example, to receive the trigger signal STV.
  • the n 2 +3th stage shift register units of the plurality of shift register units (for example, the a first control signal terminal and a fourth control signal terminal STU2 Con2 four shift register unit A4) is connected to a plurality of shift register unit second-stage shift register unit n 2 (e.g., the first-stage shift register unit A1)
  • the shift signal output terminal CR, n 2 is an integer greater than 0.
  • the second input signal terminal BP of the first-stage shift register unit A1 and the second input signal terminal BP of the second-stage shift register unit A2 are both connected to the input signal line .
  • the n 2 +2-th shift register unit of the multiple shift register units shift signal output terminal connected to a second input signal terminal BP n-stage shift register unit (e.g., the first-stage shift register unit A1) of the shift signal output terminal CR, i.e., the n-stage shift register unit 2
  • the signal output by CR is used as the second input signal BP of the n 2 +2 stage shift register unit.
  • the shift register unit in the case where the control signal comprises a first reset terminal of Re1, shown in Figure 6, in some embodiments, except the last-stage shift register unit second-stage shift register unit n 2 (
  • the first reset control signal terminal Re1 of the first stage shift register unit A1) is connected to the shift signal output terminal CR of the n 2 +3th stage shift register unit (for example, the fourth stage shift register unit A4) .
  • the gate driving circuit 20 only includes four shift register units, the first reset control signal terminal Re1 of the second stage shift register unit A2 and the first reset control signal of the third stage shift register unit A3
  • the terminal Re1 and the first reset control signal terminal Re1 of the fourth-stage shift register unit A4 may be respectively connected to separately set reset signal lines.
  • the gate driving circuit 20 may further include a timing controller T-CON.
  • the timing controller T-CON is, for example, configured to provide the aforementioned clock signals to the shift register units at various levels, and the timing controller T-CON may also be configured to Provide trigger signal and reset signal. It should be noted that the phase relationship between the multiple clock signals provided by the timing controller T-CON can be determined according to actual requirements. In different examples, more clock signals can be provided according to different configurations.
  • the gate driving circuit 20 further includes multiple voltage lines to provide multiple voltage signals to the shift register units of each stage.
  • the gate driving circuit 20 when used to drive the display panel, the gate driving circuit 20 can be arranged on one side of the display panel.
  • the gate driving circuit 20 can also be arranged on both sides of the display panel to realize bilateral driving.
  • the embodiment of the present disclosure does not limit the arrangement of the gate driving circuit 20.
  • the gate driving circuit 20 may be provided on one side of the display panel for driving odd-numbered gate lines, and the gate driving circuit 20 may be provided on the other side of the display panel for driving even-numbered gate lines.
  • FIG. 7 is a signal timing diagram of a gate driving circuit provided by some embodiments of the present disclosure.
  • the signal timing diagram is the timing of the gate driving circuit 20 shown in FIG. 6, and the shift in the gate driving circuit 20 is
  • the register unit is the shift register unit 10 shown in FIG. 4B.
  • Q ⁇ 7> and Q ⁇ 8> respectively represent the first node Q in the seventh and eighth stages of the shift register unit in the gate drive circuit 20; H ⁇ 7> represents the gate The second node H in the seventh-stage shift register unit in the pole drive circuit 20; N ⁇ 7> represents the third node N in the seventh-stage shift register unit in the gate drive circuit 20.
  • OT1 ⁇ 7> and OT2 ⁇ 7> respectively represent the first scan signal output terminal OT1 and the second scan signal output terminal OT2 in the seventh stage shift register unit in the gate drive circuit 20, OT1 ⁇ 8> and OT2 ⁇ 8 > Respectively indicate the first scan signal output terminal OT1 and the second scan signal output terminal OT2 in the eighth stage shift register unit in the gate driving circuit 20.
  • MF represents the Mth frame, and M is a positive integer.
  • DS represents the display period in one frame, and BL represents the blanking period in one frame.
  • BL represents the blanking period in one frame.
  • the shift register unit 10 outputs scan driving signals to multiple rows of gate lines row by row, until the scan driving signals are output to the last row of gate lines to complete one frame of display.
  • the pixel unit of the nth row needs to be detected and compensated, and the pixel unit of the nth row is connected to the output terminal of the nth stage shift register unit 10, so that in the blanking period BL, the nth stage shift register
  • the first scanning signal output terminal OT1 of the unit 10 outputs a high-level signal to detect the pixel unit in the nth row.
  • the external control circuit outputs the signal output by the shift signal output terminal CR of the fifth stage shift register unit to the detection control signal terminal OE of each stage shift register unit, that is, the detection control signal and the fifth stage
  • the waveform pulse width of the signal output by the shift signal output terminal CR of the shift register unit is the same.
  • the second input signal terminal BP of the n 2 +2 stage shift register unit is connected to the shift signal output terminal CR of the n 2 stage shift register unit.
  • the seventh stage shift register unit is charged
  • the first transistor M1 in the electronic circuit 210 is turned on, as a result, the shift signal output terminal CR of the fifth stage shift register unit outputs a high level signal which is written into the second node H of the seventh stage shift register unit, In order to pull up the second node H of the fifth stage shift register unit to a high level.
  • the waveforms of the first clock signal CLK_1, the second clock signal CLK_2, the third clock signal CLK_3, and the fourth clock signal CLK_4 in the display period of one frame overlap in sequence by 50% of the effective pulse width.
  • the output signals OT1 ⁇ 1>, OT1 ⁇ 2>, OT1 ⁇ 3> and OT1 ⁇ 4> of the first scan signal output terminals OT1 of the first to fourth stage shift register units A1-A4 The waveforms sequentially overlap 50% of the effective pulse width.
  • the waveforms of the fifth clock signal line CLK_5, the sixth clock signal line CLK_6, the seventh clock signal line CLK_7, and the eighth clock signal line CLK_8 in the display period of one frame also overlap by 50% of the effective pulse width.
  • the waveforms of the output signals OT2 ⁇ 1>, OT2 ⁇ 2>, OT2 ⁇ 3> and OT2 ⁇ 4> of the second scanning signal output terminals OT2 of the four-stage shift register units A1-A4 are also sequentially Overlap 50% of the effective pulse width.
  • the gate driving circuit 20 overlaps the output signal waveforms in the display period, so it can realize the pre-charging function, improve the charging efficiency, and shorten the overall charging time of the pixel circuit (that is, the display period in one frame).
  • the pixels in the odd rows and the pixels in the even rows on the display panel can be connected to different data lines, so that when two adjacent rows of pixel units are charged at the same time, the adjacent two rows of pixel units can respectively receive the corresponding Data signal.
  • the gate driving circuit 20 is not limited to the cascade connection mode described in FIG. 9, and may be any applicable cascade connection mode.
  • the output signals OT1 ⁇ 1>, OT1 ⁇ 2>, OT1 ⁇ 3> and OT1 of the first scan signal output terminals OT1 of the first to fourth stage shift register units A1-A4 ⁇ 4> The overlapped portion of the waveform in the display period will also change accordingly.
  • the output signals OT2 ⁇ 1>, OT2 ⁇ 2>, OT2 ⁇ 2>, OT2 of the second scan signal output terminals OT2 of the first to fourth stage shift register units A1-A4 The overlapped portion of the waveforms of OT2 ⁇ 3> and OT2 ⁇ 4> during the display period will also change accordingly, for example, overlap 33% or 0% (that is, no overlap) to meet various application requirements.
  • the waveform of the signal output by the first scan signal output terminal OT1 of the seventh-stage shift register unit and the waveform of the signal output by the first scan signal output terminal OT1 of the eighth-stage shift register unit There is overlap. Therefore, in the first stage 1, in the process of charging the second node H of the seventh-stage shift register unit, the first transistor M1 in the charging sub-circuit 210 of the eighth-stage shift register unit When the shift signal output terminal CR of the sixth stage shift register unit outputs a high level signal, the shift signal output terminal CR of the sixth stage shift register unit outputs a high level signal and is written into the eighth stage. The second node H of the shift register unit of the eighth stage is pulled up to the high level. When the detection control signal OE is at a low level, the potentials of the second node H of the seventh-stage shift register unit and the second node H of the eighth-stage shift register unit may be able to be maintained until the blanking period BL.
  • the first clock signal CLKA is a high level signal
  • the second node H of the seventh stage shift register unit and the eighth stage shift The second node H of the bit register unit is high, and the first compensation transistor M15 in the seventh-stage shift register unit and the eighth-stage shift register unit is turned on, so that the seventh-stage shift register unit can be The level of the second node H of the second node H and the second node H of the eighth stage shift register unit is compensated.
  • the first clock signal CLKA is a high-level signal, so that the second transistor M2 of the shift register unit of all stages is turned on, because the second node of the seventh stage shift register unit H and the second node H of the eighth-stage shift register unit are both high (at this time, the level of the second node H has been compensated), thus, the first node Q of the seventh-stage shift register unit And the first node Q of the eighth stage shift register unit is charged to a high level.
  • the third clock signal CLK_3 (used to provide the first output clock signal CLKD) connected to the seventh-stage shift register unit provides a high-level signal, which is consistent with the seventh-stage shift
  • the seventh clock signal line CLK_7 (used to provide the second output clock signal CLKE) connected to the register unit provides a pulse signal, whereby the first scan signal output terminal OT1 of the seventh-stage shift register unit outputs a high-level signal.
  • the second scanning signal output terminal OT2 of the seven-stage shift register unit outputs a pulse signal. Therefore, in the M-th frame period, detection of pixel units in the seventh row can be achieved.
  • the fourth clock signal line CLK_4 (used to provide the first output clock signal CLKD) connected to the eighth stage shift register unit provides a low-level signal
  • the eighth clock signal line CLK_8 connected to the eighth stage shift register unit (For providing the second output clock signal CLKE) also provides a low-level signal, so the first scanning signal output terminal OT1 and the second scanning signal output terminal OT2 of the eighth stage shift register unit both output low-level signals. Therefore, in the M-th frame period, the eighth row of pixel units (which correspond to the eighth-stage shift register unit) will not be detected.
  • the detection control signal of each stage of the shift register unit can be based on
  • the second input signal input to the W-th stage shift register unit changes to ensure that when the first transistor M1 of the W-th stage shift register unit is turned on, the second input signal transmitted to the W-th stage shift register unit is High level signal, W is a positive integer.
  • the related description of other stages in the display period DS and the blanking period BL can refer to the detailed description of the other stages in the display period DS and the blanking period BL in the above-mentioned shift register unit, and the repetition will not be repeated here.
  • FIG. 8 is a schematic block diagram of a display device provided by some embodiments of the present disclosure.
  • the display device 30 includes a gate driving circuit 20, which is the gate driving circuit according to any embodiment of the disclosure.
  • the display device 30 may be any product or component with a display function, such as a liquid crystal panel, a liquid crystal TV, a display, an OLED panel, an OLED TV, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, etc.
  • a display function such as a liquid crystal panel, a liquid crystal TV, a display, an OLED panel, an OLED TV, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, etc.
  • the embodiment of the present disclosure does not limit this.
  • the display device 30 includes a display panel 3000, a gate driving circuit 20, a timing controller 3020, and a data driving circuit 3030.
  • the display panel 3000 includes a plurality of pixel units P, which are defined by a plurality of gate lines GL and a plurality of data lines DL.
  • the gate drive circuit 20 is used to drive multiple gate lines GL;
  • the data drive circuit 3030 is used to drive multiple data lines DL;
  • the timing controller 3020 is used to process image data RGB input from the outside of the display device 30, and then send it to the data drive circuit 3030 provides processed image data RGB.
  • the timing controller 3020 is also used to output the scan control signal GCS and the data control signal DCS to the gate drive circuit 20 and the data drive circuit 3030, respectively, for the purpose of comparing the gate drive circuit 20 and the data
  • the drive circuit 3030 performs control.
  • the first scan signal output terminals OT1 of the plurality of shift register units 10 in the gate driving circuit 20 are correspondingly connected to the plurality of gate lines GL.
  • the first scan signal output terminal OT1 of each level of shift register unit 10 in the gate drive circuit 20 sequentially outputs scan drive signals to the multiple gate lines GL, so that the multiple rows of pixel units P in the display panel 3000 are in the display period
  • the first scan signal output terminal OT1 of a shift register unit selected at random among the plurality of shift register units 10 outputs a scan driving signal to the corresponding gate line GL to achieve random compensation Detection.
  • the gate driving circuit 20 may be implemented as a semiconductor chip, or integrated in the display panel 3000 to form a GOA circuit.
  • the data driving circuit 3030 provides converted data signals to a plurality of data lines DL.
  • the data driving circuit 3030 may be implemented as a semiconductor chip.
  • the timing controller 3020 processes externally input image data RGB to match the size and resolution of the display panel 3000, and then provides the processed image data to the data driving circuit 3030.
  • the timing controller 3020 uses synchronization signals (such as dot clock DCLK, data enable signal DE, horizontal synchronization signal Hsync, and vertical synchronization signal Vsync) input from the outside of the display device 30 to generate a plurality of scan control signals GCS and a plurality of data control signals DCS .
  • synchronization signals such as dot clock DCLK, data enable signal DE, horizontal synchronization signal Hsync, and vertical synchronization signal Vsync
  • the display device 30 may also include other components, such as a signal decoding circuit, a voltage conversion circuit, etc. These components may, for example, use existing conventional components, which will not be described in detail here.
  • At least one embodiment of the present disclosure also provides a method for driving the shift register unit, which can be used to drive the shift register unit provided in any embodiment of the present disclosure.
  • FIG. 9 is a flowchart of a driving method of a shift register unit provided by some embodiments of the present disclosure.
  • the driving method may include a display period and a blanking period for one frame.
  • the display period includes a first input stage and a first output stage
  • the blanking period includes a second input stage and a second output stage
  • the driving method may include the following operations:
  • the compensation circuit compensates for the level of the second node, and the second input circuit responds to the second control signal to transmit the level of the second node to the first node;
  • the output circuit In the second output stage, the output circuit outputs the composite output signal to the output terminal under the control of the level of the first node.
  • step S10 further includes: controlling the level of the fourth node through the third control circuit in response to the fourth control signal, so as to The level of the fourth node is pulled down to the non-operating potential.
  • the output terminal includes a shift signal output terminal and a first scan signal output terminal
  • the output circuit includes a first output transistor and a second output transistor.
  • Step S11 may include: under the control of the level of the first node, transmitting the display shift signal to the shift signal output terminal via the first output transistor, and transmitting the display output signal to the first scan signal output via the second output transistor end.
  • the composite output signal includes a display output signal and a display shift signal.
  • the display output signal and the display shift signal are the same, and both are the first output clock signal.
  • the display output signal can be used to drive pixel units in the display panel for display.
  • step S20 may include: under the control of the level of the second node, writing a high-level first clock signal to the third node; based on the high-level write to the third node The first clock signal compensates the level of the second node; then, in response to the second control signal, the compensated level of the second node is transmitted to the first node.
  • step S20 further includes: controlling the level of the fourth node in response to the third control signal, so as to control the level of the fourth node The level is pulled down to the non-operating potential.
  • step S21 may include: under the control of the level of the first node, transmitting the blanking shift signal to the shift signal output terminal via the first output transistor, and blanking via the second output transistor.
  • the output signal is transmitted to the first scanning signal output terminal.
  • the composite output signal includes a blanking output signal and a blanking shift signal.
  • the blanking output signal and the blanking shift signal are the same and both are the first output clock signal.
  • the blanking output signal can be used to drive pixel units in the display panel for external compensation.
  • the first output signal may include a display shift signal and a blanking shift signal
  • the second output signal includes a display output signal and a blanking output signal.
  • the display output signal may be the signal output by the first scanning signal output terminal during the display period
  • the display shift signal may be the signal output by the shift signal output terminal during the display period
  • the display shift signal and the display output signal may be the same.
  • the output signal may be, for example, a pulse signal; the blanking output signal may be a signal output by the first scanning signal output terminal during the blanking period, and the blanking shift signal may be a signal output by the shift signal output terminal during the blanking period,
  • the blanking shift signal and the blanking output signal may also be the same, and the blanking output signal may be a high-level signal, for example.
  • the driving method may further include: a display reset phase, under the control of the first reset signal, reset the first node; under the control of the level of the fourth node, reduce The noise circuit reduces noise on the first node, the shift signal output terminal, the first scan signal output terminal and the second scan signal output terminal.
  • the driving method may further include: a blanking reset stage, in which the first node and the second node are reset under the control of the second reset signal and the detection control signal.

Abstract

一种移位寄存器单元(10)及其驱动方法、栅极驱动电路(20)、显示装置(30)，移位寄存器单元(10)包括：第一输入电路(100)、第二输入电路(200)、输出电路(300)和补偿电路(400)，第一输入电路(100)连接第一节点(Q)，被配置为响应于第一控制信号将第一输入信号写入至第一节点(Q)；第二输入电路(200)连接到第一节点(Q)和第二节点(H)，被配置为响应于检测控制信号将第二输入信号输入至第二节点(H)，且响应于第二控制信号将第二节点(H)的电平传输到第一节点(Q)；补偿电路(400)连接到第二节点(H)，被配置为对第二节点(H)的电平进行补偿；输出电路(300)连接第一节点(Q)和输出端(OP)，且被配置为在第一节点(Q)的电平的控制下，将复合输出信号输出至输出端(OP)。

Description

移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
本申请要求于2019年02月25日递交的中国专利申请第201910138433.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种移位寄存器单元及其驱动方法、栅极驱动电路、显示装置。
背景技术
在显示技术领域，显示面板例如液晶显示面板(Liquid crystal display,LCD)或有机发光二极管(Organic Light Emitting Diode,OLED)显示面板，包括多条栅线和多条数据线。对栅线的驱动可以通过栅极驱动电路实现。栅极驱动电路通常集成在栅极驱动芯片(Gate Integrated Circuit)中。随着显示技术的飞速发展，显示面板越来越向着高集成度和低成本的方向发展。在驱动芯片设计中，芯片的面积是影响芯片成本的主要因素，如何有效地减小芯片面积是技术开发人员需要着重考虑的问题。
发明内容
本公开一些实施例提供一种移位寄存器单元，包括：第一输入电路、第二输入电路、输出电路和补偿电路，所述第一输入电路连接第一节点，被配置为响应于第一控制信号将第一输入信号写入至所述第一节点；所述第二输入电路连接到所述第一节点和第二节点，被配置为响应于检测控制信号将第二输入信号输入至所述第二节点，且响应于第二控制信号将所述第二节点的电平传输到所述第一节点；所述补偿电路连接到所述第二节点，被配置为对所述第二节点的电平进行补偿；所述输出电路连接所述第一节点和输出端，且被配置为在所述第一节点的电平的控制下，将复合输出信号输出至所述输出端。
例如，在本公开一些实施例提供的移位寄存器单元中，所述补偿电路包括第一补偿子电路、第二补偿子电路和存储子电路，所述第一补偿子电路分别连接到所述第二节点和第三节点，且被配置为在所述第二节点的电平的控制下， 将第一时钟信号写入所述第三节点；所述存储子电路分别连接到所述第二节点和所述第三节点，且被配置为基于写入至所述第三节点的所述第一时钟信号对所述第二节点的电平进行补偿；所述第二补偿子电路连接到所述第三节点，且被配置为在补偿降噪信号的控制下，对所述第三节点进行降噪。
例如，在本公开一些实施例提供的移位寄存器单元中，所述第二补偿子电路还连接到第四节点，以接收所述第四节点的电压作为所述补偿降噪信号。
例如，在本公开一些实施例提供的移位寄存器单元中，所述第一补偿子电路包括第一补偿晶体管，所述第二补偿子电路包括第二补偿晶体管，所述存储子电路包括第一电容，所述第一补偿晶体管的第一极连接到第一时钟信号端以接收所述第一时钟信号，所述第一补偿晶体管的第二极连接到所述第三节点，所述第一补偿晶体管的栅极连接到所述第二节点，所述第一电容的第一端连接到所述第二节点，所述第一电容的第二端连接到所述第三节点，所述第二补偿晶体管的第一极连接到所述第三节点，所述第二补偿晶体管的第二极连接到第一电压端，所述第二补偿晶体管的栅极连接到所述第四节点。
例如，在本公开一些实施例提供的移位寄存器单元中，所述第一时钟信号和所述第二控制信号相同。
例如，在本公开一些实施例提供的移位寄存器单元中，所述第二输入电路包括充电子电路和隔离子电路，所述充电子电路被配置为响应于所述检测控制信号，将所述第二输入信号输入至所述第二节点；所述隔离子电路分别连接所述第一节点和所述第二节点，被配置为在所述第二控制信号的控制下，将所述第二节点的电平传输到所述第一节点。
例如，在本公开一些实施例提供的移位寄存器单元中，所述充电子电路包括第一晶体管，所述第一晶体管的栅极被配置为接收所述检测控制信号，所述第一晶体管的第一极被配置为接收所述第二输入信号，所述第一晶体管的第二极连接到所述第二节点；所述隔离子电路包括第二晶体管，所述第二晶体管的栅极配置为接收所述第二控制信号，所述第二晶体管的第一极连接至所述第二节点，所述第二晶体管的第一极连接至所述第一节点。
例如，在本公开一些实施例提供的移位寄存器单元中，所述第一输入电路包括第三晶体管，所述第三晶体管的栅极连接至第一控制信号端以接收所述第一控制信号，所述第三晶体管的第一极被配置为接收所述第一输入信号，所述第三晶体管的第二极与所述第一节点连接。
例如，在本公开一些实施例提供的移位寄存器单元中，所述输出端包括移位信号输出端和第一扫描信号输出端，所述输出电路包括第一输出晶体管、第二输出晶体管和第二电容；所述第一输出晶体管的栅极与所述第一节点连接，所述第一输出晶体管的第一极与第一输出时钟信号端连接以接收第一输出时钟信号，所述第一输出晶体管的第二极与所述移位信号输出端连接；所述第二输出晶体管的栅极和所述第一节点连接，所述第二输出晶体管的第一极与所述第一输出时钟信号端连接以接收所述第一输出时钟信号，所述第二输出晶体管的第二极与所述第一扫描信号输出端连接；所述第二电容的第一端和所述第一节点连接，所述第二电容的第二端与所述第二输出晶体管的第二极连接；所述第一输出时钟信号经由所述第一输出晶体管传输到所述移位信号输出端以作为第一输出信号，所述第一输出时钟信号经由所述第二输出晶体管传输到所述第一扫描信号输出端以作为第二输出信号，所述复合输出信号包括所述第一输出信号和所述第二输出信号。
例如，在本公开一些实施例提供的移位寄存器单元中，所述输出端还包括第二扫描信号输出端，所述输出电路还包括第三输出晶体管和第三电容，所述第三输出晶体管的栅极与所述第一节点连接，所述第三输出晶体管的第一极与第二输出时钟信号端连接以接收第二输出时钟信号，所述第三输出晶体管的第二极与所述第二扫描信号输出端连接，所述第三电容的第一端和所述第一节点连接，所述第三电容的第二端与所述第三输出晶体管的第二极连接，所述第二输出时钟信号经由所述第三输出晶体管传输到所述第二扫描信号输出端以作为第三输出信号，所述复合输出信号还包括所述第三输出信号。
例如，本公开一些实施例提供的移位寄存器单元还包括降噪电路和第一控制电路，所述降噪电路连接所述第一节点、第四节点和所述输出端，且被配置为在所述第四节点的电平的控制下，同时对所述第一节点和所述输出端进行降噪；所述第一控制电路连接所述第一节点和所述第四节点，且配置为在所述第一节点的电平的控制下，对所述第四节点的电平进行控制。
例如，本公开一些实施例提供的移位寄存器单元还包括第二控制电路，所述第二控制电路连接第四节点，且被配置为响应于第三控制信号对所述第四节点的电平进行控制，所述第三控制信号包括第一时钟信号和所述第二节点的电压值。
例如，本公开一些实施例提供的移位寄存器单元还包括第三控制电路，所 述第三控制电路连接第四节点，且被配置为响应于第四控制信号对所述第四节点的电平进行控制。
例如，本公开一些实施例提供的移位寄存器单元还包括：第一复位电路和第二复位电路，所述第一复位电路连接所述第一节点，且被配置为响应于第一复位控制信号对所述第一节点进行复位；所述第二复位电路连接所述第一节点，且被配置为响应于第二复位控制信号对所述第一节点进行复位。
例如，本公开一些实施例提供的移位寄存器单元还包括：降噪电路、第一控制电路、第二控制电路、第三控制电路、第一复位电路和第二复位电路，所述补偿电路包括第一补偿晶体管、第二补偿晶体管和第一电容，所述第一补偿晶体管的第一极连接到第一时钟信号端以接收第一时钟信号，所述第一补偿晶体管的第二极连接到第三节点，所述第一补偿晶体管的栅极连接到所述第二节点，所述第一电容的第一端连接到所述第二节点，所述第一电容的第二端连接到所述第三节点，所述第二补偿晶体管的第一极连接到所述第三节点，所述第二补偿晶体管的第二极连接到第一电压端，所述第二补偿晶体管的栅极连接到第四节点，以接收所述第四节点的电压作为补偿降噪信号；所述第二输入电路包括充电子电路和隔离子电路，所述充电子电路包括第一晶体管，所述第一晶体管的栅极被配置为接收所述检测控制信号，所述第一晶体管的第一极被配置为接收所述第二输入信号，所述第一晶体管的第二极连接到所述第二节点，所述隔离子电路包括第二晶体管，所述第二晶体管的栅极配置为接收所述第二控制信号，所述第二晶体管的第一极连接至所述第二节点，所述第二晶体管的第一极连接至所述第一节点；所述第一输入电路包括第三晶体管，所述第三晶体管的栅极被配置为接收所述第一控制信号，所述第三晶体管的第一极被配置为接收所述第一输入信号，所述第三晶体管的第二极与所述第一节点连接；所述输出电路包括第一输出晶体管、第二输出晶体管、第三输出晶体管、第二电容和第三电容，所述输出端包括移位信号输出端、第一扫描信号输出端和第二扫描信号输出端，所述第一输出晶体管的栅极与所述第一节点连接，所述第一输出晶体管的第一极与第一输出时钟信号端连接以接收第一输出时钟信号，所述第一输出晶体管的第二极与所述移位信号输出端连接，所述第二输出晶体管的栅极和所述第一节点连接，所述第二输出晶体管的第一极与所述第一输出时钟信号端连接以接收所述第一输出时钟信号，所述第二输出晶体管的第二极与所述第一扫描信号输出端连接，所述第二电容的第一端和所述第一节点连接，所 述第二电容的第二端与所述第一输出晶体管的第二极连接，所述第三输出晶体管的栅极与所述第一节点连接，所述第三输出晶体管的第一极与第二输出时钟信号端连接以接收第二输出时钟信号，所述第三输出晶体管的第二极与所述第二扫描信号输出端连接，所述第三电容的第一端和所述第一节点连接，所述第三电容的第二端与所述第三输出晶体管的第二极连接，所述第一输出时钟信号经由所述第一输出晶体管传输到所述移位信号输出端以作为第一输出信号，所述第一输出时钟信号经由所述第二输出晶体管传输到所述第一扫描信号输出端以作为第二输出信号，所述第二输出时钟信号经由所述第三输出晶体管传输到所述第二扫描信号输出端以作为第三输出信号，所述复合输出信号包括所述第一输出信号、所述第二输出信号和所述第三输出信号；所述降噪电路包括第四晶体管、第五晶体管、第六晶体管和第七晶体管，所述第四晶体管的栅极与所述第四节点连接，所述第四晶体管的第一极与所述第一节点连接，所述第四晶体管的第二极与所述第一电压端连接，所述第五晶体管的栅极与所述第四节点连接，所述第五晶体管的第一极与所述移位信号输出端连接，所述第五晶体管的第二极与所述第一电压端连接，所述第六晶体管的栅极与所述第四节点连接，所述第六晶体管的第一极与所述第一扫描信号输出端连接，所述第六晶体管的第二极与第二电压端连接，所述第七晶体管的栅极与所述第四节点连接，所述第七晶体管的第一极与所述第二扫描信号输出端连接，所述第七晶体管的第二极与所述第二电压端连接；所述第一控制电路包括第八晶体管和第九晶体管，所述第八晶体管的栅极和第一极连接且被配置为连接第三电压端，所述第八晶体管的第二极连接所述第四节点，所述第九晶体管的栅极连接所述第一节点，所述第九晶体管的第一极连接到所述第四节点，所述第九晶体管的第二极连接到所述第一电压端；所述第一复位电路包括第十晶体管，所述第十晶体管的栅极连接至第一复位控制信号端以接收第一复位控制信号，所述第十晶体管的第一极连接到所述第一节点，所述第十晶体管的第二极连接到所述第一电压端；所述第二复位电路包括第十一晶体管，所述第十一晶体管的栅极连接至第一复位控制信号端以接收第二复位控制信号，所述第十一晶体管的第一极连接到所述第一节点，所述第十一晶体管的第二极连接到所述第一电压端；所述第二控制电路包括第十二晶体管和第十三晶体管，所述第十二晶体管的栅极被配置为接收所述第一时钟信号，所述第十二晶体管的第一极被配置为连接所述第四节点，所述第十二晶体管的第二极连接到所述第十三晶体管的第一极，所述 第十三晶体管的栅极连接到所述第二节点，所述第十三晶体管的第二极连接到所述第一电压端；所述第三控制电路包括第十四晶体管，所述第十四晶体管的栅极被配置为接收第四控制信号，所述第十四晶体管的第一极连接至所述第四节点，所述第十四晶体管的第二极连接所述第一电压端。
本公开一些实施例还提供一种栅极驱动电路，包括多个移位寄存器单元，多个移位寄存器单元级联，且所述多个移位寄存器单元中的每个移位寄存器单元为如上述任一实施例所述的移位寄存器单元。
例如，本公开一些实施例提供的栅极驱动电路还包括第一时钟信号线、第二时钟信号线、第三时钟信号线和第四时钟信号线，在所述移位寄存器单元包括第一输出时钟信号端的情形下，所述多个移位寄存器单元中第4n 1-3级移位寄存器单元的第一输出时钟信号端与所述第一时钟信号线连接；所述多个移位寄存器单元中第4n 1-2级移位寄存器单元的第一输出时钟信号端与所述第二时钟信号线连接；所述多个移位寄存器单元中第4n 1-1级移位寄存器单元的第一输出时钟信号端与所述第三时钟信号线连接；所述多个移位寄存器单元中第4n 1级移位寄存器单元的第一输出时钟信号端与所述第四时钟信号线连接；n 1为大于0的整数。
例如，本公开一些实施例提供的栅极驱动电路还包括第五时钟信号线、第六时钟信号线、第七时钟信号线和第八时钟信号线，在所述移位寄存器单元包括第二输出时钟信号端的情形下，所述第4n 1-3级移位寄存器单元的第二输出时钟信号端与所述第五时钟信号线连接；所述第4n 1-2级移位寄存器单元的第二输出时钟信号端与所述第六时钟信号线连接；所述第4n 1-1级移位寄存器单元的第二输出时钟信号端与所述第七时钟信号线连接；所述第4n 1级移位寄存器单元的第二输出时钟信号端与所述第八时钟信号线连接。
例如，在本公开一些实施例提供的栅极驱动电路中，在所述移位寄存器单元包括移位信号输出端和第一控制信号端的情形下，所述多个移位寄存器单元中第n 2+3级移位寄存器单元的第一控制信号端和所述多个移位寄存器单元中第n 2级移位寄存器单元的移位信号输出端连接，n 2为大于0的整数。
例如，在本公开一些实施例提供的栅极驱动电路中，所述第n 2级移位寄存器单元的移位信号输出端输出的信号作为所述第n 2+2级移位寄存器单元的第二输入信号。
例如，在本公开一些实施例提供的栅极驱动电路中，在所述移位寄存器单 元还包括第一复位控制信号端的情形下，所述第n 2级移位寄存器单元的第一复位控制信号端和所述第n 2+3级移位寄存器单元的移位信号输出端连接。
本公开一些实施例还提供一种显示装置，包括上述任一实施例所述的栅极驱动电路。
本公开一些实施例还提供一种如上述任一实施例所述的移位寄存器单元的驱动方法，其中，一帧包括显示时段和消隐时段，所述显示时段包括第一输入阶段和第一输出阶段，所述消隐时段包括第二输入阶段和第二输出阶段，所述驱动方法包括：在所述第一输入阶段，响应于所述第一控制信号，所述第一输入电路将所述第一输入信号写入到所述第一节点；在所述第一输出阶段，在所述第一节点的电平的控制下，所述输出电路将所述复合输出信号输出至所述输出端；在所述第二输入阶段，所述补偿电路对所述第二节点的电平进行补偿，以及所述第二输入电路响应于所述第二控制信号，以将所述第二节点的电平传输到所述第一节点；在所述第二输出阶段，所述输出电路在所述第一节点的电平的控制下，将所述复合输出信号输出至所述输出端。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一些实施例提供的一种移位寄存器单元的示意框图；
图2A为本公开一些实施例提供的另一种移位寄存器单元的示意框图；
图2B为本公开一些实施例提供的又一种移位寄存器单元的示意框图；
图3A为本公开另一些实施例提供的一种移位寄存器单元的示意框图；
图3B为本公开另一些实施例提供的又一种移位寄存器单元的示意框图；
图3C为本公开另一些实施例提供的另一种移位寄存器单元的示意框图；
图3D为本公开另一些实施例提供的再一种移位寄存器单元的示意框图；
图4A为图3D中所示的移位寄存器单元的一种电路结构图；
图4B为图3D中所示的移位寄存器单元的另一种电路结构图；
图5为本公开一些实施例提供的一种移位寄存器单元的信号时序图；
图6为本公开一些实施例提供的一种栅极驱动电路的示意框图；
图7为本公开一些实施例提供的一种栅极驱动电路的信号时序图；
图8为本公开一些实施例提供的一种显示装置的示意框图；以及
图9为本公开一些实施例提供的一种移位寄存器单元的驱动方法的流程图。
具体实施方式
为了使得本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。
在OLED显示面板中，为了对像素电路中的驱动晶体管的阈值漂移、电源线的电压降、有机发光二极管的老化等造成的显示不均匀进行补偿，可以采用外部补偿方式。在外部补偿方式中，像素电路包括数据写入晶体管、驱动晶体管、存储电容、感测晶体管和感测线，通过该感测晶体管和感测线来感测驱动晶体管的阈值电压或像素电路中的电源电压降等，并基于感测线上的感测数据进行补偿。像素电路的工作周期也包括显示时段和感测时段(或消隐时段)。在进行外部补偿时，在一帧的显示时段(Display)，栅极驱动电路需要提供用于数据写入晶体管的显示输出信号，在一帧的消隐时段(Blank)，栅极驱动电路需要提供用于感测晶体管的消隐输出信号。
在OLED显示面板中，栅极驱动电路(Gate-driver on Array，GOA)的移 位寄存器单元包括检测子电路、显示扫描子电路和输出两者复合脉冲的连接子电路(或门电路或Hiz电路)，此时，移位寄存器单元可以输出具有不同宽度和时序的两个波形组成的复合波形的输出脉冲，从而为像素电路中的数据写入晶体管和感测晶体管分别提供显示输出信号和消隐输出信号。然而，该移位寄存器单元的结构非常复杂，且尺寸较大，不利于实现高分辨率和窄边框，也不利于减小芯片面积以降低成本。
目前，栅极驱动电路输出的消隐输出信号是逐行顺序扫描的，例如，在第一帧的消隐时段输出用于显示面板中第一行的像素单元的消隐输出信号，在第二帧的消隐时段输出用于显示面板中第二行的像素单元的消隐输出信号，依次类推，从而完成对显示面板的逐行顺序补偿。长时间的逐行顺序补偿会带来两个严重的问题：一个是在进行多帧的扫描显示过程中会有一条逐行移动的扫描线，另一个是由于补偿时间的差异造成显示面板上的不同区域亮度差异较大。
此外，栅极驱动电路的移位寄存器单元包括多个薄膜晶体管，由于薄膜晶体管输出的信号存在阈值损失，该移位寄存器单元输出的脉冲信号不准确，从而影响显示效果、降低显示质量。
本公开至少一些实施例提供一种移位寄存器单元及其驱动方法、栅极驱动电路、显示装置。该移位寄存器单元包括第一输入电路、第二输入电路、输出电路和补偿电路。第一输入电路连接第一节点，配置为响应于第一控制信号将第一输入信号写入至第一节点；第二输入电路连接到第一节点和第二节点，被配置为响应于检测控制信号将第二输入信号输入至第二节点，且响应于第二控制信号将第二节点的电平传输到第一节点；补偿电路连接到第二节点，配置为对第二节点的电平进行补偿；输出电路连接第一节点和输出端，且配置为在第一节点的电平的控制下，将复合输出信号输出至输出端。
该移位寄存器单元的电路结构简单，可以补偿在消隐时段写入第一节点的电平的阈值电压损失，从而防止由于晶体管的阈值电压损失而对输出信号造成影响，增强电路的信赖性。同时，该移位寄存器单元还可以实现随机补偿，避免由于逐行顺序补偿造成的扫描线和面板的亮度偏差，提高显示均匀性，提升显示效果。
需要说明的是，在本公开的实施例中，“随机补偿”指的是区别于逐行顺序补偿的一种外部补偿方法，在该补偿方法中，在某一帧的消隐时段可以随机输出对应于显示面板中任意一行的像素单元的消隐输出信号，以下各实施例与此 相同，不再赘述。
另外，在本公开的实施例中，“一帧”、“每帧”或“某一帧”包括依次进行的显示时段和消隐时段，例如，在显示时段中，栅极驱动电路输出多个显示输出信号，该多个显示输出信号可以驱动显示面板从第一行到最后一行完成完整的一幅图像的扫描显示，在消隐时段中，栅极驱动电路输出消隐输出信号，该消隐输出信号可以用于驱动显示面板中的某一行像素单元中的感测晶体管，以完成该行像素单元的外部补偿。
下面结合附图对本公开的一些实施例进行详细说明，但是本公开并不限于这些具体的实施例。
图1为本公开一些实施例提供的一种移位寄存器单元的示意框图，图2A为本公开一些实施例提供的另一种移位寄存器单元的示意框图，图2B为本公开一些实施例提供的又一种移位寄存器单元的示意框图。
例如，如图1所示，该移位寄存器单元10可以包括第一输入电路100、第二输入电路200、输出电路300和补偿电路400。通过级联多个该移位寄存器单元10可以得到栅极驱动电路，该栅极驱动电路用于驱动显示面板，为显示面板的多条栅线依序提供扫描信号，从而在显示面板显示一帧画面的期间进行逐行或隔行扫描等。
例如，如图1所示，第一输入电路100连接第一节点Q，且被配置为响应于第一控制信号将第一输入信号写入到第一节点Q(例如，这里第一节点Q为上拉节点)。例如，在一些示例中，第一输入电路100与第一输入信号端DP、第一控制信号端STU2和第一节点Q连接，在第一控制信号端STU2提供的第一控制信号的控制下，当第一输入电路100导通时，第一输入信号端DP和第一节点Q连接，从而使第一输入信号端DP提供的第一输入信号被写入到第一节点Q，从而控制第一节点Q的电平，例如将第一节点Q的电位上拉到工作电位。
例如，第二输入电路200连接到第一节点Q和第二节点H，被配置为响应于检测控制信号将第二输入信号输入至第二节点H，且响应于第二控制信号将第二节点H的电平传输到第一节点Q。例如，在一些示例中，第二输入电路200与第二输入信号端BP、第二控制信号端STU1和检测控制信号端OE连接，且被配置为在检测控制信号端OE提供的检测控制信号的控制下利用第二输入信号对第二节点H的电平进行控制，例如对第二节点H进行充电，然后 根据第二控制信号端STU1提供的第二控制信号将第二节点H的电平传输到第一节点Q，从而将第一节点Q的电位上拉到工作电位。
例如，第二输入电路200可以在第N帧的显示时段利用第二输入信号对第二节点H进行充电，并在第N帧的消隐时段，根据第二控制信号将第二节点H的电平传输到第一节点Q。又例如，第二输入电路200还可以在第N帧的消隐时段利用第二输入信号对第二节点H进行充电，并在第N+1帧的消隐时段第二控制信号将第二节点H的电平传输到第一节点Q。本公开的实施例对此不作限定。
例如，如图1所示，输出电路300连接第一节点Q和输出端OP，且被配置为在第一节点Q的电平的控制下，将复合输出信号输出至输出端OP。例如，在一些示例中，输出电路300还可以与第一输出时钟信号端CLKD连接，在第一节点Q的电平的控制下，当输出电路300导通时，使第一输出时钟信号端CLKD提供的第一输出时钟信号分别通过不同的晶体管输出至输出端OP以作为第一输出信号和第二输出信号。复合输出信号包括第一输出信号和第二输出信号，第一输出信号和第二输出信号相同。第二输出信号可以用于驱动显示面板中的像素单元进行显示或实现外部补偿。在多个移位寄存器单元10级联的情况下，第一输出信号可以用于上下级移位寄存器单元的扫描移位。
例如，如图1所示，补偿电路400连接到第二节点H，被配置为对第二节点H的电平进行补偿。例如，补偿电路400可以在第N帧的消隐时段，对第二节点H的电平进行补偿，以补偿阈值电压损失等因素对于第二节点H的电平的影响，从而提高对于第二节点H的电平控制。
例如，如图2A所示，在一些示例中，补偿电路400包括第一补偿子电路401、第二补偿子电路402和存储子电路403。第一补偿子电路401分别连接到第二节点H和第三节点N，且被配置为在第二节点H的电平的控制下，将第一时钟信号写入第三节点N；存储子电路403分别连接到第二节点H和第三节点N，且被配置为基于写入至第三节点N的第一时钟信号对第二节点H的电平进行补偿；第二补偿子电路402连接到第三节点N，且被配置为在补偿降噪信号CM的控制下，对第三节点N进行降噪。
例如，如图2B所示，在一些实施例中，第二补偿子电路402还连接到第四节点QB，以接收第四节点QB的电压作为补偿降噪信号CM。也就是说，在第四节点QB的电平的控制下，第二补偿子电路402可以对第三节点N进行降 噪。从而，不用为第二补偿子电路402单独设置一条信号线以用于提供补偿降噪信号CM，节省信号线数量。
需要说明的是，在另一些示例中，第二补偿子电路402也可以连接到单独设置的补偿降噪信号端，补偿降噪信号端被配置为输出补偿降噪信号CM。本公开对此不作具体限制。
例如，在一些示例中，第一补偿子电路401还连接到第一时钟信号端CLKA，在第二节点H的电平的控制下，当第一补偿子电路401导通时，第一时钟信号端CLKA提供的第一时钟信号可以被写入第三节点N。第二补偿子电路402还连接到第一电压端VGL1，在补偿降噪信号CM(即第四节点QB的电平)的控制下，当第二补偿子电路402导通时，第一电压端VGL1提供的第一电压可以被写入第三节点N以实现对第三节点N进行降噪。
在移位寄存器单元不包括补偿电路400的情形下，由于晶体管具有阈值电压损失，在通过第二输入电路200将第二输入信号输入至第二节点H时，存在阈值电压损失问题，从而导致第二节点H的信号与第二输入信号不相等；然后再将第二节点H的电平写入第一节点Q时，还存在阈值电压损失问题，也就是说，经过两次阈值电压损失，最终第二输入信号被传输至第一节点Q，从而导致第一节点Q的电平与第二输入信号相差较大，写入到第一节点Q的高电平会低于预定值，从而影响输出端OP输出的复合输出信号。本公开的实施例提供的移位寄存器单元10包括补偿电路400，补偿电路400可以在一帧的消隐时段中对第二节点H的电平进行补偿，从而解决第二节点H处的阈值电压损失的问题，使第二节点H处的信号大于或等于第二输入信号，由此，在第二输入电路200将第二节点H的电平写入第一节点Q后，第一节点Q的电平能够达到预定值，解决由于阈值电压损失而造成第一节点Q处的高电平会低于预定值的问题，因此可防止由于晶体管的阈值电压损失而影响输出信号的质量，增强电路的信赖性。
在本公开的一些实施例提供的移位寄存器单元10中，可以将第一输入电路100(实现为显示扫描子电路)、输出电路300(实现为连接子电路)和第二输入电路200(实现为检测子电路)进行整合，使用通过级联多个该移位寄存器单元10得到的栅极驱动电路来驱动显示面板时，则可以使一帧画面的消隐时段的消隐输出信号和显示时段的显示输出信号通过同一个输出电路输出，从而简化移位寄存器单元以及由此得到的栅极驱动电路的电路结构，减小移位寄 存器单元以及包括移位寄存器单元的栅极驱动电路的尺寸。
例如，如图2A和图2B所示，输出电路300还可以与第二输出时钟信号端CLKE连接，在第一节点Q的电平的控制下，当输出电路300导通时，使第二输出时钟信号端CLKE提供的第二输出时钟信号输出至输出端OP以作为第三输出信号。复合输出信号还包括第三输出信号。第二输出信号和第三输出信号可以是具有不同宽度和时序的相互独立的两个波形。
例如，第一输入电路100被配置为在一帧的显示阶段将第一节点Q的电位上拉到工作电位，第二输入电路200被配置为在一帧的消隐阶段将第一节点Q的电位上拉到工作电位。例如，在一帧的显示时段，输出电路300在第一节点Q的电平的控制下经由输出端OP输出第二输出信号和第三输出信号，以通过与之相连的栅线驱动对应像素单元中的扫描晶体管，从而进行显示；在一帧的消隐时段，输出电路300在第一节点Q的电平的控制下经由输出端OP输出第二输出信号和/或第三输出信号，以驱动像素单元中的感测晶体管，从而进行补偿检测。
例如，如图2A和图2B所示，第二输入电路200可以包括充电子电路210和隔离子电路220。
例如，充电子电路210被配置为响应于检测控制信号，将第二输入信号输入至第二节点H。例如，在一些示例中，充电子电路210连接第二节点H、检测控制信号端OE和第二输入信号端BP，在检测控制信号端OE提供的检测控制信号的控制下，当充电子电路210导通时，第二输入信号端BP和第二节点H连接，从而将第二输入信号写入第二节点H。例如，在一个示例中，在检测控制信号的控制下，当充电子电路210导通时，第二输入信号可以为高电平，以对第二节点H进行充电。
例如，检测控制信号可以为随机信号，在一些示例中，检测控制信号端OE与外部控制电路连接，外部控制电路可以向检测控制信号端OE提供检测控制信号，且检测控制信号为随机信号。外部控制电路例如可以为采用现场可编程门阵列(Field Programmable Gate Array，FPGA)或其他信号发生电路实现，由此输出适当类型的随机信号作为检测控制信号。例如，外部控制电路可以被配置为在一帧的显示时段将随机信号输出至检测控制信号端OE。例如，在一些示例中，外部控制电路可以与所有级移位寄存器单元的移位信号输出端连接，根据实际需要，外部控制电路可以在一帧的显示时段随机选择一个移位寄存器 单元的移位信号输出端的信号，并将该信号传输至所有移位寄存器单元中的检测控制信号端OE。
例如，输出端OP可以包括移位信号输出端，在一些示例中，第i+2级移位寄存器单元的第二输入信号端BP可以与第i级移位寄存器单元的移位信号输出端连接，从而第i级移位寄存器单元的移位信号输出端输出的信号可以作为第i+2级移位寄存器单元的第二输入信号。在进行随机检测时，在第N帧时，需要对显示面板中的第i+2行像素单元进行检测时。第i+2行像素单元与第i+2级移位寄存器单元对应，在第N帧的显示时段，外部控制电路用于将第i级移位寄存器单元的移位信号输出端输出的信号传输至所有级移位寄存器单元的检测控制信号端OE，即所有级移位寄存器单元的检测控制信号可以与第i级移位寄存器单元的移位信号输出端输出的信号的波形脉冲宽度和时序相同，当输出信号的波形不重叠时，在检测控制信号端OE控制下，只有第i+2级移位寄存器单元中的充电子电路210可以将高电平的第二输入信号传输至第二节点H，以使得第二节点H被充电至高电平。由此，在第N帧的消隐时段中，第i+2级移位寄存器单元的第二节点H的高电平信号可以被传输至第一节点Q，从而第i+2级移位寄存器单元的输出电路300可以输出用于驱动第i+2行像素单元中的感测晶体管的消隐输出信号。i为正整数。
例如，本公开的一些实施例提供的移位寄存器单元还可以实现逐行顺序补偿。在进行逐行顺序补偿时，在一些示例中，本级移位寄存器单元的第二输入信号端BP均可以与本级移位寄存器单元的移位信号输出端CR连接，所有级移位寄存器单元的检测控制信号端OE在第一帧的显示时段时接收第一级移位寄存器单元的移位信号输出端CR的信号，所有级移位寄存器单元的检测控制信号端OE在第二帧的显示时段时接收第二级移位寄存器单元的移位信号输出端CR的信号，依次类推，由此，在第一帧的显示时段，第一级移位寄存器单元的第二节点H可以被充电至高电平，在第二帧的显示时段，第二级移位寄存器单元的第二节点H可以被充电至高电平，从而显示面板可以实现逐行顺序补偿。
例如，隔离子电路220分别连接第一节点Q和第二节点H，被配置为在第二控制信号的控制下，将第二节点H的电平传输到第一节点Q。例如，隔离子电路220设置在第一节点Q和第二节点H之间，用于防止第一节点Q与第二节点H的相互影响。例如，在不需要将第二节点H的电平传输到第一节点Q 时，隔离子电路220可以断开第一节点Q与第二节点H之间的电连接。
例如，在一些示例中，隔离子电路220与第一节点Q、第二节点H和第二控制信号端STU1连接，被配置为在第二控制信号端STU1提供的第二控制信号的控制下导通，使第一节点Q和第二节点H连接，从而将第二节点H的电平传输到第一节点Q。例如，在一个示例中，当隔离子电路220在第二控制信号的控制下导通时，第二节点H的电平为高电平，从而将第一节点Q的电位上拉到工作电位。
例如，在一些实施例中，第一时钟信号和第二控制信号相同，第一时钟信号端CLKA等同于前述的第二控制信号端STU1，即第二控制信号端STU1和第一时钟信号端CLKA为同一个信号端。隔离子电路220和第一补偿子电路401连接至同一个信号端，例如第一时钟信号端CLKA，从而隔离子电路220可以在第一时钟信号端CLKA提供的第一时钟信号的控制下，将第二节点H的电平传输到第一节点Q；同时，第一补偿子电路401可以将第一时钟信号写入第三节点N。
需要说明的是，本公开的各实施例中，第二输入电路200可以包括任意适用的子电路，不局限于上述充电子电路210和隔离子电路220，只要能实现相应功能即可。此外，图2A和图2B所示的移位寄存器单元10的其他电路结构与图1中所示的移位寄存器单元10基本上相同，重复之处不再赘述。
图3A为本公开另一些实施例提供的一种移位寄存器单元的示意框图；图3B为本公开另一些实施例提供的又一种移位寄存器单元的示意框图；图3C为本公开另一些实施例提供的另一种移位寄存器单元的示意框图；图3D为本公开另一些实施例提供的再一种移位寄存器单元的示意框图。
例如，如图3A所示，移位寄存器单元还包括降噪电路500(这里为下拉电路)和第一控制电路600。
例如，降噪电路500连接第一节点Q、第四节点QB(这里第四节点QB为下拉节点)和输出端OP，且被配置为在第四节点QB的电平的控制下，同时对第一节点Q和输出端OP进行降噪。例如，在一些示例中，降噪电路500与第一节点Q、第四节点QB、输出端OP和第一电压端VGL1连接。在第四节点QB的电平的控制下，当降噪电路500导通时，第一节点Q和输出端OP均连接第一电压端VGL1，从而通过第一电压端VGL1将第一节点Q和输出端OP下拉至非工作电位，以实现降噪。
需要说明的是，在本公开的实施例中，第一电压端VGL1例如可以被配置为提供直流低电平信号，以下各实施例与此相同，不再赘述。
例如，第一控制电路600被配置为在第一节点Q的电平的控制下，对第四节点QB的电平进行控制。例如，第一控制电路600与第一节点Q和第四节点QB均连接，被配置为当第一节点Q为高电平时将第四节点QB的电平下拉至低电平，当第一节点Q为低电平时将第四节点QB上拉为高电平。例如，第一控制电路600可以为反相电路。
例如，如图3B所示，移位寄存器单元10还包括第二控制电路610。第二控制电路610被配置为响应于第三控制信号对第四节点QB的电平进行控制。例如，第二控制电路610连接第四节点QB、第三控制信号端Con1和第一电压端VGL1。例如，在一帧的消隐时段，在第三控制信号端Con1提供的第三控制信号的控制下，当第二控制电路610导通时，第四节点QB与第一电压端VGL1连接，通过第一电压端VGL1将第四节点QB的电平下拉至非工作电位，从而在消隐时段中，可以保证第四节点QB处于低电平，降低第四节点QB对第一节点Q的影响，使得第一节点Q的高电平达到预定值，因此可防止晶体管阈值电压漂移后影响输出信号，增强电路的信赖性。
例如，在一些实施例中，第三控制信号包括第一时钟信号，即在该示例中，用于提供第一时钟信号的第一时钟信号端CLKA等同于前述的第三控制信号端Con1，即第三控制信号端Con1和第一时钟信号端CLKA为同一个信号端。
例如，在另一些实施例中，第三控制信号包括第一时钟信号和第二节点H的电压值，从而第二控制电路610还连接至第二节点H。从而在一帧的消隐时段，在第二节点H的电压和第一时钟信号的控制下，第二控制电路610导通，以对第四节点QB进行下拉，确保第四节点QB处于低电平。
例如，如图3C所示，移位寄存器单元10还包括第三控制电路620。第三控制电路620被配置为响应于第四控制信号对第四节点QB的电平进行控制。例如，在一个示例中，第三控制电路620连接第四控制信号端Con2、第四节点QB和第一电压端VGL1。在一帧的显示时段，在第四控制信号端Con2提供的第四控制信号的控制下，当第三控制电路620导通时，第四节点QB与第一电压端VGL1连接，通过第一电压端VGL1将第四节点QB的电平下拉至非工作电位，由此，在显示时段中，降低第四节点QB对第一节点Q的影响，使得第一节点Q的高电平达到预定值，防止晶体管阈值电压漂移后影响输出信号，增 强电路的信赖性。
例如，如图3D所示，与图3B和图3C所示的示例不同，移位寄存器单元10也可以包括第二控制电路610和第三控制电路620。在一帧的消隐时段，在第三控制信号端Con1提供的第三控制信号的控制下，当第二控制电路610导通时，第四节点QB与第一电压端VGL1连接，通过第一电压端VGL1将第四节点QB的电平下拉至非工作电位。在一帧的显示时段，第三控制电路620被配置在第四控制信号端Con2提供的第四控制信号的控制下导通，第四节点QB与第一电压端VGL1连接，通过第一电压端VGL1将第四节点QB的电平下拉至非工作电位。由此，在图3D所示的示例中，在消隐时段和显示时段，均可以将第四节点QB的电平下拉至非工作电位，从而降低第四节点QB对第一节点Q的影响，使得第一节点Q的高电平达到预定值。
例如，如图3A-3D所示，移位寄存器单元10还包括第一复位电路700(这里为显示复位电路)和第二复位电路800(这里为消隐复位电路)。
例如，第一复位电路700被配置为响应于第一复位控制信号对第一节点Q进行复位。例如，如图3A-3D所示，第一复位电路700连接第一复位控制信号端Re1、第一节点Q和第一电压端VGL1。在第一复位控制信号端Re1提供的第一复位控制信号的控制下，当第一复位电路700导通时，第一节点Q与第一电压端VGL1连接，从而利用第一电压端VGL1的第一电压对第一节点Q复位。例如，在一帧的显示时段，当输出电路300输出信号(例如，第一输出信号、第二输出信号和第三输出信号)后，利用第一电压端VGL1的第一电压对第一节点Q复位。
例如，第二复位电路800被配置为响应于第二复位控制信号对第一节点Q进行复位。例如，如图3A-3D所示，第二复位电路800连接第二复位控制信号端Re2、第一节点Q和第一电压端VGL1。在第二复位控制信号端Re2提供的第二复位控制信号的控制下，当第二复位电路800导通时，第一节点Q与第一电压端VGL1连接，从而利用第一电压端VGL1的第一电压对第一节点Q复位。例如，在一帧的消隐时段，当输出电路300输出信号输出信号(例如，第一输出信号、第二输出信号和第三输出信号)后，利用第一电压端VGL1的第一电压对第一节点Q复位；又例如，在一帧的显示时段前，第二复位电路800可以响应于第二复位控制信号而导通，从而可以利用第一电压端VGL1的第一电压对第一节点Q进行复位。
值得注意的是，在图3A-3D所示的示例中，第一控制电路600、第二控制电路610、第三控制电路620、第一复位电路700和第二复位电路800均连接到第一电源电压VGL1以接收直流低电平信号，但不限于此，第一控制电路600、第二控制电路610、第三控制电路620、第一复位电路700和第二复位电路800也可以分别连接到不同的电源电压端，以接收不同的低电平信号，只要能够实现相应的功能即可，本公开对此不作具体限制。
需要说明的是，图3A-3D所示的移位寄存器单元10的其他电路结构与图2B中所示的移位寄存器单元10基本上相同，重复之处不再赘述。
图4A为图3D中所示的移位寄存器单元的一种电路结构图，图4B为图3D中所示的移位寄存器单元的另一种电路结构图。在下面对本公开的说明中以各晶体管为N型晶体管为例进行说明，但这并不构成对本公开实施例的限制。
例如，如图4A和图4B所示，第一补偿子电路401包括第一补偿晶体管M15，第二补偿子电路402包括第二补偿晶体管M16，存储子电路403包括第一电容C1。
例如，如图4A和图4B所示，在一些示例中，第一补偿晶体管M15的第一极连接到第一时钟信号端CLKA以接收第一时钟信号，第一补偿晶体管M15的第二极连接到第三节点N，第一补偿晶体管M15的栅极连接到第二节点H。第一电容C1的第一端连接到第二节点H，第一电容C1的第二端连接到第三节点N。第二补偿晶体管M16的第一极连接到第三节点N，第二补偿晶体管M16的第二极连接到第一电压端VGL1，第二补偿晶体管M16的栅极被配置为接收补偿降噪信号CM。例如，在一些示例中，第二补偿晶体管M16的栅极连接到第四节点QB以接收第四节点QB的电压作为补偿降噪信号CM。例如，若第二补偿晶体管M16为N型晶体管，则当第四节点QB的电平为高电平时，第二补偿晶体管M16导通，以将第一电压端VGL1的第一电压传输至第三节点N，从而对第三节点N进行降噪；当第四节点QB的电平为低电平时，第二补偿晶体管M16断开。
例如，第一电压端VGL1被配置为提供第一电压，在一些示例中，第一电压可以为直流低电平信号，以下各实施例与此相同，不再赘述。需要说明的是，在另一些示例中，当移位寄存器单元中的所有晶体管均为P型晶体管时，第一电压也可以为直流高电平信号。
例如，如图4A和图4B所示，充电子电路210包括第一晶体管M1，隔离子电路220包括第二晶体管M2。
例如，第一晶体管M1的栅极被配置为接收检测控制信号OE，第一晶体管M1的第一极被配置为接收第二输入信号，第一晶体管M1的第二极连接到第二节点H。例如，第一晶体管M1的第一极连接至第二输入信号端BP，第二输入信号端BP用于提供第二输入信号。
例如，第二晶体管M2的栅极配置为接收第二控制信号，第二晶体管M2的第一极连接至第二节点H，第二晶体管M2的第一极连接至第一节点Q。例如，在一些示例中，第二晶体管M2的栅极连接至第一时钟信号端CLKA以接收第一时钟信号作为第二控制信号，即第一时钟信号和第二控制信号相同。本公开的实施例不限于此，在另一示例中，第一时钟信号和第二控制信号也可以不相同。
例如，由于晶体管(例如，图4A和图4B所示的第一晶体管M1和第二晶体管M2)的阈值电压损失，当通过第一晶体管M1向第二节点H写入第二输入信号的过程中，由于第一晶体管M1的阈值电压损失，写入第二节点H的电压为V H，V H＝Vin2-Vth1，其中，Vin2为第二输入信号，Vth1为第一晶体管M1的阈值电压。V H小于Vin2。然后，在通过第二晶体管M2将第二节点H的电平写入第一节点Q时，由于第二晶体管M2的阈值电压损失，写入第一节点Q的电压为V Q，V Q＝Vin2-Vth1-Vth2，其中，Vth2为第二晶体管M2的阈值电压。经过两次阈值电压损失，导致第一节点Q的电压V Q与第二输入信号Vin2相差较大，写入到第一节点Q的高电平会低于预定值，从而影响输出端OP输出的复合输出信号。
而在本公开的实施例提供的移位寄存器单元中，如图4A和图4B所示，在第一补偿晶体管M15导通时，第一时钟信号端CLKA提供的第一时钟信号写入第三节点N，基于第一电容C1的自举作用，则可以对第二节点H的电压进行补偿。例如，当第一晶体管M1导通，通过第二输入信号对第二节点H进行充电，使第二节点H的电平为V H，V H＝Vin2-Vth1；当第二补偿晶体管M16导通时，第一电压端VGL1的第一电压被写入至第三节点N，使第三节点N的电压为第一电压；在消隐时段，当第二补偿晶体管M16断开，且在第二节点H的控制下，第一补偿晶体管M15导通时，第一时钟信号的高电平被写入至第三节点N，即第三节点N的电压从第一电压变为第一时钟信号的高电平，由于 第一电容C1的自举作用，第二节点H的电压变为V' H，V' H＝Vin2-Vth1-Vgl1+Vclka，其中，Vgl1为第一电压，Vclka为第一时钟信号的高电平。此时，第二节点H的电压V' H大于第二输入信号Vin2，由此，在将第二节点H的电平写入第一节点Q后，第一节点Q的电平能够达到预定值。
例如，如图4A和图4B所示，移位寄存器单元10还包括第一控制信号端STU2。第一输入电路100包括第三晶体管M3。第三晶体管M3的栅极连接至第一控制信号端STU2以接收第一控制信号，第三晶体管M3的第一极被配置为接收第一输入信号，第三晶体管M3的第二极与第一节点Q连接。例如，在一些示例中，第三晶体管M3的第一极连接至第四电压端VDD，第四电压端VDD等同于前述的第一输入信号端DP，第四电压端VDD提供的第四电压作为第一输入信号。在一帧的显示时段，当第一控制信号为有效电平(例如，高电平)时，第三晶体管M3导通，使第四电压端VDD与第一节点Q连接，从而将第四电压写入第一节点Q，将第一节点Q的电位上拉到工作电位。
例如，在一个示例中，在多个移位寄存器单元10级联的情形下，第n 2级移位寄存器单元10的移位信号输出端CR与第n 2+3级移位寄存器单元10的第一控制信号端STU2连接，以将第n 2级移位寄存器单元10的移位信号输出端CR的输出信号作为第n 2+3级移位寄存器单元10的第一控制信号。这里，n 2为大于0的整数。当然，本公开的实施例不限于此，第一控制信号端STU2也可以与单独设置的信号线连接。
例如，第四电压可以为直流高电平信号(例如高于或等于时钟信号的高电平部分)，以下各实施例与此相同，不再赘述。
例如，如图4A所示，输出端OP包括移位信号输出端CR和第一扫描信号输出端OT1。输出电路300包括第一输出晶体管M18、第二输出晶体管M19和第二电容C2。
例如，第一输出晶体管M18的栅极与第一节点Q连接，第一输出晶体管M18的第一极与第一输出时钟信号端CLKD连接以接收第一输出时钟信号，第一输出晶体管M18的第二极与移位信号输出端CR连接。
例如，第二输出晶体管M19的栅极和第一节点Q连接，第二输出晶体管M19的第一极与第一输出时钟信号端CLKD连接以接收第一输出时钟信号，第二输出晶体管M19的第二极与第一扫描信号输出端OT1连接；第二电容C2的第一端和第一节点Q连接，第二电容C2的第二端与第二输出晶体管M19的 第二极连接。
例如，当第一节点Q处于工作电位(例如，高电平)时，第一输出晶体管M18和第二输出晶体管M19均导通，从而第一输出时钟信号经由第一输出晶体管M18传输到移位信号输出端CR以作为第一输出信号，第一输出时钟信号经由第二输出晶体管M19传输到第一扫描信号输出端OT1以作为第二输出信号。
例如，复合输出信号包括第一输出信号和第二输出信号，第一输出信号和第二输出信号相同。例如，第二输出信号包括上述显示输出信号和消隐输出信号，即在显示时段，第一扫描信号输出端OT1输出的信号为显示输出信号；在消隐时段，第一扫描信号输出端OT1输出的信号为消隐输出信号。
例如，如图4A所示，输出端OP还包括第二扫描信号输出端OT2，输出电路300还包括第三输出晶体管M20和第三电容C3。
例如，第三输出晶体管M20的栅极与第一节点Q连接，第三输出晶体管M20的第一极与第二输出时钟信号端CLKE连接以接收第二输出时钟信号，第三输出晶体管M20的第二极与第二扫描信号输出端OT2连接。第三电容C3的第一端和第一节点Q连接，第三电容C3的第二端与第三输出晶体管M20的第二极连接。
例如，当第一节点Q处于工作电位(例如，高电平)时，第三输出晶体管M20导通，第二输出时钟信号经由第三输出晶体管M20传输到第二扫描信号输出端OT2以作为第三输出信号。例如，复合输出信号还包括第三输出信号。
例如，在一个示例中，第一输出时钟信号端CLKD和第二输出时钟信号端CLKE提供的时钟信号相同，因此，第一扫描信号输出端OT1输出的第二输出信号和第二扫描信号输出端OT2输出的第三输出信号相同。例如，在另一个示例中，第一输出时钟信号端CLKD和第二输出时钟信号端CLKE提供的信号不同，从而使得第一扫描信号输出端OT1输出的第二输出信号和第二扫描信号输出端OT2输出的第三输出信号不同，以便为像素单元提供多种驱动信号。
例如，第一输出时钟信号的低电平可以与第一电压端VGL1输出的第一电压的低电平相同。第二输出时钟信号的低电平也可以与第一电压端VGL1输出的第一电压的低电平相同。第一输出时钟信号的高电平和第二输出时钟信号的高电平相同。
例如，如图4B所示，在另一些实施例中，输出电路300还包括第四电容 C4，第四电容C4的第一端和第一节点Q连接，第四电容C4的第二端与第一输出晶体管M18的第二极连接。
需要说明的是，本公开的各实施例中，第一电容C1、第二电容C2、第三电容C3和第四电容C4可以是通过工艺制程制作的电容器件，例如通过制作专门的电容电极来实现电容器件，该电容的各个电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现，并且，第一电容C1、第二电容C2、第三电容C3和第四电容C4也可以是晶体管之间的寄生电容，可以通过晶体管本身与其他器件、线路来实现。例如，第一电容C1能够维持第二节点H的电平，且在第一时钟信号的高电平被传输至第三节点N时能够实现自举作用。第二电容C2、第三电容C3和第四电容C4均能够维持第一节点Q的电平，在第一扫描信号输出端OT1输出信号时，第二电容C2能够实现自举作用，在第二扫描信号输出端OT2输出信号时，第三电容C3能够实现自举作用，在移位信号输出端CR输出信号时，第四电容C4能够实现自举作用。
例如，如图4A和图4B所示，降噪电路500包括第四晶体管M4、第五晶体管M5、第六晶体管M6和第七晶体管M7。
例如，第四晶体管M4的栅极与第四节点QB连接，第四晶体管M4的第一极与第一节点Q连接，第四晶体管M4的第二极与第一电压端VGL1连接以接收第一电压。
例如，第五晶体管M5的栅极与第四节点QB连接，第五晶体管M5的第一极与移位信号输出端CR连接，第五晶体管M5的第二极与第一电压端VGL1连接以接收第一电压。
例如，第六晶体管M6的栅极与第四节点QB连接，第六晶体管M6的第一极与第一扫描信号输出端OT1连接，第六晶体管M6的第二极与第二电压端VGL2连接以接收第二电压。
例如，第七晶体管M7的栅极与第四节点QB连接，第七晶体管M7的第一极与第二扫描信号输出端OT2连接，第七晶体管M7的第二极与第二电压端VGL2连接以接收第二电压。
例如，第二电压端VGL2被配置为提供第二电压，且第二电压为直流低电平信号(例如低于或等于时钟信号的低电平)，例如，第二电压端VGL2可以接地，以下各实施例与此相同，不再赘述。例如，在一个示例中，第二电压端VGL2提供的第二电压高于第一电压端VGL1提供的第一电压，例如，第一电 压为-10V，第二电压为-6V；在另一个示例中，第二电压端VGL2的第二电压等于第一电压端VGL1的第一电压，从而该移位寄存器单元10可以不设置第二电压端VGL2，而将第六晶体管M6的第二极和第七晶体管M7的第二极均连接到第一电压端VGL1。第一电压和第二电压可以相同也可以不同，这可以根据实际需求而定。本公开的实施例对此不作限定。
需要说明的是，当输出电路300不设置第三输出晶体管M20时，相应地，降噪电路500可以不设置第七晶体管M7。
例如，当第四节点QB为有效电平(例如，高电平)时，第四晶体管M4、第五晶体管M5、第六晶体管M6和第七晶体管M7均导通，第一节点Q和移位信号输出端CR均与第一电压端VGL1连接，从而通过第一压端VGL1将第一节点Q的电位和移位信号输出端CR的电位下拉为低电位，第一扫描信号输出端OT1和第二扫描信号输出端OT2均与第二电压端VGL2连接，从而通过第二电压端VGL2将第一扫描信号输出端OT1和第二扫描信号输出端OT2的电位下拉为低电位，由此，降低第一节点Q、移位信号输出端CR、第一扫描信号输出端OT1和第二扫描信号输出端OT2的噪声。需要说明的是，本公开的各实施例中，当输出端OP包括多个第一扫描信号输出端和/或多个移位信号输出端时，降噪电路500也相应地包括与多个移位信号输出端和/或多个第一扫描信号输出端一一对应连接的多个晶体管，以对多个移位信号输出端和/或多个第一扫描信号输出端进行降噪。
例如，如图4A所示，在一些实施例中，第一控制电路600包括第八晶体管M8和第九晶体管M9。
例如，第八晶体管M8的栅极和第一极连接且被配置为连接第三电压端VDD_A以接收第三电压，第八晶体管M8的第二极连接第四节点QB。第九晶体管M9的栅极连接第一节点Q，第九晶体管M9的第一极连接到第四节点QB，第九晶体管M9的第二极连接到第一电压端VGL1以接收第一电压。
例如，如图4B所示，在另一些实施例中，第一控制电路600还包括第十七晶体管M17。第十七晶体管M17的栅极与第一极连接且被配置为与第五电压端VDD_B连接以接收第五电压，第十七晶体管M17的第二极与第四节点QB连接。
例如，在一个示例中，第三电压端VDD_A被配置为提供直流低电平信号，第五电压端VDD_B被配置为提供直流高电平信号，因此，第八晶体管M8始 终截止，第十七晶体管M17始终导通。例如，在另一个示例中，第三电压端VDD_A和第五电压端VDD_B被配置为交替提供直流高电平信号，从而使第八晶体管M8和第十七晶体管M17交替导通，以避免晶体管长期导通引起的性能漂移。例如，当第三电压端VDD_A提供高电平信号时，第五电压端VDD_B提供低电平信号，此时第八晶体管M8导通，第十七晶体管M17截止；当第五电压端VDD_B提供高电平信号时，第三电压端VDD_A提供低电平信号，此时，第十七晶体管M17导通，第八晶体管M8截止。
例如，当第一节点Q为有效电平(例如，高电平)时，第九晶体管M9导通，通过设计第九晶体管M9的沟道宽长比与导通的第八晶体管M8的沟道宽长比或导通的第十七晶体管M17的沟道宽长比的比例关系，例如，第九晶体管M9的沟道宽长比大于第八晶体管M8的沟道宽长比和第十七晶体管M17的沟道宽长比中的任意一个，由此，可以将第四节点QB的电位下拉到低电平。当第一节点Q为低电平时，第九晶体管M9截止，若第八晶体管M8导通，第十七晶体管M17截止，则通过第八晶体管M8将第三电压端VDD_A提供的第三电压(高电平)写入第四节点QB，以将第四节点QB的电位上拉至高电平；若第八晶体管M8截止，第十七晶体管M17导通，则通过第十七晶体管M17将第五电压端VDD_B提高的第五电压(高电平)写入第四节点QB，以将第四节点QB的电位上拉至高电平。
例如，如图4A和图4B所示，第一复位电路700包括第十晶体管M10。第十晶体管M10的栅极连接至第一复位控制信号端Re1以接收第一复位控制信号，第十晶体管M10的第一极连接到第一节点Q，第十晶体管M10的第二极连接到第一电压端VGL1以接收第一电压。例如，在一帧的显示时段，当第一复位信号为有效电平(例如，高电平)时，第十晶体管M10导通，第一节点Q与第一电压端VGL1连接，第一电压端VGL1提供的第一电压被写入第一节点Q，从而实现对第一节点Q复位。
例如，在一个示例中，在多个移位寄存器单元10级联的情形下，第n 2+3级移位寄存器单元10的移位信号输出端CR与第n 2级移位寄存器单元10的第一复位控制信号端Re1连接，以将第n 2+3级移位寄存器单元10的移位信号输出端CR的输出信号作为第n 2级移位寄存器单元10的第一复位控制信号。这里，n 2为大于0的整数。当然，本公开的实施例不限于此，第一复位控制信号端Re1也可以与单独设置的信号线连接。
例如，如图4A和图4B所示，第二复位电路800包括第十一晶体管M11。第十一晶体管M11的栅极连接至第二复位控制信号端Re2以接收第二复位控制信号，第十一晶体管M11的第一极连接到第一节点Q，第十一晶体管M11的第二极连接到第一电压端VGL1以接收第一电压。例如，在一帧的消隐时段，当第二复位信号为有效电平(例如，高电平)时，第十一晶体管M11导通，第一节点Q与第一电压端VGL1连接，第一电压端VGL1提供的第一电压被写入第一节点Q，从而实现对第一节点Q复位。
例如，如图4A和图4B所示，第二控制电路610包括第十二晶体管M12和第十三晶体管M13。第三控制信号包括第一时钟信号和第二节点H的电压值。
例如，第十二晶体管M12的栅极被配置为连接第一时钟信号端CLKA以接收第一时钟信号，第十二晶体管M12的第一极被配置为连接第四节点QB，第十二晶体管M12的第二极连接到第十三晶体管M13的第一极，第十三晶体管M13的栅极连接到第二节点H，第十三晶体管M13的第二极连接到第一电压端VGL1以接收第一电压。
例如，在一帧的消隐时段，当第一时钟信号和第二节点H的电平均为有效电平(例如，高电平)时，第十二晶体管M12和第十三晶体管M13导通，第四节点QB与第一电压端VGL1连接，第一电压端VGL1提供的第一电压被写入第四节点QB，从而第四节点QB被下拉至低电平。
需要说明的是，在一些实施例中，第二控制电路610可以仅包括第十二晶体管M12，第三控制信号可以仅包括第一时钟信号，第十二晶体管M12的栅极被配置为连接第一时钟信号端CLKA以接收第一时钟信号，第十二晶体管M12的第一极被配置为连接第四节点QB，第十二晶体管M12的第二极连接到第一电压端VGL1以接收第一电压。
例如，如图4A和图4B所示，第三控制电路620包括第十四晶体管M14。第十四晶体管M14的栅极被配置为连接至第四控制信号端Con2以接收第四控制信号，第十四晶体管M14的第一极连接至第四节点QB，第十四晶体管M14的第二极连接第一电压端VGL1以接收第一电压。例如，在一帧的显示时段，当第四控制信号为有效电平(例如，高电平)时，第十四晶体管M14导通，第四节点QB与第一电压端VGL1连接，第一电压端VGL1提供的第一电压被写入第四节点QB，从而第四节点QB被下拉至低电平。
例如，在一个示例中，在多个移位寄存器单元10级联的情形下，第m2级移位寄存器单元10的移位信号输出端CR与第m2+3级移位寄存器单元10的第四控制信号端Con2连接，以将第m2级移位寄存器单元10的移位信号输出端CR的输出信号作为第m2+3级移位寄存器单元10的第四控制信号。这里，m2为大于0的整数。当然，本公开的实施例不限于此，第四控制信号端Con2也可以与单独设置的信号线连接。
需要说明的是，本领域技术人员可以理解，在本公开的实施例中，第一输入电路100、第二输入电路200、输出电路300、补偿电路400、降噪电路500、第一控制电路600，第二控制电路610、第三控制电路620、第一复位电路700以及第二复位电路800等的具体实现方式不局限于上面描述的方式，其可以为任意适用的实现方式，例如为本领域技术人员熟知的常规连接方式，只需保证实现相应功能即可。上述示例并不能限制本公开的保护范围。在实际应用中，技术人员可以根据情况选择使用或不使用上述各电路中的一个或多个，基于前述各电路的各种组合变型均不脱离本公开的原理，对此不再赘述。例如，本领域技术人员可以理解，根据本公开的实施例提供的移位寄存器单元可以具有防漏电功能，例如，根据实际情况选择移位寄存器单元10中的一个或多个晶体管增加防漏电的电路结构。另外，在本公开的各个实施例的说明中，第一节点Q、第二节点H、第三节点N、第四节点QB等并非表示实际存在的部件，而是表示电路图中相关连接的汇合点。
本公开的实施例中采用的晶体管均可以为薄膜晶体管、场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。此外，本公开的实施例中的晶体管均以N型晶体管为例进行说明，此时，晶体管的第一极是漏极，第二极是源极。需要说明的是，本公开包括但不限于此。例如，本公开的实施例提供的移位寄存器单元10中的一个或多个晶体管也可以采用P型晶体管，此时，晶体管的第一极是源极，第二极是漏极，只需将选定类型的晶体管的各极参照本公开的实施例中的相应晶体管的各极相应连接，并且使相应的电压端提供对应的高电压或低电压即可。当采用N型晶体管时，可以采用氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)作为薄膜晶体管的有源层，相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及防止漏电流。
图5为本公开一些实施例提供的一种移位寄存器单元的信号时序图。下面结合图5所示的信号时序图，对图4B所示的移位寄存器单元10的工作原理进行说明，并且这里以各个晶体管为N型晶体管为例进行说明，但是本公开的实施例不限于此。
在图5中以及下面的描述中，1F和2F分别表示第一帧、第二帧、第三帧和第四帧的时序。DS表示一帧的显示时段，BL表示一帧的消隐时段。STU1、STU2、Con1、Con2、VDD_A、VDD_B、CLKA、CLKD、CLKE、OT1、OT2、CR等既用于表示相应的信号端，也用于表示相应的信号。以下各实施例与此相同，不再赘述。
例如，如图4B和图5所示，在初始阶段0，第二复位信号Re2为高电平，第十一晶体管M11导通，第一电压端VGL1的第一电压经由第十一晶体管M11被写入第一节点Q，以对第一节点Q进行复位。第三电压VDD_A为低高电平信号，第五电压VDD_B为高电平信号，由此，第八晶体管M8截止，第十七晶体管M17导通，第五电压VDD_B经由第十七晶体管M17被写入第四节点QB，第四节点QB的电位上拉至高电平，由此，第四晶体管M4导通，从而对第一节点Q进行辅助下拉，使第一节点Q的电位为低电平。由于第四节点QB的电平为高电平，第二补偿晶体管M16也导通，由此第三节点N也被复位。此外，由于第四节点QB的电位为高电平，由此，第五晶体管M5、第六晶体管M6和第七晶体管M7均导通，从而对移位信号输出端CR、第一扫描信号输出端OT1和第二扫描信号输出端OT2进行降噪，使移位信号输出端CR、第一扫描信号输出端OT1和第二扫描信号输出端OT2的电位为低电平。
例如，在显示时段DS，在第一阶段1中，第一控制信号端STU2为高电平，第三晶体管M3导通，第一输入信号(例如，第四电压端VDD提供的高电平的第四电压)经由第三晶体管M3被写入第一节点Q，且被第四电容C4存储。检测控制信号OE为高电平，从而第一晶体管M1导通，第二输入信号(例如，高电平信号)经由第一晶体管M1被写入第二节点H，且被第一电容C1存储，此时，第二节点H的电平为高电平。需要说明的是，第一电容C1可以存储高电平的第二输入信号并保持到一帧的显示时段结束，以用于在消隐时段使用。第一时钟信号CLKA为低电平信号，第二晶体管M2截止。
由于第一节点Q为高电平，第一输出晶体管M18、第二输出晶体管M19和第三输出晶体管M20均导通，第一输出时钟信号CLKD经由第一输出晶体 管M18和第二输出晶体管M19被分别输出至移位信号输出端CR和第一扫描信号输出端OT1，第二输出时钟信号CLKE经由第三输出晶体管M20被输出至第二扫描信号输出端OT2。但由于第一输出时钟信号CLKD和第二输出时钟信号CLKE均为低电平信号，即移位信号输出端CR、第一扫描信号输出端OT1和第二扫描信号输出端OT2均输出低电平信号。另外，由于第一节点Q为高电平，第九晶体管M9导通，从而将第四节点QB的电位下拉到低电平。
例如，如图4B和图5所示，在第二阶段2中，第一节点Q保持为高电平，第一输出晶体管M18、第二输出晶体管M19和第三输出晶体管M20保持导通，第一输出时钟信号CLKD和第二输出时钟信号CLKE均变为高电平，由此移位信号输出端CR、第一扫描信号输出端OT1和第二扫描信号输出端OT2均输出高电平信号，由于第二电容C2、第三电容C3和第四电容C4的自举效应，第一节点Q的电位进一步被拉高，第一输出晶体管M18、第二输出晶体管M19和第三输出晶体管M20更加充分导通。例如，移位信号输出端CR输出的高电平信号可以用于上下级移位寄存器单元的扫描移位，从第一扫描信号输出端OT1和第二扫描信号输出端OT2输出的高电平信号可以用于驱动显示面板中的像素单元进行显示。
例如，如图4B和图5所示，在第三阶段3，第一输出时钟信号CLKD和第二输出时钟信号CLKE变为低电平，移位信号输出端CR和第一扫描信号输出端OT1均可以通过第一输出时钟信号端CLKD放电，从而完成移位信号输出端CR和第一扫描信号输出端OT1的复位；第二扫描信号输出端OT2通过第二输出时钟信号端CLKE放电，从而完成第二扫描信号输出端OT2的复位。此时，移位信号输出端CR、第一扫描信号输出端OT1和第二扫描信号输出端OT2均输出低电平信号，由于第二电容C2、第三电容C3和第四电容C4的自举作用，第一节点Q的电位有所降低但仍然保持高电平，第一输出晶体管M18、第二输出晶体管M19和第三输出晶体管M20仍保持导通，第一输出时钟信号端CLKD的低电平输出至移位信号输出端CR和第一扫描信号输出端OT1，第二输出时钟信号端CLKE的低电平输出至第二扫描信号输出端OT2，由此实现输出端OP的复位。
例如，如图4B和图5所示，在第四阶段4中，第一复位信号Re1(图中未示出)为高电平信号，第十晶体管M10导通，从而第一电压端VGL1的第一电压被写入第一节点Q，以对第一节点Q进行复位。第一节点Q的电平变 为低电平，从而第九晶体管M9截止，第三电压VDD_A为高电平信号，第五电压VDD_B为低电平信号，由此，第八晶体管M8截止，第十七晶体管M17导通，从而第五电压VDD_B经由第十七晶体管M17被写入第四节点QB，第四节点QB被上拉为高电平，从而第四晶体管M4导通，以进一步对第一节点Q进行降噪。第五晶体管M5、第六晶体管M6和第七晶体管M7也在第一节点QB的高电平的控制下导通，从而对移位信号输出端CR、第一扫描信号输出端OT1和第二扫描信号输出端OT2进行降噪。
例如，在上述第一阶段1至第三阶段3中，由于第四节点QB均为低电平，第二补偿晶体管M16截止。而在第四阶段4中，由于第四节点QB被上拉为高电平，第二补偿晶体管M16导通，从而对第三节点N进行降噪，使第三节点N的电平为低电平。
例如，在上述第一阶段1至第四阶段4中，由于第一时钟信号CLKA一直保持低电平，第二晶体管M2处于截止状态，从而隔离第二节点H和第一节点Q，以避免第二节点H的电平影响显示时段的输出信号。如图5所示，第一节点Q的电平呈塔状波形，移位信号输出端CR的输出信号的上拉和复位都通过第一输出晶体管M18实现，第一扫描信号输出端OT1的输出信号的上拉和复位都通过第二输出晶体管M19实现，第二扫描信号输出端OT2的输出信号的上拉和复位都通过第三输出晶体管M20实现，第五晶体管M5对移位信号输出端CR的输出信号起辅助下拉的作用，第六晶体管M6对第一扫描信号输出端OT1的输出信号起辅助下拉的作用，第七晶体管M7对第二扫描信号输出端OT2的输出信号起辅助下拉的作用，因此可以减小第五晶体管M5、第六晶体管M6和第七晶体管M7的体积，有利于减小电路版图的面积。
例如，如图4B和图5所示，在消隐时段BL，在第五阶段5，由于第一电容C1的保持作用，第二节点H仍然保持为高电平，第一补偿晶体管M15导通，第一时钟信号CLKA为高电平信号，第一时钟信号CLKA可以对第三节点N充电，以使第三节点N的电平变为高电平，由于第一电容C1的自举效应，第二节点H的电位进一步被拉高，从而实现对第二节点H的补偿操作。此时，第一补偿晶体管M15更加充分导通，使第三节点N的电平能够达到第一时钟信号CLKA的高电平。同时，由于第一时钟信号CLKA为高电平信号，第二晶体管M2导通，第二节点H的电平被传输至第一节点Q，以将第一节点Q上拉至高电位。第九晶体管M9在第一节点Q的控制下导通，第四节点QB 被下拉至低电平。由于第一节点Q的电平为高电平，第一输出晶体管M18、第二输出晶体管M19和第三输出晶体管M20均导通，第一输出时钟信号CLKD经由第一输出晶体管M18和第二输出晶体管M19被分别输出至移位信号输出端CR和第一扫描信号输出端OT1，第二输出时钟信号CLKE经由第三输出晶体管M20被输出至第二扫描信号输出端OT2。但由于第一输出时钟信号CLKD和第二输出时钟信号CLKE均为低电平信号，即移位信号输出端CR、第一扫描信号输出端OT1和第二扫描信号输出端OT2均输出低电平信号。
例如，如图4B和图5所示，在第六阶段6，第一时钟信号CLKA变为低电平，第二晶体管M2截止，从而第一节点Q不会通过第二晶体管M2漏电。第一节点Q保持为高电平，第一输出晶体管M18、第二输出晶体管M19和第三输出晶体管M20保持导通，第一输出时钟信号CLKD变为高电平，由此移位信号输出端CR和第一扫描信号输出端OT1均输出高电平信号，由于第二电容C2、第三电容C3和第四电容C4的自举效应，第一节点Q的电位进一步被拉高，第一输出晶体管M18、第二输出晶体管M19和第三输出晶体管M20更加充分导通。例如，第一扫描信号输出端OT1输出的信号可以用于驱动显示面板中像素单元中的感测晶体管，以实现外部补偿。由于第二输出时钟信号CLKE输出脉冲信号，从而第二扫描信号输出端OT2也输出脉冲信号。需要说明的是，在第六阶段6，第二扫描信号输出端OT2输出的信号可以根据实际应用设计，本公开对此不作限制。
例如，在第六阶段6，第一时钟信号CLKA变为低电平，从而第三节点N的电平变为低电平，由于第一电容C1的自举作用，第二节点H的电位有所降低但仍然保持高电平。
例如，如图4B和图5所示，在第七阶段7，第一输出时钟信号CLKD和第二输出时钟信号CLKE变为低电平，移位信号输出端CR和第一扫描信号输出端OT1均可以通过第一输出时钟信号端CLKD放电，从而完成移位信号输出端CR和第一扫描信号输出端OT1的复位；第二扫描信号输出端OT2通过第二输出时钟信号端CLKE放电，从而完成第二扫描信号输出端OT2的复位。此时，移位信号输出端CR、第一扫描信号输出端OT1和第二扫描信号输出端OT2均输出低电平信号，由于第二电容C2、第三电容C3和第四电容C4的自举作用，第一节点Q的电位有所降低但仍然保持高电平，第一输出晶体管M18、第二输出晶体管M19和第三输出晶体管M20仍保持导通，第一输出时钟信号 端CLKD的低电平输出至移位信号输出端CR和第一扫描信号输出端OT1，第二输出时钟信号端CLKE的低电平输出至第二扫描信号输出端OT2，由此实现输出端OP的复位。
例如，如图4B和图5所示，在第八阶段8，第二复位信号Re2为高电平，第十一晶体管M11导通，第一电压端VGL1的第一电压经由第十一晶体管M11被写入第一节点Q，以对第一节点Q进行复位。检测控制信号OE为高电平，第一晶体管M1也导通，此时，第二输入信号BP为低电平信号，第二输入信号BP经由第一晶体管M1被写入第二节点H，由此第二节点H也被复位。这样可以使第二节点H保持为高电平的时间较短，以降低与第二节点H连接的晶体管阈值电压漂移(例如正漂)的风险，有助于提高该电路的信赖性。
需要说明的是，上述关于显示时段DS和消隐时段BL的工作过程的描述中，以移位寄存器单元包括两个扫描信号输出端(即，第一扫描信号输出端OT1和第二扫描信号输出端OT2)为例，但不限于此，该移位寄存器单元可以仅包括一个扫描信号输出端(例如，第一扫描信号输出端OT1)。当该移位寄存器单元可以仅包括第一扫描信号输出端OT1时，移位寄存器单元的工作过程与上述工作过程相似，只要省略关于第二扫描信号输出端OT2的相关描述即可，在此不再赘述。
值得注意的是，在本公开的实施例中，例如，当各个电路实现为N型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如截止)。术语“工作电位”表示该节点处于高电位，从而当一个晶体管的栅极连接到该节点时，该晶体管导通；术语“非工作电位”表示该节点处于低电位，从而当一个晶体管的栅极连接到该节点时，该晶体管截止。又例如，当各个电路实现为P型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如截止)。术语“工作电位”表示该节点处于低电位，从而当一个晶体管的栅极连接到该节点时，该晶体管导通；术语“非工作电位”表示该节点处于高电位， 从而当一个晶体管的栅极连接到该节点时，该晶体管截止。
图6为本公开一些实施例提供的一种栅极驱动电路的示意框图。
本公开至少一些实施例还提供一种栅极驱动电路。例如，如图6所示，该栅极驱动电路20包括多个移位寄存器单元(例如，A1、A2、A3、A4等)。多个移位寄存器单元级联设置。多个移位寄存器单元的数量不受限制，可以根据实际需求而定。例如，移位寄存器单元采用本公开任一实施例所述的移位寄存器单元10。
该栅极驱动电路的电路结构简单，可以补偿在消隐时段写入第一节点的电平的阈值电压损失，从而防止由于晶体管的阈值电压损失而对输出信号造成影响，增强电路的信赖性。同时，该移位寄存器单元可以实现随机补偿，避免由于逐行顺序补偿造成的扫描线和面板的亮度偏差，提高显示均匀性，提升显示效果。
例如，该栅极驱动电路20可以采用与薄膜晶体管同样制程的工艺直接集成在显示装置的阵列基板上，以实现逐行扫描驱动功能。这些移位寄存器单元的第一扫描信号输出端OT1分别与多条第一栅线(例如，G11、G21、G31、G41等)一一对应连接；这些移位寄存器单元的第二扫描信号输出端OT2分别与多条第二栅线(例如，G12、G22、G32、G42等)一一对应连接。
例如，每个移位寄存器单元包括第一控制信号端STU2、第一时钟信号端CLKA(第一时钟信号端CLKA也为第二控制信号端STU1)、检测控制信号端OE、第一输出时钟信号端CLKD、第二输出时钟信号端CLKE、第一复位信号端Re1、第二复位信号端Re2、第四控制信号端Con2、移位信号输出端CR、第一扫描信号输出端OT1和第二扫描信号输出端OT2等。
例如，如图6所示，栅极驱动电路20还包括第一时钟信号线CLK_1、第二时钟信号线CLK_2、第三时钟信号线CLK_3和第四时钟信号线CLK_4。各级移位寄存器单元与上述各时钟信号线的连接方式如下并以此类推。
例如，在移位寄存器单元包括第一输出时钟信号端的情形下，如图6所示，多个移位寄存器单元的第4n 1-3级移位寄存器单元(例如，第一级移位寄存器单元A1)的第一输出时钟信号端CLKD与第一时钟信号线CLK_1连接；多个移位寄存器单元的第4n 1-2级移位寄存器单元(例如，第二级移位寄存器单元A2)的第一输出时钟信号端CLKD与第二时钟信号线CLK_2连接；多个移位寄存器单元的第4n 1-1级移位寄存器单元(例如，第三级移位寄存器单元A3) 的第一输出时钟信号端CLKD与第三时钟信号线CLK_3连接；多个移位寄存器单元的第4n 1级移位寄存器单元(例如，第四级移位寄存器单元A4)的第一输出时钟信号端CLKD与第四时钟信号线CLK_4连接；n 1为大于0的整数。
例如，如图6所示，栅极驱动电路20还包括第五时钟信号线CLK_5、第六时钟信号线CLK_6、第七时钟信号线CLK_7、第八时钟信号线CLK_8。各级移位寄存器单元与上述各时钟信号线的连接方式如下并以此类推。
例如，如图6所示，在移位寄存器单元包括第二输出时钟信号端的情形下，第4n 1-3级移位寄存器单元(例如，第一级移位寄存器单元A1)的第二输出时钟信号端CLKE与第五时钟信号线CLK_5连接；第4n 1-2级移位寄存器单元(例如，第二级移位寄存器单元A2)的第二输出时钟信号端CLKE与第六时钟信号线CLK_6连接；第4n 1-1级移位寄存器单元(例如，第三级移位寄存器单元A3)的第二输出时钟信号端CLKE与第七时钟信号线CLK_7连接；第4n 1级移位寄存器单元(例如，第四级移位寄存器单元A4)的第二输出时钟信号端CLKE与第八时钟信号线CLK_8连接。
例如，如图6所示，栅极驱动电路20还包括第九时钟信号线CLK_9和第十时钟信号线CLK_10。第九时钟信号线CLK_9被配置为与各级移位寄存器单元(例如，第一级移位寄存器单元A1、第二级移位寄存器单元A2、第三级移位寄存器单元A3和第四级移位寄存器单元A4)的第一时钟信号端CLKA(即第二控制信号端STU1)连接。第十时钟信号线CLK_10被配置为与各级移位寄存器单元(例如，第一级移位寄存器单元A1、第二级移位寄存器单元A2、第三级移位寄存器单元A3和第四级移位寄存器单元A4)的第二复位控制信号端Re2连接。
例如，在移位寄存器单元包括移位信号输出端和第一控制信号端STU2的情形下，如图6所示，在一些实施例中，第一级移位寄存器单元A1的第一控制信号端STU2和第四控制信号端Con2、第二级移位寄存器单元A2的第一控制信号端STU2和第四控制信号端Con2、以及第三级移位寄存器单元A3的第一控制信号端STU2和第四控制信号端Con2均连接控制信号线STU，例如接收触发信号STV。除了第一级移位寄存器单元A1、第二级移位寄存器单元A2和第三级移位寄存器单元A3外，多个移位寄存器单元的第n 2+3级移位寄存器单元(例如，第四级移位寄存器单元A4)的第一控制信号端STU2和第四控制信号端Con2连接多个移位寄存器单元的第n 2级移位寄存器单元(例如，第一 级移位寄存器单元A1)的移位信号输出端CR，n 2为大于0的整数。
例如，如图6所示，在一些实施例中，第一级移位寄存器单元A1的第二输入信号端BP和第二级移位寄存器单元A2的第二输入信号端BP均连接输入信号线。除了第一级移位寄存器单元A1和第二级移位寄存器单元A2外，多个移位寄存器单元的第n 2+2级移位寄存器单元(例如，第三级移位寄存器单元A2)的第二输入信号端BP连接第n 2级移位寄存器单元(例如，第一级移位寄存器单元A1)的移位信号输出端CR，即第n 2级移位寄存器单元的移位信号输出端CR输出的信号作为第n 2+2级移位寄存器单元的第二输入信号BP。
例如，在移位寄存器单元包括第一复位控制信号端Re1的情形下，如图6所示，在一些实施例中，除了最后三级移位寄存器单元外，第n 2级移位寄存器单元(例如，第一级移位寄存器单元A1)的第一复位控制信号端Re1连接第n 2+3级移位寄存器单元(例如，第四级移位寄存器单元A4)的移位信号输出端CR连接。例如，当该栅极驱动电路20仅包括四个移位寄存器单元时，第二级移位寄存器单元A2的第一复位控制信号端Re1、第三级移位寄存器单元A3的第一复位控制信号端Re1、第四级移位寄存器单元A4的第一复位控制信号端Re1可以分别与单独设置复位信号线连接。
例如，栅极驱动电路20还可以包括时序控制器T-CON，时序控制器T-CON例如配置为向各级移位寄存器单元提供上述各个时钟信号，时序控制器T-CON还可以被配置为提供触发信号和复位信号。需要说明的是，时序控制器T-CON提供的多个时钟信号彼此之间的相位关系可以根据实际需求而定。在不同的示例中，根据不同的配置，还可以提供更多的时钟信号。例如，该栅极驱动电路20还包括多条电压线，以向各级移位寄存器单元提供多个电压信号。
例如，当采用该栅极驱动电路20驱动显示面板时，可以将该栅极驱动电路20设置于显示面板的一侧。当然，还可以分别在显示面板的两侧设置该栅极驱动电路20，以实现双边驱动，本公开的实施例对栅极驱动电路20的设置方式不作限制。例如，可以在显示面板的一侧设置栅极驱动电路20以用于驱动奇数行栅线，而在显示面板的另一侧设置栅极驱动电路20以用于驱动偶数行栅线。
图7为本公开一些实施例提供的一种栅极驱动电路的信号时序图，该信号时序图为图6中所示的栅极驱动电路20的时序，该栅极驱动电路20中的移位寄存器单元为图4B中所示的移位寄存器单元10。栅极驱动电路20的工作原 理可参考本公开的实施例中对于移位寄存器单元10的相应描述，重复之处不再赘述。
需要说明的是，在图7中，Q<7>和Q<8>分别表示栅极驱动电路20中第七级和第八级移位寄存器单元中第一节点Q；H<7>表示栅极驱动电路20中第七级移位寄存器单元中第二节点H；N<7>表示栅极驱动电路20中第七级移位寄存器单元中第三节点N。OT1<7>和OT2<7>分别表示栅极驱动电路20中的第七级移位寄存器单元中第一扫描信号输出端OT1和第二扫描信号输出端OT2，OT1<8>和OT2<8>分别表示栅极驱动电路20中的第八级移位寄存器单元中第一扫描信号输出端OT1和第二扫描信号输出端OT2。MF表示第M帧，M为正整数。DS表示一帧中的显示时段，BL表示一帧中的消隐时段。需要说明的是，由于每一级移位寄存器单元中的第一扫描信号输出端OT1和移位信号输出端CR的电位相同，所以在图7中未示出移位信号输出端CR。值得注意的是，图5和图7所示的信号时序图中的信号电平只是示意性的，不代表真实电平值。
例如，在显示时段DS，移位寄存器单元10向多行栅线逐行输出扫描驱动信号，直至向最后一行栅线输出扫描驱动信号后完成一帧的显示。例如，在第M帧中，第n行像素单元需要进行检测补偿，第n行像素单元与第n级移位寄存器单元10的输出端连接，从而在消隐时段BL，第n级移位寄存器单元10的第一扫描信号输出端OT1输出高电平信号，以对第n行像素单元进行检测。
例如，如图4B和图7所示，若在第M帧内，需要对第七行像素单元进行检测，第七行像素单元与第七级移位寄存器单元对应。在第M帧内，外部控制电路将第五级移位寄存器单元的移位信号输出端CR输出的信号输出至每级移位寄存器单元的检测控制信号端OE，即检测控制信号与第五级移位寄存器单元的移位信号输出端CR输出的信号的波形脉冲宽度相同。
由于在图6所示的示例中，第n 2+2级移位寄存器单元的第二输入信号端BP连接第n 2级移位寄存器单元的移位信号输出端CR。由此，在显示时段DS的第一阶段1，当第五级移位寄存器单元的移位信号输出端CR输出高电平信号时，如图4B所示，第七级移位寄存器单元的充电子电路210中的第一晶体管M1导通，由此，第五级移位寄存器单元的移位信号输出端CR输出高电平信号被写入第七级移位寄存器单元的第二节点H，以将第五级移位寄存器单元的第二节点H拉高至高电平。
例如，如图7所示，第一时钟信号CLK_1、第二时钟信号CLK_2、第三时钟信号CLK_3和第四时钟信号CLK_4在一帧的显示时段内的波形依次重叠有效脉宽的50％，第一至第四级移位寄存器单元A1-A4的第一扫描信号输出端OT1的输出信号OT1<1>、OT1<2>、OT1<3>和OT1<4>在一帧的显示时段内的波形依次重叠有效脉宽的50％。第五时钟信号线CLK_5、第六时钟信号线CLK_6、第七时钟信号线CLK_7、第八时钟信号线CLK_8在一帧的显示时段内的波形也依次重叠有效脉宽的50％，第一至第四级移位寄存器单元A1-A4的第二扫描信号输出端OT2的输出信号OT2<1>、OT2<2>、OT2<3>和OT2<4>在一帧的显示时段内的波形也依次重叠有效脉宽的50％。该栅极驱动电路20在显示时段内的输出信号的波形有重叠，因此可以实现预充电功能，提高充电效率，可缩短像素电路的整体充电时间(即一帧中的显示时段的时间)，有利于实现高刷新率。此时，显示面板上的位于奇数行的像素和位于偶数行的像素可以分别连接不同的数据线，从而在相邻两行像素单元同时被充电时，相邻两行像素单元可以分别接收对应的数据信号。
需要说明的是，本公开的各实施例中，栅极驱动电路20不局限于图9中描述的级联方式，可以为任意适用的级联方式。当级联方式或时钟信号改变时，第一至第四级移位寄存器单元A1-A4的第一扫描信号输出端OT1的输出信号OT1<1>、OT1<2>、OT1<3>和OT1<4>在显示时段内的波形重叠部分也会相应变化，第一至第四级移位寄存器单元A1-A4的第二扫描信号输出端OT2的输出信号OT2<1>、OT2<2>、OT2<3>和OT2<4>在显示时段内的波形重叠部分也会相应变化，例如重叠33％或0％(即不重叠)，以满足多种应用需求。
例如，如图7所示，由于第七级移位寄存器单元的第一扫描信号输出端OT1输出的信号的波形和第八级移位寄存器单元的第一扫描信号输出端OT1输出的信号的波形有重叠，由此，在第一阶段1，在对第七级移位寄存器单元的第二节点H进行充电的过程中，第八级移位寄存器单元的充电子电路210中的第一晶体管M1也导通，当第六级移位寄存器单元的移位信号输出端CR输出高电平信号时，第六级移位寄存器单元的移位信号输出端CR输出高电平信号被写入第八级移位寄存器单元的第二节点H，以将第八级移位寄存器单元的第二节点H拉高至高电平。在检测控制信号OE为低电平时，第七级移位寄存器单元的第二节点H和第八级移位寄存器单元的第二节点H的电位可以能够一直保持至消隐时段BL。
例如，如图4B和图7所示，在消隐时段BL的第5阶段，第一时钟信号CLKA为高电平信号，由于第七级移位寄存器单元的第二节点H和第八级移位寄存器单元的第二节点H均为高电平，第七级移位寄存器单元和第八级移位寄存器单元中的第一补偿晶体管M15导通，从而可以实现对第七级移位寄存器单元的第二节点H和第八级移位寄存器单元的第二节点H的电平进行补偿。
例如，在消隐时段BL的第5阶段，第一时钟信号CLKA为高电平信号，从而所有级移位寄存器单元的第二晶体管M2导通，由于第七级移位寄存器单元的第二节点H和第八级移位寄存器单元的第二节点H均为高电平(此时，第二节点H的电平已经被补偿)，由此，第七级移位寄存器单元的第一节点Q和第八级移位寄存器单元的第一节点Q被充电至高电平。
例如，在消隐时段BL的第6阶段，与第七级移位寄存器单元连接的第三时钟信号CLK_3(用于提供第一输出时钟信号CLKD)提供高电平信号，与第七级移位寄存器单元连接的第七时钟信号线CLK_7(用于提供第二输出时钟信号CLKE)提供脉冲信号，由此，第七级移位寄存器单元的第一扫描信号输出端OT1输出高电平信号，第七级移位寄存器单元的第二扫描信号输出端OT2输出脉冲信号。由此，在第M帧时段内，可以实现对第七行像素单元进行检测。
而与第八级移位寄存器单元连接的第四时钟信号线CLK_4(用于提供第一输出时钟信号CLKD)提供低电平信号，与第八级移位寄存器单元连接的第八时钟信号线CLK_8(用于提供第二输出时钟信号CLKE)也提供低电平信号，由此第八级移位寄存器单元的第一扫描信号输出端OT1和第二扫描信号输出端OT2均输出低电平信号。由此，在第M帧时段内，不会对第八行像素单元(其与第八级移位寄存器单元对应)进行检测。
需要说明的是，在进行随机检测补偿时，若需要对第W行像素单元进行检测，第W行像素单元对应第W级移位寄存器单元，则每级移位寄存器单元的检测控制信号可以根据输入至第W级移位寄存器单元的第二输入信号而变化，以保证第W级移位寄存器单元的第一晶体管M1导通时，传输至第W级移位寄存器单元的第二输入信号为高电平信号，W为正整数。
例如，显示时段DS和消隐时段BL中其他阶段的相关描述可以参考上述移位寄存器单元中对显示时段DS和消隐时段BL中其他阶段的详细说明，重复之处在此不再赘述。
图8为本公开一些实施例提供的一种显示装置的示意框图。例如，如图8所示，显示装置30包括栅极驱动电路20，该栅极驱动电路20为本公开任一实施例所述的栅极驱动电路。
例如，显示装置30可以为液晶面板、液晶电视、显示器、OLED面板、OLED电视、电子纸显示装置、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。本公开的实施例对此不作限制。显示装置30的技术效果可以参考上述实施例中关于移位寄存器单元10和栅极驱动电路20的相应描述，这里不再赘述。
例如，在一个示例中，显示装置30包括显示面板3000、栅极驱动电路20、定时控制器3020和数据驱动电路3030。显示面板3000包括多个像素单元P，多个像素单元P由多条栅线GL和多条数据线DL交叉限定。栅极驱动电路20用于驱动多条栅线GL；数据驱动电路3030用于驱动多条数据线DL；定时控制器3020用于处理从显示装置30外部输入的图像数据RGB，然后向数据驱动电路3030提供处理后的图像数据RGB，定时控制器3020还用于分别向栅极驱动电路20和数据驱动电路3030输出扫描控制信号GCS和数据控制信号DCS，以用于对栅极驱动电路20和数据驱动电路3030进行控制。
例如，栅极驱动电路20中的多个移位寄存器单元10的第一扫描信号输出端OT1与多条栅线GL对应连接。栅极驱动电路20中的各级移位寄存器单元10的第一扫描信号输出端OT1依序输出扫描驱动信号到多条栅线GL，以使显示面板3000中的多行像素单元P在显示时段实现逐行扫描，在消隐时段，多个移位寄存器单元10中的随机选择的一个移位寄存器单元的第一扫描信号输出端OT1输出扫描驱动信号到对应的栅线GL，以实现随机补偿检测。
例如，栅极驱动电路20可以实现为半导体芯片，也可以集成在显示面板3000中以构成GOA电路。
例如，数据驱动电路3030向多条数据线DL提供转换的数据信号。例如，数据驱动电路3030可以实现为半导体芯片。
例如，定时控制器3020对外部输入的图像数据RGB进行处理以匹配显示面板3000的大小和分辨率，然后向数据驱动电路3030提供处理后的图像数据。定时控制器3020使用从显示装置30外部输入的同步信号(例如点时钟DCLK、数据使能信号DE、水平同步信号Hsync以及垂直同步信号Vsync)产生多个扫描控制信号GCS和多个数据控制信号DCS。
需要说明的是，显示装置30还可以包括其他部件，例如信号解码电路、电压转换电路等，这些部件例如可以采用已有的常规部件，这里不再详述。
本公开至少一实施例还提供一种移位寄存器单元的驱动方法，可以用于驱动本公开任一实施例提供的移位寄存器单元。
图9为本公开一些实施例提供的一种移位寄存器单元的驱动方法的流程图。驱动方法可以包括用于一帧的显示时段和消影时段。显示时段包括第一输入阶段和第一输出阶段，消隐时段包括第二输入阶段和第二输出阶段，
例如，如图9所示，驱动方法可以包括如下操作：
S10：在第一输入阶段，响应于第一控制信号，第一输入电路将第一输入信号写入到第一节点；
S11：在第一输出阶段，在第一节点的电平的控制下，输出电路将复合输出信号输出至输出端；
S20：在第二输入阶段，补偿电路对第二节点的电平进行补偿，以及第二输入电路响应于第二控制信号，以将第二节点的电平传输到第一节点；
S21：在第二输出阶段，输出电路在第一节点的电平的控制下，将复合输出信号输出至输出端。
例如，在一个示例中，在移位寄存器单元10包括第三控制电路的情形下，步骤S10还包括：响应于第四控制信号通过第三控制电路对第四节点的电平进行控制，以将第四节点的电平下拉至非工作电位。
例如，在一些示例中，输出端包括移位信号输出端和第一扫描信号输出端，输出电路包括第一输出晶体管和第二输出晶体管。步骤S11可以包括：在第一节点的电平的控制下，经由第一输出晶体管将显示移位信号传输至移位信号输出端，经由第二输出晶体管将显示输出信号传输至第一扫描信号输出端。复合输出信号包括显示输出信号和显示移位信号，显示输出信号和显示移位信号相同，且均为第一输出时钟信号。例如，显示输出信号可以用于驱动显示面板中的像素单元进行显示。
例如，在一些示例中，步骤S20可以包括：在第二节点的电平的控制下，将高电平的第一时钟信号写入第三节点；基于写入至第三节点的高电平的第一时钟信号对第二节点的电平进行补偿；然后响应于第二控制信号，将补偿后的第二节点的电平传输到第一节点。
例如，在另一个示例中，在移位寄存器单元10包括第二控制电路的情形 下，步骤S20还包括：响应于第三控制信号对第四节点的电平进行控制，以将第四节点的电平下拉至非工作电位。
例如，在一些示例中，步骤S21可以包括：在第一节点的电平的控制下，经由第一输出晶体管将消隐移位信号传输至移位信号输出端，经由第二输出晶体管将消隐输出信号传输至第一扫描信号输出端。复合输出信号包括消隐输出信号和消隐移位信号，消隐输出信号和消隐移位信号相同，且均为第一输出时钟信号。例如，消隐输出信号可以用于驱动显示面板中的像素单元进行外部补偿。
需要说明的是，在上述移位寄存器单元的实施例中，第一输出信号可以包括显示移位信号和消隐移位信号，第二输出信号包括显示输出信号和消隐输出信号。显示输出信号可以为在显示时段由第一扫描信号输出端输出的信号，显示移位信号可以为在显示时段由移位信号输出端输出的信号，显示移位信号和显示输出信号可以相同，显示输出信号例如可以为脉冲信号；消隐输出信号可以为在消隐时段由第一扫描信号输出端输出的信号，消隐移位信号可以为在消隐时段由移位信号输出端输出的信号，消隐移位信号和消隐输出信号也可以相同，消隐输出信号例如可以为高电平信号。
例如，在显示时段，在步骤S11之后，驱动方法还可以包括：显示复位阶段，在第一复位信号的控制下，对第一节点进行复位；在第四节点的电平的控制下，通过降噪电路对第一节点、移位信号输出端、第一扫描信号输出端和第二扫描信号输出端进行降噪。
例如，在消隐时段，在步骤S21之后，驱动方法还可以包括：消隐复位阶段，在第二复位信号和检测控制信号的控制下，对第一节点和第二节点进行复位。
需要说明的是，关于该驱动方法的详细描述以及技术效果可以参考本公开的实施例中对于移位寄存器单元10和栅极驱动电路20的相应描述，这里不再赘述。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本发明的实施例的附图中，层或结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位 于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (23)

  1. 一种移位寄存器单元，包括：第一输入电路、第二输入电路、输出电路和补偿电路，其中，
    所述第一输入电路连接第一节点，被配置为响应于第一控制信号将第一输入信号写入至所述第一节点；
    所述第二输入电路连接到所述第一节点和第二节点，被配置为响应于检测控制信号将第二输入信号输入至所述第二节点，且响应于第二控制信号将所述第二节点的电平传输到所述第一节点；
    所述补偿电路连接到所述第二节点，被配置为对所述第二节点的电平进行补偿；
    所述输出电路连接所述第一节点和输出端，且被配置为在所述第一节点的电平的控制下，将复合输出信号输出至所述输出端。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述补偿电路包括第一补偿子电路、第二补偿子电路和存储子电路，
    所述第一补偿子电路分别连接到所述第二节点和第三节点，且被配置为在所述第二节点的电平的控制下，将第一时钟信号写入所述第三节点；
    所述存储子电路分别连接到所述第二节点和所述第三节点，且被配置为基于写入至所述第三节点的所述第一时钟信号对所述第二节点的电平进行补偿；
    所述第二补偿子电路连接到所述第三节点，且被配置为在补偿降噪信号的控制下，对所述第三节点进行降噪。
  3. 根据权利要求2所述的移位寄存器单元，其中，所述第二补偿子电路还连接到第四节点，以接收所述第四节点的电压作为所述补偿降噪信号。
  4. 根据权利要求3所述的移位寄存器单元，其中，所述第一补偿子电路包括第一补偿晶体管，所述第二补偿子电路包括第二补偿晶体管，所述存储子电路包括第一电容，
    所述第一补偿晶体管的第一极连接到第一时钟信号端以接收所述第一时钟信号，所述第一补偿晶体管的第二极连接到所述第三节点，所述第一补偿晶体管的栅极连接到所述第二节点，
    所述第一电容的第一端连接到所述第二节点，所述第一电容的第二端连接到所述第三节点，
    所述第二补偿晶体管的第一极连接到所述第三节点，所述第二补偿晶体管的第二极连接到第一电压端，所述第二补偿晶体管的栅极连接到所述第四节点。
  5. 根据权利要求2-4任一项所述的移位寄存器单元，其中，所述第一时钟信号和所述第二控制信号相同。
  6. 根据权利要求1-5任一项所述的移位寄存器单元，其中，所述第二输入电路包括充电子电路和隔离子电路，
    所述充电子电路被配置为响应于所述检测控制信号，将所述第二输入信号输入至所述第二节点；
    所述隔离子电路分别连接所述第一节点和所述第二节点，被配置为在所述第二控制信号的控制下，将所述第二节点的电平传输到所述第一节点。
  7. 根据权利要求6所述的移位寄存器单元，其中，所述充电子电路包括第一晶体管，所述第一晶体管的栅极被配置为接收所述检测控制信号，所述第一晶体管的第一极被配置为接收所述第二输入信号，所述第一晶体管的第二极连接到所述第二节点；
    所述隔离子电路包括第二晶体管，所述第二晶体管的栅极配置为接收所述第二控制信号，所述第二晶体管的第一极连接至所述第二节点，所述第二晶体管的第一极连接至所述第一节点。
  8. 根据权利要求1-7任一项所述的移位寄存器单元，其中，所述第一输入电路包括第三晶体管，
    所述第三晶体管的栅极连接至第一控制信号端以接收所述第一控制信号，所述第三晶体管的第一极被配置为接收所述第一输入信号，所述第三晶体管的第二极与所述第一节点连接。
  9. 根据权利要求1-8任一项所述的移位寄存器单元，其中，所述输出端包括移位信号输出端和第一扫描信号输出端，
    所述输出电路包括第一输出晶体管、第二输出晶体管和第二电容；
    所述第一输出晶体管的栅极与所述第一节点连接，所述第一输出晶体管的第一极与第一输出时钟信号端连接以接收第一输出时钟信号，所述第一输出晶体管的第二极与所述移位信号输出端连接；
    所述第二输出晶体管的栅极和所述第一节点连接，所述第二输出晶体管的第一极与所述第一输出时钟信号端连接以接收所述第一输出时钟信号，所述第二输出晶体管的第二极与所述第一扫描信号输出端连接；
    所述第二电容的第一端和所述第一节点连接，所述第二电容的第二端与所述第二输出晶体管的第二极连接；
    所述第一输出时钟信号经由所述第一输出晶体管传输到所述移位信号输出端以作为第一输出信号，所述第一输出时钟信号经由所述第二输出晶体管传输到所述第一扫描信号输出端以作为第二输出信号，所述复合输出信号包括所述第一输出信号和所述第二输出信号。
  10. 根据权利要求9所述的移位寄存器单元，其中，所述输出端还包括第二扫描信号输出端，所述输出电路还包括第三输出晶体管和第三电容，
    所述第三输出晶体管的栅极与所述第一节点连接，所述第三输出晶体管的第一极与第二输出时钟信号端连接以接收第二输出时钟信号，所述第三输出晶体管的第二极与所述第二扫描信号输出端连接，
    所述第三电容的第一端和所述第一节点连接，所述第三电容的第二端与所述第三输出晶体管的第二极连接，
    所述第二输出时钟信号经由所述第三输出晶体管传输到所述第二扫描信号输出端以作为第三输出信号，所述复合输出信号还包括所述第三输出信号。
  11. 根据权利要求1、2、5-10任一项所述的移位寄存器单元，还包括：降噪电路和第一控制电路，
    其中，所述降噪电路连接所述第一节点、第四节点和所述输出端，且被配置为在所述第四节点的电平的控制下，同时对所述第一节点和所述输出端进行降噪；
    所述第一控制电路连接所述第一节点和所述第四节点，且配置为在所述第一节点的电平的控制下，对所述第四节点的电平进行控制。
  12. 根据权利要求1、2、5-10任一项所述的移位寄存器单元，还包括：第二控制电路，
    其中，所述第二控制电路连接第四节点，且被配置为响应于第三控制信号对所述第四节点的电平进行控制，所述第三控制信号包括第一时钟信号和所述第二节点的电压值。
  13. 根据权利要求1、2、5-10任一项所述的移位寄存器单元，还包括：第三控制电路，
    其中，所述第三控制电路连接第四节点，且被配置为响应于第四控制信号对所述第四节点的电平进行控制。
  14. 根据权利要求1-13任一项所述的移位寄存器单元，还包括：第一复位电路和第二复位电路，其中，
    所述第一复位电路连接所述第一节点，且被配置为响应于第一复位控制信号对所述第一节点进行复位；
    所述第二复位电路连接所述第一节点，且被配置为响应于第二复位控制信号对所述第一节点进行复位。
  15. 根据权利要求1所述的移位寄存器单元，还包括：降噪电路、第一控制电路、第二控制电路、第三控制电路、第一复位电路和第二复位电路，
    其中，所述补偿电路包括第一补偿晶体管、第二补偿晶体管和第一电容，所述第一补偿晶体管的第一极连接到第一时钟信号端以接收第一时钟信号，所述第一补偿晶体管的第二极连接到第三节点，所述第一补偿晶体管的栅极连接到所述第二节点，所述第一电容的第一端连接到所述第二节点，所述第一电容的第二端连接到所述第三节点，所述第二补偿晶体管的第一极连接到所述第三节点，所述第二补偿晶体管的第二极连接到第一电压端，所述第二补偿晶体管的栅极连接到第四节点，以接收所述第四节点的电压作为补偿降噪信号；
    所述第二输入电路包括充电子电路和隔离子电路，
    所述充电子电路包括第一晶体管，所述第一晶体管的栅极被配置为接收所述检测控制信号，所述第一晶体管的第一极被配置为接收所述第二输入信号，所述第一晶体管的第二极连接到所述第二节点，
    所述隔离子电路包括第二晶体管，所述第二晶体管的栅极配置为接收所述第二控制信号，所述第二晶体管的第一极连接至所述第二节点，所述第二晶体管的第一极连接至所述第一节点；
    所述第一输入电路包括第三晶体管，所述第三晶体管的栅极被配置为接收所述第一控制信号，所述第三晶体管的第一极被配置为接收所述第一输入信号，所述第三晶体管的第二极与所述第一节点连接；
    所述输出电路包括第一输出晶体管、第二输出晶体管、第三输出晶体管、第二电容和第三电容，所述输出端包括移位信号输出端、第一扫描信号输出端和第二扫描信号输出端，
    所述第一输出晶体管的栅极与所述第一节点连接，所述第一输出晶体管的第一极与第一输出时钟信号端连接以接收第一输出时钟信号，所述第一输出晶体管的第二极与所述移位信号输出端连接，
    所述第二输出晶体管的栅极和所述第一节点连接，所述第二输出晶体管的第一极与所述第一输出时钟信号端连接以接收所述第一输出时钟信号，所述第二输出晶体管的第二极与所述第一扫描信号输出端连接，
    所述第二电容的第一端和所述第一节点连接，所述第二电容的第二端与所述第一输出晶体管的第二极连接，
    所述第三输出晶体管的栅极与所述第一节点连接，所述第三输出晶体管的第一极与第二输出时钟信号端连接以接收第二输出时钟信号，所述第三输出晶体管的第二极与所述第二扫描信号输出端连接，
    所述第三电容的第一端和所述第一节点连接，所述第三电容的第二端与所述第三输出晶体管的第二极连接，
    所述第一输出时钟信号经由所述第一输出晶体管传输到所述移位信号输出端以作为第一输出信号，所述第一输出时钟信号经由所述第二输出晶体管传输到所述第一扫描信号输出端以作为第二输出信号，所述第二输出时钟信号经由所述第三输出晶体管传输到所述第二扫描信号输出端以作为第三输出信号，所述复合输出信号包括所述第一输出信号、所述第二输出信号和所述第三输出信号；
    所述降噪电路包括第四晶体管、第五晶体管、第六晶体管和第七晶体管，
    所述第四晶体管的栅极与所述第四节点连接，所述第四晶体管的第一极与所述第一节点连接，所述第四晶体管的第二极与所述第一电压端连接，
    所述第五晶体管的栅极与所述第四节点连接，所述第五晶体管的第一极与所述移位信号输出端连接，所述第五晶体管的第二极与所述第一电压端连接，
    所述第六晶体管的栅极与所述第四节点连接，所述第六晶体管的第一极与所述第一扫描信号输出端连接，所述第六晶体管的第二极与第二电压端连接，
    所述第七晶体管的栅极与所述第四节点连接，所述第七晶体管的第一极与所述第二扫描信号输出端连接，所述第七晶体管的第二极与所述第二电压端连接；
    所述第一控制电路包括第八晶体管和第九晶体管，
    所述第八晶体管的栅极和第一极连接且被配置为连接第三电压端，所述第八晶体管的第二极连接所述第四节点，
    所述第九晶体管的栅极连接所述第一节点，所述第九晶体管的第一极连接到所述第四节点，所述第九晶体管的第二极连接到所述第一电压端；
    所述第一复位电路包括第十晶体管，所述第十晶体管的栅极连接至第一复位控制信号端以接收第一复位控制信号，所述第十晶体管的第一极连接到所述第一节点，所述第十晶体管的第二极连接到所述第一电压端；
    所述第二复位电路包括第十一晶体管，所述第十一晶体管的栅极连接至第一复位控制信号端以接收第二复位控制信号，所述第十一晶体管的第一极连接到所述第一节点，所述第十一晶体管的第二极连接到所述第一电压端；
    所述第二控制电路包括第十二晶体管和第十三晶体管，
    所述第十二晶体管的栅极被配置为接收所述第一时钟信号，所述第十二晶体管的第一极被配置为连接所述第四节点，所述第十二晶体管的第二极连接到所述第十三晶体管的第一极，所述第十三晶体管的栅极连接到所述第二节点，所述第十三晶体管的第二极连接到所述第一电压端；
    所述第三控制电路包括第十四晶体管，所述第十四晶体管的栅极被配置为接收第四控制信号，所述第十四晶体管的第一极连接至所述第四节点，所述第十四晶体管的第二极连接所述第一电压端。
  16. 一种栅极驱动电路，包括多个移位寄存器单元，
    其中，所述多个移位寄存器单元级联，且所述多个移位寄存器单元中的每个移位寄存器单元为如权利要求1-15任一所述的移位寄存器单元。
  17. 根据权利要求16所述的栅极驱动电路，还包括第一时钟信号线、第二时钟信号线、第三时钟信号线和第四时钟信号线，
    其中，在所述移位寄存器单元包括第一输出时钟信号端的情形下，
    所述多个移位寄存器单元中的第4n 1-3级移位寄存器单元的第一输出时钟信号端与所述第一时钟信号线连接；
    所述多个移位寄存器单元中的第4n 1-2级移位寄存器单元的第一输出时钟信号端与所述第二时钟信号线连接；
    所述多个移位寄存器单元中的第4n 1-1级移位寄存器单元的第一输出时钟信号端与所述第三时钟信号线连接；
    所述多个移位寄存器单元中的第4n 1级移位寄存器单元的第一输出时钟信号端与所述第四时钟信号线连接；
    n 1为大于0的整数。
  18. 根据权利要求17所述的栅极驱动电路，还包括第五时钟信号线、第六时钟信号线、第七时钟信号线和第八时钟信号线，
    其中，在所述移位寄存器单元包括第二输出时钟信号端的情形下，
    所述第4n 1-3级移位寄存器单元的第二输出时钟信号端与所述第五时钟信号线连接；
    所述第4n 1-2级移位寄存器单元的第二输出时钟信号端与所述第六时钟信号线连接；
    所述第4n 1-1级移位寄存器单元的第二输出时钟信号端与所述第七时钟信号线连接；
    所述第4n 1级移位寄存器单元的第二输出时钟信号端与所述第八时钟信号线连接。
  19. 根据权利要求16-18任一项所述的栅极驱动电路，其中，在所述移位寄存器单元包括移位信号输出端和第一控制信号端的情形下，
    所述多个移位寄存器单元中的第n 2+3级移位寄存器单元的第一控制信号端和所述多个移位寄存器单元中的第n 2级移位寄存器单元的移位信号输出端连接，n 2为大于0的整数。
  20. 根据权利要求19所述的栅极驱动电路，其中，所述第n 2级移位寄存器单元的移位信号输出端输出的信号作为所述第n 2+2级移位寄存器单元的第二输入信号。
  21. 根据权利要求19或20所述的栅极驱动电路，其中，在所述移位寄存器单元还包括第一复位控制信号端的情形下，
    所述第n 2级移位寄存器单元的第一复位控制信号端和所述第n 2+3级移位寄存器单元的移位信号输出端连接。
  22. 一种显示装置，包括如权利要求16-21任一所述的栅极驱动电路。
  23. 一种如权利要求1-15任一所述的移位寄存器单元的驱动方法，其中，一帧包括显示时段和消隐时段，所述显示时段包括第一输入阶段和第一输出阶段，所述消隐时段包括第二输入阶段和第二输出阶段，
    所述驱动方法包括：
    在所述第一输入阶段，响应于所述第一控制信号，所述第一输入电路将所述第一输入信号写入到所述第一节点；
    在所述第一输出阶段，在所述第一节点的电平的控制下，所述输出电路将所述复合输出信号输出至所述输出端；
    在所述第二输入阶段，所述补偿电路对所述第二节点的电平进行补偿，以 及所述第二输入电路响应于所述第二控制信号，以将所述第二节点的电平传输到所述第一节点；
    在所述第二输出阶段，所述输出电路在所述第一节点的电平的控制下，将所述复合输出信号输出至所述输出端。
PCT/CN2020/070866 2019-02-25 2020-01-08 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置 WO2020173229A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP20763467.6A EP3933817A4 (en) 2019-02-25 2020-01-08 SLIDER REGISTER UNIT AND DRIVE METHOD THEREOF, GATE DRIVE CIRCUIT AND DISPLAY DEVICE
US16/765,565 US11328672B2 (en) 2019-02-25 2020-01-08 Shift register unit and driving method thereof, gate driving circuit, and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910138433.6A CN109658865B (zh) 2019-02-25 2019-02-25 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN201910138433.6 2019-02-25

Publications (1)

Publication Number Publication Date
WO2020173229A1 true WO2020173229A1 (zh) 2020-09-03

Family

ID=66123651

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/070866 WO2020173229A1 (zh) 2019-02-25 2020-01-08 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置

Country Status (4)

Country Link
US (1) US11328672B2 (zh)
EP (1) EP3933817A4 (zh)
CN (1) CN109658865B (zh)
WO (1) WO2020173229A1 (zh)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109658865B (zh) * 2019-02-25 2021-01-05 合肥京东方卓印科技有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN110136653B (zh) 2019-05-29 2022-05-13 合肥京东方卓印科技有限公司 移位寄存器、栅极驱动电路及显示装置
CN112133355B (zh) 2019-06-25 2023-08-04 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置和控制方法
TWI728698B (zh) * 2020-02-14 2021-05-21 友達光電股份有限公司 液晶顯示器(lcd)驅動電路
CN111243547B (zh) * 2020-03-18 2021-06-01 Tcl华星光电技术有限公司 Goa电路及显示面板
CN111402829B (zh) * 2020-04-10 2021-07-27 苏州华星光电技术有限公司 Goa电路、显示面板
CN111445851B (zh) * 2020-04-30 2021-10-08 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN112017585B (zh) * 2020-09-21 2023-12-22 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
KR20220094916A (ko) * 2020-12-29 2022-07-06 엘지디스플레이 주식회사 게이트 구동 회로 및 이를 이용한 전계 발광 표시 장치
CN112687227A (zh) 2021-01-08 2021-04-20 厦门天马微电子有限公司 显示面板和显示装置
GB2609795A (en) * 2021-03-18 2023-02-15 Boe Technology Group Co Ltd Shift register unit and drive method therefor, gate driver circuit, and display panel
CN113920937B (zh) * 2021-07-09 2022-09-09 北京京东方技术开发有限公司 显示基板及显示装置
CN113593465B (zh) * 2021-08-06 2023-12-12 北京京东方显示技术有限公司 电压补偿模块、栅极驱动电路及其驱动方法、显示基板
KR20230040221A (ko) * 2021-09-15 2023-03-22 에스케이하이닉스 주식회사 쉬프트레지스터 및 쉬프트레지스터를 포함하는 전자장치
CN114078457B (zh) * 2021-11-26 2024-03-08 京东方科技集团股份有限公司 栅极驱动电路以及显示装置
CN114220391B (zh) * 2022-01-04 2023-03-31 格兰菲智能科技有限公司 像素驱动电路、驱动方法及显示装置
WO2023225847A1 (zh) * 2022-05-24 2023-11-30 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路和栅极驱动方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160232852A1 (en) * 2015-02-06 2016-08-11 Samsung Display Co., Ltd. Display device and method for driving display device
CN108648716A (zh) * 2018-07-25 2018-10-12 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN108735142A (zh) * 2018-08-15 2018-11-02 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路
CN109192171A (zh) * 2018-10-24 2019-01-11 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、栅极驱动电路、显示装置
CN109658865A (zh) * 2019-02-25 2019-04-19 合肥京东方卓印科技有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101324410B1 (ko) * 2009-12-30 2013-11-01 엘지디스플레이 주식회사 쉬프트 레지스터와 이를 이용한 표시장치
CN104332144B (zh) * 2014-11-05 2017-04-12 深圳市华星光电技术有限公司 液晶显示面板及其栅极驱动电路
CN104900268B (zh) * 2015-06-30 2018-10-30 上海天马有机发光显示技术有限公司 移位寄存器及其驱动方法、栅极驱动电路、显示装置
KR102560314B1 (ko) * 2015-12-29 2023-07-28 삼성디스플레이 주식회사 스캔 드라이버 및 이를 포함하는 표시 장치
KR102338948B1 (ko) * 2017-05-22 2021-12-14 엘지디스플레이 주식회사 게이트 쉬프트 레지스터와 이를 포함한 유기발광 표시장치
CN107507556B (zh) * 2017-09-30 2020-06-12 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、栅极驱动电路以及显示装置
CN108154835B (zh) * 2018-01-02 2020-12-25 京东方科技集团股份有限公司 移位寄存器单元、其驱动方法、栅极驱动电路及显示装置
CN108682398B (zh) * 2018-08-08 2020-05-29 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置及驱动方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160232852A1 (en) * 2015-02-06 2016-08-11 Samsung Display Co., Ltd. Display device and method for driving display device
CN108648716A (zh) * 2018-07-25 2018-10-12 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN108735142A (zh) * 2018-08-15 2018-11-02 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路
CN109192171A (zh) * 2018-10-24 2019-01-11 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、栅极驱动电路、显示装置
CN109658865A (zh) * 2019-02-25 2019-04-19 合肥京东方卓印科技有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3933817A4

Also Published As

Publication number Publication date
US11328672B2 (en) 2022-05-10
CN109658865A (zh) 2019-04-19
CN109658865B (zh) 2021-01-05
US20210201806A1 (en) 2021-07-01
EP3933817A1 (en) 2022-01-05
EP3933817A4 (en) 2022-11-09

Similar Documents

Publication Publication Date Title
WO2020173229A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
JP7366753B2 (ja) シフトレジスタユニットおよびその駆動方法、ゲート駆動回路および表示装置
JP7315469B2 (ja) シフトレジスタユニットおよびその駆動方法、ゲート駆動回路および表示装置
US11749158B2 (en) Shift register unit, gate driving circuit, display device, and driving method
US11081058B2 (en) Shift register unit, gate drive circuit, display device and driving method
CN109935185B (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
US11176871B2 (en) Shift register unit and driving method thereof, gate driving circuit and display device
US11087855B2 (en) Shift register unit and driving method, gate drive circuit and display device
US11127478B2 (en) Shift register unit and driving method thereof, gate driving circuit, and display device
WO2017059792A1 (zh) 移位寄存器单元、栅线驱动装置以及驱动方法
WO2020007054A1 (zh) 移位寄存器单元、栅极驱动电路及其驱动方法、显示装置
WO2019242317A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
WO2020140292A1 (zh) 移位寄存器单元及驱动方法、栅极驱动电路、显示装置
US11610524B2 (en) Shift register unit and driving method thereof, gate drive circuit and display device
WO2020168887A1 (zh) 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
WO2020097816A1 (zh) 移位寄存器单元及驱动方法、栅极驱动电路、显示装置
WO2022222408A1 (zh) 移位寄存器及其驱动方法、栅极驱动电路、显示装置
WO2020187043A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
WO2021081703A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20763467

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2020763467

Country of ref document: EP

Effective date: 20210927