WO2019242317A1 - 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置 - Google Patents

移位寄存器单元及其驱动方法、栅极驱动电路及显示装置 Download PDF

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Publication number
WO2019242317A1
WO2019242317A1 PCT/CN2019/075397 CN2019075397W WO2019242317A1 WO 2019242317 A1 WO2019242317 A1 WO 2019242317A1 CN 2019075397 W CN2019075397 W CN 2019075397W WO 2019242317 A1 WO2019242317 A1 WO 2019242317A1
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Prior art keywords
transistor
node
reset
pole
circuit
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PCT/CN2019/075397
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English (en)
French (fr)
Inventor
谢勇贤
邹宜峰
王慧
郑敏栋
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US16/491,910 priority Critical patent/US11335293B2/en
Publication of WO2019242317A1 publication Critical patent/WO2019242317A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance

Definitions

  • Embodiments of the present disclosure relate to a shift register unit and a driving method thereof, a gate driving circuit, and a display device.
  • a pixel array of a liquid crystal display panel generally includes a plurality of rows of grid lines and a plurality of columns of data lines interleaved therewith.
  • the gate line can be driven by a gate driving circuit.
  • the gate drive circuit can be implemented by a bonded integrated drive circuit.
  • the gate driving circuit can also be directly integrated on the thin film transistor array substrate to form a GOA (Gate-driver On Array) to perform gate line drive.
  • GOA Gate-driver On Array
  • a GOA composed of multiple cascaded shift register units can be used to provide switching voltage signals for multiple rows of gate lines of a pixel array, thereby controlling, for example, the multiple rows of gate lines to be sequentially turned on, and simultaneously from the data lines to the pixel array.
  • the pixel units of the corresponding row in the center provide data signals to form the gray voltages required for each gray level of the display image at each pixel unit, and then display a frame of image.
  • Current display panels increasingly use GOA technology to drive grid lines. GOA technology helps achieve narrow bezels and can reduce production costs.
  • At least one embodiment of the present disclosure provides a shift register unit including an input circuit, an output circuit, a first reset circuit, and a reset control circuit; wherein the input circuit is configured to perform a level adjustment on a first node in response to an input signal. Control; the output circuit is configured to output a clock signal to an output terminal under the control of the level of the first node; the first reset circuit is configured to perform a response to the first node in response to a first reset signal Reset; the reset control circuit is configured to input the first reset signal to the first reset circuit in response to a reset control signal and a reference signal to turn on the first reset circuit.
  • the reset control circuit is further configured to make the amplitude of the level of the first reset signal greater than the amplitude of the level of the reference signal.
  • the reset control circuit includes a driving sub-circuit configured to adjust a level of a reset control node according to the reset control signal and the reference signal, The level of the reset control node is used as the first reset signal; the reset sub-circuit is configured to reset the reset control node and the driving sub-circuit in response to a reset sub-signal.
  • the driving sub-circuit includes a first capacitor and a first transistor, and a first pole of the first capacitor is configured to be connected to a reset control signal terminal to receive the reset capacitor.
  • the reset control signal, the second electrode of the first capacitor is configured to be connected to a reference signal terminal to receive the reference signal, and the gate of the first transistor is configured to be connected to the first electrode of the first capacitor, A first pole of the first transistor is configured to be connected to a second pole of the first capacitor, and a second pole of the first transistor is configured to be connected to the reset control node;
  • the reset sub-circuit includes a second A transistor and a third transistor, the gate of the second transistor is configured to be connected to a reset sub-signal terminal to receive the reset sub-signal, and the first pole of the second transistor is configured to be connected to the gate of the first transistor Connected, the second pole of the second transistor is configured to be connected to a first voltage terminal to receive a first voltage, and the gate of
  • the reference signal terminal is connected to a clock signal terminal to receive the clock signal as the reference signal.
  • a shift register unit provided in an embodiment of the present disclosure includes a first control circuit, a second control circuit, a third control circuit, a fourth control circuit, a first node noise reduction circuit, and an output noise reduction circuit;
  • the first control circuit is configured to control the level of the second node under the control of the levels of the first node and the first control node;
  • the second control circuit is configured to control the level of the first node and the Control the level of the third node under the control of the level of the second control node;
  • the third control circuit is configured to control the level of the first control node under the control of the level of the first node Level control;
  • the fourth control circuit is configured to control the level of the second control node under the control of the level of the first node;
  • the first node noise reduction circuit is configured to Performing noise reduction on the first node under the control of the level of the second node or the third node;
  • the output noise reduction circuit is configured to Under the control of the output End for noise reduction.
  • the input circuit includes a fourth transistor; a gate of the fourth transistor is connected to the first electrode and is configured to be connected to an input terminal to receive the input. Signal, the second pole of the fourth transistor is configured to be connected to the first node.
  • the output terminal of the output circuit includes at least one shift signal output terminal and at least one pixel signal output terminal.
  • the output circuit includes a fifth transistor, a sixth transistor, and a second capacitor; a gate of the fifth transistor is configured to be connected to the first node A first pole of the fifth transistor is configured to be connected to a clock signal terminal to receive the clock signal, and a second pole of the fifth transistor is configured to be connected to the shift signal output terminal; the sixth transistor The gate of is configured to be connected to the first node, the first pole of the sixth transistor is configured to be connected to the clock signal terminal to receive the clock signal, and the second pole of the sixth transistor is configured to be and The pixel signal output terminal is connected; the first pole of the second capacitor is configured to be connected to the first node, and the second pole of the second capacitor is configured to be connected to the second pole of the sixth transistor or The second electrode connection of the fifth transistor is described.
  • the first reset circuit includes a seventh transistor; a gate of the seventh transistor is configured to be connected to the reset control node, and the seventh transistor A first pole of is configured to be connected to the first node, and a second pole of the seventh transistor is configured to be connected to a first voltage terminal to receive a first voltage.
  • the first control circuit includes an eighth transistor and a ninth transistor, and a gate of the eighth transistor is configured to be connected to the first control node, A first pole of the eighth transistor is configured to be connected to a second voltage terminal to receive a second voltage, a second pole of the eighth transistor is configured to be connected to the second node, and a gate of the ninth transistor Configured to be connected to the first node, a first pole of the ninth transistor is configured to be connected to the second node, and a second pole of the ninth transistor is configured to be connected to a first voltage terminal to receive the first Voltage;
  • the second control circuit includes a tenth transistor and an eleventh transistor, a gate of the tenth transistor is configured to be connected to the second control node, and a first pole of the tenth transistor is configured to be connected to the first The three voltage terminals are connected to receive a third voltage, the second pole of the tenth transistor is configured to be connected to the third node, the gate of
  • the third control circuit includes a twelfth transistor and a thirteenth transistor, and a gate of the twelfth transistor is connected to the first electrode and is configured to Connected to a second voltage terminal to receive a second voltage, a second pole of the twelfth transistor is configured to be connected to the first control node, and a gate of the thirteenth transistor is configured to be connected to the first node Connected, the first pole of the thirteenth transistor is configured to be connected to the first control node, and the second pole of the thirteenth transistor is configured to be connected to a first voltage terminal to receive a first voltage;
  • the four control circuits include a fourteenth transistor and a fifteenth transistor, a gate of the fourteenth transistor is connected to the first electrode and is configured to be connected to a third voltage terminal to receive a third voltage, and the fourteenth transistor A second pole is configured to be connected to the second control node, a gate of the fifteenth transistor is configured to be connected to
  • the first node noise reduction circuit includes a sixteenth transistor and a seventeenth transistor; a gate of the sixteenth transistor is configured to be the same as the first transistor.
  • a two-node connection a first pole of the sixteenth transistor is configured to be connected to the first node, and a second pole of the sixteenth transistor is configured to be connected to a first voltage terminal to receive a first voltage;
  • the gate of the seventeenth transistor is configured to be connected to the third node, the first pole of the seventeenth transistor is configured to be connected to the first node, and the second pole of the seventeenth transistor is configured to be and The first voltage terminal is connected.
  • the output noise reduction circuit includes an eighteenth transistor, a nineteenth transistor, a twentieth transistor, and a twenty-first transistor; the eighteenth transistor The gate of is configured to be connected to the second node, the first pole of the eighteenth transistor is configured to be connected to the shift signal output terminal, and the second pole of the eighteenth transistor is configured to be connected to the first node A voltage terminal is connected to receive the first voltage; a gate of the nineteenth transistor is configured to be connected to the third node, and a first pole of the nineteenth transistor is configured to be connected to the shift signal output terminal, The second pole of the nineteenth transistor is configured to be connected to the first voltage terminal; the gate of the twentieth transistor is configured to be connected to the second node, and the first pole of the twentieth transistor is configured And the second electrode of the twentieth transistor is configured to be connected to a fourth voltage terminal to receive a fourth voltage; the gate of the twenty-first transistor is configured to be connected to the pixel signal output terminal; Third
  • a shift register unit provided in an embodiment of the present disclosure includes a second reset circuit; wherein the second reset circuit is configured to reset the first node in response to a second reset signal.
  • the second reset circuit includes a twenty-second transistor; a gate of the twenty-second transistor is configured to be connected to a second reset terminal to receive the second reset terminal.
  • the second reset signal, a first pole of the twenty-second transistor is configured to be connected to the first node, and a second pole of the twenty-second transistor is configured to be connected to a first voltage terminal to receive the first Voltage.
  • At least one embodiment of the present disclosure further provides a gate driving circuit including the shift register unit according to any one of the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure further provides a display device including the gate driving circuit according to any one of the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure also provides a method for driving a shift register unit according to any one of the embodiments of the present disclosure, including: an input stage, in which the input circuit controls the power of the first node in response to the input signal. Level to a first level, the output circuit outputs a second level of the clock signal to the output terminal; in an output stage, the output circuit outputs a third level of the clock signal to the output terminal; In a first reset stage, the reset control circuit inputs the first reset signal to the first reset circuit in response to the reset control signal and the reference signal to turn on the first reset circuit, so that the first A reset circuit resets the first node.
  • the clock signal and the reference signal are the same signal, and the input pulse and the output phase are periodic pulses.
  • the first reset phase is a DC signal.
  • FIG. 1 is a schematic block diagram of a shift register unit according to some embodiments of the present disclosure
  • FIG. 2 is a schematic block diagram of a reset control circuit of a shift register unit provided by some embodiments of the present disclosure
  • FIG. 3 is a schematic block diagram of another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 4 is a schematic block diagram of another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 5 is a schematic block diagram of another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 6 is a circuit diagram of a specific implementation example of the shift register unit shown in FIG. 4;
  • FIG. 7 is a circuit diagram of a specific implementation example of the shift register unit shown in FIG. 5;
  • 8A is a signal timing diagram of a shift register unit provided by some embodiments of the present disclosure.
  • 8B is a timing diagram of a reset control node of a shift register unit provided by some embodiments of the present disclosure.
  • FIG. 9 is a schematic block diagram of a gate driving circuit according to some embodiments of the present disclosure.
  • FIG. 10 is a signal timing diagram of a gate driving circuit provided by some embodiments of the present disclosure.
  • FIG. 11 is a schematic block diagram of a display device provided by some embodiments of the present disclosure.
  • GOA technology has certain advantages over traditional technology of IC chip binding in reducing the manufacturing cost of display devices and improving the aesthetics of display devices.
  • the shift register unit of GOA circuit is prone to the problem of insufficient noise reduction of the pull-up node.
  • Multi-OP multiple output
  • GOA's multiple output phenomenon is the most common and serious GOA anomaly.
  • the noise transistor transistor used to reduce the noise of the pull-up node
  • Ids channel current
  • the channel current of the noise reduction transistor is reduced, and the pull-up node cannot sufficiently reduce noise.
  • the output terminal After the charge of the pull-up node is accumulated, the output terminal generates multiple outputs. This multiple output phenomenon not only affects the display of one row of pixel units corresponding to the shift register unit, but also affects the display of other rows of pixel units due to the cascading relationship of the shift register units, eventually resulting in abnormal screen display.
  • At least one embodiment of the present disclosure provides a shift register unit and a driving method thereof, a gate driving circuit, and a display device.
  • the shift register unit can sufficiently reduce noise of a first node (such as a pull-up node) and solve a problem in a low temperature environment.
  • the problem of insufficient noise reduction at the first node caused by the reduction of the channel current of the noise reduction transistor, thereby avoiding the phenomenon of multiple outputs, and ensuring the normal operation of the product.
  • At least one embodiment of the present disclosure provides a shift register unit including an input circuit, an output circuit, a first reset circuit, and a reset control circuit.
  • the input circuit is configured to control the level of the first node in response to the input signal;
  • the output circuit is configured to output a clock signal to the output terminal under the control of the level of the first node;
  • the first reset circuit is configured to respond to the first signal A reset signal resets the first node;
  • the reset control circuit is configured to input a first reset signal to the first reset circuit in response to the reset control signal and the reference signal to turn on the first reset circuit.
  • FIG. 1 is a schematic block diagram of a shift register unit according to some embodiments of the present disclosure.
  • the shift register unit 10 includes an input circuit 100, an output circuit 200, a first reset circuit 300, and a reset control circuit 400.
  • the pull-up node PU is an example of the first node.
  • the following description uses the first node as a pull-up node PU as an example, but this does not constitute an implementation of the present disclosure. Case restrictions.
  • the input circuit 100 is configured to control the level of the pull-up node PU of the shift register unit 10 in response to an input signal. For example, in one example, an input signal is written to a pull-up node PU and charges the pull-up node PU to raise the level of the pull-up node PU.
  • the input circuit 100 is connected to the input terminal INT, and is configured to electrically connect the pull-up node PU to the input terminal INT under the control of the input signal provided by the input terminal INT, so that the high level of the input signal can be connected to the pull-up node PU. Charging causes the level of the pull-up node PU to change (eg, rise) to control the output circuit 200 to be turned on.
  • the input circuit 100 may also be connected to a high voltage terminal provided separately, and configured to connect the pull-up node PU to the high voltage terminal under the control of an input signal provided by the input terminal INT. It is electrically connected, so that the high-level signal output from the high-voltage terminal can charge the pull-up node PU.
  • the output circuit 200 is configured to output a clock signal CLK to the output terminal OT of the shift register unit 10 under the control of the level of the pull-up node PU as an output signal of the shift register unit 10 to drive, for example, the The grid line of the display panel connected to the output terminal OT.
  • the output circuit 200 is connected to the clock signal terminal CLK, the pull-up node PU and the output terminal OT, and is configured to be turned on under the control of the level of the pull-up node PU, so that the clock signal terminal CLK and the output terminal OT are electrically connected, so that The clock signal provided by the clock signal terminal CLK can be output to the output terminal OT.
  • the first reset circuit 300 is configured to reset the pull-up node PU in response to the first reset signal Re1.
  • the first reset circuit 300 is connected to the pull-up node PU and the reset control node H, and is configured to electrically connect the pull-up node PU to a low voltage terminal provided additionally under the control of the level of the reset control node H, so as to Pull the node PU to reset.
  • the level of the reset control node H is used as the first reset signal Re1 to control whether the first reset circuit 300 is turned on or not.
  • the first reset circuit 300 may reset the pull-up node PU before and after the start of one frame of image scanning, or may reset the pull-up node PU only after the end of one frame of image scanning.
  • the reset control circuit 400 is configured to input a first reset signal Re1 to the first reset circuit 300 in response to a reset control signal and a reference signal to turn on the first reset circuit 300.
  • the reset control circuit 400 is connected to the reset control signal terminal Con, the reference signal terminal Stan, and the reset control node H, and is configured to control the reference signal provided by the reference signal terminal Stan under the control of the reset control signal provided by the reset control signal terminal Con.
  • the amplitude is adjusted, and the adjusted signal is provided to the reset control node H, and the level of the reset control node H is used as the first reset signal Re1 to control the first reset circuit 300 to be turned on.
  • the reset control circuit 400 is also configured so that the amplitude of the level of the first reset signal Re1 is greater than the amplitude of the level of the reference signal.
  • the reset control circuit 400 pulls up the amplitude of the reference signal and provides it to the reset control node H, and the first reset circuit 300 is turned on by the high level of the reset control node H.
  • the level of the reset control node H (the level of the first reset signal Re1) is higher than the level of the reference signal, so that compared with a case where the reference signal is directly applied to the first reset circuit 300 to control it,
  • the first reset circuit 300 can be fully turned on to sufficiently reduce the noise of the pull-up node PU (reset), thereby solving the problem of insufficient noise reduction of the pull-up node PU caused by the reduction of the channel current of the noise transistor in the low temperature environment, and avoiding GOA Produce multiple output phenomenon to ensure the normal operation of the product.
  • the embodiments of the present disclosure are not limited to this.
  • the first reset circuit 300 is turned on under the action of a low level (the low level is greater than 0V).
  • the reset control circuit 400 pulls down the amplitude of the reference signal and provides it to the reset control node H.
  • the first reset circuit 300 is turned on by the low level of the reset control node H. At this time, the power of the reset control node H is reset.
  • Level (the level of the first reset signal Re1) is lower than the level of the reference signal, so that the first reset circuit 300 can be fully turned on to sufficiently reduce the noise of the pull-up node PU.
  • the reference signal terminal Stan can also be connected to the clock signal terminal CLK, so as to multiplex the clock signal into a reference signal. Only when the first reset circuit 300 needs to be turned on, the clock signal outputs a corresponding DC signal (for example, high power Level or low-level signals), this method can reduce the number of signal lines and facilitate wiring.
  • the embodiments of the present disclosure are not limited to this, and the reference signal terminal Stan may also be connected to other signal terminals and voltage terminals as long as the signals meet the requirements.
  • FIG. 2 is a schematic block diagram of a reset control circuit of a shift register unit provided by some embodiments of the present disclosure.
  • the reset control circuit 400 includes a driving sub-circuit 410 and a reset sub-circuit 420.
  • the driving sub-circuit 410 is configured to adjust (eg, charge) the level of the reset control node H according to the reset control signal and the reference signal, and use the level of the reset control node H as the first reset signal Re1.
  • the driving sub-circuit 410 is connected to the reset control signal terminal Con, the reference signal terminal Stan, and the reset control node H, and is configured to control the reference signal provided by the reference signal terminal Stan under the control of the reset control signal provided by the reset control signal terminal Con. The amplitude is adjusted, and the reset control node H is charged by using the adjusted signal.
  • the reset sub-circuit 420 is configured to reset the reset control node H and the driving sub-circuit 410 in response to a reset sub-signal.
  • the reset sub-circuit 420 is connected to the reset sub-signal terminal RST and the reset control node H, and is configured to electrically connect the reset control node H and a low voltage terminal provided additionally under the control of the reset sub-signal provided by the reset sub-signal terminal RST. Thereby, the reset control node H and the driving sub-circuit 410 are reset.
  • FIG. 3 is a schematic block diagram of another shift register unit provided by some embodiments of the present disclosure.
  • the shift register unit 10 in this embodiment further includes a first control circuit 510, a second control circuit 520, a third control circuit 610, a fourth control circuit 620, a first node noise reduction circuit 700, and an output noise reduction.
  • the other structures of the circuit 800 are basically the same as those of the shift register unit 10 shown in FIG. 1.
  • the first pull-down node PD1 is an example of the second node
  • the second pull-down node PD2 is an example of the third node
  • the second node is the first in the following.
  • the drop-down node PD1 and the third node are the second pull-down node PD2 as an example for description, but this does not constitute a limitation on the embodiment of the present disclosure.
  • the first control circuit 510 is configured to control the level of the first pull-down node PD1 under the control of the levels of the pull-up node PU and the first control node PD_CN1.
  • the first control circuit 510 is connected to the first voltage terminal VGL1, the second voltage terminal VDDo, the pull-up node PU, the first pull-down node PD1, and the first control node PD_CN1, and is configured to be at the level of the pull-up node PU.
  • the first pull-down node PD1 and the first voltage terminal VGL1 are electrically connected, so that the level of the first pull-down node PD1 is pulled down and controlled to be at a low level.
  • the first voltage terminal VGL1 is, for example, configured to maintain an input DC low-level signal, and the DC low-level is referred to as a first voltage.
  • the first control circuit 510 can electrically connect the first pull-down node PD1 and the second voltage terminal VDDo under the control of the level of the first control node PD_CN1, so that when the second voltage terminal VDDo provides a high-level signal, The first pull-down node PD1 is charged to be at a high level, and the first pull-down node PD1 is discharged when a low-level signal is provided at the second voltage terminal VDDo.
  • the second control circuit 520 is configured to control the level of the second pull-down node PD2 under the control of the levels of the pull-up node PU and the second control node PD_CN2.
  • the second control circuit 520 is connected to the first voltage terminal VGL1, the third voltage terminal VDDe, the pull-up node PU, the second pull-down node PD2, and the second control node PD_CN2, and is configured to control the level of the pull-up node PU.
  • the second pull-down node PD2 is electrically connected to the first voltage terminal VGL1 to perform pull-down control on the level of the second pull-down node PD2 to be at a low level.
  • the second control circuit 520 can electrically connect the second pull-down node PD2 and the third voltage terminal VDDe under the control of the level of the second control node PD_CN2, so that when the third voltage terminal VDDe provides a high-level signal to the first
  • the second pull-down node PD2 is charged to be at a high level, and the second pull-down node PD2 is discharged when the third voltage terminal VDDe provides a low-level signal.
  • the third control circuit 610 is configured to control the level of the first control node PD_CN1 under the control of the level of the pull-up node PU.
  • the third control circuit 610 is connected to the first voltage terminal VGL1, the second voltage terminal VDDo, the pull-up node PU, and the first control node PD_CN1, and is configured to make the first control node under the control of the level of the pull-up node PU.
  • PD_CN1 is electrically connected to the first voltage terminal VGL1, so as to pull down the level of the first control node PD_CN1 to make it at a low level.
  • the third control circuit 610 can make the first control node PD_CN1 at a high level when the second voltage terminal VDDo provides a high level signal.
  • the fourth control circuit 620 is configured to control the level of the second control node PD_CN2 under the control of the level of the pull-up node PU.
  • the fourth control circuit 620 is connected to the first voltage terminal VGL1, the third voltage terminal VDDe, the pull-up node PU, and the second control node PD_CN2, and is configured to make the second control node under the control of the level of the pull-up node PU.
  • PD_CN2 is electrically connected to the first voltage terminal VGL1, so as to pull down the level of the second control node PD_CN2 to make it at a low level.
  • the fourth control circuit 620 may cause the second control node PD_CN2 to be at a high level when the third voltage terminal VDDe provides a high-level signal.
  • the first node noise reduction circuit 700 is configured to perform noise reduction on the pull-up node PU under the control of the level of the first pull-down node PD1 or the second pull-down node PD2.
  • the first node noise reduction circuit 700 is connected to the first voltage terminal VGL1, the pull-up node PU, the first pull-down node PD1, and the second pull-down node PD2, and is configured to be at the first pull-down node PD1 or the second pull-down node PD2.
  • the pull-up node PU is electrically connected to the first voltage terminal VGL1, thereby performing pull-down noise reduction on the pull-up node PU.
  • the output noise reduction circuit 800 is configured to perform noise reduction on the output terminal OT under the control of the level of the first pull-down node PD1 or the second pull-down node PD2.
  • the output noise reduction circuit 800 is connected to the first voltage terminal VGL1, the output terminal OT, the first pull-down node PD1, and the second pull-down node PD2, and is configured to be at the level of the first pull-down node PD1 or the second pull-down node PD2.
  • the output terminal OT and the first voltage terminal VGL1 are electrically connected, so that the output terminal OT is pulled down to reduce noise.
  • the second voltage terminal VDDo and the third voltage terminal VDDe are configured to alternately provide a DC high-level signal.
  • the third control circuit 610, the fourth control circuit 620, and the first control circuit The functions of 510 and the second control circuit 520 make the first pull-down node PD1 and the second pull-down node PD2 alternately high, thereby controlling the first node noise reduction circuit 700 and the output noise reduction circuit 800 to the pull-up node PU, respectively. Noise reduction with output OT.
  • the first pull-down node PD1 is at a high level; when the third voltage terminal VDDe provides a high-level signal At this time, the second voltage terminal VDDo provides a low-level signal, and at this time, the second pull-down node PD2 is high-level.
  • a signal provided by the second voltage terminal VDDo is referred to as a second voltage
  • a signal provided by the third voltage terminal VDDe is referred to as a third voltage.
  • FIG. 4 is a schematic block diagram of another shift register unit provided by some embodiments of the present disclosure.
  • the shift register unit 10 in this embodiment further includes a second reset circuit 900, and other structures are basically the same as those of the shift register unit 10 shown in FIG. 3.
  • the second reset circuit 900 is configured to reset the pull-up node PU in response to a second reset signal.
  • the second reset circuit 900 is connected to the pull-up node PU, the second reset signal terminal Re2, and the first voltage terminal VGL1, and is configured to enable the pull-up node under the control of the second reset signal provided by the second reset signal terminal Re2.
  • the PU is electrically connected to the first voltage terminal VGL1, thereby resetting the pull-up node PU.
  • the second reset circuit 900 resets the pull-up node PU after the output of the shift register unit 10 is completed.
  • FIG. 5 is a schematic block diagram of another shift register unit provided by some embodiments of the present disclosure.
  • the shift register unit 10 in this embodiment includes a fifth control circuit 500 and a sixth control circuit 600, and correspondingly includes a fourth node. PD and third control node PD_CN.
  • the sixth control circuit 600 is connected to the power supply voltage terminal VDD.
  • the power supply voltage terminal VDD is configured to keep a DC high-level signal input. This DC high-level is referred to as a power supply voltage.
  • the following embodiments are the same, and will not be described again.
  • the first node noise reduction circuit 700 and the output noise reduction circuit 800 perform noise reduction on the pull-up node PU and the output terminal OT under the control of the level of the fourth node PD, respectively.
  • the circuit structure of the shift register unit 10 is simple, easy to process, and beneficial to achieving a narrow frame.
  • the other structures of the shift register unit 10 are basically the same as those of the shift register unit 10 shown in FIG. 4, and are not repeated here.
  • the shift register unit 10 may be obtained by a combination of the reset control circuit 400 and a general shift register unit of any structure, and is not limited to the above structure.
  • the reset control circuit 400 can make the amplitude of the level of the first reset signal Re1 greater than the amplitude of the level of the reference signal, make the first reset circuit 300 fully conductive, and thereby sufficiently reduce noise (reset) the pull-up node PU to Avoid multiple outputs.
  • FIG. 6 is a circuit diagram of a specific implementation example of the shift register unit shown in FIG. 4.
  • each transistor is described as an N-type transistor, but this does not constitute a limitation on the embodiments of the present disclosure.
  • the shift register unit 10 includes first to twenty-second transistors T1-T22, and further includes first to third capacitors C1-C3.
  • the reset control circuit 400 includes a driving sub-circuit 410 and a reset sub-circuit 420.
  • the driving sub-circuit 410 may be implemented as a first capacitor C1 and a first transistor T1.
  • a first pole of the first capacitor C1 is configured to be connected to the reset control signal terminal Con to receive a reset control signal
  • a second pole of the first capacitor C1 is configured to be connected to a reference signal terminal Stan to receive a reference signal.
  • the gate of the first transistor T1 is configured to be connected to the first pole of the first capacitor C1
  • the first pole of the first transistor T1 is configured to be connected to the second pole of the first capacitor C1
  • the second pole of the first transistor T1 is arranged Connected to reset control node H.
  • the reset sub-circuit 420 may be implemented as a second transistor T2 and a third transistor T3.
  • the gate of the second transistor T2 is configured to be connected to the reset sub-signal terminal RST to receive the reset sub-signal.
  • the first pole of the second transistor T2 is configured to be connected to the gate of the first transistor T1 and the second pole of the second transistor T2. It is configured to be connected to the first voltage terminal VGL1 to receive the first voltage.
  • the gate of the third transistor T3 is configured to be connected to the reset sub-signal terminal RST to receive the reset sub-signal, the first pole of the third transistor T3 is configured to be connected to the reset control node H, and the second pole of the third transistor T3 is configured to be and The first voltage terminal VGL1 is connected.
  • the reset control signal provided by the reset control signal terminal Con changes from an inactive level that turns off the first transistor T1 to an effective level that turns on the first transistor T1 (for example, from a low level to a high level), because the bootstrapping effect of the first capacitor C1, the level of the second pole of the first capacitor C1 will be further raised and higher than the high level of the reference signal of the reference signal terminal Stan, and this raised level is called the operation Level.
  • the first transistor T1 is turned on by the high level of the reset control signal, and the working level of the second pole of the first capacitor C1 charges the reset control node H so that the level of the reset control node H also reaches the working level.
  • the reference signal terminal Stan can be connected to any signal terminal and voltage terminal.
  • the reset sub-signal provided by the reset sub-signal terminal RST is an active level (for example, high level)
  • the second transistor T2 and the third transistor T3 are both turned on, thereby respectively resetting the gate of the first transistor T1 and the reset control node. H to reset.
  • the reset control circuit 400 may also be implemented as other circuit structures, and may further include more circuit elements, which are not limited in the embodiments of the present disclosure.
  • the reset control circuit 400 further includes a third capacitor C3, a first pole of the third capacitor C3 is configured to be connected to a gate of the first transistor T1, The two poles are configured to be connected to the first voltage terminal VGL1.
  • the third capacitor C3 can improve the isolation between the gate of the first transistor T1 and the first voltage terminal VGL1, and is beneficial to better control the gate voltage of the first transistor T1.
  • the input circuit 100 may be implemented as a fourth transistor T4.
  • the gate of the fourth transistor T4 is connected to the first electrode and is configured to be connected to the input terminal INT to receive an input signal.
  • the second electrode of the fourth transistor T4 is configured to be connected to the pull-up node PU.
  • the fourth transistor T4 When the input signal at the input terminal INT is an active level (for example, a high level), the fourth transistor T4 is turned on, and the input signal charges the pull-up node PU so that it is at a high level.
  • the output terminal OT of the output circuit 200 includes at least one shift signal output terminal OC and at least one pixel signal output terminal OP to improve the driving capability of the shift register unit 10.
  • the shift signal output terminal OC is used to provide input signals for other cascaded shift register units 10, and the pixel signal output terminal OP is used to provide driving signals for the pixel circuit.
  • the output signals of the shift signal output terminal OC and the pixel signal output terminal OP are the same.
  • the output circuit 200 may be implemented as a fifth transistor T5, a sixth transistor T6, and a second capacitor C2.
  • the gate of the fifth transistor T5 is configured to be connected to the pull-up node PU.
  • the first pole of the fifth transistor T5 is configured to be connected to the clock signal terminal CLK to receive a clock signal.
  • the second pole of the fifth transistor T5 is configured to be shifted.
  • the signal output terminal OC is connected.
  • the gate of the sixth transistor T6 is configured to be connected to a pull-up node PU.
  • the first pole of the sixth transistor T6 is configured to be connected to a clock signal terminal CLK to receive a clock signal.
  • the second pole of the sixth transistor T6 is configured to be connected to a pixel signal. Output OP connected.
  • the first pole of the second capacitor C2 is configured to be connected to the pull-up node PU, and the second pole of the second capacitor C2 is configured to be connected to the second pole of the sixth transistor T6.
  • the embodiment of the present disclosure is not limited thereto.
  • the second pole of the second capacitor C2 may also be connected to the second pole of the fifth transistor T5.
  • the first reset circuit 300 may be implemented as a seventh transistor T7.
  • the gate of the seventh transistor T7 is configured to be connected to the reset control node H
  • the first pole of the seventh transistor T7 is configured to be connected to the pull-up node PU
  • the second pole of the seventh transistor T7 is configured to be connected to the first voltage terminal VGL1 .
  • the channel current Ids k (Vg-Vth) 2 of the seventh transistor T7, where Vg is the gate voltage of the seventh transistor T7, and Vth is the threshold voltage (about 0V) of the seventh transistor T7. Therefore, the channel current Ids is approximately proportional to the square of the gate voltage Vg. Because the working level of the reset control node H is higher than the high level of the reference signal at the reference signal terminal Stan, that is, the working level of the reset control node H is higher than the levels of other high level signals in the shift register unit 10, Therefore, the gate voltage Vg of the seventh transistor T7 is increased, and the channel current Ids is correspondingly increased.
  • the seventh transistor T7 can be fully turned on to sufficiently reduce the noise of the pull-up node PU (reset), thereby solving the insufficient noise reduction of the pull-up node PU caused by the decrease of the channel current of the low-temperature environment noise-reducing transistor (the seventh transistor T7). To avoid the problem of multiple output and ensure the normal operation of the product.
  • the first control circuit 510 may be implemented as an eighth transistor T8 and a ninth transistor T9.
  • the gate of the eighth transistor T8 is configured to be connected to the first control node PD_CN1, the first pole of the eighth transistor is configured to be connected to the second voltage terminal VDDo, and the second pole of the eighth transistor T8 is configured to be connected to the first pull-down node PD1 is connected.
  • the gate of the ninth transistor T9 is configured to be connected to the pull-up node PU, the first pole of the ninth transistor T9 is configured to be connected to the first pull-down node PD1, and the second pole of the ninth transistor T9 is configured to be connected to the first voltage terminal VGL1 connection.
  • the second control circuit 520 may be implemented as a tenth transistor T10 and an eleventh transistor T11.
  • the gate of the tenth transistor T10 is configured to be connected to the second control node PD_CN2, the first pole of the tenth transistor T10 is configured to be connected to the third voltage terminal VDDe, and the second pole of the tenth transistor T10 is configured to be connected to the second pull-down node PD2 connection.
  • the gate of the eleventh transistor T11 is configured to be connected to the pull-up node PU, the first pole of the eleventh transistor T11 is configured to be connected to the second pull-down node PD2, and the second pole of the eleventh transistor T11 is configured to be connected to the first The voltage terminal VGL1 is connected.
  • the third control circuit 610 may be implemented as a twelfth transistor T12 and a thirteenth transistor T13.
  • the gate of the twelfth transistor T12 is connected to the first electrode and is configured to be connected to the second voltage terminal VDDo, and the second electrode of the twelfth transistor T12 is configured to be connected to the first control node PD_CN1.
  • the gate of the thirteenth transistor T13 is configured to be connected to the pull-up node PU, the first pole of the thirteenth transistor T13 is configured to be connected to the first control node PD_CN1, and the second pole of the thirteenth transistor T13 is configured to be connected to the first The voltage terminal VGL1 is connected.
  • the fourth control circuit 620 may be implemented as a fourteenth transistor T14 and a fifteenth transistor T15.
  • the gate of the fourteenth transistor T14 is connected to the first electrode and is configured to be connected to the third voltage terminal VDDe.
  • the second electrode of the fourteenth transistor T14 is configured to be connected to the second control node PD_CN2.
  • the gate is configured to be connected to the pull-up node PU, the first pole of the fifteenth transistor T15 is configured to be connected to the second control node PD_CN2, and the second pole of the fifteenth transistor T15 is configured to be connected to the first voltage terminal VGL1.
  • the first node noise reduction circuit 700 may be implemented as a sixteenth transistor T16 and a seventeenth transistor T17.
  • the gate of the sixteenth transistor T16 is configured to be connected to the first pull-down node PD1
  • the first pole of the sixteenth transistor T16 is configured to be connected to the pull-up node PU
  • the second pole of the sixteenth transistor T16 is configured to be connected to the first A voltage terminal VGL1 is connected.
  • the gate of the seventeenth transistor T17 is configured to be connected to the second pull-down node PD2
  • the first pole of the seventeenth transistor T17 is configured to be connected to the pull-up node PU
  • the second pole of the seventeenth transistor T17 is configured to be connected to the first The voltage terminal VGL1 is connected.
  • the sixteenth transistor T16 is turned on, and the pull-up node PU is electrically connected to the first voltage terminal VGL1, so that the pull-up node PU can be pulled down to Achieve noise reduction.
  • the second pull-down node PD2 is at an active level (for example, a high level)
  • the seventeenth transistor T17 is turned on, and the pull-up node PU can also be reduced in noise.
  • the output noise reduction circuit 800 may be implemented as an eighteenth transistor T18, a nineteenth transistor T19, a twentieth transistor T20, and a twenty-first transistor T21.
  • the gate of the eighteenth transistor T18 is configured to be connected to the first pull-down node PD1
  • the first pole of the eighteenth transistor T18 is configured to be connected to the shift signal output terminal OC
  • the second pole of the eighteenth transistor T18 is configured to Connected to the first voltage terminal VGL1.
  • the gate of the nineteenth transistor T19 is configured to be connected to the second pull-down node PD2, the first pole of the nineteenth transistor T19 is configured to be connected to the shift signal output terminal OC, and the second pole of the nineteenth transistor T19 is configured to be and The first voltage terminal VGL1 is connected.
  • the gate of the twentieth transistor T20 is configured to be connected to the first pull-down node PD1, the first pole of the twentieth transistor T20 is configured to be connected to the pixel signal output terminal OP, and the second pole of the twentieth transistor T20 is configured to be and The fourth voltage terminal VGL2 is connected to receive a fourth voltage.
  • the gate of the twenty-first transistor T21 is configured to be connected to the second pull-down node PD2, the first pole of the twenty-first transistor T21 is configured to be connected to the pixel signal output terminal OP, and the second pole of the twenty-first transistor T21 is configured It is connected to the fourth voltage terminal VGL2.
  • the fourth voltage terminal VGL2 is configured to keep an input DC low-level signal, and this DC low-level is referred to as a fourth voltage.
  • the fourth voltage terminal VGL2 may also be connected to the first voltage terminal VGL1, and the first voltage is used as the fourth voltage.
  • the eighteenth transistor T18 is turned on, and the shift signal output terminal OC and the first voltage terminal VGL1 are electrically connected, so that the shift signal can be output.
  • the terminal OC is pulled down to achieve noise reduction; the twentieth transistor T20 is also turned on, and the pixel signal output terminal OP is electrically connected to the fourth voltage terminal VGL2, so that the pixel signal output terminal OP can be pulled down to achieve noise reduction.
  • the second pull-down node PD2 is at an active level (for example, high level)
  • the nineteenth transistor T19 and the twenty-first transistor T21 are turned on, and the shift signal output terminal OC and the pixel signal output terminal OP can also be lowered. noise.
  • the second reset circuit 900 may be implemented as a twenty-second transistor T22.
  • the gate of the twenty-second transistor T22 is configured to be connected to the second reset terminal Re2 to receive a second reset signal
  • the first pole of the twenty-second transistor T22 is configured to be connected to a pull-up node PU
  • the twenty-second transistor T22 The second pole is configured to be connected to the first voltage terminal VGL1.
  • the second reset signal of the second reset terminal Re2 is an active level (for example, a high level)
  • the twenty-second transistor T22 is turned on, and the pull-up node PU is electrically connected to the first voltage terminal VGL1, thereby pulling up The node PU is reset.
  • the first capacitor C1, the second capacitor C2, and the third capacitor C3 may be capacitor devices manufactured through a process, for example, a capacitor device is implemented by manufacturing a special capacitor electrode.
  • Each electrode of the capacitor can be implemented by a metal layer, a semiconductor layer (such as doped polysilicon), and the first capacitor C1, the second capacitor C2, and the third capacitor C3 can also be parasitic capacitances between transistors, and can be passed through the transistor itself. And other devices, circuits to achieve.
  • FIG. 7 is a circuit diagram of a specific implementation example of the shift register unit shown in FIG. 5.
  • the shift register unit 10 includes a fifth control circuit 500 and a sixth control circuit 600.
  • the shift register unit 10 includes a fourth node PD and a third control node PD_CN.
  • the first node noise reduction circuit 700 may be implemented as a sixteenth transistor T16
  • the output noise reduction circuit 800 may be implemented as a twentieth transistor T20.
  • the output circuit 200 includes an output terminal OT, which is used to provide both input signals for the cascaded other shift register units 10 and driving signals for the pixel circuits.
  • the second control node PD_CN2 and the third control node PD_CN do not indicate actual components, but rather indicate a meeting point of related electrical connections in the circuit diagram.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • the thin film transistors are used as an example for description.
  • the source and drain of the transistor used here can be symmetrical in structure, so there can be no difference in structure of the source and drain of the transistor.
  • one pole is directly described as the first pole and the other pole is the second pole.
  • the transistors in the embodiments of the present disclosure are described by taking N-type transistors as an example.
  • the first electrode of the transistor is a drain
  • the second electrode is a source.
  • the present disclosure includes but is not limited to this.
  • one or more transistors in the shift register unit 10 provided by the embodiment of the present disclosure may also be a P-type transistor.
  • the first pole of the transistor is the source and the second pole is the drain.
  • the poles of a certain type of transistor are connected with reference to the poles of the corresponding transistor in the embodiment of the present disclosure, and the corresponding voltage terminal may provide a corresponding high voltage or low voltage.
  • the signal or voltage polarity is adjusted accordingly, and in this case, the terms “pull-up” and “pull-down” also cover the absolute value reduction of the corresponding levels, Raise to achieve the same transistor operation (e.g. on, off).
  • IGZO Indium Gallium Zinc Oxide
  • LTPS Low Temperature Polysilicon
  • amorphous silicon such as (Crystalline silicon
  • FIG. 8A is a signal timing diagram of a shift register unit provided by some embodiments of the present disclosure.
  • the working principle of the shift register unit 10 shown in FIG. 6 is described below with reference to the signal timing diagram shown in FIG. 8A, and each transistor is described here as an N-type transistor, but the embodiments of the present disclosure are not limited to this.
  • the shift register unit 10 may perform the following operations, respectively.
  • the reset control signal terminal Con provides a high-level signal, and the first transistor T1 is turned on.
  • the reference signal terminal Stan is connected to the clock signal terminal CLK, and the clock signal is used as a reference signal. At this time, the reference signal is at a high level. Due to the bootstrapping effect of the first capacitor C1, the level of the second pole of the first capacitor C1 is raised to the working level and charges the reset control node H so that the level of the reset control node H is the working level.
  • the amplitude A2 of the working level is greater than the amplitude A1 of the reference signal (that is, the working level is higher than the level of the reference signal).
  • the relationship between A2 and A1 is shown in Figure 8B.
  • the seventh transistor T7 is fully turned on by the working level of the reset control node H, thereby resetting the pull-up node PU.
  • the second voltage terminal VDDo provides a high-level signal, and the twelfth transistor T12 is turned on, so that the first control node PD_CN1 is at a high level.
  • the eighth transistor T8 is turned on, so that the first pull-down node PD1 is high, and controls the sixteenth transistor T16, the eighteenth transistor T18, and the twentieth transistor T20 to be turned on, thereby respectively shifting the pull-up node PU and shifting.
  • the signal output terminal OC and the pixel signal output terminal OP reduce noise.
  • the second pull-down node PD2 is at a low level.
  • the reset sub-signal terminal RST provides a high-level signal
  • the second transistor T2 and the third transistor T3 are turned on, thereby resetting the gate of the first transistor T1 and the reset control node H, so that the first transistor T1 And the seventh transistor T7 is turned off.
  • the input terminal INT provides a high level signal
  • the fourth transistor T4 is turned on
  • the pull-up node PU is charged to the first level (high level).
  • the fifth transistor T5 and the sixth transistor T6 are both turned on, and the clock signal of the clock signal terminal CLK is output to the shift signal output terminal OC and the pixel signal output terminal OP, respectively.
  • the clock signal is at a low level, so the shift signal output terminal OC and the pixel signal output terminal OP output a low level.
  • the thirteenth transistor T13 and the ninth transistor T9 are both turned on. Because the twelfth transistor T12 and the thirteenth transistor T13 are divided in series, the first control node PD_CN1 is pulled down to a low level. The eighth transistor T8 is turned off, and the first pull-down node PD1 is pulled down to a low level by the ninth transistor T9 that is turned on.
  • the sixteenth transistor T16, the eighteenth transistor T18, and the twentieth transistor T20 are all turned off.
  • the reset sub-signal terminal RST continues to provide a high-level signal, and the second transistor T2 and the third transistor T3 remain on, so that the first transistor T1 and the seventh transistor T7 remain off.
  • the clock signal at the clock signal terminal CLK becomes high level
  • the potential of the pull-up node PU is further increased due to the coupling effect of the clock signal
  • the fifth transistor T5 and the sixth transistor T6 are fully turned on
  • the high level of the clock signal is output to The shift signal output terminal OC and the pixel signal output terminal OP.
  • the first pull-down node PD1 is kept at a low level, and the sixteenth transistor T16, the eighteenth transistor T18, and the twentieth transistor T20 are kept off, and will not affect the output.
  • the third voltage terminal VDDe provides a high-level signal
  • the second voltage terminal VDDo provides a low-level signal.
  • the fifteenth transistor T15 and the eleventh transistor T11 are both turned on by the high level of the pull-up node PU.
  • the fourteenth transistor T14 is turned on. Since the fourteenth transistor T14 and the fifteenth transistor T15 are divided in series, the second control node PD_CN2 is at a low level.
  • the tenth transistor T10 is turned off, and the second pull-down node PD2 is at a low level under the action of the turned-on eleventh transistor T11.
  • the seventeenth transistor T17, the nineteenth transistor T19, and the twenty-first transistor T21 are all turned off. At this time, the first pull-down node PD1 remains at a low level.
  • the clock signal of the clock signal terminal CLK becomes a low level, and the potential of the pull-up node PU is reduced due to the coupling effect of the clock signal but is still high.
  • the fifth transistor T5 and the sixth transistor T6 Keeping on, the low level of the clock signal is output to the shift signal output terminal OC and the pixel signal output terminal OP.
  • the second reset terminal Re2 provides a high-level signal (not shown in FIG. 8A), the twenty-second transistor T22 is turned on, and the level of the pull-up node PU is pulled down to a low level.
  • the eleventh transistor T11 and the fifteenth transistor T15 are turned off.
  • the third voltage terminal VDDe provides a high-level signal
  • the second control node PD_CN2 is pulled up to a high level by the fourteenth transistor T14
  • the tenth transistor T10 is turned on
  • the second pull-down node PD2 is turned on. Pull up to high.
  • the seventeenth transistor T17, the nineteenth transistor T19, and the twenty-first transistor T21 are all turned on, thereby reducing noise on the pull-up node PU, the shift signal output terminal OC, and the pixel signal output terminal OP, respectively.
  • the second voltage terminal VDDo and the third voltage terminal VDDe alternately provide a high-level signal, so that the first pull-down node PD1 and the second pull-down node PD2 alternate to a high level, so that the pull-up node PU,
  • the shift signal output terminal OC and the pixel signal output terminal OP continuously reduce noise.
  • the reset control signal terminal Con provides a high-level signal
  • the first transistor T1 is turned on.
  • the reference signal (clock signal) provides a continuous high level signal. Due to the bootstrapping effect of the first capacitor C1, the level of the second pole of the first capacitor C1 is raised to the working level and charges the reset control node H so that the level of the reset control node H is the working level.
  • the amplitude A2 of the working level is greater than the amplitude A1 of the reference signal (that is, the working level is higher than the level of the reference signal).
  • the seventh transistor T7 is fully turned on by the working level of the reset control node H, so as to reset (noise reduce) the pull-up node PU.
  • the first stage 1 is a stage before the start of one-frame image scanning
  • the seventh stage 7 is a stage after the end of one-frame image scanning.
  • the reset control signal terminal Con can be provided with a high-level signal in both the first stage 1 and the seventh stage 7, so that the pull-up node is provided before and after the start of one frame of image scanning.
  • the PU performs a full reset (noise reduction);
  • the reset control signal terminal Con can also be provided with a high-level signal only in the seventh stage 7, so that the pull-up node PU is fully reset (noise reduction) only after the end of one frame of image scanning .
  • the clock signal in a scanning period t2 of one frame is made to be a periodic pulse; in the remaining periods (such as before Period t1 and period t3 after the end), keep the clock signal input a DC signal (such as a high-level signal), so that the level of the second pole of the first capacitor C1 can be performed in the first stage 1 and the seventh stage 7 Lift up.
  • a DC signal such as a high-level signal
  • each transistor when each transistor is a P-type transistor and the effective level for controlling the conduction of the transistor is a low level (the low level is greater than 0V), the clock signal needs to be made in one frame.
  • the low-level signal is maintained during the period t1 before the image scanning starts and the period t3 after the end of the scanning, so as to pull down the level of the second electrode of the first capacitor C1 in the first stage 1 and the seventh stage 7, so that The level is lower than the low level of the clock signal.
  • At least one embodiment of the present disclosure also provides a gate driving circuit.
  • the gate driving circuit includes a shift register unit according to any embodiment of the present disclosure.
  • the gate driving circuit can sufficiently reduce the noise of the first node (for example, a pull-up node), and solve the problem of insufficient noise reduction of the first node caused by the reduction of the channel current of the noise-reducing transistor in a low temperature environment, thereby avoiding the occurrence of multiple outputs. Phenomenon to ensure the normal operation of the product.
  • FIG. 9 is a schematic block diagram of a gate driving circuit according to some embodiments of the present disclosure.
  • the gate driving circuit 20 includes a plurality of cascaded shift register units (SR1-SR6, etc.).
  • the number of multiple shift register units is not limited and can be determined according to actual needs.
  • the shift register unit adopts the shift register unit 10 according to any embodiment of the present disclosure.
  • a part or all of the shift register units may adopt the shift register unit 10 described in any embodiment of the present disclosure.
  • the gate driving circuit 20 can be directly integrated on the array substrate of the display device by using the same process as the thin film transistor, so as to realize the progressive scanning driving function.
  • each shift register unit has an input terminal INT, a clock signal terminal CLK, a reference signal terminal Stan, a reset control signal terminal Con, a reset sub-signal terminal RST, a second reset terminal Re2, a shift signal output terminal OC, and a pixel signal. Output OP and so on.
  • the reference signal terminal Stan of each stage of the shift register unit is connected to the clock signal terminal CLK.
  • the input terminal INT of the s-th stage shift register unit is connected to the shift signal output terminal OC of the s-3-stage shift register unit, and s is an integer greater than 3.
  • the second reset terminal Re2 of the m-th stage shift register unit is connected to the shift signal output terminal OC of the m + 4-th stage shift register unit, and m is an integer greater than 0.
  • the input terminal INT of the first three stages of the shift register unit is connected to the trigger signal line STV1.
  • the second reset terminal Re2 of the last four-stage shift register unit is connected to a reset signal line provided separately.
  • the reset control signal terminal Con of each stage of the shift register unit is connected to the reset control signal line STV0, and the reset sub signal terminal RST of each stage of the shift register unit is connected to the trigger signal line STV1.
  • the pixel signal output terminal OP of each stage of the shift register unit is connected to the pixel unit of the corresponding row to output a driving signal to the pixel unit of the row.
  • the gate driving circuit 20 further includes a first clock signal line CLK1, a second clock signal line CLK2, a third clock signal line CLK3, a fourth clock signal line CLK4, a fifth clock signal line CLK5, and a sixth clock signal line. CLK6.
  • the connection modes of the shift register units of each stage and the above-mentioned clock signal lines are as follows and so on.
  • the clock signal terminal CLK of the 6n-5th stage shift register unit (for example, the first stage shift register unit SR1 in the figure) is connected to the first clock signal line CLK1, and the 6n-4th stage shift register unit (for example, the figure).
  • the clock signal terminal CLK of the second stage shift register unit SR2) is connected to the second clock signal line CLK2, and the clock signal of the 6n-3 stage shift register unit (for example, the third stage shift register unit SR3 in the figure)
  • the terminal CLK is connected to the third clock signal line CLK3, and the clock signal terminal CLK of the 6n-2th stage shift register unit (for example, the fourth stage shift register unit SR4 in the figure) is connected to the fourth clock signal line CLK4, and the 6n
  • the clock signal terminal CLK of the -1 stage shift register unit (for example, the fifth stage shift register unit SR5 in the figure) is connected to the fifth clock signal line CLK5, and the 6n stage shift register unit (for example, the sixth stage in the figure)
  • the gate driving circuit 20 may further include a timing controller T-CON.
  • the timing controller T-CON is configured to provide the above-mentioned clock signals to the shift register units at various levels.
  • the timing controller T-CON may also be configured to Provide reset control signals and reset sub-signals. It should be noted that the phase relationship between the multiple clock signals provided by the timing controller T-CON can be determined according to actual needs. In different examples, depending on the configuration, more or fewer clock signals can also be provided.
  • the gate driving circuit 20 further includes a plurality of voltage lines to provide a plurality of voltage signals to the shift register units of each stage.
  • the gate driving circuit 20 when used to drive a display panel, the gate driving circuit 20 may be disposed on one side of the display panel.
  • the display panel includes multiple rows of gate lines, and the pixel signal output terminals OP of the shift register units in the gate driving circuit 20 may be configured to be sequentially connected to the multiple rows of gate lines for outputting driving signals.
  • the gate driving circuit 20 can also be provided on both sides of the display panel to achieve bilateral driving.
  • the embodiment of the present disclosure does not limit the manner of setting the gate driving circuit 20.
  • a gate driving circuit 20 may be provided on one side of the display panel for driving odd-numbered rows of gate lines, and a gate driving circuit 20 may be provided on the other side of the display panel for driving even-numbered rows of gate lines.
  • FIG. 10 is a signal timing diagram of a gate driving circuit according to some embodiments of the present disclosure.
  • the signal timing diagram is the timing of the gate driving circuit 20 shown in FIG. 9, and the shift in the gate driving circuit 20 is shown in FIG.
  • the register unit is a shift register unit 10 shown in FIG. 6.
  • the gate driving circuit 20 outputs line by line during one frame image scanning, and displays one frame image after the last line is output.
  • the reset control signal line STV0 provides a high-level signal, thereby fully resetting (noise reduction) the pull-up node PU of each stage of the shift register unit.
  • the first to sixth clock signal lines CLK1-CLK6 provide periodic pulses during one frame image scanning, and the phases of the clock signals are sequentially delayed by 1/3 of the effective pulse width.
  • the first to sixth clock signal lines CLK1-CLK6 provide a high-level signal after one frame of image scanning is completed, so that the level of the second pole of the first capacitor C1 is further raised relative to the high-level signal, thereby achieving Working level.
  • the gate driving circuit 20 is not limited to the cascade manner described in FIG. 9, and may be any applicable cascade manner.
  • the waveform overlapping portions of the output signals Out1-Out6 of the pixel signal output terminals OP of the first to sixth stages of the shift register units SR1-SR6 will also be changed accordingly to meet the requirements of various applications. .
  • At least one embodiment of the present disclosure also provides a display device.
  • the display device includes a gate driving circuit according to any embodiment of the present disclosure.
  • the gate driving circuit in the display device can sufficiently reduce the noise of the first node (for example, the pull-up node), and solve the problem of insufficient noise reduction of the first node caused by the reduction of the channel current of the noise transistor in a low temperature environment, thereby avoiding the occurrence of The phenomenon of multiple output guarantees the normal operation of the product.
  • FIG. 11 is a schematic block diagram of a display device provided by some embodiments of the present disclosure.
  • the display device 30 includes a gate driving circuit 20.
  • the gate driving circuit 20 is a gate driving circuit according to any embodiment of the present disclosure.
  • the display device 30 may be a liquid crystal panel, a liquid crystal television, a display, an Organic Light-Emitting Diode (OLED) panel, an OLED television, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator Any product or component having a display function is not limited by the embodiments of the present disclosure.
  • OLED Organic Light-Emitting Diode
  • the display device 30 includes a display panel 3000, a gate driver 3010, a timing controller 3020, and a data driver 3030.
  • the display panel 3000 includes a plurality of pixel units P that are defined according to a plurality of scanning lines GL and a plurality of data lines DL crossing; a gate driver 3010 is used to drive a plurality of scanning lines GL; a data driver 3030 is used to drive a plurality of data lines DL;
  • the timing controller 3020 is configured to process the image data RGB input from the outside of the display device 30, provide the processed image data RGB to the data driver 3030, and output the scan control signal GCS and the data control signal DCS to the gate driver 3010 and the data driver 3030.
  • the gate driver 3010 and the data driver 3030 are controlled.
  • the gate driver 3010 includes the gate driving circuit 20 provided in any of the above embodiments.
  • the pixel signal output terminals OP of the plurality of shift register units 10 in the gate driving circuit 20 are correspondingly connected to the plurality of scanning lines GL.
  • the plurality of scanning lines GL are correspondingly connected to the pixel units P arranged in a plurality of rows.
  • the pixel signal output terminals OP of the shift register units 10 in the gate driving circuit 20 sequentially output signals to the plurality of scanning lines GL, so that the plurality of rows of pixel units P in the display panel 3000 can perform progressive scanning.
  • the gate driver 3010 may be implemented as a semiconductor chip, or may be integrated in the display panel 3000 to form a GOA circuit.
  • the data driver 3030 converts digital image data RGB input from the timing controller 3020 into a data signal according to a plurality of data control signals DCS originating from the timing controller 3020 using a reference gamma voltage.
  • the data driver 3030 provides the converted data signals to the plurality of data lines DL.
  • the data driver 3030 may be implemented as a semiconductor chip.
  • the timing controller 3020 processes the externally input image data RGB to match the size and resolution of the display panel 3000, and then provides the processed image data to the data driver 3030.
  • the timing controller 3020 generates a plurality of scan control signals GCS and a plurality of data control signals DCS using synchronization signals (such as the dot clock DCLK, the data enable signal DE, the horizontal synchronization signal Hsync, and the vertical synchronization signal Vsync) input from the outside of the display device 30. .
  • the timing controller 3020 provides the scan control signal GCS and the data control signal DCS to the gate driver 3010 and the data driver 3030, respectively, for controlling the gate driver 3010 and the data driver 3030.
  • the display device 30 may further include other components, such as a signal decoding circuit, a voltage conversion circuit, and the like.
  • these components may use existing conventional components, which will not be described in detail here.
  • At least one embodiment of the present disclosure also provides a driving method of a shift register unit, which can be used to drive the shift register unit 10 according to any embodiment of the present disclosure.
  • the first node (such as a pull-up node) can be sufficiently reduced in noise, and the problem of insufficient noise reduction in the first node caused by the reduction of the channel current of the noise-reducing transistor in a low-temperature environment can be avoided, thereby avoiding the occurrence of multiple outputs. Phenomenon to ensure the normal operation of the product.
  • the driving method of the shift register unit 10 includes the following operations:
  • the input circuit 100 controls the level of the first node (for example, the pull-up node PU) to the first level in response to the input signal, and the output circuit 200 outputs the second voltage of the clock signal.
  • Level to output OT the first node (for example, the pull-up node PU)
  • the output circuit 200 outputs the third level of the clock signal to the output terminal OT;
  • the reset control circuit 400 inputs a first reset signal Re1 to the first reset circuit 300 in response to the reset control signal and the reference signal to turn on the first reset.
  • the circuit 300 enables the first reset circuit 300 to reset the pull-up node PU.
  • the second level is low and the third level is high.
  • the first level is a high level, and the first level may be the same as or different from the third level.
  • the clock signal and the reference signal are the same signal, and are periodic pulses in the input phase and the output phase, and are DC signals (such as high-level or low-level signals) in the first reset phase.

Abstract

一种移位寄存器单元(10)及其驱动方法、栅极驱动电路(20)及显示装置(30)，移位寄存器单元(10)包括输入电路(100)、输出电路(200)、第一复位电路(300)和复位控制电路(400)。输入电路(100)配置为响应于输入信号对第一节点(PU)的电平进行控制；输出电路(200)配置为在第一节点(PU)的电平的控制下，将时钟信号(CLK)输出至输出端(OT)；第一复位电路(300)配置为响应于第一复位信号(Re1)对第一节点(PU)进行复位；复位控制电路(400)配置为响应于复位控制信号和基准信号向第一复位电路(300)输入第一复位信号(Re1)，以开启第一复位电路(300)。移位寄存器单元(10)可解决低温环境下降噪晶体管沟道电流降低导致的第一节点(PU)降噪不充分的问题，避免产生多次输出的现象，保证产品的正常工作。

Description

移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
本申请要求于2018年6月21日递交的中国专利申请第201810644213.6号的优先权，该中国专利申请的全文以引入的方式并入以作为本申请的一部分。
技术领域
本公开的实施例涉及一种移位寄存器单元及其驱动方法、栅极驱动电路及显示装置。
背景技术
在显示技术领域，例如液晶显示面板的像素阵列通常包括多行栅线和与之交错的多列数据线。对栅线的驱动可以通过栅极驱动电路实现。例如，栅极驱动电路可以通过绑定的集成驱动电路实现。近几年随着非晶硅薄膜晶体管或氧化物薄膜晶体管制备工艺的不断提高，也可以将栅极驱动电路直接集成在薄膜晶体管阵列基板上构成GOA(Gate-driver On Array)来对栅线进行驱动。例如，可以采用由多个级联的移位寄存器单元构成的GOA为像素阵列的多行栅线提供开关态电压信号，从而例如控制多行栅线依序打开，并且同时由数据线向像素阵列中对应行的像素单元提供数据信号，以在各像素单元形成显示图像的各灰阶所需要的灰度电压，进而显示一帧图像。目前的显示面板越来越多地采用GOA技术来对栅线进行驱动。GOA技术有助于实现窄边框，并且可以降低生产成本。
发明内容
本公开至少一个实施例提供一种移位寄存器单元，包括输入电路、输出电路、第一复位电路和复位控制电路；其中，所述输入电路配置为响应于输入信号对第一节点的电平进行控制；所述输出电路配置为在所述第一节点的电平的控制下，将时钟信号输出至输出端；所述第一复位电路配置为响应于第一复位信号对所述第一节点进行复位；所述复位控制电路配置为响应于复位控制信号和基准信号向所述第一复位电路输入所述第一复位信号，以开启 所述第一复位电路。
例如，在本公开一实施例提供的移位寄存器单元中，所述复位控制电路还配置为使得所述第一复位信号的电平的幅度大于所述基准信号的电平的幅度。
例如，在本公开一实施例提供的移位寄存器单元中，所述复位控制电路包括：驱动子电路，配置为根据所述复位控制信号和所述基准信号对复位控制节点的电平进行调节，并将所述复位控制节点的电平作为所述第一复位信号；复位子电路，配置为响应于复位子信号对所述复位控制节点和所述驱动子电路进行复位。
例如，在本公开一实施例提供的移位寄存器单元中，所述驱动子电路包括第一电容和第一晶体管，所述第一电容的第一极配置为和复位控制信号端连接以接收所述复位控制信号，所述第一电容的第二极配置为和基准信号端连接以接收所述基准信号，所述第一晶体管的栅极配置为和所述第一电容的第一极连接，所述第一晶体管的第一极配置为和所述第一电容的第二极连接，所述第一晶体管的第二极配置为和所述复位控制节点连接；所述复位子电路包括第二晶体管和第三晶体管，所述第二晶体管的栅极配置为和复位子信号端连接以接收所述复位子信号，所述第二晶体管的第一极配置为和所述第一晶体管的栅极连接，所述第二晶体管的第二极配置为和第一电压端连接以接收第一电压，所述第三晶体管的栅极配置为和所述复位子信号端连接以接收所述复位子信号，所述第三晶体管的第一极配置为和所述复位控制节点连接，所述第三晶体管的第二极配置为和所述第一电压端连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述基准信号端与时钟信号端连接以接收所述时钟信号作为所述基准信号。
例如，在本公开一实施例提供的移位寄存器单元包括第一控制电路、第二控制电路、第三控制电路、第四控制电路、第一节点降噪电路和输出降噪电路；其中，所述第一控制电路配置为在所述第一节点和第一控制节点的电平的控制下，对第二节点的电平进行控制；所述第二控制电路配置为在所述第一节点和第二控制节点的电平的控制下，对第三节点的电平进行控制；所述第三控制电路配置为在所述第一节点的电平的控制下，对所述第一控制节点的电平进行控制；所述第四控制电路配置为在所述第一节点的电平的控制下，对所述第二控制节点的电平进行控制；所述第一节点降噪电路配置为在 所述第二节点或所述第三节点的电平的控制下，对所述第一节点进行降噪；所述输出降噪电路配置为在所述第二节点或所述第三节点的电平的控制下，对所述输出端进行降噪。
例如，在本公开一实施例提供的移位寄存器单元中，所述输入电路包括第四晶体管；所述第四晶体管的栅极与第一极连接且配置为和输入端连接以接收所述输入信号，所述第四晶体管的第二极配置为和所述第一节点连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述输出电路的输出端包括至少一个移位信号输出端和至少一个像素信号输出端。
例如，在本公开一实施例提供的移位寄存器单元中，所述输出电路包括第五晶体管、第六晶体管和第二电容；所述第五晶体管的栅极配置为和所述第一节点连接，所述第五晶体管的第一极配置为和时钟信号端连接以接收所述时钟信号，所述第五晶体管的第二极配置为和所述移位信号输出端连接；所述第六晶体管的栅极配置为和所述第一节点连接，所述第六晶体管的第一极配置为和所述时钟信号端连接以接收所述时钟信号，所述第六晶体管的第二极配置为和所述像素信号输出端连接；所述第二电容的第一极配置为和所述第一节点连接，所述第二电容的第二极配置为和所述第六晶体管的第二极或所述第五晶体管的第二极连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一复位电路包括第七晶体管；所述第七晶体管的栅极配置为和所述复位控制节点连接，所述第七晶体管的第一极配置为和所述第一节点连接，所述第七晶体管的第二极配置为和第一电压端连接以接收第一电压。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一控制电路包括第八晶体管和第九晶体管，所述第八晶体管的栅极配置为和所述第一控制节点连接，所述第八晶体管的第一极配置为和第二电压端连接以接收第二电压，所述第八晶体管的第二极配置为和所述第二节点连接，所述第九晶体管的栅极配置为和所述第一节点连接，所述第九晶体管的第一极配置为和所述第二节点连接，所述第九晶体管的第二极配置为和第一电压端连接以接收第一电压；所述第二控制电路包括第十晶体管和第十一晶体管，所述第十晶体管的栅极配置为和所述第二控制节点连接，所述第十晶体管的第一极配置为和第三电压端连接以接收第三电压，所述第十晶体管的第二极配置为和所述第三节点连接，所述第十一晶体管的栅极配置为和所述第一节点连接，所 述第十一晶体管的第一极配置为和所述第三节点连接，所述第十一晶体管的第二极配置为和所述第一电压端连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述第三控制电路包括第十二晶体管和第十三晶体管，所述第十二晶体管的栅极与第一极连接且配置为和第二电压端连接以接收第二电压，所述第十二晶体管的第二极配置为和所述第一控制节点连接，所述第十三晶体管的栅极配置为和所述第一节点连接，所述第十三晶体管的第一极配置为和所述第一控制节点连接，所述第十三晶体管的第二极配置为和第一电压端连接以接收第一电压；所述第四控制电路包括第十四晶体管和第十五晶体管，所述第十四晶体管的栅极与第一极连接且配置为和第三电压端连接以接收第三电压，所述第十四晶体管的第二极配置为和所述第二控制节点连接，所述第十五晶体管的栅极配置为和所述第一节点连接，所述第十五晶体管的第一极配置为和所述第二控制节点连接，所述第十五晶体管的第二极配置为和所述第一电压端连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一节点降噪电路包括第十六晶体管和第十七晶体管；所述第十六晶体管的栅极配置为和所述第二节点连接，所述第十六晶体管的第一极配置为和所述第一节点连接，所述第十六晶体管的第二极配置为和第一电压端连接以接收第一电压；所述第十七晶体管的栅极配置为和所述第三节点连接，所述第十七晶体管的第一极配置为和所述第一节点连接，所述第十七晶体管的第二极配置为和所述第一电压端连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述输出降噪电路包括第十八晶体管、第十九晶体管、第二十晶体管和第二十一晶体管；所述第十八晶体管的栅极配置为和所述第二节点连接，所述第十八晶体管的第一极配置为和所述移位信号输出端连接，所述第十八晶体管的第二极配置为和第一电压端连接以接收第一电压；所述第十九晶体管的栅极配置为和所述第三节点连接，所述第十九晶体管的第一极配置为和所述移位信号输出端连接，所述第十九晶体管的第二极配置为和所述第一电压端连接；所述第二十晶体管的栅极配置为和所述第二节点连接，所述第二十晶体管的第一极配置为和所述像素信号输出端连接，所述第二十晶体管的第二极配置为和第四电压端连接以接收第四电压；所述第二十一晶体管的栅极配置为和所述第三节点连接，所述第二十一晶体管的第一极配置为和所述像素信号输出端连接，所述 第二十一晶体管的第二极配置为和所述第四电压端连接。
例如，在本公开一实施例提供的移位寄存器单元包括第二复位电路；其中，所述第二复位电路配置为响应于第二复位信号对所述第一节点进行复位。
例如，在本公开一实施例提供的移位寄存器单元中，所述第二复位电路包括第二十二晶体管；所述第二十二晶体管的栅极配置为和第二复位端连接以接收所述第二复位信号，所述第二十二晶体管的第一极配置为和所述第一节点连接，所述第二十二晶体管的第二极配置为和第一电压端连接以接收第一电压。
本公开至少一个实施例还提供一种栅极驱动电路，包括本公开任一实施例所述的移位寄存器单元。
本公开至少一个实施例还提供一种显示装置，包括本公开任一实施例所述的栅极驱动电路。
本公开至少一个实施例还提供一种本公开任一实施例所述的移位寄存器单元的驱动方法，包括：输入阶段，所述输入电路响应于所述输入信号控制所述第一节点的电平至第一电平，所述输出电路输出所述时钟信号的第二电平至所述输出端；输出阶段，所述输出电路输出所述时钟信号的第三电平至所述输出端；第一复位阶段，所述复位控制电路响应于所述复位控制信号和所述基准信号向所述第一复位电路输入所述第一复位信号，以开启所述第一复位电路，使得所述第一复位电路对所述第一节点进行复位。
例如，在本公开一实施例提供的移位寄存器单元的驱动方法中，所述时钟信号和所述基准信号为同一个信号，且在所述输入阶段和所述输出阶段为周期脉冲，在所述第一复位阶段为直流信号。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一些实施例提供的一种移位寄存器单元的示意框图；
图2为本公开一些实施例提供的一种移位寄存器单元的复位控制电路的示意框图；
图3为本公开一些实施例提供的另一种移位寄存器单元的示意框图；
图4为本公开一些实施例提供的另一种移位寄存器单元的示意框图；
图5为本公开一些实施例提供的另一种移位寄存器单元的示意框图；
图6为图4中所示的移位寄存器单元的一种具体实现示例的电路图；
图7为图5中所示的移位寄存器单元的一种具体实现示例的电路图；
图8A为本公开一些实施例提供的一种移位寄存器单元的信号时序图；
图8B为本公开一些实施例提供的一种移位寄存器单元的复位控制节点的时序图；
图9为本公开一些实施例提供的一种栅极驱动电路的示意框图；
图10为本公开一些实施例提供的一种栅极驱动电路的信号时序图；以及
图11为本公开一些实施例提供的一种显示装置的示意框图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
GOA技术在降低显示装置的制造成本、提升显示装置的美观等方面相对于IC芯片绑定传统技术具有一定的优势，但是GOA电路的移位寄存器单元容易出现上拉节点降噪不充分的问题，从而产生多次输出(Multi-OP)的现象，极大地降低了产品的品质。GOA的多次输出现象是最为普遍也最为严重的一种GOA异常现象。产生多次输出的原因有很多种，例如移位寄存器单 元的上拉节点在一帧图像显示后未完全放电，或者在低温环境下降噪晶体管(用于对上拉节点降噪的晶体管)的沟道电流(Ids)降低等。在低温环境下，降噪晶体管的沟道电流降低，无法对上拉节点充分降噪，上拉节点的电荷累积后使输出端产生多次输出。这种多次输出现象不仅会影响与移位寄存器单元对应的一行像素单元的显示，还会由于移位寄存器单元的级联关系而影响其他行像素单元的显示，最终导致画面显示的异常。
本公开至少一实施例提供一种移位寄存器单元及其驱动方法、栅极驱动电路及显示装置，该移位寄存器单元可对第一节点(例如上拉节点)充分降噪，解决低温环境下降噪晶体管沟道电流降低导致的第一节点降噪不充分的问题，从而避免产生多次输出的现象，保证产品的正常工作。
下面，将参考附图详细地说明本公开的实施例。应当注意的是，不同的附图中相同的附图标记将用于指代已描述的相同的元件。
本公开至少一实施例提供一种移位寄存器单元，包括输入电路、输出电路、第一复位电路和复位控制电路。输入电路配置为响应于输入信号对第一节点的电平进行控制；输出电路配置为在第一节点的电平的控制下，将时钟信号输出至输出端；第一复位电路配置为响应于第一复位信号对第一节点进行复位；复位控制电路配置为响应于复位控制信号和基准信号向第一复位电路输入第一复位信号，以开启第一复位电路。
图1为本公开一些实施例提供的一种移位寄存器单元的示意框图。参考图1，该移位寄存器单元10包括输入电路100、输出电路200、第一复位电路300和复位控制电路400。需要说明的是，在本公开各个实施例的说明中，上拉节点PU为第一节点的一个示例，下面以第一节点为上拉节点PU为例进行说明，但这并不构成对本公开实施例的限制。
输入电路100配置为响应于输入信号对该移位寄存器单元10的上拉节点PU的电平进行控制。例如，在一个示例中，输入信号被写入上拉节点PU并对上拉节点PU进行充电，以使上拉节点PU的电平升高。例如，输入电路100与输入端INT连接，配置为在输入端INT提供的输入信号的控制下使上拉节点PU与输入端INT电连接，从而可以使输入信号的高电平对上拉节点PU充电，使得上拉节点PU的电平改变(例如上升)以控制输出电路200导通。当然，本公开的实施例不限于此，例如，输入电路100还可以与另外提供的高电压端连接，配置为在输入端INT提供的输入信号的控制下使上拉节 点PU与该高电压端电连接，从而可以使该高电压端输出的高电平信号对上拉节点PU充电。
输出电路200配置为在上拉节点PU的电平的控制下，将时钟信号CLK输出至该移位寄存器单元10的输出端OT，作为该移位寄存器单元10的输出信号，以驱动例如与该输出端OT连接的显示面板的栅线。例如，输出电路200与时钟信号端CLK、上拉节点PU和输出端OT连接，配置为在上拉节点PU的电平的控制下导通，使时钟信号端CLK和输出端OT电连接，从而可以将时钟信号端CLK提供的时钟信号输出至输出端OT。
第一复位电路300配置为响应于第一复位信号Re1对上拉节点PU进行复位。例如，第一复位电路300与上拉节点PU和复位控制节点H连接，配置为在复位控制节点H的电平的控制下使上拉节点PU和另外提供的低电压端电连接，从而对上拉节点PU进行复位。在本公开的实施例中，将复位控制节点H的电平作为第一复位信号Re1以控制第一复位电路300开启与否。例如，第一复位电路300可以在一帧图像扫描开始前和结束后均对上拉节点PU进行复位，也可以仅在一帧图像扫描结束后对上拉节点PU进行复位。
复位控制电路400配置为响应于复位控制信号和基准信号向第一复位电路300输入第一复位信号Re1，以开启第一复位电路300。例如，复位控制电路400与复位控制信号端Con、基准信号端Stan和复位控制节点H连接，配置为在复位控制信号端Con提供的复位控制信号的控制下对基准信号端Stan提供的基准信号的幅度进行调节，并将调节后的信号提供给复位控制节点H，将复位控制节点H的电平作为第一复位信号Re1以控制第一复位电路300导通。
例如，复位控制电路400还配置为使得第一复位信号Re1的电平的幅度大于基准信号的电平的幅度。例如，在一个示例中，复位控制电路400将基准信号的幅度拉高并提供给复位控制节点H，第一复位电路300在复位控制节点H的高电平的作用下导通。此时复位控制节点H的电平(第一复位信号Re1的电平)高于基准信号的电平，从而与将基准信号直接施加至第一复位电路300以对其进行控制的情形相比，可以使第一复位电路300充分导通，对上拉节点PU充分降噪(复位)，进而解决低温环境下降噪晶体管沟道电流降低导致的上拉节点PU降噪不充分的问题，避免GOA产生多次输出的现象，保证产品的正常工作。当然，本公开的实施例不限于此，例如，在另一 个示例中，第一复位电路300在低电平(该低电平大于0V)的作用下导通，当需要对上拉节点PU进行复位时，复位控制电路400将基准信号的幅度拉低并提供给复位控制节点H，第一复位电路300在复位控制节点H的低电平的作用下导通，此时复位控制节点H的电平(第一复位信号Re1的电平)低于基准信号的电平，从而可以使第一复位电路300充分导通，以对上拉节点PU充分降噪。
例如，基准信号端Stan还可以与时钟信号端CLK连接，从而将时钟信号复用为基准信号，只需在需要使第一复位电路300导通时使时钟信号输出相应的直流信号(例如高电平或低电平信号)即可，这种方式可以减少信号线的数量，便于布线。当然，本公开的实施例不限于此，基准信号端Stan也可以与其他信号端、电压端连接，只要信号满足要求即可。
图2为本公开一些实施例提供的一种移位寄存器单元的复位控制电路的示意框图。参考图2，复位控制电路400包括驱动子电路410和复位子电路420。
驱动子电路410配置为根据复位控制信号和基准信号对复位控制节点H的电平进行调节(例如进行充电)，并将复位控制节点H的电平作为第一复位信号Re1。例如，驱动子电路410与复位控制信号端Con、基准信号端Stan和复位控制节点H连接，配置为在复位控制信号端Con提供的复位控制信号的控制下对基准信号端Stan提供的基准信号的幅度进行调节，并利用调节后的信号对复位控制节点H充电。
复位子电路420配置为响应于复位子信号对复位控制节点H和驱动子电路410进行复位。例如，复位子电路420与复位子信号端RST和复位控制节点H连接，配置为在复位子信号端RST提供的复位子信号的控制下使复位控制节点H和另外提供的低电压端电连接，从而对复位控制节点H和驱动子电路410复位。
图3为本公开一些实施例提供的另一种移位寄存器单元的示意框图。参考图3，该实施例中移位寄存器单元10还包括第一控制电路510、第二控制电路520、第三控制电路610、第四控制电路620、第一节点降噪电路700和输出降噪电路800，其他结构与图1中所示的移位寄存器单元10基本相同。需要说明的是，在本公开各个实施例的说明中，第一下拉节点PD1为第二节点的一个示例，第二下拉节点PD2为第三节点的一个示例，下面以第二节点 为第一下拉节点PD1、第三节点为第二下拉节点PD2为例进行说明，但这并不构成对本公开实施例的限制。
第一控制电路510配置为在上拉节点PU和第一控制节点PD_CN1的电平的控制下，对第一下拉节点PD1的电平进行控制。例如，第一控制电路510与第一电压端VGL1、第二电压端VDDo、上拉节点PU、第一下拉节点PD1和第一控制节点PD_CN1连接，配置为在上拉节点PU的电平的控制下使第一下拉节点PD1和第一电压端VGL1电连接，从而对第一下拉节点PD1的电平进行下拉控制，使其处于低电平。第一电压端VGL1例如配置为保持输入直流低电平信号，将该直流低电平称为第一电压，以下各实施例与此相同，不再赘述。同时，第一控制电路510可以在第一控制节点PD_CN1的电平的控制下使第一下拉节点PD1和第二电压端VDDo电连接，从而在第二电压端VDDo提供高电平信号时对第一下拉节点PD1进行充电以使其处于高电平，在第二电压端VDDo提供低电平信号时使第一下拉节点PD1放电。
第二控制电路520配置为在上拉节点PU和第二控制节点PD_CN2的电平的控制下，对第二下拉节点PD2的电平进行控制。例如，第二控制电路520与第一电压端VGL1、第三电压端VDDe、上拉节点PU、第二下拉节点PD2和第二控制节点PD_CN2连接，配置为在上拉节点PU的电平的控制下使第二下拉节点PD2和第一电压端VGL1电连接，从而对第二下拉节点PD2的电平进行下拉控制，使其处于低电平。同时，第二控制电路520可以在第二控制节点PD_CN2的电平的控制下使第二下拉节点PD2和第三电压端VDDe电连接，从而在第三电压端VDDe提供高电平信号时对第二下拉节点PD2进行充电以使其处于高电平，在第三电压端VDDe提供低电平信号时使第二下拉节点PD2放电。
第三控制电路610配置为在上拉节点PU的电平的控制下，对第一控制节点PD_CN1的电平进行控制。例如，第三控制电路610与第一电压端VGL1、第二电压端VDDo、上拉节点PU和第一控制节点PD_CN1连接，配置为在上拉节点PU的电平的控制下使第一控制节点PD_CN1和第一电压端VGL1电连接，从而对第一控制节点PD_CN1的电平进行下拉控制，使其处于低电平。同时，第三控制电路610可以在第二电压端VDDo提供高电平信号时使第一控制节点PD_CN1处于高电平。
第四控制电路620配置为在上拉节点PU的电平的控制下，对第二控制 节点PD_CN2的电平进行控制。例如，第四控制电路620与第一电压端VGL1、第三电压端VDDe、上拉节点PU和第二控制节点PD_CN2连接，配置为在上拉节点PU的电平的控制下使第二控制节点PD_CN2和第一电压端VGL1电连接，从而对第二控制节点PD_CN2的电平进行下拉控制，使其处于低电平。同时，第四控制电路620可以在第三电压端VDDe提供高电平信号时使第二控制节点PD_CN2处于高电平。
第一节点降噪电路700配置为在第一下拉节点PD1或第二下拉节点PD2的电平的控制下，对上拉节点PU进行降噪。例如，第一节点降噪电路700与第一电压端VGL1、上拉节点PU、第一下拉节点PD1和第二下拉节点PD2连接，配置为在第一下拉节点PD1或第二下拉节点PD2的电平的控制下，使上拉节点PU和第一电压端VGL1电连接，从而对上拉节点PU进行下拉降噪。
输出降噪电路800配置为在第一下拉节点PD1或第二下拉节点PD2的电平的控制下，对输出端OT进行降噪。例如，输出降噪电路800与第一电压端VGL1、输出端OT、第一下拉节点PD1和第二下拉节点PD2连接，配置为在第一下拉节点PD1或第二下拉节点PD2的电平的控制下，使输出端OT和第一电压端VGL1电连接，从而对输出端OT进行下拉降噪。
需要说明的是，本公开的实施例中，第二电压端VDDo和第三电压端VDDe配置为交替提供直流高电平信号，通过第三控制电路610、第四控制电路620、第一控制电路510和第二控制电路520的作用，使第一下拉节点PD1和第二下拉节点PD2交替为高电平，从而控制第一节点降噪电路700和输出降噪电路800分别对上拉节点PU和输出端OT进行降噪。例如，当第二电压端VDDo提供高电平信号时，第三电压端VDDe提供低电平信号，此时第一下拉节点PD1为高电平；当第三电压端VDDe提供高电平信号时，第二电压端VDDo提供低电平信号，此时第二下拉节点PD2为高电平。通过这种方式，可以避免移位寄存器单元10中的晶体管长期导通引起的性能漂移。例如，将第二电压端VDDo提供的信号称为第二电压，将第三电压端VDDe提供的信号称为第三电压，以下各实施例与此相同，不再赘述。
图4为本公开一些实施例提供的另一种移位寄存器单元的示意框图。参考图4，该实施例中移位寄存器单元10还包括第二复位电路900，其他结构与图3中所示的移位寄存器单元10基本相同。
第二复位电路900配置为响应于第二复位信号对上拉节点PU进行复位。例如，第二复位电路900与上拉节点PU、第二复位信号端Re2和第一电压端VGL1连接，配置为在第二复位信号端Re2提供的第二复位信号的控制下，使上拉节点PU和第一电压端VGL1电连接，从而对上拉节点PU进行复位。例如，第二复位电路900在该移位寄存器单元10输出结束后对上拉节点PU进行复位。
图5为本公开一些实施例提供的另一种移位寄存器单元的示意框图。参考图5，与图4中所示的移位寄存器单元10相比，该实施例中的移位寄存器单元10包括第五控制电路500和第六控制电路600，相应地，还包括第四节点PD和第三控制节点PD_CN。第六控制电路600与电源电压端VDD连接，电源电压端VDD例如配置为保持输入直流高电平信号，将该直流高电平称为电源电压，以下各实施例与此相同，不再赘述。第一节点降噪电路700和输出降噪电路800在第四节点PD的电平的控制下分别对上拉节点PU和输出端OT进行降噪。该移位寄存器单元10的电路结构简单，便于加工，且有利于实现窄边框。该移位寄存器单元10的其他结构与图4中所示的移位寄存器单元10基本相同，此处不再赘述。
需要说明的是，本公开的实施例中，移位寄存器单元10可以由复位控制电路400与通常的任意结构的移位寄存器单元的结合得到，而不限于上述的结构形式。复位控制电路400可以使第一复位信号Re1的电平的幅度大于基准信号的电平的幅度，使第一复位电路300充分导通，从而对上拉节点PU进行充分降噪(复位)，以避免产生多次输出的现象。
图6为图4中所示的移位寄存器单元的一种具体实现示例的电路图。在下面的说明中以各晶体管为N型晶体管为例进行说明，但这并不构成对本公开实施例的限制。参考图6，该移位寄存器单元10包括第一至第二十二晶体管T1-T22，以及还包括第一至第三电容C1-C3。
例如，复位控制电路400包括驱动子电路410和复位子电路420。如图6所示，驱动子电路410可以实现为第一电容C1和第一晶体管T1。第一电容C1的第一极配置为和复位控制信号端Con连接以接收复位控制信号，第一电容C1的第二极配置为和基准信号端Stan连接以接收基准信号。第一晶体管T1的栅极配置为和第一电容C1的第一极连接，第一晶体管T1的第一极配置为和第一电容C1的第二极连接，第一晶体管T1的第二极配置为和复位 控制节点H连接。
复位子电路420可以实现为第二晶体管T2和第三晶体管T3。第二晶体管T2的栅极配置为和复位子信号端RST连接以接收复位子信号，第二晶体管T2的第一极配置为和第一晶体管T1的栅极连接，第二晶体管T2的第二极配置为和第一电压端VGL1连接以接收第一电压。第三晶体管T3的栅极配置为和复位子信号端RST连接以接收复位子信号，第三晶体管T3的第一极配置为和复位控制节点H连接，第三晶体管T3的第二极配置为和第一电压端VGL1连接。
当复位控制信号端Con提供的复位控制信号由使第一晶体管T1截止的无效电平变为使第一晶体管T1导通的有效电平(例如由低电平变为高电平)时，由于第一电容C1的自举作用，第一电容C1的第二极的电平会进一步抬高且高于基准信号端Stan的基准信号的高电平，将该抬高后的电平称为工作电平。第一晶体管T1在复位控制信号的高电平的作用下导通，第一电容C1的第二极的工作电平对复位控制节点H充电，使复位控制节点H的电平也达到工作电平。例如，基准信号端Stan可以与任意的信号端、电压端连接，只需保证在需要时提供高电平信号即可，以使第一电容C1的第二极的电平相对于该高电平信号进一步抬高，从而达到工作电平。当复位子信号端RST提供的复位子信号为有效电平(例如高电平)时，第二晶体管T2和第三晶体管T3均导通，从而分别对第一晶体管T1的栅极和复位控制节点H进行复位。
需要说明的是，本公开的各实施例中，复位控制电路400也可以实现为其他电路结构，还可以进一步包括更多的电路元件，本公开的实施例对此不作限制。例如，在一个示例中，如图6所示，复位控制电路400还包括第三电容C3，第三电容C3的第一极配置为和第一晶体管T1的栅极连接，第三电容C3的第二极配置为和第一电压端VGL1连接。第三电容C3可以提高第一晶体管T1的栅极和第一电压端VGL1的隔离度，有利于更好地控制第一晶体管T1的栅极电压。
输入电路100可以实现为第四晶体管T4。第四晶体管T4的栅极与第一极连接，且配置为和输入端INT连接以接收输入信号，第四晶体管T4的第二极配置为和上拉节点PU连接。当输入端INT的输入信号为有效电平(例如高电平)时，第四晶体管T4导通，输入信号对上拉节点PU进行充电，使其处于高电平。
例如，在一个示例中，输出电路200的输出端OT包括至少一个移位信号输出端OC和至少一个像素信号输出端OP，以提高该移位寄存器单元10的驱动能力。移位信号输出端OC用于为级联的其他移位寄存器单元10提供输入信号，像素信号输出端OP用于为像素电路提供驱动信号。例如，移位信号输出端OC和像素信号输出端OP的输出信号相同。
输出电路200可以实现为第五晶体管T5、第六晶体管T6和第二电容C2。第五晶体管T5的栅极配置为和上拉节点PU连接，第五晶体管T5的第一极配置为和时钟信号端CLK连接以接收时钟信号，第五晶体管T5的第二极配置为和移位信号输出端OC连接。第六晶体管T6的栅极配置为和上拉节点PU连接，第六晶体管T6的第一极配置为和时钟信号端CLK连接以接收时钟信号，第六晶体管T6的第二极配置为和像素信号输出端OP连接。第二电容C2的第一极配置为和上拉节点PU连接，第二电容C2的第二极配置为和第六晶体管T6的第二极连接。当然，本公开的实施例不限于此，在另一个示例中，第二电容C2的第二极也可以和第五晶体管T5的第二极连接。当上拉节点PU处于有效电平(例如高电平)时，第五晶体管T5和第六晶体管T6均导通，从而分别将时钟信号端CLK的时钟信号输出到移位信号输出端OC和像素信号输出端OP。
第一复位电路300可以实现为第七晶体管T7。第七晶体管T7的栅极配置为和复位控制节点H连接，第七晶体管T7的第一极配置为和上拉节点PU连接，第七晶体管T7的第二极配置为和第一电压端VGL1连接。当复位控制节点H被充电至工作电平时，第七晶体管T7导通，将上拉节点PU和第一电压端VGL1电连接，从而可以对上拉节点PU进行复位。
例如，第七晶体管T7的沟道电流Ids＝k(Vg-Vth) 2，其中，Vg为第七晶体管T7的栅极电压，Vth为第七晶体管T7的阈值电压(约为0V)。因此，沟道电流Ids与栅极电压Vg的平方近似地成正比。由于复位控制节点H的工作电平高于基准信号端Stan的基准信号的高电平，即复位控制节点H的工作电平高于该移位寄存器单元10中其他高电平信号的电平，因此第七晶体管T7的栅极电压Vg得到提高，沟道电流Ids会相应增大。第七晶体管T7可以充分导通，从而对上拉节点PU充分降噪(复位)，进而解决低温环境下降噪晶体管(第七晶体管T7)沟道电流降低导致的上拉节点PU降噪不充分的问题，避免产生多次输出的现象，保证产品的正常工作。
第一控制电路510可以实现为第八晶体管T8和第九晶体管T9。第八晶体管T8的栅极配置为和第一控制节点PD_CN1连接，第八晶体管的第一极配置为和第二电压端VDDo连接，第八晶体管T8的第二极配置为和第一下拉节点PD1连接。第九晶体管T9的栅极配置为和上拉节点PU连接，第九晶体管T9的第一极配置为和第一下拉节点PD1连接，第九晶体管T9的第二极配置为和第一电压端VGL1连接。
第二控制电路520可以实现为第十晶体管T10和第十一晶体管T11。第十晶体管T10的栅极配置为和第二控制节点PD_CN2连接，第十晶体管T10的第一极配置为和第三电压端VDDe连接，第十晶体管T10的第二极配置为和第二下拉节点PD2连接。第十一晶体管T11的栅极配置为和上拉节点PU连接，第十一晶体管T11的第一极配置为和第二下拉节点PD2连接，第十一晶体管T11的第二极配置为和第一电压端VGL1连接。
第三控制电路610可以实现为第十二晶体管T12和第十三晶体管T13。第十二晶体管T12的栅极与第一极连接，且配置为和第二电压端VDDo连接，第十二晶体管T12的第二极配置为和第一控制节点PD_CN1连接。第十三晶体管T13的栅极配置为和上拉节点PU连接，第十三晶体管T13的第一极配置为和第一控制节点PD_CN1连接，第十三晶体管T13的第二极配置为和第一电压端VGL1连接。
第四控制电路620可以实现为第十四晶体管T14和第十五晶体管T15。第十四晶体管T14的栅极与第一极连接，且配置为和第三电压端VDDe连接，第十四晶体管T14的第二极配置为和第二控制节点PD_CN2连接，第十五晶体管T15的栅极配置为和上拉节点PU连接，第十五晶体管T15的第一极配置为和第二控制节点PD_CN2连接，第十五晶体管T15的第二极配置为和第一电压端VGL1连接。
第一节点降噪电路700可以实现为第十六晶体管T16和第十七晶体管T17。第十六晶体管T16的栅极配置为和第一下拉节点PD1连接，第十六晶体管T16的第一极配置为和上拉节点PU连接，第十六晶体管T16的第二极配置为和第一电压端VGL1连接。第十七晶体管T17的栅极配置为和第二下拉节点PD2连接，第十七晶体管T17的第一极配置为和上拉节点PU连接，第十七晶体管T17的第二极配置为和第一电压端VGL1连接。当第一下拉节点PD1为有效电平(例如高电平)时，第十六晶体管T16导通，将上拉节点 PU和第一电压端VGL1电连接，从而可以对上拉节点PU下拉以实现降噪。当第二下拉节点PD2为有效电平(例如高电平)时，第十七晶体管T17导通，同样可以对上拉节点PU进行降噪。
输出降噪电路800可以实现为第十八晶体管T18、第十九晶体管T19、第二十晶体管T20和第二十一晶体管T21。第十八晶体管T18的栅极配置为和第一下拉节点PD1连接，第十八晶体管T18的第一极配置为和移位信号输出端OC连接，第十八晶体管T18的第二极配置为和第一电压端VGL1连接。第十九晶体管T19的栅极配置为和第二下拉节点PD2连接，第十九晶体管T19的第一极配置为和移位信号输出端OC连接，第十九晶体管T19的第二极配置为和第一电压端VGL1连接。第二十晶体管T20的栅极配置为和第一下拉节点PD1连接，第二十晶体管T20的第一极配置为和像素信号输出端OP连接，第二十晶体管T20的第二极配置为和第四电压端VGL2连接以接收第四电压。第二十一晶体管T21的栅极配置为和第二下拉节点PD2连接，第二十一晶体管T21的第一极配置为和像素信号输出端OP连接，第二十一晶体管T21的第二极配置为和第四电压端VGL2连接。
例如，第四电压端VGL2配置为保持输入直流低电平信号，将该直流低电平称为第四电压，以下各实施例与此相同，不再赘述。例如，第四电压端VGL2也可以连接到第一电压端VGL1，将第一电压作为第四电压。当第一下拉节点PD1为有效电平(例如高电平)时，第十八晶体管T18导通，将移位信号输出端OC和第一电压端VGL1电连接，从而可以对移位信号输出端OC下拉以实现降噪；第二十晶体管T20也导通，将像素信号输出端OP和第四电压端VGL2电连接，从而可以对像素信号输出端OP下拉以实现降噪。当第二下拉节点PD2为有效电平(例如高电平)时，第十九晶体管T19和第二十一晶体管T21导通，同样可以对移位信号输出端OC和像素信号输出端OP进行降噪。
第二复位电路900可以实现为第二十二晶体管T22。第二十二晶体管T22的栅极配置为和第二复位端Re2连接以接收第二复位信号，第二十二晶体管T22的第一极配置为和上拉节点PU连接，第二十二晶体管T22的第二极配置为和第一电压端VGL1连接。当第二复位端Re2的第二复位信号为有效电平(例如高电平)时，第二十二晶体管T22导通，将上拉节点PU和第一电压端VGL1电连接，从而对上拉节点PU复位。
需要说明的是，本公开的各实施例中，第一电容C1、第二电容C2和第三电容C3可以是通过工艺制程制作的电容器件，例如通过制作专门的电容电极来实现电容器件，该电容的各个电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现，并且，第一电容C1、第二电容C2和第三电容C3也可以是晶体管之间的寄生电容，可以通过晶体管本身与其他器件、线路来实现。
图7为图5中所示的移位寄存器单元的一种具体实现示例的电路图。该移位寄存器单元10包括第五控制电路500和第六控制电路600，第五控制电路500和第六控制电路600的具体实现方式可以参照图6中所示的移位寄存器单元10的第一控制电路510和第三控制电路610的具体实现方式，此处不再赘述。相应地，该移位寄存器单元10包括第四节点PD和第三控制节点PD_CN。第一节点降噪电路700可以实现为第十六晶体管T16，输出降噪电路800可以实现为第二十晶体管T20。该移位寄存器单元10的各个晶体管的连接方式与图6中所示的移位寄存器单元10类似，此处不再赘述。在该示例中，输出电路200包括一个输出端OT，该输出端OT既用于为级联的其他移位寄存器单元10提供输入信号，又用于为像素电路提供驱动信号。
需要注意的是，在本公开的各个实施例的说明中，复位控制节点H、上拉节点PU、第一下拉节点PD1、第二下拉节点PD2、第四节点PD、第一控制节点PD_CN1、第二控制节点PD_CN2和第三控制节点PD_CN并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管、场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
另外，在本公开的实施例中的晶体管均以N型晶体管为例进行说明，此时，晶体管的第一极是漏极，第二极是源极。需要说明的是，本公开包括但不限于此。例如，本公开的实施例提供的移位寄存器单元10中的一个或多个晶体管也可以采用P型晶体管，此时，晶体管第一极是源极，第二极是漏极，只需将选定类型的晶体管的各极参照本公开的实施例中的相应晶体管的各极 相应连接，并且使相应的电压端提供对应的高电压或低电压即可。例如，本公开的实施例通过P型晶体管实现时，相应地调整信号或电压极性，而且在这种情况下术语“上拉”、“下拉”也分别涵盖了相应电平的绝对值降低、升高以实现相同的晶体管操作(例如导通、截止)。当采用N型晶体管时，可以采用氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)作为薄膜晶体管的有源层，相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及防止漏电流。
图8A为本公开一些实施例提供的一种移位寄存器单元的信号时序图。下面结合图8A所示的信号时序图，对图6所示的移位寄存器单元10的工作原理进行说明，并且这里以各个晶体管为N型晶体管为例进行说明，但是本公开的实施例不限于此。
在图8A中以及下面的描述中，Con、RST、CLK、Stan、INT、VDDo、VDDe、OP、OC等既用于表示相应的信号端，也用于表示相应的信号，以下各实施例与此相同，不再赘述。在图8A所示的第一阶段至第七阶段1-7中，该移位寄存器单元10可以分别进行如下操作。
在第一阶段1，复位控制信号端Con提供高电平信号，第一晶体管T1导通。基准信号端Stan连接到时钟信号端CLK，将时钟信号作为基准信号，此时基准信号为高电平。由于第一电容C1的自举作用，第一电容C1的第二极的电平被抬高至工作电平并对复位控制节点H充电，使复位控制节点H的电平为工作电平。工作电平的幅度A2大于基准信号的幅度A1(即工作电平高于基准信号的电平)，A2与A1的大小关系如图8B所示。第七晶体管T7在复位控制节点H的工作电平的作用下充分导通，从而对上拉节点PU进行复位。第二电压端VDDo提供高电平信号，第十二晶体管T12导通，使第一控制节点PD_CN1为高电平。第八晶体管T8导通，使第一下拉节点PD1为高电平，控制第十六晶体管T16、第十八晶体管T18和第二十晶体管T20导通，从而分别对上拉节点PU、移位信号输出端OC、像素信号输出端OP降噪。此时，第二下拉节点PD2为低电平。
在第二阶段2，复位子信号端RST提供高电平信号，第二晶体管T2和第三晶体管T3导通，从而对第一晶体管T1的栅极和复位控制节点H复位，使第一晶体管T1和第七晶体管T7截止。输入端INT提供高电平信号，第四 晶体管T4导通，上拉节点PU被充电至第一电平(高电平)。第五晶体管T5和第六晶体管T6均导通，将时钟信号端CLK的时钟信号分别输出至移位信号输出端OC和像素信号输出端OP。此时，时钟信号为低电平，因此移位信号输出端OC和像素信号输出端OP输出低电平。第十三晶体管T13和第九晶体管T9均导通。由于第十二晶体管T12和第十三晶体管T13串联分压，第一控制节点PD_CN1被下拉至低电平。第八晶体管T8截止，第一下拉节点PD1被导通的第九晶体管T9下拉至低电平。第十六晶体管T16、第十八晶体管T18和第二十晶体管T20均截止。
在第三阶段3，复位子信号端RST继续提供高电平信号，第二晶体管T2和第三晶体管T3保持导通，使第一晶体管T1和第七晶体管T7保持截止。时钟信号端CLK的时钟信号变为高电平，上拉节点PU的电位因时钟信号耦合作用而进一步升高，第五晶体管T5和第六晶体管T6充分导通，时钟信号的高电平输出至移位信号输出端OC和像素信号输出端OP。第一下拉节点PD1保持为低电平，第十六晶体管T16、第十八晶体管T18和第二十晶体管T20保持截止，不会对输出产生影响。
在第四阶段4，第三电压端VDDe提供高电平信号，第二电压端VDDo提供低电平信号。第十五晶体管T15和第十一晶体管T11在上拉节点PU的高电平的作用下均导通。第十四晶体管T14导通。由于第十四晶体管T14和第十五晶体管T15串联分压，第二控制节点PD_CN2为低电平。第十晶体管T10截止，第二下拉节点PD2在导通的第十一晶体管T11的作用下处于低电平。第十七晶体管T17、第十九晶体管T19和第二十一晶体管T21均截止。此时，第一下拉节点PD1保持为低电平。
在第五阶段5，时钟信号端CLK的时钟信号变为低电平，上拉节点PU的电位因时钟信号耦合作用而有所降低但仍然为高电平，第五晶体管T5和第六晶体管T6保持导通，时钟信号的低电平输出至移位信号输出端OC和像素信号输出端OP。
在第六阶段6，第二复位端Re2提供高电平信号(图8A中未示出)，第二十二晶体管T22导通，将上拉节点PU的电平下拉至低电平。第十一晶体管T11和第十五晶体管T15截止。在第六阶段6的初始时刻，第三电压端VDDe提供高电平信号，第二控制节点PD_CN2被第十四晶体管T14上拉至高电平，第十晶体管T10导通，将第二下拉节点PD2上拉至高电平。第十七 晶体管T17、第十九晶体管T19和第二十一晶体管T21均导通，从而分别对上拉节点PU、移位信号输出端OC、像素信号输出端OP降噪。在第六阶段6，第二电压端VDDo和第三电压端VDDe交替提供高电平信号，使第一下拉节点PD1和第二下拉节点PD2交替为高电平，从而对上拉节点PU、移位信号输出端OC、像素信号输出端OP持续降噪。
在第七阶段7，复位控制信号端Con提供高电平信号，第一晶体管T1导通。基准信号(时钟信号)提供持续的高电平信号。由于第一电容C1的自举作用，第一电容C1的第二极的电平被抬高至工作电平并对复位控制节点H充电，使复位控制节点H的电平为工作电平。工作电平的幅度A2大于基准信号的幅度A1(即工作电平高于基准信号的电平)。第七晶体管T7在复位控制节点H的工作电平的作用下充分导通，从而对上拉节点PU进行复位(降噪)。
例如，第一阶段1为一帧图像扫描开始前的阶段，第七阶段7为一帧图像扫描结束后的阶段。在本公开的各实施例中，可以在第一阶段1和第七阶段7中均使复位控制信号端Con提供高电平信号，从而在一帧图像扫描开始前和结束后均对上拉节点PU进行充分复位(降噪)；也可以仅在第七阶段7使复位控制信号端Con提供高电平信号，从而仅在一帧图像扫描结束后对上拉节点PU进行充分复位(降噪)。例如，当时钟信号端CLK的时钟信号复用为基准信号端Stan的基准信号时，在一帧图像的扫描时段t2，使时钟信号为周期脉冲；在其余时段(例如一帧图像扫描开始前的时段t1和结束后的时段t3)，使时钟信号保持输入直流信号(例如高电平信号)，以便于在第一阶段1和第七阶段7对第一电容C1的第二极的电平进行抬升。
需要说明的是，本公开的各实施例中，当各个晶体管为P型晶体管且控制晶体管导通的有效电平为低电平(该低电平大于0V)时，需要使时钟信号在一帧图像扫描开始前的时段t1和结束后的时段t3保持输入低电平信号，以便于在第一阶段1和第七阶段7对第一电容C1的第二极的电平进行拉低，使该电平低于时钟信号的低电平。
本公开至少一实施例还提供一种栅极驱动电路。该栅极驱动电路包括本公开任一实施例所述的移位寄存器单元。该栅极驱动电路可对第一节点(例如上拉节点)充分降噪，解决低温环境下降噪晶体管沟道电流降低导致的第一节点降噪不充分的问题，从而避免产生多次输出的现象，保证产品的正常 工作。
图9为本公开一些实施例提供的一种栅极驱动电路的示意框图。参考图9，该栅极驱动电路20包括多个级联的移位寄存器单元(SR1-SR6等)。多个移位寄存器单元的数量不受限制，可以根据实际需求而定。例如，移位寄存器单元采用本公开任一实施例所述的移位寄存器单元10。例如，在栅极驱动电路20中，可以部分或全部移位寄存器单元采用本公开任一实施例所述的移位寄存器单元10。例如，该栅极驱动电路20可以采用与薄膜晶体管同样制程的工艺直接集成在显示装置的阵列基板上，以实现逐行扫描驱动功能。
例如，每个移位寄存器单元具有输入端INT、时钟信号端CLK、基准信号端Stan、复位控制信号端Con、复位子信号端RST、第二复位端Re2、移位信号输出端OC和像素信号输出端OP等。例如，每一级移位寄存器单元的基准信号端Stan与时钟信号端CLK连接。例如，除前三级以外，第s级移位寄存器单元的输入端INT与第s-3级移位寄存器单元的移位信号输出端OC连接，s为大于3的整数。例如，除最后四级以外，第m级移位寄存器单元的第二复位端Re2与第m+4级移位寄存器单元的移位信号输出端OC连接，m为大于0的整数。例如，前三级移位寄存器单元的输入端INT与触发信号线STV1连接。例如，最后四级移位寄存器单元的第二复位端Re2与另行提供的复位信号线连接。例如，每一级移位寄存器单元的复位控制信号端Con与复位控制信号线STV0连接，每一级移位寄存器单元的复位子信号端RST与触发信号线STV1连接。每一级移位寄存器单元的像素信号输出端OP与对应行的像素单元连接，以向该行像素单元输出驱动信号。
例如，该栅极驱动电路20还包括第一时钟信号线CLK1、第二时钟信号线CLK2、第三时钟信号线CLK3、第四时钟信号线CLK4、第五时钟信号线CLK5和第六时钟信号线CLK6。各级移位寄存器单元与上述各时钟信号线的连接方式如下并以此类推。
第6n-5级移位寄存器单元(例如，图中第一级移位寄存器单元SR1)的时钟信号端CLK和第一时钟信号线CLK1连接，第6n-4级移位寄存器单元(例如，图中第二级移位寄存器单元SR2)的时钟信号端CLK和第二时钟信号线CLK2连接，第6n-3级移位寄存器单元(例如，图中第三级移位寄存器单元SR3)的时钟信号端CLK和第三时钟信号线CLK3连接，第6n-2级移位寄存器单元(例如，图中第四级移位寄存器单元SR4)的时钟信号端CLK 和第四时钟信号线CLK4连接，第6n-1级移位寄存器单元(例如，图中第五级移位寄存器单元SR5)的时钟信号端CLK和第五时钟信号线CLK5连接，第6n级移位寄存器单元(例如，图中第六级移位寄存器单元SR6)的时钟信号端CLK和第六时钟信号线CLK6连接。这里，n为大于0的整数。
例如，该栅极驱动电路20还可以包括时序控制器T-CON，时序控制器T-CON例如配置为向各级移位寄存器单元提供上述各个时钟信号，时序控制器T-CON还可以配置为提供复位控制信号和复位子信号等。需要说明的是，时序控制器T-CON提供的多个时钟信号彼此之间的相位关系可以根据实际需求而定。在不同的示例中，根据不同的配置，还可以提供更多或更少的时钟信号。例如，该栅极驱动电路20还包括多条电压线，以向各级移位寄存器单元提供多个电压信号。
例如，当采用该栅极驱动电路20驱动一显示面板时，可以将该栅极驱动电路20设置于显示面板的一侧。例如，该显示面板包括多行栅线，栅极驱动电路20中的各级移位寄存器单元的像素信号输出端OP可以配置为依序和多行栅线连接，以用于输出驱动信号。当然，还可以分别在显示面板的两侧设置该栅极驱动电路20，以实现双边驱动，本公开的实施例对栅极驱动电路20的设置方式不作限制。例如，可以在显示面板的一侧设置栅极驱动电路20以用于驱动奇数行栅线，而在显示面板的另一侧设置栅极驱动电路20以用于驱动偶数行栅线。
图10为本公开一些实施例提供的一种栅极驱动电路的信号时序图，该信号时序图为图9中所示的栅极驱动电路20的时序，该栅极驱动电路20中的移位寄存器单元为图6中所示的移位寄存器单元10。栅极驱动电路20的工作原理可参考本公开的实施例中对于移位寄存器单元10的相应描述，这里不再赘述。
栅极驱动电路20在一帧图像扫描时逐行输出，直至最后一行输出后完成一帧图像的显示。在一帧图像扫描结束后，复位控制信号线STV0提供高电平信号，从而对每一级移位寄存器单元的上拉节点PU进行充分复位(降噪)。第一至第六时钟信号线CLK1-CLK6在一帧图像扫描时提供周期脉冲，且各个时钟信号的相位依次延迟有效脉宽的1/3。第一至第六时钟信号线CLK1-CLK6在一帧图像扫描结束后提供高电平信号，以使第一电容C1的第二极的电平相对于该高电平信号进一步抬高，从而达到工作电平。第一至第 六级移位寄存器单元SR1-SR6的像素信号输出端OP的输出信号Out1-Out6的波形依次重叠有效脉宽的1/3。该栅极驱动电路20的输出信号Out1-Out6有重叠，因此可以实现预充电功能，可缩短像素电路的充电时间，有利于实现高刷新率。
需要说明的是，本公开的各实施例中，栅极驱动电路20不局限于图9中描述的级联方式，可以为任意适用的级联方式。当级联方式或时钟信号改变时，第一至第六级移位寄存器单元SR1-SR6的像素信号输出端OP的输出信号Out1-Out6的波形重叠部分也会相应变化，以满足多种应用需求。
本公开至少一实施例还提供一种显示装置。该显示装置包括本公开任一实施例所述的栅极驱动电路。该显示装置中的栅极驱动电路可对第一节点(例如上拉节点)充分降噪，解决低温环境下降噪晶体管沟道电流降低导致的第一节点降噪不充分的问题，从而避免产生多次输出的现象，保证产品的正常工作。
图11为本公开一些实施例提供的一种显示装置的示意框图。参考图11，显示装置30包括栅极驱动电路20，栅极驱动电路20为本公开任一实施例所述的栅极驱动电路。例如，显示装置30可以为液晶面板、液晶电视、显示器、有机发光二极管(Organic Light-Emitting Diode,OLED)面板、OLED电视、电子纸显示装置、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开的实施例对此不作限制。显示装置30的技术效果可以参考上述实施例中关于移位寄存器单元10和栅极驱动电路20的相应描述，这里不再赘述。
例如，在一个示例中，显示装置30包括显示面板3000、栅极驱动器3010、定时控制器3020和数据驱动器3030。显示面板3000包括根据多条扫描线GL和多条数据线DL交叉限定的多个像素单元P；栅极驱动器3010用于驱动多条扫描线GL；数据驱动器3030用于驱动多条数据线DL；定时控制器3020用于处理从显示装置30外部输入的图像数据RGB，向数据驱动器3030提供处理的图像数据RGB以及向栅极驱动器3010和数据驱动器3030输出扫描控制信号GCS和数据控制信号DCS，以对栅极驱动器3010和数据驱动器3030进行控制。
例如，栅极驱动器3010包括上述任一实施例中提供的栅极驱动电路20。栅极驱动电路20中的多个移位寄存器单元10的像素信号输出端OP与多条 扫描线GL对应连接。多条扫描线GL与排列为多行的像素单元P对应连接。栅极驱动电路20中的各级移位寄存器单元10的像素信号输出端OP依序输出信号到多条扫描线GL，以使显示面板3000中的多行像素单元P实现逐行扫描。例如，栅极驱动器3010可以实现为半导体芯片，也可以集成在显示面板3000中以构成GOA电路。
例如，数据驱动器3030使用参考伽玛电压根据源自定时控制器3020的多个数据控制信号DCS将从定时控制器3020输入的数字图像数据RGB转换成数据信号。数据驱动器3030向多条数据线DL提供转换的数据信号。例如，数据驱动器3030可以实现为半导体芯片。
例如，定时控制器3020对外部输入的图像数据RGB进行处理以匹配显示面板3000的大小和分辨率，然后向数据驱动器3030提供处理后的图像数据。定时控制器3020使用从显示装置30外部输入的同步信号(例如点时钟DCLK、数据使能信号DE、水平同步信号Hsync以及垂直同步信号Vsync)产生多条扫描控制信号GCS和多条数据控制信号DCS。定时控制器3020分别向栅极驱动器3010和数据驱动器3030提供产生的扫描控制信号GCS和数据控制信号DCS，以用于栅极驱动器3010和数据驱动器3030的控制。
该显示装置30还可以包括其他部件，例如信号解码电路、电压转换电路等，这些部件例如可以采用已有的常规部件，这里不再详述。
本公开至少一实施例还提供一种移位寄存器单元的驱动方法，可以用于驱动本公开任一实施例所述的移位寄存器单元10。利用该驱动方法，可以对第一节点(例如上拉节点)充分降噪，解决低温环境下降噪晶体管沟道电流降低导致的第一节点降噪不充分的问题，从而避免产生多次输出的现象，保证产品的正常工作。
例如，在一个示例中，该移位寄存器单元10的驱动方法包括如下操作：
在输入阶段(即前述的第二阶段2)，输入电路100响应于输入信号控制第一节点(例如上拉节点PU)的电平至第一电平，输出电路200输出时钟信号的第二电平至输出端OT；
在输出阶段(即前述的第三阶段3和第四阶段4)，输出电路200输出时钟信号的第三电平至输出端OT；
在第一复位阶段(即前述的第一阶段1或第七阶段7)，复位控制电路400响应于复位控制信号和基准信号向第一复位电路300输入第一复位信号 Re1，以开启第一复位电路300，使得第一复位电路300对上拉节点PU进行复位。
例如，第二电平为低电平，第三电平为高电平。例如，第一电平为高电平，且第一电平可以与第三电平相同或不同。
例如，在一个示例中，时钟信号和基准信号为同一个信号，且在输入阶段和输出阶段为周期脉冲，在第一复位阶段为直流信号(例如高电平或低电平信号)。
需要说明的是，关于该驱动方法的详细描述以及技术效果可以参考本公开的实施例中对于移位寄存器单元10和栅极驱动电路20的相应描述，这里不再赘述。
有以下几点需要说明：
(1)本公开实施例附图只涉及到本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种移位寄存器单元，包括输入电路、输出电路、第一复位电路和复位控制电路；其中，
    所述输入电路配置为响应于输入信号对第一节点的电平进行控制；
    所述输出电路配置为在所述第一节点的电平的控制下，将时钟信号输出至输出端；
    所述第一复位电路配置为响应于第一复位信号对所述第一节点进行复位；
    所述复位控制电路配置为响应于复位控制信号和基准信号向所述第一复位电路输入所述第一复位信号，以开启所述第一复位电路。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述复位控制电路还配置为使得所述第一复位信号的电平的幅度大于所述基准信号的电平的幅度。
  3. 根据权利要求1或2所述的移位寄存器单元，其中，所述复位控制电路包括：
    驱动子电路，配置为根据所述复位控制信号和所述基准信号对复位控制节点的电平进行调节，并将所述复位控制节点的电平作为所述第一复位信号；
    复位子电路，配置为响应于复位子信号对所述复位控制节点和所述驱动子电路进行复位。
  4. 根据权利要求3所述的移位寄存器单元，其中，
    所述驱动子电路包括第一电容和第一晶体管，所述第一电容的第一极配置为和复位控制信号端连接以接收所述复位控制信号，所述第一电容的第二极配置为和基准信号端连接以接收所述基准信号，所述第一晶体管的栅极配置为和所述第一电容的第一极连接，所述第一晶体管的第一极配置为和所述第一电容的第二极连接，所述第一晶体管的第二极配置为和所述复位控制节点连接；
    所述复位子电路包括第二晶体管和第三晶体管，所述第二晶体管的栅极配置为和复位子信号端连接以接收所述复位子信号，所述第二晶体管的第一极配置为和所述第一晶体管的栅极连接，所述第二晶体管的第二极配置为和第一电压端连接以接收第一电压，所述第三晶体管的栅极配置为和所述复位 子信号端连接以接收所述复位子信号，所述第三晶体管的第一极配置为和所述复位控制节点连接，所述第三晶体管的第二极配置为和所述第一电压端连接。
  5. 根据权利要求4所述的移位寄存器单元，其中，所述基准信号端与时钟信号端连接以接收所述时钟信号作为所述基准信号。
  6. 根据权利要求1-5任一所述的移位寄存器单元，还包括第一控制电路、第二控制电路、第三控制电路、第四控制电路、第一节点降噪电路和输出降噪电路；其中，
    所述第一控制电路配置为在所述第一节点和第一控制节点的电平的控制下，对第二节点的电平进行控制；
    所述第二控制电路配置为在所述第一节点和第二控制节点的电平的控制下，对第三节点的电平进行控制；
    所述第三控制电路配置为在所述第一节点的电平的控制下，对所述第一控制节点的电平进行控制；
    所述第四控制电路配置为在所述第一节点的电平的控制下，对所述第二控制节点的电平进行控制；
    所述第一节点降噪电路配置为在所述第二节点或所述第三节点的电平的控制下，对所述第一节点进行降噪；
    所述输出降噪电路配置为在所述第二节点或所述第三节点的电平的控制下，对所述输出端进行降噪。
  7. 根据权利要求6所述的移位寄存器单元，其中，所述输入电路包括第四晶体管；
    所述第四晶体管的栅极与第一极连接且配置为和输入端连接以接收所述输入信号，所述第四晶体管的第二极配置为和所述第一节点连接。
  8. 根据权利要求6或7所述的移位寄存器单元，其中，所述输出电路的输出端包括至少一个移位信号输出端和至少一个像素信号输出端。
  9. 根据权利要求8所述的移位寄存器单元，其中，所述输出电路包括第五晶体管、第六晶体管和第二电容；
    所述第五晶体管的栅极配置为和所述第一节点连接，所述第五晶体管的第一极配置为和时钟信号端连接以接收所述时钟信号，所述第五晶体管的第二极配置为和所述移位信号输出端连接；
    所述第六晶体管的栅极配置为和所述第一节点连接，所述第六晶体管的第一极配置为和所述时钟信号端连接以接收所述时钟信号，所述第六晶体管的第二极配置为和所述像素信号输出端连接；
    所述第二电容的第一极配置为和所述第一节点连接，所述第二电容的第二极配置为和所述第六晶体管的第二极或所述第五晶体管的第二极连接。
  10. 根据权利要求3-5任一所述的移位寄存器单元，其中，所述第一复位电路包括第七晶体管；
    所述第七晶体管的栅极配置为和所述复位控制节点连接，所述第七晶体管的第一极配置为和所述第一节点连接，所述第七晶体管的第二极配置为和第一电压端连接以接收第一电压。
  11. 根据权利要求6-9任一所述的移位寄存器单元，其中，
    所述第一控制电路包括第八晶体管和第九晶体管，所述第八晶体管的栅极配置为和所述第一控制节点连接，所述第八晶体管的第一极配置为和第二电压端连接以接收第二电压，所述第八晶体管的第二极配置为和所述第二节点连接，所述第九晶体管的栅极配置为和所述第一节点连接，所述第九晶体管的第一极配置为和所述第二节点连接，所述第九晶体管的第二极配置为和第一电压端连接以接收第一电压；
    所述第二控制电路包括第十晶体管和第十一晶体管，所述第十晶体管的栅极配置为和所述第二控制节点连接，所述第十晶体管的第一极配置为和第三电压端连接以接收第三电压，所述第十晶体管的第二极配置为和所述第三节点连接，所述第十一晶体管的栅极配置为和所述第一节点连接，所述第十一晶体管的第一极配置为和所述第三节点连接，所述第十一晶体管的第二极配置为和所述第一电压端连接。
  12. 根据权利要求6-9、11任一所述的移位寄存器单元，其中，
    所述第三控制电路包括第十二晶体管和第十三晶体管，所述第十二晶体管的栅极与第一极连接且配置为和第二电压端连接以接收第二电压，所述第十二晶体管的第二极配置为和所述第一控制节点连接，所述第十三晶体管的栅极配置为和所述第一节点连接，所述第十三晶体管的第一极配置为和所述第一控制节点连接，所述第十三晶体管的第二极配置为和第一电压端连接以接收第一电压；
    所述第四控制电路包括第十四晶体管和第十五晶体管，所述第十四晶体 管的栅极与第一极连接且配置为和第三电压端连接以接收第三电压，所述第十四晶体管的第二极配置为和所述第二控制节点连接，所述第十五晶体管的栅极配置为和所述第一节点连接，所述第十五晶体管的第一极配置为和所述第二控制节点连接，所述第十五晶体管的第二极配置为和所述第一电压端连接。
  13. 根据权利要求6-9、11、12任一所述的移位寄存器单元，其中，所述第一节点降噪电路包括第十六晶体管和第十七晶体管；
    所述第十六晶体管的栅极配置为和所述第二节点连接，所述第十六晶体管的第一极配置为和所述第一节点连接，所述第十六晶体管的第二极配置为和第一电压端连接以接收第一电压；
    所述第十七晶体管的栅极配置为和所述第三节点连接，所述第十七晶体管的第一极配置为和所述第一节点连接，所述第十七晶体管的第二极配置为和所述第一电压端连接。
  14. 根据权利要求8或9所述的移位寄存器单元，其中，所述输出降噪电路包括第十八晶体管、第十九晶体管、第二十晶体管和第二十一晶体管；
    所述第十八晶体管的栅极配置为和所述第二节点连接，所述第十八晶体管的第一极配置为和所述移位信号输出端连接，所述第十八晶体管的第二极配置为和第一电压端连接以接收第一电压；
    所述第十九晶体管的栅极配置为和所述第三节点连接，所述第十九晶体管的第一极配置为和所述移位信号输出端连接，所述第十九晶体管的第二极配置为和所述第一电压端连接；
    所述第二十晶体管的栅极配置为和所述第二节点连接，所述第二十晶体管的第一极配置为和所述像素信号输出端连接，所述第二十晶体管的第二极配置为和第四电压端连接以接收第四电压；
    所述第二十一晶体管的栅极配置为和所述第三节点连接，所述第二十一晶体管的第一极配置为和所述像素信号输出端连接，所述第二十一晶体管的第二极配置为和所述第四电压端连接。
  15. 根据权利要求6-9、11-13任一所述的移位寄存器单元，还包括第二复位电路；其中，
    所述第二复位电路配置为响应于第二复位信号对所述第一节点进行复位。
  16. 根据权利要求15所述的移位寄存器单元，其中，所述第二复位电路包括第二十二晶体管；
    所述第二十二晶体管的栅极配置为和第二复位端连接以接收所述第二复位信号，所述第二十二晶体管的第一极配置为和所述第一节点连接，所述第二十二晶体管的第二极配置为和第一电压端连接以接收第一电压。
  17. 一种栅极驱动电路，包括如权利要求1-16任一所述的移位寄存器单元。
  18. 一种显示装置，包括如权利要求17所述的栅极驱动电路。
  19. 一种如权利要求1-16任一所述的移位寄存器单元的驱动方法，包括：
    输入阶段，所述输入电路响应于所述输入信号控制所述第一节点的电平至第一电平，所述输出电路输出所述时钟信号的第二电平至所述输出端；
    输出阶段，所述输出电路输出所述时钟信号的第三电平至所述输出端；
    第一复位阶段，所述复位控制电路响应于所述复位控制信号和所述基准信号向所述第一复位电路输入所述第一复位信号，以开启所述第一复位电路，使得所述第一复位电路对所述第一节点进行复位。
  20. 根据权利要求19所述的移位寄存器单元的驱动方法，其中，所述时钟信号和所述基准信号为同一个信号，且在所述输入阶段和所述输出阶段为周期脉冲，在所述第一复位阶段为直流信号。
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