WO2020048305A1 - 移位寄存器单元、栅极驱动电路、显示装置及驱动方法 - Google Patents

移位寄存器单元、栅极驱动电路、显示装置及驱动方法 Download PDF

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Publication number
WO2020048305A1
WO2020048305A1 PCT/CN2019/101103 CN2019101103W WO2020048305A1 WO 2020048305 A1 WO2020048305 A1 WO 2020048305A1 CN 2019101103 W CN2019101103 W CN 2019101103W WO 2020048305 A1 WO2020048305 A1 WO 2020048305A1
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Prior art keywords
node
transistor
pole
output
terminal
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PCT/CN2019/101103
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English (en)
French (fr)
Inventor
谢勇贤
刘金良
王慧
张淼
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US16/641,737 priority Critical patent/US11132934B2/en
Publication of WO2020048305A1 publication Critical patent/WO2020048305A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3433—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices
    • G09G3/344—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices based on particles moving in a fluid or in a gas, e.g. electrophoretic devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • Embodiments of the present disclosure relate to a shift register unit, a gate driving circuit, a display device, and a driving method.
  • a pixel array of a liquid crystal display panel generally includes a plurality of rows of gate lines and a plurality of columns of data lines interleaved with the plurality of rows of gate lines.
  • the gate line can be driven by the integrated driving circuit.
  • gate line driving circuits can also be directly integrated on thin film transistor array substrates to form GOA (Gate Driver On Array) to drive gate lines. .
  • a GOA including a plurality of cascaded shift register units may be used to provide switching voltage signals (scanning signals) for a plurality of rows of gate lines of a pixel array, thereby controlling, for example, the plurality of rows of gate lines to be sequentially turned on, and simultaneously by the data lines.
  • Data signals are provided to the pixel units of the corresponding rows in the pixel array to form the gray voltages required for each gray level of the display image at each pixel unit, and then a frame of image is displayed.
  • Current display panels increasingly use GOA technology to drive grid lines. GOA technology helps to realize the narrow bezel design of the display panel and can reduce the production cost of the display panel.
  • At least one embodiment of the present disclosure provides a shift register unit including an input circuit, an output circuit, and a first node control circuit.
  • the input circuit is connected to a first node and is configured to charge the first node in response to an input signal;
  • the output circuit is connected to the first node and configured to be at a level of the first node Outputting an output signal under the control of a signal;
  • the first node control circuit is respectively connected to the first node and a precharge control terminal, and is configured to receive a precharge control signal from the precharge control terminal and In response to the precharge control signal, the first node is charged before the output terminal outputs the output signal.
  • the input circuit is connected to the first node
  • the output circuit includes the output terminal
  • the output circuit is connected to the first node Connected
  • the first node control circuit is connected to the first node and the precharge control terminal, respectively.
  • the shift register unit provided by at least one embodiment of the present disclosure further includes an output control circuit.
  • the output control circuit is respectively connected to the output terminal and the pre-charge control terminal, and is configured to receive the pre-charge control signal from the pre-charge control terminal and respond to the pre-charge control signal, The output is controlled to an inactive output level during non-output periods.
  • the first node control circuit includes a first capacitor.
  • a first pole of the first capacitor is connected to the first node, and a second pole of the first capacitor is connected to the precharge control terminal to receive the precharge control signal.
  • the output control circuit includes a first transistor.
  • a gate of the first transistor is connected to the precharge control terminal to receive the precharge control signal, a first pole of the first transistor is connected to the output terminal, and a second pole of the first transistor Connected to the first voltage terminal for receiving a first voltage.
  • the shift register unit provided by at least one embodiment of the present disclosure further includes a first node reset circuit.
  • the first node reset circuit is connected to the first node and is configured to reset the first node in response to a reset signal.
  • the shift register unit provided by at least one embodiment of the present disclosure further includes a second node control circuit, a first node noise reduction circuit, and an output noise reduction circuit.
  • the second node control circuit is respectively connected to the first node and the second node, and is configured to control the level of the second node under the control of the level signal of the first node;
  • the first node noise reduction circuit is connected to the first node and the second node, and is configured to perform noise reduction on the first node under the control of the level signal of the second node;
  • An output noise reduction circuit is connected to the second node and the output terminal, and is configured to perform noise reduction on the output terminal under the control of the level signal of the second node.
  • the output terminal includes a shift output terminal and at least one scan signal output terminal.
  • the at least one scan signal output terminal includes a scan signal output terminal
  • the output circuit includes a second transistor, a third transistor, and a second capacitor.
  • a gate of the second transistor is connected to the first node, a first pole of the second transistor is connected to a clock signal terminal to receive a clock signal, a second pole of the second transistor and the shift output
  • a gate of the third transistor is connected to the first node, a first pole of the third transistor is connected to the clock signal terminal to receive the clock signal, and a second of the third transistor
  • Electrode is connected to the scan signal output terminal; the first electrode of the second capacitor is connected to the first node, and the second electrode of the second capacitor is connected to the scan signal output terminal or the shift output terminal Connection, the clock signal is transmitted to the output terminal as the output signal.
  • the shift register unit provided by at least one embodiment of the present disclosure further includes: a first node reset circuit, a total reset circuit, a second node control circuit, a first node noise reduction circuit, and an output noise reduction circuit;
  • a node reset circuit is connected to the first node and configured to reset the first node in response to a reset signal;
  • the total reset circuit is connected to the first node and configured to respond to the first node in response to a total reset signal.
  • a node is reset;
  • the second node control circuit is respectively connected to the first node, the second node, and the third node, and is configured to control the first node under the control of the level signal of the first node;
  • the level of the two nodes and the level of the third node are controlled;
  • the noise reduction circuit of the first node is connected to the first node and the second node, and is configured to be at the level of the second node Under the control of the signal, perform noise reduction on the first node;
  • the output noise reduction circuit is connected to the second node and the output terminal, and is configured to control the level signal at the second node Performing noise reduction on the output terminal;
  • the first node control circuit includes: a first capacitor, a first pole of the first capacitor is connected to the first node, and a second pole of the first capacitor is connected to The precharge control terminal is connected to receive the precharge control signal;
  • the output control circuit includes: a first transistor, a gate of the first transistor is connected to the precharge
  • the gate of the seven transistors is connected to a first control node, the first pole of the seventh transistor and a third voltage terminal are connected to receive a third voltage, and the second pole of the seventh transistor and the second node Connected; the gate of the eighth transistor is connected to the first node, the first pole of the eighth transistor is connected to the second node, the second pole of the eighth transistor and the second voltage A terminal of the ninth transistor and its own first electrode are electrically connected to each other, and are configured to be connected to the third voltage terminal for receiving the first voltage Three voltages of the ninth transistor A second pole is connected to the first control node; a gate of the tenth transistor is connected to the first node, a first pole of the tenth transistor is connected to the first control node, and the tenth transistor A second electrode of the second electrode is connected to the second voltage terminal for receiving the second voltage; a gate of the twenty-seventh transistor is connected to a second control node, and a first electrode of the twenty-seventh transistor Connected to a fourth voltage
  • the second pole is connected to the second control node; And a first pole of the twentieth transistor are connected to the second control node, and a second pole of the twentieth transistor is connected to the second voltage terminal for receiving the A second voltage;
  • the first node noise reduction circuit includes an eleventh transistor and a twenty-first transistor, a gate of the eleventh transistor is connected to the second node, and a first of the eleventh transistor And the second node of the eleventh transistor is connected to the second voltage terminal for receiving the second voltage;
  • the gate of the twenty-first transistor and the A third node is connected, a first pole of the twenty-first transistor is connected to the first node, and a second pole of the twenty-first transistor is connected to the second voltage terminal for receiving the first node Two voltages;
  • the output noise reduction circuit may be implemented as a twelfth transistor, a twenty-second transistor, a thirteenth transistor, and a twenty-third transistor, and a gate of the twelfth transistor is connected to the second node ,
  • the gate of the twenty-third transistor is connected to the third node, the first pole of the twenty-third transistor is connected to the scan signal output terminal, so The second pole of the twenty-third transistor is connected to the first voltage terminal for receiving the first voltage.
  • At least one embodiment of the present disclosure also provides a gate driving circuit including a plurality of cascaded shift register units provided by any one of the embodiments of the present disclosure.
  • the pre-charge control terminals of the shift register units of the other stages are separated by at least m stages.
  • the output terminals of the upper-level shift register unit are connected; except for the first to m-th stage shift register units, the input terminals of the other stages of the shift register unit and the output terminals of the upper-stage shift register unit spaced m-1 apart therefrom Connection; except for the last m-stage shift register units, the reset ends of the other stages of the shift register units are connected to the output ends of the lower-stage shift register units separated by m-1 stages; where m is an integer greater than 2.
  • At least one embodiment of the present disclosure also provides a display device including a gate driving circuit provided by any one of the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure also provides a method for driving a shift register unit, including: in a first stage, the first node control circuit charges the first node in response to the precharge control signal; the second Phase, the input circuit charges the first node in response to an input signal; in the third phase, the output circuit controls the output signal at the output under the control of the level signal of the first node Output.
  • the shift register unit further includes an output control circuit
  • the first stage of the driving method further includes: the output control circuit is responsive to the pre- Charge the control signal to control the output terminal at an invalid output level.
  • FIG. 1 is a schematic diagram of a shift register unit provided by at least one embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of another shift register unit provided by at least one embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of still another shift register unit provided by at least one embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of still another shift register unit provided by at least one embodiment of the present disclosure.
  • FIG. 5 is a schematic circuit diagram of a specific implementation example of the shift register unit shown in FIG. 4;
  • FIG. 6 is a schematic circuit diagram of another specific implementation example of the shift register unit shown in FIG. 4;
  • FIG. 7 is a schematic diagram of a gate driving circuit provided by at least one embodiment of the present disclosure.
  • FIG. 8A is a signal timing diagram corresponding to an example when the gate driving circuit shown in FIG. 7 operates;
  • FIG. 8B is a signal timing diagram corresponding to another example when the gate driving circuit shown in FIG. 7 operates.
  • FIG. 9 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure.
  • the refresh frequency of the display screen is continuously increased, for example, to 144 Hz.
  • a display screen with a refresh rate of 144Hz can display a smoother game scene, especially it can eliminate the smear phenomenon caused by the display panel in 3D mode due to the refresh rate being too low.
  • the high refresh rate of the display screen means that the charging time of the GOA is shortened during the display of each frame of the image. Therefore, in order to meet the charging rate, the GOA is usually charged with a higher power supply voltage.
  • At least one embodiment of the present disclosure provides a shift register unit including an input circuit, an output circuit, and a first node control circuit.
  • the input circuit is connected to the first node and is configured to charge the first node in response to the input signal;
  • the output circuit is connected to the first node and configured to output the output signal at the output under the control of the level signal of the first node
  • the first node control circuit is respectively connected to the first node and the pre-charge control terminal, and is configured to receive the pre-charge control signal from the pre-charge control terminal and respond to the pre-charge control signal, before the output terminal outputs the output signal, Charge the first node.
  • Embodiments of the present disclosure also provide a gate driving circuit, a display device, and a driving method corresponding to the above-mentioned shift register unit.
  • the shift register unit provided by the above embodiments of the present disclosure adopts the design of a dual bootstrap capacitor, which can improve the charging capability of the first node (for example, a pull-up node) to solve the problem caused by the characteristic drift of the transistor at a high refresh frequency
  • the problem of insufficient charging of the first node (for example, the pull-up node) improves the stability of the circuit structure of the shift register unit and prolongs the service life of the display panel.
  • FIG. 1 is a schematic diagram of a shift register unit provided by at least one embodiment of the present disclosure.
  • the shift register unit 100 includes an input circuit 110, an output circuit 120, a first node N1 and a first node control circuit 130.
  • a gate driving circuit can be obtained by cascading a plurality of the shift register units 100.
  • the gate driving circuit is used to drive a display panel, and sequentially provides scanning signals for a plurality of gate lines of the display panel, thereby displaying a frame on the display panel. Progressive or interlaced scanning is performed during the screen.
  • the input circuit 110 is configured to charge the first node N1 in response to an input signal.
  • the input circuit 110 is connected to the input signal terminal INT and the first node N1 (for example, a pull-up node here), and is configured to be turned on under the control of the input signal provided by the input signal terminal INT, so that the input
  • the signal terminal INT is connected to the first node N1, so that the input signal provided by the input signal terminal INT is input to the first node N1, and the potential of the first node N1 is charged (for example, pulled up) to the working potential.
  • the output circuit 120 includes an output terminal OUT, and is configured to output an output signal at the output terminal OUT under the control of the level signal of the first node N1.
  • the output circuit 120 is connected to the clock signal terminal CLK, the first node N1, and the output terminal OUT, and is configured to be turned on under the control of the level signal of the first node N1 to provide the clock signal terminal CLK.
  • the clock signal is transmitted to the output terminal OUT and output as an output signal at the output terminal OUT.
  • the output circuit 120 is also connected to a voltage terminal (for example, a high voltage terminal), and uses a clock signal provided by the clock signal terminal CLK as a control signal to control whether the voltage terminal is connected to the output terminal OUT. Thereby, it is controlled whether the voltage signal at the voltage terminal is transmitted to the output terminal OUT and output as an output signal at the output terminal OUT.
  • the output terminal OUT may include multiple output terminals, such as a shift output terminal and at least one scan signal output terminal, so as to output an output signal such as a clock signal provided by the clock signal terminal CLK to the shift output terminal and the scan signal output terminal.
  • at least one scan signal output terminal includes one scan signal output terminal.
  • the shift output terminal is connected to the upper and lower stage shift register unit 100 adjacent thereto to provide a precharge control signal, an input signal or a reset signal to the upper and lower stage shift register unit 100 connected thereto, and the scan signal output is connected to the display panel.
  • the pixel circuit of the pixel unit is connected to provide a driving signal to the pixel circuit.
  • Setting the shift output terminal and the scan signal output terminal separately can reduce the influence of the load and signal in the pixel area on the cascaded shift register unit.
  • the shift output terminal and the scan signal output terminal output the same output signal. It should be noted that, in other examples, when multiple scanning signal output terminals are included, each scanning signal output terminal may also output different output signals.
  • the specific settings are determined according to the actual situation. The embodiments of the present disclosure do not deal with this. limit.
  • the first node control circuit 130 is respectively connected to the first node N1 and the precharge control terminal Ctr, and is configured to receive a precharge control signal from the precharge control terminal Ctr, and in response to the precharge control signal, output a clock signal at the output terminal OUT.
  • the first node N1 was previously charged. For example, the timing of the precharge control signal provided by the precharge control terminal Ctr is earlier than the input signal.
  • the first node control circuit 130 can charge the first node N1 in advance, and at the same time, Under the control of the level signal of the first node N1, perform a control operation (for example, a pull-down discharge) on the second node (for example, a pull-down node here) to prevent the level of the first node N1 from being controlled by the second node N2.
  • the transistor for example, the eleventh transistor T11 is discharged, so the charging capacity of the first node N1 in the circuit can be improved.
  • the shift register unit provided by the above embodiments of the present disclosure can improve the charging capability of the pull-up node (ie, the first node N1) to solve the problem of insufficient charging of the pull-up node due to the characteristic drift of the transistor at a high refresh frequency.
  • the stability of the circuit structure of the shift register unit is improved, and the service life of the display panel is extended.
  • FIG. 2 is a schematic block diagram of another shift register unit provided by at least one embodiment of the present disclosure. As shown in FIG. 2, the shift register unit 100 further includes an output control circuit 140. It should be noted that other circuit structures of the shift register unit 100 shown in FIG. 2 are basically the same as the shift register unit 100 shown in FIG. 1, and details are not repeated herein.
  • the output control circuit 140 is connected to the output terminal OUT and the pre-charge control terminal Ctr, and is configured to receive a pre-charge control signal from the pre-charge control terminal Ctr, and in response to the pre-charge control signal, the control output OUT is maintained at an invalid output during a non-output period. Level.
  • the output control circuit 140 is connected to the precharge control terminal Ctr, the output terminal OUT, and the first voltage terminal VGL1 (for example, providing a low level) or a separately provided voltage terminal (for example, a low voltage terminal), and is configured to respond to
  • the pre-charge control signal received by the pre-charge control terminal Ctr connects the output terminal OUT to the first voltage terminal VGL1 to achieve noise reduction on the output terminal OUT, so as to avoid pre-processing the first node N1 through the first node control circuit 130.
  • the charging stage causes a false output at the output terminal OUT.
  • the “effective output level” of the shift register unit refers to a switching transistor in a pixel circuit of a display panel connected to it can be turned on so that writing into the pixel circuit can be performed.
  • the level of the data signal correspondingly, "invalid output level” refers to a level at which a switching transistor in a pixel circuit connected thereto cannot be turned on (that is, the switching transistor is turned off).
  • the effective output level may be higher or lower than the invalid output level.
  • the shift register unit outputs a square wave pulse signal at the output end during operation.
  • the effective output level corresponds to the level of the square wave pulse portion of the square wave pulse signal, and the invalid output level corresponds to the non-square wave pulse. Partial level.
  • the input circuit and output circuit (and the first node N1) included in the shift register unit shown in Figs. 1 and 2 can be implemented in various forms, such as the basic structure of 4T1C, and in different implementations, these
  • the shift register unit may further include other functional modules, for example, see the following description, however, the embodiments of the present disclosure are not limited to these specific forms.
  • FIG. 3 is a schematic block diagram of still another shift register unit according to at least one embodiment of the present disclosure.
  • the shift register unit 100 further includes a first node reset circuit 150. It should be noted that other circuit structures of the shift register unit 100 shown in FIG. 3 are basically the same as the shift register unit 100 shown in FIG. 2, and details are not repeated herein.
  • the first node reset circuit 150 is connected to the first node N1 and is configured to reset the first node N1 in response to a reset signal.
  • the first node reset circuit 150 may be configured to be connected to the first node N1, the second voltage terminal VGL2 (for example, providing a low level) or a separately provided voltage terminal (for example, a low voltage terminal), and the reset terminal RST. Therefore, under the control of the reset signal inputted from the reset terminal RST, the first node N1 and the second voltage terminal VGL2 or the low voltage terminal can be electrically connected to reset the first node N1.
  • FIG. 4 is a schematic block diagram of still another shift register unit provided by at least one embodiment of the present disclosure.
  • the shift register unit 100 further includes a second node control circuit 160, a first node noise reduction circuit 170, and an output noise reduction circuit 180. It should be noted that other circuit structures of the shift register unit 100 shown in FIG. 4 are basically the same as those of the shift register unit 100 shown in FIG. 3, and details are not repeated here.
  • the second node control circuit 160 is connected to the first node N1 and the second node N2, and is configured to control the level of the second node N2 under the control of the level signal of the first node N1.
  • the second node control circuit 160 when the first node N1 is at a low level, the second node control circuit 160 causes the second node N2 to be connected to one of the third voltage terminal VGH1 or the fourth voltage terminal VGH2, thereby pulling up the second node N2 to a high voltage.
  • the first node N1 is at a high level, for example, the second node N2 is connected to the second voltage terminal VGL2 or a separately provided voltage terminal (for example, a low voltage terminal), thereby pulling down the second node N2 to a low level .
  • the second node control circuit 160 may be implemented as an inverter, which is not limited in the embodiments of the present disclosure.
  • the second node control circuit 160 may further include a third node (not shown in the figure).
  • the level of the second node N2 is affected by the level of the first node N1 and The third voltage control provided by the third voltage terminal VGH1, and the level of the third node N3 is controlled by the level of the first node N1 and the fourth voltage provided by the fourth voltage terminal VGH2.
  • the specific connection method will be described in detail below. .
  • the third voltage terminal VGH1 and the fourth voltage terminal VGH2 may be set to alternately input a high level, that is, when the third voltage terminal VGH1 inputs a high level, the fourth voltage terminal VGH1 inputs a low level, When the third voltage terminal VGH1 is input with a low level, the fourth voltage terminal VGH2 is input with a high level, so that the second node N2 and the third node N3 work alternately, so that the transistors connected thereto can work alternately, extending the use of these transistors life.
  • the third voltage terminal VGH1 and the fourth voltage terminal VGH2 may also be replaced with a clock signal terminal that alternately provides a high level (or a DC low level when the implemented transistor is a P-type).
  • the embodiments of the present disclosure are not limited thereto.
  • the first node noise reduction circuit 170 is connected to the first node N1 and the second node N2, and is configured to perform noise reduction on the first node N1 under the control of the level of the second node N2.
  • the first node noise reduction circuit 170 is connected to the first node N1, the second node N2, and the second voltage terminal VGL2, and is configured to be turned on when the second node N2 is, for example, a high level, so that the first node N1 and the first node N1
  • the two voltage terminals VGL2 or a separately provided voltage terminal are connected to pull down the potential of the first node N1 to a non-working potential to achieve noise reduction on the first node N1.
  • the output noise reduction circuit 180 is connected to the second node N2 and the output terminal OUT, and is configured to perform noise reduction on the output terminal OUT under the control of the level of the second node N2.
  • the output noise reduction circuit 180 is connected to the second node N2, the second voltage terminal VGL2, and the output terminal OUT, and is configured to be turned on when the second node N2 is at a high level, for example, so that the output terminal OUT and the second voltage terminal VGL2 Or a voltage terminal (for example, a low voltage terminal) provided separately is connected to achieve noise reduction on the output terminal OUT.
  • the shift register unit 100 further includes a total reset circuit 190.
  • the total reset circuit 190 is connected to the first node N1 and is configured to reset the first node N1 in response to the total reset signal.
  • the total reset circuit 190 may be configured to be connected to the first node N1, the second voltage terminal VGL2 (for example, providing a low level) or a separately provided voltage terminal (for example, a low voltage terminal), and the total reset terminal TRST, so that The first node N1 may be electrically connected to the second voltage terminal VGL2 or the low voltage terminal under the control of the total reset signal input from the total reset terminal TRST to reset the first node N1.
  • the first voltage terminal VGL1 is configured to provide a DC low-level signal (for example, a low-level portion that is lower than or equal to the clock signal), such as ground.
  • a DC low-level signal for example, a low-level portion that is lower than or equal to the clock signal
  • the DC low-level signal is referred to as a first voltage.
  • the following The embodiments are the same and will not be described again.
  • the second voltage terminal VGL2 is configured to provide a DC low-level signal (for example, lower than or equal to a low-level portion of a clock signal), such as ground, and this DC low-level signal is referred to as a second voltage, for example, the The second voltage may be less than or equal to the first voltage, and the following embodiments are the same, and will not be described again.
  • a DC low-level signal for example, lower than or equal to a low-level portion of a clock signal
  • this DC low-level signal is referred to as a second voltage
  • the second voltage may be less than or equal to the first voltage, and the following embodiments are the same, and will not be described again.
  • the third voltage terminal VGH1 is configured to provide a DC high-level signal, and the signal provided by it is referred to as a third voltage
  • the fourth voltage terminal VGH2 is also configured to provide a DC high-level signal, and the signal provided by it is referred to as a first voltage
  • the four voltages, for example, the third voltage and the fourth voltage may be the same voltage, and both are greater than the first voltage and the second voltage. The following embodiments are the same, and will not be described again.
  • FIG. 5 is a circuit diagram of a specific implementation example of the shift register unit shown in FIG. 4.
  • the shift register unit 100 includes second to twenty-ninth transistors T2-T29, and further includes first to second capacitors C1 to C2.
  • FIG. 6 is a circuit diagram of another specific implementation example of the shift register unit shown in FIG. 4. It should be noted that, in the following description, each transistor is described as an N-type transistor, but this does not constitute a limitation on the embodiments of the present disclosure.
  • the input circuit 110 includes a fourth transistor T4.
  • the gate and the first pole of the fourth transistor T4 are electrically connected to each other, and are configured to both be connected to the input terminal INT to receive an input signal, and the second pole of the fourth transistor T4 is configured to be connected to the first node N1, so that when the fourth When the transistor T4 is turned on due to a turn-on signal (for example, a high-level signal) received at the input terminal INT, the turn-on signal is used to charge the first node N1 to be at a high level.
  • the gate and the first electrode of the fourth transistor T4 may be connected to the input terminal INT or other high-voltage terminals (such as the third voltage terminal VGH1 or the fourth voltage terminal VGH2), respectively.
  • the embodiments of the present disclosure do not deal with this. limit.
  • the output circuit 120 includes a second transistor T2, a third transistor T3, and a second capacitor C2.
  • the gate of the second transistor T2 is connected to the first node N1, the first pole of the second transistor T2 is connected to the clock signal terminal CLK to receive a clock signal, and the second pole of the second transistor T2 is connected to the shift output terminal CR.
  • the gate of the third transistor T3 is connected to the first node N1, the first pole of the third transistor T3 is connected to the clock signal terminal CLK to receive a clock signal, and the second pole of the third transistor T3 is connected to the scan signal output terminal OUT1.
  • the first pole of the second capacitor C2 is connected to the first node N1, and the second pole of the second capacitor C2 is connected to the scan signal output terminal OUT1.
  • the second pole of the second capacitor C2 may also be connected to the shift output terminal CR, which is not limited in the embodiments of the present disclosure. It should be noted that, not limited to this, the shift register unit may further include more output signals and a scanning signal output terminal corresponding thereto.
  • the first node control circuit 130 includes a first capacitor C1.
  • a first pole of the first capacitor C1 is connected to the first node N1, and a second pole of the first capacitor C1 is connected to the precharge control terminal Ctr to receive a precharge control signal.
  • the voltage of the first pole of the first capacitor C1 (that is, the first node N1) is bootstrap according to the voltage of the precharge control signal received by the second pole of the first capacitor C1, so as to realize Pre-charging the first node N1, solving the problem of insufficient charging of the first node (for example, a pull-up node) due to the characteristic drift of the transistor at a high refresh frequency, and improving the stability of the circuit structure of the shift register unit, Extends the life of the display panel.
  • the first node reset circuit 150 includes a fifth transistor T5.
  • the gate of the fifth transistor T5 is configured to be connected to the reset terminal RST to receive the reset signal, the first pole of the fifth transistor T5 is connected to the first node N1, and the second pole of the fifth transistor T5 is connected to the second voltage terminal VGL2 to For receiving a second voltage.
  • the fifth transistor T5 is turned on in response to the reset signal, the first node N1 and the second voltage terminal VGL2 are electrically connected, so that the first node N1 can be reset.
  • the reset terminal RST is connected to the output terminal of the cascaded shift register to realize real-time reset of the first node N1 of the stage shift register unit during the shift output of the gate scan signal to avoid Incorrect output at the output.
  • the total reset circuit 190 includes a sixth transistor T6.
  • the gate of the sixth transistor T6 is connected to the total reset terminal TRST to receive the total reset signal, the first pole of the sixth transistor T6 is connected to the first node N1, and the second pole of the sixth transistor T6 is connected to the second voltage terminal VGL2 to Receive a second voltage.
  • the sixth transistor T6 is turned on in response to the total reset signal, the first node N1 and the second voltage terminal VGL2 are electrically connected, so that the first node N1 can be reset.
  • the overall reset circuit 190 is configured to globally reset all cascaded shift register units at the beginning stage of the display stage of one frame of image or the end stage of the display stage of one frame of image.
  • the timing of the total reset signal is earlier than the trigger signal that controls the beginning of the display phase of a frame of image (which will be described in detail later), so that all of the The first node N1 of the shift register unit is reset to avoid an abnormality in the display screen.
  • the second node control circuit 160 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10.
  • the gate of the seventh transistor T7 is connected to the first control node CN1, the first pole of the seventh transistor T7 is connected to the third voltage terminal VGH1 to receive the third voltage, and the second pole of the seventh transistor T7 is connected to the second node N2.
  • the gate of the eighth transistor T8 is connected to the first node N1, the first pole of the eighth transistor T8 is connected to the second node N2, and the second pole of the eighth transistor T8 is connected to the second voltage terminal VGL2 to receive the second voltage .
  • the gate of the ninth transistor T9 and its own first pole are electrically connected to each other, and are configured to be connected to the third voltage terminal VGH1 to receive the third voltage, and the second pole of the ninth transistor T9 is connected to the first control node CN1.
  • the gate of the tenth transistor T10 is connected to the first node N1, the first pole of the tenth transistor T10 is connected to the first control node CN1, and the second pole of the tenth transistor T10 is connected to the second voltage terminal VGL2 to receive the second Voltage.
  • the second node control circuit 160 further includes a twenty-seventh transistor T27, a twenty-eighth transistor T28, a twenty-ninth transistor T29, and a twentieth transistor T20.
  • the gate of the twenty-seventh transistor T27 is connected to the second control node CN2, the first pole of the twenty-seventh transistor T27 and the fourth voltage terminal VGH2 are connected to receive the fourth voltage, and the second pole of the twenty-seventh transistor T27 Connected to the third node N3;
  • the gate of the twenty-eighth transistor T28 is connected to the first node N1, the first pole of the twenty-eighth transistor T28 is connected to the third node N3, and the second pole of the twenty-eighth transistor T28 Connected to the second voltage terminal VGL2 to receive the second voltage.
  • the gate of the twenty-ninth transistor T29 and its own first electrode are electrically connected to each other, and are configured to be connected to the fourth voltage terminal VGH2 to receive the fourth voltage, and the second and second electrodes of the twenty-ninth transistor T29
  • the control node CN2 is connected; the gate of the twentieth transistor T20 is connected to the first node N1, the first pole of the twentieth transistor T20 is connected to the second control node CN2, the second pole of the twentieth transistor T20 is connected to the second voltage terminal VGL2 Connected to receive a second voltage.
  • the first node noise reduction circuit 170 includes an eleventh transistor T11 and a twenty-first transistor T21.
  • the gate of the eleventh transistor T11 is connected to the second node N2, the first pole of the eleventh transistor T11 is connected to the first node N1, and the second pole of the eleventh transistor T11 is connected to the second voltage terminal VGL2 to receive the first Two voltages.
  • the eleventh transistor T11 is turned on when the second node N2 is at a high potential, and connects the first node N1 and the second voltage terminal VGL2, so that the first node N1 can be pulled down (for example, discharged) to achieve noise reduction.
  • the gate of the twenty-first transistor T21 is connected to the third node N3, the first pole of the twenty-first transistor T21 is connected to the first node N1, and the second pole of the twenty-first transistor T21 is connected to the second voltage terminal VGL2.
  • the twenty-first transistor T21 is turned on when the third node N3 is at a high potential, and connects the first node N1 and the second voltage terminal VGL2, so that the first node N1 can be pulled down to achieve noise reduction.
  • the eleventh transistor T11 and the twenty-first transistor T21 work alternately under the control of the levels of the second node N2 and the third node N3, respectively, to extend the service life of these transistors.
  • the output terminal OUT includes a shift output terminal CR and a scan signal output terminal OUT1.
  • the output noise reduction circuit 180 may be implemented as a twelfth transistor T12, a twenty-second transistor T22, and a thirteenth transistor T13. And twenty-third transistor T23.
  • the twelfth transistor T12 and the twenty-second transistor T22 are used to reduce noise on the shift output terminal CR
  • the thirteenth transistor T13 and the twenty-third transistor T23 are used to reduce noise on the scan signal output terminal OUT1.
  • the output noise reduction circuit 180 may further include more transistors to achieve noise reduction on the scan signal output terminals.
  • the gate of the twelfth transistor T12 is connected to the second node N2, the first pole of the twelfth transistor T12 is connected to the shift output terminal CR, and the second pole of the twelfth transistor T12 is connected to the second voltage terminal VGL2 to receive Second voltage.
  • the twelfth transistor T12 is turned on when the second node N2 is at a high potential, and the shift output terminal CR is connected to the second voltage terminal VGL2, so that the shift output terminal CR can be reduced in noise.
  • the gate of the twenty-second transistor T22 is connected to the third node N3, the first pole of the twenty-second transistor T22 is connected to the shift output terminal CR, and the second pole of the twenty-second transistor T22 and the second voltage terminal VGL2 Connected to receive a second voltage.
  • the twenty-second transistor T22 is turned on when the third node N3 is at a high potential, and the shift output terminal CR is connected to the second voltage terminal VGL2, so that the shift output terminal CR can be reduced in noise.
  • the twelfth transistor T12 and the twenty-second transistor T22 are alternately operated under the control of the levels of the second node N2 and the third node N3, respectively, to extend the service life of these transistors.
  • the gate of the thirteenth transistor T13 is connected to the second node N2, the first pole of the thirteenth transistor T13 is connected to the scan signal output terminal OUT1, and the second pole of the thirteenth transistor T13 is connected to the first voltage terminal VGL1 to receive First voltage.
  • the thirteenth transistor T13 is turned on when the second node N2 is at a high potential, and connects the scan signal output terminal OUT1 and the first voltage terminal VGL1, so that the scan signal output terminal OUT1 can be reduced in noise.
  • the gate of the twenty-third transistor T23 is connected to the third node N3, the first electrode of the twenty-third transistor T23 is connected to the scan signal output terminal OUT1, and the second electrode of the twenty-third transistor T23 is connected to the first voltage terminal VGL1.
  • the twenty-third transistor T23 is turned on when the third node N3 is at a high potential, and the scan signal output terminal OUT1 and the first voltage terminal VGL1 are connected, so that the scan signal output terminal OUT1 can be reduced in noise.
  • the thirteenth transistor T13 and the twenty-third transistor T23 are alternately operated under the control of the levels of the second node N2 and the third node N3, respectively, to extend the service life of these transistors.
  • the circuit structure of the shift register unit 100 is basically the same as the circuit structure shown in FIG. 5, except that the shift register unit 100 further includes a first transistor T1, which is not repeated here. To repeat.
  • the output control circuit 140 includes a first transistor T1.
  • the gate of the first transistor T1 is connected to the precharge control terminal Ctr to receive a precharge control signal.
  • the first electrode of the first transistor T1 is connected to the output terminal OUT (for example, the shift output terminal CR and / or the scan signal output terminal OUT1).
  • the second pole of the first transistor T1 is connected to the first voltage terminal VGL1 to receive the first voltage.
  • the first transistor T1 is turned on in response to the precharge control terminal Ctr receiving the precharge control signal, and the shift output terminal CR and / or the scan signal output terminal OUT1 are respectively connected to the first voltage terminal VGL1 to realize the shift output terminal.
  • CR and the scan signal output terminal OUT1 are pulled down to avoid erroneous output of the shift output terminal CR and the scan signal output terminal OUT1 during the stage of precharging the first node N1 through the first node control circuit 130.
  • pulse-up means charging a node or an electrode of a transistor so that the absolute level of the node or the electrode is The value increases to achieve the operation of the corresponding transistor (for example, turn on);
  • pulse-down means to discharge a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode is reduced to achieve the corresponding Operation of the transistor (e.g. off).
  • pulse-up means discharging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode is reduced, thereby realizing the corresponding transistor.
  • Operation (such as turning on);
  • pulse-down means charging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode increases, thereby realizing the operation of the corresponding transistor (such as turning off) .
  • the first node N1, the second node N2, the third node N3, the first control node CN1, and the second control node CN2 do not indicate actual components (physical Structure or point), but represents the meeting point of related electrical connections in the circuit diagram, which is a functional connection point.
  • all the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • the thin film transistors are used as an example for description.
  • the source and drain of the transistor used here can be symmetrical in structure, so there can be no difference in structure of the source and drain of the transistor.
  • one pole is directly described as the first pole and the other pole is the second pole.
  • the transistors in the embodiments of the present disclosure are described by taking N-type transistors as an example.
  • the first electrode of the transistor is a drain
  • the second electrode is a source.
  • the present disclosure includes but is not limited to this.
  • one or more transistors in the shift register unit 100 provided by the embodiment of the present disclosure may also be a P-type transistor.
  • the first pole of the transistor is the source and the second pole is the drain.
  • the poles of a certain type of transistor are connected with reference to the poles of the corresponding transistor in the embodiment of the present disclosure, and the corresponding voltage terminal may provide a corresponding high voltage or low voltage.
  • ITZO Indium Gallium Zinc Oxide
  • LTPS Low Temperature Polysilicon
  • amorphous silicon such as (Crystalline silicon
  • FIG. 7 is a schematic diagram of a gate driving circuit provided by at least one embodiment of the present disclosure.
  • the gate driving circuit 10 includes a plurality of cascaded shift register units 100, and any one or more of the shift register units 100 may adopt the shift register unit 100 provided by any embodiment of the present disclosure.
  • the shift register unit 100 shown in FIG. 5 may be adopted, or the shift register unit 100 shown in FIG. 6 may be adopted.
  • the gate driving circuit 10 can be directly integrated on the array substrate of the display device by using the same semiconductor manufacturing process as the thin film transistor, so as to realize the progressive or interlaced scanning driving function.
  • the output terminal OUT is connected.
  • the input terminals INT of the shift register units of the other stages are connected to the output terminal OUT of the upper-stage shift register unit separated by m-1 stages;
  • the reset terminal RST of the remaining stages of the shift register unit is connected to the output terminal OUT of the lower-stage shift register unit m-1 stages apart therefrom.
  • the gate driving circuit 10 further includes a first clock signal line CLK1, a second clock signal line CLK2, a third clock signal line CLK3, a fourth clock signal line CLK4, a fifth clock signal line CLK5, and a sixth Clock signal line CLK6.
  • the first clock signal line CLK1 is connected to, for example, the clock signal terminal CLK of the 6n-5th (n is an integer greater than 0) stage shift register unit;
  • the second clock signal line CLK2 is, for example, to the 6n -The clock signal terminal CLK of the 4-stage shift register unit is connected;
  • the third clock signal line CLK3 is connected to the clock signal terminal CLK of the 6n-3 stage shift register unit, for example;
  • the fourth clock signal line CLK4 is connected to the 6n-2 The clock signal terminal CLK of the stage shift register unit is connected;
  • the fifth clock signal line CLK5 is connected to the clock signal terminal CLK of the 6n-1 stage shift register unit, for example;
  • the sixth clock signal line CLK6 is shifted to the 6n stage, for example The clock signal terminal of the register unit is connected.
  • the embodiments of the present disclosure may also include other connection modes, which are not limited in the embodiments of the present disclosure.
  • N-6_CR (N is an integer greater than 0) shown in FIG. 7 represents the shift output terminal of the N-6th stage shift register unit
  • N-5_CR represents the N-5th stage shift register
  • N-4_CR represents the shift output of the N-4th stage shift register unit
  • N-3_CR represents the shift output of the N-3th stage shift register unit
  • N-2_CR represents the first The shift output terminal of the N-2 stage shift register unit
  • N-1_CR represents the shift output terminal of the N-1th stage shift register unit
  • N_CR represents the shift output terminal of the Nth stage shift register unit.
  • the reset terminal RST of the other stages of the shift register unit is connected to the shift output terminal CR of the lower stage shift register unit separated by two stages.
  • the input terminals INT of the shift register units of the other stages are connected to the shift output terminal CR of the upper-stage shift register unit separated from it by two stages.
  • the precharge control terminal Ctr (ie, the second pole of the first capacitor C1) of the Nth stage shift register unit 100 of the gate driving circuit 10 and the shift output terminal of the upper stage shift register unit separated from it by three stages CR connection, that is, to the CR output shift terminal CR of the N-4th stage shift register unit, the precharge control terminal Ctr and N-5th stage of the N-1th stage shift register unit 100 of the gate driving circuit 10
  • the shift output terminal CR of the stage shift register unit is connected.
  • the precharge control terminal Ctr of the N-2 stage shift register unit 100 and the shift output of the N-6 stage shift register unit of the gate driving circuit 10 End CR connection.
  • the pre-charge control terminal Ctr of the shift register unit 100 at each level may also be connected to the shift output terminal CR of an upper-stage shift register unit separated from it by four, five, and more stages. No restrictions. However, from the perspective of the storage capacity of the first capacitor, it is better to choose a shift output terminal with fewer stages separated from the shift register unit to avoid the influence of the storage capacity of the capacitor on the first node N1. Charging.
  • the input terminal INT of the first, second, and third stage shift register units may be configured to receive a trigger signal STV
  • the reset terminal RST of the last three stage shift register units may be configured to receive a reset signal.
  • the trigger signal STV and the reset signal are not shown in FIG. 7 for brevity.
  • the gate driving circuit 10 further includes a first voltage line, a second voltage line, a third voltage line, and a fourth voltage line (not shown in the figure).
  • the first voltage line is connected to the first voltage terminal VGL1 and is configured to provide the first voltage
  • the second voltage line is connected to the second voltage terminal VGL2 and is configured to provide the second voltage
  • the third voltage line is connected to the third voltage
  • the terminal VGH1 is connected and configured to provide a third voltage
  • the fourth voltage line is connected to the fourth voltage terminal VGH2 and configured to provide a fourth voltage.
  • the gate driving circuit 10 may further include a timing controller 300.
  • the timing controller 300 may be configured to communicate with the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CLK4, the fifth clock signal line CLK5, and the sixth clock.
  • the signal line CLK6 is connected to provide a clock signal to each shift register unit.
  • the gate driving circuit 10 may also be configured to be connected to the first voltage line, the second voltage line, the third voltage line, and the fourth voltage line.
  • Each of the shift register units 100 is provided with a first voltage to a fourth voltage, respectively.
  • the timing controller 300 may be further configured to provide a trigger signal STV and a reset signal.
  • the timing of the clock signals provided on the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CLK4, the fifth clock signal line CLK5, and the sixth clock signal line CLK6 may be
  • the signal timing shown in FIG. 8A or FIG. 8B is adopted to realize the function of the gate driving circuit 10 outputting the gate scan signal line by line.
  • the duty cycle of the clock signal shown in FIG. 8A is 40%; the duty cycle of the clock signal shown in FIG. 8B is 50%.
  • the potential levels of the signal timing diagrams shown in FIG. 8A and FIG. 8B are only schematic, and do not represent real potential values or relative proportions.
  • high-level signals correspond to N-type transistors.
  • the low-level signal corresponds to the N-type transistor as the off signal.
  • the working principle of the Nth-stage shift register unit of the gate driving circuit 10 shown in FIG. 7 will be described below with reference to the signal timing diagram shown in FIG. 8A.
  • the N-th stage shift register unit may adopt the circuit structure shown in FIG. 5, and may also adopt the circuit structure shown in FIG. 6.
  • the working principle of the shift register unit 100 is:
  • the third clock signal line CLK3 provides a high level. Since the clock signal terminal CLK of the N-4th stage shift register unit is connected to the third clock signal line CLK3, at this stage, the N- The shift output terminal N-4_CR of the 4-stage shift register unit outputs an effective output level (for example, a high level), because the second pole of the first capacitor of the N-th stage shift register unit and the N-4th stage shift The shift output terminal N-4_CR of the bit register unit is connected, so the second pole of the first capacitor C1 changes from low level to high level, and according to the characteristic that the voltage across the capacitor cannot be abruptly changed, the first capacitor C1 The voltage of one pole (that is, the first node N1) is bootstrap.
  • the first node N1 is charged to a high level; at the same time, the first clock signal line CLK1 provides a low level.
  • the clock signal terminal CLK of the register unit is connected to the first clock signal line CLK1. Therefore, at this stage, the shift output terminal N_CR and the scan signal output terminal N_OUT1 of the Nth stage shift register unit output a low level.
  • the circuit structure further includes a first transistor T1.
  • the gate of the first transistor T1 is also connected to the shift output terminal N-4_CR of the N-4th stage shift register unit, so the first transistor T1 responds to the The shift output terminal N-4_CR outputs a high level and is turned on, so that the first voltage terminal VGL1 is connected to the shift output terminal N_CR and the scan signal output terminal N_OUT1 of the Nth stage shift register unit, further avoiding the Nth stage shift
  • the output terminal of the bit register unit outputs a high level at this stage, which ensures the display quality of the display panel.
  • the fourth clock signal line CLK4 provides a high level. Since the clock signal terminal CLK of the N-3 stage shift register unit is connected to the fourth clock signal line CLK4, at this stage, the N- The shift output terminal N-3_CR of the 3-stage shift register unit outputs an effective output level (for example, high level), and because the input terminal INT of the N-th stage shift register unit and the N-3-stage shift register unit The shift output terminal N-3_CR is connected.
  • the first node N1 of the Nth stage shift register unit continues to be charged to a high level; at the same time, because the first clock signal line CLK1 provides a low level, so At this stage, the shift output terminal N_CR and the scan signal output terminal N_OUT1 of the Nth stage shift register unit output a low level.
  • the first node N1 is precharged in advance in the first phase t1, that is, the effect of the drift of the characteristics of the transistor (for example, the threshold voltage) is compensated in advance, and the The pull-down (for example, discharge) of the two node N2 avoids that after the first node N1 is charged in the second stage t2, its voltage leaks through the transistor (eg, the eleventh transistor T11) connected to it, thereby improving the first node N1.
  • the transistor eg, the eleventh transistor T11
  • the charging capacity of one node N1 therefore, solves the problem of insufficient charging of the first node (for example, a pull-up node) due to the characteristic drift of the transistor at a high refresh frequency, and improves the stability of the circuit structure of the shift register unit , Extending the life of the display panel.
  • the first clock signal line CLK1 provides a high level. Since the clock signal terminal CLK of the N-th stage shift register unit 100 is connected to the first clock signal line CLK1, at this stage, the first node N1 Is charged to the second high level, at the same time, the output circuit 120 of the Nth stage shift register unit 100 is turned on under the control of the high level of the first node N1, and the first clock signal line CLK1 provides The high level is output to the shift output terminal N_CR and the scan signal output terminal N_OUT1 of the Nth stage shift register unit.
  • the working principle of the Nth-stage shift register unit of the gate driving circuit 10 shown in FIG. 7 will be described below with reference to the signal timing diagram shown in FIG. 8B.
  • the N-th stage shift register unit can adopt the circuit structure shown in FIG. 6, and cannot adopt the circuit structure shown in FIG. 5.
  • the specific working principle of the shift register unit is described as follows:
  • the third clock signal line CLK3 provides a high level. Since the clock signal terminal CLK of the N-4th stage shift register unit is connected to the third clock signal line CLK3, at this stage, the N- The shift output terminal N-4_CR of the 4-stage shift register unit outputs an effective output level (for example, a high level), because the second pole of the first capacitor of the N-th stage shift register unit and the N-4th stage shift The shift output terminal N-4_CR of the bit register unit is connected, so the second pole of the first capacitor C1 changes from low level to high level, and according to the characteristic that the voltage across the capacitor cannot be abruptly changed, the first capacitor C1 The voltage of one pole (that is, the first node N1) is bootstrap.
  • the first node N1 is charged to a high level.
  • the first clock signal line CLK1 provides a portion of the high level.
  • the clock signal terminal CLK of the Nth stage shift register unit is connected to the first clock signal line CLK1, because the gate of the first transistor T1 is also connected to the shift output terminal N-4_CR of the N-4th stage shift register unit, Therefore, the first transistor T1 responds to the shift output of the N-4th stage shift register unit.
  • the N-4_CR output is turned on at a high level, so that the first voltage terminal VGL1 is connected to the shift output terminal N_CR and the scan signal output terminal N_OUT1 of the Nth stage shift register unit, thereby avoiding the Nth stage of the shift register unit.
  • the output terminal outputs the high level provided by the first clock signal line CLK1 at this stage, thereby ensuring the display quality of the display panel.
  • the fourth clock signal line CLK4 provides a high level. Since the clock signal terminal CLK of the N-3 stage shift register unit is connected to the fourth clock signal line CLK4, at this stage, the N- The shift output terminal CR of the 3-stage shift register unit outputs an effective output level (for example, high level), and because the input terminal INT of the N-th stage shift register unit and the shift of the N-3-stage shift register unit The bit output terminal N-3_CR is connected.
  • the first node N1 of the Nth stage shift register unit continues to be charged to a high level; at the same time, because the first clock signal line CLK1 provides a low level, At this stage, the shift output terminal N_CR and the scan signal output terminal N_OUT1 of the Nth stage shift register unit output a low level.
  • the first clock signal line CLK1 provides a high level. Since the clock signal terminal CLK of the N-th stage shift register unit 100 is connected to the first clock signal line CLK1, at this stage, the first node N1 Is charged to the second high level, at the same time, the output circuit 120 of the Nth stage shift register unit 100 is turned on under the control of the high level of the first node N1, and the first clock signal line CLK1 provides The high level is output to the shift output terminal N_CR and the scan signal output terminal N_OUT1 of the Nth stage shift register unit.
  • the gate driving circuit 10 may further include eight, ten or twelve or more clock signal lines, and the number of clock signal lines depends on specific circumstances, which is not limited in the embodiments of the present disclosure. .
  • the gate driving circuit 10 may be disposed on one side of the display panel.
  • the display panel includes multiple rows of gate lines, and the second output terminals of the voltage conversion circuits in the gate driving circuits 10 may be configured to be sequentially connected to the multiple rows of gate lines for outputting a gate scan signal.
  • the gate driving circuit 10 may also be provided on both sides of the display panel to achieve bilateral driving. The embodiment of the present disclosure does not limit the manner of setting the gate driving circuit 10.
  • the display device 1 includes a gate driving circuit 10 provided by an embodiment of the present disclosure.
  • the display device 1 further includes a display panel 40 including an array of a plurality of sub-pixel units 410.
  • the display device 1 may further include a data driving circuit 30.
  • the data driving circuit 30 is used to provide a data signal to the pixel array;
  • the gate driving circuit 10 is used to provide a driving signal to the pixel array.
  • the driving signal can drive the scanning transistor and the sensing transistor in the sub-pixel unit 410.
  • the data driving circuit 30 is electrically connected to the sub-pixel unit 410 through a data line DL, and the gate driving circuit 10 is electrically connected to the sub-pixel unit 410 through a gate line GL.
  • the display device 1 in this embodiment may be any of: a liquid crystal panel, a liquid crystal television, a display, an OLED panel, an OLED television, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, etc Products or parts with display capabilities.
  • the display device 1 may further include other conventional components such as a display panel, which is not limited in the embodiments of the present disclosure.
  • Embodiments of the present disclosure also provide a driving method that can be used to drive the shift register unit 100 provided by the embodiments of the present disclosure.
  • the driving method includes the following operations.
  • the first node control circuit 130 charges the first node N1 in response to the precharge control signal.
  • the input circuit 110 charges the first node N1 in response to the input signal.
  • the output circuit 120 outputs the output signal at the output terminal OUT under the control of the level signal of the first node N1.
  • the shift register unit 100 includes an output control circuit 140, and the driving method further includes:
  • the output control circuit 140 controls the output terminal OUT to an invalid output level during a non-output period in response to a precharge control signal.

Abstract

公开了一种移位寄存器单元、栅极驱动电路、显示装置和驱动方法。该移位寄存器单元(100)包括输入电路(110)、输出电路(120)和第一节点控制电路(130)。输入电路(110)配置为响应于输入信号对第一节点(N1)进行充电；输出电路(120)配置为在第一节点(N1)的电平信号的控制下，将输出信号在输出端(OUT)输出；第一节点控制电路(130)配置为从预充控制端(Ctr)接收预充控制信号且响应于预充控制信号，在输出端(OUT)将输出信号输出之前，对第一节点(N1)进行充电。该移位寄存器单元可以提高第一节点的充电能力，以解决在高刷新频率下由于晶体管的特性漂移导致的第一节点充电不足的问题。

Description

移位寄存器单元、栅极驱动电路、显示装置及驱动方法
本申请要求于2018年9月6日递交的中国专利申请第201811038779.0号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种移位寄存器单元、栅极驱动电路、显示装置及驱动方法。
背景技术
在显示技术领域，例如液晶显示面板的像素阵列通常包括多行栅线和与该多行栅线交错的多列数据线。对栅线的驱动可以通过绑定的集成驱动电路实现。近几年随着非晶硅薄膜晶体管或氧化物薄膜晶体管制备工艺的不断提高，也可以将栅线驱动电路直接集成在薄膜晶体管阵列基板上形成GOA(Gate driver On Array)来对栅线进行驱动。例如，可以采用包括多个级联的移位寄存器单元的GOA为像素阵列的多行栅线提供开关态电压信号(扫描信号)，从而例如控制多行栅线依序打开，并且同时由数据线向像素阵列中对应行的像素单元提供数据信号，以在各像素单元形成显示图像的各灰阶所需要的灰度电压，进而显示一帧图像。目前的显示面板越来越多地采用GOA技术来对栅线进行驱动。GOA技术有助于实现显示面板的窄边框设计，并且可以降低显示面板的生产成本。
发明内容
本公开至少一实施例提供一种移位寄存器单元，包括输入电路、输出电路和第一节点控制电路。所述输入电路与第一节点连接，且配置为响应于输入信号对所述第一节点进行充电；所述输出电路与所述第一节点连接，且配置为在所述第一节点的电平信号的控制下，将输出信号在输出端输出；所述第一节点控制电路分别与所述第一节点和预充控制端连接，且配置为从所述 预充控制端接收预充控制信号且响应于所述预充控制信号，在所述输出端输出所述输出信号之前，对所述第一节点进行充电。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述输入电路与所述第一节点连接，所述输出电路包括所述输出端，且所述输出电路与所述第一节点连接，所述第一节点控制电路分别与所述第一节点和所述预充控制端连接。
例如，本公开至少一实施例提供的移位寄存器单元，还包括输出控制电路。所述输出控制电路分别与所述输出端和所述预充控制端连接，且配置为从所述预充控制端接收所述预充控制信号且响应于所述预充控制信号，将所述输出端在非输出期间控制在无效输出电平。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述第一节点控制电路包括第一电容。所述第一电容的第一极与所述第一节点连接，所述第一电容的第二极与所述预充控制端连接以接收所述预充控制信号。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述输出控制电路包括第一晶体管。所述第一晶体管的栅极与所述预充控制端连接以接收所述预充控制信号，所述第一晶体管的第一极与所述输出端连接，所述第一晶体管的第二极与第一电压端连接以用于接收第一电压。
例如，本公开至少一实施例提供的移位寄存器单元，还包括第一节点复位电路。所述第一节点复位电路与所述第一节点连接，配置为响应于复位信号对所述第一节点进行复位。
例如，本公开至少一实施例提供的移位寄存器单元，还包括第二节点控制电路、第一节点降噪电路和输出降噪电路。所述第二节点控制电路分别与所述第一节点以及第二节点连接，且配置为在所述第一节点的电平信号的控制下，对所述第二节点的电平进行控制；所述第一节点降噪电路与所述第一节点以及所述第二节点连接，且配置为在所述第二节点的电平信号的控制下，对所述第一节点进行降噪；所述输出降噪电路与所述第二节点以及所述输出端连接，且配置为在所述第二节点的电平信号的控制下，对所述输出端进行降噪。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述输出端包括移位输出端和至少一个扫描信号输出端。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述至少一个扫描信号输出端包括一个扫描信号输出端，所述输出电路包括第二晶体管、第三晶体管和第二电容。所述第二晶体管的栅极和所述第一节点连接，所述第二晶体管的第一极和时钟信号端连接以接收时钟信号，所述第二晶体管的第二极和所述移位输出端连接；所述第三晶体管的栅极和所述第一节点连接，所述第三晶体管的第一极和所述时钟信号端连接以接收所述时钟信号，所述第三晶体管的第二极和所述扫描信号输出端连接；所述第二电容的第一极和所述第一节点连接，所述第二电容的第二极和所述扫描信号输出端或所述移位输出端连接，所述时钟信号被传输至所述输出端作为所述输出信号。
例如，本公开至少一实施例提供的移位寄存器单元，还包括：第一节点复位电路、总复位电路、第二节点控制电路、第一节点降噪电路和输出降噪电路；所述第一节点复位电路与所述第一节点连接，配置为响应于复位信号对所述第一节点进行复位；所述总复位电路与所述第一节点连接，配置为响应于总复位信号对所述第一节点进行复位；所述第二节点控制电路分别与所述第一节点、第二节点以及第三节点连接，且配置为在所述第一节点的电平信号的控制下，对所述第二节点的电平和所述第三节点的电平进行控制；所述第一节点降噪电路与所述第一节点以及所述第二节点连接，且配置为在所述第二节点的电平信号的控制下，对所述第一节点进行降噪；所述输出降噪电路与所述第二节点以及所述输出端连接，且配置为在所述第二节点的电平信号的控制下，对所述输出端进行降噪；所述第一节点控制电路包括：第一电容，所述第一电容的第一极与所述第一节点连接，所述第一电容的第二极与所述预充控制端连接以接收所述预充控制信号；所述输出控制电路包括：第一晶体管，所述第一晶体管的栅极与所述预充控制端连接以接收所述预充控制信号，所述第一晶体管的第一极与所述输出端连接，所述第一晶体管的第二极与第一电压端连接以用于接收第一电压；在所述输出端包括移位输出端和一个扫描信号输出端的情形下，所述输出电路包括第二晶体管、第三晶体管和第二电容，所述第二晶体管的栅极和所述第一节点连接，所述第二晶体管的第一极和时钟信号端连接以接收时钟信号，所述第二晶体管的第二极和所述移位输出端连接；所述第三晶体管的栅极和所述第一节点连接，所述第三晶体管的第一极和所述时钟信号端连接以接收所述时钟信号，所述第三 晶体管的第二极和所述扫描信号输出端连接；所述第二电容的第一极和所述第一节点连接，所述第二电容的第二极和所述扫描信号输出端或所述移位输出端连接，所述时钟信号被传输至所述输出端作为所述输出信号；所述输入电路包括：第四晶体管，所述第四晶体管的栅极和第一极彼此电连接，且配置为都和输入端连接以接收所述输入信号，所述第四晶体管的第二极配置为和所述第一节点连接；所述第一节点复位电路包括：第五晶体管，所述第五晶体管的栅极配置为和复位端连接以接收所述复位信号，所述第五晶体管的第一极和所述第一节点连接，所述第五晶体管的第二极和第二电压端连接以用于接收第二电压；所述总复位电路包括：第六晶体管，所述第六晶体管的栅极和总复位端连接以接收所述总复位信号，所述第六晶体管的第一极和所述第一节点连接，所述第六晶体管的第二极和所述第二电压端连接以用于接收所述第二电压；所述第二节点控制电路包括第七晶体管、第八晶体管、第九晶体管、第十晶体管、第二十七晶体管、第二十八晶体管、第二十九晶体管和第二十晶体管，所述第七晶体管的栅极和第一控制节点连接，所述第七晶体管的第一极和第三电压端连接以用于接收第三电压，所述第七晶体管的第二极和所述第二节点连接；所述第八晶体管的栅极和所述第一节点连接，所述第八晶体管的第一极和所述第二节点连接，所述第八晶体管的第二极和所述第二电压端连接以用于接收所述第二电压；所述第九晶体管的栅极和其自身的第一极彼此电连接，且配置为都和所述第三电压端连接以用于接收所述第三电压，所述第九晶体管的第二极和所述第一控制节点连接；所述第十晶体管的栅极和所述第一节点连接，所述第十晶体管的第一极和所述第一控制节点连接，所述第十晶体管的第二极和所述第二电压端连接以用于接收所述第二电压；所述第二十七晶体管的栅极和第二控制节点连接，所述第二十七晶体管的第一极和第四电压端连接以用于接收第四电压，所述第二十七晶体管的第二极和所述第三节点连接；所述第二十八晶体管的栅极和所述第一节点连接，所述第二十八晶体管的第一极和所述第三节点连接，所述第二十八晶体管的第二极和所述第二电压端连接以用于接收所述第二电压；所述第二十九晶体管的栅极和其自身的第一极彼此电连接，且配置为都和所述第四电压端连接以用于接收所述第四电压，所述第二十九晶体管的第二极和所述第二控制节点连接；所述第二十晶体管的栅极和所述第一节点连接，所述第 二十晶体管第一极和所述第二控制节点连接，所述第二十晶体管第二极和所述第二电压端连接以用于接收所述第二电压；所述第一节点降噪电路包括第十一晶体管和第二十一晶体管，所述第十一晶体管的栅极和所述第二节点连接，所述第十一晶体管的第一极和所述第一节点连接，所述第十一晶体管的第二极和所述第二电压端连接以用于接收所述第二电压；所述第二十一晶体管的栅极和所述第三节点连接，所述第二十一晶体管的第一极和所述第一节点连接，所述第二十一晶体管的第二极和所述第二电压端连接以用于接收所述第二电压；所述输出降噪电路可以实现为第十二晶体管、第二十二晶体管、第十三晶体管和第二十三晶体管，所述第十二晶体管的栅极和所述第二节点连接，所述第十二晶体管的第一极和所述移位输出端连接，所述第十二晶体管的第二极和所述第二电压端连接以接收所述第二电压；所述第二十二晶体管的栅极和所述第三节点连接，所述第二十二晶体管的第一极和所述移位输出端连接，所述第二十二晶体管的第二极和所述第二电压端连接以用于接收所述第二电压；所述第十三晶体管的栅极和所述第二节点连接，所述第十三晶体管的第一极和所述扫描信号输出端连接，所述第十三晶体管的第二极和所述第一电压端连接以用于接收所述第一电压；所述第二十三晶体管的栅极和所述第三节点连接，所述第二十三晶体管的第一极和所述扫描信号输出端连接，所述第二十三晶体管的第二极和所述第一电压端连接以用于接收所述第一电压。
本公开至少一实施例还提供一种栅极驱动电路，包括多个级联的本公开任一实施例提供的移位寄存器单元。
例如，在本公开至少一实施例提供的栅极驱动电路中，除第1级至第m级移位寄存器单元外，其余各级移位寄存器单元的预充控制端和与其相隔至少m级的上级移位寄存器单元的输出端连接；除第1级至第m级移位寄存器单元外，其余各级移位寄存器单元的输入端和与其相隔m-1级的上级移位寄存器单元的输出端连接；除最后m级移位寄存器单元外，其余各级移位寄存器单元的复位端和与其相隔m-1级的下级移位寄存器单元的输出端连接；其中，m为大于2的整数。
本公开至少一实施例还提供一种显示装置，包括本公开任一实施例提供的栅极驱动电路。
本公开至少一实施例还提供一种移位寄存器单元的驱动方法，包括：第一阶段，所述第一节点控制电路响应于所述预充控制信号对所述第一节点进行充电；第二阶段，所述输入电路响应于输入信号对所述第一节点进行充电；第三阶段，所述输出电路在所述第一节点的电平信号的控制下，将所述输出信号在所述输出端输出。
例如，在本公开至少一实施例提供的驱动方法中，所述移位寄存器单元还包括输出控制电路，所述驱动方法的所述第一阶段还包括：所述输出控制电路响应于所述预充控制信号，将所述输出端控制在无效输出电平。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开至少一实施例提供的一种移位寄存器单元的示意图；
图2为本公开至少一实施例提供的另一种移位寄存器单元的示意图；
图3为本公开至少一实施例提供的又一种移位寄存器单元的示意图；
图4为本公开至少一实施例提供的再一种移位寄存器单元的示意图；
图5为图4中所示的移位寄存器单元的一种具体实现示例的电路示意图；
图6为图4中所示的移位寄存器单元的另一种具体实现示例的电路示意图；
图7为本公开至少一实施例提供的一种栅极驱动电路的示意图；
图8A为对应于图7中所示的栅极驱动电路工作时的一种示例的信号时序图；
图8B为对应于图7中所示的栅极驱动电路工作时的另一种示例的信号时序图；以及
图9为本公开至少一实施例提供的一种显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
下面通过几个具体的实施例对本公开进行说明。为了保持本公开实施例的以下说明清楚且简明，可省略已知功能和已知部件的详细说明。当本公开实施例的任一部件在一个以上的附图中出现时，该部件在每个附图中由相同或类似的参考标号表示。
在目前的显示技术中，例如在3D显示技术中，为了满足3D游戏的需求，显示屏的刷新频率被不断提高，例如，提高至144Hz。与刷新频率为60Hz的显示屏相比，刷新频率为144Hz的显示屏可以显示更加流畅的游戏场景，尤其是能够消除在3D模式下显示面板由于刷新频率太低造成的拖影现象。显示屏的高刷新率意味着在每帧图像的显示过程中对GOA的充电时间缩短，因此，为了满足充电率，通常采用较高的电源电压对GOA进行充电。但是，较高的电源电压会加速导致晶体管的特性(例如，阈值电压)的漂移，使得通过输入电路写入到上拉节点的高电平低于预定值，因此难以通过上拉节点控制下拉节点的电平，并进一步影响输出端的输出信号；同时，还会加速显示器的老化，影响显示器的使用寿命。为解决上述问题，需要提升GOA中的上拉节点的充电能力。
本公开至少一实施例提供了一种移位寄存器单元，包括输入电路、输出电路和第一节点控制电路。输入电路与第一节点连接，且配置为响应于输入信号对第一节点进行充电；输出电路与第一节点连接，且配置为在第一节点的电平信号的控制下，将输出信号在输出端输出；第一节点控制电路分别与 第一节点和预充控制端连接，且配置为从预充控制端接收预充控制信号且响应于预充控制信号，在输出端将输出信号输出之前，对第一节点进行充电。本公开的实施例还提供对应于上述移位寄存器单元的栅极驱动电路、显示装置及驱动方法。
本公开上述实施例提供的移位寄存器单元，采用双自举电容的设计，可以提高第一节点(例如，上拉节点)的充电能力，以解决在高刷新频率下由于晶体管的特性漂移导致的第一节点(例如，上拉节点)充电不足的问题，提升了移位寄存器单元的电路结构的稳定性，延长了显示面板的使用寿命。
下面结合附图对本公开的实施例及其示例进行详细说明。
图1为本公开至少一实施例提供的一种移位寄存器单元的示意图。如图1所示，该移位寄存器单元100包括输入电路110、输出电路120、第一节点N1和第一节点控制电路130。通过级联多个该移位寄存器单元100可以得到栅极驱动电路，该栅极驱动电路用于驱动显示面板，为显示面板的多条栅线依序提供扫描信号，从而在显示面板显示一帧画面的期间进行逐行或隔行扫描等。
如图1所示，输入电路110配置为响应于输入信号对第一节点N1进行充电。例如，在一些示例中，输入电路110与输入信号端INT和第一节点N1(例如，这里为上拉节点)连接，配置为在输入信号端INT提供的输入信号的控制下导通，使输入信号端INT和第一节点N1连接，从而使输入信号端INT提供的输入信号被输入到第一节点N1，将第一节点N1的电位充电(例如上拉)到工作电位。
输出电路120包括输出端OUT，配置为在第一节点N1的电平信号的控制下，将输出信号在输出端OUT输出。例如，在一些示例中，输出电路120与时钟信号端CLK、第一节点N1以及输出端OUT连接，且配置为在第一节点N1的电平信号的控制下导通，将时钟信号端CLK提供的时钟信号传输至输出端OUT，并作为输出信号在输出端OUT输出。或者，在另一些示例中，输出电路120还与一个电压端(例如，高电压端)连接，使用时钟信号端CLK提供的时钟信号作为控制信号以控制是否将该电压端与输出端OUT连接，从而控制是否将该电压端的电压信号传输至输出端OUT并作为输出信号在输出端OUT输出。
例如，输出端OUT可以包括多个输出端，例如包括移位输出端和至少一个扫描信号输出端，从而将输出信号例如时钟信号端CLK提供的时钟信号输出至移位输出端和扫描信号输出端，以提高该移位寄存器单元100的驱动能力。例如，在本公开的至少一个实施例提供的移位寄存器单元中，至少一个扫描信号输出端包括一个扫描信号输出端。例如，移位输出端与与其相邻的上下级移位寄存器单元100连接以向与其连接的上下级移位寄存器单元100提供预充控制信号、输入信号或复位信号，扫描信号输出端与显示面板中的像素单元的像素电路连接，以向该像素电路提供驱动信号。分别设置移位输出端和扫描信号输出端，可以减少像素区中的负载和信号对级联的移位寄存器单元的影响。例如，移位输出端和扫描信号输出端输出相同的输出信号。需要注意的是，在其他示例中，当包括多个扫描信号输出端时，各个扫描信号输出端也可以输出不同的输出信号，具体的设置根据实际情况而定，本公开的实施例对此不作限制。
第一节点控制电路130分别与第一节点N1和预充控制端Ctr连接，且配置为从预充控制端Ctr接收预充控制信号，且响应于预充控制信号，在输出端OUT输出时钟信号之前对第一节点N1进行充电。例如，预充控制端Ctr提供的预充控制信号的时序早于输入信号，在输入信号对第一节点N1进行充电之前，通过第一节点控制电路130可以提前对第一节点N1进行充电，同时在第一节点N1的电平信号的控制下，对第二节点(例如，这里为下拉节点)进行控制操作(例如，下拉放电)以避免第一节点N1的电平通过第二节点N2控制的晶体管(例如，第十一晶体管T11)放电，因此，可以提高电路中第一节点N1的充电能力。
本公开上述实施例提供的移位寄存器单元，可以提高上拉节点(即第一节点N1)的充电能力，以解决在高刷新频率下由于晶体管的特性漂移导致的上拉节点充电不足的问题，提升了移位寄存器单元的电路结构的稳定性，延长了显示面板的使用寿命。
图2为本公开至少一实施例提供的另一种移位寄存器单元的示意框图。如图2所示，该移位寄存器单元100还包括输出控制电路140。需要说明的是，图2所示的移位寄存器单元100的其他电路结构与图1中所示的移位寄存器单元100基本上相同，在此重复之处不再赘述。
输出控制电路140与输出端OUT和预充控制端Ctr连接，且配置为从预充控制端Ctr接收预充控制信号，且响应于预充控制信号在非输出期间控制输出端OUT保持在无效输出电平。例如，输出控制电路140与预充控制端Ctr、输出端OUT和第一电压端VGL1(例如，提供低电平)或另行提供的电压端(例如，低电压端)连接，且配置为响应于预充控制端Ctr接收的预充控制信号，将输出端OUT与第一电压端VGL1连接，实现对输出端OUT的降噪，以避免在通过第一节点控制电路130对第一节点N1进行预充电的阶段造成输出端OUT的误输出。
请注意，本公开实施例中提供的移位寄存器单元的“有效输出电平”指的是能够使得与之连接的显示面板的像素电路中的开关晶体管被导通从而可以向像素电路中写入数据信号的电平，相应地“无效输出电平”指的是不能使得与之连接的像素电路中的开关晶体管被导通(即，该开关晶体管被截止)的电平。根据像素电路中的开关晶体管的类型(N型或P型)等因素，有效输出电平可以比无效输出电平高或者低。通常，移位寄存器单元在工作期间于输出端输出方波脉冲信号，有效输出电平对应于该方波脉冲信号的方波脉冲部分的电平，而无效输出电平则对应于非方波脉冲部分的电平。
如图1和图2所示的移位寄存器单元所包括的输入电路和输出电路(以及第一节点N1)可以通过各种形式实现，例如4T1C的基本结构，而且在不同的实现方式中，这些移位寄存器单元还可以进一步包括其他功能模块，例如参见下面的描述，然而本公开的实施例并不限于这些具体形式。
图3为本公开至少一实施例提供的又一种移位寄存器单元的示意框图。如图3所示，该移位寄存器单元100还包括第一节点复位电路150。需要说明的是，图3所示的移位寄存器单元100的其他电路结构与图2中所示的移位寄存器单元100基本上相同，在此重复之处不再赘述。
例如，第一节点复位电路150与第一节点N1连接，配置为响应于复位信号对第一节点N1进行复位。例如，该第一节点复位电路150可以配置为和第一节点N1、第二电压端VGL2(例如，提供低电平)或另行提供的电压端(例如，低电压端)以及复位端RST连接，从而可以在复位端RST输入的复位信号的控制下，使得第一节点N1和第二电压端VGL2或低电压端电连接，以对第一节点N1进行复位。
图4为本公开至少一实施例提供的再一种移位寄存器单元的示意框图。如图4所示，在一些示例中，该移位寄存器单元100还包括第二节点控制电路160、第一节点降噪电路170和输出降噪电路180。需要说明的是，图4所示的移位寄存器单元100的其他电路结构与图3中所示的移位寄存器单元100基本上相同，在此重复之处不再赘述。
第二节点控制电路160与第一节点N1以及第二节点N2连接，且配置为在第一节点N1的电平信号的控制下，对第二节点N2的电平进行控制。例如，在一些示例中，第二节点控制电路160与第一节点N1、第二节点N2、第二电压端VGL2、第三电压端VGH1以及第四电压端VGH2或另行提供的电压端(例如，高电压端)连接，从而对第二节点N2的电平进行控制。例如，在第一节点N1为低电平时，第二节点控制电路160使得第二节点N2与第三电压端VGH1或第四电压端VGH2其中一个连接，从而将第二节点N2上拉为高电平；在第一节点N1例如为高电平时，使得第二节点N2与第二电压端VGL2或另行提供的电压端(例如，低电压端)连接，从而将第二节点N2下拉为低电平。例如，该第二节点控制电路160可以实现为反相器，本公开的实施例对此不作限制。
例如，在另一些示例中，第二节点控制电路160还可以包括第三节点(图中未示出)，例如，在该示例中，第二节点N2的电平受第一节点N1的电平和第三电压端VGH1提供的第三电压控制，第三节点N3的电平受第一节点N1的电平和第四电压端VGH2提供的第四电压控制，具体的连接方式将在下面进行详细地介绍。
例如，在一些示例中，该第三电压端VGH1和第四电压端VGH2可以被设置为交替输入高电平，即第三电压端VGH1输入高电平时，第四电压端VGH1输入低电平，而第三电压端VGH1输入低电平时，第四电压端VGH2输入高电平，从而，第二节点N2和第三节点N3交替工作，以使得与其相连的晶体管可以交替工作，延长这些晶体管的使用寿命。例如，在另一些示例中，该第三电压端VGH1和第四电压端VGH2也可以用交替提供高电平(在实现的晶体管为P型时，则为直流低电平)的时钟信号端代替，本公开的实施例对此不作限制。
第一节点降噪电路170与第一节点N1以及第二节点N2连接，且配置为 在第二节点N2的电平的控制下，对第一节点N1进行降噪。例如，第一节点降噪电路170与第一节点N1、第二节点N2以及第二电压端VGL2连接，且配置为在第二节点N2例如为高电平时导通，使得第一节点N1与第二电压端VGL2或另行提供的电压端(例如，低电压端)连接，将第一节N1的电位下拉至非工作电位，以实现对第一节点N1降噪。
输出降噪电路180与第二节点N2以及输出端OUT连接，且配置为在第二节点N2的电平的控制下，对输出端OUT进行降噪。例如，输出降噪电路180与第二节点N2、第二电压端VGL2以及输出端OUT连接，且配置为在第二节点N2例如为高电平时导通，使得输出端OUT与第二电压端VGL2或另行提供的电压端(例如，低电压端)连接，以实现对输出端OUT降噪。
如图4所示，在另一些示例中，移位寄存器单元100还包括总复位电路190。
例如，总复位电路190与第一节点N1连接，配置为响应于总复位信号对第一节点N1进行复位。例如，该总复位电路190可以配置为和第一节点N1、第二电压端VGL2(例如，提供低电平)或另行提供的电压端(例如，低电压端)以及总复位端TRST连接，从而可以在总复位端TRST输入的总复位信号的控制下，使得第一节点N1和第二电压端VGL2或低电压端电连接，以对第一节点N1进行复位。
例如，第一电压端VGL1配置为提供直流低电平信号(例如低于或等于时钟信号的低电平部分)，例如接地，这里将该直流低电平信号称为第一电压，例如，以下各实施例与此相同，不再赘述。
例如，第二电压端VGL2配置为提供直流低电平信号(例如低于或等于时钟信号的低电平部分)，例如接地，这里将该直流低电平信号称为第二电压，例如，该第二电压可以小于或等于第一电压，以下各实施例与此相同，不再赘述。
例如，第三电压端VGH1配置为提供直流高电平信号，将其提供的信号称为第三电压，第四电压端VGH2也配置为提供直流高电平信号，将其提供的信号称为第四电压，例如，第三电压和第四电压可以是相同的电压，且均大于第一电压和第二电压，以下各实施例与此相同，不再赘述。
图5为图4中所示的移位寄存器单元的一种具体实现示例的电路图。如 图5所示，该移位寄存器单元100包括第二晶体管至第二十九晶体管T2-T29，以及还包括第一电容C1至第二电容C2。图6为图4中所示的移位寄存器单元的另一种具体实现示例的电路图。需要注意的是，在下面的说明中以各晶体管为N型晶体管为例进行说明，但这并不构成对本公开实施例的限制。
输入电路110包括第四晶体管T4。第四晶体管T4的栅极和第一极彼此电连接，且配置为都和输入端INT连接以接收输入信号，第四晶体管T4的第二极配置为和第一节点N1连接，从而当第四晶体管T4由于输入端INT接收到的导通信号(例如，高电平信号)导通时，使用该导通信号以对第一节点N1进行充电，使其处于高电平。例如，第四晶体管T4的栅极和第一极也可以分别和输入端INT或其他的高电压端(例如第三电压端VGH1或第四电压端VGH2)连接，本公开的实施例对此不作限制。
输出电路120包括第二晶体管T2、第三晶体管T3和第二电容C2。第二晶体管T2的栅极和第一节点N1连接，第二晶体管T2的第一极和时钟信号端CLK连接以接收时钟信号，第二晶体管T2的第二极和移位输出端CR连接。第三晶体管T3的栅极和第一节点N1连接，第三晶体管T3的第一极和时钟信号端CLK连接以接收时钟信号，第三晶体管T3的第二极和扫描信号输出端OUT1连接。第二电容C2的第一极和第一节点N1连接，第二电容C2的第二极和扫描信号输出端OUT1连接。例如，在另一些示例中中，第二电容C2的第二极还可以和移位输出端CR连接，本公开的实施例对此不作限制。需要注意的是，不限于此，移位寄存器单元还可以包括更多的输出信号，以及与其对应的扫描信号输出端。
第一节点控制电路130包括第一电容C1。第一电容C1的第一极与第一节点N1连接，第一电容C1的第二极与预充控制端Ctr连接以接收预充控制信号。根据电容两端的电压不能突变的特性，使得第一电容C1第一极(即第一节点N1)的电压根据第一电容C1的第二极接收的预充控制信号的电压而自举，以实现对第一节点N1预充电，解决了在高刷新频率下由于晶体管的特性漂移导致的第一节点(例如，上拉节点)充电不足的问题，提升了移位寄存器单元的电路结构的稳定性，延长了显示面板的使用寿命。
第一节点复位电路150包括第五晶体管T5。第五晶体管T5的栅极配置为和复位端RST连接以接收复位信号，第五晶体管T5的第一极和第一节点 N1连接，第五晶体管T5的第二极和第二电压端VGL2连接以用于接收第二电压。第五晶体管T5响应于复位信号而导通时，将第一节点N1和第二电压端VGL2电连接，从而可以对第一节点N1进行复位。例如，复位端RST和与其级联的移位寄存器的输出端连接，以实现在栅极扫描信号的移位输出的过程中对该级移位寄存器单元的第一节点N1进行实时复位，以避免输出端的误输出。
总复位电路190包括第六晶体管T6。第六晶体管T6的栅极和总复位端TRST连接以接收总复位信号，第六晶体管T6的第一极和第一节点N1连接，第六晶体管T6的第二极和第二电压端VGL2连接以接收第二电压。第六晶体管T6响应于总复位信号而导通时，将第一节点N1和第二电压端VGL2电连接，从而可以对第一节点N1进行复位。例如，该总复位电路190配置为在一帧图像的显示阶段的起始阶段或一帧图像的显示阶段的结束阶段，对所有级联的移位寄存器单元进行全局复位。例如，该总复位信号的时序早于控制一帧图像的显示阶段的起始时的触发信号(将在后面进行详细地介绍)，从而可以在一帧图像的显示阶段的起始阶段对所有的移位寄存器单元的第一节点N1进行复位，以避免显示画面出现异常。
例如，在一些示例中，第二节点控制电路160包括第七晶体管T7、第八晶体管T8、第九晶体管T9和第十晶体管T10。第七晶体管T7的栅极和第一控制节点CN1连接，第七晶体管T7的第一极和第三电压端VGH1连接以接收第三电压，第七晶体管T7的第二极和第二节点N2连接；第八晶体管T8的栅极和第一节点N1连接，第八晶体管T8的第一极和第二节点N2连接，第八晶体管T8的第二极和第二电压端VGL2连接以接收第二电压。第九晶体管T9的栅极和其自身的第一极彼此电连接，且配置为都和第三电压端VGH1连接以接收第三电压，第九晶体管T9的第二极和第一控制节点CN1连接；第十晶体管T10的栅极和第一节点N1连接，第十晶体管T10的第一极和第一控制节点CN1连接，第十晶体管T10的第二极和第二电压端VGL2连接以接收第二电压。
例如，在另一些示例中，第二节点控制电路160还包括第二十七晶体管T27、第二十八晶体管T28、第二十九晶体管T29和第二十晶体管T20。第二十七晶体管T27的栅极和第二控制节点CN2连接，第二十七晶体管T27的第 一极和第四电压端VGH2连接以接收第四电压，第二十七晶体管T27的第二极和第三节点N3连接；第二十八晶体管T28的栅极和第一节点N1连接，第二十八晶体管T28的第一极和第三节点N3连接，第二十八晶体管T28的第二极和第二电压端VGL2连接以接收第二电压。第二十九晶体管T29的栅极和其自身的第一极彼此电连接，且配置为都和第四电压端VGH2连接以接收第四电压，第二十九晶体管T29的第二极和第二控制节点CN2连接；第二十晶体管T20的栅极和第一节点N1连接，第二十晶体管T20第一极和第二控制节点CN2连接，第二十晶体管T20第二极和第二电压端VGL2连接以接收第二电压。
第一节点降噪电路170包括第十一晶体管T11和第二十一晶体管T21。第十一晶体管T11的栅极和第二节点N2连接，第十一晶体管T11的第一极和第一节点N1连接，第十一晶体管T11的第二极和第二电压端VGL2连接以接收第二电压。第十一晶体管T11在第二节点N2为高电位时导通，将第一节点N1和第二电压端VGL2连接，从而可以对第一节点N1下拉(例如，放电)以实现降噪。第二十一晶体管T21的栅极和第三节点N3连接，第二十一晶体管T21的第一极和第一节点N1连接，第二十一晶体管T21的第二极和第二电压端VGL2连接以接收第二电压。第二十一晶体管T21在第三节点N3为高电位时导通，将第一节点N1和第二电压端VGL2连接，从而可以对第一节点N1下拉以实现降噪。例如，第十一晶体管T11和第二十一晶体管T21分别在第二节点N2和第三节点N3的电平的控制下交替工作，以延长这些晶体管的使用寿命。
例如，在一些示例中，输出端OUT包括移位输出端CR和一个扫描信号输出端OUT1，输出降噪电路180可以实现为第十二晶体管T12、第二十二晶体管T22、第十三晶体管T13和第二十三晶体管T23。第十二晶体管T12和第二十二晶体管T22用于对移位输出端CR降噪，第十三晶体管T13和第二十三晶体管T23用于对扫描信号输出端OUT1降噪。当包括更多的扫描信号输出端时，该输出降噪电路180还可以包括更多的晶体管以实现对扫描信号输出端的降噪。
第十二晶体管T12的栅极和第二节点N2连接，第十二晶体管T12的第一极和移位输出端CR连接，第十二晶体管T12的第二极和第二电压端VGL2 连接以接收第二电压。第十二晶体管T12在第二节点N2为高电位时导通，将移位输出端CR和第二电压端VGL2连接，从而可以对移位输出端CR降噪。第二十二晶体管T22的栅极和第三节点N3连接，第二十二晶体管T22的第一极和移位输出端CR连接，第二十二晶体管T22的第二极和第二电压端VGL2连接以接收第二电压。第二十二晶体管T22在第三节点N3为高电位时导通，将移位输出端CR和第二电压端VGL2连接，从而可以对移位输出端CR降噪。例如，第十二晶体管T12和第二十二晶体管T22分别在第二节点N2和第三节点N3的电平的控制下交替工作，以延长这些晶体管的使用寿命。
第十三晶体管T13的栅极和第二节点N2连接，第十三晶体管T13的第一极和扫描信号输出端OUT1连接，第十三晶体管T13的第二极和第一电压端VGL1连接以接收第一电压。第十三晶体管T13在第二节点N2为高电位时导通，将扫描信号输出端OUT1和第一电压端VGL1连接，从而可以对扫描信号输出端OUT1降噪。第二十三晶体管T23的栅极和第三节点N3连接，第二十三晶体管T23的第一极和扫描信号输出端OUT1连接，第二十三晶体管T23的第二极和第一电压端VGL1连接以接收第一电压。第二十三晶体管T23在第三节点N3为高电位时导通，将扫描信号输出端OUT1和第一电压端VGL1连接，从而可以对扫描信号输出端OUT1降噪。例如，第十三晶体管T13和第二十三晶体管T23分别在第二节点N2和第三节点N3的电平的控制下交替工作，以延长这些晶体管的使用寿命。
如图6所示，该移位寄存器单元100的电路结构与图5中所示的电路结构基本相同，区别在于：该移位寄存器单元100还包括第一晶体管T1，在此重复之处不再赘述。
如图6所示，输出控制电路140包括第一晶体管T1。第一晶体管T1的栅极与预充控制端Ctr连接以接收预充控制信号，第一晶体管T1的第一极与输出端OUT(例如，移位输出端CR和/或扫描信号输出端OUT1)连接，第一晶体管T1的第二极与第一电压端VGL1连接以接收第一电压。例如，第一晶体管T1响应于预充控制端Ctr接收预充控制信号导通，将移位输出端CR和/或扫描信号输出端OUT1分别与第一电压端VGL1连接，实现对移位输出端CR以及扫描信号输出端OUT1下拉，以避免在通过第一节点控制电路130对第一节点N1进行预充电的阶段造成移位输出端CR以及扫描信号输出端 OUT1的误输出。
在本公开的实施例中，例如，当各个电路实现为N型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如截止)。
又例如，当各个电路实现为P型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如截止)。
需要注意的是，在本公开的各个实施例的说明中，第一节点N1、第二节点N2、第三节点N3、第一控制节点CN1和第二控制节点CN2并非表示实际存在的部件(物理结构或点)，而是表示电路图中相关电连接的汇合点，即是一个功能性连接点。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
另外，在本公开的实施例中的晶体管均以N型晶体管为例进行说明，此时，晶体管的第一极是漏极，第二极是源极。需要说明的是，本公开包括但不限于此。例如，本公开的实施例提供的移位寄存器单元100中的一个或多个晶体管也可以采用P型晶体管，此时，晶体管第一极是源极，第二极是漏极，只需将选定类型的晶体管的各极参照本公开的实施例中的相应晶体管的各极相应连接，并且使相应的电压端提供对应的高电压或低电压即可。当采用N型晶体管时，可以采用氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)作为薄膜晶体管的有源层，相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可 以有效减小晶体管的尺寸以及防止漏电流。
本公开至少一个实施例还提供一种栅极驱动电路。图7为本公开至少一实施例提供的一种栅极驱动电路的示意图。如图7所示，该栅极驱动电路10包括多个级联的移位寄存器单元100，其中任意一个或多个移位寄存器单元100可以采用本公开任一实施例提供的移位寄存器单元100的结构或其变型，例如，可以采用图5中所示的移位寄存器单元100，也可以采用图6中所示的移位寄存器单元100。例如，该栅极驱动电路10可以采用与薄膜晶体管同样半导体制程的工艺直接集成在显示装置的阵列基板上，以实现逐行或隔行扫描驱动功能。
例如，除第1级至第m(m为大于2的整数)级移位寄存器单元外，其余各级移位寄存器单元的预充控制端Ctr和与其相隔至少m级的上级移位寄存器单元的输出端OUT连接；除第1级至第m级移位寄存器单元外，其余各级移位寄存器单元的输入端INT和与其相隔m-1级的上级移位寄存器单元的输出端OUT连接；除最后m级移位寄存器单元外，其余各级移位寄存器单元的复位端RST和与其相隔m-1级的下级移位寄存器单元的输出端OUT连接。
如图7所示，栅极驱动电路10还包括第一时钟信号线CLK1、第二时钟信号线CLK2、第三时钟信号线CLK3、第四时钟信号线CLK4、第五时钟信号线CLK5和第六时钟信号线CLK6。
例如，如图7所示，第一时钟信号线CLK1例如和第6n-5(n为大于0的整数)级移位寄存器单元的时钟信号端CLK连接；第二时钟信号线CLK2例如和第6n-4级移位寄存器单元的时钟信号端CLK连接；第三时钟信号线CLK3例如和第6n-3级移位寄存器单元的时钟信号端CLK连接；第四时钟信号线CLK4例如和第6n-2级移位寄存器单元的第时钟信号端CLK连接；第五时钟信号线CLK5例如和第6n-1级移位寄存器单元的时钟信号端CLK连接；第六时钟信号线CLK6例如和第6n级移位寄存器单元的时钟信号端连接。需要注意的是，本公开的实施例还可以包括其他的连接方式，本公开的实施例对此不作限制。
需要说明的是，图7中所示的N-6_CR(N为大于0的整数)表示第N-6级移位寄存器单元的移位输出端，N-5_CR表示第N-5级移位寄存器单元的移位输出端，N-4_CR表示第N-4级移位寄存器单元的移位输出端，N-3_CR表 示第N-3级移位寄存器单元的移位输出端，N-2_CR表示第N-2级移位寄存器单元的移位输出端，N-1_CR表示第N-1级移位寄存器单元的移位输出端，N_CR表示第N级移位寄存器单元的移位输出端，以此类推。以下各实施例中的附图标记与此类似，不再赘述。
例如，如图7所示，除最后三级移位寄存器单元外，其余各级移位寄存器单元的复位端RST和与其相隔两级的下级移位寄存器单元的移位输出端CR连接。除第一级、第二级和第三级移位寄存器单元外，其余各级移位寄存器单元的输入端INT和与其相隔两级的上级移位寄存器单元的移位输出端CR连接。
例如，该栅极驱动电路10的第N级移位寄存器单元100的预充控制端Ctr(即第一电容C1的第二极)和与其相隔三级的上级移位寄存器单元的移位输出端CR连接，即和第N-4级移位寄存器单元的移位输出端CR连接，该栅极驱动电路10的第N-1级移位寄存器单元100的预充控制端Ctr和第N-5级移位寄存器单元的移位输出端CR连接，该栅极驱动电路10的第N-2级移位寄存器单元100的预充控制端Ctr和第N-6级移位寄存器单元的移位输出端CR连接。例如，各级移位寄存器单元100的预充控制端Ctr还可以和与其相隔四级、五级以及更多级的上级移位寄存器单元的移位输出端CR连接，本公开的实施例对此不作限制。但是，从第一电容的存储能力的角度的出发，还是选择与该移位寄存器单元相隔级数较少的移位输出端连接较好，以避免因电容的存储能力影响对第一节点N1的充电。
例如，第一级、第二级和第三级移位寄存器单元的输入端INT可以被配置为接收触发信号STV，最后三级移位寄存器单元的复位端RST可以被配置为接收复位信号，为简洁起见触发信号STV和复位信号在图7中未示出。
例如，该栅极驱动电路10还包括第一电压线、第二电压线、第三电压线和第四电压线(图中未示出)。例如，第一电压线与第一电压端VGL1连接，且配置为提供第一电压；第二电压线与第二电压端VGL2连接，且配置为提供第二电压；第三电压线与第三电压端VGH1连接，且配置为提供第三电压；第四电压线与第四电压端VGH2连接，且配置为提供第四电压。
例如，如图7所示，该栅极驱动电路10还可以包括时序控制器300。例如，该时序控制器300可以被配置为和第一时钟信号线CLK1、第二时钟信号 线CLK2、第三时钟信号线CLK3、第四时钟信号线CLK4、第五时钟信号线CLK5和第六时钟信号线CLK6连接，以向各移位寄存器单元提供时钟信号；该栅极驱动电路10还可以被配置为与第一电压线、第二电压线、第三电压线和第四电压线连接，以向各移位寄存器单元100分别提供第一电压至第四电压。例如，时序控制器300还可以被配置为提供触发信号STV以及复位信号。
例如，第一时钟信号线CLK1、第二时钟信号线CLK2、第三时钟信号线CLK3、第四时钟信号线CLK4、第五时钟信号线CLK5和第六时钟信号线CLK6上提供的时钟信号时序可以采用图8A或图8B中所示的信号时序，以实现栅极驱动电路10逐行输出栅极扫描信号的功能。例如，图8A所示的时钟信号的占空比为40％；图8B所示的时钟信号的占空比为50％。需要说明的是，图8A和图8B中所示的信号时序图的电位的高低仅是示意性的，不代表真实电位值或相对比例，对应于上述示例，高电平信号对应于N型晶体管的开启信号，而低电平信号对应于N型晶体管为截止信号。
例如，在一些示例中，下面结合图8A所示的信号时序图，对图7中所示的栅极驱动电路10的第N级移位寄存器单元的工作原理进行说明。例如，第N级移位寄存器单元可以采用图5所示的电路结构，也可以采用图6所示的电路结构。该移位寄存器单元100的工作原理为：
在第一阶段t1，第三时钟信号线CLK3提供高电平，由于第N-4级移位寄存器单元的时钟信号端CLK与第三时钟信号线CLK3连接，因此，在此阶段，第N-4级移位寄存器单元的移位输出端N-4_CR输出有效输出电平(例如，高电平)，由于第N级移位寄存器单元的第一电容的第二极与第N-4级移位寄存器单元的移位输出端N-4_CR连接，所以，第一电容C1的第二极由低电平变为高电平，且根据电容两端的电压不能突变这一特性，第一电容C1第一极(即第一节点N1)的电压被自举，因此，在此阶段，第一节点N1被充电至高电平；同时，第一时钟信号线CLK1提供低电平，由于第N级移位寄存器单元的时钟信号端CLK与第一时钟信号线CLK1连接，因此，在此阶段，第N级移位寄存器单元的移位输出端N_CR和扫描信号输出端N_OUT1输出低电平。
在采用图6中的电路结构时，该电路结构还包括第一晶体管T1。在此阶段，第一晶体管T1的栅极也与第N-4级移位寄存器单元的移位输出端N-4_CR 连接，所以，第一晶体管T1响应于第N-4级移位寄存器单元的移位输出端N-4_CR输出的高电平而开启，使得第一电压端VGL1与第N级移位寄存器单元的移位输出端N_CR和扫描信号输出端N_OUT1连接，进一步避免了第N级移位寄存器单元的输出端在此阶段输出高电平，保证了显示面板的显示质量。
在第二阶段t2，第四时钟信号线CLK4提供高电平，由于第N-3级移位寄存器单元的时钟信号端CLK与第四时钟信号线CLK4连接，因此，在此阶段，第N-3级移位寄存器单元的移位输出端N-3_CR输出有效输出电平(例如，高电平)，又由于第N级移位寄存器单元的输入端INT与第N-3级移位寄存器单元的移位输出端N-3_CR连接，因此，在此阶段，第N级移位寄存器单元的第一节点N1继续被充电至高电平；同时，由于第一时钟信号线CLK1提供低电平，所以，在此阶段，第N级移位寄存器单元的移位输出端N_CR和扫描信号输出端N_OUT1输出低电平。
由于，在第二阶段t2开始之前，第一阶段t1中提前对第一节点N1进行预充电，即提前补偿了晶体管的特性(例如，阈值电压)的漂移带来的影响，同时对提前对第二节点N2进行下拉(例如，放电)，避免了在第二阶段t2中对第一节点N1进行充电后，其电压通过与其相连的晶体管(例如，第十一晶体管T11)漏电，从而提高了第一节点N1的充电能力，因此，解决了在高刷新频率下由于晶体管的特性漂移导致的第一节点(例如，上拉节点)充电不足的问题，提升了移位寄存器单元的电路结构的稳定性，延长了显示面板的使用寿命。
在第三阶段t3，第一时钟信号线CLK1提供高电平，由于第N级移位寄存器单元100的时钟信号端CLK和第一时钟信号线CLK1连接，因此，在此阶段，第一节点N1的电平被充电至第二高电平，同时，第N级移位寄存器单元100的输出电路120在第一节点N1的高电平的控制下导通，将第一时钟信号线CLK1提供的高电平输出至第N级移位寄存器单元的移位输出端N_CR和扫描信号输出端N_OUT1。
例如，在另一些示例中，下面结合图8B所示的信号时序图，对图7中所示的栅极驱动电路10的第N级移位寄存器单元的工作原理进行说明。例如，在该示例中，第N级移位寄存器单元可以采用图6所示的电路结构，不能采 用图5所示的电路结构，该移位寄存器单元的工作原理的具体介绍如下：
在第一阶段t1，第三时钟信号线CLK3提供高电平，由于第N-4级移位寄存器单元的时钟信号端CLK与第三时钟信号线CLK3连接，因此，在此阶段，第N-4级移位寄存器单元的移位输出端N-4_CR输出有效输出电平(例如，高电平)，由于第N级移位寄存器单元的第一电容的第二极与第N-4级移位寄存器单元的移位输出端N-4_CR连接，所以，第一电容C1的第二极由低电平变为高电平，且根据电容两端的电压不能突变这一特性，第一电容C1第一极(即第一节点N1)的电压被自举，因此，在此阶段，第一节点N1被充电至高电平；同时，在此阶段，第一时钟信号线CLK1提供一部分的高电平，第N级移位寄存器单元的时钟信号端CLK与第一时钟信号线CLK1连接，由于第一晶体管T1的栅极也与第N-4级移位寄存器单元的移位输出端N-4_CR连接，所以，第一晶体管T1响应于第N-4级移位寄存器单元的移位输出端N-4_CR输出的高电平而开启，使得第一电压端VGL1与第N级移位寄存器单元的移位输出端N_CR和扫描信号输出端N_OUT1连接，避免了第N级移位寄存器单元的输出端在此阶段输出第一时钟信号线CLK1提供的高电平，保证了显示面板的显示质量。
在第二阶段t2，第四时钟信号线CLK4提供高电平，由于第N-3级移位寄存器单元的时钟信号端CLK与第四时钟信号线CLK4连接，因此，在此阶段，第N-3级移位寄存器单元的移位输出端CR输出有效输出电平(例如，高电平)，又由于第N级移位寄存器单元的输入端INT与第N-3级移位寄存器单元的移位输出端N-3_CR连接，因此，在此阶段，第N级移位寄存器单元的第一节点N1继续被充电至高电平；同时，由于第一时钟信号线CLK1提供低电平，所以，在此阶段，第N级移位寄存器单元的移位输出端N_CR和扫描信号输出端N_OUT1输出低电平。
在第三阶段t3，第一时钟信号线CLK1提供高电平，由于第N级移位寄存器单元100的时钟信号端CLK和第一时钟信号线CLK1连接，因此，在此阶段，第一节点N1的电平被充电至第二高电平，同时，第N级移位寄存器单元100的输出电路120在第一节点N1的高电平的控制下导通，将第一时钟信号线CLK1提供的高电平输出至第N级移位寄存器单元的移位输出端N_CR和扫描信号输出端N_OUT1。
需要注意的是，该栅极驱动电路10还可以包括八条、十条或十二条以及更多的时钟信号线，时钟信号线的条数视具体情况而定，本公开的实施例在此不作限定。
需要说明的是，当采用本公开的实施例提供的栅极驱动电路10驱动一显示面板时，可以将该栅极驱动电路10设置于显示面板的一侧。例如，该显示面板包括多行栅线，栅极驱动电路10中的各级电压转换电路的第二输出端可以配置为依序和该多行栅线连接，以用于输出栅极扫描信号。需要说明的是，还可以分别在显示面板的两侧设置该栅极驱动电路10，以实现双边驱动，本公开的实施例对栅极驱动电路10的设置方式不作限定。
本公开的实施例还提供一种显示装置1，如图9所示，该显示装置1包括本公开实施例提供的栅极驱动电路10。该显示装置1还包括显示面板40，显示面板40包括由多个子像素单元410构成的阵列。例如，该显示装置1还可以包括数据驱动电路30。数据驱动电路30用于提供数据信号给像素阵列；栅极驱动电路10用于提供驱动信号给像素阵列，例如该驱动信号可以驱动子像素单元410中的扫描晶体管和感测晶体管。数据驱动电路30通过数据线DL与子像素单元410电连接，栅极驱动电路10通过栅线GL与子像素单元410电连接。
需要说明的是，本实施例中的显示装置1可以为：液晶面板、液晶电视、显示器、OLED面板、OLED电视、电子纸显示装置、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置1还可以包括显示面板等其他常规部件，本公开的实施例对此不作限定。
本公开的实施例提供的显示装置1的技术效果可以参考上述实施例中关于栅极驱动电路10的相应描述，这里不再赘述。
需要说明的是，为表示清楚、简洁，并没有给出该显示装置1的全部结构。为实现显示装置的必要功能，本领域技术人员可以根据具体应用场景进行设置其他未示出的结构，本公开的实施例对此不做限制。
本公开的实施例还提供一种驱动方法，可以用于驱动本公开的实施例提供的移位寄存器单元100，例如，在一些示例中，该驱动方法包括如下操作。
第一阶段，第一节点控制电路130响应于预充控制信号对第一节点N1进行充电。
第二阶段，输入电路110响应于输入信号对第一节点N1进行充电。
第三阶段，输出电路120在第一节点N1的电平信号的控制下，将输出信号在输出端OUT输出。
例如，在另一些示例中，移位寄存器单元100包括输出控制电路140，该驱动方法还包括：
输出控制电路140响应于预充控制信号，在非输出期间将输出端OUT控制在无效输出电平。
本公开的实施例提供的移位寄存器100的驱动方法的技术效果可以参考上述实施例中关于移位寄存器100的相应描述，这里不再赘述。
有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (15)

  1. 一种移位寄存器单元，包括输入电路、输出电路和第一节点控制电路；其中，
    所述输入电路配置为响应于输入信号对第一节点进行充电；
    所述输出电路配置为在所述第一节点的电平信号的控制下，将输出信号在输出端输出；
    所述第一节点控制电路配置为从预充控制端接收预充控制信号且响应于所述预充控制信号，在所述输出端输出所述输出信号之前，对所述第一节点进行充电。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述输入电路与所述第一节点连接，所述输出电路包括所述输出端，且所述输出电路与所述第一节点连接，所述第一节点控制电路分别与所述第一节点和所述预充控制端连接。
  3. 根据权利要求1或2所述的移位寄存器单元，还包括输出控制电路，其中，所述输出控制电路分别与所述输出端和所述预充控制端连接，且配置为从所述预充控制端接收所述预充控制信号且响应于所述预充控制信号，将所述输出端在非输出期间控制在无效输出电平。
  4. 根据权利要求1-3任一所述的移位寄存器单元，其中，所述第一节点控制电路包括：
    第一电容，其中，所述第一电容的第一极与所述第一节点连接，所述第一电容的第二极与所述预充控制端连接以接收所述预充控制信号。
  5. 根据权利要求3所述的移位寄存器单元，其中，所述输出控制电路包括：
    第一晶体管，其中，所述第一晶体管的栅极与所述预充控制端连接以接收所述预充控制信号，所述第一晶体管的第一极与所述输出端连接，所述第一晶体管的第二极与第一电压端连接以用于接收第一电压。
  6. 根据权利要求1-5任一所述的移位寄存器单元，还包括第一节点复位电路，
    其中，所述第一节点复位电路与所述第一节点连接，配置为响应于复位 信号对所述第一节点进行复位。
  7. 根据权利要求1-6任一所述的移位寄存器单元，还包括第二节点控制电路、第一节点降噪电路和输出降噪电路；其中，
    所述第二节点控制电路分别与所述第一节点以及第二节点连接，且配置为在所述第一节点的电平信号的控制下，对所述第二节点的电平进行控制；
    所述第一节点降噪电路与所述第一节点以及所述第二节点连接，且配置为在所述第二节点的电平信号的控制下，对所述第一节点进行降噪；
    所述输出降噪电路与所述第二节点以及所述输出端连接，且配置为在所述第二节点的电平信号的控制下，对所述输出端进行降噪。
  8. 根据权利要求1-6任一所述的移位寄存器单元，其中，所述输出端包括移位输出端和至少一个扫描信号输出端。
  9. 根据权利要求8所述的移位寄存器单元，其中，所述至少一个扫描信号输出端包括一个扫描信号输出端，所述输出电路包括第二晶体管、第三晶体管和第二电容；其中，
    所述第二晶体管的栅极和所述第一节点连接，所述第二晶体管的第一极和时钟信号端连接以接收时钟信号，所述第二晶体管的第二极和所述移位输出端连接；
    所述第三晶体管的栅极和所述第一节点连接，所述第三晶体管的第一极和所述时钟信号端连接以接收所述时钟信号，所述第三晶体管的第二极和所述扫描信号输出端连接；
    所述第二电容的第一极和所述第一节点连接，所述第二电容的第二极和所述扫描信号输出端或所述移位输出端连接；
    所述时钟信号被传输至所述输出端作为所述输出信号。
  10. 根据权利要求3所述的移位寄存器单元，还包括：第一节点复位电路、总复位电路、第二节点控制电路、第一节点降噪电路和输出降噪电路；其中，
    所述第一节点复位电路与所述第一节点连接，配置为响应于复位信号对所述第一节点进行复位；
    所述总复位电路与所述第一节点连接，配置为响应于总复位信号对所述第一节点进行复位；
    所述第二节点控制电路分别与所述第一节点、第二节点以及第三节点连接，且配置为在所述第一节点的电平信号的控制下，对所述第二节点的电平和所述第三节点的电平进行控制；
    所述第一节点降噪电路与所述第一节点以及所述第二节点连接，且配置为在所述第二节点的电平信号的控制下，对所述第一节点进行降噪；
    所述输出降噪电路与所述第二节点以及所述输出端连接，且配置为在所述第二节点的电平信号的控制下，对所述输出端进行降噪；
    其中，所述第一节点控制电路包括：
    第一电容，其中，所述第一电容的第一极与所述第一节点连接，所述第一电容的第二极与所述预充控制端连接以接收所述预充控制信号；
    所述输出控制电路包括：
    第一晶体管，其中，所述第一晶体管的栅极与所述预充控制端连接以接收所述预充控制信号，所述第一晶体管的第一极与所述输出端连接，所述第一晶体管的第二极与第一电压端连接以用于接收第一电压；
    在所述输出端包括移位输出端和一个扫描信号输出端的情形下，所述输出电路包括第二晶体管、第三晶体管和第二电容，其中，
    所述第二晶体管的栅极和所述第一节点连接，所述第二晶体管的第一极和时钟信号端连接以接收时钟信号，所述第二晶体管的第二极和所述移位输出端连接；
    所述第三晶体管的栅极和所述第一节点连接，所述第三晶体管的第一极和所述时钟信号端连接以接收所述时钟信号，所述第三晶体管的第二极和所述扫描信号输出端连接；
    所述第二电容的第一极和所述第一节点连接，所述第二电容的第二极和所述扫描信号输出端或所述移位输出端连接，所述时钟信号被传输至所述输出端作为所述输出信号；
    所述输入电路包括：
    第四晶体管，其中，所述第四晶体管的栅极和第一极彼此电连接，且配置为都和输入端连接以接收所述输入信号，所述第四晶体管的第二极配置为和所述第一节点连接；
    所述第一节点复位电路包括：
    第五晶体管，其中，所述第五晶体管的栅极配置为和复位端连接以接收所述复位信号，所述第五晶体管的第一极和所述第一节点连接，所述第五晶体管的第二极和第二电压端连接以用于接收第二电压；
    所述总复位电路包括：
    第六晶体管，其中，所述第六晶体管的栅极和总复位端连接以接收所述总复位信号，所述第六晶体管的第一极和所述第一节点连接，所述第六晶体管的第二极和所述第二电压端连接以用于接收所述第二电压；
    所述第二节点控制电路包括第七晶体管、第八晶体管、第九晶体管、第十晶体管、第二十七晶体管、第二十八晶体管、第二十九晶体管和第二十晶体管，其中，
    所述第七晶体管的栅极和第一控制节点连接，所述第七晶体管的第一极和第三电压端连接以用于接收第三电压，所述第七晶体管的第二极和所述第二节点连接；
    所述第八晶体管的栅极和所述第一节点连接，所述第八晶体管的第一极和所述第二节点连接，所述第八晶体管的第二极和所述第二电压端连接以用于接收所述第二电压；
    所述第九晶体管的栅极和其自身的第一极彼此电连接，且配置为都和所述第三电压端连接以用于接收所述第三电压，所述第九晶体管的第二极和所述第一控制节点连接；
    所述第十晶体管的栅极和所述第一节点连接，所述第十晶体管的第一极和所述第一控制节点连接，所述第十晶体管的第二极和所述第二电压端连接以用于接收所述第二电压；
    所述第二十七晶体管的栅极和第二控制节点连接，所述第二十七晶体管的第一极和第四电压端连接以用于接收第四电压，所述第二十七晶体管的第二极和所述第三节点连接；
    所述第二十八晶体管的栅极和所述第一节点连接，所述第二十八晶体管的第一极和所述第三节点连接，所述第二十八晶体管的第二极和所述第二电压端连接以用于接收所述第二电压；
    所述第二十九晶体管的栅极和其自身的第一极彼此电连接，且配置为都和所述第四电压端连接以用于接收所述第四电压，所述第二十九晶体管的第 二极和所述第二控制节点连接；
    所述第二十晶体管的栅极和所述第一节点连接，所述第二十晶体管第一极和所述第二控制节点连接，所述第二十晶体管第二极和所述第二电压端连接以用于接收所述第二电压；
    所述第一节点降噪电路包括第十一晶体管和第二十一晶体管，其中，
    所述第十一晶体管的栅极和所述第二节点连接，所述第十一晶体管的第一极和所述第一节点连接，所述第十一晶体管的第二极和所述第二电压端连接以用于接收所述第二电压；
    所述第二十一晶体管的栅极和所述第三节点连接，所述第二十一晶体管的第一极和所述第一节点连接，所述第二十一晶体管的第二极和所述第二电压端连接以用于接收所述第二电压；
    所述输出降噪电路可以实现为第十二晶体管、第二十二晶体管、第十三晶体管和第二十三晶体管，其中，
    所述第十二晶体管的栅极和所述第二节点连接，所述第十二晶体管的第一极和所述移位输出端连接，所述第十二晶体管的第二极和所述第二电压端连接以接收所述第二电压；
    所述第二十二晶体管的栅极和所述第三节点连接，所述第二十二晶体管的第一极和所述移位输出端连接，所述第二十二晶体管的第二极和所述第二电压端连接以用于接收所述第二电压；
    所述第十三晶体管的栅极和所述第二节点连接，所述第十三晶体管的第一极和所述扫描信号输出端连接，所述第十三晶体管的第二极和所述第一电压端连接以用于接收所述第一电压；
    所述第二十三晶体管的栅极和所述第三节点连接，所述第二十三晶体管的第一极和所述扫描信号输出端连接，所述第二十三晶体管的第二极和所述第一电压端连接以用于接收所述第一电压。
  11. 一种栅极驱动电路，包括多个级联的如权利要求1-10任一所述的移位寄存器单元。
  12. 根据权利要求11所述的栅极驱动电路，其中，
    除第1级至第m级移位寄存器单元外，其余各级移位寄存器单元的预充控制端和与其相隔至少m级的上级移位寄存器单元的输出端连接；
    除第1级至第m级移位寄存器单元外，其余各级移位寄存器单元的输入端和与其相隔m-1级的上级移位寄存器单元的输出端连接；
    除最后m级移位寄存器单元外，其余各级移位寄存器单元的复位端和与其相隔m-1级的下级移位寄存器单元的输出端连接；
    其中，m为大于2的整数。
  13. 一种显示装置，包括如权利要求11或12所述的栅极驱动电路。
  14. 一种如权利要求1所述的移位寄存器单元的驱动方法，包括：
    第一阶段，所述第一节点控制电路响应于所述预充控制信号对所述第一节点进行充电；
    第二阶段，所述输入电路响应于输入信号对所述第一节点进行充电；
    第三阶段，所述输出电路在所述第一节点的电平信号的控制下，将所述输出信号在所述输出端输出。
  15. 根据权利要求14所述的驱动方法，所述移位寄存器单元还包括输出控制电路，其中，所述驱动方法的所述第一阶段还包括：
    所述输出控制电路响应于所述预充控制信号，将所述输出端控制在无效输出电平。
PCT/CN2019/101103 2018-09-06 2019-08-16 移位寄存器单元、栅极驱动电路、显示装置及驱动方法 WO2020048305A1 (zh)

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