WO2020019819A1 - 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置 - Google Patents

移位寄存器单元及其驱动方法、栅极驱动电路及显示装置 Download PDF

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Publication number
WO2020019819A1
WO2020019819A1 PCT/CN2019/085872 CN2019085872W WO2020019819A1 WO 2020019819 A1 WO2020019819 A1 WO 2020019819A1 CN 2019085872 W CN2019085872 W CN 2019085872W WO 2020019819 A1 WO2020019819 A1 WO 2020019819A1
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WIPO (PCT)
Prior art keywords
signal
transistor
output
node
shift register
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PCT/CN2019/085872
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English (en)
French (fr)
Inventor
冯雪欢
李永谦
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/607,156 priority Critical patent/US11263942B2/en
Priority to EP19835214.8A priority patent/EP3828875A4/en
Priority to JP2019559054A priority patent/JP7366753B2/ja
Publication of WO2020019819A1 publication Critical patent/WO2020019819A1/zh

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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3674Details of drivers for scan electrodes
    • G09G3/3677Details of drivers for scan electrodes suitable for active matrices only
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266Details of drivers for scan electrodes
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287Organisation of a multiplicity of shift registers
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264Details of driving circuits
    • G09G2310/0286Details of a shift registers arranged for use in a driving circuit
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/06Details of flat display driving waveforms
    • G09G2310/061Details of flat display driving waveforms for resetting or blanking
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/08Details of timing specific for flat panels, other than clock recovery

Definitions

  • Embodiments of the present disclosure relate to a shift register unit, a driving method thereof, a gate driving circuit, and a display device.
  • display panels such as liquid crystal display panels (Liquid Crystal Display, LCD) or organic light emitting diode (Organic Light Emitting Diode, OLED) display panels, include a plurality of grid lines.
  • the gate line can be driven by a gate driving circuit.
  • the gate driving circuit is usually integrated in a gate driving chip (Gate IC).
  • Gate IC gate driving chip
  • a shift register unit including: a blanking input circuit, a display input circuit, an output circuit, a control node, and a first node; the blanking input circuit is configured to respond to a blanking input signal Inputting a blanking control signal to the first node during a blanking period, the blanking input circuit including a charging sub-circuit configured to respond to a first compensation control signal and a second compensation control signal, Inputting the blanking control signal to the control node; the display input circuit is configured to input a display control signal to the first node during a display period in response to a display input signal; and the output circuit is configured to The composite output signal is output to an output terminal under the control of the level of the first node.
  • one of the first compensation control signal and the second compensation control signal is a random signal.
  • the charging sub-circuit includes a first transistor and a second transistor, and a gate of the first transistor is configured to receive the first compensation control signal
  • a first pole of the first transistor is configured to be connected to a blanking control signal terminal to receive the blanking control signal, and a second pole of the first transistor is configured to be connected to a first of the second transistor
  • the second electrode of the second transistor is configured to be connected to the control node, and the gate of the second transistor is configured to receive the second compensation control signal.
  • the blanking input circuit further includes: a storage sub-circuit configured to store the blanking control signal input by the charging sub-circuit; an isolator A circuit configured to input the blanking control signal to the first node under the control of the blanking input signal.
  • the storage subcircuit includes a first capacitor, and a first pole of the first capacitor is configured to be connected to the control node, and the first The second pole of the capacitor is configured to be connected to the first voltage terminal to receive the first voltage;
  • the isolation sub-circuit includes a third transistor, and the gate of the third transistor is configured to be connected to the blanking input signal terminal to receive In the blanking input signal, a first pole of the third transistor is configured to be connected to the control node, and a second pole of the third transistor is configured to be connected to the first node.
  • the display input circuit includes a fourth transistor, and a gate of the fourth transistor is connected to a display input signal terminal to receive the display input signal, so A first pole of the fourth transistor is connected to a display control signal terminal to receive the display control signal, and a second pole of the fourth transistor is connected to the first node.
  • the output terminal includes a shift signal output terminal and a first pixel signal output terminal
  • the output circuit includes a first output transistor, a second output transistor, and A second capacitor
  • a gate of the first output transistor is connected to the first node, a first pole of the first output transistor is connected to a first output clock signal terminal to receive a first output clock signal, and the first A second pole of an output transistor is connected to the shift signal output terminal
  • a gate of the second output transistor is connected to the first node, and a first pole of the second output transistor is connected to the first output.
  • a clock signal terminal is connected to receive the first output clock signal, a second pole of the second output transistor is connected to the first pixel signal output terminal; a first pole of the second capacitor and the first node Connected, the second pole of the second capacitor is connected to the second pole of the first output transistor; the first output clock signal is transmitted to the shift signal via the first output transistor The output end is used as a first output signal, and the first output clock signal is transmitted to the first pixel signal output end as a second output signal through the second output transistor.
  • the composite output signal includes the first output signal. An output signal and the second output signal.
  • the output terminal further includes a second pixel signal output terminal
  • the output circuit further includes a third output transistor, and a gate of the third output transistor Is connected to the first node, a first pole of the third output transistor is connected to a second output clock signal terminal to receive a second output clock signal, and a second pole of the third output transistor is connected to the second pixel
  • the signal output terminal is connected, the second output clock signal is transmitted to the second pixel signal output terminal via the third output transistor as a third output signal, and the composite output signal further includes the third output signal.
  • the blanking control signal and the display control signal are the same.
  • the shift register unit provided by at least some embodiments of the present disclosure further includes a noise reduction circuit, a first control circuit, and a second node, and the noise reduction circuit is configured to be under the control of the level of the second node.
  • the noise reduction circuit is configured to be under the control of the level of the second node.
  • the first control circuit is configured to control the level of the second node under the control of the level of the first node.
  • the first control circuit includes a fifth transistor, a sixth transistor, and a seventh transistor; a gate of the fifth transistor and the first node Connected, the first pole of the fifth transistor is connected to the second node, the second pole of the fifth transistor is connected to a second voltage terminal to receive a second voltage; the gate of the sixth transistor and the first One pole is connected and configured to be connected to a third voltage terminal to receive a third voltage, the second pole of the sixth transistor is connected to the second node; the gate of the seventh transistor is connected to the first pole and It is configured to be connected to a fourth voltage terminal to receive a fourth voltage, and a second pole of the seventh transistor is connected to the second node.
  • the output terminal includes a shift signal output terminal and a first pixel signal output terminal
  • the noise reduction circuit includes a first noise reduction transistor, a second noise reduction A noise reduction transistor and a third noise reduction transistor; a gate of the first noise reduction transistor is connected to the second node, a first pole of the first noise reduction transistor is connected to the first node, and the first The second pole of the noise reduction transistor is connected to a second voltage terminal to receive a second voltage; the gate of the second noise reduction transistor is connected to the second node, and the first pole of the second noise reduction transistor is connected to all The shift signal output terminal is connected, the second pole of the second noise reduction transistor is connected to the second voltage terminal to receive the second voltage; the gate of the third noise reduction transistor is connected to the second A node is connected, a first pole of the third noise reduction transistor is connected to the first pixel signal output terminal, and a second pole of the third noise reduction transistor is connected to a fifth voltage terminal to receive a
  • the output terminal further includes a second pixel signal output terminal
  • the noise reduction circuit further includes a fourth noise reduction transistor
  • the gate of the fourth noise reduction transistor is connected to the second node, the first pole of the fourth noise reduction transistor is connected to the second pixel signal output terminal, and the second of the fourth noise reduction transistor is connected to the second node.
  • a pole is connected to the fifth voltage terminal to receive the fifth voltage.
  • the shift register unit provided by at least some embodiments of the present disclosure further includes a second control circuit; the second control circuit is configured to control a level of the second node in response to a first control signal.
  • the shift register unit provided by at least some embodiments of the present disclosure further includes a blanking reset circuit and a display reset circuit, the blanking reset circuit is configured to reset the first node in response to a blanking reset signal, so The display reset circuit is configured to reset the first node in response to a display reset signal.
  • At least some embodiments of the present disclosure also provide a gate driving circuit including a plurality of cascaded shift register units as described above.
  • the gate driving circuit further includes a first sub-clock signal line, a second sub-clock signal line, a third sub-clock signal line, and a fourth sub-clock signal line; in the shift register, a first case unit comprising a clock signal output terminal, a first first-stage 4n 1 -3 clock signal output terminal of the shift register unit is connected to the first sub-clock signal line; 4n 1 -2-stage shift register unit The first output clock signal terminal is connected to the second sub clock signal line; the first output clock signal terminal of the 4n 1 -1 stage shift register unit is connected to the third sub clock signal line; the 4n 1 stage shift The first output clock signal terminal of the bit register unit is connected to the fourth sub-clock signal line; n 1 is an integer greater than 0.
  • n 2 is an integer greater than 0.
  • a signal output from a shift signal output terminal of the nth 2 -stage shift register unit is used as a signal of the n 2 + 2-stage shift register unit.
  • the signal output from the terminal is used as the second compensation control signal of the n 2 +2 stage shift register unit, and the signal output from the shift signal output terminal of the n 2 stage shift register unit is also used as the n 2 + Blanking control signal for the 2-stage shift register unit.
  • the gate driving circuit provided by at least some embodiments of the present disclosure further includes a fifth sub-clock signal line; and in a case where the shift register unit includes a blanking input signal terminal, the blanking input signal of each stage of the shift register unit The terminal is connected to the fifth sub-clock signal line.
  • At least some embodiments of the present disclosure also provide a display device including the gate driving circuit according to any one of the above.
  • the display period includes: a first input stage, In response to the display input signal, inputting the display control signal to the first node through the display input circuit; a first output stage, under the control of the level of the first node, through the output The circuit outputs the composite output signal to the output terminal; in the charging phase, in response to the first compensation control signal and the second compensation control signal, the blanking control signal is input to the charging sub-circuit through The control node; the blanking period includes: a second input stage, in response to the blanking input signal, inputting the blanking control signal to the first node through the blanking input circuit; In the two output stage, under the control of the level of the first node, the composite output signal is output to the output terminal through the output circuit.
  • FIG. 1 is a schematic block diagram of a shift register unit according to some embodiments of the present disclosure
  • FIG. 2 is a schematic block diagram of another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 3 is a schematic block diagram of still another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 4 is a schematic block diagram of still another shift register unit according to some embodiments of the present disclosure.
  • 5A is a circuit structural diagram of a shift register unit shown in FIG. 2;
  • 5B is a circuit structural diagram of the shift register unit shown in FIG. 3;
  • 5C is a circuit configuration diagram of the shift register unit shown in FIG. 4;
  • FIG. 6A is another circuit configuration diagram of the shift register unit shown in FIG. 2; FIG.
  • FIG. 6B is another circuit configuration diagram of the shift register unit shown in FIG. 3; FIG.
  • FIG. 6C is another circuit configuration diagram of the shift register unit shown in FIG. 4; FIG.
  • FIG. 7 is another circuit configuration diagram of the shift register unit shown in FIG. 2;
  • FIG. 9 is a schematic block diagram of a gate driving circuit according to some embodiments of the present disclosure.
  • 10A is a circuit structural diagram of a blanking input circuit and a display input circuit provided by some embodiments of the present disclosure
  • 10B is a circuit structural diagram of another blanking input circuit and a display input circuit provided by some embodiments of the present disclosure.
  • FIG. 10C is a circuit structural diagram of a blanking input circuit and a display input circuit provided by some embodiments of the present disclosure.
  • 10D is a circuit structure diagram of another blanking input circuit and a display input circuit provided by some embodiments of the present disclosure.
  • FIG. 10E is a circuit structural diagram of yet another blanking input circuit and a display input circuit provided by some embodiments of the present disclosure.
  • FIG. 11 is a signal timing diagram of a gate driving circuit provided by some embodiments of the present disclosure.
  • FIG. 12 is a schematic block diagram of a display device provided by some embodiments of the present disclosure.
  • FIG. 13 is a flowchart of a method for driving a shift register unit provided by some embodiments of the present disclosure.
  • a sensing transistor in addition to providing a pixel compensation circuit in a sub-pixel unit for internal compensation, a sensing transistor can also be provided for external compensation.
  • a gate drive circuit composed of a shift register unit needs to provide a driving signal for a scanning transistor and a sensing transistor to a sub-pixel unit in a display panel, for example, in a display period of one frame (DS ) Provides a scan driving signal for a scanning transistor, and a sensing driving signal for a sensing transistor is provided in a blanking period (BL) of one frame.
  • the sensing driving signals output by the gate driving circuit are scanned sequentially row by row. For example, the output during the blanking period of the first frame is used for the first row in the display panel.
  • the sensing driving signal of the sub-pixel unit of the pixel is output during the blanking period of the second frame for the sensing driving signal of the sub-pixel unit in the second row of the display panel, and so on, so as to complete the progressive sequence compensation of the display panel.
  • the long-term progressive sequence compensation will bring two serious problems: one is that there will be a scanning line that moves progressively during the scanning display of multiple frames, and the other is that the display panel will be caused by the difference in compensation time.
  • the shift register unit includes a blanking input circuit, a display input circuit, an output circuit, a control node, and a first Node;
  • the blanking input circuit is configured to input a blanking control signal to the first node in a blanking period in response to the blanking input signal, and the blanking input circuit includes a charging sub-circuit configured to respond to the first node A compensation control signal and a second compensation control signal to input a blanking control signal to the control node;
  • the display input circuit is configured to input the display control signal to the first node in a display period in response to the display input signal;
  • the output circuit is configured to The composite output signal is output to the output terminal under the control of the level of the first node.
  • the circuit structure of the shift register unit according to the embodiment of the present disclosure is simple, can realize random compensation, avoid the brightness deviation of the scan line and the panel caused by the progressive compensation, improve the display uniformity and the display effect.
  • random compensation refers to an external compensation method that is different from sequential compensation in a row.
  • a random output corresponding to any row in the display panel can be randomly output.
  • the driving signals of the sub-pixel units are sensed to implement the operation of compensating the sub-pixel units of the row.
  • one frame “each frame” or “a certain frame” includes a display period and a blanking period performed sequentially, for example, the gate driving circuit outputs a display output signal in the display period
  • the display output signal can drive the display panel to complete a complete scanning display of an image from the first line to the last line.
  • the gate driving circuit outputs a blanking output signal, and the blanking output signal can be used for driving.
  • the sensing transistors in a row of sub-pixel units in the display panel are used to complete external compensation of the row of sub-pixel units.
  • FIG. 1 is a schematic block diagram of a shift register unit according to some embodiments of the present disclosure.
  • the shift register unit 10 may include a blanking input circuit 100, a display input circuit 200, an output circuit 300, a control node H, and a first node Q.
  • a gate driving circuit By cascading a plurality of the shift register units 10, a gate driving circuit can be obtained.
  • the gate driving circuit is used for driving a display panel, and sequentially provides scanning signals for a plurality of gate lines of the display panel, thereby displaying one frame on the display panel. Progressive or interlaced scanning is performed during the screen.
  • the blanking input circuit 100 is configured to input a blanking control signal (ie, a blanking pull-up signal) to a first node Q (here, a pull-up node) in a blanking period in response to the blanking input signal.
  • a blanking control signal ie, a blanking pull-up signal
  • the blanking input circuit 100 is connected to a blanking input signal terminal STU1, a blanking control signal terminal BP (ie, a blanking pull-up signal terminal) and a first node Q.
  • the blanking input circuit 100 may receive and store the blanking control signal provided by the blanking control signal terminal BP during the display period of the Nth frame, and output to the first node Q according to the blanking input signal during the blanking period of the Nth frame.
  • the control signal is blanked to pull up the potential of the first node Q to the working potential.
  • the blanking input circuit 100 may also receive and store a blanking control signal during the blanking period of the Nth frame, and output blanking to the first node Q according to the blanking input signal during the blanking period of the N + 1th frame. Control signal to pull up the potential of the first node Q to the working potential.
  • the embodiments of the present disclosure are not limited thereto.
  • the blanking input circuit 100 includes a charging sub-circuit 110 configured to input a blanking control signal to a control node H (here, pull-up control) in response to a first compensation control signal and a second compensation control signal. node).
  • a control node H here, pull-up control
  • the charging sub-circuit 110 is connected to the first compensation control signal terminal OE1, the second compensation control signal terminal OE2, the blanking control signal terminal BP, and the control node H.
  • the charging sub-circuit 110 inputs the blanking control signal output from the blanking control signal terminal BP to the control node H.
  • the display input circuit 200 is configured to input a display control signal (ie, a display pull-up signal) to the first node Q during a display period in response to a display input signal.
  • a display control signal ie, a display pull-up signal
  • the display input circuit 200 is connected to the display input signal terminal STU2, the display control signal terminal DP (that is, the display pull-up signal terminal) and the first node Q.
  • the display input circuit 200 is connected to the display input signal terminal STU2
  • the display control signal terminal DP is connected to the first node Q, so that the display control signal provided by the display control signal terminal DP is written to the first node Q, so that the first node The potential of Q is pulled up to the working potential.
  • the blanking control signal and the display control signal may be the same. That is, the blanking control signal terminal BP and the display control signal terminal DP can be the same signal terminal, thereby reducing the number of signal terminals and saving costs; or, the blanking control signal terminal BP and the display control signal terminal DP can also be Different signal ends, but output the same signal. This disclosure does not limit this.
  • the blanking control signal and the display control signal may be different.
  • the output circuit 300 is configured to output a composite output signal to the output terminal OP under the control of the level of the first node Q.
  • the output circuit 300 is connected to a first node Q, a first output clock signal terminal CLKD, and an output terminal OP.
  • the composite output signal provided by the first output clock signal terminal CLKD is output to the output terminal OP.
  • the output signal of the output terminal OP may include a display output signal and a blanking output signal, and the display output signal and the blanking output signal may be signals of two independent waveforms having different widths and timings.
  • the output circuit 300 outputs a display output signal through the output terminal OP under the control of the level of the first node Q to drive the scanning transistor in the pixel unit to perform display;
  • the output circuit 300 outputs a blanking output signal through the output terminal OP under the control of the level of the first node Q to drive the sensing transistor in the pixel unit to perform compensation detection.
  • the blanking input circuit 100, the display input circuit 200, and the output circuit 300 may be integrated, so that the blanking output signal and the display output signal of the blanking period of a frame of the picture pass through the same One output circuit 300 outputs, thereby simplifying the circuit structure and reducing the size of the shift register unit and the gate driving circuit including the shift register unit.
  • one of the first compensation control signal and the second compensation control signal is a random signal.
  • the first compensation control signal is a random signal
  • the first compensation control signal terminal OE1 is connected to an external control circuit
  • the external control circuit may provide the first compensation control signal terminal OE1 with the first compensation control signal
  • the first compensation The control signal may be a random signal.
  • the external control circuit may be implemented by, for example, a Field Programmable Gate Array (FPGA) or other signal generating circuits, and thereby outputting a random signal of an appropriate type as the first compensation control signal.
  • the external control circuit may be configured to output a random signal to the first compensation control signal terminal OE1 in a display period of one frame.
  • the shift register unit provided by the present disclosure is described in detail by taking the first compensation control signal as a random signal as an example.
  • the present disclosure is not limited to this.
  • the second compensation control signal may be a random signal, or both the first compensation control signal and the second compensation control signal are random signals.
  • the output terminal OP may include a shift signal output terminal and a first pixel signal output terminal.
  • the second compensation control signal terminal OE2 of the shift register unit of the current stage may be shifted with the shift register unit of the current stage.
  • the signal output terminal is connected, so that the signal output from the shift signal output terminal can be used as the second compensation control signal.
  • the external control circuit may be connected to the shift signal output terminals of all stages of the shift register unit. According to actual needs, the external control circuit may randomly select the shift of one shift register unit during a display period of one frame. The signal at the signal output terminal is output to the first compensation control signal terminal OE1.
  • the i-th row sub-pixel unit corresponds to the i-th stage shift register unit.
  • an external control circuit is used to shift the i-th stage shift register unit.
  • the signal output from the signal output terminal is transmitted to the first compensation control signal terminal OE1 of all stages of the shift register unit, that is, the first compensation control signal of all stages of the shift register unit can be output with the shift signal of the i-th stage shift register unit.
  • the waveform pulse width and timing of the signal output from the terminal are the same.
  • the second compensation control signal of the i-th shift register unit is also the signal output from the shift signal output of the i-th shift register unit, and the charging sub-circuit 110 It is controlled by the first compensation control signal and the second compensation control signal.
  • the charging sub-circuit 110 in the i-th stage shift register unit can perform the first compensation control signal and the second compensation control. Conducted under signal control. Since the charging sub-circuit 110 is connected to the blanking control signal terminal BP and the control node H, in the i-th shift register unit, when the charging sub-circuit 110 is turned on, the blanking control signal output by the blanking control signal terminal BP is high.
  • the control node H can be charged by using the blanking control signal, so that the control node H is charged to a high level. Therefore, during the blanking period of the Nth frame, the high-level signal of the control node H of the i-th stage shift register unit can be transmitted to the first node Q, so that the output circuit 300 of the i-th stage shift register unit can A blanking output signal for driving the sensing transistors in the i-th row of the sub-pixel units is output.
  • the shift register unit provided by the embodiment of the present disclosure may also implement sequential line-by-line compensation.
  • the second compensation control signal terminal OE2 of the shift register unit of this stage may be connected to the shift signal output terminal of the shift register unit of this stage.
  • the first compensation control signal terminal OE1 receives the signals of the shift signal output terminals of the first-stage shift register units during the display period of the first frame, and the first compensation control signal terminals OE1 of the shift register units of all stages in the second frame. During the display period, the signal of the shift signal output terminal of the second-stage shift register unit is received, and so on.
  • the shift register unit 10 provided by the embodiment of the present disclosure, by setting the charging sub-circuit 110, can also realize random compensation on the premise of taking into account the progressive order compensation, so as to avoid scanning lines and display brightness changes caused by progressive order compensation. Uniformity and other display problems.
  • the blanking input circuit 100 further includes a storage sub-circuit 120 and an isolation sub-circuit 130.
  • the storage sub-circuit 120 is connected to the control node H and is configured to store a blanking control signal input by the charging sub-circuit 110.
  • the control node H is charged to a high level by using the blanking control signal, and the storage sub-circuit 120 may store the blanking control signal so that the high level of the control node H is always Hold until the blanking period of the frame.
  • the isolation sub-circuit 130 is configured to input a blanking control signal to the first node Q during a blanking period under the control of the blanking input signal.
  • the isolation sub-circuit 130 is connected to a blanking input signal terminal STU1, a control node H, and a first node Q.
  • the control node H is connected to the first node Q, thereby inputting the blanking control signal stored in the storage sub-circuit 120 to the first
  • a node Q is used to charge the first node Q and pull up the potential of the first node Q to the working potential.
  • the blanking input circuit 100 may include any applicable sub-circuits, and is not limited to the above-mentioned charging sub-circuit 110, storage sub-circuit 120, and isolation sub-circuit 130, as long as the corresponding functions can be realized Just fine.
  • FIG. 2 is a schematic block diagram of another shift register unit provided by some embodiments of the present disclosure.
  • the shift register unit 10 may further include a noise reduction circuit 400 (here, a pull-down circuit), a first control circuit 500 (here, a first pull-down control circuit), and a second node QB (here Is a drop-down node).
  • a noise reduction circuit 400 here, a pull-down circuit
  • a first control circuit 500 here, a first pull-down control circuit
  • a second node QB here Is a drop-down node
  • the noise reduction circuit 400 is configured to perform noise reduction on the first node Q and the output terminal OP under the control of the level of the second node QB; that is, the noise reduction circuit 400 is configured to perform noise reduction on the second node QB Under the control of the level, the level of the first node Q and the electrical average of the output terminal OP are pulled down to a low level. For example, as shown in FIG.
  • the noise reduction circuit 400 is connected to the second node QB, the first node Q, the second voltage terminal VGL1 and the output terminal OP, and when the level of the noise reduction circuit 400 is controlled at the second node QB
  • the first node Q and the output terminal OP may be connected to the second voltage terminal VGL1 (for example, a low voltage terminal), so that the first node Q is pulled down to a non-working potential through the second voltage of the second voltage terminal VGL1.
  • the level of the output terminal OP is pulled down to a low level to achieve the noise reduction of the first node Q and the output terminal OP.
  • the second voltage terminal VGL1 may be configured to provide a second voltage, and the second voltage is a DC low-level signal.
  • the second voltage is a DC low-level signal.
  • the first control circuit 500 is configured to control the level of the second node QB under the control of the level of the first node Q.
  • the first control circuit 500 connects the first node Q and the second node QB.
  • the first control circuit 500 may be configured to pull down the second node QB to a low level when the first node Q is high, and pull up the second node QB to a high level when the first node Q is low.
  • the first control circuit 500 may be an inverter circuit, an input terminal of the inverter circuit is connected to the first node Q, and an output terminal of the inverter circuit is connected to the second node QB.
  • FIG. 3 is a schematic block diagram of still another shift register unit provided by some embodiments of the present disclosure
  • FIG. 4 is a schematic block diagram of still another shift register unit provided by some embodiments of the present disclosure.
  • the shift register unit 10 may further include a second control circuit 600 (here, a second pull-down control circuit).
  • the second control circuit 600 is configured to control the level of the second node QB in response to a first control signal (here, a blanking pull-down control signal).
  • a first control signal here, a blanking pull-down control signal
  • the second control circuit 600 is connected to the second voltage terminal VGL1, the second node QB, and the blanking pull-down control terminal Con1, and the second control circuit 600 is configured to be in a blanking period of one frame.
  • the blanking pull-down control terminal Con1 is turned on under the control of the first control signal, so that the second node QB is connected to the second voltage terminal VGL1, so that the second node QB is pulled down to non- Working potential.
  • the shift register unit 10 includes a second control circuit 600.
  • the second control circuit 600 can pull down the second node QB during a blanking period of a frame to ensure that the second node QB is at a low power level. Leveling, so that the blanking input circuit 100 charges the first node Q more fully, and the high level of the first node Q reaches a predetermined value. Therefore, the transistor threshold voltage can be prevented from affecting the output signal and the reliability of the circuit is enhanced.
  • the shift register unit 10 may further include a third control circuit 700 (here, a third pull-down control circuit).
  • the third control circuit 700 is configured to control the level of the second node QB in response to a second control signal (here, a display pull-down control signal).
  • a second control signal here, a display pull-down control signal
  • the third control circuit 700 is connected to the second node QB, the display pull-down control terminal Con2, and the second voltage terminal VGL1.
  • the second node QB is connected to the second voltage terminal VGL1, so as to pass the second voltage
  • the second voltage at the terminal VGL1 pulls the second node QB to a non-working potential.
  • the third control circuit 700 may pull down the second node QB during a display period of one frame to ensure that the second node QB is at a low level so that the display input
  • the circuit 200 charges the first node Q more fully, so that the high level of the first node Q reaches a predetermined value. Therefore, it can prevent the output signal from being affected after the threshold voltage of the transistor drifts, thereby enhancing the reliability of the circuit.
  • the shift register unit may also include only the third control circuit 700, and The second control circuit 600 is not included.
  • the shift register unit 10 further includes a blanking reset circuit 800 and a display reset circuit 900.
  • the blanking reset circuit 800 is configured to reset the first node Q in response to a blanking reset signal.
  • the display reset circuit 900 is configured to reset the first node Q in response to a display reset signal.
  • the blanking reset circuit 800 is connected to the blanking reset signal terminal TR, the second voltage terminal VGL1 and the first node Q.
  • the first node Q Under the control of the blanking reset signal provided by the blanking reset signal terminal TR, when the blanking reset circuit 800 is turned on, the first node Q is connected to the second voltage terminal VGL1 so as to pass the second voltage of the second voltage terminal VGL1
  • the first node Q is pulled down to a non-working potential to reset the first node Q, that is, write a low-level second voltage to the first node Q.
  • the blanking reset circuit 800 is turned on under the control of the blanking reset signal, thereby writing the second voltage output from the second voltage terminal VGL1 to the first A node Q to reset the first node Q; for another example, before the display period of one frame, the blanking reset circuit 800 is turned on under the control of the blanking reset signal, so that the second voltage terminal VGL1 outputs the first Two voltages are written into the first node Q to reset the first node Q.
  • the display reset circuit 900 is connected to the display reset signal terminal STD, the second voltage terminal VGL1 and the first node Q.
  • the first node Q is connected to the second voltage terminal VGL1, so that the first node is connected to the first voltage by the second voltage of the second voltage terminal VGL1.
  • the node Q is pulled down to a non-working potential to reset the first node Q.
  • the display reset circuit 900 is turned on under the control of the display reset signal, thereby writing the second voltage output from the second voltage terminal VGL1 to the first node Q To reset the first node Q.
  • the first control circuit 500, the second control circuit 600, the third control circuit 700, the blanking reset circuit 800, and the display reset circuit 900 are all connected to the second voltage VGL1 to Receives a DC low-level signal, but is not limited to this.
  • the first control circuit 500, the second control circuit 600, the third control circuit 700, the blanking reset circuit 800, and the display reset circuit 900 may also be connected to different power supply voltage terminals, respectively. In order to receive different low-level signals, as long as the corresponding functions can be achieved, this disclosure does not specifically limit this.
  • FIG. 5A is a circuit configuration diagram of the shift register unit shown in FIG. 2
  • FIG. 5B is a circuit configuration diagram of the shift register unit shown in FIG. 3
  • FIG. 5C is a shift register shown in FIG. 4.
  • FIG. 6A is another circuit structure diagram of the shift register unit shown in FIG. 2
  • FIG. 6B is another circuit structure diagram of the shift register unit shown in FIG. 3.
  • FIG. 6C is another circuit configuration diagram of the shift register unit shown in FIG. 4.
  • each transistor is described as an N-type transistor, but this does not constitute a limitation on the embodiments of the present disclosure.
  • the charging sub-circuit 110 includes a first transistor M1 and a second transistor M2.
  • the gate of the first transistor M1 is configured to be connected to the first compensation control signal terminal OE1 to receive the first compensation control signal
  • the first electrode of the first transistor M1 is configured to be connected to the blanking control signal terminal BP to receive the blanking.
  • the second pole of the first transistor M1 is configured to be connected to the first pole of the second transistor M2
  • the second pole of the second transistor M2 is configured to be connected to the control node H
  • the gate of the second transistor M1 is It is configured to be connected to the second compensation control signal terminal OE2 to receive the second compensation control signal.
  • the blanking control signal terminal BP and the display control signal terminal DP may be the same signal terminal, and both are the sixth voltage terminal VDD, that is, the sixth voltage terminal VDD is equal to the foregoing.
  • Blanking control signal terminal BP and display control signal terminal DP are configured to provide a sixth voltage
  • the sixth voltage is a DC high-level signal.
  • the first pole of the first transistor M1 is configured to be connected to the sixth voltage terminal VDD to receive the sixth voltage
  • the blanking control signal may be the sixth voltage.
  • the first compensation control signal and the second compensation control signal are both active levels (eg, high level)
  • the first transistor M1 and the second transistor M2 are turned on, so that the sixth voltage terminal VDD and the control node H Connected to write the sixth voltage (high-level signal) to the control node H.
  • the first pole of the first transistor M1 may also be connected to other signal terminals to receive the blanking control signal. This is not limited.
  • the storage sub-circuit 120 includes a first capacitor C1.
  • the first pole of the first capacitor C1 is configured to be connected to the control node H, and the second pole of the first capacitor C1 is configured to be connected to the first voltage terminal VA to receive the first voltage.
  • the blanking control signal is written to the control node H, the first capacitor C1 stores the blanking control signal (high level), and maintains the control node H at a high level until the frame Blanking period.
  • the first voltage terminal VA is configured to provide a first voltage.
  • the first voltage is a DC high-level signal; in other examples, the first voltage may be a DC low-level signal.
  • the following embodiments are the same and will not be described again.
  • the first capacitor C1 may be a capacitor device manufactured through a process, for example, a capacitor device is realized by manufacturing a special capacitor electrode, and each electrode of the capacitor may be a metal layer or a semiconductor. Layer (such as doped polysilicon), and the first capacitor C1 may also be a parasitic capacitor between various devices, which may be implemented by the transistor itself and other devices and lines.
  • the connection method of the first capacitor C1 is not limited to the method described above, and may also be other suitable connection methods, as long as it can store the blanking control signal written to the control node H.
  • the first pole of the first capacitor C1 is configured to be connected to the control node H, and the second pole of the first capacitor C1 is grounded.
  • the isolation sub-circuit 130 includes a third transistor M3.
  • the gate of the third transistor M3 is configured to be connected to the blanking input signal terminal STU1 to receive the blanking input signal
  • the first pole of the third transistor M3 is configured to be connected to the control node H
  • the second pole of the third transistor M3 It is configured to be connected to the first node Q.
  • the first clock signal terminal CLKA is equivalent to the aforementioned blanking input signal terminal STU1, and the first clock signal terminal CLKA is used to provide the first clock signal and blank the input signal. It may be a first clock signal. That is, as shown in FIGS. 5A to 6C, the gate of the third transistor M3 is configured to be connected to the first clock signal terminal CLKA. When the first clock signal is at a high level, the third transistor M3 is turned on, and the control node H is connected to the first node Q, so that the blanking control signal is written to the first node Q to increase the potential of the first node Q Pull to working potential.
  • the display input circuit 200 includes a fourth transistor M4.
  • the gate of the fourth transistor M4 is connected to the display input signal terminal STU2 to receive the display input signal
  • the first electrode of the fourth transistor M4 is connected to the display control signal terminal DP (that is, the sixth voltage terminal VDD) to receive the display control signal (that is, (Sixth voltage)
  • the second pole of the fourth transistor M4 is connected to the first node Q.
  • the fourth transistor M4 is turned on, and the sixth voltage terminal VDD is connected to the first node Q, thereby connecting the sixth voltage terminal VDD.
  • the voltage is written into the first node Q, and the potential of the first node Q is pulled up to the working potential.
  • the first pole of the fourth transistor M4 may also be connected to other signal terminals to receive display control signals. Not limited.
  • the output terminal OP may include a shift signal output terminal CR and a first pixel signal output terminal OT1, and a signal output from the shift signal output terminal CR and the first pixel signal output terminal OT1 output
  • the signals are the same.
  • the shift register unit 10 shown in FIGS. 5A to 6C is cascaded to form a gate driving circuit
  • the display input signal terminal STU2 of the n + 2 stage shift register unit 10 may be connected to the n stage
  • the shift signal output terminal CR of the shift register unit 10 is connected, and n is an integer greater than 0.
  • the first pixel signal output terminal OT1 may be used to provide a scanning driving signal for a pixel circuit.
  • the output circuit 300 may include a first output transistor M13, a second output transistor M15, and a second capacitor C2.
  • the gate of the first output transistor M13 is connected to the first node Q.
  • the first pole of the first output transistor M13 is connected to the first output clock signal terminal CLKD to receive the first output clock signal.
  • the second pole of the first output transistor M13 Connected to the shift signal output terminal CR; the gate of the second output transistor M15 is connected to the first node Q, and the first pole of the second output transistor M15 is connected to the first output clock signal terminal CLKD to receive the first output clock signal,
  • the second pole of the second output transistor M15 is connected to the first pixel signal output terminal OT1; the first pole of the second capacitor C2 is connected to the first node Q, and the second pole of the second capacitor C2 is connected to the first pole of the first output transistor M13. Diode connection.
  • both the first output transistor M13 and the second output transistor M15 are turned on, and the first output clock signal is transmitted to the shift signal via the first output transistor M13.
  • the output terminal CR is used as the first output signal, and the first output clock signal is transmitted to the first pixel signal output terminal OT1 as the second output signal through the second output transistor M15.
  • the composite output signal includes a first output signal and a second output signal, and the first output signal and the second output signal are the same.
  • the second output signal includes the above display output signal and the blanking output signal, that is, during the display period, the signal output by the first pixel signal output terminal OT1 is the display output signal; during the blanking period, the first pixel signal output terminal OT1 outputs The signal is the blanking output signal.
  • the second capacitor C2 may be a capacitor device manufactured by a process, for example, a capacitor device is realized by manufacturing a special capacitor electrode, and each electrode of the capacitor may be a metal layer or a semiconductor. Layer (such as doped polysilicon), and the second capacitor C2 can also be a parasitic capacitor between the transistors, which can be implemented by the transistor itself and other devices and lines, as long as the level of the first node Q can be maintained and When the shift signal output terminal CR or the first pixel signal output terminal OT1 outputs a signal, the bootstrap effect can be realized.
  • the output terminal OP further includes a second pixel signal output terminal OT2
  • the output circuit 300 further includes a third output transistor M17.
  • the output circuit 300 is also connected to a second output clock signal terminal CLKE, and the second output clock signal terminal CLKE is used to output a second output clock signal.
  • the gate of the third output transistor M17 is connected to the first node Q.
  • the first pole of the third output transistor M17 is connected to the second output clock signal terminal CLKE to receive the second output clock signal.
  • the two poles are connected to the second pixel signal output terminal OT2.
  • the third output transistor M17 when the first node Q is at an operating potential (for example, a high level), the third output transistor M17 is turned on, and the second output clock signal is transmitted to the second pixel signal output terminal OT2 via the third output transistor M17 as the first Three output signals, and the composite output signal also includes a third output signal.
  • an operating potential for example, a high level
  • the clock signals provided by the first output clock signal terminal CLKD and the second output clock signal terminal CLKE are the same. Therefore, the signals output by the first pixel signal output terminal OT1 and the second pixel signal output terminal OT2 are the same.
  • the signals provided by the first output clock signal terminal CLKD and the second output clock signal terminal CLKE are different, so that the second output signal and the second pixel signal output terminal output by the first pixel signal output terminal OT1.
  • the third output signal output by the OT2 is different, so as to provide a plurality of different driving signals for the pixel unit.
  • the first control circuit 500 includes a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7.
  • the gate of the fifth transistor M5 is connected to the first node Q
  • the first pole of the fifth transistor M5 is connected to the second node QB
  • the second pole of the fifth transistor M5 is connected to the second voltage terminal VGL1 to receive the second voltage
  • the gate of the sixth transistor M6 is connected to the first electrode and is configured to be connected to the third voltage terminal VDD_A to receive the third voltage
  • the second electrode of the sixth transistor M6 is connected to the second node QB
  • the gate of the seventh transistor M7 The pole is connected to the first pole and is configured to be connected to the fourth voltage terminal VDD_B to receive the fourth voltage
  • the second pole of the seventh transistor M7 is connected to the second node QB.
  • the third voltage terminal VDD_A is configured to provide a DC low-level signal
  • the fourth voltage terminal VDD_B is configured to provide a DC high-level signal. Therefore, the sixth transistor M6 is always off and the seventh transistor M7 is always off. Always on.
  • the third voltage terminal VDD_A and the fourth voltage terminal VDD_B are configured to alternately provide a DC high-level signal, so that the sixth transistor M6 and the seventh transistor M7 are alternately turned on to prevent the transistor from being turned on for a long time. Performance drift caused by communication.
  • the sixth transistor M6 when the third voltage terminal VDD_A provides a high-level signal and the fourth voltage terminal VDD_B provides a low-level signal, the sixth transistor M6 is turned on and the seventh transistor M7 is turned off; when the fourth voltage terminal VDD_B provides high power When the signal is flat, the third voltage terminal VDD_A provides a low-level signal. At this time, the seventh transistor M7 is turned on and the sixth transistor M6 is turned off.
  • the fifth transistor M5 when the first node Q is at an active level (for example, a high level), the fifth transistor M5 is turned on.
  • the channel width-to-length ratio of the fifth transistor M5 and the channel of the sixth transistor M6 that is turned on.
  • the channel width to length ratio of the fifth transistor M5 is greater than the channel width to length ratio of the sixth transistor M6 and the seventh transistor M7. Any one of the channel width-to-length ratios can thereby pull down the potential of the second node QB to a low level.
  • the fifth transistor M5 When the first node Q is at a low level, the fifth transistor M5 is turned off.
  • the third voltage (high power) that the third voltage terminal VDD_A is increased by the sixth transistor M6 is increased.
  • (Ping) Write to the second node QB to pull up the potential of the second node QB to a high level; if the sixth transistor M6 is turned off and the seventh transistor M7 is turned on, the fourth voltage terminal VDD_B is increased by the seventh transistor M7 The fourth voltage (high level) is written into the second node QB to pull up the potential of the second node QB to a high level.
  • the noise reduction circuit 400 may include a first noise reduction transistor M19, a second noise reduction transistor M14, and a third noise reduction transistor M16.
  • the gate of the first noise reduction transistor M19 is connected to the second node QB
  • the first pole of the first noise reduction transistor M19 is connected to the first node Q
  • the second pole of the first noise reduction transistor M19 is connected to the second voltage terminal VGL1.
  • the gate of the second noise reduction transistor M14 is connected to the second node QB, the first pole of the second noise reduction transistor M14 is connected to the shift signal output terminal CR, and the second of the second noise reduction transistor M14 is The gate is connected to the second voltage terminal VGL1 to receive the second voltage; the gate of the third noise reduction transistor M16 is connected to the second node Q, and the first pole of the third noise reduction transistor M16 is connected to the first pixel signal output terminal OT1, The second pole of the third noise reduction transistor M16 is connected to the fifth voltage terminal VGL2 to receive the fifth voltage.
  • the fifth voltage terminal VGL2 is configured to provide a fifth voltage
  • the fifth voltage is a DC low-level signal (for example, a low level lower than or equal to a clock signal).
  • the fifth voltage terminal VGL2 can be grounded, and the following The embodiments are the same and will not be described again.
  • the fifth voltage provided by the fifth voltage terminal VGL2 is higher than the second voltage provided by the second voltage terminal VGL1, for example, the second voltage is -10V and the fifth voltage is -6V; in another example The fifth voltage of the fifth voltage terminal VGL2 is equal to the second voltage of the second voltage terminal VGL1.
  • the shift register unit 10 may not provide the fifth voltage terminal VGL, and the second pole of the third noise reduction transistor M16
  • the second voltage terminal VGL1 is connected to receive a second voltage.
  • the fifth voltage and the second voltage may be the same or different, which may be determined according to actual needs.
  • the embodiments of the present disclosure are not limited thereto.
  • the first noise reduction transistor M19, the second noise reduction transistor M14, and the third noise reduction transistor M16 are all turned on, and the first node Q and the shift
  • the bit signal output terminal CR is connected to the second voltage terminal VGL1, so that the potential of the first node Q and the potential of the shift signal output terminal CR are pulled down to a low potential by the second voltage of the second voltage terminal VGL1, and the first pixel signal
  • the output terminal OT1 is connected to the fifth voltage terminal VGL2, so that the potential of the first pixel signal output terminal OT1 is pulled down to a low potential by the fifth voltage of the fifth voltage terminal VGL2, thereby reducing the first node Q and the shift signal output Noise at the terminal CR and the first pixel signal output terminal OT1.
  • the noise reduction circuit 400 when the output terminal OP includes a plurality of first pixel signal output terminals OT1 and / or a plurality of shift signal output terminals CR, the noise reduction circuit 400 also includes and A plurality of shift signal output terminals CR and / or a plurality of first pixel signal output terminals OT1 are correspondingly connected to a plurality of transistors, so that a plurality of shift signal output terminals CR and / or a plurality of first pixel signal output terminals OT1 are provided. Perform noise reduction.
  • the noise reduction circuit 400 further includes a fourth noise reduction transistor M18.
  • the gate of the fourth noise reduction transistor M18 is connected to the second node QB, the first pole of the fourth noise reduction transistor M18 is connected to the second pixel signal output terminal OT2, and the second pole of the fourth noise reduction transistor M18 is connected to the fifth voltage.
  • the terminal VGL2 is connected to receive a fifth voltage.
  • the fourth noise reduction transistor M18 is turned on, and the second pixel signal output terminal OT2 is connected to the fifth voltage terminal VGL2, thereby passing through the fifth voltage terminal
  • the fifth voltage of VGL2 pulls down the potential of the second pixel signal output terminal OT2 to a low potential, thereby reducing the noise of the second pixel signal output terminal OT2.
  • the second control circuit 600 includes an eighth transistor M8, the first clock signal terminal CLKA provides a first clock signal, and the first control signal includes a first clock signal. That is, the first clock signal terminal CLKA is equivalent to the aforementioned blanking pull-down control terminal Con1.
  • the gate of the eighth transistor M8 is connected to the first clock signal terminal CLKA to receive the first clock signal
  • the first pole of the eighth transistor M8 is connected to the second node QB
  • the second pole of the eighth transistor M8 is connected to the second voltage terminal.
  • VGL1 is connected to receive the second voltage.
  • the eighth transistor M8 is turned on, the second node QB is connected to the second voltage terminal VGL1, and the second voltage is The second voltage provided by the terminal VGL1 is written into the second node QB, so that the second node QB is pulled down to a low level.
  • the third control circuit 700 includes an eleventh transistor M11.
  • the gate of the eleventh transistor M11 is configured to be connected to the display pull-down control terminal Con2 to receive a second control signal.
  • the first pole of the eleventh transistor M11 is configured to be connected to the second node QB, and the second pole of the eleventh transistor M11 is configured. To connect the second voltage terminal VGL1 to receive the second voltage.
  • the eleventh transistor M11 is turned on, the second node QB is connected to the second voltage terminal VGL1, and the second voltage The second voltage provided by the terminal VGL1 is written into the second node QB, so that the second node QB is pulled down to a low level.
  • the shift signal output CR of the m1-th stage shift register unit 10 and the second shift register unit 10 of the m1 + 2-stage shift register unit 10 The control signal terminal Con2 is connected, and the output signal of the shift signal output terminal CR of the m1-th stage shift register unit 10 is used as the second control signal of the m1 + 2-stage shift register unit 10.
  • m1 is an integer greater than 0.
  • the embodiment of the present disclosure is not limited to this, and the display pull-down control terminal Con2 may also be connected to a signal line provided separately.
  • the blanking reset circuit 800 includes a ninth transistor M9.
  • the gate of the ninth transistor M9 is connected to the blanking reset signal terminal TR to receive the blanking reset signal.
  • the first pole of the ninth transistor M9 is connected to the first node Q.
  • the second pole of the ninth transistor M9 is connected to the second voltage terminal.
  • VGL1 is connected to receive the second voltage.
  • the ninth transistor M9 is turned on, the first node Q is connected to the second voltage terminal VGL1, and the second voltage is The second voltage provided by the terminal VGL1 is written into the first node Q, so that the first node Q is reset.
  • the display reset circuit 900 includes a tenth transistor M10.
  • the gate of the tenth transistor M10 is connected to the display reset signal terminal STD to receive the display reset signal.
  • the first pole of the tenth transistor M10 is connected to the first node Q.
  • the second pole of the tenth transistor M10 is connected to the second voltage terminal VGL1. To receive a second voltage.
  • the tenth transistor M10 is turned on, the first node Q is connected to the second voltage terminal VGL1, and the second voltage terminal VGL1 The provided second voltage is written into the first node Q, so that the first node Q is reset.
  • an active level for example, a high level
  • the shift signal output terminal CR of the m2 + 3-stage shift register unit 10 and the display of the m2-stage shift register unit 10 are reset.
  • the signal terminal STD is connected to use the output signal of the shift signal output terminal CR of the m2 + 3-stage shift register unit 10 as the display reset signal of the m2-stage shift register unit 10.
  • m2 is an integer greater than 0.
  • the embodiments of the present disclosure are not limited to this, and the display reset signal terminal STD may also be connected to a signal line provided separately.
  • the blanking input circuit 100, display input circuit 200, output circuit 300, noise reduction circuit 400, first control circuit 500, and second control circuit The specific implementations of 600, the third control circuit 700, the blanking reset circuit 800, and the display reset circuit 900 are not limited to those described above, and may be any suitable implementation, such as a conventional connection known to those skilled in the art. Way, just need to ensure that the corresponding function can be achieved.
  • the above examples do not limit the scope of protection of the present disclosure. In practical applications, a technician may choose to use or not use one or more of the above circuits according to the situation. Based on various combinations and modifications of the foregoing circuits, the principles of the present disclosure are not deviated, and details are not described herein again.
  • FIG. 7 is another circuit configuration diagram of the shift register unit shown in FIG. 2.
  • the shift register unit 10 of this embodiment is substantially the same as the shift register unit 10 described in FIG. 5A except that it further includes an anti-leakage circuit.
  • the potential of the first node Q can be maintained by the second capacitor C2.
  • some of the transistors in the shift register unit 10 for example, the ninth transistor M9, the tenth transistor M10, and the first noise reduction transistor M19
  • the first pole of is connected to the first node Q, and the second pole of these transistors is connected to the low-level signal line.
  • the shift register unit 10 shown in FIG. 7 adds an anti-leakage circuit to improve the effect of maintaining the potential of the first node Q.
  • the first leakage prevention circuit may include a first leakage prevention transistor M20, a second leakage prevention transistor M9b, a third leakage prevention transistor M10b, and a fourth leakage prevention transistor M19b.
  • the first leakage prevention circuit is configured to prevent the charge at the first node Q from leaking to the second voltage terminal VGL1 via the ninth transistor M9a, the tenth transistor M10a, and the first noise reduction transistor M19a when the first node Q is at a high level. .
  • the gate of the second leakage prevention transistor M9b is connected to the gate of the ninth transistor M9a (that is, the gate of the second leakage prevention transistor M9b is connected to the blanking reset signal terminal TR).
  • the first pole of the leakage prevention transistor M9b is connected to the first node Q
  • the second pole of the second leakage prevention transistor M9b is connected to the first pole of the ninth transistor M9a
  • the second pole of the second leakage prevention transistor M9b is also connected to the first A second pole of an anti-leakage transistor M20.
  • the gate of the first leakage prevention transistor M20 is connected to the first node Q
  • the first electrode of the first leakage prevention transistor M20 is connected to the sixth voltage terminal VDD.
  • the first leakage prevention transistor M20 is turned on under the control of the first node Q, and a sixth voltage (high voltage) is written to the second of the second leakage prevention transistor M9b. So that the first and second electrodes of the second leakage prevention transistor M9b are both in a high-level state to prevent the charge at the first node Q from leaking through the ninth transistor M9a.
  • the gate of the ninth transistor M9a is connected to the gate of the second leakage prevention transistor M9b, the combination of the ninth transistor M9a and the second leakage prevention transistor M9b can achieve the ninth shown in FIGS. 5A to 6C.
  • the transistor M9 has the same function and has the effect of preventing leakage at the same time. Similarly, the principle of leakage prevention using the third leakage prevention transistor M10b and the fourth leakage prevention transistor M19b is similar to the principle of leakage prevention using the second leakage prevention transistor M9b, which will not be repeated here.
  • FIG. 7 only illustrates an exemplary circuit structure including a leakage prevention circuit, and does not constitute a limitation on the embodiment of the present disclosure.
  • the first node Q, the second node QB, the control node H, and the like do not indicate actual components, but rather indicate a meeting point of related connections in the circuit diagram.
  • all the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • the thin film transistors are used as an example for description.
  • the source and drain of the transistor used here can be symmetrical in structure, so there can be no difference in structure of the source and drain of the transistor.
  • one pole is directly described as the first pole and the other pole is the second pole.
  • the transistors in the embodiments of the present disclosure are described by taking N-type transistors as an example.
  • the first electrode of the transistor is a drain
  • the second electrode is a source.
  • the present disclosure includes but is not limited to this.
  • one or more transistors in the shift register unit 10 provided by the embodiment of the present disclosure may also be a P-type transistor.
  • the first pole of the transistor is the source and the second pole is the drain.
  • the poles of a certain type of transistor are connected with reference to the poles of the corresponding transistor in the embodiment of the present disclosure, and the corresponding voltage terminal may provide a corresponding high voltage or low voltage.
  • ITZO Indium Gallium Zinc Oxide
  • LTPS Low Temperature Polysilicon
  • amorphous silicon such as (Crystalline silicon
  • FIG. 8 is a signal timing diagram of a shift register unit provided by some embodiments of the present disclosure.
  • the working principle of the shift register unit 10 shown in FIG. 6A is described below with reference to the signal timing diagram shown in FIG. 8.
  • each transistor is described as an N-type transistor, but the embodiment of the present disclosure is not limited to this. this.
  • 1F indicates the timing of the first frame.
  • DS indicates a display period of one frame
  • BL indicates a blanking period of one frame.
  • STU1, STU2, TR, VDD_A, VDD_B, CLKA, CLKD, CLKE, OT1, OT2, CR, etc. are used to indicate both the corresponding signal end and the corresponding signal. The following embodiments are the same and will not be described again.
  • the blanking reset signal TR and the first clock signal CLKA are at a high level
  • the ninth transistor M9 is turned on
  • the second voltage at the second voltage terminal VGL1 is written into the first node via the ninth transistor M9.
  • the third voltage VDD_A is a low-level signal
  • the fourth voltage VDD_B is a high-level signal.
  • the sixth transistor M6 is turned off
  • the seventh transistor M7 is turned on
  • the fourth voltage VDD_B is written into the first via the seventh transistor M7.
  • the potentials of the two nodes QB and the second node QB are pulled up to a high level, whereby the first noise reduction transistor M19 is turned on, thereby assisting the pull-down of the first node Q, so that the potential of the first node Q is a low level.
  • the third transistor M3 is also turned on, whereby the control node H is also reset.
  • the display input signal terminal STU2 is at a high level
  • the fourth transistor M4 is turned on
  • the control signal for example, the sixth level at the high level provided by the sixth voltage terminal VDD
  • the voltage is written into the first node Q via the fourth transistor M4 and stored by the second capacitor C2.
  • the display reset signal STD (not shown) and the first clock signal CLKA are both low-level signals, and the tenth transistor M10 and the third transistor M3 are both turned off.
  • the first output transistor M13, the second output transistor M15, and the third output transistor M17 are all turned on, and the first output clock signal CLKD is transmitted via the first output transistor M13 and the second output transistor M15. It is output to the shift signal output terminal CR and the first pixel signal output terminal OT1, respectively, and the second output clock signal CLKE is output to the second pixel signal output terminal OT2 via the third output transistor M17.
  • the first output clock signal CLKD and the second output clock signal CLKE are low-level signals, that is, the shift signal output terminal CR, the first pixel signal output terminal OT1, and the second pixel signal output terminal OT2 all output low levels. signal.
  • the fifth transistor M5 is turned on, thereby pulling down the potential of the second node QB to a low level.
  • the first node Q remains at a high level, the first output transistor M13, the second output transistor M15, and the third output transistor M17 remain on, and the first output clock signal CLKD and the second output
  • the clock signal CLKE goes high, so that the shift signal output terminal CR, the first pixel signal output terminal OT1, and the second pixel signal output terminal OT2 all output high-level signals. Due to the bootstrap effect of the second capacitor C2
  • the potential of the first node Q is further pulled up, and the first output transistor M13, the second output transistor M15, and the third output transistor M17 are more fully turned on.
  • the high-level signal output from the shift signal output terminal CR can be used for the scan shift of the upper and lower shift register units.
  • the second compensation control signal terminal OE2 of the shift register unit of the present stage may be connected to the shift signal output terminal CR of the shift register unit of the present stage.
  • the first compensation control signal OE1 is a high-level signal
  • the first transistor M1 is turned on
  • the signal output from the shift signal output terminal CR is also a high-level signal, that is, the second compensation control
  • the signal OE2 is a high-level signal, and thus the second transistor M2 is also turned on.
  • the blanking control signal (for example, a high-level sixth voltage provided by the sixth voltage terminal VDD) passes through the first transistor M1 and the second transistor M2.
  • the first capacitor C1 can store a high-level blanking control signal and keep it until the end of the display period of one frame for use in the blanking period.
  • the first output clock signal CLKD and the second output clock signal CLKE become low level, and both the shift signal output terminal CR and the first pixel signal output terminal OT1 can pass through the first output clock signal terminal.
  • CLKD is discharged, thereby completing the reset of the shift signal output terminal CR and the first pixel signal output terminal OT1;
  • the second pixel signal output terminal OT2 is discharged through the second output clock signal terminal CLKE, thereby completing the reset of the second pixel signal output terminal OT2.
  • the shift signal output terminal CR, the first pixel signal output terminal OT1 and the second pixel signal output terminal OT2 all output low-level signals.
  • the potential of the first node Q is somewhat Lowered but still maintained at a high level, the first output transistor M13, the second output transistor M15, and the third output transistor M17 remain on, and the low level of the first output clock signal terminal CLKD is output to the shift signal output terminals CR and The low level of the first pixel signal output terminal OT1 and the second output clock signal terminal CLKE is output to the second pixel signal output terminal OT2, thereby realizing the reset of the output terminal OP.
  • the display reset signal STD (not shown in the figure) is a high-level signal, and the tenth transistor M10 is turned on, so that the second voltage at the second voltage terminal VGL2 is written into the first node Q To reset the first node Q.
  • the level of the first node Q becomes a low level, so that the fifth transistor M5 is turned off, the third voltage VDD_A is a high-level signal, and the fourth voltage VDD_B is a low-level signal.
  • the sixth transistor M6 is turned off, and the first The seventh transistor M7 is turned on, so that the fourth voltage VDD_B is written to the second node QB via the seventh transistor M7, and the second node QB is pulled up to a high level, so that the first noise reduction transistor M19 is turned on to further One node Q performs noise reduction.
  • the second noise reduction transistor M14, the third noise reduction transistor M16, and the fourth noise reduction transistor M18 are also turned on under the control of the high level of the second node QB, thereby outputting the shift signal output terminal CR and the first pixel signal
  • the terminal OT1 and the second pixel signal output terminal OT2 perform noise reduction.
  • the third transistor M3 is in an off state, thereby isolating the control node H from the first node Q to avoid the control node
  • the level of H affects the output signal of the display period.
  • the level of the first node Q has a tower-like waveform.
  • the pull-up and reset of the output signal of the shift signal output terminal CR are realized by the first output transistor M13.
  • the output of the first pixel signal output terminal OT1 Both the pull-up and reset of the signal are implemented by the second output transistor M15, the pull-up and reset of the output signal of the second pixel signal output terminal OT2 are implemented by the third output transistor M17, and the second noise reduction transistor M14 outputs the shift signal
  • the output signal from the CR terminal assists the pull-down function.
  • the third noise reduction transistor M16 assists the pull-down function of the output signal of the first pixel signal output terminal OT1.
  • the fourth noise reduction transistor M18 outputs the second pixel signal output OT2.
  • the signal acts as an auxiliary pull-down, so the volume of the second noise reduction transistor M14, the third noise reduction transistor M16, and the fourth noise reduction transistor M18 can be reduced, which is beneficial to reducing the area of the circuit layout.
  • the control node H remains high due to the holding effect of the first capacitor C1, and the first clock signal CLKA is a high level signal, and the third transistor M3 Continuity.
  • the blanking control signal charges the first node Q via the third transistor M3 and pulls the first node Q to a high potential.
  • the fifth transistor M5 is turned on under the control of the first node Q, and the second node QB is pulled down to a low level.
  • the first output transistor M13, the second output transistor M15, and the third output transistor M17 are all turned on, and the first output clock signal CLKD passes through the first output transistor M13 and the second output
  • the transistor M15 is output to the shift signal output terminal CR and the first pixel signal output terminal OT1, respectively, and the second output clock signal CLKE is output to the second pixel signal output terminal OT2 via the third output transistor M17.
  • the first output clock signal CLKD and the second output clock signal CLKE are low-level signals, that is, the shift signal output terminal CR, the first pixel signal output terminal OT1, and the second pixel signal output terminal OT2 all output low levels. signal.
  • the first clock signal CLKA becomes a low level
  • the third transistor M3 is turned off, so that the first node Q does not leak electricity through the third transistor M3.
  • the first node Q is kept at a high level
  • the first output transistor M13, the second output transistor M15, and the third output transistor M17 are kept on, and the first output clock signal CLKD becomes high, thereby shifting the signal output terminal Both CR and the first pixel signal output terminal OT1 output high-level signals. Due to the bootstrap effect of the second capacitor C2, the potential of the first node Q is further pulled up.
  • the first output transistor M13, the second output transistor M15, and the first The three-output transistor M17 is more fully turned on.
  • the signal output from the first pixel signal output terminal OT1 may be used to drive a sensing transistor in a sub-pixel unit in a display panel to achieve external compensation. Since the second output clock signal CLKE outputs a pulse signal, the second pixel signal output terminal OT2 also outputs a pulse signal. It should be noted that, in the sixth stage 6, the signal output from the second pixel signal output terminal OT2 may be designed according to practical applications, which is not limited in the present disclosure.
  • the first output clock signal CLKD and the second output clock signal CLKE become low, and both the shift signal output terminal CR and the first pixel signal output terminal OT1 can pass through the first output clock signal terminal.
  • CLKD is discharged, thereby completing the reset of the shift signal output terminal CR and the first pixel signal output terminal OT1;
  • the second pixel signal output terminal OT2 is discharged through the second output clock signal terminal CLKE, thereby completing the reset of the second pixel signal output terminal OT2.
  • the shift signal output terminal CR, the first pixel signal output terminal OT1 and the second pixel signal output terminal OT2 all output low-level signals.
  • the potential of the first node Q is somewhat Lowered but still maintained at a high level, the first output transistor M13, the second output transistor M15, and the third output transistor M17 remain on, and the low level of the first output clock signal terminal CLKD is output to the shift signal output terminals CR and The low level of the first pixel signal output terminal OT1 and the second output clock signal terminal CLKE is output to the second pixel signal output terminal OT2, thereby realizing the reset of the output terminal OP.
  • the blanking reset signal TR and the first clock signal CLKA are high, the ninth transistor M9 is turned on, and the second voltage at the second voltage terminal VGL1 is written into the first via the ninth transistor M9.
  • the third transistor M3 is also turned on, and the second voltage at the second voltage terminal VGL1 is written into the control node H via the ninth transistor M9 and the third transistor M3, thereby controlling the node H is also reset.
  • the control node H can be kept at a high level for a short time, so as to reduce the risk of a threshold voltage drift (for example, a positive drift) of a transistor connected to the control node H, and help improve the reliability of the circuit.
  • a threshold voltage drift for example, a positive drift
  • the shift register unit includes two pixel signal output terminals (that is, the first pixel signal output terminal OT1 and the second pixel signal output The terminal OT2) is taken as an example, but is not limited thereto.
  • the shift register unit may include only one pixel signal output terminal (for example, the first pixel signal output terminal OT1).
  • the working process of the shift register unit is similar to the above-mentioned working process, as long as the relevant description about the second pixel signal output terminal OT2 is omitted, it is not described here. More details.
  • pulse-up means charging a node or an electrode of a transistor such that the node or the electrode The absolute value of the level is increased to achieve the operation of the corresponding transistor (such as turning on);
  • pulse-down means discharging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode Lowered, thereby enabling operation (eg, off) of the corresponding transistor.
  • working potential means that the node is at a high potential, so that when a gate of a transistor is connected to the node, the transistor is turned on; the term “non-working potential” means that the node is at a low potential, so that when the gate of a transistor is When connected to this node, the transistor is turned off.
  • pulse-up means discharging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode is reduced, thereby realizing the corresponding transistor.
  • Operation means charging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode increases, thereby realizing the operation of the corresponding transistor (such as turning off) .
  • working potential means that the node is at a low potential, so that when a gate of a transistor is connected to the node, the transistor is turned on; the term “non-working potential” means that the node is at a high potential, so that when the gate of a transistor is When connected to this node, the transistor is turned off.
  • At least some embodiments of the present disclosure also provide a gate driving circuit.
  • the gate driving circuit includes a shift register unit according to any embodiment of the present disclosure.
  • the gate driving circuit has a simple circuit structure, can realize random compensation, avoids the brightness deviation of the scanning lines and the panel caused by the progressive compensation, improves the display uniformity and the display effect.
  • FIG. 9 is a schematic block diagram of a gate driving circuit provided by some embodiments of the present disclosure
  • FIG. 10A is a circuit structure diagram of a blanking input circuit and a display input circuit provided by some embodiments of the present disclosure
  • FIG. 10B is A circuit structure diagram of another blanking input circuit and a display input circuit provided by some embodiments is disclosed
  • FIG. 10C is a circuit structure diagram of a blanking input circuit and a display input circuit provided by some embodiments of the present disclosure
  • FIG. 10D Circuit structure diagrams of another blanking input circuit and display input circuit provided by some embodiments of the present disclosure
  • FIG. 10E is a circuit structure of another blanking input circuit and display input circuit provided by some embodiments of the present disclosure; Illustration.
  • the gate driving circuit 20 includes a plurality of cascaded shift register units (for example, A1, A2, A3, A4, etc.).
  • the number of multiple shift register units is not limited and can be determined according to actual needs.
  • the shift register unit adopts the shift register unit 10 according to any embodiment of the present disclosure.
  • a part or all of the shift register units may adopt the shift register unit 10 described in any embodiment of the present disclosure.
  • the gate driving circuit 20 can be directly integrated on the array substrate of the display device by using the same process as the thin film transistor, so as to realize the progressive scanning driving function.
  • the first pixel signal output terminals OT1 of these shift register units are connected to the first gate lines (for example, G11, G21, G31, G41, etc.) in a one-to-one correspondence; the second pixel signal output terminals of these shift register units OT2 is connected one-to-one with a plurality of second gate lines (for example, G12, G22, G32, G42, etc.).
  • each shift register unit includes a display input signal terminal STU2, a first clock signal terminal CLKA (ie, a blanking input signal terminal STU1), a first compensation control signal terminal OE1, a second compensation control signal terminal OE2, and a first output.
  • the gate driving circuit 20 further includes a first sub-clock signal line CLK_1, a second sub-clock signal line CLK_2, a third sub-clock signal line CLK_3, and a fourth sub-clock signal line CLK_4.
  • the connection modes of the shift register units of each stage and the above-mentioned sub-clock signal lines are as follows and so on.
  • the first output clock signal terminal CLKD of the 4n 1 -3 stage shift register unit (for example, the first stage shift register unit A1) is connected to the first sub-clock signal line CLK_1; the 4n 1-2-stage shift register unit (e.g., the second-stage shift register unit A2), the first clock signal output terminal and the second sub-clock CLKD signal line connected CLK_2; 4n 1 -1 first-stage shift register unit (e.g.
  • n 1 is an integer greater than 0.
  • the gate driving circuit 20 further includes a fifth sub-clock signal line CLK_5, a sixth sub-clock signal line CLK_6, a seventh sub-clock signal line CLK_7, and an eighth sub-clock signal line CLK_8.
  • the connection modes of the shift register units of each stage and the above-mentioned sub-clock signal lines are as follows and so on.
  • the first-stage shift register unit 4n 1 -3 e.g., the first-stage shift register unit A1
  • the 4n 1-2-stage shift register unit e.g., the second-stage shift register unit A2
  • the sixth sub-clock signal CLKE CLK_6 line connection 4n 1 -1 first-stage shift register unit (e.g.
  • the third-stage shift register unit A3) a second clock signal output terminal and the seventh sub-clock signal CLKE CLK_7 line connection; 4n 1 of the first-stage shift register unit (e.g., the fourth-stage shift register unit A4),
  • the two-output clock signal terminal CLKE is connected to the eighth sub-clock signal line CLK_8.
  • the gate driving circuit 20 further includes a blanking input clock signal line CLK_9, and the blanking input clock signal line CLK_9 is configured to communicate with the shift register unit of each stage (for example, the first stage shift register unit).
  • A1 the second-stage shift register unit A2, the third-stage shift register unit A3, and the fourth-stage shift register unit A4) are connected to a first clock signal terminal CLKA (that is, a blanking input signal terminal STU1).
  • the blanking input signal terminal STU1 of each stage of the shift register unit is connected to the first clock signal terminal CLKA, that is, the first clock signal terminal CLKA is equivalent to each The blanking input signal terminal STU1 of the stage shift register unit.
  • the display reset signal terminal STD of the n-th stage of the second -stage shift register unit 10 (for example, the first-stage shift register unit A1) and the n 2 + 3-stage shift register unit 10 ( For example, the shift signal output terminal CR of the fourth-stage shift register unit A4) is connected.
  • the display reset signal terminal STD of the first stage shift register unit A1 is connected to the shift signal output terminal CR of the fourth stage shift register unit A4.
  • the display reset signal terminal STD of the second-stage shift register unit A2, the display reset signal terminal STD of the third-stage shift register unit A3, and the display reset signal terminal STD of the fourth-stage shift register unit A4 can be respectively associated with multiple Set the reset signal line connection separately.
  • n 2 stage shift register unit e.g., the first-stage shift register unit A1
  • n 2 is an integer greater than 0.
  • the display input signal terminal STU2 of the first-stage shift register unit A1 and the display input signal terminal STU2 of the second-stage shift register unit A2 are both connected to the input signal line STU, for example, to receive the trigger signal STV.
  • the first compensation control signal terminal OE1 of each stage of the shift register unit receives an external random signal
  • the n 2 +2 stage shift register unit for example, the first stage shift register unit
  • the second compensation control signal terminal OE2 of A1 is connected to the shift signal output terminal CR of the n 2 +2 stage shift register unit (for example, the first stage shift register unit A1), that is, the n 2 stage shift register unit
  • the signal output from the shift signal output terminal is used as a second compensation control signal of the n 2 +2 stage shift register unit.
  • n 2 stage shift register unit e.g., the first-stage shift register unit A1 is connected to the shift signal output terminal CR, n 2 is an integer greater than 0.
  • the first compensation control signal terminal OE1 of each stage of the shift register unit receives an external random signal, except for the first stage of the shift register unit A1 and the second stage of the shift register unit A2.
  • the second compensation control signal terminal OE2 of the n 2 +2 stage shift register unit (for example, the third stage shift register unit A3) is connected to the n 2 stage shift register unit (for example, the first stage shift register)
  • the shift signal output terminal CR of the unit A1) that is, the signal output from the shift signal output terminal of the nth 2 -stage shift register unit is used as the second compensation control signal of the n 2 + 2-stage shift register unit.
  • the shift signal output terminal CR is connected, and n 2 is an integer greater than 0.
  • the first compensation control signal terminal OE1 of each stage of the shift register unit receives an external random signal, except for the last three stages of the shift register unit, the n 2 +3 stage shifts second compensation bit register unit (e.g., the fourth-stage shift register unit A4) of the CR shift signal output terminal connected to the n-stage shift register unit (e.g., the first-stage shift register unit A1) is a control signal terminal OE2, that is, the signal output from the shift signal output terminal of the n 2 +3 stage shift register unit is used as the second compensation control signal of the n 2 stage shift register unit.
  • the shift signal output terminal CR is connected, and n 2 is an integer greater than 0.
  • the second compensation control signal terminal OE2 of each stage of the shift register unit receives an external random signal, except for the first stage of the shift register unit A1 and the second stage of the shift register unit A2.
  • the first compensation control signal terminal OE1 of the n 2 +2 stage shift register unit (for example, the third stage shift register unit A3) is connected to the n 2 stage shift register unit (for example, the first stage shift register
  • the shift signal output terminal CR of the unit A1) that is, the signal output from the shift signal output terminal of the nth 2nd stage shift register unit is used as the first compensation control signal of the n 2 + 2th stage shift register unit.
  • the shift signal output terminal CR is connected, and n 2 is an integer greater than 0.
  • the n-stage shift register unit e.g., a first shift register stage 10E
  • the shift signal output terminal CR of the unit A1 is connected to the second compensation control signal terminal OE2 of the n 2 +2 stage shift register unit (for example, the third stage shift register unit A3), that is, the n 2 stage shift register A signal output from the shift signal output terminal of the unit is used as a second compensation control signal of the n 2 +2 stage shift register unit.
  • An n-stage shift register unit (e.g., the first-stage shift register unit A1) is connected to the shift signal output terminal CR 2 +2 n-stage shift register unit (e.g., the third-stage shift register unit A3)
  • the blanking control signal terminal BP and the display control signal terminal DP that is, the signal output from the shift signal output terminal of the nth stage 2 shift register unit are also used as the blanking control signal of the n 2 +2 stage shift register unit and Control signals are displayed.
  • n-stage shift register unit e.g., the third-stage shift register unit A3 a display signal input terminal STU2 and further n-th stage second shift register unit (e.g., the first-stage shift register unit A1)
  • the shift signal output terminal CR is connected, and n 2 is an integer greater than 0.
  • each shift register cell in FIG. 10E may further include a second leakage prevention circuit, and the second leakage prevention circuit may include a fifth leakage prevention transistor M4b and a sixth leakage prevention transistor M21.
  • the second leakage prevention circuit is configured to prevent the charge at the first node Q from leaking through the fourth transistor M4a when the first node Q is at a high level.
  • Gate of the fifth transistor leakage power is connected to the fourth transistor M4b M4a (i.e., the gate of the fifth transistor is electrically leakproof n 2 +2 M4b stage shift register unit is connected to the n 2 second-stage shift register The shift signal output terminal CR of the unit), the first pole of the fifth leakage prevention transistor M4b is connected to the second pole of the fourth transistor M4a, and the second pole of the fifth leakage prevention transistor M4b is connected to the first node Q.
  • the gate of the sixth leakage prevention transistor M21 is connected to the first node Q, the first pole of the sixth leakage prevention transistor M21 is connected to the sixth voltage terminal VDD, and the second pole of the sixth leakage prevention transistor M21 is connected to the fifth leakage prevention.
  • the first pole of the transistor M4b is Similarly, the principle of preventing leakage by using the second leakage preventing circuit is similar to the principle of preventing leakage by using the first leakage preventing circuit, and details are not described herein again.
  • the gate driving circuit 20 may further include a timing controller T-CON, for example, the timing controller T-CON is configured to provide the above-mentioned various clock signals to the shift register units at various levels, and the timing controller T-CON may also be configured to Provide trigger signal and reset signal. It should be noted that the phase relationship between the multiple clock signals provided by the timing controller T-CON can be determined according to actual needs. In different examples, more clock signals can be provided depending on the configuration.
  • the gate driving circuit 20 further includes a plurality of voltage lines to provide a plurality of voltage signals to the shift register units of each stage.
  • the gate driving circuit 20 when used to drive a display panel, the gate driving circuit 20 may be disposed on one side of the display panel.
  • the gate driving circuit 20 can also be provided on both sides of the display panel to achieve bilateral driving.
  • the embodiment of the present disclosure does not limit the manner of setting the gate driving circuit 20.
  • a gate driving circuit 20 may be provided on one side of the display panel for driving odd-numbered rows of gate lines, and a gate driving circuit 20 may be provided on the other side of the display panel for driving even-numbered rows of gate lines.
  • FIG. 11 is a signal timing diagram of a gate driving circuit provided by some embodiments of the present disclosure.
  • the signal timing diagram is the timing of the gate driving circuit 20 shown in FIG. 9 and the shift in the gate driving circuit 20 is shown in FIG.
  • the register unit is the shift register unit 10 shown in FIG. 6A.
  • Q ⁇ 5> and Q ⁇ 6> represent the first node Q in the fifth-stage and sixth-stage shift register units in the gate driving circuit 20, respectively.
  • OT1 ⁇ 5> and OT2 ⁇ 5> indicate the first pixel signal output terminal OT1 and the second pixel signal output terminal OT2, OT1 ⁇ 6>, and OT2 ⁇ 6 in the fifth-stage shift register unit in the gate driving circuit 20, respectively.
  • > Represents the first pixel signal output terminal OT1 and the second pixel signal output terminal OT2 in the sixth-stage shift register unit in the gate driving circuit 20, respectively.
  • MF represents the Mth frame, and M is a positive integer.
  • the shift register unit 10 outputs the scanning driving signals to the multiple rows of gate lines line by line, until one frame of display is completed after the scanning driving signals are output to the gate lines of the last line.
  • the n-th row of the sub-pixel units needs to be detected and compensated.
  • the n-th row of the sub-pixel units are connected to the output of the n-th stage shift register unit 10, so that during the blanking period BL, the n-th stage shifts
  • the first pixel signal output terminal OT1 of the bit register unit 10 outputs a high-level signal to detect the n-th row of the sub-pixel units.
  • the fifth row of sub-pixel units corresponds to the fifth-stage shift register unit.
  • the external control circuit outputs the signal output from the shift signal output terminal CR of the fifth-stage shift register unit to the first compensation control signal terminal OE1 of each stage of the shift register unit, that is, the external control circuit provides
  • the first compensation control signal has the same waveform pulse width as the signal output from the shift signal output terminal CR of the fifth-stage shift register unit. Because the example shown in FIG. 9 and FIG.
  • the n 2 second-stage shift register unit compensation control signal OE2 connected to the shift signal output terminal of the CR n 2 stage shift register unit, whereby, in In the second stage of the display period DS, when the shift signal output terminal CR of the fifth-stage shift register unit outputs a high-level signal, as shown in FIG. 6A, the Both the first transistor M1 and the second transistor M2 are turned on, and therefore, the sixth voltage provided by the sixth voltage terminal VDD is written into the control node H of the fifth-stage shift register unit to write the fifth-stage shift register unit. The control node H is pulled high to a high level.
  • the waveforms of the first sub-clock signal CLK_1, the second sub-clock signal CLK_2, the third sub-clock signal CLK_3, and the fourth sub-clock signal CLK_4 in the display period of one frame sequentially overlap the effective pulse width.
  • the output signals OT1 ⁇ 1>, OT1 ⁇ 2>, OT1 ⁇ 3>, and OT1 ⁇ 4> of the first pixel signal output terminal OT1 of the first to fourth stage shift register units A1-A4 in one frame The waveforms in the display period sequentially overlap by 50% of the effective pulse width.
  • the waveforms of the fifth sub-clock signal line CLK_5, the sixth sub-clock signal line CLK_6, the seventh sub-clock signal line CLK_7, and the eighth sub-clock signal line CLK_8 in the display period of one frame also sequentially overlap by 50% of the effective pulse width.
  • the output signals OT2 ⁇ 1>, OT2 ⁇ 2>, OT2 ⁇ 3>, and OT2 ⁇ 4> of the second pixel signal output terminal OT2 of the first to fourth stage shift register units A1-A4 are within the display period of one frame
  • the waveforms in turn also overlap by 50% of the effective pulse width.
  • the waveform of the output signal of the gate driving circuit 20 during the display period overlaps, so the pre-charging function can be implemented, the charging efficiency can be improved, and the overall charging time of the pixel circuit (that is, the time of the display period in one frame) can be reduced. Conducive to achieving a high refresh rate. At this time, the pixels on the odd-numbered rows and the pixels on the even-numbered rows on the display panel can be connected to different data lines, so that when two adjacent pixel units are charged at the same time, the adjacent two pixel units can receive the corresponding Data signal.
  • the gate driving circuit 20 is not limited to the cascade manner described in FIG. 9, and may be any applicable cascade manner.
  • the output signals OT1 ⁇ 1>, OT1 ⁇ 2>, OT1 ⁇ 3>, and OT1 of the first pixel signal output terminal OT1 of the first to fourth stage shift register units A1-A4 ⁇ 4> During the display period, the waveform overlap will also change accordingly.
  • the output signals OT2 ⁇ 1>, OT2 ⁇ 2>, OT2, OT2 ⁇ 3> and OT2 ⁇ 4> also have corresponding waveform overlap changes during the display period, such as 33% or 0% overlap (that is, non-overlap) to meet the requirements of various applications.
  • the waveform of the signal output from the first pixel signal output terminal OT1 of the fifth-stage shift register unit and the waveform of the signal output from the first pixel signal output terminal OT1 of the sixth-stage shift register unit There is overlap, therefore, in the second stage 2, in the process of charging the control node H of the fifth stage shift register unit, when the shift signal output terminal CR of the sixth stage shift register unit outputs a high level
  • the first transistor M1 and the second transistor M2 in the charging sub-circuit 110 of the sixth-stage shift register unit are also turned on. Therefore, the sixth voltage provided by the sixth voltage terminal VDD is written into the sixth stage.
  • the control node H of the shift register unit is configured to pull the control node H of the sixth-stage shift register unit to a high level.
  • the first compensation control signal is at a low level, the potentials of the control node H of the fifth-stage shift register unit and the control node H of the sixth-stage shift register unit can be maintained until the blanking period BL.
  • the first clock signal CLKA is a high-level signal, so that the third transistors M3 of all the shift register units are turned on.
  • the control node H of the stage shift register unit and the control node H of the sixth stage shift register unit are both high-level, and thus, the first node Q and the sixth stage shift register unit of the fifth stage shift register unit The first node Q is charged to a high level.
  • the first sub-clock signal CLK_1 (for providing the first output clock signal line CLKD) connected to the fifth-stage shift register unit provides a high-level signal
  • the fifth stage The fifth sub-clock signal line CLK_5 (for providing the second output clock signal CLKE) connected to the shift register unit provides a pulse signal, whereby the first pixel signal output terminal OT1 of the fifth-stage shift register unit outputs a high level.
  • the second pixel signal output terminal OT2 of the fifth-stage shift register unit outputs a pulse signal. Therefore, in the M-th frame period, detection of the fifth row of sub-pixel units can be implemented.
  • the second sub-clock signal line CLK_2 (for providing the first output clock signal CLKD) connected to the sixth-stage shift register unit provides a low-level signal
  • the sixth sub-clock signal connected to the sixth-stage shift register unit
  • the line CLK_6 (for providing the second output clock signal CLKE) also provides a low-level signal, whereby the first pixel signal output terminal OT1 and the second pixel signal output terminal OT2 of the sixth-stage shift register unit both output low levels. signal. Therefore, during the M-th frame period, the sub-pixel units in the sixth row (which correspond to the sixth-stage shift register unit) will not be detected.
  • the first compensation control signal of each stage of the shift register unit It can be changed according to the second compensation control signal of the W-th stage shift register unit to ensure that when the second transistor M2 of the W-th stage shift register unit is turned on, the first transistor M1 of the W-th stage shift register unit is also simultaneously Continuity.
  • W is a positive integer.
  • the external control circuit outputs a signal output from the shift signal output terminal CR of the eighth stage shift register unit to the first compensation control signal terminal OE1 of the shift register unit of each stage.
  • FIG. 12 is a schematic block diagram of a display device provided by some embodiments of the present disclosure.
  • the display device 30 includes a gate driving circuit 20 including the gate driving circuit according to any embodiment of the present disclosure.
  • the display device 30 in this embodiment may be: a liquid crystal panel, a liquid crystal television, a display, an OLED panel, an OLED television, an OLED display, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, etc. Products or parts with display capabilities.
  • the display device 30 includes a display panel 3000, a gate driver 3010, a timing controller 3020, and a data driver 3030.
  • the display panel 3000 includes a plurality of pixel units P, and the plurality of pixel units P are defined by a plurality of gate lines GL and a plurality of data lines DL crossing.
  • the gate driver 3010 is used to drive a plurality of gate lines GL;
  • the data driver 3030 is used to drive a plurality of data lines DL;
  • the timing controller 3020 is used to process image data RGB input from the outside of the display device 30, and provide the processed data to the data driver 3030.
  • the image data RGB and the scan control signal GCS and the data control signal DCS are output to the gate driver 3010 and the data driver 3030 to control the gate driver 3010 and the data driver 3030.
  • the gate driver 3010 includes the gate driving circuit 20 provided in any of the above embodiments.
  • the first pixel signal output terminals OT1 of the plurality of shift register units 10 in the gate driving circuit 20 are correspondingly connected to the plurality of gate lines GL.
  • the first pixel signal output terminals OT1 of the shift register units 10 in each level of the gate driving circuit 20 sequentially output scan driving signals to the plurality of gate lines GL, so that the rows of pixel units P in the display panel 3000 are in the display period. Realize progressive scanning and random compensation detection during blanking period.
  • the gate driver 3010 may be implemented as a semiconductor chip, or may be integrated in the display panel 3000 to constitute a GOA circuit.
  • the data driver 3030 provides the converted data signals to the plurality of data lines DL.
  • the data driver 3030 may be implemented as a semiconductor chip.
  • the timing controller 3020 processes the externally input image data RGB to match the size and resolution of the display panel 3000, and then provides the processed image data to the data driver 3030.
  • the timing controller 3020 generates a plurality of scan control signals GCS and a plurality of data control signals DCS using synchronization signals (such as the dot clock DCLK, the data enable signal DE, the horizontal synchronization signal Hsync, and the vertical synchronization signal Vsync) input from the outside of the display device 30. .
  • the timing controller 3020 provides the scan control signal GCS and the data control signal DCS to the gate driver 3010 and the data driver 3030, respectively, for controlling the gate driver 3010 and the data driver 3030.
  • the display device 30 may further include other components, such as a signal decoding circuit, a voltage conversion circuit, and the like. These components may use existing conventional components, for example, and are not described in detail here.
  • At least some embodiments of the present disclosure also provide a method for driving a shift register unit, which can be used to drive a shift register unit provided by any embodiment of the present disclosure.
  • FIG. 13 is a flowchart of a method for driving a shift register unit provided by some embodiments of the present disclosure.
  • the driving method may include a display period and a blanking period for one frame. As shown in FIG. 13, the driving method may include the following operations:
  • Display period in one frame including:
  • the blanking period in one frame includes:
  • step S10 further includes: controlling the level of the second node through the third control circuit in response to the second control signal, so as to Pull down the level of the second node to a non-working potential.
  • the output terminal includes a shift signal output terminal and a first pixel signal output terminal
  • the output circuit includes a first output transistor and a second output transistor.
  • Step S11 may include: under the control of the level of the first node, transmitting a display shift signal to a shift signal output terminal via a first output transistor, and transmitting a display output signal to a first pixel signal output via a second output transistor end.
  • the composite output signal includes a display output signal and a display shift signal.
  • the display output signal can be used to drive a sub-pixel unit in a display panel for display.
  • step S11 and step S12 are not sequential, and step S12 may be performed before step S11; step S12 may be performed after step S11; step S12 and step S11 may be performed simultaneously.
  • step S20 further includes: controlling the level of the second node through the second control circuit in response to the first control signal, To pull down the level of the second node to a non-working potential.
  • step S21 may include: under the control of the level of the first node, transmitting the blanking shift signal to the shift signal output terminal via the first output transistor, and blanking the blank signal via the second output transistor.
  • the output signal is transmitted to the first pixel signal output terminal.
  • the composite output signal includes a blanking output signal and a blanking shift signal.
  • the blanking output signal can be used to drive a sub-pixel unit in a display panel for external compensation.
  • the first output signal may include a display shift signal and a blanking shift signal
  • the second output signal includes a display output signal and a blanking output signal.
  • the display output signal may be a signal output by the first pixel signal output terminal during the display period
  • the display shift signal may be a signal output by the shift signal output terminal during the display period.
  • the display shift signal and the display The output signals can be the same.
  • the display output signal can be a pulse signal, for example.
  • the blanking output signal can be a signal output by the first pixel signal output terminal during the blanking period.
  • the blanking shift signal can be a shift signal during the blanking period.
  • the signal output from the output end may be the same as the blanking shift signal and the blanking output signal, and the blanking output signal may be a high-level signal, for example.
  • the driving method may further include: a display reset phase, resetting the first node under the control of the display reset signal; and under the control of the level of the second node, through noise reduction
  • the circuit performs noise reduction on the first node, the shift signal output terminal, the first pixel signal output terminal and the second pixel signal output terminal.
  • the driving method may further include: a blanking reset phase, resetting the first node and the control node under the control of the blanking reset signal and the blanking input signal.

Abstract

公开了一种移位寄存器单元及其驱动方法、栅极驱动电路、显示装置。该移位寄存器单元(10)包括:消隐输入电路(100)、显示输入电路(200)、输出电路(300)、控制节点(H)和第一节点(Q);消隐输入电路(100)被配置为响应于消隐输入信号在消隐时段将消隐上拉信号输入到第一节点(Q),并且,消隐输入电路(100)包括充电子电路(110),充电子电路(110)被配置为响应于第一补偿控制信号和第二补偿控制信号,将消隐上拉信号输入到控制节点(H);显示输入电路(200)被配置为响应于显示输入信号在显示时段将显示上拉信号输入到第一节点(Q);输出电路(300)被配置为在第一节点(Q)的电平的控制下,将复合输出信号输出至输出端(OP)。

Description

移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
本申请要求于2018年07月25日递交的中国专利申请第201810828750.6号的优先权,在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种移位寄存器单元及其驱动方法、栅极驱动电路、显示装置。
背景技术
在显示技术领域,显示面板,例如液晶显示面板(Liquid crystal display,LCD)或有机发光二极管(Organic Light Emitting Diode,OLED)显示面板,包括多条栅线。对栅线的驱动可以通过栅极驱动电路实现。栅极驱动电路通常集成在栅极驱动芯片(Gate IC)中。随着显示技术的飞速发展,显示面板越来越向着高集成度和低成本的方向发展。而在驱动芯片的设计中,芯片的面积是影响芯片成本的主要因素,如何有效地减小芯片面积是技术开发人员需要着重考虑的问题。
发明内容
本公开至少一些实施例提供一种移位寄存器单元,包括:消隐输入电路、显示输入电路、输出电路、控制节点和第一节点;所述消隐输入电路被配置为响应于消隐输入信号在消隐时段将消隐控制信号输入到所述第一节点,所述消隐输入电路包括充电子电路,所述充电子电路被配置为响应于第一补偿控制信号和第二补偿控制信号,将所述消隐控制信号输入到所述控制节点;所述显示输入电路被配置为响应于显示输入信号在显示时段将显示控制信号输入到所述第一节点;所述输出电路被配置为在所述第一节点的电平的控制下,将复合输出信号输出至输出端。
例如,在本公开至少一些实施例提供的移位寄存器单元中,所述第一补偿控制信号和所述第二补偿控制信号其中之一为随机信号。
例如,在本公开至少一些实施例提供的移位寄存器单元中,所述充电子电 路包括第一晶体管和第二晶体管,所述第一晶体管的栅极被配置为接收所述第一补偿控制信号,所述第一晶体管的第一极被配置为与消隐控制信号端连接以接收所述消隐控制信号,所述第一晶体管的第二极被配置为与所述第二晶体管的第一极连接,所述第二晶体管的第二极被配置为与所述控制节点连接,所述第二晶体管的栅极被配置为接收所述第二补偿控制信号。
例如,在本公开至少一些实施例提供的移位寄存器单元中,所述消隐输入电路还包括:存储子电路,被配置为存储所述充电子电路输入的所述消隐控制信号;隔离子电路,被配置为在所述消隐输入信号的控制下,将所述消隐控制信号输入到所述第一节点。
例如,在本公开至少一些实施例提供的移位寄存器单元中,所述存储子电路包括第一电容,所述第一电容的第一极被配置为和所述控制节点连接,所述第一电容的第二极被配置为与第一电压端连接以接收第一电压;所述隔离子电路包括第三晶体管,所述第三晶体管的栅极被配置为与消隐输入信号端连接以接收所述消隐输入信号,所述第三晶体管的第一极被配置为与所述控制节点连接,所述第三晶体管的第二极被配置为与所述第一节点连接。
例如,在本公开至少一些实施例提供的移位寄存器单元中,所述显示输入电路包括第四晶体管,所述第四晶体管的栅极与显示输入信号端连接以接收所述显示输入信号,所述第四晶体管的第一极与显示控制信号端连接以接收所述显示控制信号,所述第四晶体管的第二极与所述第一节点连接。
例如,在本公开至少一些实施例提供的移位寄存器单元中,所述输出端包括移位信号输出端和第一像素信号输出端,所述输出电路包括第一输出晶体管、第二输出晶体管和第二电容;所述第一输出晶体管的栅极与所述第一节点连接,所述第一输出晶体管的第一极与第一输出时钟信号端连接以接收第一输出时钟信号,所述第一输出晶体管的第二极与所述移位信号输出端连接;所述第二输出晶体管的栅极和所述第一节点连接,所述第二输出晶体管的第一极与所述第一输出时钟信号端连接以接收所述第一输出时钟信号,所述第二输出晶体管的第二极与所述第一像素信号输出端连接;所述第二电容的第一极和所述第一节点连接,所述第二电容的第二极与所述第一输出晶体管的第二极连接;所述第一输出时钟信号经由所述第一输出晶体管传输至所述移位信号输出端以作为第一输出信号,所述第一输出时钟信号经由所述第二输出晶体管传输至所述第一像素信号输出端以作为第二输出信号,所述复合输出信号包括所述第一输 出信号和所述第二输出信号。
例如,在本公开至少一些实施例提供的移位寄存器单元中,所述输出端还包括第二像素信号输出端,所述输出电路还包括第三输出晶体管,所述第三输出晶体管的栅极与所述第一节点连接,所述第三输出晶体管的第一极与第二输出时钟信号端连接以接收第二输出时钟信号,所述第三输出晶体管的第二极与所述第二像素信号输出端连接,所述第二输出时钟信号经由所述第三输出晶体管传输至所述第二像素信号输出端以作为第三输出信号,所述复合输出信号还包括所述第三输出信号。
例如,在本公开至少一些实施例提供的移位寄存器单元中,所述消隐控制信号和所述显示控制信号相同。
例如,本公开至少一些实施例提供的移位寄存器单元还包括:降噪电路、第一控制电路和第二节点,所述降噪电路被配置为在所述第二节点的电平的控制下,对所述第一节点和所述输出端进行降噪;所述第一控制电路配置为在所述第一节点的电平的控制下,对所述第二节点的电平进行控制。
例如,在本公开至少一些实施例提供的移位寄存器单元中,所述第一控制电路包括第五晶体管、第六晶体管和第七晶体管;所述第五晶体管的栅极与所述第一节点连接,所述第五晶体管的第一极与所述第二节点连接,所述第五晶体管的第二极与第二电压端连接以接收第二电压;所述第六晶体管的栅极和第一极连接且被配置为与第三电压端连接以接收第三电压,所述第六晶体管的第二极与所述第二节点连接;所述第七晶体管的栅极与第一极连接且被配置为与第四电压端连接以接收第四电压,所述第七晶体管的第二极与所述第二节点连接。
例如,在本公开至少一些实施例提供的移位寄存器单元中,所述输出端包括移位信号输出端和第一像素信号输出端,所述降噪电路包括第一降噪晶体管、第二降噪晶体管和第三降噪晶体管;所述第一降噪晶体管的栅极与所述第二节点连接,所述第一降噪晶体管的第一极与所述第一节点连接,所述第一降噪晶体管的第二极与第二电压端连接以接收第二电压;所述第二降噪晶体管的栅极与所述第二节点连接,所述第二降噪晶体管的第一极与所述移位信号输出端连接,所述第二降噪晶体管的第二极与所述第二电压端连接以接收所述第二电压;所述第三降噪晶体管的栅极与所述第二节点连接,所述第三降噪晶体管的第一极与所述第一像素信号输出端连接,所述第三降噪晶体管的第二极与第五电压 端连接以接收第五电压。
例如,在本公开至少一些实施例提供的移位寄存器单元中,所述输出端还包括第二像素信号输出端,所述降噪电路还包括第四降噪晶体管;
所述第四降噪晶体管的栅极与所述第二节点连接,所述第四降噪晶体管的第一极与所述第二像素信号输出端连接,所述第四降噪晶体管的第二极与所述第五电压端连接以接收所述第五电压。
例如,本公开至少一些实施例提供的移位寄存器单元还包括第二控制电路;所述第二控制电路被配置为响应于第一控制信号对所述第二节点的电平进行控制。
例如,本公开至少一些实施例提供的移位寄存器单元还包括消隐复位电路和显示复位电路,所述消隐复位电路被配置为响应于消隐复位信号对所述第一节点进行复位,所述显示复位电路被配置为响应于显示复位信号对所述第一节点进行复位。
本公开至少一些实施例还提供一种栅极驱动电路,包括多个级联的如上述任一所述的移位寄存器单元。
例如,本公开至少一些实施例提供的栅极驱动电路还包括第一子时钟信号线、第二子时钟信号线、第三子时钟信号线和第四子时钟信号线;在所述移位寄存器单元包括第一输出时钟信号端的情形下,第4n 1-3级移位寄存器单元的第一输出时钟信号端与所述第一子时钟信号线连接;第4n 1-2级移位寄存器单元的第一输出时钟信号端与所述第二子时钟信号线连接;第4n 1-1级移位寄存器单元的第一输出时钟信号端与所述第三子时钟信号线连接;第4n 1级移位寄存器单元的第一输出时钟信号端与所述第四子时钟信号线连接;n 1为大于0的整数。
例如,在本公开至少一些实施例提供的栅极驱动电路中,在所述移位寄存器单元包括显示输入信号端和移位信号输出端的情形下,第n 2+2级移位寄存器单元的显示输入信号端和第n 2级移位寄存器单元的移位信号输出端连接,n 2为大于0的整数。
例如,在本公开至少一些实施例提供的栅极驱动电路中,所述第n 2级移位寄存器单元的移位信号输出端输出的信号作为所述第n 2+2级移位寄存器单元的第二补偿控制信号;或者所述第n 2+3级移位寄存器单元的移位信号输出端输出的信号作为所述第n 2级移位寄存器单元的第二补偿控制信号;或者所述第 n 2级移位寄存器单元的移位信号输出端输出的信号作为所述第n 2级移位寄存器单元的第二补偿控制信号;或者所述第n 2级移位寄存器单元的移位信号输出端输出的信号作为所述第n 2+2级移位寄存器单元的第二补偿控制信号,所述第n 2级移位寄存器单元的移位信号输出端输出的信号还作为所述第n 2+2级移位寄存器单元的消隐控制信号。
例如,本公开至少一些实施例提供的栅极驱动电路还包括第五子时钟信号线;在所述移位寄存器单元包括消隐输入信号端的情形下,每级移位寄存器单元的消隐输入信号端与所述第五子时钟信号线连接。
本公开至少一些实施例还提供一种显示装置,包括如上述任一项所述的栅极驱动电路。
本公开至少一些实施例还提供一种如上述任一所述的移位寄存器单元的驱动方法,包括用于一帧的显示时段和消隐时段:所述显示时段,包括:第一输入阶段,响应于所述显示输入信号,通过所述显示输入电路将所述显示控制信号输入到所述第一节点;第一输出阶段,在所述第一节点的电平的控制下,通过所述输出电路将所述复合输出信号输出至所述输出端;充电阶段,响应于所述第一补偿控制信号和所述第二补偿控制信号,通过所述充电子电路将所述消隐控制信号输入到所述控制节点;所述消隐时段,包括:第二输入阶段,响应于所述消隐输入信号,通过所述消隐输入电路将所述消隐控制信号输入到所述第一节点;第二输出阶段,在所述第一节点的电平的控制下,通过所述输出电路将所述复合输出信号输出至所述输出端。
附图说明
为了更清楚地说明本公开实施例的技术方案,下面将对实施例的附图作简单地介绍,显而易见地,下面描述中的附图仅仅涉及本公开的一些实施例,而非对本公开的限制。
图1为本公开一些实施例提供的一种移位寄存器单元的示意性框图;
图2为本公开一些实施例提供的另一种移位寄存器单元的示意性框图;
图3为本公开一些实施例提供的又一种移位寄存器单元的示意性框图;
图4为本公开一些实施例提供的再一种移位寄存器单元的示意性框图;
图5A为图2中所示的移位寄存器单元的一种电路结构图;
图5B为图3中所示的移位寄存器单元的一种电路结构图;
图5C为图4中所示的移位寄存器单元的一种电路结构图;
图6A为图2中所示的移位寄存器单元的另一种电路结构图;
图6B为图3中所示的移位寄存器单元的另一种电路结构图;
图6C为图4中所示的移位寄存器单元的另一种电路结构图;
图7为图2中所示的移位寄存器单元的再一种电路结构图;
图8为本公开一些实施例提供的一种移位寄存器单元的信号时序图;
图9为本公开一些实施例提供的一种栅极驱动电路的示意性框图;
图10A为本公开一些实施例提供的一种消隐输入电路和显示输入电路的电路结构图;
图10B为本公开一些实施例提供的另一种消隐输入电路和显示输入电路的电路结构图;
图10C为本公开又一些实施例提供的一种消隐输入电路和显示输入电路的电路结构图;
图10D为本公开又一些实施例提供的又一种消隐输入电路和显示输入电路的电路结构图;
图10E为本公开又一些实施例提供的再一种消隐输入电路和显示输入电路的电路结构图;
图11为本公开一些实施例提供的一种栅极驱动电路的信号时序图;
图12为本公开一些实施例提供的一种显示装置的示意性框图;
图13为本公开一些实施例提供的一种移位寄存器单元的驱动方法的流程图。
具体实施方式
为了使得本公开实施例的目的、技术方案和优点更加清楚,下面将结合本公开实施例的附图,对本公开实施例的技术方案进行清楚、完整地描述。显然,所描述的实施例是本公开的一部分实施例,而不是全部的实施例。基于所描述的本公开的实施例,本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例,都属于本公开保护的范围。
除非另外定义,本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性,而只是用来区分不同的 组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同,而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接,而是可以包括电性的连接,不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系,当被描述对象的绝对位置改变后,则该相对位置关系也可能相应地改变。
为了保持本公开实施例的以下说明清楚且简明,本公开省略了已知功能和已知部件的详细说明。
在通常的OLED显示面板中,除了在子像素单元中设置像素补偿电路以进行内部补偿外,还可以通过设置感测晶体管以进行外部补偿。在进行外部补偿时,由移位寄存器单元构成的栅极驱动电路需要向显示面板中的子像素单元分别提供用于扫描晶体管和感测晶体管的驱动信号,例如,在一帧的显示时段(DS)提供用于扫描晶体管的扫描驱动信号,在一帧的消隐时段(BL)提供用于感测晶体管的感测驱动信号。
目前,在GOA(Gate-driver on Array)电路中,栅极驱动电路输出的感测驱动信号是逐行顺序扫描的,例如,在第一帧的消隐时段输出用于显示面板中第一行的子像素单元的感测驱动信号,在第二帧的消隐时段输出用于显示面板中第二行的子像素单元的感测驱动信号,依次类推,从而完成对显示面板的逐行顺序补偿。长时间的逐行顺序补偿会带来两个严重的问题:一个是在进行多帧的扫描显示过程中会有一条逐行移动的扫描线,另一个是由于补偿时间的差异造成显示面板上的不同区域亮度差异较大。例如,在对显示面板的第100行的子像素单元进行外部补偿时,显示面板的第10行的子像素单元虽然已经进行过外部补偿了,但此时第10行的子像素单元的发光亮度可能已经发生变化,例如发光亮度降低,从而会造成显示面板不同区域的亮度不均匀,在大尺寸的显示面板中这种问题会更加明显。另外,由于在高频率高分辨率的显示中,扫描驱动信号的波形需要有一定的重叠(overlap),重叠的波形对补偿检测过程会有很大的影响,容易使补偿信号产生误输出。
本公开至少一些实施例提供一种移位寄存器单元及其驱动方法、栅极驱动电路及显示装置,该移位寄存器单元包括:消隐输入电路、显示输入电路、输出电路、控制节点和第一节点;消隐输入电路被配置为响应于消隐输入信号在消隐时段将消隐控制信号输入到第一节点,并且,消隐输入电路包括充电子电 路,充电子电路被配置为响应于第一补偿控制信号和第二补偿控制信号,将消隐控制信号输入到控制节点;显示输入电路被配置为响应于显示输入信号在显示时段将显示控制信号输入到第一节点;输出电路被配置为在第一节点的电平的控制下,将复合输出信号输出至输出端。
本公开实施例的移位寄存器单元的电路结构简单,可以实现随机补偿,避免由于逐行顺序补偿造成的扫描线和面板的亮度偏差,提高显示均匀性,提升显示效果。
需要说明的是,在本公开的实施例中,随机补偿指的是区别于逐行顺序补偿的一种外部补偿方法,在某一帧的消隐时段可以随机输出对应于显示面板中任意一行的子像素单元的感测驱动信号,以实现对该行的子像素单元进行补偿的操作,以下各实施例与此相同,不再赘述。
另外,在本公开的实施例中,“一帧”、“每帧”或“某一帧”包括依次进行的显示时段和消隐时段,例如,在显示时段中栅极驱动电路输出显示输出信号,该显示输出信号可以驱动显示面板从第一行到最后一行完成完整的一幅图像的扫描显示,在消隐时段中栅极驱动电路输出消隐输出信号,该消隐输出信号可以用于驱动显示面板中的某一行子像素单元中的感测晶体管,以完成该行子像素单元的外部补偿。
下面结合附图对本公开的几个实施例进行详细说明,但是本公开并不限于这些具体的实施例。
图1为本公开一些实施例提供的一种移位寄存器单元的示意性框图。例如,如图1所示,该移位寄存器单元10可以包括消隐输入电路100、显示输入电路200、输出电路300、控制节点H和第一节点Q。通过级联多个该移位寄存器单元10可以得到栅极驱动电路,该栅极驱动电路用于驱动显示面板,为显示面板的多条栅线依序提供扫描信号,从而在显示面板显示一帧画面的期间进行逐行或隔行扫描等。
例如,消隐输入电路100被配置为响应于消隐输入信号在消隐时段将消隐控制信号(即消隐上拉信号)输入到第一节点Q(这里为上拉节点)。例如,如图1所示,消隐输入电路100连接消隐输入信号端STU1、消隐控制信号端BP(即消隐上拉信号端)和第一节点Q。消隐输入电路100可以在第N帧的显示时段接收并存储消隐控制信号端BP提供的消隐控制信号,并在第N帧的消隐时段,根据消隐输入信号向第一节点Q输出消隐控制信号,从而将第一节点Q 的电位上拉到工作电位。又例如,消隐输入电路100还可以在第N帧的消隐时段接收并存储消隐控制信号,并在第N+1帧的消隐时段根据消隐输入信号向第一节点Q输出消隐控制信号,从而将第一节点Q的电位上拉至工作电位。本公开的实施例对此不作限定。
例如,消隐输入电路100包括充电子电路110,充电子电路110被配置为响应于第一补偿控制信号和第二补偿控制信号,将消隐控制信号输入到控制节点H(这里为上拉控制节点)。例如,如图1所示,充电子电路110连接第一补偿控制信号端OE1、第二补偿控制信号端OE2、消隐控制信号端BP和控制节点H,在一帧的显示时段,当充电子电路110在第一补偿控制信号和第二补偿控制信号的控制下导通时,充电子电路110将消隐控制信号端BP输出的消隐控制信号输入到控制节点H。
例如,显示输入电路200被配置为响应于显示输入信号在显示时段将显示控制信号(即显示上拉信号)输入到第一节点Q。例如,如图1所示,显示输入电路200连接显示输入信号端STU2、显示控制信号端DP(即显示上拉信号端)和第一节点Q连接,当显示输入电路200在显示输入信号端STU2提供的显示输入信号的控制下导通时,显示控制信号端DP和第一节点Q连接,从而使显示控制信号端DP提供的显示控制信号被写入到第一节点Q,以将第一节点Q的电位上拉到工作电位。
例如,消隐控制信号和显示控制信号可以相同。也就是说,消隐控制信号端BP和显示控制信号端DP可以为同一个信号端,由此减少信号端的数量,节约成本;或者,消隐控制信号端BP和显示控制信号端DP也可以为不同的信号端,但输出相同的信号。本公开对此不作限制,例如,消隐控制信号和显示控制信号也可以不相同。
例如,输出电路300被配置为在第一节点Q的电平的控制下,将复合输出信号输出至输出端OP。例如,如图1所示,输出电路300连接第一节点Q、第一输出时钟信号端CLKD和输出端OP。当输出电路300在第一节点Q的电平的控制下导通时,第一输出时钟信号端CLKD提供的复合输出信号被输出至输出端OP。例如,输出端OP的输出信号可以包括显示输出信号和消隐输出信号,显示输出信号和消隐输出信号可以是具有不同宽度和时序的相互独立的两个波形的信号。例如,在一帧的显示时段,输出电路300在第一节点Q的电平的控制下经由输出端OP输出显示输出信号,以驱动像素单元中的扫描晶体管, 从而进行显示;在一帧的消隐时段,输出电路300在第一节点Q的电平的控制下经由输出端OP输出消隐输出信号,以驱动像素单元中的感测晶体管,从而进行补偿检测。
在本公开的实施例中,可以将消隐输入电路100、显示输入电路200和输出电路300可以进行整合,使一帧画面的消隐时段的消隐输出信号和显示时段的显示输出信号通过同一个输出电路300输出,从而简化电路结构,减小移位寄存器单元以及包括移位寄存器单元的栅极驱动电路的尺寸。
例如,第一补偿控制信号和第二补偿控制信号其中之一为随机信号。在一些示例中,第一补偿控制信号为随机信号,第一补偿控制信号端OE1与外部控制电路连接,外部控制电路可以向第一补偿控制信号端OE1提供第一补偿控制信号,且第一补偿控制信号可以为随机信号。外部控制电路例如可以为采用现场可编程门阵列(Field Programmable Gate Array,FPGA)或其他信号发生电路实现,由此输出适当类型的随机信号作为第一补偿控制信号。例如,外部控制电路可以被配置为在一帧的显示时段将随机信号输出至第一补偿控制信号端OE1。下面,以第一补偿控制信号为随机信号为例详细描述本公开提供的移位寄存器单元。但本公开不限于此,在另一些实施例中,第二补偿控制信号可以为随机信号,或者第一补偿控制信号和第二补偿控制信号均为随机信号。
例如,输出端OP可以包括移位信号输出端和第一像素信号输出端,在一些示例中,本级移位寄存器单元的第二补偿控制信号端OE2可以与本级移位寄存器单元的移位信号输出端连接,从而移位信号输出端输出的信号可以作为第二补偿控制信号。
例如,在一些示例中,外部控制电路可以与所有级移位寄存器单元的移位信号输出端连接,根据实际需要,外部控制电路可以在一帧的显示时段随机选择一个移位寄存器单元的移位信号输出端的信号,并将该信号向第一补偿控制信号端OE1输出。
例如,在一些实施例中,在进行随机检测时,在第N帧时,需要对显示面板中的第i行子像素单元进行检测时。第i行子像素单元与第i级移位寄存器单元对应,在第i级移位寄存器单元中,在第N帧的显示时段,外部控制电路用于将第i级移位寄存器单元的移位信号输出端输出的信号传输至所有级移位寄存器单元的第一补偿控制信号端OE1,即所有级移位寄存器单元的第一补偿控制信号可以与第i级移位寄存器单元的移位信号输出端输出的信号的波形脉 冲宽度和时序相同,由于第i级移位寄存器单元的第二补偿控制信号也为第i级移位寄存器单元的移位信号输出端输出的信号,且充电子电路110由第一补偿控制信号和第二补偿控制信号共同控制,当输出信号的波形不重叠时,只有第i级移位寄存器单元中的充电子电路110可以在第一补偿控制信号和第二补偿控制信号控制下导通。由于充电子电路110连接消隐控制信号端BP和控制节点H,在第i级移位寄存器单元中,当充电子电路110导通时,消隐控制信号端BP输出的消隐控制信号为高电平信号,从而可以利用消隐控制信号对控制节点H进行充电,以使得控制节点H被充电至高电平。由此,在第N帧的消隐时段中,第i级移位寄存器单元的控制节点H的高电平信号可以被传输第一节点Q,从而第i级移位寄存器单元的输出电路300可以输出用于驱动第i行子像素单元中的感测晶体管的消隐输出信号。
例如,本公开实施例提供的移位寄存器单元还可以实现逐行顺序补偿。在进行逐行顺序补偿时,在一些示例中,本级移位寄存器单元的第二补偿控制信号端OE2可以与本级移位寄存器单元的移位信号输出端连接,所有级移位寄存器单元的第一补偿控制信号端OE1在第一帧的显示时段时接收第一级移位寄存器单元的移位信号输出端的信号,所有级移位寄存器单元的第一补偿控制信号端OE1在第二帧的显示时段时接收第二级移位寄存器单元的移位信号输出端的信号,依次类推,由此,在第一帧的显示时段,只有第一级移位寄存器单元的控制节点H可以被充电至高电平,在第二帧的显示时段,只有第二级移位寄存器单元的控制节点H可以被充电至高电平,以此类推,从而显示面板可以实现逐行顺序补偿。
本公开的实施例提供的移位寄存器单元10,通过设置充电子电路110可以在兼顾逐行顺序补偿的前提下还实现随机补偿,从而可以避免由于逐行顺序补偿造成的扫描线以及显示亮度不均匀等显示不良问题。
例如,如图1所示,消隐输入电路100还包括存储子电路120和隔离子电路130。存储子电路120与控制节点H连接,且被配置为存储充电子电路110输入的消隐控制信号。例如,在一些示例中,在一帧的显示时段中,利用消隐控制信号将控制节点H充电至高电平,存储子电路120可以存储消隐控制信号,从而使得控制节点H的高电平一直保持至该帧的消隐时段。
例如,隔离子电路130被配置为在消隐输入信号的控制下,在消隐时段将消隐控制信号输入到第一节点Q。如图1所示,隔离子电路130连接消隐输入 信号端STU1、控制节点H和第一节点Q。当隔离子电路130在消隐输入信号端STU1提供的消隐输入信号的控制下导通时,控制节点H和第一节点Q连接,从而将存储子电路120存储的消隐控制信号输入到第一节点Q,以对第一节点Q充电,将第一节点Q的电位上拉到工作电位。
需要说明的是,本公开的各实施例中,消隐输入电路100可以包括任意适用的子电路,不局限于上述充电子电路110、存储子电路120和隔离子电路130,只要能实现相应功能即可。
图2为本公开一些实施例提供的另一种移位寄存器单元的示意性框图。
例如,如图2所示,该移位寄存器单元10还可以包括降噪电路400(这里为下拉电路)、第一控制电路500(这里为第一下拉控制电路)和第二节点QB(这里为下拉节点)。
例如,降噪电路400被配置为在第二节点QB的电平的控制下,对第一节点Q和输出端OP进行降噪;也就是说,降噪电路400被配置为在第二节点QB的电平的控制下,将第一节点Q的电平和输出端OP的电平均下拉为低电平。例如,如图2所示,降噪电路400与第二节点QB、第一节点Q、第二电压端VGL1和输出端OP连接,且当降噪电路400在第二节点QB的电平的控制下导通时,第一节点Q和输出端OP可以连接第二电压端VGL1(例如,低电压端),从而通过第二电压端VGL1的第二电压将第一节点Q下拉至非工作电位,并将输出端OP的电平下拉至低电平,以实现第一节点Q和输出端OP的降噪。
需要说明的是,在本公开的实施例中第二电压端VGL1例如可以被配置为提供第二电压,且第二电压为直流低电平信号,以下各实施例与此相同,不再赘述。
例如,第一控制电路500被配置为在第一节点Q的电平的控制下,对第二节点QB的电平进行控制。例如,如图2所示,第一控制电路500连接第一节点Q和第二节点QB。第一控制电路500可以被配置为当第一节点Q为高电平时将第二节点QB下拉为低电平,而当第一节点Q为低电平时将第二节点QB上拉为高电平。例如,第一控制电路500可以为反相电路,反相电路的输入端连接第一节点Q,反相电路的输出端连接第二节点QB。
需要说明的是,图2所示的移位寄存器单元10的其他电路结构与图1中所示的移位寄存器单元10基本上相同,重复之处不再赘述。
图3为本公开一些实施例提供的又一种移位寄存器单元的示意性框图,图4为本公开一些实施例提供的再一种移位寄存器单元的示意性框图。
例如,如图3所示,该移位寄存器单元10还可以包括第二控制电路600(这里为第二下拉控制电路)。第二控制电路600被配置为响应于第一控制信号(这里为消隐下拉控制信号)对第二节点QB的电平进行控制。例如,如图3所示,第二控制电路600连接第二电压端VGL1、第二节点QB和消隐下拉控制端Con1,且第二控制电路600被配置为在一帧的消隐时段,在消隐下拉控制端Con1提供的第一控制信号的控制下导通,使第二节点QB与第二电压端VGL1连接,从而通过第二电压端VGL1的第二电压将第二节点QB下拉为非工作电位。
由于移位寄存器单元长时间工作后,电路中的晶体管的阈值电压容易漂移,例如正漂,因此通过消隐输入电路100写入到第一节点Q的高电平会低于预定值,从而难以通过第一控制电路500对第二节点QB进行下拉,也会进一步影响输出端OP的输出信号。本公开的实施例提供的移位寄存器单元10包括第二控制电路600,第二控制电路600可以在一帧的消隐时段中对第二节点QB进行下拉,以确保第二节点QB处于低电平,使得消隐输入电路100对第一节点Q的充电更充分,使第一节点Q的高电平达到预定值,因此可防止晶体管阈值电压漂移后影响输出信号,增强了电路的信赖性。
例如,如图4所示,该移位寄存器单元10还可以包括第三控制电路700(这里为第三下拉控制电路)。第三控制电路700被配置为响应于第二控制信号(这里为显示下拉控制信号)对第二节点QB的电平进行控制。例如,第三控制电路700连接第二节点QB、显示下拉控制端Con2和第二电压端VGL1。在一帧的显示时段,在显示下拉控制端Con2提供的第二控制信号的控制下,当第三控制电路700导通时,第二节点QB与第二电压端VGL1连接,从而通过第二电压端VGL1的第二电压将第二节点QB下拉为非工作电位。
在本公开的实施例提供的移位寄存器单元10中,第三控制电路700可以在一帧的显示时段中对第二节点QB进行下拉,以确保第二节点QB处于低电平,使得显示输入电路200对第一节点Q的充电更充分,使第一节点Q的高电平达到预定值,因此可防止晶体管阈值电压漂移后影响输出信号,增强了电路的信赖性。
需要说明的是,在本公开实施例提供的移位寄存器单元中,与图3和图4 所示的示例不同,在一些示例中,移位寄存器单元也可以仅包括第三控制电路700,而不包括第二控制电路600。
例如,如图2、图3和图4所示,移位寄存器单元10还包括消隐复位电路800和显示复位电路900。消隐复位电路800被配置为响应于消隐复位信号对第一节点Q进行复位。显示复位电路900被配置为响应于显示复位信号对第一节点Q进行复位。
例如,如图2、图3和图4所示,消隐复位电路800连接消隐复位信号端TR、第二电压端VGL1和第一节点Q。在消隐复位信号端TR提供的消隐复位信号的控制下,当消隐复位电路800导通时,第一节点Q与第二电压端VGL1连接,从而通过第二电压端VGL1的第二电压将第一节点Q下拉为非工作电位,以对第一节点Q进行复位,即将低电平的第二电压写入第一节点Q。例如,在一帧的消隐时段,当输出电路300完成信号输出后,消隐复位电路800在消隐复位信号的控制下导通,从而将第二电压端VGL1输出的第二电压写入第一节点Q,以对第一节点Q进行复位;又例如,在一帧的显示时段前,消隐复位电路800在消隐复位信号的控制下导通,从而将第二电压端VGL1输出的第二电压写入第一节点Q,以对第一节点Q进行复位。
例如,如图2、图3和图4所示,显示复位电路900连接显示复位信号端STD、第二电压端VGL1和第一节点Q。在显示复位信号端STD提供的显示复位信号的控制下,当显示复位电路900导通时,第一节点Q与第二电压端VGL1连接,从而通过第二电压端VGL1的第二电压将第一节点Q下拉为非工作电位,以对第一节点Q进行复位。例如,在一帧的显示时段,当输出电路300完成信号输出后,显示复位电路900在显示复位信号的控制下导通,从而将第二电压端VGL1输出的第二电压写入第一节点Q,以对第一节点Q复位。
值得注意的是,图3和图4所示的移位寄存器单元10的其他电路结构可以与图2中所示的移位寄存器单元10基本上相同,重复之处不再赘述。另外,在图3和图4所示的示例中,第一控制电路500、第二控制电路600、第三控制电路700、消隐复位电路800和显示复位电路900均连接到第二电压VGL1以接收直流低电平信号,但不限于此,第一控制电路500、第二控制电路600、第三控制电路700、消隐复位电路800和显示复位电路900也可以分别连接到不同的电源电压端,以接收不同的低电平信号,只要能够实现相应的功能即可,本公开对此不作具体限制。
图5A为图2中所示的移位寄存器单元的一种电路结构图,图5B为图3中所示的移位寄存器单元的一种电路结构图,图5C为图4中所示的移位寄存器单元的一种电路结构图,图6A为图2中所示的移位寄存器单元的另一种电路结构图,图6B为图3中所示的移位寄存器单元的另一种电路结构图,图6C为图4中所示的移位寄存器单元的另一种电路结构图。在下面对本公开的说明中以各晶体管为N型晶体管为例进行说明,但这并不构成对本公开实施例的限制。
例如,如图5A至图6C所示,充电子电路110包括第一晶体管M1和第二晶体管M2。第一晶体管M1的栅极被配置为与第一补偿控制信号端OE1连接以接收第一补偿控制信号,第一晶体管M1的第一极被配置为与消隐控制信号端BP连接以接收消隐控制信号,第一晶体管M1的第二极被配置为与第二晶体管M2的第一极连接,第二晶体管M2的第二极被配置为与控制节点H连接,第二晶体管M的栅极被配置为与第二补偿控制信号端OE2连接以接收第二补偿控制信号。
例如,图5A至图6C所示的示例中,消隐控制信号端BP和显示控制信号端DP可以为同一个信号端,且均为第六电压端VDD,即第六电压端VDD等同于前述的消隐控制信号端BP和显示控制信号端DP。例如,第六电压端VDD被配置为提供第六电压,第六电压为直流高电平信号,以下各实施例与此相同,不再赘述。也就是说,如图5A至图6C所示,第一晶体管M1的第一极被配置为与第六电压端VDD连接以接收第六电压,消隐控制信号可以为第六电压。
例如,当第一补偿控制信号和第二补偿控制信号均为有效电平(例如,高电平)时,第一晶体管M1和第二晶体管M2导通,使第六电压端VDD与控制节点H连接,从而将第六电压(高电平信号)写入控制节点H。
需要说明的是,除了图5A至图6C所示的示例外,在本公开的实施例中,第一晶体管M1的第一极还可以与其他信号端连接以接收消隐控制信号,本公开对此不作限定。
例如,如图5A至图6C所示,存储子电路120包括第一电容C1。第一电容C1的第一极被配置为和控制节点H连接,第一电容C1的第二极被配置为与第一电压端VA连接以接收第一电压。例如,在一帧的显示时段中,消隐控制信号被写入到控制节点H,第一电容C1存储消隐控制信号(高电平),并将控制节点H维持在高电平直到该帧的消隐时段。
例如,第一电压端VA被配置为提供第一电压,在一些示例中,第一电压为直流高电平信号;在另一些示例中,第一电压可以为直流低电平信号。以下各实施例与此相同,不再赘述。
需要说明的是,本公开的各实施例中,第一电容C1可以是通过工艺制程制作的电容器件,例如通过制作专门的电容电极来实现电容器件,该电容的各个电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现,并且,第一电容C1也可以是各个器件之间的寄生电容,可以通过晶体管本身与其他器件、线路来实现。第一电容C1的连接方式不局限于上面描述的方式,也可以为其他适用的连接方式,只要能存储写入到控制节点H的消隐控制信号即可。例如,在一些示例中,第一电容C1的第一极被配置为和控制节点H连接,第一电容C1的第二极接地。
例如,如图5A至图6C所示,隔离子电路130包括第三晶体管M3。第三晶体管M3的栅极被配置为与消隐输入信号端STU1连接以接收消隐输入信号,第三晶体管M3的第一极被配置为与控制节点H连接,第三晶体管M3的第二极被配置为与第一节点Q连接。
例如,在图5A至图6C所示的实施例中,第一时钟信号端CLKA等同于前述的消隐输入信号端STU1,第一时钟信号端CLKA用于提供第一时钟信号,消隐输入信号可以为第一时钟信号。也就是说,如图5A至图6C所示,第三晶体管M3的栅极被配置为与第一时钟信号端CLKA连接。当第一时钟信号为高电平时,第三晶体管M3导通,控制节点H与第一节点Q连接,从而将消隐控制信号写入到第一节点Q,以将第一节点Q的电位上拉到工作电位。
例如,如图5A至图6C所示,显示输入电路200包括第四晶体管M4。第四晶体管M4的栅极与显示输入信号端STU2连接以接收显示输入信号,第四晶体管M4的第一极与显示控制信号端DP(即第六电压端VDD)连接以接收显示控制信号(即第六电压),第四晶体管M4的第二极与第一节点Q连接。例如,在一帧的显示时段,当显示输入信号为有效电平(例如,高电平)时,第四晶体管M4导通,使第六电压端VDD与第一节点Q连接,从而将第六电压写入第一节点Q,将第一节点Q的电位上拉到工作电位。
需要说明的是,除了图5A至图6C所示的示例外,在本公开的实施例中,第四晶体管M4的第一极还可以与其他信号端连接以接收显示控制信号,本公开对此不作限定。
例如,如图5A至图6C所示,输出端OP可以包括移位信号输出端CR和第一像素信号输出端OT1,移位信号输出端CR输出的信号和第一像素信号输出端OT1输出的信号相同。在一些示例中,当图5A至图6C所示的移位寄存器单元10级联构成一栅极驱动电路时,第n+2级移位寄存器单元10的显示输入信号端STU2可以与第n级移位寄存器单元10的移位信号输出端CR连接,n为大于0的整数。第一像素信号输出端OT1可以用于为像素电路提供扫描驱动信号。
例如,如图5A至图6C所示,输出电路300可以包括第一输出晶体管M13、第二输出晶体管M15和第二电容C2。第一输出晶体管M13的栅极与第一节点Q连接,第一输出晶体管M13的第一极与第一输出时钟信号端CLKD连接以接收第一输出时钟信号,第一输出晶体管M13的第二极与移位信号输出端CR连接;第二输出晶体管M15的栅极和第一节点Q连接,第二输出晶体管M15的第一极与第一输出时钟信号端CLKD连接以接收第一输出时钟信号,第二输出晶体管M15的第二极与第一像素信号输出端OT1连接;第二电容C2的第一极和第一节点Q连接,第二电容C2的第二极与第一输出晶体管M13的第二极连接。
例如,当第一节点Q处于工作电位(例如,高电平)时,第一输出晶体管M13和第二输出晶体管M15均导通,第一输出时钟信号经由第一输出晶体管M13传输至移位信号输出端CR以作为第一输出信号,第一输出时钟信号经由第二输出晶体管M15传输至第一像素信号输出端OT1以作为第二输出信号。
例如,复合输出信号包括第一输出信号和第二输出信号,第一输出信号和第二输出信号相同。例如,第二输出信号包括上述显示输出信号和消隐输出信号,即在显示时段,第一像素信号输出端OT1输出的信号为显示输出信号;在消隐时段,第一像素信号输出端OT1输出的信号为消隐输出信号。
需要说明的是,本公开的各实施例中,第二电容C2可以是通过工艺制程制作的电容器件,例如通过制作专门的电容电极来实现电容器件,该电容的各个电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现,并且,第二电容C2也可以是晶体管之间的寄生电容,可以通过晶体管本身与其他器件、线路来实现,只要能维持第一节点Q的电平且在移位信号输出端CR或第一像素信号输出端OT1输出信号时实现自举作用即可。
例如,如图6A至图6C所示,在一些示例中,输出端OP还包括第二像素 信号输出端OT2,输出电路300还包括第三输出晶体管M17。输出电路300还连接第二输出时钟信号端CLKE,第二输出时钟信号端CLKE用于输出第二输出时钟信号。
例如,第三输出晶体管M17的栅极与第一节点Q连接,第三输出晶体管M17的第一极与第二输出时钟信号端CLKE连接以接收第二输出时钟信号,第三输出晶体管M17的第二极与第二像素信号输出端OT2连接。
例如,当第一节点Q处于工作电位(例如,高电平)时,第三输出晶体管M17导通,第二输出时钟信号经由第三输出晶体管M17传输至第二像素信号输出端OT2以作为第三输出信号,复合输出信号还包括第三输出信号。
例如,在一个示例中,第一输出时钟信号端CLKD和第二输出时钟信号端CLKE提供的时钟信号相同,因此,第一像素信号输出端OT1和第二像素信号输出端OT2输出的信号相同。例如,在另一个示例中,第一输出时钟信号端CLKD和第二输出时钟信号端CLKE提供的信号不同,从而使得第一像素信号输出端OT1输出的第二输出信号和第二像素信号输出端OT2输出的第三输出信号不同,以便为像素单元提供多种不同的驱动信号。
例如,如图5A至图6C所示,第一控制电路500包括第五晶体管M5、第六晶体管M6和第七晶体管M7。第五晶体管M5的栅极与第一节点Q连接,第五晶体管M5的第一极与第二节点QB连接,第五晶体管M5的第二极与第二电压端VGL1连接以接收第二电压;第六晶体管M6的栅极和第一极连接且被配置为与第三电压端VDD_A连接以接收第三电压,第六晶体管M6的第二极与第二节点QB连接;第七晶体管M7的栅极与第一极连接且被配置为与第四电压端VDD_B连接以接收第四电压,第七晶体管M7的第二极与第二节点QB连接。
例如,在一个示例中,第三电压端VDD_A被配置为提供直流低电平信号,第四电压端VDD_B被配置为提供直流高电平信号,因此,第六晶体管M6始终截止,第七晶体管M7始终导通。例如,在另一个示例中,第三电压端VDD_A和第四电压端VDD_B被配置为交替提供直流高电平信号,从而使第六晶体管M6和第七晶体管M7交替导通,以避免晶体管长期导通引起的性能漂移。例如,当第三电压端VDD_A提供高电平信号时,第四电压端VDD_B提供低电平信号,此时第六晶体管M6导通,第七晶体管M7截止;当第四电压端VDD_B提供高电平信号时,第三电压端VDD_A提供低电平信号,此时,第七晶体管 M7导通,第六晶体管M6截止。
例如,当第一节点Q为有效电平(例如,高电平)时,第五晶体管M5导通,通过设计第五晶体管M5的沟道宽长比与导通的第六晶体管M6的沟道宽长比或导通的第七晶体管M7的沟道宽长比的比例关系,例如,第五晶体管M5的沟道宽长比大于第六晶体管M6的沟道宽长比和第七晶体管M7的沟道宽长比中的任意一个,由此,可以将第二节点QB的电位下拉到低电平。当第一节点Q为低电平时,第五晶体管M5截止,若第六晶体管M6导通,第七晶体管M7截止,则通过第六晶体管M6将第三电压端VDD_A提高的第三电压(高电平)写入第二节点QB,以将第二节点QB的电位上拉至高电平;若第六晶体管M6截止,第七晶体管M7导通,则通过第七晶体管M7将第四电压端VDD_B提高的第四电压(高电平)写入第二节点QB,以将第二节点QB的电位上拉至高电平。
例如,如图5A至图6C所示,降噪电路400可以包括第一降噪晶体管M19、第二降噪晶体管M14和第三降噪晶体管M16。第一降噪晶体管M19的栅极与第二节点QB连接,第一降噪晶体管M19的第一极与第一节点Q连接,第一降噪晶体管M19的第二极与第二电压端VGL1连接以接收第二电压;第二降噪晶体管M14的栅极与第二节点QB连接,第二降噪晶体管M14的第一极与移位信号输出端CR连接,第二降噪晶体管M14的第二极与第二电压端VGL1连接以接收第二电压;第三降噪晶体管M16的栅极与第二节点Q连接,第三降噪晶体管M16的第一极与第一像素信号输出端OT1连接,第三降噪晶体管M16的第二极与第五电压端VGL2连接以接收第五电压。
例如,第五电压端VGL2被配置为提供第五电压,且第五电压为直流低电平信号(例如低于或等于时钟信号的低电平),例如,第五电压端VGL2可以接地,以下各实施例与此相同,不再赘述。例如,在一个示例中,第五电压端VGL2提供的第五电压高于第二电压端VGL1提供的第二电压,例如,第二电压为-10V,第五电压为-6V;在另一个示例中,第五电压端VGL2的第五电压等于第二电压端VGL1的第二电压,从而该移位寄存器单元10可以不设置第五电压端VGL,而将第三降噪晶体管M16的第二极连接第二电压端VGL1以接收第二电压。第五电压和第二电压可以相同也可以不同,这可以根据实际需求而定。本公开的实施例对此不作限定。
例如,当第二节点QB为有效电平(例如,高电平)时,第一降噪晶体管 M19、第二降噪晶体管M14和第三降噪晶体管M16均导通,第一节点Q和移位信号输出端CR均与第二电压端VGL1连接,从而通过第二电压端VGL1的第二电压将第一节点Q的电位和移位信号输出端CR的电位下拉为低电位,第一像素信号输出端OT1与第五电压端VGL2连接,从而通过第五电压端VGL2的第五电压将第一像素信号输出端OT1的电位下拉为低电位,由此,降低第一节点Q、移位信号输出端CR和第一像素信号输出端OT1的噪声。需要说明的是,本公开的各实施例中,当输出端OP包括多个第一像素信号输出端OT1和/或多个移位信号输出端CR时,降噪电路400也相应地包括与多个移位信号输出端CR和/或多个第一像素信号输出端OT1一一对应连接的多个晶体管,以对多个移位信号输出端CR和/或多个第一像素信号输出端OT1进行降噪。
例如,如图6A至图6C所示,在一些示例中,在输出端OP还包括第二像素信号输出端OT2的情况下,降噪电路400还包括第四降噪晶体管M18。第四降噪晶体管M18的栅极与第二节点QB连接,第四降噪晶体管M18的第一极与第二像素信号输出端OT2连接,第四降噪晶体管M18的第二极与第五电压端VGL2连接以接收第五电压。例如,当第二节点QB为有效电平(例如,高电平)时,第四降噪晶体管M18导通,第二像素信号输出端OT2与第五电压端VGL2连接,从而通过第五电压端VGL2的第五电压将第二像素信号输出端OT2的电位下拉为低电位,由此降低第二像素信号输出端OT2的噪声。
例如,如图5B、图5C、图6B和图6C所示,第二控制电路600包括第八晶体管M8,第一时钟信号端CLKA提供第一时钟信号,第一控制信号包括第一时钟信号,即第一时钟信号端CLKA等同于前述的消隐下拉控制端Con1。第八晶体管M8的栅极与第一时钟信号端CLKA连接以接收第一时钟信号,第八晶体管M8的第一极与第二节点QB连接,第八晶体管M8的第二极与第二电压端VGL1连接以接收第二电压。例如,在一帧的消隐时段,当第一时钟信号为有效电平(例如,高电平)时,第八晶体管M8导通,第二节点QB与第二电压端VGL1连接,第二电压端VGL1提供的第二电压被写入第二节点QB,从而第二节点QB被下拉至低电平。
例如,如图5C和图6C所示,第三控制电路700包括第十一晶体管M11。第十一晶体管M11的栅极配置为连接显示下拉控制端Con2以接收第二控制信号,第十一晶体管M11的第一极配置为连接第二节点QB,第十一晶体管M11的第二极配置为连接第二电压端VGL1以接收第二电压。例如,在一帧的显示 时段,当第二控制信号为有效电平(例如,高电平)时,第十一晶体管M11导通,第二节点QB与第二电压端VGL1连接,第二电压端VGL1提供的第二电压被写入第二节点QB,从而第二节点QB被下拉至低电平。
例如,在一个示例中,在多个移位寄存器单元10级联的情形下,第m1级移位寄存器单元10的移位信号输出端CR与第m1+2级移位寄存器单元10的第二控制信号端Con2连接,以将第m1级移位寄存器单元10的移位信号输出端CR的输出信号作为第m1+2级移位寄存器单元10的第二控制信号。这里,m1为大于0的整数。当然,本公开的实施例不限于此,显示下拉控制端Con2也可以与单独设置的信号线连接。
例如,如图5A至图6C所示,消隐复位电路800包括第九晶体管M9。第九晶体管M9的栅极与消隐复位信号端TR连接以接收消隐复位信号,第九晶体管M9的第一极与第一节点Q连接,第九晶体管M9的第二极与第二电压端VGL1连接以接收第二电压。例如,在一帧的消隐时段,当消隐复位信号为有效电平(例如,高电平)时,第九晶体管M9导通,第一节点Q与第二电压端VGL1连接,第二电压端VGL1提供的第二电压被写入第一节点Q,从而实现对第一节点Q进行复位。
例如,如图5A至图6C所示,显示复位电路900包括第十晶体管M10。第十晶体管M10的栅极与显示复位信号端STD连接以接收显示复位信号,第十晶体管M10的第一极与第一节点Q连接,第十晶体管M10的第二极与第二电压端VGL1连接以接收第二电压。例如,在一帧的显示时段,当显示复位信号为有效电平(例如,高电平)时,第十晶体管M10导通,第一节点Q与第二电压端VGL1连接,第二电压端VGL1提供的第二电压被写入第一节点Q,从而实现对第一节点Q进行复位。
例如,在一个示例中,在多个移位寄存器单元10级联的情形下,第m2+3级移位寄存器单元10的移位信号输出端CR与第m2级移位寄存器单元10的显示复位信号端STD连接,以将第m2+3级移位寄存器单元10的移位信号输出端CR的输出信号作为第m2级移位寄存器单元10的显示复位信号。这里,m2为大于0的整数。当然,本公开的实施例不限于此,显示复位信号端STD也可以与单独设置的信号线连接。
需要说明的是,本领域技术人员可以理解,在本公开的实施例中,消隐输入电路100、显示输入电路200、输出电路300、降噪电路400、第一控制电路 500,第二控制电路600、第三控制电路700、消隐复位电路800以及显示复位电路900等的具体实现方式不局限于上面描述的方式,其可以为任意适用的实现方式,例如为本领域技术人员熟知的常规连接方式,只需保证实现相应功能即可。上述示例并不能限制本公开的保护范围。在实际应用中,技术人员可以根据情况选择使用或不使用上述各电路中的一个或多个,基于前述各电路的各种组合变型均不脱离本公开的原理,对此不再赘述。
图7为图2中所示的移位寄存器单元的再一种电路结构图。例如,如图7所示,除了进一步包括防漏电电路外,该实施例的移位寄存器单元10与图5A中描述的移位寄存器单元10基本上相同。在图5A所示的移位寄存器单元10中,可以利用第二电容C2维持第一节点Q的电位。例如,如图5A所示,当第一节点Q的电位维持在高电平时,移位寄存器单元10中的一些晶体管(例如,第九晶体管M9、第十晶体管M10和第一降噪晶体管M19)的第一极连接第一节点Q,这些晶体管的第二极连接低电平的信号线。即使当这些晶体管的栅极接收非导通信号的情况下,由于这些晶体管的第一极和第二极之间存在电压差,也可能出现漏电的现象,从而第一节点Q的电位的维持效果变差。因此,图7所示的移位寄存器单元10增加了防漏电电路,以改善对第一节点Q的电位的维持效果。
例如,如图7所示,第一防漏电电路可以包括第一防漏电晶体管M20、第二防漏电晶体管M9b、第三防漏电晶体管M10b和第四防漏电晶体管M19b。第一防漏电电路被配置为在第一节点Q为高电平时,防止第一节点Q处的电荷经由第九晶体管M9a、第十晶体管M10a和第一降噪晶体管M19a漏电到第二电压端VGL1。以第二防漏电晶体管M9b为例,第二防漏电晶体管M9b的栅极连接到第九晶体管M9a的栅极(即第二防漏电晶体管M9b的栅极连接消隐复位信号端TR),第二防漏电晶体管M9b的第一极连接到第一节点Q,第二防漏电晶体管M9b的第二极连接到第九晶体管M9a的第一极,第二防漏电晶体管M9b的第二极还连接到第一防漏电晶体管M20的第二极。第一防漏电晶体管M20的栅极连接到第一节点Q,第一防漏电晶体管M20的第一极连接到第六电压端VDD。
例如,当第一节点Q为高电平时,第一防漏电晶体管M20在第一节点Q的控制下导通,并将第六电压(高电压)写入到第二防漏电晶体管M9b的第二极,从而使第二防漏电晶体管M9b的第一极和第二极都处于高电平的状态, 以防止第一节点Q处的电荷通过第九晶体管M9a漏电。此时,由于第九晶体管M9a的栅极与第二防漏电晶体管M9b的栅极连接,因此第九晶体管M9a与第二防漏电晶体管M9b的结合可以实现与图5A至图6C所示的第九晶体管M9相同的功能,并同时具有防漏电的效果。类似地,利用第三防漏电晶体管M10b和第四防漏电晶体管M19b进行防漏电的原理与利用第二防漏电晶体管M9b防漏电的原理类似,此处不再赘述。
需要说明的是,本领域技术人员可以理解,根据本公开的实施例提供的具有防漏电功能的电路的实施例,可以根据实际情况选择移位寄存器单元10中的一个或多个晶体管增加防漏电的电路结构。图7仅示出了包括防漏电电路的一种示例性的电路结构,而不构成对本公开实施例的限制。另外,在本公开的各个实施例的说明中,第一节点Q、第二节点QB和控制节点H等并非表示实际存在的部件,而是表示电路图中相关连接的汇合点。
需要说明的是,本公开的实施例中采用的晶体管均可以为薄膜晶体管、场效应晶体管或其他特性相同的开关器件,本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的,所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中,为了区分晶体管除栅极之外的两极,直接描述了其中一极为第一极,另一极为第二极。
另外,本公开的实施例中的晶体管均以N型晶体管为例进行说明,此时,晶体管的第一极是漏极,第二极是源极。需要说明的是,本公开包括但不限于此。例如,本公开的实施例提供的移位寄存器单元10中的一个或多个晶体管也可以采用P型晶体管,此时,晶体管第一极是源极,第二极是漏极,只需将选定类型的晶体管的各极参照本公开的实施例中的相应晶体管的各极相应连接,并且使相应的电压端提供对应的高电压或低电压即可。当采用N型晶体管时,可以采用氧化铟镓锌(Indium Gallium Zinc Oxide,IGZO)作为薄膜晶体管的有源层,相对于采用低温多晶硅(Low Temperature Poly Silicon,LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层,可以有效减小晶体管的尺寸以及防止漏电流。
图8为本公开一些实施例提供的一种移位寄存器单元的信号时序图。下面结合图8所示的信号时序图,对图6A所示的移位寄存器单元10的工作原理进行说明,并且这里以各个晶体管为N型晶体管为例进行说明,但是本公开的实施例不限于此。
在图8中以及下面的描述中,1F表示第一帧的时序。DS表示一帧的显示时段,BL表示一帧的消隐时段。STU1、STU2、TR、VDD_A、VDD_B、CLKA、CLKD、CLKE、OT1、OT2、CR等既用于表示相应的信号端,也用于表示相应的信号。以下各实施例与此相同,不再赘述。
例如,在初始阶段0,消隐复位信号TR和第一时钟信号CLKA为高电平,第九晶体管M9导通,第二电压端VGL1的第二电压经由第九晶体管M9被写入第一节点Q,以对第一节点Q进行复位。第三电压VDD_A为低高电平信号,第四电压VDD_B为高电平信号,由此,第六晶体管M6截止,第七晶体管M7导通,第四电压VDD_B经由第七晶体管M7被写入第二节点QB,第二节点QB的电位上拉至高电平,由此,第一降噪晶体管M19导通,从而对第一节点Q进行辅助下拉,使第一节点Q的电位为低电平。第三晶体管M3也导通,由此控制节点H也被复位。
例如,在显示时段DS,在第一阶段1中,显示输入信号端STU2为高电平,第四晶体管M4导通,显示控制信号(例如,第六电压端VDD提供的高电平的第六电压)经由第四晶体管M4被写入第一节点Q,且被第二电容C2存储。显示复位信号STD(未示出)和第一时钟信号CLKA均为低电平信号,第十晶体管M10和第三晶体管M3均截止。由于第一节点Q为高电平,第一输出晶体管M13、第二输出晶体管M15和第三输出晶体管M17均导通,第一输出时钟信号CLKD经由第一输出晶体管M13和第二输出晶体管M15被分别输出至移位信号输出端CR和第一像素信号输出端OT1,第二输出时钟信号CLKE经由第三输出晶体管M17被输出至第二像素信号输出端OT2。但由于第一输出时钟信号CLKD和第二输出时钟信号CLKE均为低电平信号,即移位信号输出端CR、第一像素信号输出端OT1和第二像素信号输出端OT2均输出低电平信号。另外,由于第一节点Q为高电平,第五晶体管M5导通,从而将第二节点QB的电位下拉到低电平。
例如,在第二阶段2中,第一节点Q保持为高电平,第一输出晶体管M13、第二输出晶体管M15和第三输出晶体管M17保持导通,第一输出时钟信号CLKD和第二输出时钟信号CLKE均变为高电平,由此移位信号输出端CR、第一像素信号输出端OT1和第二像素信号输出端OT2均输出高电平信号,由于第二电容C2的自举效应,第一节点Q的电位进一步被拉高,第一输出晶体管M13、第二输出晶体管M15和第三输出晶体管M17更加充分导通。例如, 移位信号输出端CR输出的高电平信号可以用于上下级移位寄存器单元的扫描移位,从第一像素信号输出端OT1和第二像素信号输出端OT2输出的高电平信号可以用于驱动显示面板中的子像素单元进行显示。
例如,在图6A所示的示例中,本级移位寄存器单元的第二补偿控制信号端OE2可以与本级移位寄存器单元的移位信号输出端CR连接。在第二阶段2中,第一补偿控制信号OE1为高电平信号,第一晶体管M1导通,移位信号输出端CR输出的信号也为高电平信号,也就是说,第二补偿控制信号OE2为高电平信号,由此第二晶体管M2也导通,消隐控制信号(例如,第六电压端VDD提供的高电平的第六电压)经由第一晶体管M1和第二晶体管M2被写入到控制节点H,控制节点H的电平变为高电平。需要说明的是,第一电容C1可以存储高电平的消隐控制信号并保持到一帧的显示时段结束,以在消隐时段使用。
例如,在第三阶段3,第一输出时钟信号CLKD和第二输出时钟信号CLKE变为低电平,移位信号输出端CR和第一像素信号输出端OT1均可以通过第一输出时钟信号端CLKD放电,从而完成移位信号输出端CR和第一像素信号输出端OT1的复位;第二像素信号输出端OT2通过第二输出时钟信号端CLKE放电,从而完成第二像素信号输出端OT2的复位。此时,移位信号输出端CR、第一像素信号输出端OT1和第二像素信号输出端OT2均输出低电平信号,由于第二电容C2的自举作用,第一节点Q的电位有所降低但仍然保持高电平,第一输出晶体管M13、第二输出晶体管M15和第三输出晶体管M17仍保持导通,第一输出时钟信号端CLKD的低电平输出至移位信号输出端CR和第一像素信号输出端OT1,第二输出时钟信号端CLKE的低电平输出至第二像素信号输出端OT2,由此实现输出端OP的复位。
例如,在第四阶段4中,显示复位信号STD(图中未示出)为高电平信号,第十晶体管M10导通,从而第二电压端VGL2的第二电压被写入第一节点Q,以对第一节点Q进行复位。第一节点Q的电平变为低电平,从而第五晶体管M5截止,第三电压VDD_A为高电平信号,第四电压VDD_B为低电平信号,由此,第六晶体管M6截止,第七晶体管M7导通,从而第四电压VDD_B经由第七晶体管M7被写入第二节点QB,第二节点QB被上拉为高电平,从而第一降噪晶体管M19导通,以进一步对第一节点Q进行降噪。第二降噪晶体管M14、第三降噪晶体管M16和第四降噪晶体管M18也在第二节点QB的高电平的控制下导通,从而对移位信号输出端CR、第一像素信号输出端OT1和 第二像素信号输出端OT2进行降噪。
例如,在上述第一阶段1至第四阶段4中,由于第一时钟信号CLKA一直保持低电平,第三晶体管M3处于截止状态,从而隔离控制节点H和第一节点Q,以避免控制节点H的电平影响显示时段的输出信号。如图8所示,第一节点Q的电平呈塔状波形,移位信号输出端CR的输出信号的上拉和复位都通过第一输出晶体管M13实现,第一像素信号输出端OT1的输出信号的上拉和复位都通过第二输出晶体管M15实现,第二像素信号输出端OT2的输出信号的上拉和复位都通过第三输出晶体管M17实现,第二降噪晶体管M14对移位信号输出端CR的输出信号起辅助下拉的作用,第三降噪晶体管M16对第一像素信号输出端OT1的输出信号起辅助下拉的作用,第四降噪晶体管M18对第二像素信号输出端OT2的输出信号起辅助下拉的作用,因此可以减小第二降噪晶体管M14、第三降噪晶体管M16和第四降噪晶体管M18的体积,有利于减小电路版图的面积。
例如,在消隐时段BL,在第五阶段5,由于第一电容C1的保持作用,控制节点H仍然保持为高电平,同时,第一时钟信号CLKA为高电平信号,第三晶体管M3导通。消隐控制信号经由第三晶体管M3对第一节点Q进行充电,将第一节点Q上拉至高电位。第五晶体管M5在第一节点Q的控制下导通,第二节点QB被下拉至低电平。由于第一节点Q的电平为高电平,第一输出晶体管M13、第二输出晶体管M15和第三输出晶体管M17均导通,第一输出时钟信号CLKD经由第一输出晶体管M13和第二输出晶体管M15被分别输出至移位信号输出端CR和第一像素信号输出端OT1,第二输出时钟信号CLKE经由第三输出晶体管M17被输出至第二像素信号输出端OT2。但由于第一输出时钟信号CLKD和第二输出时钟信号CLKE均为低电平信号,即移位信号输出端CR、第一像素信号输出端OT1和第二像素信号输出端OT2均输出低电平信号。
例如,在第六阶段6,第一时钟信号CLKA变为低电平,第三晶体管M3截止,从而第一节点Q不会通过第三晶体管M3漏电。第一节点Q保持为高电平,第一输出晶体管M13、第二输出晶体管M15和第三输出晶体管M17保持导通,第一输出时钟信号CLKD变为高电平,由此移位信号输出端CR和第一像素信号输出端OT1均输出高电平信号,由于第二电容C2的自举效应,第一节点Q的电位进一步被拉高,第一输出晶体管M13、第二输出晶体管M15 和第三输出晶体管M17更加充分导通。例如,第一像素信号输出端OT1输出的信号可以用于驱动显示面板中子像素单元中的感测晶体管,以实现外部补偿。由于第二输出时钟信号CLKE输出脉冲信号,从而第二像素信号输出端OT2也输出脉冲信号。需要说明的是,在第六阶段6,第二像素信号输出端OT2输出的信号可以根据实际应用设计,本公开对此不作限制。
例如,在第七阶段7,第一输出时钟信号CLKD和第二输出时钟信号CLKE变为低电平,移位信号输出端CR和第一像素信号输出端OT1均可以通过第一输出时钟信号端CLKD放电,从而完成移位信号输出端CR和第一像素信号输出端OT1的复位;第二像素信号输出端OT2通过第二输出时钟信号端CLKE放电,从而完成第二像素信号输出端OT2的复位。此时,移位信号输出端CR、第一像素信号输出端OT1和第二像素信号输出端OT2均输出低电平信号,由于第二电容C2的自举作用,第一节点Q的电位有所降低但仍然保持高电平,第一输出晶体管M13、第二输出晶体管M15和第三输出晶体管M17仍保持导通,第一输出时钟信号端CLKD的低电平输出至移位信号输出端CR和第一像素信号输出端OT1,第二输出时钟信号端CLKE的低电平输出至第二像素信号输出端OT2,由此实现输出端OP的复位。
例如,在第八阶段8,消隐复位信号TR和第一时钟信号CLKA为高电平,第九晶体管M9导通,第二电压端VGL1的第二电压经由第九晶体管M9被写入第一节点Q,以对第一节点Q进行复位,第三晶体管M3也导通,第二电压端VGL1的第二电压经由第九晶体管M9和第三晶体管M3被写入控制节点H,由此控制节点H也被复位。这样可以使控制节点H保持为高电平的时间较短,以降低与控制节点H连接的晶体管阈值电压漂移(例如正漂)的风险,有助于提高该电路的信赖性。
需要说明的是,上述关于显示时段DS和消隐时段BL的工作过程的描述中,以移位寄存器单元包括两个像素信号输出端(即,第一像素信号输出端OT1和第二像素信号输出端OT2)为例,但不限于此,该移位寄存器单元可以仅包括一个像素信号输出端(例如,第一像素信号输出端OT1)。当该移位寄存器单元可以仅包括第一像素信号输出端OT1时,移位寄存器单元的工作过程与上述工作过程相似,只要省略关于第二像素信号输出端OT2的相关描述即可,在此不再赘述。
值得注意的是,在本公开的实施例中,例如,当各个电路实现为N型晶体 管时,术语“上拉”表示对一个节点或一个晶体管的一个电极进行充电,以使得该节点或该电极的电平的绝对值升高,从而实现相应晶体管的操作(例如导通);“下拉”表示对一个节点或一个晶体管的一个电极进行放电,以使得该节点或该电极的电平的绝对值降低,从而实现相应晶体管的操作(例如截止)。术语“工作电位”表示该节点处于高电位,从而当一个晶体管的栅极连接到该节点时,该晶体管导通;术语“非工作电位”表示该节点处于低电位,从而当一个晶体管的栅极连接到该节点时,该晶体管截止。又例如,当各个电路实现为P型晶体管时,术语“上拉”表示对一个节点或一个晶体管的一个电极进行放电,以使得该节点或该电极的电平的绝对值降低,从而实现相应晶体管的操作(例如导通);“下拉”表示对一个节点或一个晶体管的一个电极进行充电,以使得该节点或该电极的电平的绝对值升高,从而实现相应晶体管的操作(例如截止)。术语“工作电位”表示该节点处于低电位,从而当一个晶体管的栅极连接到该节点时,该晶体管导通;术语“非工作电位”表示该节点处于高电位,从而当一个晶体管的栅极连接到该节点时,该晶体管截止。
本公开至少一些实施例还提供一种栅极驱动电路。该栅极驱动电路包括本公开任一实施例所述的移位寄存器单元。该栅极驱动电路的电路结构简单,可以实现随机补偿,避免由于逐行顺序补偿造成的扫描线和面板的亮度偏差,提高显示均匀性,提升显示效果。
图9为本公开一些实施例提供的一种栅极驱动电路的示意性框图;图10A为本公开一些实施例提供的一种消隐输入电路和显示输入电路的电路结构图;图10B为本公开一些实施例提供的另一种消隐输入电路和显示输入电路的电路结构图;图10C为本公开又一些实施例提供的一种消隐输入电路和显示输入电路的电路结构图;图10D为本公开又一些实施例提供的又一种消隐输入电路和显示输入电路的电路结构图;图10E为本公开又一些实施例提供的再一种消隐输入电路和显示输入电路的电路结构图。
例如,如图9所示,该栅极驱动电路20包括多个级联的移位寄存器单元(例如,A1、A2、A3、A4等)。多个移位寄存器单元的数量不受限制,可以根据实际需求而定。例如,移位寄存器单元采用本公开任一实施例所述的移位寄存器单元10。例如,在栅极驱动电路20中,可以部分或全部移位寄存器单元采用本公开任一实施例所述的移位寄存器单元10。例如,该栅极驱动电路20可以采用与薄膜晶体管同样制程的工艺直接集成在显示装置的阵列基板上,以 实现逐行扫描驱动功能。这些移位寄存器单元的第一像素信号输出端OT1分别与多条第一栅线(例如,G11、G21、G31、G41等)一一对应连接;这些移位寄存器单元的第二像素信号输出端OT2分别与多条第二栅线(例如,G12、G22、G32、G42等)一一对应连接。
例如,每个移位寄存器单元包括显示输入信号端STU2、第一时钟信号端CLKA(即消隐输入信号端STU1)、第一补偿控制信号端OE1、第二补偿控制信号端OE2、第一输出时钟信号端CLKD、第二输出时钟信号端CLKE、显示复位信号端STD、移位信号输出端CR、第一像素信号输出端OT1和第二像素信号输出端OT2等。
例如,如图9所示,栅极驱动电路20还包括第一子时钟信号线CLK_1、第二子时钟信号线CLK_2、第三子时钟信号线CLK_3和第四子时钟信号线CLK_4。各级移位寄存器单元与上述各子时钟信号线的连接方式如下并以此类推。
例如,如图9所示,第4n 1-3级移位寄存器单元(例如,第一级移位寄存器单元A1)的第一输出时钟信号端CLKD与第一子时钟信号线CLK_1连接;第4n 1-2级移位寄存器单元(例如,第二级移位寄存器单元A2)的第一输出时钟信号端CLKD与第二子时钟信号线CLK_2连接;第4n 1-1级移位寄存器单元(例如,第三级移位寄存器单元A3)的第一输出时钟信号端CLKD与第三子时钟信号线CLK_3连接;第4n 1级移位寄存器单元(例如,第四级移位寄存器单元A4)的第一输出时钟信号端CLKD与第四子时钟信号线CLK_4连接;n 1为大于0的整数。
例如,如图9所示,栅极驱动电路20还包括第五子时钟信号线CLK_5、第六子时钟信号线CLK_6、第七子时钟信号线CLK_7、第八子时钟信号线CLK_8。各级移位寄存器单元与上述各子时钟信号线的连接方式如下并以此类推。
例如,如图9所示,第4n 1-3级移位寄存器单元(例如,第一级移位寄存器单元A1)的第二输出时钟信号端CLKE与第五子时钟信号线CLK_5连接;第4n 1-2级移位寄存器单元(例如,第二级移位寄存器单元A2)的第二输出时钟信号端CLKE与第六子时钟信号线CLK_6连接;第4n 1-1级移位寄存器单元(例如,第三级移位寄存器单元A3)的第二输出时钟信号端CLKE与第七子时钟信号线CLK_7连接;第4n 1级移位寄存器单元(例如,第四级移位寄存 器单元A4)的第二输出时钟信号端CLKE与第八子时钟信号线CLK_8连接。
例如,如图9所示,栅极驱动电路20还包括消隐输入时钟信号线CLK_9,消隐输入时钟信号线CLK_9被配置为与各级移位寄存器单元(例如,第一级移位寄存器单元A1、第二级移位寄存器单元A2、第三级移位寄存器单元A3和第四级移位寄存器单元A4)的第一时钟信号端CLKA(即消隐输入信号端STU1)连接。
例如,如图9、图10A-图10E所示,在一些示例中,每级移位寄存器单元的消隐输入信号端STU1连接第一时钟信号端CLKA,即第一时钟信号端CLKA等同于每级移位寄存器单元的消隐输入信号端STU1。除最后三级移位寄存器单元以外,第n 2级移位寄存器单元10(例如,第一级移位寄存器单元A1)的显示复位信号端STD与第n 2+3级移位寄存器单元10(例如,第四级移位寄存器单元A4)的移位信号输出端CR连接。例如,当该栅极驱动电路20仅包括四个移位寄存器单元时,第一级移位寄存器单元A1的显示复位信号端STD与第四级移位寄存器单元A4的移位信号输出端CR连接,第二级移位寄存器单元A2的显示复位信号端STD、第三级移位寄存器单元A3的显示复位信号端STD、第四级移位寄存器单元A4的显示复位信号端STD可以分别与多条单独设置复位信号线连接。除了第一级移位寄存器单元A1和第二级移位寄存器单元A2外,第n 2+2级移位寄存器单元(例如,第三级移位寄存器单元A3)的显示输入信号端STU2和第n 2级移位寄存器单元(例如,第一级移位寄存器单元A1)的移位信号输出端CR连接,n 2为大于0的整数。例如,第一级移位寄存器单元A1的显示输入信号端STU2以及第二级移位寄存器单元A2的显示输入信号端STU2均连接输入信号线STU,例如接收触发信号STV。
例如,如图9和图10A所示,每级移位寄存器单元的第一补偿控制信号端OE1接收外部随机信号,第n 2+2级移位寄存器单元(例如,第一级移位寄存器单元A1)的第二补偿控制信号端OE2连接第n 2+2级移位寄存器单元(例如,第一级移位寄存器单元A1)的移位信号输出端CR,即第n 2级移位寄存器单元的移位信号输出端输出的信号作为第n 2+2级移位寄存器单元的第二补偿控制信号。除了第一级移位寄存器单元A1和第二级移位寄存器单元A2外,第n 2+2级移位寄存器单元(例如,第三级移位寄存器单元A3)的显示输入信号端STU2和第n 2级移位寄存器单元(例如,第一级移位寄存器单元A1)的移位信号输出端CR连接,n 2为大于0的整数。
例如,如图10B所示,在一些示例中,每级移位寄存器单元的第一补偿控制信号端OE1接收外部随机信号,除了第一级移位寄存器单元A1和第二级移位寄存器单元A2外,第n 2+2级移位寄存器单元(例如,第三级移位寄存器单元A3)的第二补偿控制信号端OE2连接第n 2级移位寄存器单元(例如,第一级移位寄存器单元A1)的移位信号输出端CR,即第n 2级移位寄存器单元的移位信号输出端输出的信号作为第n 2+2级移位寄存器单元的第二补偿控制信号。第n 2+2级移位寄存器单元(例如,第三级移位寄存器单元A3)的显示输入信号端STU2和第n 2级移位寄存器单元(例如,第一级移位寄存器单元A1)的移位信号输出端CR连接,n 2为大于0的整数。
例如,如图10C所示,在一些示例中,每级移位寄存器单元的第一补偿控制信号端OE1接收外部随机信号,除了最后三级移位寄存器单元之外,第n 2+3级移位寄存器单元(例如,第四级移位寄存器单元A4)的移位信号输出端CR连接第n 2级移位寄存器单元(例如,第一级移位寄存器单元A1)的第二补偿控制信号端OE2,即第n 2+3级移位寄存器单元的移位信号输出端输出的信号作为第n 2级移位寄存器单元的第二补偿控制信号。第n 2+2级移位寄存器单元(例如,第三级移位寄存器单元A3)的显示输入信号端STU2和第n 2级移位寄存器单元(例如,第一级移位寄存器单元A1)的移位信号输出端CR连接,n 2为大于0的整数。
例如,如图10D所示,在一些示例中,每级移位寄存器单元的第二补偿控制信号端OE2接收外部随机信号,除了第一级移位寄存器单元A1和第二级移位寄存器单元A2外,第n 2+2级移位寄存器单元(例如,第三级移位寄存器单元A3)的第一补偿控制信号端OE1连接第n 2级移位寄存器单元(例如,第一级移位寄存器单元A1)的移位信号输出端CR,即第n 2级移位寄存器单元的移位信号输出端输出的信号作为第n 2+2级移位寄存器单元的第一补偿控制信号。第n 2+2级移位寄存器单元(例如,第三级移位寄存器单元A3)的显示输入信号端STU2和第n 2级移位寄存器单元(例如,第一级移位寄存器单元A1)的移位信号输出端CR连接,n 2为大于0的整数。
例如,如图10E所示,在一些示例中,除了第一级移位寄存器单元A1和第二级移位寄存器单元A2外,第n 2级移位寄存器单元(例如,第一级移位寄存器单元A1)的移位信号输出端CR连接第n 2+2级移位寄存器单元(例如,第三级移位寄存器单元A3)的第二补偿控制信号端OE2,即第n 2级移位寄存 器单元的移位信号输出端输出的信号作为所述第n 2+2级移位寄存器单元的第二补偿控制信号。第n 2级移位寄存器单元(例如,第一级移位寄存器单元A1)的移位信号输出端CR连接第n 2+2级移位寄存器单元(例如,第三级移位寄存器单元A3)的消隐控制信号端BP和显示控制信号端DP,即第n 2级移位寄存器单元的移位信号输出端输出的信号还作为第n 2+2级移位寄存器单元的消隐控制信号和显示控制信号。第n 2+2级移位寄存器单元(例如,第三级移位寄存器单元A3)的显示输入信号端STU2还和第n 2级移位寄存器单元(例如,第一级移位寄存器单元A1)的移位信号输出端CR连接,n 2为大于0的整数。
例如,如图10E所示,当第n 2级移位寄存器单元的移位信号输出端CR连接第n 2+2级移位寄存器单元的消隐控制信号端BP时,每个移位寄存器单元还可以包括第二防漏电电路,第二防漏电电路可以包括第五防漏电晶体管M4b和第六防漏电晶体管M21。第二防漏电电路被配置为在第一节点Q为高电平时,防止第一节点Q处的电荷经由第四晶体管M4a漏电。第五防漏电晶体管M4b的栅极连接到第四晶体管M4a的栅极(即,第n 2+2级移位寄存器单元的第五防漏电晶体管M4b的栅极连接到第n 2级移位寄存器单元的移位信号输出端CR),第五防漏电晶体管M4b的第一极连接到第四晶体管M4a的第二极,第五防漏电晶体管M4b的第二极连接到第一节点Q。第六防漏电晶体管M21的栅极连接到第一节点Q,第六防漏电晶体管M21的第一极连接到第六电压端VDD,第六防漏电晶体管M21的第二极连接到第五防漏电晶体管M4b的第一极。类似地,利用第二防漏电电路进行防漏电的原理与利用第一防漏电电路防漏电的原理类似,此处不再赘述。
例如,栅极驱动电路20还可以包括时序控制器T-CON,时序控制器T-CON例如配置为向各级移位寄存器单元提供上述各个时钟信号,时序控制器T-CON还可以被配置为提供触发信号和复位信号。需要说明的是,时序控制器T-CON提供的多个时钟信号彼此之间的相位关系可以根据实际需求而定。在不同的示例中,根据不同的配置,还可以提供更多的时钟信号。例如,该栅极驱动电路20还包括多条电压线,以向各级移位寄存器单元提供多个电压信号。
例如,当采用该栅极驱动电路20驱动显示面板时,可以将该栅极驱动电路20设置于显示面板的一侧。当然,还可以分别在显示面板的两侧设置该栅极驱动电路20,以实现双边驱动,本公开的实施例对栅极驱动电路20的设置方式不作限制。例如,可以在显示面板的一侧设置栅极驱动电路20以用于驱 动奇数行栅线,而在显示面板的另一侧设置栅极驱动电路20以用于驱动偶数行栅线。
图11为本公开一些实施例提供的一种栅极驱动电路的信号时序图,该信号时序图为图9中所示的栅极驱动电路20的时序,该栅极驱动电路20中的移位寄存器单元为图6A中所示的移位寄存器单元10。栅极驱动电路20的工作原理可参考本公开的实施例中对于移位寄存器单元10的相应描述,重复之处不再赘述。
需要说明的是,在图11中,Q<5>和Q<6>分别表示栅极驱动电路20中第五级和第六级移位寄存器单元中第一节点Q。OT1<5>和OT2<5>分别表示栅极驱动电路20中的第五级移位寄存器单元中第一像素信号输出端OT1和第二像素信号输出端OT2,OT1<6>和OT2<6>分别表示栅极驱动电路20中的第六级移位寄存器单元中第一像素信号输出端OT1和第二像素信号输出端OT2。MF表示第M帧,M为正整数。DS表示一帧中的显示时段,BL表示一帧中的消隐时段。需要说明的是,由于每一级移位寄存器单元中的第一像素信号输出端OT1和移位信号输出端CR的电位相同,所以在图11中未示出移位信号输出端CR。值得注意的是,图8和图11所示的信号时序图中的信号电平只是示意性的,不代表真实电平值。
例如,在显示时段DS,移位寄存器单元10向多行栅线逐行输出扫描驱动信号,直至向最后一行栅线输出扫描驱动信号后完成一帧的显示。例如,在第M帧中,第n行子像素单元需要进行检测补偿,第n行子像素单元与第n级移位寄存器单元10的输出端连接,从而在消隐时段BL,第n级移位寄存器单元10的第一像素信号输出端OT1输出高电平信号,以对第n行子像素单元进行检测。
例如,如图9、图10A和图11所示,若在第M帧内,需要对第五行子像素单元进行检测,第五行子像素单元与第五级移位寄存器单元对应。在第M帧内,外部控制电路将第五级移位寄存器单元的移位信号输出端CR输出的信号输出至每级移位寄存器单元的第一补偿控制信号端OE1,即外部控制电路提供的第一补偿控制信号与第五级移位寄存器单元的移位信号输出端CR输出的信号的波形脉冲宽度相同。由于在图9和图10A所示的示例中,第n 2级移位寄存器单元的第二补偿控制信号端OE2连接第n 2级移位寄存器单元的移位信号输出端CR,由此,在显示时段DS的第2阶段,当第五级移位寄存器单元的移 位信号输出端CR输出高电平信号时,如图6A所示,第五级移位寄存器单元的充电子电路110中的第一晶体管M1和第二晶体管M2均导通,由此,第六电压端VDD提供的第六电压被写入第五级移位寄存器单元的控制节点H,以将第五级移位寄存器单元的控制节点H拉高至高电平。
例如,如图11所示,第一子时钟信号CLK_1、第二子时钟信号CLK_2、第三子时钟信号CLK_3和第四子时钟信号CLK_4在一帧的显示时段内的波形依次重叠有效脉宽的50%,第一至第四级移位寄存器单元A1-A4的第一像素信号输出端OT1的输出信号OT1<1>、OT1<2>、OT1<3>和OT1<4>在一帧的显示时段内的波形依次重叠有效脉宽的50%。第五子时钟信号线CLK_5、第六子时钟信号线CLK_6、第七子时钟信号线CLK_7、第八子时钟信号线CLK_8在一帧的显示时段内的波形也依次重叠有效脉宽的50%,第一至第四级移位寄存器单元A1-A4的第二像素信号输出端OT2的输出信号OT2<1>、OT2<2>、OT2<3>和OT2<4>在一帧的显示时段内的波形也依次重叠有效脉宽的50%。该栅极驱动电路20在显示时段内的输出信号的波形有重叠,因此可以实现预充电功能,提高充电效率,可缩短像素电路的整体充电时间(即一帧中的显示时段的时间),有利于实现高刷新率。此时,显示面板上的位于奇数行的像素和位于偶数行的像素可以分别连接不同的数据线,从而在相邻两行像素单元同时被充电时,相邻两行像素单元可以分别接收对应的数据信号。
需要说明的是,本公开的各实施例中,栅极驱动电路20不局限于图9中描述的级联方式,可以为任意适用的级联方式。当级联方式或时钟信号改变时,第一至第四级移位寄存器单元A1-A4的第一像素信号输出端OT1的输出信号OT1<1>、OT1<2>、OT1<3>和OT1<4>在显示时段内的波形重叠部分也会相应变化,第一至第四级移位寄存器单元A1-A4的第二像素信号输出端OT2的输出信号OT2<1>、OT2<2>、OT2<3>和OT2<4>在显示时段内的波形重叠部分也会相应变化,例如重叠33%或0%(即不重叠),以满足多种应用需求。
例如,如图11所示,由于第五级移位寄存器单元的第一像素信号输出端OT1输出的信号的波形和第六级移位寄存器单元的第一像素信号输出端OT1输出的信号的波形有重叠,由此,在第二阶段2,在对第五级移位寄存器单元的控制节点H进行充电的过程中,当第六级移位寄存器单元的移位信号输出端CR输出高电平信号时,第六级移位寄存器单元的充电子电路110中的第一晶体管M1和第二晶体管M2也均导通,由此,第六电压端VDD提供的第六电 压被写入第六级移位寄存器单元的控制节点H,以将第六级移位寄存器单元的控制节点H拉高至高电平。在第一补偿控制信号为低电平时,第五级移位寄存器单元的控制节点H和第六级移位寄存器单元的控制节点H的电位可以能够一直保持至消隐时段BL。
例如,如图6A和图11所示,在消隐时段BL的第5阶段,第一时钟信号CLKA为高电平信号,从而所有级移位寄存器单元的第三晶体管M3导通,由于第五级移位寄存器单元的控制节点H和第六级移位寄存器单元的控制节点H均为高电平,由此,第五级移位寄存器单元的第一节点Q和第六级移位寄存器单元的第一节点Q被充电至高电平。
例如,在消隐时段BL的第6阶段,与第五级移位寄存器单元连接的第一子时钟信号CLK_1(用于提供第一输出时钟信号线CLKD)提供高电平信号,与第五级移位寄存器单元连接的第五子时钟信号线CLK_5(用于提供第二输出时钟信号CLKE)提供脉冲信号,由此,第五级移位寄存器单元的第一像素信号输出端OT1输出高电平信号,第五级移位寄存器单元的第二像素信号输出端OT2输出脉冲信号。由此,在第M帧时段内,可以实现对第五行子像素单元进行检测。
而与第六级移位寄存器单元连接的第二子时钟信号线CLK_2(用于提供第一输出时钟信号CLKD)提供低电平信号,与第六级移位寄存器单元连接的第六子时钟信号线CLK_6(用于提供第二输出时钟信号CLKE)也提供低电平信号,由此第六级移位寄存器单元的第一像素信号输出端OT1和第二像素信号输出端OT2均输出低电平信号。由此,在第M帧时段内,不会对第六行子像素单元(其与第六级移位寄存器单元对应)进行检测。
需要说明的是,在进行随机检测补偿时,若需要对第W行子像素进行检测,第W行子像素对应第W级移位寄存器单元,则每级移位寄存器单元的第一补偿控制信号可以根据第W级移位寄存器单元的第二补偿控制信号而变化,以保证第W级移位寄存器单元的第二晶体管M2导通时,第W级移位寄存器单元的第一晶体管M1也同时导通。例如,W为正整数。例如,在图10B所示的示例中,当需要对第五行子像素单元进行检测,由于第n 2+2级移位寄存器单元的第二补偿控制信号端OE2连接第n 2级移位寄存器单元的移位信号输出端CR,则外部控制电路将第三级移位寄存器单元的移位信号输出端CR输出的信号输出至每级移位寄存器单元的第一补偿控制信号端OE1。又例如,在图 10C所示的示例中,当需要对第五行子像素单元进行检测,由于第n 2+3级移位寄存器单元的移位信号输出端CR连接第n 2级移位寄存器单元的第二补偿控制信号端OE2,则外部控制电路将第八级移位寄存器单元的移位信号输出端CR输出的信号输出至每级移位寄存器单元的第一补偿控制信号端OE1。
例如,显示时段DS和消隐时段BL中其他阶段的相关描述可以参考上述移位寄存器单元中对显示时段DS和消隐时段BL中其他阶段的详细说明,重复之处在此不再赘述。
图12为本公开一些实施例提供的一种显示装置的示意性框图。例如,如图12所示,显示装置30包括栅极驱动电路20,该栅极驱动电路20包括本公开任一实施例所述的栅极驱动电路。
显示装置30的技术效果可以参考上述实施例中关于移位寄存器单元10和栅极驱动电路20的相应描述,这里不再赘述。
例如,本实施例中的显示装置30可以为:液晶面板、液晶电视、显示器、OLED面板、OLED电视、OLED显示器、电子纸显示装置、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
例如,在一个示例中,显示装置30包括显示面板3000、栅极驱动器3010、定时控制器3020和数据驱动器3030。显示面板3000包括多个像素单元P,多个像素单元P由多条栅线GL和多条数据线DL交叉限定。栅极驱动器3010用于驱动多条栅线GL;数据驱动器3030用于驱动多条数据线DL;定时控制器3020用于处理从显示装置30外部输入的图像数据RGB,向数据驱动器3030提供处理的图像数据RGB以及向栅极驱动器3010和数据驱动器3030输出扫描控制信号GCS和数据控制信号DCS,以对栅极驱动器3010和数据驱动器3030进行控制。
例如,栅极驱动器3010包括上述任一实施例中提供的栅极驱动电路20。栅极驱动电路20中的多个移位寄存器单元10的第一像素信号输出端OT1与多条栅线GL对应连接。栅极驱动电路20中的各级移位寄存器单元10的第一像素信号输出端OT1依序输出扫描驱动信号到多条栅线GL,以使显示面板3000中的多行像素单元P在显示时段实现逐行扫描,并在消隐时段实现随机补偿检测。例如,栅极驱动器3010可以实现为半导体芯片,也可以集成在显示面板3000中以构成GOA电路。
例如,数据驱动器3030向多条数据线DL提供转换的数据信号。例如,数 据驱动器3030可以实现为半导体芯片。
例如,定时控制器3020对外部输入的图像数据RGB进行处理以匹配显示面板3000的大小和分辨率,然后向数据驱动器3030提供处理后的图像数据。定时控制器3020使用从显示装置30外部输入的同步信号(例如点时钟DCLK、数据使能信号DE、水平同步信号Hsync以及垂直同步信号Vsync)产生多条扫描控制信号GCS和多条数据控制信号DCS。定时控制器3020分别向栅极驱动器3010和数据驱动器3030提供产生的扫描控制信号GCS和数据控制信号DCS,以用于栅极驱动器3010和数据驱动器3030的控制。
需要说明的是,显示装置30还可以包括其他部件,例如信号解码电路、电压转换电路等,这些部件例如可以采用已有的常规部件,这里不再详述。
本公开至少一些实施例还提供一种移位寄存器单元的驱动方法,可以用于驱动本公开任一实施例提供的移位寄存器单元。
图13为本公开一些实施例提供的一种移位寄存器单元的驱动方法的流程图。驱动方法可以包括用于一帧的显示时段和消隐时段。如图13所示,驱动方法可以包括如下操作:
在一帧的显示时段,包括:
S10:第一输入阶段,响应于显示输入信号,通过显示输入电路将显示控制信号输入到第一节点;
S11:第一输出阶段,在第一节点的电平的控制下,通过输出电路将复合输出信号输出至输出端;
S12:充电阶段,响应于第一补偿控制信号和第二补偿控制信号,通过充电子电路将消隐控制信号输入到控制节点;
在一帧的消隐时段,包括:
S20:第二输入阶段,响应于消隐输入信号,通过消隐输入电路将消隐控制信号输入到第一节点;
S21:第二输出阶段,在第一节点的电平的控制下,通过输出电路将复合输出信号输出至输出端。
例如,在一个示例中,在移位寄存器单元10包括第三控制电路700的情形下,步骤S10还包括:响应于第二控制信号通过第三控制电路对第二节点的电平进行控制,以将第二节点的电平下拉至非工作电位。
例如,在一些示例中,输出端包括移位信号输出端和第一像素信号输出端, 输出电路包括第一输出晶体管和第二输出晶体管。步骤S11可以包括:在第一节点的电平的控制下,经由第一输出晶体管将显示移位信号传输至移位信号输出端,经由第二输出晶体管将显示输出信号传输至第一像素信号输出端。复合输出信号包括显示输出信号和显示移位信号。例如,显示输出信号可以用于驱动显示面板中的子像素单元进行显示。
需要说明的是,步骤S11和步骤S12并没有先后顺序,步骤S12可以在步骤S11之前执行;步骤S12可以在步骤S11之后执行;步骤S12和步骤S11可以同时执行。
例如,在另一个示例中,在移位寄存器单元10包括第二控制电路600的情形下,步骤S20还包括:响应于第一控制信号通过第二控制电路对第二节点的电平进行控制,以将第二节点的电平下拉至非工作电位。
例如,在一些示例中,步骤S21可以包括:在第一节点的电平的控制下,经由第一输出晶体管将消隐移位信号传输至移位信号输出端,经由第二输出晶体管将消隐输出信号传输至第一像素信号输出端。复合输出信号包括消隐输出信号和消隐移位信号。例如,消隐输出信号可以用于驱动显示面板中的子像素单元进行外部补偿。
需要说明的是,在上述移位寄存器单元的实施例中,第一输出信号可以包括显示移位信号和消隐移位信号,第二输出信号包括显示输出信号和消隐输出信号。如图8所示,显示输出信号可以为在显示时段由第一像素信号输出端输出的信号,显示移位信号可以为在显示时段由移位信号输出端输出的信号,显示移位信号和显示输出信号可以相同,显示输出信号例如可以为脉冲信号;消隐输出信号可以为在消隐时段由第一像素信号输出端输出的信号,消隐移位信号可以为在消隐时段由移位信号输出端输出的信号,消隐移位信号和消隐输出信号也可以相同,消隐输出信号例如可以为高电平信号。
例如,在显示时段,在步骤S12之后,驱动方法还可以包括:显示复位阶段,在显示复位信号的控制下,对第一节点进行复位;在第二节点的电平的控制下,通过降噪电路对第一节点、移位信号输出端、第一像素信号输出端和第二像素信号输出端进行降噪。
例如,在消隐时段,在步骤S21之后,驱动方法还可以包括:消隐复位阶段,在消隐复位信号和消隐输入信号的控制下,对第一节点和控制节点进行复位。
需要说明的是,关于该驱动方法的详细描述以及技术效果可以参考本公开的实施例中对于移位寄存器单元10和栅极驱动电路20的相应描述,这里不再赘述。
对于本公开,还有以下几点需要说明:
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构,其他结构可参考通常设计。
(2)在不冲突的情况下,本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅为本公开的具体实施方式,但本公开的保护范围并不局限于此,本公开的保护范围应以所述权利要求的保护范围为准。

Claims (22)

  1. 一种移位寄存器单元,包括:消隐输入电路、显示输入电路、输出电路、控制节点和第一节点;
    其中,所述消隐输入电路被配置为响应于消隐输入信号在消隐时段将消隐控制信号输入到所述第一节点,所述消隐输入电路包括充电子电路,所述充电子电路被配置为响应于第一补偿控制信号和第二补偿控制信号,将所述消隐控制信号输入到所述控制节点;
    所述显示输入电路被配置为响应于显示输入信号在显示时段将显示控制信号输入到所述第一节点;
    所述输出电路被配置为在所述第一节点的电平的控制下,将复合输出信号输出至输出端。
  2. 根据权利要求1所述的移位寄存器单元,其中,所述第一补偿控制信号和所述第二补偿控制信号其中之一为随机信号。
  3. 根据权利要求1或2所述的移位寄存器单元,其中,所述充电子电路包括第一晶体管和第二晶体管,
    所述第一晶体管的栅极被配置为接收所述第一补偿控制信号,所述第一晶体管的第一极被配置为与消隐控制信号端连接以接收所述消隐控制信号,所述第一晶体管的第二极被配置为与所述第二晶体管的第一极连接,
    所述第二晶体管的第二极被配置为与所述控制节点连接,所述第二晶体管的栅极被配置为接收所述第二补偿控制信号。
  4. 根据权利要求1-3任一项所述的移位寄存器单元,其中,所述消隐输入电路还包括:
    存储子电路,被配置为存储所述充电子电路输入的所述消隐控制信号;
    隔离子电路,被配置为在所述消隐输入信号的控制下,将所述消隐控制信号输入到所述第一节点。
  5. 根据权利要求4所述的移位寄存器单元,其中,所述存储子电路包括第一电容,所述第一电容的第一极被配置为和所述控制节点连接,所述第一电容的第二极被配置为与第一电压端连接以接收第一电压;
    所述隔离子电路包括第三晶体管,所述第三晶体管的栅极被配置为与消隐输入信号端连接以接收所述消隐输入信号,所述第三晶体管的第一极被配置为 与所述控制节点连接,所述第三晶体管的第二极被配置为与所述第一节点连接。
  6. 根据权利要求1-5任一项所述的移位寄存器单元,其中,所述显示输入电路包括第四晶体管,
    所述第四晶体管的栅极与显示输入信号端连接以接收所述显示输入信号,所述第四晶体管的第一极与显示控制信号端连接以接收所述显示控制信号,所述第四晶体管的第二极与所述第一节点连接。
  7. 根据权利要求1-6任一项所述的移位寄存器单元,其中,所述输出端包括移位信号输出端和第一像素信号输出端,
    所述输出电路包括第一输出晶体管、第二输出晶体管和第二电容;
    所述第一输出晶体管的栅极与所述第一节点连接,所述第一输出晶体管的第一极与第一输出时钟信号端连接以接收第一输出时钟信号,所述第一输出晶体管的第二极与所述移位信号输出端连接;
    所述第二输出晶体管的栅极和所述第一节点连接,所述第二输出晶体管的第一极与所述第一输出时钟信号端连接以接收所述第一输出时钟信号,所述第二输出晶体管的第二极与所述第一像素信号输出端连接;
    所述第二电容的第一极和所述第一节点连接,所述第二电容的第二极与所述第一输出晶体管的第二极连接;
    所述第一输出时钟信号经由所述第一输出晶体管传输至所述移位信号输出端以作为第一输出信号,所述第一输出时钟信号经由所述第二输出晶体管传输至所述第一像素信号输出端以作为第二输出信号,所述复合输出信号包括所述第一输出信号和所述第二输出信号。
  8. 根据权利要求7所述的移位寄存器单元,其中,所述输出端还包括第二像素信号输出端,所述输出电路还包括第三输出晶体管,
    所述第三输出晶体管的栅极与所述第一节点连接,所述第三输出晶体管的第一极与第二输出时钟信号端连接以接收第二输出时钟信号,所述第三输出晶体管的第二极与所述第二像素信号输出端连接,
    所述第二输出时钟信号经由所述第三输出晶体管传输至所述第二像素信号输出端以作为第三输出信号,所述复合输出信号还包括所述第三输出信号。
  9. 根据权利要求1-8任一项所述的移位寄存器单元,其中,所述消隐控制信号和所述显示控制信号相同。
  10. 根据权利要求1-9任一项所述的移位寄存器单元,还包括:降噪电路、 第一控制电路和第二节点,
    其中,所述降噪电路被配置为在所述第二节点的电平的控制下,对所述第一节点和所述输出端进行降噪;
    所述第一控制电路配置为在所述第一节点的电平的控制下,对所述第二节点的电平进行控制。
  11. 根据权利要求10所述的移位寄存器单元,其中,所述第一控制电路包括第五晶体管、第六晶体管和第七晶体管;
    所述第五晶体管的栅极与所述第一节点连接,所述第五晶体管的第一极与所述第二节点连接,所述第五晶体管的第二极与第二电压端连接以接收第二电压;
    所述第六晶体管的栅极和第一极连接且被配置为与第三电压端连接以接收第三电压,所述第六晶体管的第二极与所述第二节点连接;
    所述第七晶体管的栅极与第一极连接且被配置为与第四电压端连接以接收第四电压,所述第七晶体管的第二极与所述第二节点连接。
  12. 根据权利要求10或11所述的移位寄存器单元,其中,所述输出端包括移位信号输出端和第一像素信号输出端,
    所述降噪电路包括第一降噪晶体管、第二降噪晶体管和第三降噪晶体管;
    所述第一降噪晶体管的栅极与所述第二节点连接,所述第一降噪晶体管的第一极与所述第一节点连接,所述第一降噪晶体管的第二极与第二电压端连接以接收第二电压;
    所述第二降噪晶体管的栅极与所述第二节点连接,所述第二降噪晶体管的第一极与所述移位信号输出端连接,所述第二降噪晶体管的第二极与所述第二电压端连接以接收所述第二电压;
    所述第三降噪晶体管的栅极与所述第二节点连接,所述第三降噪晶体管的第一极与所述第一像素信号输出端连接,所述第三降噪晶体管的第二极与第五电压端连接以接收第五电压。
  13. 根据权利要求12所述的移位寄存器单元,其中,所述输出端还包括第二像素信号输出端,所述降噪电路还包括第四降噪晶体管;
    所述第四降噪晶体管的栅极与所述第二节点连接,所述第四降噪晶体管的第一极与所述第二像素信号输出端连接,所述第四降噪晶体管的第二极与所述第五电压端连接以接收所述第五电压。
  14. 根据权利要求10-13任一项所述的移位寄存器单元,还包括第二控制电路;其中,
    所述第二控制电路被配置为响应于第一控制信号对所述第二节点的电平进行控制。
  15. 根据权利要求1-14任一项所述的移位寄存器单元,还包括消隐复位电路和显示复位电路,
    其中,所述消隐复位电路被配置为响应于消隐复位信号对所述第一节点进行复位;
    所述显示复位电路被配置为响应于显示复位信号对所述第一节点进行复位。
  16. 一种栅极驱动电路,包括多个级联的如权利要求1-15任一项所述的移位寄存器单元。
  17. 根据权利要求16所述的栅极驱动电路,还包括第一子时钟信号线、第二子时钟信号线、第三子时钟信号线和第四子时钟信号线;其中,在所述移位寄存器单元包括第一输出时钟信号端的情形下,
    第4n 1-3级移位寄存器单元的第一输出时钟信号端与所述第一子时钟信号线连接;
    第4n 1-2级移位寄存器单元的第一输出时钟信号端与所述第二子时钟信号线连接;
    第4n 1-1级移位寄存器单元的第一输出时钟信号端与所述第三子时钟信号线连接;
    第4n 1级移位寄存器单元的第一输出时钟信号端与所述第四子时钟信号线连接;
    n 1为大于0的整数。
  18. 根据权利要求16或17所述的栅极驱动电路,其中,在所述移位寄存器单元包括显示输入信号端和移位信号输出端的情形下,
    第n 2+2级移位寄存器单元的显示输入信号端和第n 2级移位寄存器单元的移位信号输出端连接,n 2为大于0的整数。
  19. 根据权利要求18所述的栅极驱动电路,其中,
    所述第n 2级移位寄存器单元的移位信号输出端输出的信号作为所述第n 2+2级移位寄存器单元的第二补偿控制信号;或者
    所述第n 2+3级移位寄存器单元的移位信号输出端输出的信号作为所述第n 2级移位寄存器单元的第二补偿控制信号;或者
    所述第n 2级移位寄存器单元的移位信号输出端输出的信号作为所述第n 2级移位寄存器单元的第二补偿控制信号;或者
    所述第n 2级移位寄存器单元的移位信号输出端输出的信号作为所述第n 2+2级移位寄存器单元的第二补偿控制信号,所述第n 2级移位寄存器单元的移位信号输出端输出的信号还作为所述第n 2+2级移位寄存器单元的消隐控制信号。
  20. 根据权利要求16-19任一项所述的栅极驱动电路,还包括消隐输入时钟信号线;
    其中,在所述移位寄存器单元包括消隐输入信号端的情形下,每级移位寄存器单元的消隐输入信号端与所述消隐输入时钟信号线连接。
  21. 一种显示装置,包括如权利要求16-20任一项所述的栅极驱动电路。
  22. 一种如权利要求1-15任一项所述的移位寄存器单元的驱动方法,包括用于一帧的显示时段和消隐时段:
    所述显示时段,包括:
    第一输入阶段,响应于所述显示输入信号,通过所述显示输入电路将所述显示控制信号输入到所述第一节点;
    第一输出阶段,在所述第一节点的电平的控制下,通过所述输出电路将所述复合输出信号输出至所述输出端;
    充电阶段,响应于所述第一补偿控制信号和所述第二补偿控制信号,通过所述充电子电路将所述消隐控制信号输入到所述控制节点;
    所述消隐时段,包括:
    第二输入阶段,响应于所述消隐输入信号,通过所述消隐输入电路将所述消隐控制信号输入到所述第一节点;
    第二输出阶段,在所述第一节点的电平的控制下,通过所述输出电路将所述复合输出信号输出至所述输出端。
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