WO2020007054A1 - 移位寄存器单元、栅极驱动电路及其驱动方法、显示装置 - Google Patents

移位寄存器单元、栅极驱动电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2020007054A1
WO2020007054A1 PCT/CN2019/076345 CN2019076345W WO2020007054A1 WO 2020007054 A1 WO2020007054 A1 WO 2020007054A1 CN 2019076345 W CN2019076345 W CN 2019076345W WO 2020007054 A1 WO2020007054 A1 WO 2020007054A1
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Prior art keywords
transistor
output
shift register
circuit
sub
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PCT/CN2019/076345
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English (en)
French (fr)
Inventor
袁志东
李永谦
冯雪欢
袁粲
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US16/500,625 priority Critical patent/US11398179B2/en
Publication of WO2020007054A1 publication Critical patent/WO2020007054A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels

Definitions

  • Embodiments of the present disclosure relate to a shift register unit, a gate driving circuit and a driving method thereof, and a display device.
  • a pixel array of a liquid crystal display panel or an organic light emitting diode (OLED) display panel generally includes a plurality of rows of gate lines and a plurality of columns of data lines interlaced therewith.
  • the gate line can be driven by a bound integrated driving circuit.
  • the gate line driving circuit can also be directly integrated on the thin film transistor array substrate to form a GOA (Gate Driver On Array) to drive the gate lines. .
  • a GOA composed of multiple cascaded shift register units can be used to provide switching voltage signals for multiple rows of gate lines of a pixel array, thereby controlling, for example, the multiple rows of gate lines to be sequentially turned on, and simultaneously from the data lines to the pixel array
  • the pixel units of the corresponding row in the center provide data signals to form the gray voltages required for each gray level of the display image at each pixel unit, and then display a frame of image.
  • Current display panels increasingly use GOA technology to drive grid lines. GOA technology helps to realize the narrow bezel design of the display panel and can reduce the production cost of the display panel.
  • At least one embodiment of the present disclosure provides a shift register unit including a first sub-shift register, a second sub-shift register, and an output control circuit.
  • the first sub-shift register includes a first output terminal and is configured to output a first clock signal under the control of the level of a first control node;
  • the second sub-shift register includes a second output and is configured to Under the control of the level of the second control node, the second output terminal outputs a display output signal in a display stage and a random output signal in an interval stage;
  • the output control circuit and the first sub-shift register and The second control node is connected and configured to control a level of the second control node under the control of an output control signal.
  • the shift register unit provided by an embodiment of the present disclosure further includes a composite output circuit and a third output terminal.
  • the composite output circuit is connected to the output control circuit, the second control node, and the third output terminal, and is configured to make the third output under the control of the level of the second control node.
  • the terminal outputs the display output signal in the display phase, and outputs the random output signal in the interval phase.
  • the output control signal includes a level of the first control node and the first clock signal
  • the output control circuit includes a first transistor and a first Two transistors.
  • the gate of the first transistor is connected to the first control node, the first pole of the first transistor is connected to a first clock signal terminal to receive the first clock signal, and the second of the first transistor is Electrode is connected to the gate of the second transistor; the first electrode of the second transistor is connected to a second clock signal terminal to receive a second clock signal, or the first electrode of the second transistor and the second transistor are connected
  • the gate of the transistor is connected, and the second pole of the second transistor is connected to the second control node of the second sub-shift register.
  • the output control circuit further includes: a third transistor, wherein a gate of the third transistor is connected to a third control node, and the third transistor The first pole of the third transistor is connected to the gate of the second transistor, and the second pole of the third transistor is connected to the first voltage terminal to receive the first voltage.
  • the output control signal includes the first clock signal output from the first output terminal
  • the output control circuit includes a first transistor.
  • the gate of the first transistor is connected to the first output terminal of the first sub-shift register, and the first pole of the first transistor is connected to a second clock signal terminal to receive a second clock signal, so The second pole of the first transistor is connected to the second control node.
  • the composite output circuit includes a fourth transistor.
  • a gate of the fourth transistor is connected to the second control node, a first pole of the fourth transistor is connected to a third clock signal terminal to receive a third clock signal, and a second pole of the fourth transistor is connected to The third output terminal is connected; wherein the third clock signal includes the display output signal and the random output signal.
  • the composite output circuit further includes a fifth transistor.
  • a gate of the fifth transistor is connected to a fourth control node, a first pole of the fifth transistor is connected to the third output terminal, and a second pole of the fifth transistor is connected to a first voltage terminal to receive First voltage.
  • the first sub-shift register includes a first input circuit, a first control node reset circuit, and a first output circuit.
  • the first input circuit is configured to charge the first control node in response to a first input signal;
  • the first control node reset circuit is configured to reset the first control node in response to a first reset signal;
  • the first output circuit is configured to output the first clock signal to the first output terminal under the control of the level of the first control node.
  • the first sub-shift register further includes a first inverter circuit, a first control node noise reduction circuit, and a first output noise reduction circuit.
  • the first inverter circuit is configured to control the level of a third control node under the control of the level of the first control node;
  • the first control node noise reduction circuit is configured to control the level of the third control node Perform noise reduction on the first control node under the control of the level of the node;
  • the first output noise reduction circuit is configured to control the first output terminal under the control of the level of the third control node Perform noise reduction.
  • the first sub-shift register further includes a first leakage prevention circuit.
  • the first leakage prevention circuit is configured to maintain a high potential of the first control node under the control of the first clock signal output from the first output terminal.
  • the first leakage prevention circuit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor.
  • a gate of the eleventh transistor is connected to a first input terminal to receive the first input signal, a first pole of the eleventh transistor is connected to a second pole of the fourteenth transistor, and the first The second pole of the eleven transistor is connected to the first control node;
  • the gate of the twelfth transistor is connected to a first reset terminal to receive the first reset signal, and the first pole of the twelfth transistor Connected to the second pole of the fourteenth transistor, the second pole of the twelfth transistor is connected to a first voltage terminal to receive a first voltage;
  • the gate of the thirteenth transistor and the third control Node connection the first pole of the thirteenth transistor is connected to the second pole of the fourteenth transistor, the second pole of the thirteenth transistor is connected to the first voltage terminal to receive the first voltage;
  • the second sub-shift register includes a second input circuit, a second control node reset circuit, and a second output circuit.
  • the second input circuit is configured to charge the second control node in response to a second input signal;
  • the second control node reset circuit is configured to reset the second control node in response to a second reset signal;
  • the second output circuit is configured to output a third clock signal to the second output terminal under the control of the level of the second control node; wherein the third clock signal includes the display output signal And the random output signal.
  • the second sub-shift register includes a second inverter circuit, a second control node noise reduction circuit, and a second output noise reduction circuit.
  • the second inverter circuit is configured to control the level of the fourth control node under the control of the level of the second control node;
  • the second control node noise reduction circuit is configured to control the level of the fourth control node Perform noise reduction on the second control node under the control of the level of the node;
  • the second output noise reduction circuit is configured to control the second output terminal under the control of the level of the fourth control node Perform noise reduction.
  • the second sub-shift register further includes a second leakage prevention circuit.
  • the second leakage prevention circuit is configured to maintain a high potential of the second control node under the control of the third clock signal output from the second output terminal.
  • the second leakage prevention circuit includes a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, and a twenty-ninth transistor.
  • a gate of the twenty-sixth transistor is connected to a second input terminal to receive the second input signal, a first pole of the twenty-sixth transistor is connected to a second pole of the twenty-ninth transistor, The second pole of the twenty-sixth transistor is connected to the second control node; the gate of the twenty-seventh transistor is connected to a second reset terminal to receive the second reset signal, and the twentieth
  • the first pole of the seventh transistor is connected to the second pole of the twenty-ninth transistor, and the second pole of the twenty-seventh transistor is connected to the first voltage terminal to receive the first voltage; the twenty-eighth transistor
  • the gate of is connected to the fourth control node, the first pole of the twenty-eighth transistor is connected to the second pole of the twenty-ninth transistor,
  • the shift register unit provided by an embodiment of the present disclosure further includes a total reset circuit, wherein the total reset circuit is configured to reset the second control node under the control of the third reset signal.
  • the total reset circuit includes a thirtieth transistor.
  • the gate of the thirtieth transistor is connected to a third reset terminal to receive the third reset signal
  • the first pole of the thirtieth transistor is connected to a first voltage terminal to receive a first voltage
  • the third A second pole of the ten transistors is connected to the second control node.
  • At least one embodiment of the present disclosure further provides a gate driving circuit, which includes a plurality of cascaded shift register units provided by any one of the embodiments of the present disclosure.
  • the output control circuit is connected to the first sub-shift register and The second sub-shift register is electrically connected; except for the first sub-shift register of the first stage, the first input end of the first sub-shift register of the other stages and the first input of the first sub-shift register of the previous stage
  • the output end is connected; except for the first sub-shift register of the last stage, the first reset end of the first sub-shift register of the other stages is connected to the first output end of the first sub-shift register of the next stage;
  • the second input end of the second sub-shift register of the remaining stages is connected to the second output of the second sub-shift register of the previous stage;
  • the second reset terminal of the second sub-shift register of the other stages is connected to the second output terminal of the second sub-shift register of the next stage.
  • a display device provided by an embodiment of the present disclosure further includes a display panel including a plurality of sub-pixel units arranged in an array, the array including N rows, and the gate driving circuit including N cascaded A shift register unit, and the second output ends of the N cascaded shift register units are connected one-to-one with the N-row sub-pixel units, respectively, so as to step through the N-row sub-pixel units one by one in the display stage.
  • the line output displays an output signal, and in the interval stage, a random output signal is output to one of the N rows of sub-pixel units, where N is an integer greater than 1.
  • At least one embodiment of the present disclosure also provides a display device including a gate driving circuit provided by any one of the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure also provides a driving method of a gate driving circuit, including: during a display phase, a second output terminal of the second sub-shift register outputs the display output signal; during an interval phase, the The second output terminal of the second sub-shift register outputs the random output signal.
  • the driving method further includes: in a display stage, the third output terminal outputs the display output signal; In the interval phase, the third output terminal outputs the random output signal.
  • FIG. 1A is a schematic diagram of a pixel circuit
  • FIG. 1B is a signal timing diagram of a pixel circuit during operation
  • FIG. 2 is a schematic diagram of a shift register unit provided by some embodiments of the present disclosure.
  • FIG. 3 is a schematic diagram of another shift register unit provided by some embodiments of the present disclosure.
  • 4A is a schematic diagram of a first sub-shift register provided by some embodiments of the present disclosure.
  • 4B is a schematic diagram of another first sub-shift register provided by some embodiments of the present disclosure.
  • 4C is a schematic circuit diagram of a specific implementation example of the first sub-shift register shown in FIG. 4A;
  • 4D is a schematic circuit diagram of a specific implementation example of the first sub-shift register shown in FIG. 4B;
  • 5A is a schematic diagram of a second sub-shift register provided by some embodiments of the present disclosure.
  • 5B is a schematic diagram of another second sub-shift register provided by some embodiments of the present disclosure.
  • 5C is a circuit diagram of a specific implementation example of the second sub-shift register shown in FIG. 5A;
  • 5D is a schematic circuit diagram of a specific implementation example of the second sub-shift register shown in FIG. 5B;
  • FIG. 6 is a schematic diagram of still another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 7A is a circuit diagram of a specific implementation example of the shift register unit shown in FIG. 6;
  • FIG. 7B is a schematic circuit diagram of another specific implementation example of the shift register unit shown in FIG. 6;
  • FIG. 7C is a schematic circuit diagram of another specific implementation example of the shift register unit shown in FIG. 6; FIG.
  • 7D is a schematic circuit diagram of a specific implementation example of the shift register unit shown in FIG. 3;
  • 7E is a schematic circuit diagram of another specific implementation example of the shift register unit shown in FIG. 3;
  • FIG. 8 is a schematic diagram of a gate driving circuit provided by some embodiments of the present disclosure.
  • FIG. 9 is a timing diagram of signals when the gate driving circuit shown in FIG. 8 is operating.
  • FIG. 10 is a schematic diagram of a display device provided by some embodiments of the present disclosure.
  • the pixel circuit in an OLED display device generally adopts a matrix driving method, and is divided into an active matrix (Active Matrix) drive and a passive matrix (Passive Matrix) drive according to whether a switching element is introduced in each pixel unit.
  • AMOLED integrates a set of thin film transistors and storage capacitors in the pixel circuit of each pixel. By driving and controlling the thin film transistors and storage capacitors, the control of the current flowing through the OLED is achieved, so that the OLED emits light as required.
  • the basic pixel circuit used in the AMOLED display device is usually a 2T1C pixel circuit, that is, two thin-film transistors (TFTs) and a storage capacitor Cst are used to realize the function of driving the OLED to emit light.
  • FIG. 1A shows a schematic diagram of an externally compensated pixel circuit.
  • the pixel circuit includes a switching transistor T1, a driving transistor T3, a storage capacitor Cst, a sensing transistor T2, and an organic electroluminescence (EL) device (ie, an organic light emitting diode).
  • the sensing transistor T2 may implement a compensation function.
  • the gate of the switching transistor T1 is connected to the scanning line to receive the scanning signal G1; for example, the source of the switching transistor T1 is connected to the data line to receive the data signal Vdata; the drain of the switching transistor T1 is connected to the driving transistor T3.
  • the drain of the driving transistor T3 is connected to the first voltage terminal to receive the first voltage VDD (high voltage), the source of the driving transistor T3 is connected to the positive terminal of the EL device; one end of the storage capacitor Cst is connected to the switching transistor T1 The drain and the gate of the driving transistor T3 are connected at the other end to the source of the driving transistor T3; the negative terminal of the EL device is connected to the second voltage terminal to receive a second voltage Vss (a low voltage, such as a ground voltage).
  • the data signal Vdata input by the data driving circuit through the data line can charge the storage capacitor Cst through the switching transistor T1, so that the data signal Vdata can be stored in the storage capacitor In Cst, and the stored data signal Vdata can control the conduction degree of the driving transistor T3, thereby controlling the magnitude of the current flowing through the driving transistor T3 to drive the EL device to emit light, that is, this current determines the gray level of the pixel emitting light.
  • a first terminal of the sensing transistor T2 is connected to a source of the driving transistor T3, and a second terminal of the sensing transistor T2 is connected to a detecting circuit (for example, including a resistor Rvc, a capacitor Cvc, and, for example, a modulus) via a sensing line A conversion (ADC, amplifier, etc.) is connected, and the gate of the sensing transistor T2 receives the compensation scan signal G2. Therefore, when the compensation scan signal G2 is applied to turn on the driving transistor T3, the detection circuit is charged via the sensing transistor S0, so that the source potential of the driving transistor T3 changes.
  • a detecting circuit for example, including a resistor Rvc, a capacitor Cvc, and, for example, a modulus
  • the driving transistor T3 When the voltage Vs of the source of the driving transistor T3 is equal to the difference between the gate voltage Vg of the driving transistor T3 and the threshold voltage Vth of the driving transistor T3, the driving transistor T3 is turned off. At this time, after the driving transistor T3 is turned off, the sensing voltage (that is, the source voltage Vb after the driving transistor T3 is turned off) can be obtained from the source of the driving transistor T3 via the turned-on sensing transistor T2.
  • the threshold voltage Vth Vdata-Vb of the driving transistor can be obtained, so that each pixel circuit can be established based on the threshold voltage of the driving transistor in each pixel circuit ( That is, the compensation data is determined, and then the threshold voltage compensation function of each sub-pixel of the display panel can be implemented.
  • the gate driving circuit composed of the shift register unit needs to provide the scanning signal G1 and the compensation scanning signal G2 to the switching transistor T1 and the sensing transistor T2, for example, in a frame display stage (Display)
  • the scanning signal G1 for controlling the turning on of the switching transistor is provided with a compensation scanning signal G2 for controlling the turning on of the sensing transistor in a frame interval (Blank).
  • FIG. 1B shows a signal timing diagram when the pixel circuit is operating.
  • the scanning signal G1 is a pulse signal provided in the display phase;
  • the compensation scanning signal G2 is a pulse signal provided in the interval phase.
  • the pulse widths of the scanning signal G1 and the compensation scanning signal G2 required during the display phase and the interval phase are not the same. This requires that the shift register unit has a function of adjusting the pulse width, and at the same time, the interval phase is also guaranteed.
  • the pulse period of the required compensation scan signal and the pulse period of the scan signal required in the display phase are inconsistent and do not interfere with each other.
  • a shift register unit of a gate driving circuit includes a sensing unit, a display unit, and a connection unit (or gate circuit or HIZ circuit) that outputs both composite pulses.
  • the shift register unit can output a composite waveform output pulse composed of two waveforms with different widths and timings, thereby providing the scanning signal G1 and the compensation scanning signal for the switching transistor and the sensing transistor, respectively.
  • G2 the circuit structure of the above-mentioned shift register unit is complicated, and it is inevitable that two large-sized output driving transistors are required to increase the load capacity, which is not conducive to the design of the high resolution and narrow frame of the display panel.
  • Some embodiments of the present disclosure provide a shift register unit including a first sub-shift register, a second sub-shift register, and an output control circuit.
  • the first sub-shift register includes a first output terminal and a first control node for controlling the first output terminal, and is configured to output a first clock signal under the control of the level of the first control node;
  • the second sub-shift register It includes a second output terminal and a second control node for controlling the second output terminal, and is configured to be under the control of the level of the second control node, so that the second output terminal outputs a display output signal in a display phase and
  • the stage outputs a random output signal;
  • the output control circuit is connected to the first sub-shift register and the second control node, and is configured to control the level of the second control node under the control of the output control signal.
  • Some embodiments of the present disclosure further provide a gate driving circuit, a display device, and a driving method corresponding to the above-mentioned shift register unit.
  • the shift register unit, the gate driving circuit, the display device and the driving method provided by the above embodiments of the present disclosure can make the output signals of the display stage and the interval stage output through the same output circuit, so only a large-sized output needs to be provided It is sufficient to drive the transistor to drive the load connected to the gate line, thereby helping to simplify the structure of the shift register unit and the gate driving circuit, and realizing the design of the high resolution and narrow frame of the display panel.
  • FIG. 2 is a schematic diagram of a shift register unit provided by some embodiments of the present disclosure.
  • the shift register unit 10 includes a first sub-shift register 100, a second sub-shift register 200, and an output control circuit 300.
  • the shift register unit 10 can be cascaded to obtain a gate driving circuit for driving, for example, an OLED display panel.
  • the first sub-shift register 100 includes a first output terminal (not shown in the figure) and a first control node (not shown in the figure) for controlling the first output terminal, and is configured to be in the first control node.
  • the first clock signal is output under the control of the level.
  • the shift register unit further includes a second control node, a third control node, and a fourth control node
  • the first pull-up node is an example of the first control node
  • the second pull-up node The node is an example of the second control node
  • the first pull-down node is an example of the third control node
  • the second pull-down node is an example of the fourth control node
  • the first control node is the first pull-up node in the following.
  • the second control node is a second pull-up node
  • the third control node is a first pull-down node
  • the fourth control node is a second pull-down node.
  • the embodiments of the present disclosure are not limited thereto. The following embodiments and This is the same and will not be described again.
  • the second sub-shift register 200 includes a second output terminal OUT2 and a second pull-up node PU2 for controlling the second output terminal OUT2, and is configured to be under the control of the level of the second pull-up node PU2 such that
  • the second output terminal OUT2 outputs a display output signal in a display phase, and outputs a random output signal in an interval phase (also called a blanking phase).
  • the random output signal may be used for external compensation, for example, for driving the sensing transistor T2 shown in FIG. 1A.
  • the output control circuit 300 is connected to the second pull-up node PU2 of the first sub-shift register 100 and the second sub-shift register 200, and is configured to electrically control the second pull-up node PU2 under the control of the output control signal.
  • the level is controlled so that the second output terminal OUT2 outputs a display output signal in the display phase and a random output signal in the interval phase.
  • the gate drive circuit obtained by cascading the shift register unit 10 cascades the display output signal output in the display stage and the random output signal in the interval stage, and only passes through the second sub-shift register 200 of the shift register unit 10
  • the second output terminal is output, for example, the second output terminal OUT2 is connected to both the upper and lower cascaded shift register units to provide a shift output signal, and is connected to other loads (for example, a pixel circuit) in the display panel through a gate line.
  • the transistor is an output transistor controlling the second output terminal
  • the output control signal for the output control circuit 300 may include the level of the first pull-up node of the first sub-shift register 100 and the first clock signal, or may include the first clock signal output by the first output terminal.
  • the output control circuit 300 may provide the first pull-up node of the first sub-shift register 100 and provide A first clock signal terminal (not shown) of the first clock signal is connected.
  • the output control circuit 300 may be connected to the first output terminal of the first sub-shift register 100.
  • FIG. 3 is a schematic diagram of another shift register unit provided by some embodiments of the present disclosure. As shown in FIG. 3, compared with the shift register unit shown in FIG. 2, the shift register unit 10 further includes a composite output circuit 400 and a third output terminal OUT3.
  • the composite output circuit 400 is connected to the output control circuit 300, the second pull-up node PU2, and the third output terminal OUT3, and is configured to be controlled by the level of the second pull-up node PU2 so that the third output terminal OUT3 is in the display stage.
  • the output shows the output signal, and the random output signal is output during the interval.
  • the signal output from the third output terminal OUT is the same as the signal output from the second output terminal OUT2.
  • the second output terminal OUT2 is used to connect with a second sub-shift register 200 cascaded thereon to provide a shift signal
  • the third output terminal OUT3 is used to pass a gate line and a load (for example, a pixel circuit).
  • connection can avoid crosstalk of the data signal transmitted by the data line to the shift signal output from the second output terminal OUT2, thereby ensuring the reliability of the output signals of the multiple cascaded shift register units.
  • it is only necessary to provide a larger-sized output driving transistor to increase the load capacity that is, the output transistor that controls the output of the third output terminal OUT3 in the composite output circuit 400 connected to the gate line.
  • the second output terminal is used for outputting the shift signal of the cascaded shift register unit, it is not necessary to drive the load connected to it by the gate line. Therefore, the output transistor of the second output terminal does not need a large size, so that Conducive to the realization of the narrow bezel design of the display panel.
  • FIG. 4A is a schematic diagram of an example of the first sub-shift register 100 shown in FIG. 2 or FIG. 3.
  • the first sub-shift register 100 may include a first input circuit 110, a first control node reset circuit 120, a first output circuit 130, a first control node noise reduction circuit 140, a first An output noise reduction circuit 150 and a first inverter circuit 160.
  • the first pull-up node reset circuit is an example of the first control node reset circuit 120
  • the first pull-up node noise reduction circuit is an example of the first control node noise reduction circuit 140.
  • the following description uses the first control node reset circuit 120 as the first pull-up node reset circuit and the first control node noise reduction circuit 140 as the first pull-up node noise reduction circuit as an example for description, but the embodiment of the present disclosure is not limited thereto. The following embodiments are the same and will not be described again.
  • the first input circuit 110 is configured to charge the first pull-up node PU1 in response to a first input signal.
  • the first input circuit 110 is connected to the first input terminal INT1, the second voltage terminal VGH, and the first pull-up node PU1, and is configured to enable the first pull-up node PU1 under the control of a signal input from the first input terminal INT1. It is electrically connected to the second voltage terminal VGH, so that the second voltage (for example, a high-level signal) input at the second voltage terminal can control (for example, charge) the potential of the first pull-up node PU1 so that the first The voltage of the pull-up node PU1 is increased to control the first output circuit 130 to be turned on.
  • the first input circuit 110 may also be connected to the first input terminal INT1 and the first pull-up node PU1, and is configured to make the first input circuit under the control of the signal input from the first input terminal INT1.
  • the pull node PU1 is electrically connected to the first input terminal INT1, so that the high-level signal input from the first input terminal INT1 can charge the first pull node PU1.
  • the first pull-up node reset circuit 120 is configured to reset the first pull-up node PU1 in response to a first reset signal.
  • the first pull-up node reset circuit 120 may be configured to be connected to the first reset terminal RST1, the first voltage terminal VGL, and the first pull-up node PU1, so that it can be controlled by the reset signal input from the first reset terminal RST1. So that the first pull-up node PU1 is electrically connected to a pull-down voltage terminal (such as a low-level signal or a low-voltage terminal), and the low-voltage terminal is, for example, the first voltage terminal VGL, so that the first pull-up node PU1 can be pulled down ( For example, discharge) reset.
  • a pull-down voltage terminal such as a low-level signal or a low-voltage terminal
  • the first output circuit 130 is configured to output the first clock signal input from the first clock signal terminal CLK1 to the first output terminal OUT1 under the control of the level of the first pull-up node PU1 as the first sub-shift. Output signal of the register 100.
  • the first output circuit 130 is connected to the first pull-up node PU1, the first clock signal terminal CLK1, and the first output terminal OUT1, and is configured to be turned on under the control of the level of the first pull-up node PU1, so that The first clock signal terminal CLK1 is electrically connected to the first output terminal OUT1, so that the clock signal input from the first clock signal terminal CLK1 can be output to the first output terminal OUT1.
  • the first pull-up node noise reduction circuit 140 is configured to perform noise reduction on the first pull-up node PU1 under the control of the level of the first pull-down node PD1.
  • the first pull-up node noise reduction circuit 140 is connected to the first pull-up node PU1, the first pull-down node PD1, and the first voltage terminal VGL to control the level of the first pull-down node PD1 so that The first pull-up node PU1 is electrically connected to the first voltage terminal VGL, thereby performing pull-down noise reduction on the first pull-up node PU1.
  • the first output noise reduction circuit 150 is configured to perform noise reduction on the first output terminal OUT1 under the control of the level of the first pull-down node PD1.
  • the first output noise reduction circuit 150 is connected to the first pull-down node PD1, the first output terminal OUT1, and the first voltage terminal VGL, and is configured to control the first pull-down node PD1 to make the first
  • the output terminal OUT1 is electrically connected to the first voltage terminal VGL, so as to pull down and reduce noise on the first output terminal OUT1.
  • the first inverter circuit 160 is configured to control the level of the first pull-down node PD1 under the control of the level of the first pull-up node PU1.
  • the first inverter circuit 160 is connected to the first pull-up node PU1 and the first pull-down node PD1, and is configured to pull down the first pull-down node PD1 to a low power level when the first pull-up node PU1 is high.
  • the first pull-down node PD1 is pulled up to a high level.
  • the first inverter circuit 160 may be an inverter circuit or any other circuit that can implement the inverter function.
  • the first sub-shift register 100 shown in FIG. 4A may be specifically implemented as the circuit structure shown in FIG. 4C in one example.
  • each transistor is described as an N-type transistor, but it does not constitute a limitation on the embodiments of the present disclosure.
  • the N-type transistor is turned on in response to a high-level signal and turned off in response to a low-level signal.
  • the following embodiments are the same, and will not be described again.
  • the first input circuit 110 may be implemented as a sixth transistor T6.
  • the gate of the sixth transistor T6 is electrically connected to the first input terminal INT1 to receive the input signal
  • the first electrode is electrically connected to the second voltage terminal VGH to receive the second voltage
  • the second electrode is configured to be connected to the first pull-up node PU1. Therefore, when the sixth transistor T6 is turned on due to the conduction signal (high-level signal) received by the first input terminal INT1, the first pull-up node PU1 and the second voltage terminal VGH are electrically connected to connect the first pull-up node PU1 and Pull node PU1 to charge it to high level.
  • the first pull-up node reset circuit 120 may be implemented as a seventh transistor T7.
  • the gate of the seventh transistor T7 is configured to be connected to the first reset terminal RST1 to receive the first reset signal
  • the first electrode is configured to be connected to the first pull-up node PU1
  • the second electrode is configured to be connected to the first voltage terminal VGL to Receive a first voltage.
  • the seventh transistor T7 is turned on due to the first reset signal
  • the first pull-up node PU1 is electrically connected to the first voltage terminal VGL, so that the first pull-up node PU1 can be reset and dropped from a high level to Low.
  • the first output circuit 130 may be implemented to include an eighth transistor T8 and a first storage capacitor C1.
  • the gate of the eighth transistor T8 is configured to be connected to the first pull-up node PU1, the first pole is configured to be connected to the first clock signal terminal CLK1 to receive the first clock signal, and the second pole is configured to be connected to the first output terminal OUT1
  • the first pole of the first storage capacitor C1 is configured to be connected to the gate of the eighth transistor T8, and the second pole is connected to the second pole of the eighth transistor T8.
  • the first pull-up node noise reduction circuit 140 may be implemented as a ninth transistor T9.
  • the gate of the ninth transistor T9 is configured to be connected to the first pull-down node PD1, the first electrode is configured to be connected to the first pull-up node PU1, and the second electrode is configured to be connected to the first voltage terminal VGL to receive the first voltage.
  • the ninth transistor T9 is turned on when the first pull-down node PD1 is at a high potential, and the first pull-up node PU1 is connected to the first voltage terminal VGL, so that the first pull-up node PU1 can be pulled down to achieve noise reduction.
  • the first output noise reduction circuit 150 may be implemented as a tenth transistor T10.
  • the gate of the tenth transistor T10 is configured to be connected to the first pull-down node PD1, the first electrode is configured to be connected to the first output terminal OUT1, and the second electrode is configured to be connected to the first voltage terminal VGL to receive the first voltage.
  • the tenth transistor T10 is turned on when the first pull-down node PD1 is at a high potential, and the first output terminal OUT1 and the first voltage terminal VGL are connected, so that the first output terminal OUT1 can be reduced in noise.
  • the potential of the first pull-up node PU1 When the potential of the first pull-up node PU1 is maintained at a high level, there are some transistors (for example, a sixth transistor T6 (when the gate and the first electrode of the sixth transistor T6 are connected to the first input terminal INT1), The first pole of the seven transistors T7 and the ninth transistor T9 is connected to the first pull-up node PU1, and the second pole is connected to a low-level signal. Even when a non-conducting signal is input to the gates of these transistors, a leakage current may occur due to a voltage difference between the first and second poles of the transistors. The effect of maintaining the potential of a pull-up node PU1 becomes worse.
  • a shift register unit 10 for preventing leakage is provided in one embodiment of the present disclosure.
  • the first sub-shift register 100 may further include a first leakage prevention circuit 170. It should be noted that the same problem exists in the second sub-shift register 200, and the details are not repeated.
  • the first leakage prevention circuit 170 is configured to maintain a high potential of the first pull-up node PU1 under the control of a first clock signal output as an output signal from the first output terminal OUT1.
  • the first leakage prevention circuit 170 is connected to the first clock signal terminal CLK1, the first output terminal OUT1, the first pull-up node reset circuit 120, the first pull-up node noise reduction circuit 140, and the first input circuit 110, and is configured.
  • the sources and drains of the transistors connected to the first pull-up node PU1 are simultaneously high, thereby avoiding the first The level of the pull-up node PU1 is lowered due to leakage to affect the display quality.
  • FIG. 4B illustrates only an exemplary circuit structure including a leakage prevention circuit, and does not constitute a limitation on the embodiment of the present disclosure.
  • the first sub-shift register 100 shown in FIG. 4B may be specifically implemented as the circuit structure shown in FIG. 4D in one example.
  • the structure of the first sub-shift register 100 is similar to that of the first sub-shift register 100 in FIG. 4C, and the difference is that a transistor implementing the first leakage prevention circuit 170 is added.
  • the first leakage prevention circuit 170 may be implemented as an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14.
  • the gate of the eleventh transistor T11 is connected to the first input terminal INT1 to receive the first input signal.
  • the second pole of the eleventh transistor T11 is connected to the first pull-up node PU1; the gate of the twelfth transistor T12 is connected to the first reset terminal RST1 to receive a first reset signal, and the first of the twelfth transistor T12 is connected Is connected to the second pole of the fourteenth transistor T14 and the second pole of the seventh transistor T7, and the second pole of the twelfth transistor T12 is connected to the first voltage terminal VGL to receive the first voltage;
  • the gate is connected to the first pull-down node PD1, the first pole of the thirteenth transistor T13 and the second pole of the fourteenth transistor T14 and the second pole of the ninth transistor T9 are connected, and the second pole of the thirteenth transistor T13 Connected to the first voltage terminal VGL to receive the first voltage; the gate of the fourteenth transistor T14 is connected to the first output terminal OUT1, and the first pole of the fourteenth transistor T14 is connected to the first clock signal terminal CLK1 to receive the first Clock signal.
  • the first output terminal OUT1 When the first clock signal provided by the first clock signal terminal CLK1 is in a high-level state and the first pull-up node PU1 is also in a high-level state, the first output terminal OUT1 outputs the first under the control of the first pull-up node PU1. A clock signal. At this time, the fourteenth transistor T14 is turned on under the control of the high level of the first clock signal output by the first output terminal OUT1 as an output signal, so that the first clock signal terminal CLK1 and the eleventh transistor T11 can be turned on.
  • the second electrodes of the twelfth transistor T12, the thirteenth transistor T13, the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 are connected, so that the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 are connected.
  • Both the first pole and the second pole are at a high level, for example, the first pole is at a high level at the first pull-up node PU1, and the second pole is at a high level at the first clock signal, thereby preventing the first pull-up node
  • the charge of PU1 is leaked through the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 connected to it.
  • first shift register unit is not limited to the structure shown in FIG. 4A and FIG. 4B, and may be other various types of shift register units, which are not limited in the embodiments of the present disclosure.
  • the first voltage terminal VGL may be configured to maintain an input DC low-level signal, for example, the DC low-level signal is referred to as a first voltage
  • the second voltage terminal VGH may be configured to maintain an input DC high-level signal, for example.
  • the DC high-level signal is referred to as a second voltage
  • the first voltage is lower than the second voltage.
  • the embodiment of the present disclosure does not limit the specific structure of the second sub-shift register, and a circuit structure known to implement a shift register unit may be adopted, such as including an input circuit, a second pull-up node, and an output circuit.
  • the input circuit controls the level of the second pull-up node
  • the second pull-up node controls the output circuit to output a pulse signal.
  • the first sub-shift register and the second sub-shift register may have the same structure, thereby simplifying the design and manufacturing process of the shift register unit in the embodiment of the present disclosure.
  • FIG. 5A is a schematic diagram of an example of the second sub-shift register 200 shown in FIG. 2 or FIG. 3.
  • the second sub-shift register 200 may include a second input circuit 210, a second control node reset circuit (not shown in the figure), a second output circuit 230, and a second control node A noise reduction circuit (not shown), a second output noise reduction circuit 250 and a second inverter circuit 260.
  • the second pull-up node reset circuit 220 is an example of a second control node reset circuit
  • the second pull-up node noise reduction circuit 240 is an example of a second control node noise reduction circuit.
  • the following description uses the second control node reset circuit as the second pull-up node reset circuit 220 and the second control node noise reduction circuit as the second pull-up node noise reduction circuit 240 as an example for description, but the embodiment of the present disclosure is not limited thereto. The following embodiments are the same and will not be described again.
  • the second input circuit 210 is configured to charge the second pull-up node PU2 in response to the second input signal.
  • the second input circuit 210 is connected to the second input terminal INT2, the second voltage terminal VGH, and the second pull-up node PU2, and is configured to enable the second pull-up node PU2 under the control of a signal input from the second input terminal INT2. It is electrically connected to the second voltage terminal VGH, so that the second voltage (for example, a high-level signal) input from the second voltage terminal VGH can charge the second pull-up node PU2, so that the voltage of the second pull-up node PU2 Added to control the second output circuit 230 to be turned on.
  • the second voltage for example, a high-level signal
  • the second input circuit 210 may also be connected only to the second input terminal INT2 and the second pull-up node PU2, and configured to enable the second input circuit under the control of the signal input from the second input terminal INT2.
  • the pull-up node PU2 is electrically connected to the second input terminal INT2, so that the high-level signal input from the second input terminal INT2 can charge the second pull-up node PU2.
  • the second pull-up node reset circuit 220 is configured to reset the second pull-up node PU2 in response to a second reset signal.
  • the second pull-up node reset circuit 220 may be configured to be connected to the second reset terminal RST2, the first voltage terminal VGL, and the second pull-up node PU2, so that it can be controlled by the reset signal input from the second reset terminal RST2.
  • the second pull-up node PU2 is electrically connected to a low-level signal or a low-voltage terminal, such as the first voltage terminal VGL, so that the second pull-up node PU2 can be pulled down and reset.
  • the second output circuit 230 is configured to output the third clock signal input from the third clock signal terminal CLK3 to the second output terminal OUT2 under the control of the level of the second pull-up node PU2 as the second sub-shift. Output signal of register 200.
  • the second output circuit 230 is connected to the second pull-up node PU2, the third clock signal terminal CLK3, and the second output terminal OUT2, and is configured to be turned on under the control of the level of the second pull-up node PU2 so that The third clock signal terminal CLK3 is electrically connected to the second output terminal OUT2, so that the clock signal input from the third clock signal terminal CLK3 can be output to the second output terminal OUT2.
  • the third clock signal includes a display output signal and a random output signal with different pulse widths and timings.
  • the two different signals can be implemented through a field-programmable gate array (FPGA).
  • the third clock signal is synthesized, and the synthesized third clock signal is output through the second output terminal OUT2, so that the display output signal and the random output signal can be output only through the second output terminal OUT2.
  • the second pull-up node noise reduction circuit 240 is configured to perform noise reduction on the second pull-up node PU2 under the control of the level of the second pull-down node PD2.
  • the second pull-up node noise reduction circuit 240 is connected to the second pull-up node PU2, the second pull-down node PD2, and the first voltage terminal VGL to control the second pull-down node PD2 to control the second pull-down node PD2.
  • the pull-up node PU2 is electrically connected to the first voltage terminal VGL, thereby performing pull-down noise reduction on the second pull-up node PU2.
  • the second output noise reduction circuit 250 is configured to perform noise reduction on the second output terminal OUT2 under the control of the level of the second pull-down node PD2.
  • the second output noise reduction circuit 250 is connected to the second pull-down node PD2, the second output terminal OUT2, and the first voltage terminal VGL, and is configured to enable the second output under the control of the level of the second pull-down node PD2.
  • the terminal OUT2 is electrically connected to the first voltage terminal VGL, so as to pull down and reduce noise on the second output terminal OUT2.
  • the second inverter circuit 260 is configured to control the level of the second pull-down node PD2 under the control of the level of the second pull-up node PU2.
  • the second inverter circuit 260 is connected to the second pull-up node PU2 and the second pull-down node PD2, and is configured to pull down the second pull-down node PD2 to a low level when the second pull-up node PU2 is high, When the second pull-up node PU2 is at a low level, the second pull-down node PD2 is pulled up to a high level.
  • the second inverter circuit 260 may be an inverter circuit or any other circuit that can implement the inverter function.
  • the second sub-shift register 200 shown in FIG. 5A may be specifically implemented as the circuit structure shown in FIG. 5C in one example.
  • each transistor is described as an N-type transistor, but this does not constitute a limitation on the embodiments of the present disclosure.
  • the second input circuit 210 may be implemented as a twenty-first transistor T21.
  • the gate of the twenty-first transistor T21 is electrically connected to the second input terminal INT2 to receive the input signal
  • the first electrode is electrically connected to the second voltage terminal VGH to receive the second voltage
  • the second electrode is configured to be connected to the second pull-up node.
  • PU2 is connected, so that when the twenty-first transistor T21 is turned on due to the conduction signal (high-level signal) received by the second input terminal INT2, the second pull-up node PU2 and the second voltage terminal VGH are electrically connected to Charge the second pull-up node PU2 so that it is at a high level.
  • the second pull-up node reset circuit 220 may be implemented as a twenty-second transistor T22.
  • the gate of the twenty-second transistor T22 is configured to be connected to the second reset terminal RST2 to receive a second reset signal
  • the first electrode is configured to be connected to the second pull-up node PU2
  • the second electrode is configured to be connected to the first voltage terminal VGL. Connected to receive the first voltage.
  • the twenty-second transistor T22 is turned on due to the second reset signal
  • the second pull-up node PU2 is electrically connected to the first voltage terminal VGL, so that the second pull-up node PU2 can be reset to bring it from a high level. Fall to low.
  • the second output circuit 230 may be implemented to include a twenty-third transistor T23 and a second storage capacitor C2.
  • the gate of the twenty-third transistor T23 is configured to be connected to the second pull-up node PU2, the first pole is configured to be connected to the third clock signal terminal CLK3 to receive the third clock signal, and the second pole is configured to be connected to the second output terminal OUT2 is connected; the first pole of the second storage capacitor C2 is configured to be connected to the gate of the twenty-third transistor T23, and the second pole is connected to the second pole of the twenty-third transistor T23.
  • the size of the twenty-third transistor T23 is large, and it can be connected to the gate line as an output driving transistor to drive a load such as a pixel circuit connected to the gate line.
  • the composite output circuit is used as a large-sized output driving transistor, and the twenty-third transistor T23 is used as a transistor for shift signal output, and does not need a large size.
  • the second pull-up node noise reduction circuit 240 may be implemented as a twenty-fourth transistor T24.
  • the gate of the twenty-fourth transistor T24 is configured to be connected to the second pull-down node PD2, the first electrode is configured to be connected to the second pull-up node PU2, and the second electrode is configured to be connected to the first voltage terminal VGL to receive the first voltage .
  • the twenty-fourth transistor T24 is turned on when the second pull-down node PD2 is at a high potential, and the second pull-up node PU2 is connected to the first voltage terminal VGL, so that the second pull-up node PU2 can be pulled down to achieve noise reduction.
  • the second output noise reduction circuit 250 may be implemented as a twenty-fifth transistor T25.
  • the gate of the twenty-fifth transistor T25 is configured to be connected to the second pull-down node PD2, the first electrode is configured to be connected to the second output terminal OUT2, and the second electrode is configured to be connected to the first voltage terminal VGL to receive the first voltage.
  • the twenty-fifth transistor T25 is turned on when the second pull-down node PD2 is at a high potential, and the second output terminal OUT2 is connected to the first voltage terminal VGL, so that the second output terminal OUT2 can be reduced in noise.
  • the second sub-shift register 200 may further include a second leakage prevention circuit 270.
  • the second leakage prevention circuit 270 is configured to maintain a high potential of the second pull-up node PU2 under the control of the second clock signal output from the second output terminal OUT2.
  • the second leakage prevention circuit 270 is connected to the third clock signal terminal CLK3, the second output terminal OUT2, the second pull-up node reset circuit 220, the second pull-up node noise reduction circuit 240, and the second input circuit 210, and is configured.
  • the sources and drains of the transistors connected to the second pull-up node PU2 are simultaneously high, thereby avoiding the second The level of the pull-up node PU2 is lowered due to leakage to affect the display quality.
  • the second sub-shift register 200 shown in FIG. 5B may be specifically implemented as the circuit structure shown in FIG. 5D in one example.
  • the structure of the second sub-shift register 200 is similar to that of the second sub-shift register 200 in FIG. 5C, except that a transistor for implementing the second leakage prevention circuit 270 is added.
  • the second leakage prevention circuit 270 may be implemented as a twenty-sixth transistor T26, a twenty-seventh transistor T27, a twenty-eighth transistor T28, and a twenty-ninth transistor T29.
  • the gate of the twenty-sixth transistor T26 is connected to the second input terminal INT2 to receive a second input signal, the first pole of the twenty-sixth transistor T26 and the second pole of the twenty-ninth transistor T29, and the twenty-first transistor
  • the second pole of T21 is connected, the second pole of the twenty-sixth transistor T26 is connected to the second pull-up node PU2;
  • the gate of the twenty-seventh transistor T27 is connected to the second reset terminal RST2 to receive a second reset signal, the first The first pole of the twenty-seventh transistor T27 is connected to the second pole of the twenty-ninth transistor T29 and the second pole of the twenty-second transistor T22, and the second pole of the twenty-seventh transistor T27 is connected to
  • FIG. 5B only illustrates an exemplary circuit structure including a leakage prevention circuit, and does not constitute a limitation on the embodiment of the present disclosure.
  • the structure is not limited to that shown in FIG. 5A and FIG. 5B, and the second shift register unit may be other various types of shift register units, which are not limited in the embodiments of the present disclosure.
  • FIG. 6 is a schematic diagram of another shift register unit provided by some embodiments of the present disclosure.
  • the shift register unit 10 may further include a total reset circuit 500.
  • the overall reset circuit 500 is configured to reset the second pull-up node PU2 under the control of the third reset signal, and at the same time, reset the composite output circuit 400 and the third output terminal OUT3, thereby ensuring the display panel's Contrast.
  • the shift register unit 10 shown in FIG. 6 may be specifically implemented as the circuit structure shown in FIG. 7A or FIG. 7B in one example.
  • each transistor is described as an N-type transistor, but it does not limit the embodiments of the present disclosure.
  • the first sub-shift register 100 may adopt the structure shown in FIG. 4D
  • the second sub-shift register 200 may adopt the structure shown in FIG. 5D, which is not repeated here.
  • the output control signal includes the level of the first pull-up node PU1 and the first clock signal.
  • the output control circuit 300 may be implemented as a first transistor T1 and a second transistor T2, for example.
  • the gate of the first transistor T1 is connected to the first pull-up node PU1, the first pole of the first transistor T1 is connected to the first clock signal terminal CLK1 to receive the first clock signal, and the second pole of the first transistor T1 and the second
  • the gate of the transistor T2 is connected; the first pole of the second transistor T2 and the second clock signal terminal CLK2 are connected to receive the second clock signal, or as shown in FIG. 7B, the first pole of the second transistor T2 and the second transistor T2 Gate connection.
  • the second pole of the second transistor T2 is connected to the second pull-up node PU2 of the second sub-shift register 200, so that the output control circuit 300 can control the level of the second pull-up node PU2 to control the second output terminal.
  • OUT2 and the third output terminal OUT3 output a display output signal during a display phase, and output a random output signal during an interval phase.
  • the output control circuit 300 may further include a third transistor T3.
  • the gate of the third transistor T3 is connected to the first pull-down node PD1, the first electrode of the third transistor T3 is connected to the gate of the second transistor T2, and the second electrode of the third transistor T3 is connected to the first voltage terminal VGL. Receiving the first voltage to implement pull-down reset on the gate of the second transistor T2.
  • the composite output circuit 400 may be implemented as a fourth transistor T4.
  • the gate of the fourth transistor T4 is connected to the second pull-up node PU2, the first pole of the fourth transistor T4 is connected to the third clock signal terminal CLK3 to receive the third clock signal, and the second pole of the fourth transistor T4 is connected to the third Output OUT3 is connected.
  • the third clock signal includes a display output signal and a random output signal.
  • the fourth transistor T4 is an output driving transistor connected to the load through a gate line, that is, to drive light emission of, for example, a pixel circuit connected to the gate line. Therefore, the fourth transistor T4 can be designed to have a larger size, thereby increasing the Drive capability.
  • the composite output circuit 400 may further include a fifth transistor T5.
  • the gate of the fifth transistor T5 is connected to the second pull-down node PD2, the first pole of the fifth transistor T5 is connected to the third output terminal OUT3, and the second pole of the fifth transistor T5 is connected to the first voltage terminal VGL to receive the first Voltage, so that when the fifth transistor T5 is turned on in response to the level of the second pull-down node PD2, the third output terminal OUT3 is connected to the first voltage terminal VGL, thereby resetting the third output terminal OUT3.
  • the total reset circuit 500 may be implemented as a thirtieth transistor T30.
  • the gate of the 30th transistor T30 is connected to the third reset terminal RST3 to receive a third reset signal, and the first pole of the 30th transistor T30 is connected to the first voltage terminal VGL to receive the first voltage.
  • the second pole is connected to the second pull-up node PU2.
  • the total reset circuit 500 of the cascaded shift register unit in the gate driving circuit is connected to the third reset terminal RST3, so that the third reset terminal RST3 can be used to implement The second pull-up node PU2 of the shift register unit 10 is reset.
  • the shift register unit 10 shown in FIG. 6 may be specifically implemented as the circuit structure shown in FIG. 7C in another example.
  • the circuit structure of the shift register unit 10 of this example is similar to that of the shift register unit shown in FIG. 7A, but the difference is that in this example, the output control signal includes all outputs output from the first output terminal OUT1.
  • the first clock signal is described, and the output control circuit 300 is implemented as a first transistor T1.
  • the gate of the first transistor T1 is connected to the first output terminal OUT1 of the first sub-shift register 100.
  • the first electrode of the first transistor T1 is connected to the second clock signal terminal CLK2 to receive the second clock signal.
  • the first transistor T1 The second pole is connected to the second pull-up node PU2, that is, the first transistor T1 is turned on in response to the first clock signal output from the first output terminal OUT1, so as to control the level of the second pull-up node PU2.
  • FIG. 7D is a circuit diagram of a specific implementation example of the shift register unit shown in FIG. 3.
  • the shift register unit may omit the total reset circuit 500, that is, the thirty-th transistor T30 is omitted, so the second pull-up node PU2 may be turned on at the first transistor T1 and When the second clock signal terminal CLK2 provides a low level, reset discharge is performed by the first transistor T1, so that the circuit is simple and the area occupied by the circuit on the display panel is reduced.
  • the shift register unit shown in FIG. 7A may also omit the total reset circuit 500, and the principle thereof is similar to the principle of the circuit structure shown in FIG. 7C, and is not repeated here.
  • FIG. 7E is a schematic circuit diagram of another specific implementation example of the shift register unit shown in FIG. 3.
  • the second leakage prevention circuit 270 in the shift register unit in this example may further include a thirty-first transistor T31.
  • the gate of the thirty-first transistor T31 is connected to the first output terminal OUT1, the first electrode is connected to the second electrode of the first transistor T1 and the second electrode of the twenty-ninth transistor T29, and the second electrode is connected to the second pull-up Node PU2 is connected.
  • the working principle of the second anti-leakage circuit in this example is similar to the working principle of the first anti-leakage circuit 170, and details are not described herein again.
  • all the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • the thin film transistors are used as an example for description.
  • the source and drain of the transistor used here can be symmetrical in structure, so there can be no difference in structure of the source and drain of the transistor.
  • one pole is directly described as the first pole and the other pole is the second pole.
  • the transistors in the shift register unit provided in the embodiments of the present disclosure are all described by taking N-type transistors as an example.
  • the first electrode of the transistor is a drain and the second electrode is a source.
  • the present disclosure includes but is not limited to this.
  • one or more transistors in the shift register unit provided by the embodiments of the present disclosure may also be P-type transistors.
  • the first pole of the transistor is the source and the second pole is the drain.
  • the polarities of the poles of the transistors of the type may be connected according to the polarities of the poles of the respective transistors in the embodiments of the present disclosure.
  • ITZO Indium Gallium Zinc Oxide
  • LTPS Low Temperature Polysilicon
  • amorphous silicon such as (Crystalline silicon
  • pulse-up means discharging a node or an electrode of a transistor such that the node or the The absolute value of the level of the electrode is reduced to achieve the operation of the corresponding transistor (for example, on);
  • pulse-down means that a node or an electrode of a transistor is charged so that the absolute level of the node or the electrode The value rises, thereby enabling operation (for example, off) of the corresponding transistor.
  • pulse-up means charging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode is increased, thereby achieving corresponding The operation of a transistor (for example, turning on);
  • pulseling down means discharging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode is reduced, thereby realizing the operation of the corresponding transistor (for example, turning off) .
  • the first pull-up node PU1, the first pull-down node PD1, the second pull-up node PU2, and the second pull-down node PD2 do not indicate actual components, but It is the meeting point of the related circuit connections in the circuit diagram.
  • the shift register unit provided by the above embodiments of the present disclosure can make the output signal of the display phase and the interval phase be output to the gate line only through the second output circuit or the composite output circuit, so only a large-sized output drive transistor is needed to drive The load connected to the gate line is sufficient, thereby helping to achieve a high-resolution and narrow bezel design of the display panel.
  • the gate driving circuit 20 includes a first clock signal line CLKA, a second clock signal line CLKB, a third clock signal line CLKC, and a fourth The clock signal line CLKD, the fifth clock signal line CLKE, and a plurality of cascaded shift register units 10.
  • the shift register unit 10 may use any one of the shift register units provided in the above embodiments.
  • the following description uses a gate driving circuit formed by a shift register unit shown in FIG. 3 as an example. The working principle of other types of gate driving circuits is similar to this, and is not repeated here.
  • each shift register unit 10 includes a first sub-shift register 100, a second sub-shift register 200, an output control circuit 300, and a composite output circuit 400.
  • each first sub-shift register 100 is connected to an output control circuit 300
  • the output control circuit 300 is connected to the second pull-up node PU2 of the second sub-shift register 200 and the composite output circuit 400.
  • the gate driving circuit 20 can be directly integrated on the array substrate of the display device by using the same process as the thin film transistor, so as to realize the progressive scanning driving function.
  • the first sub-shift register 100 may adopt the circuit structure in FIG. 4D
  • the second sub-shift register 200 may adopt the circuit structure in FIG. 5D.
  • the first sub-shift register 100 in each of the shift register units 10 further includes a first clock signal terminal CLK1 and is configured to communicate with the first clock signal line CLKA and the second clock signal.
  • the line CLKB is connected to receive a clock signal.
  • the first clock signal line CLKA is connected to the first clock signal terminal CLK1 of the 2m-1 (m is an integer greater than 0) first sub-shift register, and the second clock signal line CLKB and the 2m-level first sub-shift The first clock signal terminal CLK1 of the register is connected.
  • the second sub-shift register 200 and the composite output circuit 400 in each of the shift register units 10 further include a third clock signal terminal CLK3, and are configured to communicate with the third clock signal line CLKC and the fourth clock signal line.
  • CLKD is connected to receive a clock signal.
  • the third clock signal line CLKC is connected to the second sub-shift register of the 2m-1 stage and the third clock signal terminal CLK3 of the composite output circuit 400.
  • the fourth clock signal line CLKD is connected to the second sub-shift register of the 2m stage and the composite
  • the third clock signal terminal CLK3 of the output circuit 400 is connected.
  • the output control circuit 300 in each of the shift register units 10 further includes a second clock signal terminal CLK2, and is configured to be connected to a fifth clock signal line CLKE to receive a second clock signal.
  • OUT1 (N) shown in FIG. 8 represents the first output terminal of the first sub-shift register of the Nth (N is an integer greater than 1) stage, and OUT1 (N + 1) represents the N + 1th
  • OUT2 (N) shown in FIG. 8 represents the second of the second sub-shift register of the N-th stage (N is an integer greater than 1).
  • Output terminal, OUT2 (N + 1) represents the second output terminal of the second sub shift register of the N + 1th stage ...
  • OUT3 (N) shown in FIG. 8 represents the Nth (N is greater than An integer of 1) third output terminal, OUT3 (N + 1) represents the third output terminal of the N + 1th stage ...
  • the reference numerals in the following embodiments are similar to this and will not be described again.
  • the output control circuit 300 is connected between the first sub-shift register 100 and the second sub-shift register 200; in addition to the first-stage first sub-shift register, the rest of the first sub-shift registers
  • the first input terminal INT1 of the shift register is connected to the first output terminal OUT1 of the first sub-shift register of the upper stage; except for the first sub-shift register of the last stage, the first A reset terminal RST1 is connected to the first output terminal OUT1 of the first sub-shift register of the next stage; in addition to the second sub-shift register of the first stage, the second input terminals INT2 and
  • the second output terminal OUT2 of the second sub shift register of the upper stage is connected; except for the second sub shift register of the last stage, the second reset terminal RST2 of the second sub shift registers of the other stages and the second stage of the next stage
  • the second output terminal OUT2 of the sub-shift register is connected.
  • the gate driving circuit 20 may further include a timing controller 900.
  • the timing controller 900 may be configured to be connected to the first clock signal line CLKA, the second clock signal line CLKB, the third clock signal line CLKC, the fourth clock signal line CLKD, and the fifth clock signal line CLKE to Each shift register unit provides a clock signal, a trigger signal, and a reset signal.
  • the gate driving circuit further includes a total reset line (not shown in the figure) configured to provide a third reset signal to the third reset terminal to the gate driving circuit. All second pull-up nodes are reset.
  • the gate driving circuit 10 may further include four, six or eight clock signal lines, and the number of clock signal lines depends on specific circumstances, which is not limited in the embodiment of the present disclosure.
  • a gate driving circuit 20 provided by an embodiment of the present disclosure is used to drive a display panel
  • the gate driving circuit 20 may be disposed on one side of the display panel.
  • the display panel includes multiple rows of gate lines, and the output terminals of the shift register units in the gate driving circuit 20 may be configured to be sequentially connected to the multiple rows of gate lines for outputting a gate scan signal.
  • the gate driving circuit 20 may also be provided on both sides of the display panel to achieve bilateral driving.
  • the embodiment of the present disclosure does not limit the manner of setting the gate driving circuit 20.
  • a gate driving circuit 20 may be provided on one side of the display panel for driving odd-numbered rows of gate lines, and a gate driving circuit 20 may be provided on the other side of the display panel for driving even-numbered rows of gate lines.
  • FIG. 9 is a timing diagram of signals when the gate driving circuit shown in FIG. 8 operates.
  • the following describes the working principle of the gate driving circuit 20 shown in FIG. 8 with reference to the signal timing diagram shown in FIG. 9.
  • each transistor is described as an N-type transistor, but the embodiment of the present disclosure does not Limited to this.
  • each frame includes two phases: a display phase D and an interval phase S.
  • a display phase D of the Xth frame (X is an integer greater than 0)
  • the working process of the shift register unit in the gate driving circuit is described as follows. It should be noted that the working process of the remaining frames is similar to this and will not be described again.
  • the third clock signal line CLKC provides a high level, for example, the high level is a display output signal. Since the Nth stage second sub-shift register 200 and the third clock signal terminal of the composite output circuit 400 CLK3 is connected to the third clock signal line CLKC, so at this stage, a high level is input to the third clock signal terminal CLK3 of the Nth stage; and because the second pull-up node PU2_N of the second subshift register of the Nth stage is a high voltage Level, so under the control of the high level of the second pull-up node PU2_N, the high level input from the third clock signal terminal CLK3 is output to the second output terminal OUT2 (N) of the second sub shift register 200 of the Nth stage And a third output terminal OUT3 (N) of the composite output circuit 400.
  • the fourth clock signal line CLKD provides a high level, because the third clock signal terminal CLK3 of the second sub shift register 200 of the N + 1th stage and the composite output circuit 400 is connected to the fourth clock signal line CLKD. Therefore, at this stage, the third clock signal terminal CLK3 of the N + 1th stage inputs a high level; and because the second pull-up node PU2_N + 1 of the second subshift register of the N + 1th stage is at a high level, so Under the control of the high level of the second pull-up node PU2_N + 1, the high level input from the third clock signal terminal CLK3 is output to the second output terminal OUT2 (N +1) and the third output terminal OUT3 (N + 1) of the composite output circuit 400.
  • the first clock signal line CLKA provides a high level. Since the first clock signal terminal CLK1 of the first sub-shift register of the first stage is connected to the first clock signal line CLKA, at this stage, the first A clock signal terminal CLK1 inputs a high level; at the same time, the fifth clock signal line CLKE provides a high level. Since the second clock signal terminal CLK2 is connected to the fifth clock signal line CLKE, at this stage, the second clock signal terminal CLK2 is input high level; the third clock signal line CLKC provides a high level.
  • the third clock signal terminal CLK3 of the second sub shift register 200 and the composite output circuit 400 is connected to the third clock signal line CLKC, at this stage
  • the third clock signal terminal CLK3 inputs a high level, for example, the high level is a random output signal, which is different from the high level of the third clock signal line CLKC in the first stage; and because of the first sub shift of the first stage
  • the first pull-up node PU1 of the register 100 is high level, so under the control of the first pull-up node PU1 and the high level of the first clock signal terminal CLK1, the output control circuit 300 is turned on, so that the second clock Signal terminal CLK2 High level charges the second pull-up node PU2 of the first stage second sub-shift register 200 to a high level, so that under the control of the high level of the second pull-up node PU2, the high level input from the clock signal terminal CLK3
  • the level is output to the second output terminal OUT2 (1) of the first-stage second sub-shift register 200 and the third output
  • the gate driving circuit 20 repeats the same operation as that of the display phase of the first frame, which is not repeated here.
  • the difference is that during the interval of the second frame, since the fourth clock signal line CLKD provides a high level, and the fourth clock signal line is connected to the first clock signal terminal of the first sub-shift register 100 of the second stage, Therefore, at this stage, the high level input from the clock signal terminal CLK4 is output to the second output terminal OUT2 (2) of the second-stage second sub-shift register 200 and the third output terminal OUT3 (2) of the composite output circuit 400.
  • the gate driving circuit outputs a driving signal for a sensing transistor in a sub-pixel unit in a display panel, and the driving signal is sequentially provided row by row.
  • the gate driving circuit outputs a driving signal for the first row of sub-pixel units of the display panel
  • the gate driving circuit outputs the sub-pixel unit for the second row of the display panel
  • the driving signal of the pixel unit is analogized in turn to complete the line-by-line sequential compensation.
  • the driving sequence described above may further include a fourth stage 4.
  • the total reset line TT_RST provides a high-level signal. Since the total reset line TT_RST is connected to the third reset terminal RST3, a high level is input to the third reset terminal RST3, so that the total reset circuit is turned on, so that the first The two pull-up nodes PU2 are connected to the first voltage terminal VGL, so the second pull-up nodes of all the shift register units can be reset.
  • each output terminal of the last-stage shift register unit can also be reset by a reset signal STD_D.
  • STD_D For example, before entering the display phase, high-level signals may be provided to the respective input terminals of the first-stage shift register unit through the trigger signals STV_D and STV_S.
  • the display device 1 includes a gate driving circuit 20 provided by an embodiment of the present disclosure.
  • the display device further includes a display panel 50 including a pixel array composed of a plurality of sub-pixel units 40, for example.
  • the display device 1 may further include a data driving circuit 30.
  • the data driving circuit 30 is used to provide a data signal to the pixel array;
  • the gate driving circuit 20 is used to provide a gate scanning signal to the pixel array.
  • the data driving circuit 30 is electrically connected to the pixel unit 40 through a data line 31, and the gate driving circuit 20 is electrically connected to the pixel unit 40 through a gate line 21.
  • the gate driving circuit 20 includes N cascaded shift register units 10, and the second output ends of the N cascaded shift register units 10 are respectively connected with N rows of sub-pixels.
  • Units 40 are connected one-to-one correspondingly to output display output signals to the N-row sub-pixel units on a row-by-row basis during the display stage to provide a scanning signal G1 for controlling the turning on of the switching transistor T1 shown in FIG. 1A during the interval stage
  • a random output signal is output to one of the N rows of sub-pixel units to provide a compensation scan signal G2 for controlling the turning on of the sensing transistor T2 shown in FIG. 1A.
  • the display device 1 in this embodiment may be any of: a liquid crystal panel, a liquid crystal television, a display, an OLED panel, an OLED television, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, etc. Products or parts with display capabilities.
  • the display device 1 may further include other conventional components such as a display panel, which is not limited in the embodiments of the present disclosure.
  • An embodiment of the present disclosure further provides a driving method of a gate driving circuit, such as a gate driving circuit for a display device.
  • the driving method of the gate driving circuit includes the following operations:
  • the second output terminal OUT2 of the second sub-shift register 200 outputs a display output signal
  • the second output terminal OUT2 of the second sub-shift register 200 outputs a random output signal.
  • the display phase of the driving method of the gate driving circuit 20 further includes: the third output terminal OUT3 outputs a display output signal; and the interval phase It also includes: the third output terminal OUT3 outputs a random output signal.

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Abstract

一种移位寄存器单元、栅极驱动电路、显示装置及驱动方法。该移位寄存器单元包括第一子移位寄存器(100)、第二子移位寄存器(200)和输出控制电路(300)。第一子移位寄存器(100)包括第一输出端(OUT1)以及用于控制第一输出端(OUT1)的第一控制节点(PU1)，且配置为在第一控制节点(PU1)的电平的控制下输出第一时钟信号；第二子移位寄存器(200)包括第二输出端(OUT2)以及用于控制第二输出端(OUT2)的第二控制节点(PU2)，且配置为在第二控制节点(PU2)的电平的控制下，使得第二输出端(OUT2)在显示阶段输出显示输出信号，在间隔阶段输出随机输出信号；输出控制电路(300)与第一子移位寄存器(100)和第二控制节点(PU2)连接，且配置为在输出控制信号的控制下对第二控制节点(PU2)的电平进行控制。该移位寄存器单元有助于实现显示面板的高分辨率和窄边框的设计。

Description

移位寄存器单元、栅极驱动电路及其驱动方法、显示装置
本申请要求于2018年7月3日递交的中国专利申请第201810719414.8号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种移位寄存器单元、栅极驱动电路及其驱动方法、显示装置。
背景技术
在显示技术领域，例如液晶显示面板或有机发光二极管(Organic Light Emitting Diode,OLED)显示面板的像素阵列通常包括多行栅线和与之交错的多列数据线。对栅线的驱动可以通过绑定的集成驱动电路实现。近几年随着非晶硅薄膜晶体管或氧化物薄膜晶体管制备工艺的不断提高，也可以将栅线驱动电路直接集成在薄膜晶体管阵列基板上构成GOA(Gate driver On Array)来对栅线进行驱动。例如，可以采用由多个级联的移位寄存器单元构成的GOA为像素阵列的多行栅线提供开关态电压信号，从而例如控制多行栅线依序打开，并且同时由数据线向像素阵列中对应行的像素单元提供数据信号，以在各像素单元形成显示图像的各灰阶所需要的灰度电压，进而显示一帧图像。目前的显示面板越来越多地采用GOA技术来对栅线进行驱动。GOA技术有助于实现显示面板的窄边框设计，并且可以降低显示面板的生产成本。
发明内容
本公开至少一实施例提供一种移位寄存器单元，包括第一子移位寄存器、第二子移位寄存器和输出控制电路。所述第一子移位寄存器包括第一输出端，且配置为在第一控制节点的电平的控制下输出第一时钟信号；所述第二子移位寄存器包括第二输出，且配置为在第二控制节点的电平的控制下，使得所述第二输出端在显示阶段输出显示输出信号，在间隔阶段输出随机输出信号； 所述输出控制电路与所述第一子移位寄存器和所述第二控制节点连接，且配置为在输出控制信号的控制下对所述第二控制节点的电平进行控制。
例如，本公开一实施例提供的移位寄存器单元，还包括复合输出电路和第三输出端。所述复合输出电路和所述输出控制电路、所述第二控制节点以及所述第三输出端连接，且配置为在所述第二控制节点的电平的控制下，使得所述第三输出端在所述显示阶段输出所述显示输出信号，在所述间隔阶段输出所述随机输出信号。
例如，在本公开一实施例提供的移位寄存器单元中，所述输出控制信号包括所述第一控制节点的电平和所述第一时钟信号，且所述输出控制电路包括第一晶体管和第二晶体管。所述第一晶体管的栅极和所述第一控制节点连接，所述第一晶体管的第一极和第一时钟信号端连接以接收所述第一时钟信号，所述第一晶体管的第二极和所述第二晶体管的栅极连接；所述第二晶体管的第一极和第二时钟信号端连接以接收第二时钟信号，或者所述第二晶体管的第一极和所述第二晶体管的栅极连接，所述第二晶体管的第二极和所述第二子移位寄存器的所述第二控制节点连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述输出控制电路还包括：第三晶体管，其中，所述第三晶体管的栅极和第三控制节点连接，所述第三晶体管的第一极和所述第二晶体管的栅极连接，所述第三晶体管的第二极和第一电压端连接以接收第一电压。
例如，在本公开一实施例提供的移位寄存器单元中，所述输出控制信号包括所述第一输出端输出的所述第一时钟信号，且所述输出控制电路包括第一晶体管。所述第一晶体管的栅极与所述第一子移位寄存器的所述第一输出端连接，所述第一晶体管的第一极与第二时钟信号端连接以接收第二时钟信号，所述第一晶体管的第二极与所述第二控制节点连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述复合输出电路包括第四晶体管。所述第四晶体管的栅极与所述第二控制节点连接，所述第四晶体管的第一极与第三时钟信号端连接以接收第三时钟信号，所述第四晶体管的第二极与所述第三输出端连接；其中，所述第三时钟信号包括所述显示输出信号和所述随机输出信号。
例如，在本公开一实施例提供的移位寄存器单元中，所述复合输出电路 还包括第五晶体管。所述第五晶体管的栅极和第四控制节点连接，所述第五晶体管的第一极和所述第三输出端连接，所述第五晶体管的第二极和第一电压端连接以接收第一电压。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一子移位寄存器包括第一输入电路、第一控制节点复位电路以及第一输出电路。所述第一输入电路配置为响应于第一输入信号对所述第一控制节点进行充电；所述第一控制节点复位电路配置为响应于第一复位信号对所述第一控制节点进行复位；所述第一输出电路配置为在所述第一控制节点的电平的控制下，将所述第一时钟信号输出至所述第一输出端。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一子移位寄存器还包括第一反相器电路、第一控制节点降噪电路和第一输出降噪电路。第一反相器电路配置为在所述第一控制节点的电平的控制下，对第三控制节点的电平进行控制；所述第一控制节点降噪电路配置为在所述第三控制节点的电平的控制下，对所述第一控制节点进行降噪；所述第一输出降噪电路配置为在所述第三控制节点的电平的控制下，对所述第一输出端进行降噪。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一子移位寄存器还包括第一防漏电电路。所述第一防漏电电路配置为在所述第一输出端输出的所述第一时钟信号的控制下，保持所述第一控制节点的高电位。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一防漏电电路包括第十一晶体管、第十二晶体管、第十三晶体管和第十四晶体管。所述第十一晶体管的栅极和第一输入端连接以接收所述第一输入信号，所述第十一晶体管的第一极和所述第十四晶体管的第二极连接，所述第十一晶体管的第二极和所述第一控制节点连接；所述第十二晶体管的栅极和第一复位端连接以接收所述第一复位信号，所述第十二晶体管的第一极和所述第十四晶体管的第二极连接，所述第十二晶体管的第二极和第一电压端连接以接收第一电压；所述第十三晶体管的栅极和所述第三控制节点连接，所述第十三晶体管的第一极和所述第十四晶体管的第二极连接，所述第十三晶体管的第二极和第一电压端连接以接收第一电压；第十四晶体管的栅极与所述第一输出端连接，所述第十四晶体管的第一极与第一时钟信号端连接以接收所述第一时钟信号。
例如，在本公开一实施例提供的移位寄存器单元中，所述第二子移位寄存器包括第二输入电路、第二控制节点复位电路以及第二输出电路。所述第二输入电路配置为响应于第二输入信号对所述第二控制节点进行充电；所述第二控制节点复位电路配置为响应于第二复位信号对所述第二控制节点进行复位；所述第二输出电路配置为在所述第二控制节点的电平的控制下，将第三时钟信号输出至所述第二输出端；其中，所述第三时钟信号包括所述显示输出信号和所述随机输出信号。
例如，在本公开一实施例提供的移位寄存器单元中，所述第二子移位寄存器包括第二反相器电路、第二控制节点降噪电路和第二输出降噪电路。第二反相器电路配置为在所述第二控制节点的电平的控制下，对第四控制节点的电平进行控制；所述第二控制节点降噪电路配置为在所述第四控制节点的电平的控制下，对所述第二控制节点进行降噪；所述第二输出降噪电路配置为在所述第四控制节点的电平的控制下，对所述第二输出端进行降噪。
例如，在本公开一实施例提供的移位寄存器单元中，所述第二子移位寄存器还包括第二防漏电电路。所述第二防漏电电路配置为在所述第二输出端输出的所述第三时钟信号的控制下，保持所述第二控制节点的高电位。
例如，在本公开一实施例提供的移位寄存器单元中，所述第二防漏电电路包括第二十六晶体管、第二十七晶体管、第二十八晶体管和第二十九晶体管。所述第二十六晶体管的栅极和第二输入端连接以接收所述第二输入信号，所述第二十六晶体管的第一极和所述第二十九晶体管的第二极连接，所述第二十六晶体管的第二极和所述第二控制节点连接；所述第二十七晶体管的栅极和第二复位端连接以接收所述第二复位信号，所述第二十七晶体管的第一极和所述第二十九晶体管的第二极连接，所述第二十七晶体管的第二极和第一电压端连接以接收第一电压；所述第二十八晶体管的栅极与所述第四控制节点连接，所述第二十八晶体管的第一极和所述第二十九晶体管的第二极连接，所述第二十八晶体管的第二极和第一电压端连接以接收第一电压；第二十九晶体管的栅极与所述第二输出端连接，所述第二十九晶体管的第一极与第三时钟信号端连接以接收所述第三时钟信号。
例如，本公开一实施例提供的移位寄存器单元，还包括总复位电路，其中，所述总复位电路配置为在所述第三复位信号的控制下，对所述第二控制 节点进行复位。
例如，在本公开一实施例提供的移位寄存器单元中，所述总复位电路包括第三十晶体管。所述第三十晶体管的栅极和第三复位端连接以接收所述第三复位信号，所述第三十晶体管的第一极和第一电压端连接以接收第一电压，所述第三十晶体管的第二极和所述第二控制节点连接。
本公开至少一实施例还提供一种栅极驱动电路，包括多个级联的本公开任一实施例提供的移位寄存器单元，所述输出控制电路均与所述第一子移位寄存器和所述第二子移位寄存器电连接；除第一级第一子移位寄存器外，其余各级第一子移位寄存器的第一输入端和上一级第一子移位寄存器的第一输出端连接；除最后一级第一子移位寄存器外，其余各级第一子移位寄存器的第一复位端和下一级第一子移位寄存器的第一输出端连接；除第一级第二子移位寄存器外，其余各级第二子移位寄存器的第二输入端和上一级第二子移位寄存器的第二输出端连接；除最后一级第二子移位寄存器外，其余各级第二子移位寄存器的第二复位端和下一级第二子移位寄存器的第二输出端连接。
例如，本公开一实施例提供的显示装置还包括显示面板，所述显示面板包括呈阵列排布的多个子像素单元，所述阵列包括N行，所述栅极驱动电路包括N个级联的移位寄存器单元，所述N个级联的移位寄存器单元的第二输出端分别与所述N行子像素单元一一对应连接，以在所述显示阶段向所述N行子像素单元逐行输出显示输出信号，在所述间隔阶段，向所述N行子像素单元中的其中一行输出随机输出信号，N为大于1的整数。
本公开至少一实施例还提供一种显示装置，包括本公开任一实施例提供的栅极驱动电路。
本公开至少一实施例还提供一种栅极驱动电路的驱动方法，包括：在显示阶段，所述第二子移位寄存器的第二输出端输出所述显示输出信号；在间隔阶段，所述第二子移位寄存器的所述第二输出端输出所述随机输出信号。
例如，本公开一实施例提供的驱动方法，在包括复合输出电路和第三输出端的情况下，所述驱动方法还包括：在显示阶段，所述第三输出端输出所述显示输出信号；在间隔阶段，所述第三输出端输出所述随机输出信号。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为一种像素电路的示意图；
图1B为一种像素电路工作时的信号时序图；
图2为本公开一些实施例提供的一种移位寄存器单元的示意图；
图3为本公开一些实施例提供的另一种移位寄存器单元的示意图；
图4A为本公开一些实施例提供的一种第一子移位寄存器的示意图；
图4B为本公开一些实施例提供的另一种第一子移位寄存器的示意图；
图4C为图4A中所示的第一子移位寄存器的一种具体实现示例的电路示意图；
图4D为图4B中所示的第一子移位寄存器的一种具体实现示例的电路示意图；
图5A为本公开一些实施例提供的一种第二子移位寄存器的示意图；
图5B为本公开一些实施例提供的另一种第二子移位寄存器的示意图；
图5C为图5A中所示的第二子移位寄存器的一种具体实现示例的电路示意图；
图5D为图5B中所示的第二子移位寄存器的一种具体实现示例的电路示意图；
图6为本公开一些实施例提供的又一种移位寄存器单元的示意图；
图7A为图6中所示的移位寄存器单元的一种具体实现示例的电路示意图；
图7B为图6中所示的移位寄存器单元的另一种具体实现示例的电路示意图；
图7C为图6中所示的移位寄存器单元的又一种具体实现示例的电路示意图；
图7D为图3中所示的移位寄存器单元的一种具体实现示例的电路示意图；
图7E为图3中所示的移位寄存器单元的另一种具体实现示例的电路示意 图；
图8为本公开一些实施例提供的一种栅极驱动电路的示意图；
图9为图8中所示的栅极驱动电路工作时的信号时序图；以及
图10为本公开一些实施例提供的一种显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
OLED显示装置中的像素电路一般采用矩阵驱动方式，根据每个像素单元中是否引入开关元器件分为有源矩阵(Active Matrix)驱动和无源矩阵(Passive Matrix)驱动。AMOLED在每一个像素的像素电路中都集成了一组薄膜晶体管和存储电容，通过对薄膜晶体管和存储电容的驱动控制，实现对流过OLED的电流的控制，从而使OLED根据需要发光。AMOLED显示装置中使用的基础像素电路通常为2T1C像素电路，即利用两个薄膜晶体管(Thin-film transistor，TFT)和一个存储电容Cst来实现驱动OLED发光的功能。
在通常的OLED显示面板中，需要通过补偿技术来提高显示质量。在对 OLED显示面板中的子像素单元进行补偿时，除了在子像素单元中设置像素补偿电路进行内部补偿外，还可以通过设置感测晶体管进行外部补偿。图1A示出了一种外部补偿的像素电路的示意图。如图1A所示，该像素电路包括开关晶体管T1、驱动晶体管T3、存储电容Cst、感测晶体管T2以及有机电致发光(EL)器件(即有机发光二极管)。例如，该感测晶体管T2可以实现补偿功能。例如，该开关晶体管T1的栅极连接扫描线以接收扫描信号G1；例如，该开关晶体管T1的源极连接到数据线以接收数据信号Vdata；该开关晶体管T1的漏极连接到驱动晶体管T3的栅极；驱动晶体管T3的漏极连接到第一电压端以接收第一电压VDD(高电压)，驱动晶体管T3的源极连接到EL器件的正极端；存储电容Cst的一端连接到开关晶体管T1的漏极以及驱动晶体管T3的栅极，另一端连接到驱动晶体管T3的源极；EL器件的负极端连接到第二电压端以接收第二电压Vss(低电压，例如接地电压)。例如，当通过扫描线施加扫描信号G1以开启开关晶体管T1时，数据驱动电路通过数据线输入的数据信号Vdata可以通过开关晶体管T1对存储电容Cst充电，由此可以将数据信号Vdata存储在存储电容Cst中，且该存储的数据信号Vdata可以控制驱动晶体管T3的导通程度，由此可以控制流过驱动晶体管T3以驱动EL器件发光的电流大小，即此电流决定该像素发光的灰阶。
如图1A所示，感测晶体管T2的第一端连接到驱动晶体管T3的源极，感测晶体管T2的第二端经由感测线与检测电路(例如包括电阻Rvc、电容Cvc以及例如模数转换(ADC)、放大器等器件)连接，感测晶体管T2的栅极接收补偿扫描信号G2。由此当施加补偿扫描信号G2以使得驱动晶体管T3导通之后，经由感测晶体管S0对检测电路充电，使得驱动晶体管T3的源极电位改变。当驱动晶体管T3的源极的电压Vs等于驱动晶体管T3的栅极电压Vg与驱动晶体管T3的阈值电压Vth的差值时，驱动晶体管T3截止。此时，可以在驱动晶体管T3截止后，再经由导通的感测晶体管T2从驱动晶体管T3的源极获取感测电压(也即，驱动晶体管T3截止后的源极的电压Vb)。在获取驱动晶体管T3截止后的源极的电压Vb之后，则可以获取驱动晶体管的阈值电压Vth＝Vdata-Vb，由此可以基于每个像素电路中驱动晶体管的阈值电压针对每个像素电路建立(也即，确定)补偿数据，进而可以实现显示面板各个子像素的阈值电压补偿功能。
在进行外部补偿时，由移位寄存器单元构成的栅极驱动电路需要分别向开关晶体管T1和感测晶体管T2提供扫描信号G1和补偿扫描信号G2，例如，在一帧的显示阶段(Display)提供用于控制开关晶体管开启的扫描信号G1，在一帧的间隔阶段(Blank)提供用于控制感测晶体管开启的补偿扫描信号G2。
图1B示出了该像素电路进行工作时的信号时序图。扫描信号G1为显示阶段提供的脉冲信号；补偿扫描信号G2为间隔阶段提供的脉冲信号。如图1B所示，在显示阶段和在间隔阶段所要求的扫描信号G1和补偿扫描信号G2的脉冲宽度不一致，这就要求移位寄存器单元具有脉冲宽度可调节功能，同时，还要保证间隔阶段所需的补偿扫描信号的脉冲周期和显示阶段所需的扫描信号的脉冲周期不一致并且互不干扰。
对于OLED显示面板，一种栅极驱动电路的移位寄存器单元包括检测单元(sense unit)、显示单元(scan unit)和输出两者复合脉冲的连接单元(或门电路或HIZ电路)。利用包括上述三个部分的电路结构，移位寄存器单元可以输出具有不同宽度和时序的两个波形组成的复合波形的输出脉冲，从而为开关晶体管和感测晶体管分别提供扫描信号G1和补偿扫描信号G2。但是，上述移位寄存器单元的电路结构复杂，且不可避免地会需要两个尺寸较大的输出驱动晶体管来增加负载能力，从而不利于实现显示面板的高分辨率和窄边框的设计。
本公开一些实施例提供一种移位寄存器单元，包括第一子移位寄存器、第二子移位寄存器和输出控制电路。第一子移位寄存器包括第一输出端以及用于控制第一输出端的第一控制节点，且配置为在第一控制节点的电平的控制下输出第一时钟信号；第二子移位寄存器包括第二输出端以及用于控制第二输出端的第二控制节点，且配置为在所述第二控制节点的电平的控制下，使得第二输出端在显示阶段输出显示输出信号，在间隔阶段输出随机输出信号；输出控制电路与第一子移位寄存器和第二控制节点连接，且配置为在输出控制信号的控制下对第二控制节点的电平进行控制。
本公开的一些实施例还提供对应于上述移位寄存器单元的栅极驱动电路、显示装置及驱动方法。
本公开上述实施例提供的移位寄存器单元、栅极驱动电路、显示装置以 及驱动方法，可以使得显示阶段和间隔阶段的输出信号通过同一个输出电路输出，因此只需要提供一个尺寸较大的输出驱动晶体管来驱动与栅线连接的负载即可，从而有助于简化移位寄存器单元以及栅极驱动电路的结构、实现显示面板的高分辨率和窄边框的设计。
下面结合附图对本公开的实施例及其示例进行详细说明。
图2为本公开一些实施例提供的一种移位寄存器单元的示意图。如图2所示，该移位寄存器单元10包括第一子移位寄存器100、第二子移位寄存器200和输出控制电路300。移位寄存器单元10可以级联得到栅极驱动电路，以用于驱动例如OLED显示面板。
例如，第一子移位寄存器100包括第一输出端(图中未示出)以及用于控制第一输出端的第一控制节点(图中未示出)，且配置为在第一控制节点的电平的控制下输出第一时钟信号。
例如，在本公开一些实施例中，移位寄存器单元还包括第二控制节点、第三控制节点和第四控制节点，且第一上拉节点为第一控制节点的一个示例，第二上拉节点为第二控制节点的一个示例，第一下拉节点为第三控制节点的一个示例，第二下拉节点为第四控制节点的一个示例，下面以第一控制节点为第一上拉节点，第二控制节点为第二上拉节点，第三控制节点为第一下拉节点，第四控制节点为第二下拉节点为例进行说明，但是本公开的实施例不限于此，以下实施例与此相同，不再赘述。
例如，第二子移位寄存器200包括第二输出端OUT2以及用于控制第二输出端OUT2的第二上拉节点PU2，且配置为在第二上拉节点PU2的电平的控制下，使得第二输出端OUT2在显示阶段输出显示输出信号，在间隔阶段(也叫消隐阶段)输出随机输出信号。例如，该随机输出信号可以用于外部补偿，例如，用于驱动图1A中所示的感测晶体管T2。
例如，输出控制电路300与第一子移位寄存器100和第二子移位寄存器200的第二上拉节点PU2连接，且配置为在输出控制信号的控制下对第二上拉节点PU2的电平进行控制，由此使得第二输出端OUT2在显示阶段输出显示输出信号，在间隔阶段输出随机输出信号。这样，由移位寄存器单元10级联得到的栅极驱动电路在显示阶段输出的显示输出信号以及在间隔阶段输出随机输出信号，且仅通过移位寄存器单元10的第二子移位寄存器200的第二 输出端输出，例如，该第二输出端OUT2既和上下级联的移位寄存器单元连接以提供移位输出信号，又通过栅线和显示面板中的其他负载(例如，像素电路)连接以用于驱动显示面板的工作，因此只需要提供一个尺寸较大的输出驱动晶体管(例如，该晶体管是控制第二输出端的输出晶体管)来驱动与其连接的栅线所连接的负载即可，从而有助于简化移位寄存器单元以及栅极驱动电路的结构、实现显示面板的高分辨率和窄边框的设计。
例如，用于输出控制电路300的输出控制信号可以包括第一子移位寄存器100的第一上拉节点的电平和第一时钟信号，或者可以包括第一输出端输出的第一时钟信号。例如，在输出控制信号包括第一子移位寄存器100的第一上拉节点的电平和第一时钟信号时，输出控制电路300可以和第一子移位寄存器100的第一上拉节点和提供第一时钟信号的第一时钟信号端(图中未示出)连接。例如，在输出控制信号包括第一输出端输出的第一时钟信号时，输出控制电路300可以和第一子移位寄存器100的第一输出端连接。
图3为本公开一些实施例提供的另一种移位寄存器单元的示意图。如图3所示，与图2所示的移位寄存器单元相比，该移位寄存器单元10还包括复合输出电路400和第三输出端OUT3。
复合输出电路400和输出控制电路300、第二上拉节点PU2以及第三输出端OUT3连接，且配置为在第二上拉节点PU2的电平的控制下，使得第三输出端OUT3在显示阶段输出显示输出信号，在间隔阶段输出随机输出信号。该第三输出端OUT输出的信号和第二输出端OUT2输出的信号相同。例如，该第二输出端OUT2用于和与其上下级联的第二子移位寄存器200连接以提供移位信号，而第三输出端OUT3则用于通过栅线和负载(例如，像素电路)连接，从而可以避免数据线传输的数据信号对该第二输出端OUT2输出的移位信号的串扰，从而保证了该多个级联的移位寄存器单元的输出信号的可靠性。相应地，在该实施例，同样只需要提供一个尺寸较大的输出驱动晶体管来增加负载能力即可，即和栅线连接的复合输出电路400中控制第三输出端OUT3输出的输出晶体管。由于第二输出端用于与其级联的移位寄存器单元的移位信号的输出，不需要通过栅线驱动与其连接的负载，因此，第二输出端的输出晶体管不需要较大的尺寸，从而有利于实现显示面板的窄边框设计。
本公开的实施例对于第一子移位寄存器的具体构造不作限定，可以采用 已知的能够实现移位寄存器单元的电路结构即可，例如包括输入电路、第一上拉节点、输出电路，输入电路控制第一上拉节点的电平，第一上拉节点控制输出电路以输出脉冲信号。图4A为图2或图3中所示的第一子移位寄存器100的一个示例的示意图。
如图4A所示，在一个示例中，第一子移位寄存器100可以包括第一输入电路110、第一控制节点复位电路120、第一输出电路130、第一控制节点降噪电路140、第一输出降噪电路150和第一反相器电路160。例如，在本公开一些实施例中，第一上拉节点复位电路为第一控制节点复位电路120的一个示例，第一上拉节点降噪电路为第一控制节点降噪电路140的一个示例，下面以第一控制节点复位电路120为第一上拉节点复位电路，第一控制节点降噪电路140为第一上拉节点降噪电路为例进行说明，但是本公开的实施例不限于此，以下实施例与此相同，不再赘述。
第一输入电路110配置为响应于第一输入信号对第一上拉节点PU1进行充电。例如，该第一输入电路110与第一输入端INT1、第二电压端VGH和第一上拉节点PU1连接，配置为在第一输入端INT1输入的信号的控制下使第一上拉节点PU1和第二电压端VGH电连接，从而可以使第二电压端输入的第二电压(例如，高电平信号)对第一上拉节点PU1的电位进行控制(例如，充电)，以使得第一上拉节点PU1的电压增加以控制第一输出电路130导通。需要注意的是，不限于此，该第一输入电路110还可以与第一输入端INT1和第一上拉节点PU1连接，配置为在第一输入端INT1输入的信号的控制下使第一上拉节点PU1和第一输入端INT1电连接，从而可以使第一输入端INT1输入的高电平信号对第一上拉节点PU1进行充电。
该第一上拉节点复位电路120配置为响应于第一复位信号对第一上拉节点PU1进行复位。例如，该第一上拉节点复位电路120可以配置为和第一复位端RST1、第一电压端VGL以及第一上拉节点PU1连接，从而可以在第一复位端RST1输入的复位信号的控制下，使得第一上拉节点PU1和下拉电压端(例如低电平信号或低电压端)电连接，该低电压端例如为第一电压端VGL，从而可以对第一上拉节点PU1进行下拉(例如，放电)复位。
该第一输出电路130配置为在第一上拉节点PU1的电平的控制下，将第一时钟信号端CLK1输入的第一时钟信号输出至第一输出端OUT1，作为该第 一子移位寄存器100的输出信号。例如，该第一输出电路130与第一上拉节点PU1、第一时钟信号端CLK1以及第一输出端OUT1连接，且配置为在第一上拉节点PU1的电平的控制下导通，使第一时钟信号端CLK1和第一输出端OUT1电连接，从而可以将第一时钟信号端CLK1输入的时钟信号输出至第一输出端OUT1。
第一上拉节点降噪电路140配置为在第一下拉节点PD1的电平的控制下，对第一上拉节点PU1进行降噪。例如，该第一上拉节点降噪电路140与第一上拉节点PU1、第一下拉节点PD1以及第一电压端VGL连接，以在第一下拉节点PD1的电平的控制下，使第一上拉节点PU1和第一电压端VGL电连接，从而对第一上拉节点PU1进行下拉降噪。
第一输出降噪电路150配置为在第一下拉节点PD1的电平的控制下，对第一输出端OUT1进行降噪。例如，该第一输出降噪电路150与第一下拉节点PD1、第一输出端OUT1以及第一电压端VGL连接，配置为在第一下拉节点PD1的电平的控制下，使第一输出端OUT1和第一电压端VGL电连接，从而对第一输出端OUT1进行下拉降噪。
该第一反相器电路160配置为在第一上拉节点PU1的电平的控制下，对第一下拉节点PD1的电平进行控制。例如，第一反相器电路160与第一上拉节点PU1和第一下拉节点PD1连接，且配置为当第一上拉节点PU1为高电平时将第一下拉节点PD1下拉为低电平，当第一上拉节点PU1为低电平时将第一下拉节点PD1上拉为高电平。例如，该第一反相器电路160可以为反相电路或其他任意可以实现该反相功能的电路。
例如，图4A中所示的第一子移位寄存器100在一个示例中可以具体实现为图4C所示的电路结构。在下面的说明中以各晶体管为N型晶体管为例进行说明，但并不构成对本公开实施例的限制。例如，N型晶体管响应于高电平信号而导通，响应于低电平信号而截止，以下实施例与此相同，不再赘述。
第一输入电路110可以实现为第六晶体管T6。第六晶体管T6的栅极和第一输入端INT1电连接以接收输入信号，第一极和第二电压端VGH电连接以接收第二电压，第二极配置为和第一上拉节点PU1连接，从而当第六晶体管T6由于第一输入端INT1接收到的导通信号(高电平信号)导通时，使得第一上拉节点PU1和第二电压端VGH电连接，以对第一上拉节点PU1进行 充电，使其处于高电平。
第一上拉节点复位电路120可以实现为第七晶体管T7。第七晶体管T7的栅极配置为和第一复位端RST1连接以接收第一复位信号，第一极配置为和第一上拉节点PU1连接，第二极配置为和第一电压端VGL连接以接收第一电压。第七晶体管T7由于第一复位信号而导通时，将第一上拉节点PU1和第一电压端VGL电连接，从而可以对第一上拉节点PU1进行复位，使其从高电平下降至低电平。
第一输出电路130可以实现为包括第八晶体管T8和第一存储电容C1。第八晶体管T8的栅极配置为和第一上拉节点PU1连接，第一极配置为和第一时钟信号端CLK1连接以接收第一时钟信号，第二极配置为和第一输出端OUT1连接；第一存储电容C1的第一极配置为和第八晶体管T8的栅极连接，第二极和第八晶体管T8的第二极连接。
第一上拉节点降噪电路140可以实现为第九晶体管T9。第九晶体管T9的栅极配置为和第一下拉节点PD1连接，第一极配置为和第一上拉节点PU1连接，第二极配置为和第一电压端VGL连接以接收第一电压。第九晶体管T9由于第一下拉节点PD1处于高电位时导通，将第一上拉节点PU1和第一电压端VGL连接，从而可以对第一上拉节点PU1下拉以实现降噪。
第一输出降噪电路150可以实现为第十晶体管T10。第十晶体管T10的栅极配置为和第一下拉节点PD1连接，第一极配置为和第一输出端OUT1连接，第二极配置为和第一电压端VGL连接以接收第一电压。第十晶体管T10由于第一下拉节点PD1处于高电位时导通，将第一输出端OUT1和第一电压端VGL连接，从而可以对第一输出端OUT1降噪。
当第一上拉节点PU1的电位维持在高电平时，存在一些晶体管(例如第六晶体管T6(当第六晶体管T6的栅极和第一极彼此均与第一输入端INT1连接时)、第七晶体管T7、第九晶体管T9晶体管)的第一极连接第一上拉节点PU1，而第二极连接低电平信号。即使当这些晶体管的栅极输入的是非导通信号的情况下，由于其第一极和第二极之间存在电压差，也可能出现漏电流的情况，从而使得移位寄存器单元10中对于第一上拉节点PU1的电位维持的效果变差。
针对上述问题，如图4B所示，在本公开的一个实施例中提供了一种用于 防漏电的移位寄存器单元10。如图4B所示，在另一个示例中，与图4A所示的示例相比，第一子移位寄存器100还可以包括第一防漏电电路170。需要注意的是，在第二子移位寄存器200中也存在相同的问题，且不再重复赘述。
例如，第一防漏电电路170配置为在第一输出端OUT1输出的作为输出信号的第一时钟信号的控制下，保持第一上拉节点PU1的高电位。例如，该第一防漏电电路170与第一时钟信号端CLK1、第一输出端OUT1、第一上拉节点复位电路120、第一上拉节点降噪电路140以及第一输入电路110连接，配置为在第一输出端OUT1输出的第一时钟信号的高电平的控制下，使得与第一上拉节点PU1相连的各个晶体管的源极和漏极同时为高电平，从而避免了第一上拉节点PU1的电平因为漏电而降低，以影响显示质量。
需要说明的是，本领域技术人员可以理解，根据本公开的实施例提供的具有防漏电功能的电路的实施例，可以根据实际情况选择第一子移位寄存器100中的一个或多个晶体管增加防漏电的电路结构。图4B仅示出了包括防漏电电路的一种示例性的电路结构，而不构成对本公开实施例的限制。
例如，图4B中所示的第一子移位寄存器100在一个示例中可以具体实现为图4D所示的电路结构。该第一子移位寄存器100与图4C中的第一子移位寄存器100的结构类似，区别在于增加实现第一防漏电电路170的晶体管。
例如，第一防漏电电路170可以实现为第十一晶体管T11、第十二晶体管T12、第十三晶体管T13和第十四晶体管T14。第十一晶体管T11的栅极和第一输入端INT1连接以接收第一输入信号，第十一晶体管T11的第一极和第十四晶体管T14的第二极以及第六晶体管T6的第二极连接，第十一晶体管T11的第二极和第一上拉节点PU1连接；第十二晶体管T12的栅极和第一复位端RST1连接以接收第一复位信号，第十二晶体管T12的第一极和第十四晶体管T14的第二极以及第七晶体管T7的第二极连接，第十二晶体管T12的第二极和第一电压端VGL连接以接收第一电压；第十三晶体管T13的栅极和第一下拉节点PD1连接，第十三晶体管T13的第一极和第十四晶体管T14的第二极以及第九晶体管T9的第二极连接，第十三晶体管T13的第二极和第一电压端VGL连接以接收第一电压；第十四晶体管T14的栅极与第一输出端OUT1连接，第十四晶体管T14的第一极与第一时钟信号端CLK1连接以接收第一时钟信号。当第一时钟信号端CLK1提供的第一时钟信号处于高电平状态，第 一上拉节点PU1也处于高电平状态时，第一输出端OUT1在第一上拉节点PU1的控制下输出第一时钟信号。此时，第十四晶体管T14在该第一输出端OUT1输出的作为输出信号的第一时钟信号的高电平的控制下导通，从而可以将第一时钟信号端CLK1与第十一晶体管T11、第十二晶体管T12、第十三晶体管T13、第六晶体管T6、第七晶体管T7以及第九晶体管T9的第二极连接，从而使得第六晶体管T6、第七晶体管T7以及第九晶体管T9的第一极与第二极均处于高电平状态，例如，第一极为第一上拉节点PU1的高电平，第二极为第一时钟信号的高电平，从而可以防止第一上拉节点PU1的电荷通过与其连接的第六晶体管T6、第七晶体管T7以及第九晶体管T9漏电。
需要注意的是，不限于图4A和图4B中所示的结构，该第一移位寄存器单元还可以是其他各种类型的移位寄存器单元，本公开的实施例对此不作限制。
需要说明的是，第一电压端VGL例如可以配置为保持输入直流低电平信号，例如，将该直流低电平信号称为第一电压，第二电压端VGH例如可以配置为保持输入直流高电平信号，例如，将该直流高电平信号称为第二电压，第一电压低于第二电压，以下各实施例与此相同，不再赘述。
同样，本公开的实施例对于第二子移位寄存器的具体构造不作限定，可以采用已知能够实现移位寄存器单元的电路结构即可，例如包括输入电路、第二上拉节点、输出电路，输入电路控制第二上拉节点的电平，第二上拉节点控制输出电路以输出脉冲信号。例如，第一子移位寄存器和第二子移位寄存器可以具有相同的构造，从而可以简化本公开实施例的移位寄存器单元的设计与制备工艺。图5A为图2或图3中所示的第二子移位寄存器200的一个示例的示意图。
如图5A所示，在一个示例中，第二子移位寄存器200可以包括第二输入电路210、第二控制节点复位电路(图中未示出)、第二输出电路230、第二控制节点降噪电路(图中未示出)、第二输出降噪电路250和第二反相器电路260。例如，在本公开一些实施例中，第二上拉节点复位电路220为第二控制节点复位电路的一个示例，第二上拉节点降噪电路240为第二控制节点降噪电路的一个示例，下面以第二控制节点复位电路为第二上拉节点复位电路220，第二控制节点降噪电路为第二上拉节点降噪电路240为例进行说明， 但是本公开的实施例不限于此，以下实施例与此相同，不再赘述。
第二输入电路210配置为响应于第二输入信号对第二上拉节点PU2进行充电。例如，该第二输入电路210与第二输入端INT2、第二电压端VGH和第二上拉节点PU2连接，配置为在第二输入端INT2输入的信号的控制下使第二上拉节点PU2和第二电压端VGH电连接，从而可以使第二电压端VGH输入的第二电压(例如，高电平信号)对第二上拉节点PU2进行充电，以使得第二上拉节点PU2的电压增加以控制第二输出电路230导通。需要注意的是，不限于此，该第二输入电路210还可以仅与第二输入端INT2和第二上拉节点PU2连接，配置为在第二输入端INT2输入的信号的控制下使第二上拉节点PU2和第二输入端INT2电连接，从而可以使第二输入端INT2输入的高电平信号对第二上拉节点PU2进行充电。
该第二上拉节点复位电路220配置为响应于第二复位信号对第二上拉节点PU2进行复位。例如，该第二上拉节点复位电路220可以配置为和第二复位端RST2、第一电压端VGL以及第二上拉节点PU2连接，从而可以在第二复位端RST2输入的复位信号的控制下，使得第二上拉节点PU2和低电平信号或低电压端电连接，该低电压端例如为第一电压端VGL，从而可以对第二上拉节点PU2进行下拉复位。
该第二输出电路230配置为在第二上拉节点PU2的电平的控制下，将第三时钟信号端CLK3输入的第三时钟信号输出至第二输出端OUT2，作为该第二子移位寄存器200的输出信号。例如，该第二输出电路230与第二上拉节点PU2、第三时钟信号端CLK3以及第二输出端OUT2连接，且配置为在第二上拉节点PU2的电平的控制下导通，使第三时钟信号端CLK3和第二输出端OUT2电连接，从而可以将第三时钟信号端CLK3输入的时钟信号输出至第二输出端OUT2。例如，该第三时钟信号包括具有不同的脉冲宽度和时序的显示输出信号和随机输出信号，例如，可以通过现场可编辑门阵列(Field－Programmable Gate Array，FPGA)实现将该两个不同的信号合成为第三时钟信号，该合成得到的第三时钟信号通过第二输出端OUT2输出，从而可以仅通过第二输出端OUT2输出该显示输出信号和随机输出信号。
第二上拉节点降噪电路240配置为在第二下拉节点PD2的电平的控制下，对第二上拉节点PU2进行降噪。例如，该第二上拉节点降噪电路240与第二 上拉节点PU2、第二下拉节点PD2以及第一电压端VGL连接，以在第二下拉节点PD2的电平的控制下，使第二上拉节点PU2和第一电压端VGL电连接，从而对第二上拉节点PU2进行下拉降噪。
第二输出降噪电路250配置为在第二下拉节点PD2的电平的控制下，对第二输出端OUT2进行降噪。例如，该第二输出降噪电路250与第二下拉节点PD2、第二输出端OUT2以及第一电压端VGL连接，且配置为在第二下拉节点PD2的电平的控制下，使第二输出端OUT2和第一电压端VGL电连接，从而对第二输出端OUT2进行下拉降噪。
该第二反相器电路260配置为在第二上拉节点PU2的电平的控制下，对第二下拉节点PD2的电平进行控制。例如，第二反相器电路260与第二上拉节点PU2和第二下拉节点PD2连接，且配置为当第二上拉节点PU2为高电平时将第二下拉节点PD2下拉为低电平，当第二上拉节点PU2为低电平时将第二下拉节点PD2上拉为高电平。例如，该第二反相器电路260可以为反相电路或其他任意可以实现该反相功能的电路。
例如，图5A中所示的第二子移位寄存器200在一个示例中可以具体实现为图5C所示的电路结构。在下面的说明中以各晶体管为N型晶体管为例进行说明，但这并不构成对本公开实施例的限制。
第二输入电路210可以实现为第二十一晶体管T21。第二十一晶体管T21的栅极和第二输入端INT2电连接以接收输入信号，第一极和第二电压端VGH电连接以接收第二电压，第二极配置为和第二上拉节点PU2连接，从而当第二十一晶体管T21由于第二输入端INT2接收到的导通信号(高电平信号)导通时，使得第二上拉节点PU2和第二电压端VGH电连接，以对第二上拉节点PU2进行充电，使其处于高电平。
第二上拉节点复位电路220可以实现为第二十二晶体管T22。第二十二晶体管T22的栅极配置为和第二复位端RST2连接以接收第二复位信号，第一极配置为和第二上拉节点PU2连接，第二极配置为和第一电压端VGL连接以接收第一电压。第二十二晶体管T22由于第二复位信号而导通时，将第二上拉节点PU2和第一电压端VGL电连接，从而可以对第二上拉节点PU2进行复位，使其从高电平下降至低电平。
第二输出电路230可以实现为包括第二十三晶体管T23和第二存储电容 C2。第二十三晶体管T23的栅极配置为和第二上拉节点PU2连接，第一极配置为和第三时钟信号端CLK3连接以接收第三时钟信号，第二极配置为和第二输出端OUT2连接；第二存储电容C2的第一极配置为和第二十三晶体管T23的栅极连接，第二极和第二十三晶体管T23的第二极连接。例如，在不包括复合输出电路时，该第二十三晶体管T23的尺寸较大，可以作为输出驱动晶体管与栅线连接，以驱动与该栅线相连的例如像素电路等负载；在包括复合输出电路时，复合输出电路作为尺寸较大的输出驱动晶体管，该第二十三晶体管T23则作为移位信号输出的晶体管，不需要较大尺寸。
第二上拉节点降噪电路240可以实现为第二十四晶体管T24。第二十四晶体管T24的栅极配置为和第二下拉节点PD2连接，第一极配置为和第二上拉节点PU2连接，第二极配置为和第一电压端VGL连接以接收第一电压。第二十四晶体管T24由于第二下拉节点PD2处于高电位时导通，将第二上拉节点PU2和第一电压端VGL连接，从而可以对第二上拉节点PU2下拉以实现降噪。
第二输出降噪电路250可以实现为第二十五晶体管T25。第二十五晶体管T25的栅极配置为和第二下拉节点PD2连接，第一极配置为和第二输出端OUT2连接，第二极配置为和第一电压端VGL连接以接收第一电压。第二十五晶体管T25由于第二下拉节点PD2处于高电位时导通，将第二输出端OUT2和第一电压端VGL连接，从而可以对第二输出端OUT2降噪。
如图5B所示，在另一个示例中，与图5A所示的示例相比，第二子移位寄存器200还可以包括第二防漏电电路270。
第二防漏电电路270配置为在第二输出端OUT2输出的第二时钟信号的控制下，保持第二上拉节点PU2的高电位。例如，该第二防漏电电路270与第三时钟信号端CLK3、第二输出端OUT2、第二上拉节点复位电路220、第二上拉节点降噪电路240以及第二输入电路210连接，配置为在第二输出端OUT2输出的第三时钟信号的高电平的控制下，使得与第二上拉节点PU2相连的各个晶体管的源极和漏极同时为高电平，从而避免了第二上拉节点PU2的电平因为漏电而降低，以影响显示质量。
例如，图5B中所示的第二子移位寄存器200在一个示例中可以具体实现为图5D所示的电路结构。该第二子移位寄存器200与图5C中的第二子移位 寄存器200的结构类似，区别在于增加了实现第二防漏电电路270的晶体管。
第二防漏电电路270可以实现为第二十六晶体管T26、第二十七晶体管T27、第二十八晶体管T28和第二十九晶体管T29。第二十六晶体管T26的栅极和第二输入端INT2连接以接收第二输入信号，第二十六晶体管T26的第一极和第二十九晶体管T29的第二极以及第二十一晶体管T21的第二极连接，第二十六晶体管T26的第二极和第二上拉节点PU2连接；第二十七晶体管T27的栅极和第二复位端RST2连接以接收第二复位信号，第二十七晶体管T27的第一极和第二十九晶体管T29的第二极以及第二十二晶体管T22的第二极连接，第二十七晶体管T27的第二极和第一电压端VGL连接以接收第一电压；第二十八晶体管T28的栅极与第二下拉节点PD2连接，第二十八晶体管T28的第一极和第二十九晶体管T29的第二极以及第二十四晶体管T24的第二极连接，第二十八晶体管T28的第二极和第一电压端VGL连接以接收第一电压；第二十九晶体管T29的栅极与第二输出端OUT2连接，第二十九晶体管T29的第一极与第三时钟信号端CLK3连接以接收第三时钟信号。该第二防漏电电路270的工作原理与图4D中所示的第一防漏电电路170的工作原理类似，在此不再赘述。
需要说明的是，本领域技术人员可以理解，根据本公开的实施例提供的具有防漏电功能的电路的实施例，可以根据实际情况选择第二子移位寄存器200中的一个或多个晶体管增加防漏电的电路结构。图5B仅示出了包括防漏电电路的一种示例性的电路结构，而不构成对本公开实施例的限制。
需要注意的是，不限于图5A和图5B中所示的结构，该第二移位寄存器单元还可以是其他各种类型的移位寄存器单元，本公开的实施例对此不作限制。
图6为本公开一些实施例提供的另一种移位寄存器单元的示意图。如图6所示，在图3所示的示例的基础上，该移位寄存器单元10还可以包括总复位电路500。例如，该总复位电路500配置为在第三复位信号的控制下，对第二上拉节点PU2进行复位，同时，对复合输出电路400以及第三输出端OUT3进行复位，从而保证了显示面板的对比度。
例如，图6中所示的移位寄存器单元10在一个示例中可以具体实现为图7A或者如图7B所示的电路结构。在下面的说明中以各晶体管为N型晶体管 为例进行说明，但并不构成对本公开实施例的限制。需要注意的是，第一子移位寄存器100可以采用图4D中所示的结构，第二子移位寄存器200可以采用图5D中所示的结构，在此不再赘述。例如，在该示例中，输出控制信号包括第一上拉节点PU1的电平和第一时钟信号。
如图7A所示，输出控制电路300例如可以实现为第一晶体管T1和第二晶体管T2。第一晶体管T1的栅极和第一上拉节点PU1连接，第一晶体管T1的第一极和第一时钟信号端CLK1连接以接收第一时钟信号，第一晶体管T1的第二极和第二晶体管T2的栅极连接；第二晶体管T2的第一极和第二时钟信号端CLK2连接以接收第二时钟信号，或者如图7B所示第二晶体管T2的第一极和第二晶体管T2的栅极连接。第二晶体管T2的第二极和第二子移位寄存器200的第二上拉节点PU2连接，从而输出控制电路300可以对第二上拉节点PU2的电平进行控制，以控制第二输出端OUT2和第三输出端OUT3的在显示阶段输出显示输出信号，在间隔阶段输出随机输出信号。
例如，该输出控制电路300还可以包括第三晶体管T3。第三晶体管T3的栅极和第一下拉节点PD1连接，第三晶体管T3的第一极和第二晶体管T2的栅极连接，第三晶体管T3的第二极和第一电压端VGL连接以接收第一电压，从而实现对第二晶体管T2的栅极的下拉复位。
例如，该复合输出电路400可以实现为第四晶体管T4。第四晶体管T4的栅极与第二上拉节点PU2连接，第四晶体管T4的第一极与第三时钟信号端CLK3连接以接收第三时钟信号，第四晶体管T4的第二极与第三输出端OUT3连接。例如，该第三时钟信号包括显示输出信号和随机输出信号。例如，该第四晶体管T4为通过栅线与负载连接的输出驱动晶体管，即驱动与栅线连接的例如像素电路的发光，因此，该第四晶体管T4可以设计得尺寸较大，从而具有增加的驱动能力。
例如，该复合输出电路400还可以包括第五晶体管T5。第五晶体管T5的栅极和第二下拉节点PD2连接，第五晶体管T5的第一极和第三输出端OUT3连接，第五晶体管T5的第二极和第一电压端VGL连接以接收第一电压，从而在第五晶体管T5响应于第二下拉节点PD2的电平导通时，使得第三输出端OUT3与第一电压端VGL连接，从而实现对第三输出端OUT3的复位。
例如，总复位电路500可以实现为第三十晶体管T30。第三十晶体管T30的栅极和第三复位端RST3连接以接收第三复位信号，第三十晶体管T30的第一极和第一电压端VGL连接以接收第一电压，第三十晶体管T30的第二极和第二上拉节点PU2连接。例如，栅极驱动电路中级联的移位寄存器单元的总复位电路500都与第三复位端RST3连接，从而通过该第三复位端RST3可以实现在显示阶段和间隔阶段输出结束后，对所有的移位寄存器单元10的第二上拉节点PU2进行复位。
例如，图6中所示的移位寄存器单元10在另一个示例中可以具体实现为图7C所示的电路结构。例如，该示例的移位寄存器单元10的电路结构与图7A中所示的移位寄存器单元的电路结构类似，但是区别在于：在该示例中，输出控制信号包括第一输出端OUT1输出的所述第一时钟信号，且该输出控制电路300实现为第一晶体管T1。第一晶体管T1的栅极与第一子移位寄存器100的第一输出端OUT1连接，第一晶体管T1的第一极与第二时钟信号端CLK2连接以接收第二时钟信号，第一晶体管T1的第二极与第二上拉节点PU2连接，即第一晶体管T1响应于第一输出端OUT1输出的第一时钟信号导通，从而对第二上拉节点PU2的电平进行控制。
尽管以上仅示出了移位寄存器单元包括两个、三个输出端的示例，本领域技术人员可以理解，根据本公开的描述，可以根据实际情况设置更多个输出端，上述示例不应构成对本公开保护范围的限制。
图7D为图3中所示的移位寄存器单元的一种具体实现示例的电路示意图。例如，在图7C所示的电路结构的基础上，该移位寄存器单元可以省略总复位电路500，即省略第三十晶体管T30，因此第二上拉节点PU2可以在第一晶体管T1导通且第二时钟信号端CLK2提供低电平时，通过第一晶体管T1进行复位放电，从而使得电路简洁，减少电路在显示面板上的占用面积。需要注意的是，图7A中的所示的移位寄存器单元也可以省略总复位电路500，其原理与图7C所示的电路结构的原理类似，在此不再赘述。
图7E为图3中所示的移位寄存器单元的另一种具体实现示例的电路示意图。例如，在图7D所示的电路结构的基础上，由于第一晶体管T1与第二上拉节点PU2连接，可能产生第二上拉节点PU2的电平通过第一晶体管T1漏电的风险，因此，该示例中的移位寄存器单元中的第二防漏电电路270还可 以包括第三十一晶体管T31。第三十一晶体管T31的栅极和第一输出端OUT1连接，第一极和第一晶体管T1的第二极以及第二十九晶体管T29的第二极连接，第二极和第二上拉节点PU2连接。需要说明的是，该示例中的第二防漏电电路的工作原理与第一防漏电电路170的工作原理类似，在此不再赘述。需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
另外，在本公开的实施例提供的移位寄存器单元中的晶体管均以N型晶体管为例进行说明，此时，晶体管的第一极是漏极，第二极是源极。需要说明的是，本公开包括但不限于此。例如，本公开的实施例提供的移位寄存器单元中的一个或多个晶体管也可以采用P型晶体管，此时，晶体管第一极是源极，第二极是漏极，只需将选定类型的晶体管的各极的极性按照本公开的实施例中的相应晶体管的各极的极性相应连接即可。当采用N型晶体管时，可以采用氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)作为薄膜晶体管的有源层，相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为N型薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及防止漏电流。
需要注意的是，在本公开的一些实施例中，例如，当各个电路实现为P型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如导通)；术语“下拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如截止)。
又例如，当各个电路实现为N型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如截止)。
需要注意的是，在本公开的各个实施例的说明中，第一上拉节点PU1、第一下拉节点PD1、第二上拉节点PU2、第二下拉节点PD2并非表示实际存在的部件，而是表示电路图中相关电路连接的汇合点。
本公开上述实施例提供的移位寄存器单元，可以使得显示阶段和间隔阶段的输出信号仅通过第二输出电路或复合输出电路输出至栅线，因此只需要一个尺寸较大的输出驱动晶体管来驱动与栅线连接的负载即可，从而有助于实现显示面板的高分辨率和窄边框的设计。
本公开的实施例提供一种栅极驱动电路20，如图8所示，该栅极驱动电路20包括第一时钟信号线CLKA、第二时钟信号线CLKB、第三时钟信号线CLKC、第四时钟信号线CLKD、第五时钟信号线CLKE以及多个级联的移位寄存器单元10。例如，该移位寄存器单元10可以采用上述实施例中提供的任一移位寄存器单元。下面以采用图3中所示的移位寄存器单元构成的栅极驱动电路为例进行说明，其他类型的栅极驱动电路的工作原理与此类似，在此不再赘述。
例如，如图8所示，每个移位寄存器单元10包括第一子移位寄存器100、第二子移位寄存器200、输出控制电路300以及复合输出电路400。例如，每个第一子移位寄存器100与输出控制电路300连接，输出控制电路300与第二子移位寄存器200的第二上拉节点PU2以及复合输出电路400连接。该栅极驱动电路20可以采用与薄膜晶体管同样制程的工艺直接集成在显示装置的阵列基板上，实现逐行扫描驱动功能。例如，在本示例中，第一子移位寄存器100可以采用图4D中的电路结构，第二子移位寄存器200可以采用图5D中的电路结构。
例如，如图8所示，该移位寄存器单元10的每个中的第一子移位寄存器100还包括第一时钟信号端CLK1，且配置为和第一时钟信号线CLKA以及第二时钟信号线CLKB连接以接收时钟信号。第一时钟信号线CLKA和第2m-1(m为大于0的整数)级第一子移位寄存器的第一时钟信号端CLK1连接，第二时钟信号线CLKB和第2m级第一子移位寄存器的第一时钟信号端CLK1连接。例如，该移位寄存器单元10的每个中的第二子移位寄存器200以及复合输出电路400还包括第三时钟信号端CLK3，且配置为和第三时钟信号线CLKC以及第四时钟信号线CLKD连接以接收时钟信号。第三时钟信号线 CLKC和第2m-1级第二子移位寄存器以及复合输出电路400的第三时钟信号端CLK3连接，第四时钟信号线CLKD和第2m级第二子移位寄存器以及复合输出电路400的第三时钟信号端CLK3连接。例如，该移位寄存器单元10的每个中的输出控制电路300还包括第二时钟信号端CLK2，且配置为和第五时钟信号线CLKE连接以接收第二时钟信号。
需要说明的是，图8中所示的OUT1(N)表示第N(N为大于1的整数)级第一子移位寄存器的第一输出端，OUT1(N+1)表示第N+1级第一子移位寄存器的第一输出端......；图8中所示的OUT2(N)表示第N(N为大于1的整数)级第二子移位寄存器的第二输出端，OUT2(N+1)表示第N+1级第二子移位寄存器的第二输出端......；图8中所示的OUT3(N)表示第N(N为大于1的整数)级第三输出端，OUT3(N+1)表示第N+1级第三输出端......。以下各实施例中的附图标记与此类似，不再赘述。
例如，如图8所示，输出控制电路300连接到第一子移位寄存器100和第二子移位寄存器200之间；除第一级第一子移位寄存器外，其余各级第一子移位寄存器的第一输入端INT1和上一级第一子移位寄存器的第一输出端OUT1连接；除最后一级第一子移位寄存器外，其余各级第一子移位寄存器的第一复位端RST1和下一级第一子移位寄存器的第一输出端OUT1连接；除第一级第二子移位寄存器外，其余各级第二子移位寄存器的第二输入端INT2和上一级第二子移位寄存器的第二输出端OUT2连接；除最后一级第二子移位寄存器外，其余各级第二子移位寄存器的第二复位端RST2和下一级第二子移位寄存器的第二输出端OUT2连接。
例如，如图8所示，该栅极驱动电路20还可以包括时序控制器900。例如，该时序控制器900可以被配置为和第一时钟信号线CLKA、第二时钟信号线CLKB、第三时钟信号线CLKC、第四时钟信号线CLKD以及第五时钟信号线CLKE连接，以向各移位寄存器单元提供时钟信号、触发信号以及复位信号。
例如，在移位寄存器单元包括总复位电路500时，该栅极驱动电路还包括总复位线(图中未示出)，配置为向第三复位端提供第三复位信号以对栅极驱动电路的所有的第二上拉节点进行复位。
需要注意的是，根据不同的配置，该栅极驱动电路10还可以包括四条、 六条或八条时钟信号线，时钟信号线的条数视具体情况而定，本公开的实施例在此不作限定。
需要说明的是，当采用本公开的实施例提供的栅极驱动电路20驱动一显示面板时，可以将该栅极驱动电路20设置于显示面板的一侧。例如，该显示面板包括多行栅线，栅极驱动电路20中的各级移位寄存器单元的输出端可以配置为依序和该多行栅线连接，以用于输出栅极扫描信号。需要说明的是，还可以分别在显示面板的两侧设置该栅极驱动电路20，以实现双边驱动，本公开的实施例对栅极驱动电路20的设置方式不作限定。例如，可以在显示面板的一侧设置栅极驱动电路20以用于驱动奇数行栅线，而在显示面板的另一侧设置栅极驱动电路20以用于驱动偶数行栅线。
图9为图8中所示的栅极驱动电路工作时的信号时序图。下面结合图9所示的信号时序图，对图8中所示的栅极驱动电路20的工作原理进行说明，并且这里以各个晶体管为N型晶体管为例进行说明，但是本公开的实施例不限于此。
如图9所示，每帧包括显示阶段D和间隔阶段S共两个阶段。在第X(X为大于0的整数)帧的显示阶段D中，对栅极驱动电路中移位寄存器单元的工作过程描述如下。需要注意的是，其余各帧的工作过程与此类此，不再赘述。
在第一阶段1，第三时钟信号线CLKC提供高电平，例如，该高电平为显示输出信号，由于第N级第二子移位寄存器200和复合输出电路400的第三时钟信号端CLK3与第三时钟信号线CLKC连接，所以在此阶段，第N级第三时钟信号端CLK3输入高电平；又由于第N级第二子移位寄存器的第二上拉节点PU2_N为高电平，所以在第二上拉节点PU2_N的高电平的控制下，第三时钟信号端CLK3输入的高电平输出至第N级第二子移位寄存器200的第二输出端OUT2(N)和复合输出电路400的第三输出端OUT3(N)。
在第二阶段2，第四时钟信号线CLKD提供高电平，由于第N+1级第二子移位寄存器200和复合输出电路400的第三时钟信号端CLK3与第四时钟信号线CLKD连接，所以在此阶段，第N+1级第三时钟信号端CLK3输入高电平；又由于第N+1级第二子移位寄存器的第二上拉节点PU2_N+1为高电平，所以在第二上拉节点PU2_N+1的高电平的控制下，第三时钟信号端CLK3 输入的高电平输出至第N+1级第二子移位寄存器200的第二输出端OUT2(N+1)和复合输出电路400的第三输出端OUT3(N+1)。
在第1帧的间隔阶段S中，对栅极驱动电路中移位寄存器单元的工作过程描述如下。例如，在该示例中，为了描述清楚、简洁，N＝2，需要注意的是，本公开的实施例对此不作限制。
在第三阶段3，第一时钟信号线CLKA提供高电平，由于第1级第一子移位寄存器的第一时钟信号端CLK1与第一时钟信号线CLKA连接，所以，在此阶段，第一时钟信号端CLK1输入高电平；同时，第五时钟信号线CLKE提供高电平，由于第二时钟信号端CLK2与第五时钟信号线CLKE连接，所以，在此阶段，第二时钟信号端CLK2输入高电平；第三时钟信号线CLKC提供高电平，由于第二子移位寄存器200和复合输出电路400的第三时钟信号端CLK3与第三时钟信号线CLKC连接，所以在此阶段，第三时钟信号端CLK3输入高电平，例如，该高电平为随机输出信号，不同于第一阶段中第三时钟信号线CLKC的高电平；又由于第1级第一子移位寄存器100的第一上拉节点PU1为高电平，所以在第一上拉节点PU1以及第一时钟信号端CLK1的高电平的控制下，该输出控制电路300导通，从而使得第二时钟信号端CLK2提供的高电平将第1级第二子移位寄存器200的第二上拉节点PU2充电至高电平，以在第二上拉节点PU2的高电平的控制下，时钟信号端CLK3输入的高电平输出至第1级第二子移位寄存器200的第二输出端OUT2(1)和复合输出电路400的第三输出端OUT3(1)。
需要注意的是，在第2帧的显示时段中，栅极驱动电路20重复和第一帧的显示阶段相同的操作，这里不再赘述。不同的是，在第2帧的间隔阶段，由于第四时钟信号线CLKD提供高电平，且第四时钟信号线和第2级的第一子移位寄存器100的第一时钟信号端连接，所以在此阶段，时钟信号端CLK4输入的高电平输出至第2级第二子移位寄存器200的第二输出端OUT2(2)和复合输出电路400的第三输出端OUT3(2)。
如上所述，在每一帧的间隔阶段，栅极驱动电路输出用于显示面板中子像素单元中的感测晶体管的驱动信号，且该驱动信号是逐行顺序提供的。例如，在第一帧的间隔阶段，栅极驱动电路输出用于显示面板第一行子像素单元的驱动信号，在第二帧的间隔阶段，栅极驱动电路输出用于显示面板第二 行子像素单元的驱动信号，依次类推，完成逐行顺序补偿。
后续在第3帧、第4帧、第5帧等更多阶段中对栅极驱动电路的驱动可以参考上述描述，这里不再赘述。
例如，在包括总复位电路500的情况下，上述驱动时序还可以包括第四阶段4。
在第四阶段4，总复位线TT_RST提供高电平信号，由于总复位线TT_RST与第三复位端RST3连接，所以第三复位端RST3输入高电平，使得总复位电路导通，从而使得第二上拉节点PU2与第一电压端VGL连接，因此可以对全部的移位寄存器单元的第二上拉节点进行复位。
例如，在每帧显示阶段结束后，还可以通过复位信号STD_D对最后一级移位寄存器单元的各个输出端进行复位。例如，在进入显示阶段之前，可以通过触发信号STV_D以及STV_S对第一级移位寄存器单元的各个输入端提供高电平信号。
本公开一些实施例还提供一种显示装置1，如图10所示，该显示装置1包括本公开实施例提供的栅极驱动电路20。该显示装置还包括显示面板50，该显示面板50包括由多个子像素单元40构成的像素阵列，例如。例如，该显示装置1还可以包括数据驱动电路30。数据驱动电路30用于提供数据信号给像素阵列；栅极驱动电路20用于提供栅极扫描信号给像素阵列。数据驱动电路30通过数据线31与像素单元40电连接，栅极驱动电路20通过栅线21与像素单元40电连接。
例如，如图8和图10所示，栅极驱动电路20包括N个级联的移位寄存器单元10，该N个级联的移位寄存器单元10的第二输出端分别与N行子像素单元40一一对应连接，以在显示阶段向该N行子像素单元逐行输出显示输出信号，以提供用于控制图1A中所示的开关晶体管T1开启的扫描信号G1，在所述间隔阶段向该N行子像素单元中的其中一行输出随机输出信号，以提供用于控制图1A中所示的感测晶体管T2开启的补偿扫描信号G2。
需要说明的是，本实施例中的显示装置1可以为：液晶面板、液晶电视、显示器、OLED面板、OLED电视、电子纸显示装置、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置1还可以包括显示面板等其他常规部件，本公开的实施例对此不作限定。
本公开的实施例提供的显示装置1的技术效果可以参考上述实施例中关于栅极驱动电路20的相应描述，这里不再赘述。
需要说明的是，为表示清楚、简洁，并没有给出该显示装置1的全部结构。为实现显示装置的必要功能，本领域技术人员可以根据具体应用场景进行设置其他未示出的结构，本发明的实施例对此不做限制。
本公开一实施例还提供一种栅极驱动电路的驱动方法，例如用于显示装置的栅极驱动电路，例如，该栅极驱动电路的驱动方法包括如下操作：
在显示阶段，第二子移位寄存器200的第二输出端OUT2输出显示输出信号；
在间隔阶段，第二子移位寄存器200的第二输出端OUT2输出随机输出信号。
例如，在移位寄存器单元10包括复合输出电路400和第三输出端OUT3的情况下，该栅极驱动电路20的驱动方法的显示阶段还包括：第三输出端OUT3输出显示输出信号；间隔阶段还包括：第三输出端OUT3输出随机输出信号。
需要说明的是，关于该驱动方法的详细描述以及技术效果可以参考本公开的实施例中对于栅极驱动电路20的工作原理以及技术效果的描述，这里不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (22)

  1. 一种移位寄存器单元，包括第一子移位寄存器、第二子移位寄存器和输出控制电路；
    所述第一子移位寄存器包括第一输出端，且配置为在第一控制节点的电平的控制下输出第一时钟信号；
    所述第二子移位寄存器包括第二输出端，且配置为在第二控制节点的电平的控制下，使得所述第二输出端在显示阶段输出显示输出信号，在间隔阶段输出随机输出信号；
    所述输出控制电路与所述第一子移位寄存器和所述第二控制节点连接，且配置为在输出控制信号的控制下对所述第二控制节点的电平进行控制。
  2. 根据权利要求1所述的移位寄存器单元，还包括复合输出电路和第三输出端；其中，
    所述复合输出电路和所述输出控制电路、所述第二控制节点以及所述第三输出端连接，且配置为在所述第二控制节点的电平的控制下，使得所述第三输出端在所述显示阶段输出所述显示输出信号，在所述间隔阶段输出所述随机输出信号。
  3. 根据权利要求1或2所述的移位寄存器单元，其中，所述输出控制信号包括所述第一控制节点的电平和所述第一时钟信号，所述输出控制电路包括第一晶体管和第二晶体管；其中，
    所述第一晶体管的栅极和所述第一控制节点连接，所述第一晶体管的第一极和第一时钟信号端连接以接收所述第一时钟信号，所述第一晶体管的第二极和所述第二晶体管的栅极连接；
    所述第二晶体管的第一极和第二时钟信号端连接以接收第二时钟信号，或者所述第二晶体管的第一极和所述第二晶体管的栅极连接，所述第二晶体管的第二极和所述第二子移位寄存器的所述第二控制节点连接。
  4. 根据权利要求3所述的移位寄存器单元，其中，所述输出控制电路还包括：
    第三晶体管，其中，所述第三晶体管的栅极和第三控制节点连接，所述第三晶体管的第一极和所述第二晶体管的栅极连接，所述第三晶体管的第二 极和第一电压端连接以接收第一电压。
  5. 根据权利要求1或2所述的移位寄存器单元，其中，所述输出控制信号包括所述第一输出端输出的所述第一时钟信号，所述输出控制电路包括：
    第一晶体管，其中，所述第一晶体管的栅极与所述第一子移位寄存器的所述第一输出端连接，所述第一晶体管的第一极与第二时钟信号端连接以接收第二时钟信号，所述第一晶体管的第二极与所述第二控制节点连接。
  6. 根据权利要求2所述的移位寄存器单元，其中，所述复合输出电路包括：
    第四晶体管，其中，所述第四晶体管的栅极与所述第二控制节点连接，所述第四晶体管的第一极与第三时钟信号端连接以接收第三时钟信号，所述第四晶体管的第二极与所述第三输出端连接；
    其中，所述第三时钟信号包括所述显示输出信号和所述随机输出信号。
  7. 根据权利要求6所述的移位寄存器单元，其中，所述复合输出电路还包括：
    第五晶体管，其中，所述第五晶体管的栅极和第四控制节点连接，所述第五晶体管的第一极和所述第三输出端连接，所述第五晶体管的第二极和第一电压端连接以接收第一电压。
  8. 根据权利要求1-7任一所述的移位寄存器单元，其中，所述第一子移位寄存器包括第一输入电路、第一控制节点复位电路以及第一输出电路；其中，
    所述第一输入电路配置为响应于第一输入信号对所述第一控制节点进行充电；
    所述第一控制节点复位电路配置为响应于第一复位信号对所述第一控制节点进行复位；
    所述第一输出电路配置为在所述第一控制节点的电平的控制下，将所述第一时钟信号输出至所述第一输出端。
  9. 根据权利要求8所述的移位寄存器单元，其中，所述第一子移位寄存器还包括第一反相器电路、第一控制节点降噪电路和第一输出降噪电路；其中，
    所述第一反相器电路配置为在所述第一控制节点的电平的控制下，对第 三控制节点的电平进行控制；
    所述第一控制节点降噪电路配置为在所述第三控制节点的电平的控制下，对所述第一控制节点进行降噪；
    所述第一输出降噪电路配置为在所述第三控制节点的电平的控制下，对所述第一输出端进行降噪。
  10. 根据权利要求9所述的移位寄存器单元，其中，所述第一子移位寄存器还包括第一防漏电电路；其中，
    所述第一防漏电电路配置为在所述第一输出端输出的所述第一时钟信号的控制下，保持所述第一控制节点的高电位。
  11. 根据权利要求10所述的移位寄存器单元，其中，所述第一防漏电电路包括第十一晶体管、第十二晶体管、第十三晶体管和第十四晶体管；其中，
    所述第十一晶体管的栅极和第一输入端连接以接收所述第一输入信号，所述第十一晶体管的第一极和所述第十四晶体管的第二极连接，所述第十一晶体管的第二极和所述第一控制节点连接；
    所述第十二晶体管的栅极和第一复位端连接以接收所述第一复位信号，所述第十二晶体管的第一极和所述第十四晶体管的第二极连接，所述第十二晶体管的第二极和第一电压端连接以接收第一电压；
    所述第十三晶体管的栅极和所述第三控制节点连接，所述第十三晶体管的第一极和所述第十四晶体管的第二极连接，所述第十三晶体管的第二极和所述第一电压端连接以接收所述第一电压；
    第十四晶体管的栅极与所述第一输出端连接，所述第十四晶体管的第一极与第一时钟信号端连接以接收所述第一时钟信号。
  12. 根据权利要求1-11任一所述的移位寄存器单元，其中，所述第二子移位寄存器包括第二输入电路、第二控制节点复位电路以及第二输出电路；其中，
    所述第二输入电路配置为响应于第二输入信号对所述第二控制节点进行充电；
    所述第二控制节点复位电路配置为响应于第二复位信号对所述第二控制节点进行复位；
    所述第二输出电路配置为在所述第二控制节点的电平的控制下，将第三 时钟信号输出至所述第二输出端；
    其中，所述第三时钟信号包括所述显示输出信号和所述随机输出信号。
  13. 根据权利要求12所述的移位寄存器单元，其中，所述第二子移位寄存器包括第二反相器电路、第二控制节点降噪电路和第二输出降噪电路；其中，
    所述第二反相器电路配置为在所述第二控制节点的电平的控制下，对第四控制节点的电平进行控制；
    所述第二控制节点降噪电路配置为在所述第四控制节点的电平的控制下，对所述第二控制节点进行降噪；
    所述第二输出降噪电路配置为在所述第四控制节点的电平的控制下，对所述第二输出端进行降噪。
  14. 根据权利要求13所述的移位寄存器单元，其中，所述第二子移位寄存器还包括第二防漏电电路；其中，
    所述第二防漏电电路配置为在所述第二输出端输出的所述第三时钟信号的控制下，保持所述第二控制节点的高电位。
  15. 根据权利要求14所述的移位寄存器单元，其中，所述第二防漏电电路包括第二十六晶体管、第二十七晶体管、第二十八晶体管和第二十九晶体管；其中，
    所述第二十六晶体管的栅极和第二输入端连接以接收所述第二输入信号，所述第二十六晶体管的第一极和所述第二十九晶体管的第二极连接，所述第二十六晶体管的第二极和所述第二控制节点连接；
    所述第二十七晶体管的栅极和第二复位端连接以接收所述第二复位信号，所述第二十七晶体管的第一极和所述第二十九晶体管的第二极连接，所述第二十七晶体管的第二极和第一电压端连接以接收第一电压；
    所述第二十八晶体管的栅极与所述第四控制节点连接，所述第二十八晶体管的第一极和所述第二十九晶体管的第二极连接，所述第二十八晶体管的第二极和所述第一电压端连接以接收所述第一电压；
    第二十九晶体管的栅极与所述第二输出端连接，所述第二十九晶体管的第一极与第三时钟信号端连接以接收所述第三时钟信号。
  16. 根据权利要求1-15任一所述的移位寄存器单元，还包括总复位电路， 其中，所述总复位电路配置为在所述第三复位信号的控制下，对所述第二控制节点进行复位。
  17. 根据权利要求16所述的移位寄存器单元，其中，所述总复位电路包括：
    第三十晶体管，其中，所述第三十晶体管的栅极和第三复位端连接以接收所述第三复位信号，所述第三十晶体管的第一极和第一电压端连接以接收第一电压，所述第三十晶体管的第二极和所述第二控制节点连接。
  18. 一种栅极驱动电路，包括多个级联的如权利要求1-17任一所述的移位寄存器单元，其中，
    所述输出控制电路均与所述第一子移位寄存器和所述第二子移位寄存器电连接；
    除第一级第一子移位寄存器外，其余各级第一子移位寄存器的第一输入端和上一级第一子移位寄存器的第一输出端连接；
    除最后一级第一子移位寄存器外，其余各级第一子移位寄存器的第一复位端和下一级第一子移位寄存器的第一输出端连接；
    除第一级第二子移位寄存器外，其余各级第二子移位寄存器的第二输入端和上一级第二子移位寄存器的第二输出端连接；
    除最后一级第二子移位寄存器外，其余各级第二子移位寄存器的第二复位端和下一级第二子移位寄存器的第二输出端连接。
  19. 一种显示装置，包括如权利要求18所述的栅极驱动电路。
  20. 根据权利要求19所述的显示装置，还包括显示面板，其中，所述显示面板包括呈阵列排布的多个子像素单元，所述阵列包括N行，其中，
    所述栅极驱动电路包括N个级联的移位寄存器单元，所述N个级联的移位寄存器单元的第二输出端分别与所述N行子像素单元一一对应连接，以在所述显示阶段向所述N行子像素单元逐行输出显示输出信号，在所述间隔阶段向所述N行子像素单元中的其中一行输出随机输出信号；
    其中，N为大于1的整数。
  21. 一种如权利要求18所述的栅极驱动电路的驱动方法，包括：
    在显示阶段，所述第二子移位寄存器的第二输出端输出所述显示输出信号；
    在间隔阶段，所述第二子移位寄存器的所述第二输出端输出所述随机输出信号。
  22. 根据权利要求21所述的栅极驱动电路的驱动方法，在包括复合输出电路和第三输出端的情况下，所述驱动方法还包括：
    在显示阶段，所述第三输出端输出所述显示输出信号；
    在间隔阶段，所述第三输出端输出所述随机输出信号。
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