WO2020168887A1 - 移位寄存器单元、栅极驱动电路、显示装置及驱动方法 - Google Patents

移位寄存器单元、栅极驱动电路、显示装置及驱动方法 Download PDF

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Publication number
WO2020168887A1
WO2020168887A1 PCT/CN2020/073027 CN2020073027W WO2020168887A1 WO 2020168887 A1 WO2020168887 A1 WO 2020168887A1 CN 2020073027 W CN2020073027 W CN 2020073027W WO 2020168887 A1 WO2020168887 A1 WO 2020168887A1
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WIPO (PCT)
Prior art keywords
node
transistor
level
circuit
shift register
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PCT/CN2020/073027
Other languages
English (en)
French (fr)
Inventor
冯雪欢
李永谦
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/965,124 priority Critical patent/US11120746B2/en
Priority to EP20759878.0A priority patent/EP3929905B1/en
Publication of WO2020168887A1 publication Critical patent/WO2020168887A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the embodiments of the present disclosure relate to a shift register unit, a gate driving circuit, a display device, and a driving method.
  • the gate drive circuit is currently generally integrated in the gate drive chip (GATE IC).
  • GATE IC gate drive chip
  • the area of the chip is the main factor affecting the cost of the chip. How to effectively reduce the area of the chip is a key consideration for technical developers.
  • At least one embodiment of the present disclosure provides a shift register unit including a first input circuit, an output circuit, a first control circuit, a first reset circuit, a second input circuit, a transmission circuit, and a storage circuit.
  • the first input circuit is configured to control the level of the first node in response to a first input signal
  • the output circuit is configured to provide an output signal at the output terminal under the control of the level of the first node
  • the first control circuit is configured to control the level of the second node under the control of the level of the first node
  • the first reset circuit is configured to control the level of the second node.
  • the second input circuit is configured to control the level of the third node in response to a selection control signal
  • the transmission circuit is configured to The level of the first node is controlled according to the level of the third node
  • the storage circuit is electrically connected to the second node, and is configured to stabilize the level of the second node.
  • the second input circuit includes a selection input circuit and a transmission control circuit.
  • the selection input circuit is configured to use a second input signal to control the level of the fourth node in response to the selection control signal;
  • the transmission control circuit is connected to the third node and the fourth node, and It is configured to transmit the first clock signal to the third node under the control of the level of the fourth node.
  • the shift register unit provided by some embodiments of the present disclosure further includes a second reset circuit configured to reset the third node under the control of the level of the second node.
  • the second reset circuit is connected to the second node and the third node.
  • the storage circuit includes a first capacitor
  • the selection input circuit includes a first transistor
  • the transmission control circuit includes a second transistor
  • the transmission circuit includes A fourth transistor
  • the first electrode of the first capacitor is connected to the fourth node
  • the second electrode of the first capacitor is connected to the second node
  • the gate of the first transistor is configured to receive
  • the first pole of the first transistor is configured to receive the second input signal
  • the second pole of the first transistor is connected to the fourth node
  • the gate of the second transistor The first electrode of the second transistor is connected to the fourth node, the first electrode of the second transistor is configured to receive the first clock signal, and the second electrode of the second transistor is connected to the third node
  • the gate of the transistor is configured to receive the first clock signal, the first pole of the fourth transistor is connected to the third node, and the second pole of the fourth transistor is connected to the first node.
  • the storage circuit includes a first capacitor
  • the selection input circuit includes a first transistor
  • the transmission control circuit includes a second transistor
  • the second reset The circuit includes a third transistor
  • the transmission circuit includes a fourth transistor; the first electrode of the first capacitor is connected to the fourth node, and the second electrode of the first capacitor is connected to the second node;
  • the gate of the first transistor is configured to receive the selection control signal, the first electrode of the first transistor is configured to receive the second input signal, and the second electrode of the first transistor is configured to receive the second input signal.
  • the gate of the second transistor is connected to the fourth node, the first electrode of the second transistor is configured to receive the first clock signal, and the second electrode of the second transistor is connected to The third node is connected; the gate of the third transistor is connected to the second node, the first electrode of the third transistor is connected to the third node, and the second electrode of the third transistor is Is configured to receive a first voltage; the gate of the fourth transistor is connected to the third node, the first pole of the fourth transistor is configured to receive the first clock signal or the second voltage, the first The second pole of the four-transistor is connected to the first node.
  • the storage circuit includes a second capacitor
  • the selection input circuit includes a first transistor and a first capacitor
  • the transmission control circuit includes a second transistor.
  • the second reset circuit includes a third transistor
  • the transmission circuit includes a fourth transistor; the first pole of the second capacitor is connected to the second node, and the second pole of the second capacitor is configured to receive a fixed Level;
  • the gate of the first transistor is configured to receive the selection control signal, the first pole of the first transistor is configured to receive the second input signal, the second pole of the first transistor Connected to the fourth node;
  • the first electrode of the first capacitor is connected to the fourth node, and the second electrode of the first capacitor is connected to the third node;
  • the gate of the second transistor Connected to the fourth node, the first pole of the second transistor is configured to receive the first clock signal, and the second pole of the second transistor is connected to the third node;
  • the third transistor The gate of the third transistor is connected to the second node, the first electrode of the third transistor is connected
  • the first control circuit is further configured to transmit a second voltage to the second node under the control of a second clock signal; the output The circuit is also configured to receive a third clock signal, and provide the third clock signal as the output signal to the output terminal under the control of the level of the first node; the second clock signal and The third clock signal is a pulse signal with a duty ratio of one third, and the third clock signal and the second clock signal are separated by a first time in time sequence, and the first time is equal to the Two-thirds of the period of the pulse signal.
  • the first input circuit includes a fifth transistor
  • the first control circuit includes a sixth transistor and a seventh transistor
  • the output circuit includes an eighth transistor.
  • the gate of the fifth transistor is configured to receive the first input signal
  • the first pole of the fifth transistor is configured to receive the first input signal or the second voltage
  • the first pole of the fifth transistor is configured to receive the first input signal or the second voltage.
  • the two poles are connected to the first node; the gate of the sixth transistor is configured to receive the second clock signal, the first pole of the sixth transistor is configured to receive the second voltage, the The second electrode of the sixth transistor is connected to the second node; the gate of the seventh transistor is connected to the first node, the first electrode of the seventh transistor is connected to the second node, and the The second pole of the seventh transistor is configured to receive the first voltage; the gate of the eighth transistor is connected to the first node, and the first pole of the eighth transistor is configured to receive the third clock signal , The second electrode of the eighth transistor is connected to the shift signal output terminal; the gate of the ninth transistor is connected to the first node, and the first electrode of the ninth transistor is configured to receive For the third clock signal, the second electrode of the ninth transistor is connected to the drive signal output terminal; the first electrode of the third capacitor is connected to the first node, and the second electrode of the third capacitor is connected Connected to the drive signal output terminal.
  • the shift register unit provided by some embodiments of the present disclosure further includes a second control circuit configured to control the first clock signal and the level of the fourth node The level of the second node is controlled.
  • the second control circuit includes a tenth transistor and an eleventh transistor.
  • the gate of the tenth transistor is configured to receive the first clock signal
  • the first electrode of the tenth transistor is connected to the second node
  • the second electrode of the tenth transistor is connected to the tenth transistor.
  • the first pole of a transistor is connected
  • the gate of the eleventh transistor is connected to the fourth node
  • the second pole of the eleventh transistor is configured to receive a first voltage.
  • the shift register unit provided by some embodiments of the present disclosure further includes a third control circuit configured to control the level of the second node in response to the first input signal.
  • the third control circuit includes a twelfth transistor, and the gate of the twelfth transistor is configured to receive the first input signal, and The first pole of the twelfth transistor is connected to the second node, and the second pole of the twelfth transistor is configured to receive the first voltage.
  • the shift register unit provided by some embodiments of the present disclosure further includes a third reset circuit and a fourth reset circuit.
  • the third reset circuit is configured to reset the first node in response to a display reset signal
  • the fourth reset circuit is configured to reset the first node in response to a global reset signal.
  • the third reset circuit includes a thirteenth transistor
  • the fourth reset circuit includes a fourteenth transistor
  • the gate of the thirteenth transistor is Configured to receive the display reset signal, a first pole of the thirteenth transistor is connected to the first node, and a second pole of the thirteenth transistor is configured to receive a first voltage
  • the fourteenth The gate of the transistor is configured to receive the global reset signal, the first pole of the fourteenth transistor is connected to the first node, and the second pole of the fourteenth transistor is configured to receive the first Voltage.
  • At least one embodiment of the present disclosure further provides a gate driving circuit including a plurality of cascaded shift register units as provided in the embodiments of the present disclosure.
  • the gate drive circuit provided by some embodiments of the present disclosure further includes a first sub-clock signal line, a second sub-clock signal line, and a third sub-clock signal line; the 3n-2th stage shift register unit and the first The sub-clock signal line is connected to receive the second clock signal for the 3n-2th stage shift register unit, and the 3n-2th stage shift register unit and the third sub-clock signal line are connected for receiving The third clock signal at the 3n-2 stage shift register unit; the 3n-1 stage shift register unit and the second sub-clock signal line are connected to receive the 3n-1 stage shift The second clock signal of the register unit, the 3n-1th stage shift register unit and the first sub-clock signal line are connected to receive the third clock signal for the 3n-1th stage shift register unit; The 3n-th stage shift register unit and the third sub-clock signal line are connected to receive the second clock signal for the 3n-th stage shift register unit, the 3n-th stage shift register unit and the second The sub-clock signal line is connected to receive the third clock signal for the 3n-2
  • At least one embodiment of the present disclosure further provides a display device, including the gate driving circuit provided by the embodiment of the present disclosure.
  • At least one embodiment of the present disclosure further provides a method for driving a shift register unit as provided in an embodiment of the present disclosure, including: the first input circuit controls the level of the first node in response to a first input signal; The output circuit provides an output signal at the output terminal under the control of the level of the first node; the first control circuit performs the level of the second node under the control of the level of the first node Control; the first reset circuit resets the first node and the output terminal under the control of the level of the second node; the second input circuit resets the third node in response to a selection control signal
  • the transmission circuit controls the level of the first node according to the level of the third node; the storage circuit stabilizes the level of the second node.
  • FIG. 1 is a schematic diagram of a shift register unit provided by some embodiments of the present disclosure
  • FIG. 2 is a schematic diagram of another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 3 is a schematic diagram of still another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 4 is a schematic diagram of yet another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 5 is a circuit diagram of a shift register unit provided by some embodiments of the disclosure.
  • Fig. 6 is a circuit diagram of another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 7 is a circuit diagram of still another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 8 is a circuit diagram of yet another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 9 is a schematic diagram of a gate driving circuit provided by some embodiments of the disclosure.
  • FIG. 10 is a signal timing diagram corresponding to the operation of the gate driving circuit shown in FIG. 9 according to some embodiments of the present disclosure.
  • FIG. 11 is a schematic diagram of a second clock signal and a third clock signal provided by some embodiments of the disclosure.
  • FIG. 12 is a schematic diagram of a display device provided by some embodiments of the present disclosure.
  • pulse-up means charging a node or an electrode of a transistor so that the level of the node or the electrode is absolutely The value increases to achieve the operation of the corresponding transistor (for example, turn-on); “pull-down” means to discharge a node or an electrode of a transistor, so that the absolute value of the level of the node or the electrode is reduced, thereby achieving the corresponding Operation of the transistor (for example, turning off).
  • pulse-up means discharging a node or an electrode of a transistor, so that the absolute value of the level of the node or the electrode is reduced, thereby realizing the corresponding transistor Operation (for example, turn on);
  • pulse down means to charge a node or an electrode of a transistor, so that the absolute value of the level of the node or the electrode is increased, thereby realizing the operation of the corresponding transistor (for example, turning off) .
  • the gate drive circuit used in OLED usually consists of three sub-circuits, namely the detection circuit, the display circuit and the connection circuit (OR gate circuit) that outputs the composite pulse of the two.
  • the detection circuit the display circuit
  • the connection circuit OR gate circuit
  • Such a circuit structure is very complicated and cannot meet the display requirements.
  • the high-resolution narrow bezel of the panel is required.
  • the gate driving circuit composed of shift register units needs to provide driving signals for scanning transistors and sensing transistors to the sub-pixel units in the display panel, for example, for the display period of one frame.
  • a sensing driving signal for the sensing transistor is provided in a blanking period of one frame.
  • the sensing driving signal output by the gate driving circuit is sequentially scanned row by row.
  • the sensing driving signal for the sub-pixel unit of the first row in the display panel is output during the blanking period of the first frame.
  • Detect driving signal output the sensing driving signal for the second row of sub-pixel units in the display panel during the blanking period of the second frame, and so on, output the frequency of the sensing driving signal corresponding to one row of sub-pixel units in each frame Line-by-line sequential output, which completes the line-by-line sequential compensation of the display panel.
  • the gate driving circuit drives a display panel
  • the gate driving circuit is required not only to output the scan driving signal for the display period, but also to output the blanking period. Sense the drive signal.
  • the level of the control terminal (for example, connected to the first node) of the output circuit in the shift register unit needs to be maintained at a high level; for example, when not When the shift register unit is required to output the drive signal, the level of the first node above needs to be kept at a low level; that is, the level of the first node directly affects the output of the shift register unit, and in non- The level of the first node in the output stage should be kept stable at a low level, otherwise the shift register unit may output multiple times within one frame.
  • a control circuit and a reset circuit are generally provided in the shift register unit.
  • the control circuit is configured to control the level of the second node
  • the reset circuit is configured to The level of the first node is controlled under the control of the level of the two nodes.
  • the level of the second node needs to be maintained at a high level.
  • the level of the first node may drift, thereby affecting the normal output of the shift register unit.
  • At least one embodiment of the present disclosure provides a shift register unit that includes a first input circuit, an output circuit, a first control circuit, a first reset circuit, a second input circuit, a transmission circuit, and a storage circuit.
  • the first input circuit is configured to control the level of the first node in response to the first input signal
  • the output circuit is configured to provide an output signal at the output terminal under the control of the level of the first node
  • the first control circuit is It is configured to control the level of the second node under the control of the level of the first node
  • the first reset circuit is configured to reset the first node and the output terminal under the control of the level of the second node
  • the second input circuit is configured to control the level of the third node in response to the selection control signal
  • the transmission circuit is configured to control the level of the first node according to the level of the third node
  • the nodes are electrically connected and configured to stabilize the level of the second node.
  • the embodiments of the present disclosure also provide a gate driving circuit, a display device, and a driving method corresponding to the above-mentioned shift register unit.
  • the shift register unit, gate driving circuit, display device, and driving method provided by the embodiments of the present disclosure can better stabilize the level of the second node in the shift register unit.
  • the second node can be stably maintained at a high level, so that the level of the first node does not drift and is maintained stably At the low level, multiple outputs of the shift register unit can be avoided.
  • the corresponding gate driving circuit and the display device can also realize random compensation, thereby avoiding poor display problems such as scan lines and uneven display brightness caused by line-by-line sequential compensation.
  • random compensation refers to an external compensation method that is different from line-by-line sequential compensation.
  • the random output corresponding to any line in the display panel.
  • the definition of “one frame”, “every frame” or “a certain frame” includes sequential display periods and blanking periods, for example, gate driving during the display period
  • the circuit outputs a drive signal, which can drive the display panel from the first line to the last line to complete the scanning and display of a complete image.
  • the gate drive circuit outputs a drive signal, which can be used to drive the display
  • the sensing transistors in a certain row of sub-pixel units in the panel complete the external compensation of the row of sub-pixel units.
  • FIG. 1 is a schematic diagram of a shift register unit provided by some embodiments of the present disclosure
  • FIG. 2 is a schematic diagram of another shift register unit provided by some embodiments of the present disclosure.
  • the shift register unit 10 includes a first input circuit 110, an output circuit 120, a first control circuit 130, and a first reset circuit 140 , The second input circuit 150, the transmission circuit 160 and the storage circuit 170.
  • a plurality of the shift register units 10 can be cascaded to construct the gate driving circuit provided by an embodiment of the present disclosure.
  • the gate driving circuit can be used in a display device to provide a driving signal during the display process of one frame of the display device.
  • the first input circuit 110 is configured to control the level of the first node Q in response to the first input signal STU1, for example, to charge the first node Q.
  • the first input circuit 110 may be configured to receive the first input signal STU1 and the second voltage VDD, and the first input circuit 110 is turned on in response to the first input signal STU1, so that the second voltage VDD can be used for the first node Q1 is charging.
  • the first input circuit 110 may not receive the second voltage VDD, and directly use the first input signal STU1 to charge the first node Q1.
  • the second voltage VDD is, for example, a high level, and the following embodiments are the same as this, and will not be repeated.
  • the output circuit 120 is configured to provide an output signal at the output terminal OP under the control of the level of the first node Q.
  • the output terminal OP includes a shift signal output terminal CRT and a drive signal output terminal DST.
  • the output signal includes a shift signal CR and a drive signal OUT.
  • the output circuit 120 may be configured to receive the third clock signal CLKC.
  • the third clock signal CLKC may be provided to the shift signal CR as the shift signal CR.
  • the signal output terminal CRT provides the third clock signal CLKC as the driving signal OUT to the driving signal output terminal DST.
  • the shift signal CR output by the output circuit 120 may be provided to other shift register units 10 as the first input signal STU1, thereby completing the line-by-line shift of the display scan; the output circuit 120 outputs The driving signal OUT can drive a certain row of sub-pixel units in the display panel to perform display scanning.
  • some of the shift register units 10 can be connected to a clock signal line to receive the first input signal STU1 provided by the clock signal line; Alternatively, some shift register units 10 may also receive the shift signal CR output by other stages of shift register units 10 as the first input signal STU1.
  • the signal waveforms of the shift signal CR and the driving signal OUT output by the output circuit 120 may be the same or different, and the embodiment of the present disclosure does not limit this.
  • the first control circuit 130 is configured to control the level of the second node QB under the control of the level of the first node Q.
  • the first control circuit 130 is connected to the first node Q and the second node QB, and is configured to receive the first voltage VGL1 and the second voltage VDD.
  • the first control circuit 130 may use the first voltage VGL1 at a low level to pull the second node QB down to a low level.
  • the first control circuit 130 is configured to receive the second clock signal CLKB.
  • the first control circuit 130 can be turned on in response to the high-level second clock signal CLKB, so that the high-level second voltage VDD can be used to charge the second node QB to pull the second node QB up to a high voltage. level.
  • the first voltage VGL1 is, for example, a low level, and the following embodiments are the same as this, and will not be repeated.
  • the first reset circuit 140 is configured to reset the first node Q and the output terminal OP (for example, including the shift signal output terminal CRT and the drive signal output terminal DST) under the control of the level of the second node QB.
  • the first reset circuit 140 is connected to the first node Q, the second node QB, and the output terminal OP, and is configured to receive a low-level first voltage VGL1.
  • the low-level first voltage VGL1 can be used to pull down and reset the first node Q and the output terminal OP.
  • the first reset circuit 140 may also be configured to receive a low level.
  • the low-level first voltage VGL1 can be used to perform the operation on the first node Q and the shift signal output terminal CRT Pull-down reset, while using the low-level third voltage VGL2 to pull-down reset the driving signal output terminal DST.
  • the first voltage VGL1 may also be used to pull-down reset the driving signal output terminal DST, which is not limited in the present disclosure.
  • the third voltage VGL2 is, for example, a low level, and the third voltage VGL2 may be the same as or different from the first voltage VGL1. The following embodiments are the same and will not be repeated here.
  • the shift register unit 10 includes a second input circuit 150 and a transmission circuit 160.
  • the second input circuit 150 is configured to control the level of the third node N in response to the selection control signal OE.
  • the second input circuit 150 includes a selection input circuit 151 and a transmission control circuit 152.
  • the selection input circuit 151 is configured to control the level of the fourth node H using the second input signal STU2 in response to the selection control signal OE, for example, to charge the fourth node H and maintain the level of the fourth node H. For example, in the display period of one frame, the selection input circuit 151 may be turned on under the control of the selection control signal OE, so as to charge the fourth node H with the second input signal STU2.
  • the level (for example, high level) of the fourth node H can be maintained from the display period of one frame to the blanking period of the frame.
  • the transmission control circuit 152 is connected to the third node N and the fourth node H, and is configured to transmit the first clock signal CLKA to the third node N under the control of the level of the fourth node H.
  • the transmission control circuit 152 may be configured to receive the first clock signal CLKA, and may transmit the first clock signal CLKA when the transmission control circuit 152 is turned on under the control of the level of the fourth node H To the third node N, thereby controlling the level of the third node N. For example, in the blanking period of one frame, when the first clock signal CLKA is at a high level, the transmission control circuit 152 may transmit the high level to the third node N, so that the third node N becomes a high level .
  • the transmission circuit 160 is configured to control the level of the first node Q according to the level of the third node N, for example, to charge the first node Q.
  • the transmission circuit 160 is connected to the first node Q and the third node N, and is configured to receive the second voltage VDD.
  • the transmission circuit 160 may be configured to receive the first clock signal CLKA. As described above, when the first clock signal CLKA is at a high level, the transmission control circuit 152 causes the third node N to become high.
  • the transmission circuit 160 is turned on under the control of the first clock signal CLKA, so that the high level of the third node N can be transmitted to the first node Q, thereby controlling the level of the first node Q , For example, charge the first node Q.
  • a certain stage of shift register unit 10 may receive the shift signal CR output by the shift register unit 10 of the current stage as the second input signal STU2;
  • the shift register unit 10 of a certain stage may also receive the shift signal CR output by the shift register unit 10 of another stage as the second input signal STU2.
  • the shift register unit 10 of the stage when it is necessary to select a certain stage of the shift register unit 10 to output the drive signal during the blanking period of one frame, when the shift register unit 10 of the stage outputs the shift signal CR in the display period of one frame, the The shift signal CR is provided to the selection input circuit 151 in the shift register unit 10 of the stage as the second input signal STU2, and makes the selection control signal OE and the shift signal CR provided to the shift register unit 10 of the stage
  • the waveform timing is the same, so that the selection input circuit 151 in the shift register unit 10 of this stage is turned on. Since the selection input circuit 151 is turned on, the fourth node H can be charged by the second input signal STU2 to raise the level of the fourth node H. Then, the high level of the fourth node H can be maintained from the display period of the frame to the blanking period of the frame.
  • the first clock signal CLKA provided to the transmission control circuit 152 in the shift register unit 10 of the stage can be made high, and the transmission control circuit 152 is at the high level of the fourth node H. It is turned on under the control of Ping, so that the high-level first clock signal CLKA can be transmitted to the third node N, so that the level of the third node N becomes high.
  • the transmission circuit 160 in the shift register unit 10 of this stage is turned on under the control of the high level of the third node N, so that the high level second voltage VDD can be used to charge the first node Q to raise the first node Q. A level of node Q.
  • the output circuit 120 in the shift register unit 10 of this stage is turned on under the control of the high level of the first node Q, so as to provide an output signal at the output terminal, for example, a drive signal OUT is output at the drive signal output terminal DST.
  • the driving signal OUT may be used to drive the sensing transistors in a certain row of sub-pixel units in the display panel to complete the external compensation of the row of sub-pixel units.
  • the storage circuit 170 is electrically connected to the second node QB, and is configured to stabilize the level of the second node QB.
  • the storage circuit 170 may include a capacitor.
  • the first pole of the capacitor and the second node QB may be connected, and the second pole of the capacitor may be configured to receive a fixed level, so that The capacitor can stabilize the level of the second node QB.
  • the storage circuit 170 can make the second node QB stably maintain a high level, so that the level of the first node Q does not drift and is stably maintained at Low level, so as to avoid multiple output problems of the shift register unit 10.
  • the storage circuit 170 may be configured to receive the first voltage VGL1.
  • the storage circuit 170 includes a capacitor, one pole of the capacitor may receive the first voltage VGL1.
  • the storage circuit 170 may also be connected to the fourth node H.
  • the storage circuit 170 includes a capacitor, one pole of the capacitor and the fourth node Node H is connected.
  • the storage circuit 170 when the storage circuit 170 is connected to both the second node QB and the fourth node H, the storage circuit 170 can not only be used to stabilize the second node QB The level can also be used to stabilize the level of the fourth node H.
  • the high level and the low level are relative.
  • the high level indicates a higher voltage range (for example, 5V, 10V or other suitable voltages can be used for the high level), and multiple high levels can be the same or different.
  • the low level represents a lower voltage range (for example, the low level may adopt 0V, -5V, -10V or other suitable voltages), and multiple low levels may be the same or different.
  • the minimum value of the high level is greater than the maximum value of the low level.
  • controlling the level of a node includes charging the node to increase the power of the node.
  • Level, or discharge the node to pull down the level of the node For example, you can set a capacitor electrically connected to the node, charging the node means charging the capacitor electrically connected to the node; similarly, discharging the node means charging the capacitor electrically connected to the node. Discharge; the high or low level of the node can be maintained through the capacitor.
  • the shift register unit 10 provided by some embodiments of the present disclosure further includes a second reset circuit 180, which is configured to control the third node QB under the control of the level of the second node QB. Node N is reset.
  • the second reset circuit 180 is connected to the second node QB and the third node N, and is configured to receive the low-level first voltage VGL1. For example, when the level of the second node QB is at a high level, the second reset circuit 180 can be turned on under the control of the level of the second node QB, so that the first voltage VGL1 of a low level can be used to connect the third node N to reset.
  • the shift register unit 10 when the level of the second node QB is high, the level of the third node N can be pulled down to a low level through the second reset circuit 180 In this way, the transmission circuit 160 can be turned off, so as to prevent the transmission circuit 160 from charging the first node Q, thereby further avoiding multiple output problems of the shift register unit 10.
  • the first control circuit 130 is further configured to transmit the second voltage VDD to under the control of the second clock signal CLKB The second node QB.
  • the output circuit 120 is also configured to receive the third clock signal CLKC, and under the control of the level of the first node Q, provide the third clock signal CLKC as an output signal to the output terminal OP (for example, including the shift signal output terminal CRT and Drive signal output terminal DST).
  • FIG. 11 is a schematic diagram of a second clock signal and a third clock signal provided by some embodiments of the disclosure.
  • the second clock signal CLKB and the third clock signal CLKC are pulse signals with a duty ratio of one third
  • the third clock signal CLKC and the second clock signal CLKB are separated by the first One time T1, the first time T1 is equal to two-thirds of the period T of the pulse signal.
  • the shift register unit 10 provided by some embodiments of the present disclosure further includes a second control circuit 210, which is configured to operate at the level of the first clock signal CLKA and the fourth node H Under the control of, the level of the second node QB is controlled.
  • a second control circuit 210 which is configured to operate at the level of the first clock signal CLKA and the fourth node H Under the control of, the level of the second node QB is controlled.
  • the second control circuit 210 is connected to the second node QB and the fourth node H, and is configured to receive the first clock signal CLKA and the low-level first voltage VGL1. For example, in the blanking period of one frame, when the fourth node H is at a high level and the first clock signal CLKA is at a high level, the second control circuit 210 is turned on, so that a low-level first voltage can be used. VGL1 pulls down the second node QB.
  • the shift register unit 10 for example, in the blanking period of one frame, when the first clock signal CLKA is high and the fourth node H is high, the shift register The transmission circuit 160 in the unit 10 is turned on, so that the first node Q can be charged. While the transmission circuit 160 is charging the first node Q, the second control circuit 210 pulls down the level of the second node QB to a low level, which can avoid the influence of the second node QB on the first node Q, so that The transmission circuit 160 charges the first node Q more fully, which is beneficial for the shift register unit 10 to normally output the drive signal OUT during the blanking period. For example, the drive signal OUT can be used to drive a certain row of the display panel.
  • the sensing transistor in the pixel unit completes the external compensation of the row of sub-pixel units.
  • the shift register unit 10 provided by some embodiments of the present disclosure further includes a third control circuit 220.
  • the third control circuit 220 is configured to control the level of the second node QB in response to the first input signal STU1.
  • the third control circuit 220 is connected to the second node QB, and is configured to receive the first input signal STU1 and the low-level first voltage VGL1.
  • the third control circuit 220 is turned on in response to the first input signal STU1, so that the second node QB can be pulled down and reset by using the low-level first voltage VGL1. Pulling the second node QB down to a low level can avoid the influence of the second node QB on the first node Q, so that the first node Q can be charged more fully during the display period.
  • the shift register unit 10 provided by some embodiments of the present disclosure further includes a third reset circuit 230 and a fourth reset circuit 240.
  • the third reset circuit 230 is configured to reset the first node Q in response to the display reset signal STD.
  • the third reset circuit 230 is connected to the first node Q, and is configured to receive the display reset signal STD and the low-level first voltage VGL1.
  • the third reset circuit 230 is turned on in response to the display reset signal STD, so that the first node Q can be pulled down and reset by using the low-level first voltage VGL1.
  • the shift register unit 10 of a certain stage can receive the shift signal CR output by the shift register unit 10 of the other stage as the display reset signal STD.
  • the fourth reset circuit 240 is configured to reset the first node Q in response to the global reset signal TRST.
  • the fourth reset circuit 240 is connected to the first node Q and is configured to receive the global reset signal TRST and the low-level first voltage VGL1.
  • the fourth reset circuits 240 in the shift register units 10 of each stage respond to the global reset signal TRST. It is turned on, so that the low-level first voltage VGL1 can pull down and reset the first node Q through the fourth reset circuit 240.
  • each node (the first node Q, the second node QB, the third node N, the fourth node H, etc.) and each output terminal (the output terminal OP, the shift signal output The terminal CRT, the drive signal output terminal DST, etc.) are all set up to better describe the circuit structure, and do not represent actual components.
  • the node represents the junction of related circuit connections in the circuit structure, that is, the related circuits connected with the same node identifier are electrically connected to each other.
  • the first control circuit 130, the first reset circuit 140, the second control circuit 210, the third control circuit 220, the storage circuit 170, and the second reset circuit 180 are all connected to the second node QB. It means that these circuits are electrically connected to each other.
  • the shift register unit 10 shown in FIG. 4 may be implemented as the circuit structure shown in FIG. 5.
  • the shift register unit 10 includes: a first transistor M1 to a seventeenth transistor M17, a first capacitor C1, and a third capacitor C3.
  • the shift register unit 10 of FIGS. 1 to 3 can be implemented in a similar manner.
  • one pole of the capacitor of the storage circuit 170 is connected to the second node QB, and the other pole is connected to other corresponding nodes (for example, the fourth node H) Connected or configured to receive a fixed level (for example, the first voltage VGL1).
  • the selection input circuit 151 may be implemented as a first transistor M1.
  • the gate of the first transistor M1 is configured to receive the selection control signal OE
  • the first pole of the first transistor M1 is configured to receive the second input signal STU2
  • the second pole of the first transistor M1 is connected to the fourth node H.
  • the selection control signal OE is at a high level
  • the first transistor M1 is turned on, so that the fourth node H can be charged by the second input signal STU2.
  • the second input signal STU2 may be the shift signal CR output by the shift register unit 10
  • the signal timing of the selection control signal OE may be the same as the second input signal STU2, that is, The selection control signal OE and the second input signal STU2 are both at high level.
  • the transmission control circuit 152 may be implemented as a second transistor M2.
  • the gate of the second transistor M2 is connected to the fourth node H
  • the first electrode of the second transistor M2 is configured to receive the first clock signal CLKA
  • the second electrode of the second transistor M2 is connected to the third node N.
  • the fourth node H is at a high level
  • the second transistor M2 is turned on, so that the first clock signal CLKA can be transmitted to the third node N to raise the level of the third node N.
  • the second reset circuit 180 may be implemented as a third transistor M3.
  • the gate of the third transistor M3 is connected to the second node QB, the first electrode of the third transistor M3 is connected to the third node N, and the second electrode of the third transistor M3 is configured to receive the first voltage VGL1 at a low level.
  • the third transistor M3 is turned on, and the first voltage VGL1 at a low level can reset the third node N through the third transistor M3.
  • the transmission circuit 160 may include a fourth transistor M4.
  • the gate of the fourth transistor M4 is connected to the third node N, the first electrode of the fourth transistor M4 is configured to receive the high-level second voltage VDD, and the second electrode of the fourth transistor M4 is connected to the first node Q.
  • the fourth transistor M4 is turned on, and the second voltage VDD may charge the first node Q through the fourth transistor M4.
  • the shift register unit 10 when the shift register unit 10 does not need to output a driving signal, the level of the second node QB is high, and the first voltage VGL1 of low level resets the third node N through the third transistor M3 to pull Lower the level of the third node N. Since the third node N is at a low level, the fourth transistor M4 is turned off, so that the first node Q can be prevented from being charged by the second voltage VDD.
  • the first input circuit 110 may be implemented as a fifth transistor M5.
  • the gate of the fifth transistor is configured to receive the first input signal STU1
  • the first pole of the fifth transistor M5 is configured to receive the second voltage VDD
  • the second pole of the fifth transistor M5 is connected to the first node Q.
  • the shift register unit 10 of a certain stage can receive the shift signal CR of the shift register unit 10 of the previous stage as the shift signal of the current stage.
  • the fifth transistor M5 is turned on, and the high-level second voltage VDD can charge the first node Q through the fifth transistor M5 to increase the power of the first node Q. level.
  • the first pole of the fifth transistor M5 may also be configured to receive the first input signal STU1, and when the fifth transistor M5 is turned on under the control of the first input signal STU1 The first node Q can be charged directly by using the first input signal STU1.
  • the embodiment of the present disclosure does not limit the implementation of the first input circuit 110.
  • the output circuit 120 may be implemented as including an eighth transistor M8, a ninth transistor M9, and a third capacitor C3.
  • the gate of the eighth transistor M8 is connected to the first node Q, the first pole of the eighth transistor M8 is configured to receive the third clock signal CLKC, and the second pole of the eighth transistor M8 is connected to the shift signal output terminal CRT.
  • the gate of the ninth transistor M9 is connected to the first node Q, the first electrode of the ninth transistor M9 is configured to receive the third clock signal CLKC, and the second electrode of the ninth transistor M9 is connected to the driving signal output terminal DST.
  • the first pole of the third capacitor C3 is connected to the first node Q, and the second pole of the third capacitor C3 is connected to the driving signal output terminal DST.
  • the eighth transistor M8 and the ninth transistor M9 are turned on, and the eighth transistor M8 can provide the third clock signal CLKC as the shift signal CR to the shift signal output terminal CRT, for example
  • the shift signal CR may be provided to other adjacent shift register units 10 as the first input signal STU1 or the display reset signal STD.
  • the ninth transistor M9 may provide the third clock signal CLKC as the driving signal OUT to the driving signal output terminal DST.
  • the driving signal OUT may drive a certain row of sub-pixel units in the display panel to perform Display scanning; for another example, in the blanking period of one frame, the drive signal OUT can be used to drive the sensing transistors in a certain row of sub-pixel units in the display panel to complete external compensation for the row of sub-pixel units.
  • the level of the first node Q can be maintained through the third capacitor C3.
  • the second pole of the third capacitor C3 may also be connected to the shift signal output terminal CRT, which is not limited in the embodiment of the present disclosure.
  • the high-level signal can be coupled by the third capacitor C3 to further increase the level of the first node Q, so that The eighth transistor M8 and the ninth transistor M9 are more fully turned on, which is more conducive to the output of the shift signal CR and the drive signal OUT.
  • the first control circuit 130 may be implemented to include a sixth transistor M6 and a seventh transistor M7.
  • the gate of the sixth transistor M6 is configured to receive the second clock signal CLKB, the first pole of the sixth transistor M6 is configured to receive the second voltage VDD, and the second pole of the sixth transistor M6 is connected to the second node QB.
  • the gate of the seventh transistor M7 is connected to the first node Q, the first electrode of the seventh transistor M7 is connected to the second node QB, and the second electrode of the seventh transistor M7 is configured to receive the first voltage VGL1.
  • the seventh transistor M7 when the level of the first node Q is at a high level, the seventh transistor M7 is turned on, and the first voltage VGL1 at a low level can reset the second node QB.
  • the sixth transistor M6 when the level of the first node Q is low and the second clock signal CLKB is high, the sixth transistor M6 is turned on and the seventh transistor M7 is turned off, and the high-level second voltage VDD can pass through the sixth transistor M6.
  • the transistor M6 charges the second node QB, thereby pulling the level of the second node QB to a high level.
  • the second control circuit 210 may be implemented to include a tenth transistor M10 and an eleventh transistor M11.
  • the gate of the tenth transistor M10 is configured to receive the first clock signal CLKA, the first pole of the tenth transistor M10 is connected to the second node QB, and the second pole of the tenth transistor M10 and the first pole of the eleventh transistor M11 are connected. Connected, the gate of the eleventh transistor M11 is connected to the fourth node H, and the second pole of the eleventh transistor M11 is configured to receive the first voltage VGL1. For example, when the first clock signal CLKA is at a high level and the fourth node H is at a high level, the tenth transistor M10 and the eleventh transistor M11 are turned on, so that the low-level first voltage VGL1 can be applied to the second node QB performs a pull-down reset.
  • the third control circuit 220 may be implemented as a twelfth transistor M12.
  • the gate of the twelfth transistor M12 is configured to receive the first input signal STU1, the first pole of the twelfth transistor M12 is connected to the second node QB, and the second pole of the twelfth transistor M12 is configured to receive the first voltage VGL1.
  • the twelfth transistor M12 is turned on, so that the first voltage VGL1 at a low level can pull down and reset the second node QB.
  • the first reset circuit 140 may be implemented to include a fifteenth transistor M15, a sixteenth transistor M16, and a seventeenth transistor M17.
  • the gate of the fifteenth transistor M15 is connected to the second node QB, the first electrode of the fifteenth transistor M15 is connected to the first node Q, and the second electrode of the fifteenth transistor M15 is configured to receive the first voltage VGL1.
  • the gate of the sixteenth transistor M16 is connected to the second node QB, the first electrode of the sixteenth transistor M16 is connected to the shift signal output terminal CRT, and the second electrode of the sixteenth transistor M16 is configured to receive the first voltage VGL1 .
  • the gate of the seventeenth transistor M17 is connected to the second node QB, the first pole of the seventeenth transistor M17 is connected to the driving signal output terminal DST, and the second pole of the seventeenth transistor M17 is configured to receive the third voltage VGL2.
  • the fifteenth transistor M15 and the sixteenth transistor M16 are turned on, so that the first voltage VGL1 at a low level can be applied to the first node Q and the shift signal output terminal CRT. Reset; at the same time the seventeenth transistor M17 is turned on, so that the low-level third voltage VGL2 can reset the driving signal output terminal DST.
  • the second pole of the seventeenth transistor M17 may also be configured to receive the first voltage VGL1, so that the first voltage VGL1 is used to reset the driving signal output terminal DST.
  • the third reset circuit 230 may be implemented as a thirteenth transistor M13.
  • the gate of the thirteenth transistor M13 is configured to receive the display reset signal STD
  • the first pole of the thirteenth transistor M13 is connected to the first node Q
  • the second pole of the thirteenth transistor M13 is configured to receive the first voltage VGL1 .
  • the shift register unit 10 of a certain stage can receive the shift signal CR of the shift register unit 10 of the subsequent stage as the shift signal of the current stage.
  • the register unit 10 displays the reset signal STD. For example, when the display reset signal STD is at a high level, the thirteenth transistor M13 is turned on, so that the first voltage VGL1 at a low level can pull down and reset the first node Q.
  • the fourth reset circuit 240 may be implemented as a fourteenth transistor M14.
  • the gate of the fourteenth transistor M14 is configured to receive the global reset signal TRST, the first pole of the fourteenth transistor M14 is connected to the first node Q, and the second pole of the fourteenth transistor M14 is configured to receive the first voltage VGL1 .
  • the fourteenth transistors M14 in the shift register units 10 of each stage respond to the global reset signal TRST. Turn on to realize the global reset of the gate drive circuit.
  • the storage circuit 170 may be implemented as a first capacitor C1, the first pole of the first capacitor C1 is connected to the fourth node H, and the second pole of the first capacitor C1 is connected to the second node QB.
  • the first capacitor C1 can stabilize the level of the second node QB. For example, when the second clock signal CLKB is at a high level, the second voltage VDD charges the second node QB through the sixth transistor M6, so that the level of the second node QB can be pulled up to a high level. Then, when the second clock signal CLKB becomes low level, the sixth transistor M6 is turned off, that is, the charging path to the second node QB is turned off. At this time, since the first capacitor C1 is connected to the second node QB, the first capacitor C1 can maintain the high level of the second node QB to prevent the level of the second node QB from drifting and affecting the level of the first node Q.
  • the first capacitor C1 in addition to being connected to the second node QB, the first capacitor C1 is also connected to the fourth node H, so that the first capacitor C1 can also be used to stabilize the fourth node.
  • the shift register unit 10 may also be implemented as the circuit structure shown in FIG. 6. Only the differences between the shift register unit 10 shown in FIG. 6 and the shift register unit 10 shown in FIG. 5 will be described below, and the similarities will not be repeated here.
  • the second reset circuit 180 is not included in the shift register unit 10, that is, the third transistor M3 is not included.
  • the gate of the fourth transistor M4 is configured to receive the first clock signal CLKA
  • the first pole of the fourth transistor M4 is connected to the third node N
  • the second pole of M4 is connected to the first node Q.
  • the second transistor M2 and the fourth transistor M4 are both turned on, so that the first clock signal CLKA of the high level can be
  • the first node Q is charged through the second transistor M2 and the fourth transistor M4.
  • the shift register unit 10 may also be implemented as the circuit structure shown in FIG. 7. Only the differences between the shift register unit 10 shown in FIG. 7 and the shift register unit 10 shown in FIG. 5 are described below, and the similarities are not repeated here.
  • the selection input circuit 151 is implemented as including a first transistor M1 and a first capacitor C1, and the storage circuit 170 is implemented as a second capacitor C2.
  • the first pole of the first capacitor C1 is connected to the fourth node H, and the second pole of the first capacitor C1 is connected to the third node N.
  • the first pole of the second capacitor C2 is connected to the second node QB, and the second pole of the second capacitor C2 is configured to receive a fixed level, for example, configured to receive the first voltage VGL1.
  • the embodiment of the present disclosure does not limit the connection manner of the second capacitor C2.
  • the second electrode of the second capacitor C2 may also receive other fixed levels, such as receiving the second voltage VDD, the third voltage VGL2, and so on.
  • the second capacitor C2 may be used to stabilize the level of the second node QB.
  • the shift register unit 10 may also be implemented as the circuit structure shown in FIG. 8. Only the differences between the shift register unit 10 shown in FIG. 8 and the shift register unit 10 shown in FIG. 7 are described below, and the similarities are not repeated here.
  • the first pole of the first capacitor C1 is connected to the fourth node H, and the second pole of the first capacitor C1 is configured to receive the first voltage VGL1.
  • the embodiment of the present disclosure does not limit the connection mode of the first capacitor C1.
  • the second pole of the first capacitor C1 may also be configured to receive other fixed levels, such as receiving the second voltage VDD and the third voltage. Voltage VGL2 and so on.
  • transistors in the shift register unit 10 are all N-type transistors as an example for description.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • thin film transistors are used as examples for description.
  • the source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be structurally indistinguishable.
  • one pole is directly described as the first pole and the other pole is the second pole.
  • transistors can be classified into N-type and P-type transistors according to their characteristics.
  • the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages), and the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages) );
  • the transistors in the following embodiments are also described using N-type transistors as examples, and will not be repeated.
  • the embodiments of the present disclosure include but are not limited thereto.
  • one or more transistors in the shift register unit provided by the embodiments of the present disclosure may also adopt P-type transistors.
  • the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages) ).
  • the first capacitor C1 can be used to stabilize the level of the fourth node H or the level of the second node QB
  • the second capacitor C2 can be used to stabilize the The level of the second node QB is stabilized by the third capacitor C3.
  • the first capacitor C1, the second capacitor C2, and the third capacitor C3 can be capacitive devices manufactured by a process, for example, a capacitor device can be realized by making a special capacitor electrode, and each electrode of the capacitor can be made through a metal layer, a semiconductor layer (for example, Doped polysilicon), etc., or in some examples, by designing circuit wiring parameters so that the first capacitor C1, the second capacitor C2, and the third capacitor C3 can also be realized by the parasitic capacitances between the various devices.
  • a capacitor device can be realized by making a special capacitor electrode, and each electrode of the capacitor can be made through a metal layer, a semiconductor layer (for example, Doped polysilicon), etc., or in some examples, by designing circuit wiring parameters so that the first capacitor C1, the second capacitor C2, and the third capacitor C3 can also be realized by the parasitic capacitances between the various devices.
  • connection mode of the first capacitor C1, the second capacitor C2 and the third capacitor C3 is not limited to the above-described mode, and may also be other applicable connection modes, as long as the storage and writing to the fourth node H, the second node QB and the The level of the first node Q is sufficient.
  • the gate driving circuit 20 includes a plurality of cascaded shift register units 10, of which any one or more shift register units 10 may adopt the structure of the shift register unit 10 provided by the embodiment of the present disclosure or a modification thereof.
  • A1, A2, A3, and A4 in FIG. 9 represent four shift register units 10 connected in cascade.
  • the output signals of A1, A2, A3, and A4 can respectively drive four rows of sub-pixel units in the display panel.
  • A1, A2, A3, and A4 can respectively drive the first row, second row, third row, and fourth row of sub-pixel units of the display panel.
  • the gate driving circuit 20 provided by the embodiment of the present disclosure can stabilize the level of the second node QB.
  • the second node QB can be stably maintained at a high level, so that the first node
  • the level of Q does not drift and is stably maintained at a low level, so that multiple output problems of the gate drive circuit 20 can be avoided.
  • the gate driving circuit 20 can also realize random compensation, thereby avoiding poor display problems such as scan lines and uneven display brightness caused by sequential compensation row by row.
  • the gate driving circuit 20 includes a first sub-clock signal line CLK_1, a second sub-clock signal line CLK_2, and a third sub-clock signal line CLK_3.
  • the 3n-2th stage shift register unit (for example, the first stage shift register unit A1) is connected to the first sub-clock signal line CLK_1 to receive the second clock signal CLKB for the 3n-2th stage shift register unit.
  • the 3n-2 stage shift register unit is connected to the third sub-clock signal line CLK_3 to receive the third clock signal CLKC for the 3n-2 stage shift register unit.
  • the 3n-1 stage shift register unit (for example, the second stage shift register unit A2) is connected to the second sub-clock signal line CLK_2 to receive the second clock signal CLKB for the 3n-1 stage shift register unit.
  • the 3n-1 stage shift register unit is connected to the first sub-clock signal line CLK_1 to receive the third clock signal CLKC for the 3n-1 stage shift register unit.
  • the 3n-stage shift register unit (for example, the third-stage shift register unit A3) is connected to the third sub-clock signal line CLK_3 to receive the second clock signal CLKB for the 3n-stage shift register unit, and the 3n-stage shift The register unit is connected to the second sub-clock signal line CLK_2 to receive the third clock signal CLKC for the 3n-th stage shift register unit; n is an integer greater than zero.
  • the timing of signals provided by the first sub-clock signal line CLK_1, the second sub-clock signal line CLK_2, and the third sub-clock signal line CLK_3 is shown in FIG. 10.
  • the signals provided by the first sub-clock signal line CLK_1, the second sub-clock signal line CLK_2, and the third sub-clock signal line CLK_3 are all pulse signals with a duty ratio of one third.
  • the second clock signal CLKB and the third clock signal CLKC are provided to the shift register units 10 at various levels through three sub-clock signal lines, which can save the number of signal lines, thereby Simplifying the circuit structure and reducing the frame size of the display device using the gate driving circuit 20 is more conducive to improving the PPI of the display device.
  • the gate driving circuit 20 further includes a fourth sub-clock signal line CLK_4, a fifth sub-clock signal line CLK_5, a sixth sub-clock signal line CLK_6, and a seventh sub-clock signal line CLK_7.
  • each stage of the shift register unit 10 in the gate driving circuit 20 is connected to the fourth sub-clock signal line CLK_4 to receive the second voltage VDD.
  • Each stage of the shift register unit 10 in the gate driving circuit 20 is connected to the fifth sub-clock signal line CLK_5 to receive the global reset signal TRST.
  • Each stage of the shift register unit 10 in the gate driving circuit 20 is connected to the sixth sub-clock signal line CLK_6 to receive the first clock signal CLKA.
  • Each stage of the shift register unit 10 in the gate driving circuit 20 is connected to the seventh sub-clock signal line CLK_7 to receive the selection control signal OE.
  • the shift register unit 10 of the other stage is connected to the shift register unit 10 of the previous stage to receive the shift signal CR as the first input signal STU1. Except for the shift register unit 10 of the last stage, the shift register unit 10 of the other stages and the shift register unit 10 of the subsequent stage are connected to receive the shift signal CR and serve as the display reset signal STD.
  • the shift register unit 10 in the gate driving circuit 20 shown in FIG. 9 may adopt the circuit structure shown in FIG. 5, and FIG. 10 shows the gate driving circuit shown in FIG. 20 Signal timing diagram at work.
  • H ⁇ 1> represents the fourth node H in the first-stage shift register unit 10
  • the first-stage shift register unit 10 corresponds to the first row of sub-pixel units in the display panel.
  • Q ⁇ 1> represents the first node Q in the shift register unit 10 of the first stage.
  • QB ⁇ 1> represents the second node QB in the shift register unit 10 of the first stage.
  • the numbers in parentheses indicate the number of rows of sub-pixel units in the display panel corresponding to the shift register unit 10, and the following embodiments are the same, and will not be repeated.
  • STU represents the first input signal provided to the first-stage shift register unit 10
  • CR ⁇ 1> represents the shift signal CR output by the first-stage shift register unit 10
  • OUT ⁇ 1> represents the first-stage shift register unit 10 Output drive signal OUT.
  • CR ⁇ 1> and OUT ⁇ 1> are the same.
  • 1F represents the first frame
  • DS represents the display period in the first frame
  • BL represents the blanking period in the first frame. It should be noted that the signal level in the signal timing diagram shown in FIG. 10 is only schematic and does not represent a true level value.
  • the first sub-clock signal line CLK_1 provides a high level. Since the first stage shift register unit 10 and the first sub-clock signal line CLK_1 are connected to receive the second clock signal CLKB, in the first stage The second clock signal CLKB received by the first stage shift register unit 10 in 1 is at a high level. As shown in FIG. 5, the sixth transistor M6 is turned on under the control of the high-level second clock signal CLKB, and the high-level second voltage VDD charges the second node QB ⁇ 1> through the sixth transistor M6. , So that the second node QB ⁇ 1> is pulled up to a high level.
  • the fifteenth transistor M15, the sixteenth transistor M16, and the seventeenth transistor M17 are turned on, so that the first node Q ⁇ 1> and the shift signal can be output
  • the terminal CRT and the drive signal output terminal DST are reset.
  • the first input signal STU received by the first-stage shift register unit 10 is high, so the fifth transistor M5 is turned on, so that the high-level second voltage VDD can pass through the fifth transistor.
  • M5 charges the first node Q ⁇ 1>, so that the first node Q ⁇ 1> is pulled up to a high level.
  • the eighth transistor M8 and the ninth transistor M9 are turned on under the control of the level of the first node Q ⁇ 1>, but because the third clock signal CLKC provided by the third sub-clock signal line CLK_3 is low at this time, Therefore, the shift signal CR ⁇ 1> and the driving signal OUT ⁇ 1> output by the first stage shift register unit 10 are low level.
  • the precharging operation is completed for the first node in the shift register unit 10 of the first stage.
  • the seventh transistor M7 is turned on.
  • the twelfth transistor M12 is turned on.
  • the low-level first voltage VGL1 can reset the second node QB ⁇ 1> through the seventh transistor M7 and the twelfth transistor M12, so that the level of the second node QB ⁇ 1> is pulled down to a low voltage. level. Pulling down the level of the second node QB ⁇ 1> to a low level can prevent the level of the second node QB ⁇ 1> from affecting the precharge operation of the first node Q ⁇ 1>.
  • the third clock signal CLKC provided by the third sub-clock signal line CLK_3 becomes a high level, so the shift signal CR ⁇ 1> and the drive signal OUT ⁇ 1> Change to high level.
  • the shift signal CR ⁇ 1> output by the first-stage shift register unit 10 may be provided to the second-stage shift register unit 10 as the first input signal STU1, and the drive signal output by the first-stage shift register unit 10 OUT ⁇ 1> can be provided to the first row of sub-pixel units in the display panel to drive the row of sub-pixel units to perform display operations.
  • the high-level drive signal OUT ⁇ 1> output by the first-stage shift register unit 10 can couple and pull up the level of the first node Q ⁇ 1>, so that The level of the first node Q ⁇ 1> is further pulled up.
  • the level of the first node Q ⁇ 1> is higher in the third stage 3, so that the seventh transistor M7 is turned on more fully, thereby making the second node QB ⁇ 1> level Pulled lower.
  • the second-stage shift register unit 10 since the second-stage shift register unit 10 is connected to the first sub-clock signal line CLK_1 to receive the third clock signal CLKC, the second-stage shift register unit 10 outputs a high voltage in the fourth stage 4.
  • the flat shift signal CR is provided to the first-stage shift register unit 10 as the display reset signal STD. Since the display reset signal STD is at a high level, the thirteenth transistor M13 is turned on, so that the low-level first voltage VGL1 pulls down and resets the first node Q ⁇ 1> through the thirteenth transistor M13, so that the The level of a node Q ⁇ 1> is pulled down to a low level.
  • the seventh transistor M7 Since the level of the first node Q ⁇ 1> is low, the seventh transistor M7 is turned off. At the same time, since the second clock signal CLKB received by the first-stage shift register unit 10 in the fourth stage 4 is at a high level, the sixth transistor M6 is turned on, and the high-level second voltage VDD can affect the second node QB ⁇ 1> is charged so that the level of the second node QB ⁇ 1> is pulled up to a high level.
  • the seventh transistor M7, the sixteenth transistor M16, and the seventeenth transistor M17 are turned on under the control of the level of the second node QB ⁇ 1>, so that the first node Q ⁇ 1> and the shift signal output terminal
  • the CRT and the drive signal output terminal DST are reset, so the shift signal CR ⁇ 1> and the drive signal OUT ⁇ 1> output by the first-stage shift register unit 10 become low level.
  • the first capacitor C1 can maintain the high level of the second node QB ⁇ 1>, even if the second clock signal CLKB received by the first stage shift register unit 10 becomes low It will not affect the level of the second node QB ⁇ 1>, thereby avoiding the level of the second node QB ⁇ 1> from drifting, and preventing the level of the first node Q ⁇ 1> from being in the shift register unit 10.
  • the driving signal does not need to be output, it is pulled up to a high level, so that multiple output problems of the shift register unit 10 can be avoided.
  • the first-stage shift register unit 10 drives the sub-pixel units in the first row of the display panel to complete the display operation, and so on, the second-stage and third-stage shift register units 10 drive the sub-pixel units in the display panel row by row. Complete one frame of display drive. So far, the display period of the first frame ends.
  • the fourth node H ⁇ 1> is also charged in the display period DS of the first frame 1F.
  • the sub-pixel unit of the first row needs to be compensated in the first frame 1F, then in the first frame 1F, The following operations are also performed in the display period DS.
  • the selection control signal OE provided by the seventh sub-clock signal line CLK_7 is made high, so the first transistor M1 is turned on.
  • the second input signal STU2 received by the first-stage shift register unit 10 can be the same as the shift signal CR ⁇ 1> output by the first-stage shift register unit, so that the high-level second input signal STU2 can be The four node H ⁇ 1> is charged, so that the level of the fourth node H ⁇ 1> is pulled up to a high level.
  • the foregoing charging process for the fourth node H ⁇ 1> is only an example, and the embodiments of the present disclosure include but are not limited to this.
  • the second input signal STU2 received by the shift register unit 10 of the first stage may also be the same as the shift signal CR output by the shift register unit 10 of the other stages, and at the same time, the signal provided to the seventh sub-clock signal line CLK_7 and the The signal timing of the second input signal STU2 may be the same.
  • the high potential of the fourth node H ⁇ 1> may be maintained until the blanking period BL of the first frame 1F.
  • the following operations are performed in the blanking period BL of the first frame 1F.
  • the first clock signal CLKA provided by the sixth sub-clock signal line CLK_6 is at a high level. Since the fourth node H ⁇ 1> maintains a high level at this stage, the second transistor M2 is turned on. The first clock signal CLKA with a high level is transmitted to the third node N through the second transistor M2, so that the third node N becomes a high level. The fourth transistor M4 is turned on under the control of the third node N, so the high-level second voltage VDD can charge the first node Q ⁇ 1>, and the level of the first node Q ⁇ 1> is pulled up to high Level.
  • the tenth transistor M10 and the eleventh transistor M11 are turned on, thereby making the low
  • the level of the first voltage VGL1 can reset the second node QB ⁇ 1>, so that the level of the second node QB ⁇ 1> is pulled down to a low level.
  • the third clock signal CLKC provided by the third sub-clock signal line CLK_3 becomes a high level, so the shift signal CR ⁇ 1> and the drive signal OUT ⁇ 1> Change to high level.
  • the driving signal OUT ⁇ 1> can be used to drive the sensing transistors in the first row of sub-pixel units in the display panel to achieve external compensation.
  • the first node Q ⁇ 1> still maintains a high level, so the eighth transistor M8 and the ninth transistor M9 remain conductive.
  • the third clock signal CLKC provided by the third sub-clock signal line CLK_3 becomes low, the shift signal CR ⁇ 1> and the drive signal OUT ⁇ 1> output by the first-stage shift register unit 10 become low. Level.
  • the level of the first node Q ⁇ 1> will also drop.
  • the fifth sub-clock signal line CLK_5 and the seventh sub-clock signal line CLK_7 provide a high level
  • the fourteenth transistor M14 in each stage of the shift register unit 10 in the gate drive circuit 20 is Is turned on, so that the first node Q in each stage of the shift register unit 10 can be reset; the first transistor M1 in each stage of the shift register unit 10 in the gate drive circuit 20 is turned on, because of this
  • the fourth node H in each stage of the shift register unit 10 can be reset to complete the global reset.
  • the description is made by taking the output of the driving signal corresponding to the first row of sub-pixel units of the display panel in the blanking period of the first frame as an example. Not limited. For example, when it is necessary to output the driving signal corresponding to the sub-pixel unit of the nth row of the display panel in the blanking period of a certain frame, the corresponding fourth node H needs to be pulled up high in the display period DS of the frame.
  • a high-level first clock signal CLKA is provided to raise the level of the first node Q, and then when a high-level drive signal needs to be output, a high-level
  • the flat third clock signal CLKC, n is an integer greater than zero.
  • the same timing of two signals refers to time synchronization at a high level, and the amplitude of the two signals is not required to be the same.
  • the display device 1 includes the gate driving circuit 20 provided by the embodiments of the present disclosure and a plurality of sub-pixel units 510 arranged in an array.
  • the display device 1 further includes a display panel 50, and a pixel array composed of a plurality of sub-pixel units 510 is arranged in the display panel 50.
  • the driving signal OUT output by each shift register unit 10 in the gate driving circuit 20 is provided to the sub-pixel units 510 in different rows.
  • the gate driving circuit 20 is electrically connected to the sub-pixel units 510 through the gate line GL.
  • the gate driving circuit 20 is used to provide a driving signal OUT to the pixel array.
  • the driving signal OUT may be used to drive the scan transistor and the sensing transistor in the sub-pixel unit 510.
  • the display device 1 may further include a data driving circuit 30 for providing data signals to the pixel array.
  • the data driving circuit 30 is electrically connected to the sub-pixel unit 510 through the data line DL.
  • the display device 1 in this embodiment can be: LCD panel, LCD TV, display, OLED panel, OLED TV, electronic paper display device, mobile phone, tablet computer, notebook computer, digital photo frame, navigator, etc. Products or parts with display functions.
  • the embodiment of the present disclosure also provides a driving method, which can be used to drive the shift register unit 10 provided by the embodiment of the present disclosure.
  • a plurality of the shift register units 10 can be cascaded to construct the gate provided by an embodiment of the present disclosure.
  • the driving circuit is used for driving the display panel to display at least one frame.
  • the driving method includes: the first input circuit 110 controls the level of the first node Q in response to the first input signal STU1; the output circuit 120 provides an output signal at the output terminal OP under the control of the level of the first node Q; The first control circuit 130 controls the level of the second node QB under the control of the level of the first node Q; the first reset circuit 140 controls the level of the first node QB under the control of the level of the second node QB. And the output terminal OP is reset.
  • the output terminal OP includes a shift signal output terminal CRT and a drive signal output terminal DST; the second input circuit 150 controls the level of the third node N in response to the selection control signal OE; the transmission circuit 160 The level of the first node Q is controlled according to the level of the third node N; the storage circuit 170 stabilizes the level of the second node QB.

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Abstract

一种移位寄存器单元(10)、栅极驱动电路(20)、显示装置(1)及驱动方法，可以更好地稳定第二节点(QB)的电平，移位寄存器单元(10)包括第一输入电路(110)、输出电路(120)、第一控制电路(130)、第一复位电路(140)、第二输入电路(150)、传输电路(160)和存储电路(170)；第一输入电路(110)被配置为响应于第一输入信号(STU1)对第一节点(Q)的电平进行控制，输出电路(120)被配置为在第一节点(Q)的电平的控制下在输出端(OP)提供输出信号，第一控制电路(130)被配置为在第一节点(Q)的电平的控制下，对第二节点(QB)的电平进行控制，第一复位电路(140)被配置为在第二节点(QB)的电平的控制下，对第一节点(Q)以及输出端(OP)进行复位，存储电路(170)和第二节点(QB)电连接，且被配置为稳定第二节点(QB)的电平。

Description

移位寄存器单元、栅极驱动电路、显示装置及驱动方法
相关申请的交叉引用
本申请要求于2019年2月22日递交的第201910133087.2号中国专利申请的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种移位寄存器单元、栅极驱动电路、显示装置及驱动方法。
背景技术
在显示领域特别是OLED(Organic Light-Emitting Diode，有机发光二极管)显示面板中，栅极驱动电路目前一般集成在栅极驱动芯片(GATE IC)中。在集成电路(IC)设计中，芯片的面积是影响芯片成本的主要因素，如何有效地降低芯片面积是技术开发人员需要着重考虑的。
内容
本公开至少一实施例提供一种移位寄存器单元，包括第一输入电路、输出电路、第一控制电路、第一复位电路、第二输入电路、传输电路和存储电路。所述第一输入电路被配置为响应于第一输入信号对第一节点的电平进行控制，所述输出电路被配置为在所述第一节点的电平的控制下在输出端提供输出信号，所述第一控制电路被配置为在所述第一节点的电平的控制下，对第二节点的电平进行控制，所述第一复位电路被配置为在所述第二节点的电平的控制下，对所述第一节点以及所述输出端进行复位，所述第二输入电路被配置为响应于选择控制信号对第三节点的电平进行控制，所述传输电路被配置为根据所述第三节点的电平对所述第一节点的电平进行控制，所述存储电路和所述第二节点电连接，且被配置为稳定所述第二节点的电平。
例如，在本公开一些实施例提供的移位寄存器单元中，所述第二输入电 路包括选择输入电路和传输控制电路。所述选择输入电路被配置为响应于所述选择控制信号利用第二输入信号对第四节点的电平进行控制；所述传输控制电路和所述第三节点以及所述第四节点连接，且被配置为在所述第四节点的电平的控制下将第一时钟信号传输至所述第三节点。
例如，本公开一些实施例提供的移位寄存器单元还包括第二复位电路，所述第二复位电路被配置为在所述第二节点的电平的控制下对所述第三节点进行复位。
例如，在本公开一些实施例提供的移位寄存器单元中，所述第二复位电路和所述第二节点以及所述第三节点连接。
例如，在本公开一些实施例提供的移位寄存器单元中，所述存储电路包括第一电容，所述选择输入电路包括第一晶体管，所述传输控制电路包括第二晶体管，所述传输电路包括第四晶体管；所述第一电容的第一极和所述第四节点连接，所述第一电容的第二极和所述第二节点连接；所述第一晶体管的栅极被配置为接收所述选择控制信号，所述第一晶体管的第一极被配置为接收所述第二输入信号，所述第一晶体管的第二极和所述第四节点连接；所述第二晶体管的栅极和所述第四节点连接，所述第二晶体管的第一极被配置为接收所述第一时钟信号，所述第二晶体管的第二极和所述第三节点连接；所述第四晶体管的栅极被配置为接收所述第一时钟信号，所述第四晶体管的第一极和所述第三节点连接，所述第四晶体管的第二极和所述第一节点连接。
例如，在本公开一些实施例提供的移位寄存器单元中，所述存储电路包括第一电容，所述选择输入电路包括第一晶体管，所述传输控制电路包括第二晶体管，所述第二复位电路包括第三晶体管，所述传输电路包括第四晶体管；所述第一电容的第一极和所述第四节点连接，所述第一电容的第二极和所述第二节点连接；所述第一晶体管的栅极被配置为接收所述选择控制信号，所述第一晶体管的第一极被配置为接收所述第二输入信号，所述第一晶体管的第二极和所述第四节点连接；所述第二晶体管的栅极和所述第四节点连接，所述第二晶体管的第一极被配置为接收所述第一时钟信号，所述第二晶体管的第二极和所述第三节点连接；所述第三晶体管的栅极和所述第二节点连接，所述第三晶体管的第一极和所述第三节点连接，所述第三晶体管的第二极被配置为接收第一电压；所述第四晶体管的栅极和所述第三节点连接，所述第 四晶体管的第一极被配置为接收所述第一时钟信号或第二电压，所述第四晶体管的第二极和所述第一节点连接。
例如，在本公开一些实施例提供的移位寄存器单元中，所述存储电路包括第二电容，所述选择输入电路包括第一晶体管和第一电容，所述传输控制电路包括第二晶体管，所述第二复位电路包括第三晶体管，所述传输电路包括第四晶体管；所述第二电容的第一极和所述第二节点连接，所述第二电容的第二极被配置为接收固定电平；所述第一晶体管的栅极被配置为接收所述选择控制信号，所述第一晶体管的第一极被配置为接收所述第二输入信号，所述第一晶体管的第二极和所述第四节点连接；所述第一电容的第一极和所述第四节点连接，所述第一电容的第二极和所述第三节点连接；所述第二晶体管的栅极和所述第四节点连接，所述第二晶体管的第一极被配置为接收所述第一时钟信号，所述第二晶体管的第二极和所述第三节点连接；所述第三晶体管的栅极和所述第二节点连接，所述第三晶体管的第一极和所述第三节点连接，所述第三晶体管的第二极被配置为接收第一电压；所述第四晶体管的栅极和所述第三节点连接，所述第四晶体管的第一极被配置为接收所述第一时钟信号或第二电压，所述第四晶体管的第二极和所述第一节点连接。
例如，在本公开一些实施例提供的移位寄存器单元中，所述第一控制电路还被配置为在第二时钟信号的控制下，将第二电压传输至所述第二节点；所述输出电路还被配置为接收第三时钟信号，并在所述第一节点的电平的控制下将所述第三时钟信号作为所述输出信号提供至所述输出端；所述第二时钟信号和所述第三时钟信号均为占空比为三分之一的脉冲信号，且所述第三时钟信号和所述第二时钟信号在时序上间隔第一时间，所述第一时间等于所述脉冲信号的周期的三分之二。
例如，在本公开一些实施例提供的移位寄存器单元中，所述第一输入电路包括第五晶体管，所述第一控制电路包括第六晶体管和第七晶体管，所述输出电路包括第八晶体管、第九晶体管和第三电容，所述输出端包括移位信号输出端和驱动信号输出端，所述移位信号输出端以及所述驱动信号输出端被配置为输出所述输出信号；所述第五晶体管的栅极被配置为接收所述第一输入信号，所述第五晶体管的第一极被配置为接收所述第一输入信号或所述第二电压，所述第五晶体管的第二极和所述第一节点连接；所述第六晶体管 的栅极被配置为接收所述第二时钟信号，所述第六晶体管的第一极被配置为接收所述第二电压，所述第六晶体管的第二极和所述第二节点连接；所述第七晶体管的栅极和所述第一节点连接，所述第七晶体管的第一极和所述第二节点连接，所述第七晶体管的第二极被配置为接收第一电压；所述第八晶体管的栅极和所述第一节点连接，所述第八晶体管的第一极被配置为接收所述第三时钟信号，所述第八晶体管的第二极和所述移位信号输出端连接；所述第九晶体管的栅极和所述第一节点连接，所述第九晶体管的第一极被配置为接收所述第三时钟信号，所述第九晶体管的第二极和所述驱动信号输出端连接；所述第三电容的第一极和所述第一节点连接，所述第三电容的第二极和所述驱动信号输出端连接。
例如，本公开一些实施例提供的移位寄存器单元还包括第二控制电路，所述第二控制电路被配置为在所述第一时钟信号以及所述第四节点的电平的控制下，对所述第二节点的电平进行控制。
例如，在本公开一些实施例提供的移位寄存器单元中，所述第二控制电路包括第十晶体管和第十一晶体管。所述第十晶体管的栅极被配置为接收所述第一时钟信号，所述第十晶体管的第一极和所述第二节点连接，所述第十晶体管的第二极和所述第十一晶体管的第一极连接，所述第十一晶体管的栅极和所述第四节点连接，所述第十一晶体管的第二极被配置为接收第一电压。
例如，本公开一些实施例提供的移位寄存器单元还包括第三控制电路，所述第三控制电路被配置为响应于所述第一输入信号对所述第二节点的电平进行控制。
例如，在本公开一些实施例提供的移位寄存器单元中，所述第三控制电路包括第十二晶体管，所述第十二晶体管的栅极被配置为接收所述第一输入信号，所述第十二晶体管的第一极和所述第二节点连接，所述第十二晶体管的第二极被配置为接收第一电压。
例如，本公开一些实施例提供的移位寄存器单元还包括第三复位电路和第四复位电路。所述第三复位电路被配置为响应于显示复位信号对所述第一节点进行复位，所述第四复位电路被配置为响应于全局复位信号对所述第一节点进行复位。
例如，在本公开一些实施例提供的移位寄存器单元中，所述第三复位电 路包括第十三晶体管，所述第四复位电路包括第十四晶体管；所述第十三晶体管的栅极被配置为接收所述显示复位信号，所述第十三晶体管的第一极和所述第一节点连接，所述第十三晶体管的第二极被配置为接收第一电压；所述第十四晶体管的栅极被配置为接收所述全局复位信号，所述第十四晶体管的第一极和所述第一节点连接，所述第十四晶体管的第二极被配置为接收所述第一电压。
本公开至少一实施例还提供一种栅极驱动电路，包括多个级联的如本公开的实施例提供的移位寄存器单元。
例如，本公开一些实施例提供的栅极驱动电路还包括第一子时钟信号线、第二子时钟信号线和第三子时钟信号线；第3n-2级移位寄存器单元和所述第一子时钟信号线连接以接收用于所述第3n-2级移位寄存器单元的第二时钟信号，所述第3n-2级移位寄存器单元和所述第三子时钟信号线连接以接收用于所述第3n-2级移位寄存器单元的第三时钟信号；第3n-1级移位寄存器单元和所述第二子时钟信号线连接以接收用于所述第3n-1级移位寄存器单元的第二时钟信号，所述第3n-1级移位寄存器单元和所述第一子时钟信号线连接以接收用于所述第3n-1级移位寄存器单元的第三时钟信号；第3n级移位寄存器单元和所述第三子时钟信号线连接以接收用于所述第3n级移位寄存器单元的第二时钟信号，所述第3n级移位寄存器单元和所述第二子时钟信号线连接以接收用于所述第3n级移位寄存器单元的第三时钟信号；n为大于0的整数。
本公开至少一实施例还提供一种显示装置，包括如本公开的实施例提供的栅极驱动电路。
本公开至少一实施例还提供一种如本公开的实施例提供的移位寄存器单元的驱动方法，包括：所述第一输入电路响应于第一输入信号对第一节点的电平进行控制；所述输出电路在所述第一节点的电平的控制下在输出端提供输出信号；所述第一控制电路在所述第一节点的电平的控制下，对第二节点的电平进行控制；所述第一复位电路在所述第二节点的电平的控制下，对所述第一节点以及所述输出端进行复位；所述第二输入电路响应于选择控制信号对第三节点的电平进行控制；所述传输电路根据所述第三节点的电平对所述第一节点的电平进行控制；所述存储电路稳定所述第二节点的电平。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一些实施例提供的一种移位寄存器单元的示意图；
图2为本公开一些实施例提供的另一种移位寄存器单元的示意图；
图3为本公开一些实施例提供的再一种移位寄存器单元的示意图；
图4为本公开一些实施例提供的又一种移位寄存器单元的示意图；
图5为本公开一些实施例提供的一种移位寄存器单元的电路图；
图6为本公开一些实施例提供的另一种移位寄存器单元的电路图；
图7为本公开一些实施例提供的再一种移位寄存器单元的电路图；
图8为本公开一些实施例提供的又一种移位寄存器单元的电路图；
图9为本公开一些实施例提供的一种栅极驱动电路的示意图；
图10为本公开一些实施例提供的一种对应于图9所示的栅极驱动电路工作时的信号时序图；
图11为本公开一些实施例提供的第二时钟信号和第三时钟信号的示意图；以及
图12为本公开一些实施例提供的一种显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面 的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本公开的实施例中，例如，当各个电路实现为N型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如截止)。
又例如，当各个电路实现为P型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如截止)。
目前用于OLED的栅极驱动电路通常要用三个子电路组合而成，即检测电路、显示电路和输出两者复合脉冲的连接电路(或门电路)，这样的电路结构非常复杂，无法满足显示面板的高分辨率窄边框的要求。
在对OLED显示面板中的子像素单元进行补偿时，除了在子像素单元中设置像素补偿电路进行内部补偿外，还可以通过设置感测晶体管进行外部补偿。在进行外部补偿时，由移位寄存器单元构成的栅极驱动电路需要向显示面板中的子像素单元分别提供用于扫描晶体管和感测晶体管的驱动信号，例如，在一帧的显示时段提供用于扫描晶体管的扫描驱动信号，在一帧的消隐时段提供用于感测晶体管的感测驱动信号。
在一种外部补偿方法中，栅极驱动电路输出的感测驱动信号是逐行顺序扫描的，例如，在第一帧的消隐时段输出用于显示面板中第一行的子像素单元的感测驱动信号，在第二帧的消隐时段输出用于显示面板中第二行的子像素单元的感测驱动信号，依次类推，以每帧输出对应一行子像素单元的感测驱动信号的频率逐行顺序输出，即完成对该显示面板的逐行顺序补偿。
但是，在采用上述逐行顺序补偿的方法时，可能会产生显示不良问题： 一是在进行多帧的扫描显示过程中有一条逐行移动的扫描线；二是因为进行外部补偿的时间点的差异会造成显示面板不同区域的亮度差异比较大，例如，在对显示面板的第100行的子像素单元进行外部补偿时，显示面板的第10行的子像素单元虽然已经进行过外部补偿了，但此时第10行的子像素单元的发光亮度可能已经发生变化，例如发光亮度降低，从而会造成显示面板不同区域的亮度不均匀，在大尺寸的显示面板中这种问题会更加明显。
如上所述，在栅极驱动电路驱动一个显示面板时，如果要实现外部补偿，则需要该栅极驱动电路不仅可以输出用于显示时段的扫描驱动信号，同时还需要输出用于消隐时段的感测驱动信号。
另外，例如，当需要移位寄存器单元输出驱动信号时，需要使得移位寄存器单元中的输出电路的控制端(例如和第一节点连接)的电平保持在高电平；又例如，当不需要移位寄存器单元输出驱动信号时，需要使得上述第一节点的电平保持在低电平；也就是说，第一节点的电平的高低直接影响着该移位寄存器单元的输出，在非输出阶段第一节点的电平应稳定的保持在低电平，否则移位寄存器单元在一帧时间内可能会发生多次输出。
为了更好的控制第一节点的电平，在移位寄存器单元中一般会设置控制电路以及复位电路，例如该控制电路被配置为控制第二节点的电平，该复位电路被配置为在第二节点的电平的控制下控制第一节点的电平。例如，在非输出阶段，为了保证第一节点的电平稳定在低电平，需要使得第二节点的电平保持在高电平。在非输出阶段，如果第二节点的电平未能良好地保持在高电平，则可能导致第一节点的电平发生漂移，从而影响该移位寄存器单元的正常输出。
本公开的至少一实施例提供一种移位寄存器单元，该移位寄存器单元包括第一输入电路、输出电路、第一控制电路、第一复位电路、第二输入电路、传输电路、存储电路。第一输入电路被配置为响应于第一输入信号对第一节点的电平进行控制，输出电路被配置为在第一节点的电平的控制下在输出端提供输出信号，第一控制电路被配置为在第一节点的电平的控制下，对第二节点的电平进行控制，第一复位电路被配置为在第二节点的电平的控制下，对第一节点以及输出端进行复位，第二输入电路被配置为响应于选择控制信号对第三节点的电平进行控制，传输电路被配置为根据第三节点的电平对第 一节点的电平进行控制，存储电路和第二节点电连接，且被配置为稳定第二节点的电平。
本公开的实施例还提供对应于上述移位寄存器单元的栅极驱动电路、显示装置及驱动方法。
本公开的实施例提供的移位寄存器单元、栅极驱动电路、显示装置及驱动方法，可以更好地稳定移位寄存器单元中第二节点的电平。例如，在移位寄存器单元不需要输出驱动信号的阶段(非输出阶段)时，可以使得第二节点稳定地保持在高电平，从而使得第一节点的电平不会发生漂移并稳定地保持在低电平，从而可以避免移位寄存器单元发生多次输出。同时，相应的栅极驱动电路以及显示装置还可以实现随机补偿，从而可以避免由于逐行顺序补偿造成的扫描线以及显示亮度不均匀等显示不良问题。
需要说明的是，在本公开的实施例中，随机补偿指的是区别于逐行顺序补偿的一种外部补偿方法，在某一帧的消隐时段可以随机输出对应于显示面板中任意一行的子像素单元的感测驱动信号，以下各实施例与此相同，不再赘述。
另外，在本公开的实施例中，为了说明的目的，定义“一帧”、“每帧”或“某一帧”包括依次进行的显示时段和消隐时段，例如在显示时段中栅极驱动电路输出驱动信号，该驱动信号可以驱动显示面板从第一行到最后一行完成完整的一幅图像的扫描显示，在消隐时段中栅极驱动电路输出驱动信号，该驱动信号可以用于驱动显示面板中的某一行子像素单元中的感测晶体管，以完成该行子像素单元的外部补偿。
下面结合附图对本公开的实施例及其示例进行详细说明。图1为本公开一些实施例提供的一种移位寄存器单元的示意图；图2为本公开一些实施例提供的另一种移位寄存器单元的示意图。
本公开的至少一个实施例提供一种移位寄存器单元10，如图1所示，该移位寄存器单元10包括第一输入电路110、输出电路120、第一控制电路130、第一复位电路140、第二输入电路150、传输电路160和存储电路170。多个该移位寄存器单元10可以级联构建本公开一实施例提供的栅极驱动电路，该栅极驱动电路可以用于显示装置，在显示装置的一帧画面的显示过程中提供驱动信号。
该第一输入电路110被配置为响应于第一输入信号STU1对第一节点Q的电平进行控制，例如对第一节点Q进行充电。例如，第一输入电路110可以被配置为接收第一输入信号STU1和第二电压VDD，第一输入电路110响应于第一输入信号STU1而导通，从而可以利用第二电压VDD对第一节点Q1进行充电。又例如，第一输入电路110也可以不接收第二电压VDD，直接利用第一输入信号STU1对第一节点Q1进行充电。
需要说明的是，在本公开的一些实施例中，第二电压VDD例如为高电平，以下各实施例与此相同，不再赘述。
该输出电路120被配置为在第一节点Q的电平的控制下在输出端OP提供输出信号。例如，如图2所示，在一些实施例中，输出端OP包括移位信号输出端CRT和驱动信号输出端DST，相应地，输出信号包括移位信号CR和驱动信号OUT。例如，输出电路120可以被配置为接收第三时钟信号CLKC，输出电路120在第一节点Q的电平的控制下导通时，可以将第三时钟信号CLKC作为移位信号CR提供至移位信号输出端CRT，并将第三时钟信号CLKC作为驱动信号OUT提供至驱动信号输出端DST。
例如，在一帧的显示时段中，输出电路120输出的移位信号CR可以提供至其它移位寄存器单元10以作为第一输入信号STU1，从而完成显示扫描的逐行移位；输出电路120输出的驱动信号OUT可以驱动显示面板中的某一行子像素单元进行显示扫描。
例如，当多个移位寄存器单元10级联构成一栅极驱动电路时，其中有些移位寄存器单元10可以和一个时钟信号线连接，从而接收由该时钟信号线提供的第一输入信号STU1；或者，有些移位寄存器单元10还可以接收其它级移位寄存器单元10输出的移位信号CR作为第一输入信号STU1。
需要说明的是，在一帧的显示时段中，输出电路120输出的移位信号CR和驱动信号OUT的信号波形可以相同，也可以不同，本公开的实施例对此不作限定。
该第一控制电路130被配置为在第一节点Q的电平的控制下，对第二节点QB的电平进行控制。例如，第一控制电路130和第一节点Q以及第二节点QB连接，且被配置为接收第一电压VGL1和第二电压VDD。例如，当第一节点Q处于高电平时，第一控制电路130可以利用低电平的第一电压VGL1 将第二节点QB拉低至低电平。又例如，在一些实施例中，如图2所示，第一控制电路130被配置为接收第二时钟信号CLKB，当第一节点Q处于低电平且第二时钟信号CLKB为高电平时，第一控制电路130可以响应于高电平的第二时钟信号CLKB而导通，从而可以利用高电平的第二电压VDD对第二节点QB进行充电，以将第二节点QB拉高至高电平。
需要说明的是，在本公开的一些实施例中，第一电压VGL1例如为低电平，以下各实施例与此相同，不再赘述。
该第一复位电路140被配置为在第二节点QB的电平的控制下，对第一节点Q以及输出端OP(例如包括移位信号输出端CRT和驱动信号输出端DST)进行复位。例如，如图1所示，第一复位电路140和第一节点Q、第二节点QB以及输出端OP连接，且被配置为接收低电平的第一电压VGL1。例如，当第一复位电路140在第二节点QB的电平的控制下导通时，可以利用低电平的第一电压VGL1对第一节点Q以及输出端OP进行下拉复位。
又例如，在一些实施例中，如图2所示，在输出端OP包括移位信号输出端CRT和驱动信号输出端DST的情形下，第一复位电路140还可以被配置为接收低电平的第三电压VGL2，当第一复位电路140在第二节点QB的电平的控制下导通时，可以利用低电平的第一电压VGL1对第一节点Q以及移位信号输出端CRT进行下拉复位，同时利用低电平的第三电压VGL2对驱动信号输出端DST进行下拉复位。
需要说明的是，在本公开的一些实施例中，也可以利用第一电压VGL1对驱动信号输出端DST进行下拉复位，本公开对此不作限制。另外，在本公开的实施例中，第三电压VGL2例如为低电平，第三电压VGL2可以和第一电压VGL1相同，也可以不同。以下各实施例与此相同，不再赘述。
为了实现随机补偿，如图1所示，在本公开的一些实施例中，移位寄存器单元10包括第二输入电路150和传输电路160。
该第二输入电路150被配置为响应于选择控制信号OE对第三节点N的电平进行控制。例如，如图2所示，在本公开的一些实施例中，第二输入电路150包括选择输入电路151和传输控制电路152。
该选择输入电路151被配置为响应于选择控制信号OE利用第二输入信号STU2对第四节点H的电平进行控制，例如对第四节点H进行充电，并保 持第四节点H的电平。例如，在一帧的显示时段中，选择输入电路151可以在选择控制信号OE的控制下而导通，从而利用第二输入信号STU2对第四节点H进行充电。第四节点H的电平(例如高电平)可以从一帧的显示时段一直保持到该帧的消隐时段。
该传输控制电路152和第三节点N以及第四节点H连接，且被配置为在第四节点H的电平的控制下将第一时钟信号CLKA传输至第三节点N。例如，在一些实施例中，传输控制电路152可以被配置为接收第一时钟信号CLKA，当传输控制电路152在第四节点H的电平的控制下导通时可以将第一时钟信号CLKA传输至第三节点N，从而控制第三节点N的电平。例如，在一帧的消隐时段中，当第一时钟信号CLKA为高电平时，传输控制电路152可以将该高电平传输至第三节点N，从而使得第三节点N变为高电平。
该传输电路160被配置为根据第三节点N的电平对第一节点Q的电平进行控制，例如对第一节点Q进行充电。例如，传输电路160和第一节点Q以及第三节点N连接，且被配置为接收第二电压VDD。例如，当传输电路160在第三节点N的电平的控制下导通时可以利用高电平的第二电压VDD对第一节点Q进行充电。又例如，在一些实施例中，传输电路160可以被配置为接收第一时钟信号CLKA，如上所述，当第一时钟信号CLKA为高电平时，传输控制电路152使得第三节点N变为高电平，此时传输电路160在第一时钟信号CLKA的控制下被导通，从而可以将第三节点N的高电平传输至第一节点Q，从而对第一节点Q的电平进行控制，例如对第一节点Q进行充电。
例如，当多个移位寄存器单元10级联构成一栅极驱动电路时，某一级移位寄存器单元10可以接收本级移位寄存器单元10输出的移位信号CR作为第二输入信号STU2；或者，某一级移位寄存器单元10也可以接收其它级移位寄存器单元10输出的移位信号CR作为第二输入信号STU2。
例如，当需要选择某一级移位寄存器单元10在一帧的消隐时段输出驱动信号时，则在一帧的显示时段中当该级移位寄存器单元10输出移位信号CR时，可以将该移位信号CR提供至该级移位寄存器单元10中的选择输入电路151以作为第二输入信号STU2，并使得提供至该级移位寄存器单元10的选择控制信号OE和移位信号CR的波形时序相同，从而使得该级移位寄存器单元10中的选择输入电路151导通。由于选择输入电路151导通，从而可以 利用第二输入信号STU2对第四节点H进行充电以拉高第四节点H的电平。然后，第四节点H的高电平可以从该帧的显示时段保持到该帧的消隐时段。
在该帧的消隐时段中，可以使得提供至该级移位寄存器单元10中的传输控制电路152的第一时钟信号CLKA为高电平，该传输控制电路152在第四节点H的高电平的控制下被导通，从而可以将高电平的第一时钟信号CLKA传输至第三节点N，使得第三节点N的电平变为高电平。该级移位寄存器单元10中的传输电路160在第三节点N的高电平的控制下被导通，从而可以利用高电平的第二电压VDD对第一节点Q进行充电以拉高第一节点Q的电平。该级移位寄存器单元10中的输出电路120在第一节点Q的高电平的控制下被导通，从而在输出端提供输出信号，例如在驱动信号输出端DST输出驱动信号OUT。例如，该驱动信号OUT可以用于驱动显示面板中的某一行子像素单元中的感测晶体管，以完成该行子像素单元的外部补偿。
该存储电路170和第二节点QB电连接，且被配置为稳定第二节点QB的电平。例如，在一些实施例中，存储电路170可以包括电容，例如，可以使得该电容的第一极和第二节点QB连接，并使得该电容的第二极被配置为接收固定电平，从而使得该电容可以稳定第二节点QB的电平。例如，当移位寄存器单元10不需要输出驱动信号时，存储电路170可以使得第二节点QB稳定地保持在高电平，从而使得第一节点Q的电平不会发生漂移并稳定地保持在低电平，从而可以避免移位寄存器单元10发生多次输出问题。
例如，如图2所示，在一些实施例中，存储电路170可以被配置为接收第一电压VGL1，例如，当存储电路170包括电容时，可以使得该电容的一极接收第一电压VGL1。
例如，如图3或图4所示，在另一些实施例中，存储电路170还可以和第四节点H连接，例如，当存储电路170包括电容时，可以使得该电容的一极和第四节点H连接。
在本公开的一些实施例提供的移位寄存器单元10中，当存储电路170既与第二节点QB连接又与第四节点H连接时，该存储电路170不仅可以用于稳定第二节点QB的电平，还可以用于稳定第四节点H的电平。
需要说明的是，在本公开的实施例中，高电平和低电平是相对而言的。高电平表示一个较高的电压范围(例如，高电平可以采用5V、10V或其他合 适的电压)，且多个高电平可以相同也可以不同。类似地，低电平表示一个较低的电压范围(例如，低电平可以采用0V、-5V、-10V或其他合适的电压)，且多个低电平可以相同也可以不同。例如，高电平的最小值比低电平的最大值大。
另外，需要说明的是，在本公开的实施例中，对一个节点(例如第一节点Q、第二节点QB等)的电平进行控制，包括对该节点进行充电以拉高该节点的电平，或者对该节点进行放电以拉低该节点的电平。例如，可以设置一个与该节点电连接的电容，对该节点进行充电即表示对与该节点电连接的电容进行充电；类似地，对该节点进行放电即表示对与该节点电连接的电容进行放电；通过该电容可以维持该节点的高电平或低电平。
如图2所示，本公开的一些实施例提供的移位寄存器单元10还包括第二复位电路180，该第二复位电路180被配置为在第二节点QB的电平的控制下对第三节点N进行复位。
例如，第二复位电路180和第二节点QB、第三节点N连接，且被配置为接收低电平的第一电压VGL1。例如，当第二节点QB的电平为高电平时，第二复位电路180可以在第二节点QB的电平的控制下导通，从而可以利用低电平的第一电压VGL1对第三节点N进行复位。
在本公开的一些实施例提供的移位寄存器单元10中，当第二节点QB的电平为高电平时，可以通过第二复位电路180将第三节点N的电平拉低至低电平，从而可以使得传输电路160被截止，从而可以避免传输电路160对第一节点Q进行充电，进而可以进一步地避免该移位寄存器单元10发生多次输出问题。
在本公开的一些实施例提供的移位寄存器单元10中，如图2-4所示，第一控制电路130还被配置为在第二时钟信号CLKB的控制下，将第二电压VDD传输至第二节点QB。输出电路120还被配置为接收第三时钟信号CLKC，并在第一节点Q的电平的控制下将第三时钟信号CLKC作为输出信号提供至输出端OP(例如包括移位信号输出端CRT和驱动信号输出端DST)。
图11为本公开一些实施例提供的第二时钟信号和第三时钟信号的示意图。例如，如图11所示，第二时钟信号CLKB和第三时钟信号CLKC均为 占空比为三分之一的脉冲信号，且第三时钟信号CLKC和第二时钟信号CLKB在时序上间隔第一时间T1，第一时间T1等于脉冲信号的周期T的三分之二。
如图4所示，本公开的一些实施例提供的移位寄存器单元10还包括第二控制电路210，该第二控制电路210被配置为在第一时钟信号CLKA以及第四节点H的电平的控制下，对第二节点QB的电平进行控制。
例如，第二控制电路210和第二节点QB以及第四节点H连接，且被配置为接收第一时钟信号CLKA以及低电平的第一电压VGL1。例如，在一帧的消隐时段中，当第四节点H为高电平且第一时钟信号CLKA为高电平时，第二控制电路210被导通，从而可以利用低电平的第一电压VGL1对第二节点QB进行下拉。
在本公开的一些实施例提供的移位寄存器单元10中，例如，在一帧的消隐时段中，当第一时钟信号CLKA为高电平且第四节点H为高电平时，移位寄存器单元10中的传输电路160被导通，从而可以对第一节点Q进行充电。在传输电路160对第一节点Q进行充电的同时，通过第二控制电路210将第二节点QB的电平拉低至低电平，可以避免第二节点QB对第一节点Q的影响，使得传输电路160对第一节点Q的充电更充分，从而有利于该移位寄存器单元10在消隐时段正常地输出驱动信号OUT，例如，该驱动信号OUT可以用于驱动显示面板中的某一行子像素单元中的感测晶体管，以完成该行子像素单元的外部补偿。
如图4所示，本公开的一些实施例提供的移位寄存器单元10还包括第三控制电路220。该第三控制电路220被配置为响应于第一输入信号STU1对第二节点QB的电平进行控制。
例如，第三控制电路220和第二节点QB连接，且被配置为接收第一输入信号STU1以及低电平的第一电压VGL1。例如，在一帧的显示时段中，第三控制电路220响应于第一输入信号STU1而导通，从而可以利用低电平的第一电压VGL1对第二节点QB进行下拉复位。将第二节点QB下拉至低电平，可以避免第二节点QB对第一节点Q的影响，从而使得在显示时段中对第一节点Q的充电更充分。
如图4所示，本公开的一些实施例提供的移位寄存器单元10还包括第三 复位电路230和第四复位电路240。
该第三复位电路230被配置为响应于显示复位信号STD对第一节点Q进行复位。例如，该第三复位电路230和第一节点Q连接，且被配置为接收显示复位信号STD以及低电平的第一电压VGL1。例如，在一帧的显示时段中，第三复位电路230响应于显示复位信号STD而导通，从而可以利用低电平的第一电压VGL1对第一节点Q进行下拉复位。例如，当多个移位寄存器单元10级联构成一栅极驱动电路时，某一级移位寄存器单元10可以接收其它级移位寄存器单元10输出的移位信号CR作为显示复位信号STD。
该第四复位电路240被配置为响应于全局复位信号TRST对第一节点Q进行复位。例如，该第四复位电路240和第一节点Q连接，且被配置为接收全局复位信号TRST以及低电平的第一电压VGL1。例如，当多个移位寄存器单元10级联构成一栅极驱动电路时，在一帧的显示时段前，各级移位寄存器单元10中的第四复位电路240都响应于全局复位信号TRST而导通，从而使得低电平的第一电压VGL1可以通过第四复位电路240对第一节点Q进行下拉复位。
需要说明的是，在本公开的实施例中，各个节点(第一节点Q、第二节点QB、第三节点N和第四节点H等)和各个输出端(输出端OP、移位信号输出端CRT、驱动信号输出端DST等)均是为了更好地描述电路结构而设置的，并非表示实际存在的部件。节点表示电路结构中相关电路连接的汇合点，即与具有相同节点标识连接的相关电路彼此之间是电连接的。例如，如图4所示，第一控制电路130、第一复位电路140、第二控制电路210、第三控制电路220、存储电路170以及第二复位电路180都和第二节点QB连接，也就是表示这些电路彼此之间是电连接的。
本领域技术人员可以理解，尽管图4中示出了多个控制电路和多个复位电路，然而上述示例并不能限制本公开的保护范围。在实际应用中，技术人员可以根据情况选择使用或不使用上述各电路中的一个或多个，基于前述各电路的各种组合变型均不脱离本公开的原理，对此不再赘述。
在本公开的一些实施例中，图4中所示的移位寄存器单元10可以实现为图5所示的电路结构。如图5所示，该移位寄存器单元10包括：第一晶体管M1至第十七晶体管M17、第一电容C1、以及第三电容C3。图1-图3的移 位寄存器单元10可以类似的方式实现，例如，作为存储电路170的电容的一极和第二节点QB连接，另一极和其他对应的节点(例如第四节点H)连接或者被配置为接收固定电平(例如第一电压VGL1)。
如图5所示，选择输入电路151可以实现为第一晶体管M1。第一晶体管M1的栅极被配置为接收选择控制信号OE，第一晶体管M1的第一极被配置为接收第二输入信号STU2，第一晶体管M1的第二极和第四节点H连接。例如，当选择控制信号OE为高电平时，第一晶体管M1导通，从而可以利用第二输入信号STU2对第四节点H进行充电。例如，在一些实施例中，可以使得第二输入信号STU2为该移位寄存器单元10输出的移位信号CR，同时使得选择控制信号OE的信号时序和第二输入信号STU2相同，也就是说，使得选择控制信号OE和第二输入信号STU2同时为高电平。
如图5所示，传输控制电路152可以实现为第二晶体管M2。第二晶体管M2的栅极和第四节点H连接，第二晶体管M2的第一极被配置为接收第一时钟信号CLKA，第二晶体管M2的第二极和第三节点N连接。例如，当第四节点H为高电平时，第二晶体管M2导通，从而可以将第一时钟信号CLKA传输至第三节点N以拉高第三节点N的电平。
如图5所示，第二复位电路180可以实现为第三晶体管M3。第三晶体管M3的栅极和第二节点QB连接，第三晶体管M3的第一极和第三节点N连接，第三晶体管M3的第二极被配置为接收低电平的第一电压VGL1。例如，当第二节点QB的电平为高电平时，第三晶体管M3导通，低电平的第一电压VGL1可以通过第三晶体管M3对第三节点N进行复位。
如图5所示，传输电路160可以包括第四晶体管M4。第四晶体管M4的栅极和第三节点N连接，第四晶体管M4的第一极被配置为接收高电平的第二电压VDD，第四晶体管M4的第二极和第一节点Q连接。例如，当第三节点N的电平为高电平时，第四晶体管M4导通，第二电压VDD可以通过第四晶体管M4对第一节点Q进行充电。
例如，当该移位寄存器单元10不需要输出驱动信号时，第二节点QB的电平为高电平，低电平的第一电压VGL1通过第三晶体管M3对第三节点N进行复位以拉低第三节点N的电平。由于第三节点N为低电平，第四晶体管M4截止，从而可以避免第二电压VDD对第一节点Q进行充电。
如图5所示，第一输入电路110可以实现为第五晶体管M5。第五晶体管的栅极被配置为接收第一输入信号STU1，第五晶体管M5的第一极被配置为接收第二电压VDD，第五晶体管M5的第二极和第一节点Q连接。例如，当多个移位寄存器单元10级联构成一栅极驱动电路时，某一级的移位寄存器单元10可以接收前一级移位寄存器单元10的移位信号CR而作为本级移位寄存器单元10的第一输入信号STU1。例如，当第一输入信号STU1为高电平时，第五晶体管M5导通，高电平的第二电压VDD可以通过第五晶体管M5对第一节点Q进行充电以拉高第一节点Q的电平。
需要说明的是，在本公开的一些实施例中，第五晶体管M5的第一极还可以被配置为接收第一输入信号STU1，第五晶体管M5在第一输入信号STU1的控制下导通时可以直接利用第一输入信号STU1对第一节点Q进行充电。本公开的实施例对第一输入电路110的实现方式不作限定。
如图5所示，输出电路120可以实现为包括第八晶体管M8、第九晶体管M9以及第三电容C3。
第八晶体管M8的栅极和第一节点Q连接，第八晶体管M8的第一极被配置为接收第三时钟信号CLKC，第八晶体管M8的第二极和移位信号输出端CRT连接。
第九晶体管M9的栅极和第一节点Q连接，第九晶体管M9的第一极被配置为接收第三时钟信号CLKC，第九晶体管M9的第二极和驱动信号输出端DST连接。
第三电容C3的第一极和第一节点Q连接，第三电容C3的第二极和驱动信号输出端DST连接。
例如，当第一节点Q为高电平时，第八晶体管M8和第九晶体管M9导通，第八晶体管M8可以将第三时钟信号CLKC作为移位信号CR提供至移位信号输出端CRT，例如该移位信号CR可以提供至相邻的其它移位寄存器单元10以作为第一输入信号STU1或者显示复位信号STD。另外，第九晶体管M9可以将第三时钟信号CLKC作为驱动信号OUT提供至驱动信号输出端DST，例如在一帧的显示时段中，该驱动信号OUT可以驱动显示面板中的某一行子像素单元进行显示扫描；又例如，在一帧的消隐时段中，该驱动信号OUT可以用于驱动显示面板中的某一行子像素单元中的感测晶体管， 以完成对该行子像素单元的外部补偿。
在本公开的一些实施例提供的移位寄存器单元10中，通过第三电容C3可以维持第一节点Q的电平。需要说明的是，第三电容C3的第二极也可以与移位信号输出端CRT连接，本公开的实施例对此不作限定。例如，当移位信号输出端CRT或者驱动信号输出端DST输出高电平信号时，该高电平信号可以通过第三电容C3的耦合作用以进一步拉高第一节点Q的电平，从而使得第八晶体管M8和第九晶体管M9被导通的更充分，从而更有利于移位信号CR和驱动信号OUT的输出。
如图5所示，第一控制电路130可以实现为包括第六晶体管M6和第七晶体管M7。
第六晶体管M6的栅极被配置为接收第二时钟信号CLKB，第六晶体管M6的第一极被配置为接收第二电压VDD，第六晶体管M6的第二极和第二节点QB连接。
第七晶体管M7的栅极和第一节点Q连接，第七晶体管M7的第一极和第二节点QB连接，第七晶体管M7的第二极被配置为接收第一电压VGL1。
例如，当第一节点Q的电平为高电平时，第七晶体管M7导通，低电平的第一电压VGL1可以对第二节点QB进行复位。例如，当第一节点Q的电平为低电平且第二时钟信号CLKB为高电平时，第六晶体管M6导通，第七晶体管M7截止，高电平的第二电压VDD可以通过第六晶体管M6对第二节点QB进行充电，从而将第二节点QB的电平拉高至高电平。
如图5所示，第二控制电路210可以实现为包括第十晶体管M10和第十一晶体管M11。
第十晶体管M10的栅极被配置为接收第一时钟信号CLKA，第十晶体管M10的第一极和第二节点QB连接，第十晶体管M10的第二极和第十一晶体管M11的第一极连接，第十一晶体管M11的栅极和第四节点H连接，第十一晶体管M11的第二极被配置为接收第一电压VGL1。例如，当第一时钟信号CLKA为高电平且第四节点H为高电平时，第十晶体管M10以及第十一晶体管M11导通，从而使得低电平的第一电压VGL1可以对第二节点QB进行下拉复位。
如图5所示，第三控制电路220可以实现为第十二晶体管M12。第十二 晶体管M12的栅极被配置为接收第一输入信号STU1，第十二晶体管M12的第一极和第二节点QB连接，第十二晶体管M12的第二极被配置为接收第一电压VGL1。例如，当第一输入信号STU1为高电平时，第十二晶体管M12导通，从而可以使得低电平的第一电压VGL1对第二节点QB进行下拉复位。
如图5所示，第一复位电路140可以实现为包括第十五晶体管M15、第十六晶体管M16以及第十七晶体管M17。
第十五晶体管M15的栅极和第二节点QB连接，第十五晶体管M15的第一极和第一节点Q连接，第十五晶体管M15的第二极被配置为接收第一电压VGL1。
第十六晶体管M16的栅极和第二节点QB连接，第十六晶体管M16的第一极和移位信号输出端CRT连接，第十六晶体管M16的第二极被配置为接收第一电压VGL1。
第十七晶体管M17的栅极和第二节点QB连接，第十七晶体管M17的第一极和驱动信号输出端DST连接，第十七晶体管M17的第二极被配置为接收第三电压VGL2。
例如，当第二节点QB为高电平时，第十五晶体管M15和第十六晶体管M16导通，从而使得低电平的第一电压VGL1可以对第一节点Q以及移位信号输出端CRT进行复位；同时第十七晶体管M17导通，从而使得低电平的第三电压VGL2可以对驱动信号输出端DST进行复位。
需要说明的是，在本公开的一些实施例中，第十七晶体管M17的第二极也可以被配置为接收第一电压VGL1，从而利用第一电压VGL1对驱动信号输出端DST进行复位。
如图5所示，第三复位电路230可以实现为第十三晶体管M13。第十三晶体管M13的栅极被配置为接收显示复位信号STD，第十三晶体管M13的第一极和第一节点Q连接，第十三晶体管M13的第二极被配置为接收第一电压VGL1。
例如，当多个移位寄存器单元10级联构成一栅极驱动电路时，某一级的移位寄存器单元10可以接收后一级移位寄存器单元10的移位信号CR而作为本级移位寄存器单元10的显示复位信号STD。例如，当显示复位信号STD为高电平时，第十三晶体管M13导通，从而使得低电平的第一电压VGL1 可以对第一节点Q进行下拉复位。
如图5所示，第四复位电路240可以实现为第十四晶体管M14。第十四晶体管M14的栅极被配置为接收全局复位信号TRST，第十四晶体管M14的第一极和第一节点Q连接，第十四晶体管M14的第二极被配置为接收第一电压VGL1。
例如，当多个移位寄存器单元10级联构成一栅极驱动电路时，在一帧的显示时段前，各级移位寄存器单元10中的第十四晶体管M14都响应于全局复位信号TRST而导通，从而实现该栅极驱动电路的全局复位。
如图5所示，存储电路170可以实现为第一电容C1，第一电容C1的第一极和第四节点H连接，第一电容C1的第二极和第二节点QB连接。第一电容C1可以稳定第二节点QB的电平。例如，当第二时钟信号CLKB为高电平时，第二电压VDD通过第六晶体管M6对第二节点QB进行充电，从而可以将第二节点QB的电平拉高至高电平。然后，当第二时钟信号CLKB变为低电平时，第六晶体管M6截止，即对第二节点QB的充电路径被截止，此时由于第一电容C1和第二节点QB连接，所以第一电容C1可以维持第二节点QB的高电平，避免第二节点QB的电平发生漂移而对第一节点Q的电平造成影响。
在本公开的一些实施例提供的移位寄存器单元10中，第一电容C1除了和第二节点QB连接外，还与第四节点H连接，从而使得第一电容C1还可以用于稳定第四节点H的电平。采用这种方式可以使得第一电容C1被复用，从而可以节省电容数量，从而简化电路结构，减小采用该移位寄存器单元10的显示装置的边框尺寸，更有利于提高该显示装置的PPI。
在本公开的一些实施例中，移位寄存器单元10还可以实现为图6所示的电路结构。下面只描述图6所示的移位寄存器单元10和图5所示的移位寄存器单元10的区别，相同之处在此不再赘述。
如图6所示，在该移位寄存器单元10中不包括第二复位电路180，即不包括第三晶体管M3。
如图6所示，在该移位寄存器单元10中，第四晶体管M4的栅极被配置为接收第一时钟信号CLKA，第四晶体管M4的第一极和第三节点N连接，第四晶体管M4的第二极和第一节点Q连接。例如，当第四节点H的电平为 高电平且第一时钟信号CLKA为高电平时，第二晶体管M2和第四晶体管M4均导通，从而使得高电平的第一时钟信号CLKA可以通过第二晶体管M2以及第四晶体管M4对第一节点Q进行充电。
在本公开的一些实施例中，移位寄存器单元10还可以实现为图7所示的电路结构。下面只描述图7所示的移位寄存器单元10和图5所示的移位寄存器单元10的区别，相同之处在此不再赘述。
如图7所示，在该移位寄存器单元10中，选择输入电路151实现为包括第一晶体管M1以及第一电容C1，存储电路170实现为第二电容C2。
如图7所示，第一电容C1的第一极和第四节点H连接，第一电容C1的第二极和第三节点N连接。第二电容C2的第一极和第二节点QB连接，第二电容C2的第二极被配置为接收固定电平，例如，被配置为接收第一电压VGL1。本公开的实施例对第二电容C2的连接方式不作限定，第二电容C2的第二极还可以接收其它固定电平，例如接收第二电压VDD、第三电压VGL2等。在本公开的一些实施例提供的移位寄存器单元10中，第二电容C2可以用于稳定第二节点QB的电平。
在本公开的一些实施例中，移位寄存器单元10还可以实现为图8所示的电路结构。下面只描述图8所示的移位寄存器单元10和图7所示的移位寄存器单元10的区别，相同之处在此不再赘述。
如图8所示，第一电容C1的第一极和第四节点H连接，第一电容C1的第二极被配置为接收第一电压VGL1。需要说明的是，本公开的实施例对第一电容C1的连接方式不作限定，例如第一电容C1的第二极还可以被配置为接收其它固定电平，例如接收第二电压VDD、第三电压VGL2等。
需要说明的是，本公开的实施例提供的移位寄存器单元10中的晶体管均以N型晶体管为例进行说明。
本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。此外，按照晶体管的特性可以将晶体管分为N型和P型晶体管。当晶体管为N型晶体 管时，开启电压为高电平电压(例如，5V、10V或其他合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)；以下各实施例中的晶体管也均以N型晶体管为例进行说明，不再赘述。本公开的实施例包括但不限于此，例如本公开的实施例提供的移位寄存器单元中的一个或多个晶体管也可以采用P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)，关闭电压为高电平电压(例如，5V、10V或其他合适的电压)。
如前所述，在本公开的实施例提供的移位寄存器单元10中，可以利用第一电容C1稳定第四节点H的电平或第二节点QB的电平，利用第二电容C2稳定第二节点QB的电平，利用第三电容C3稳定第一节点Q的电平。第一电容C1、第二电容C2和第三电容C3可以是通过工艺制程制作的电容器件，例如通过制作专门的电容电极来实现电容器件，该电容的各个电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现，或者在一些示例中，通过设计电路布线参数使得第一电容C1、第二电容C2和第三电容C3也可以通过各个器件之间的寄生电容实现。第一电容C1、第二电容C2和第三电容C3的连接方式不局限于上面描述的方式，也可以为其他适用的连接方式，只要能存储写入到第四节点H、第二节点QB和第一节点Q的电平即可。
本公开的一些实施例还提供一种栅极驱动电路20，如图9所示，该栅极驱动电路20包括多个级联的移位寄存器单元10，其中任意一个或多个移位寄存器单元10可以采用本公开的实施例提供的移位寄存器单元10的结构或其变型。图9中的A1、A2、A3和A4表示四个级联的移位寄存器单元10。当该栅极驱动电路20用于驱动一显示面板时，A1、A2、A3以及A4的输出信号可以分别驱动显示面板中的四行子像素单元。例如，A1、A2、A3以及A4可以分别驱动显示面板的第一行、第二行、第三行和第四行子像素单元。
本公开的实施例提供的栅极驱动电路20，可以稳定第二节点QB的电平，当不需要输出驱动信号时，可以使得第二节点QB稳定地保持在高电平，从而使得第一节点Q的电平不会发生漂移并稳定地保持在低电平，从而可以避免该栅极驱动电路20发生多次输出问题。同时该栅极驱动电路20还可以实现随机补偿，从而可以避免由于逐行顺序补偿造成的扫描线以及显示亮度不均匀等显示不良问题。
下面以图9所示的栅极驱动电路20为例，对栅极驱动电路20中的信号线进行说明。
如图9所示，栅极驱动电路20包括第一子时钟信号线CLK_1、第二子时钟信号线CLK_2和第三子时钟信号线CLK_3。
第3n-2级移位寄存器单元(例如第一级移位寄存器单元A1)和第一子时钟信号线CLK_1连接以接收用于第3n-2级移位寄存器单元的第二时钟信号CLKB，第3n-2级移位寄存器单元和第三子时钟信号线CLK_3连接以接收用于第3n-2级移位寄存器单元的第三时钟信号CLKC。
第3n-1级移位寄存器单元(例如第二级移位寄存器单元A2)和第二子时钟信号线CLK_2连接以接收用于第3n-1级移位寄存器单元的第二时钟信号CLKB，第3n-1级移位寄存器单元和第一子时钟信号线CLK_1连接以接收用于第3n-1级移位寄存器单元的第三时钟信号CLKC。
第3n级移位寄存器单元(例如第三级移位寄存器单元A3)和第三子时钟信号线CLK_3连接以接收用于第3n级移位寄存器单元的第二时钟信号CLKB，第3n级移位寄存器单元和第二子时钟信号线CLK_2连接以接收用于第3n级移位寄存器单元的第三时钟信号CLKC；n为大于零的整数。
关于第一子时钟信号线CLK_1、第二子时钟信号线CLK_2和第三子时钟信号线CLK_3提供的信号时序如图10所示。如图10所示，第一子时钟信号线CLK_1、第二子时钟信号线CLK_2和第三子时钟信号线CLK_3提供的信号均为占空比为三分之一的脉冲信号。
在本公开的实施例提供的栅极驱动电路20中，通过三条子时钟信号线向各级移位寄存器单元10提供第二时钟信号CLKB以及第三时钟信号CLKC，可以节省信号线的数量，从而简化电路结构，减小采用该栅极驱动电路20的显示装置的边框尺寸，更有利于提高该显示装置的PPI。
如图9所示，栅极驱动电路20还包括第四子时钟信号线CLK_4、第五子时钟信号线CLK_5、第六子时钟信号线CLK_6和第七子时钟信号线CLK_7。
例如，栅极驱动电路20中的每一级移位寄存器单元10都和第四子时钟信号线CLK_4连接以接收第二电压VDD。栅极驱动电路20中的每一级移位寄存器单元10都和第五子时钟信号线CLK_5连接以接收全局复位信号 TRST。栅极驱动电路20中的每一级移位寄存器单元10都和第六子时钟信号线CLK_6连接以接收第一时钟信号CLKA。栅极驱动电路20中的每一级移位寄存器单元10都和第七子时钟信号线CLK_7连接以接收选择控制信号OE。
如图9所示，除了第一级移位寄存器单元10外，其它级移位寄存器单元10和前一级移位寄存器单元10连接以接收移位信号CR并作为第一输入信号STU1。除了最后一级移位寄存器单元10外，其它级移位寄存器单元10和后一级移位寄存器单元10连接以接收移位信号CR并作为显示复位信号STD。
需要说明的是，图9中所示的级联关系仅是一种示例，根据本公开的描述，还可以根据实际情况采用其它级联方式。
例如，在一些实施例中，图9所示的栅极驱动电路20中的移位寄存器单元10可以采用图5中所示的电路结构，图10示出了图9所示的栅极驱动电路20工作时的信号时序图。
在图10中，H<1>表示第一级移位寄存器单元10中的第四节点H，第一级移位寄存器单元10对应显示面板中的第一行子像素单元。Q<1>表示第一级移位寄存器单元10中的第一节点Q。QB<1>表示第一级移位寄存器单元10中的第二节点QB。括号中的数字表示移位寄存器单元10对应的显示面板中的子像素单元的行数，以下各实施例与此相同，不再赘述。
STU表示提供至第一级移位寄存器单元10的第一输入信号，CR<1>表示第一级移位寄存器单元10输出的移位信号CR，OUT<1>表示第一级移位寄存器单元10输出的驱动信号OUT。例如，如图10所示，在本实施例中，CR<1>和OUT<1>相同。
1F表示第一帧，DS表示第一帧中的显示时段，BL表示第一帧中的消隐时段。需要说明的是，图10所示的信号时序图中的信号电平只是示意性的，不代表真实电平值。
下面结合图10中的信号时序图以及图5所示的移位寄存器单元10，对图9中所示的栅极驱动电路20的工作原理进行说明。
在第一帧1F的显示时段DS中，针对第一级移位寄存器单元10的工作过程描述如下。
在第一阶段1中，第一子时钟信号线CLK_1提供高电平，由于第一级移位寄存器单元10和第一子时钟信号线CLK_1连接以接收第二时钟信号CLKB，所以在第一阶段1中第一级移位寄存器单元10接收的第二时钟信号CLKB为高电平。如图5所示，第六晶体管M6在高电平的第二时钟信号CLKB的控制下被导通，高电平的第二电压VDD通过第六晶体管M6对第二节点QB<1>进行充电，从而使得第二节点QB<1>被拉高至高电平。由于第二节点QB<1>为高电平，所以第十五晶体管M15、第十六晶体管M16以及第十七晶体管M17被导通，从而可以对第一节点Q<1>、移位信号输出端CRT以及驱动信号输出端DST进行复位。
在第二阶段2中，第一级移位寄存器单元10接收的第一输入信号STU为高电平，所以第五晶体管M5导通，从而使得高电平的第二电压VDD可以通过第五晶体管M5对第一节点Q<1>进行充电，使得第一节点Q<1>被拉高至高电平。第八晶体管M8和第九晶体管M9在第一节点Q<1>的电平的控制下被导通，但由于此时第三子时钟信号线CLK_3提供的第三时钟信号CLKC为低电平，所以第一级移位寄存器单元10输出的移位信号CR<1>和驱动信号OUT<1>为低电平。在第二阶段2对第一级移位寄存器单元10中第一节点完成预充电操作。
同时，在第二阶段2中，由于第一节点Q<1>变为高电平，所以第七晶体管M7导通。另外，由于第一输入信号为高电平，所以第十二晶体管M12导通。低电平的第一电压VGL1可以通过第七晶体管M7以及第十二晶体管M12对第二节点QB<1>进行复位操作，从而使得第二节点QB<1>的电平被拉低至低电平。将第二节点QB<1>的电平拉低至低电平可以避免第二节点QB<1>的电平对第一节点Q<1>的预充电操作造成影响。
在第三阶段3中，第三子时钟信号线CLK_3提供的第三时钟信号CLKC变为高电平，所以第一级移位寄存器单元10输出的移位信号CR<1>和驱动信号OUT<1>变为高电平。例如，第一级移位寄存器单元10输出的移位信号CR<1>可以提供至第二级移位寄存器单元10以作为第一输入信号STU1，第一级移位寄存器单元10输出的驱动信号OUT<1>可以提供至显示面板中的第一行子像素单元，以驱动该行子像素单元进行显示操作。
另外，由于第三电容C3的耦合作用，第一级移位寄存器单元10输出的 高电平的驱动信号OUT<1>可以对第一节点Q<1>的电平进行耦合上拉，从而使得第一节点Q<1>的电平进一步被拉高。相对于第二阶段2，第一节点Q<1>的电平在第三阶段3中更高，从而使得第七晶体管M7被导通的更充分，从而使得第二节点QB<1>电平被拉的更低。
在第四阶段4中，由于第二级移位寄存器单元10和第一子时钟信号线CLK_1连接以接收第三时钟信号CLKC，所以第二级移位寄存器单元10在第四阶段4输出高电平的移位信号CR，该移位信号CR被提供至第一级移位寄存器单元10以作为显示复位信号STD。由于显示复位信号STD为高电平，所以第十三晶体管M13导通，从而使得低电平的第一电压VGL1通过第十三晶体管M13对第一节点Q<1>进行下拉复位，从而使得第一节点Q<1>的电平被拉低至低电平。
由于第一节点Q<1>的电平为低电平，所以第七晶体管M7截止。同时由于第一级移位寄存器单元10在第四阶段4接收的第二时钟信号CLKB为高电平，所以第六晶体管M6导通，高电平的第二电压VDD可以对第二节点QB<1>进行充电，以使得第二节点QB<1>的电平被拉高至高电平。第七晶体管M7、第十六晶体管M16以及第十七晶体管M17在第二节点QB<1>的电平的控制下被导通，从而可以对第一节点Q<1>、移位信号输出端CRT以及驱动信号输出端DST进行复位，所以使得第一级移位寄存器单元10输出的移位信号CR<1>以及驱动信号OUT<1>变为低电平。
然后，显示时段DS的其余时间里，由于第一电容C1可以维持第二节点QB<1>的高电平，所以即使第一级移位寄存器单元10接收的第二时钟信号CLKB变为低电平，也不会影响第二节点QB<1>的电平，从而可以避免第二节点QB<1>的电平发生漂移，避免第一节点Q<1>的电平在移位寄存器单元10不需要输出驱动信号时被拉高至高电平，从而可以避免该移位寄存器单元10发生多次输出问题。
第一级移位寄存器单元10驱动显示面板中第一行的子像素单元完成显示操作后，依次类推，第二级、第三级等移位寄存器单元10逐行驱动显示面板中的子像素单元完成一帧的显示驱动。至此，第一帧的显示时段结束。
同时在第一帧1F的显示时段DS中还对第四节点H<1>进行充电，例如，当第一帧1F中需要对第一行子像素单元进行补偿时，则在第一帧1F的显示 时段DS中还进行如下操作。
在第三阶段3中，使得第七子时钟信号线CLK_7提供的选择控制信号OE为高电平，所以第一晶体管M1被导通。同时可以使得第一级移位寄存器单元10接收的第二输入信号STU2和第一级移位寄存器单元输出的移位信号CR<1>相同，从而高电平的第二输入信号STU2可以对第四节点H<1>进行充电，使得第四节点H<1>的电平被拉高至高电平。
需要说明的是，上述对第四节点H<1>的充电过程仅是一种示例，本公开的实施例包括但不限于此。例如，第一级移位寄存器单元10接收的第二输入信号STU2还可以和其它级移位寄存器单元10输出的移位信号CR相同，同时使得提供至第七子时钟信号线CLK_7的信号和该第二输入信号STU2的信号时序相同即可。
第四节点H<1>的高电位可以一直保持到第一帧1F的消隐时段BL中。当第一帧1F中需要对第一行子像素单元进行补偿时，则在第一帧1F的消隐时段BL中进行如下操作。
在第五阶段5中，第六子时钟信号线CLK_6提供的第一时钟信号CLKA为高电平，由于在此阶段第四节点H<1>保持高电平，所以第二晶体管M2导通，高电平的第一时钟信号CLKA通过第二晶体管M2传输至第三节点N，从而使得第三节点N变为高电平。第四晶体管M4在第三节点N的控制下导通，所以高电平的第二电压VDD可以对第一节点Q<1>进行充电，第一节点Q<1>的电平被上拉至高电平。
同时，在第五阶段5中，由于第一时钟信号CLKA为高电平且第四节点H<1>为高电平，所以第十晶体管M10以及第十一晶体管M11被导通，从而使得低电平的第一电压VGL1可以对第二节点QB<1>进行复位，从而使得第二节点QB<1>的电平被拉低至低电平。
在第六阶段6中，第三子时钟信号线CLK_3提供的第三时钟信号CLKC变为高电平，所以第一级移位寄存器单元10输出的移位信号CR<1>以及驱动信号OUT<1>变为高电平。例如，该驱动信号OUT<1>可以用于驱动显示面板中的第一行子像素单元中的感测晶体管，以实现外部补偿。
同时，在第六阶段6中，由于第三电容C3的耦合作用，第一节点Q<1>的电平被进一步拉高。
在第七阶段7中，由于第三电容C3的保持作用，第一节点Q<1>仍然保持高电平，所以第八晶体管M8以及第九晶体管M9保持导通。但由于第三子时钟信号线CLK_3提供的第三时钟信号CLKC变为低电平，所以第一级移位寄存器单元10输出的移位信号CR<1>以及驱动信号OUT<1>变为低电平。同时由于第三电容C3的耦合作用，第一节点Q<1>的电平也会下降。
在第八阶段8中，第五子时钟信号线CLK_5和第七子时钟信号线CLK_7提供高电平，栅极驱动电路20中的每一级移位寄存器单元10中的第十四晶体管M14被导通，从而可以对每一级移位寄存器单元10中的第一节点Q进行复位；栅极驱动电路20中的每一级移位寄存器单元10中的第一晶体管M1被导通，由于此时接收的第二输入信号STU2为低电平，所以可以对每一级移位寄存器单元10中的第四节点H进行复位，从而完成全局复位。
至此，第一帧的驱动时序结束。后续在第二帧、第三帧等更多阶段中对栅极驱动电路的驱动可以参考上述描述，这里不再赘述。
需要说明是，在上述对随机补偿的工作原理进行描述时，是以第一帧的消隐时段输出对应于显示面板的第一行子像素单元的驱动信号为例进行说明的，本公开对此不作限定。例如，当在某一帧的消隐时段中需要输出对应于显示面板的第n行子像素单元的驱动信号时，则需要在该帧的显示时段DS中将对应的第四节点H上拉至高电平，同时在该帧的消隐时段BL中，提供高电平的第一时钟信号CLKA以拉高第一节点Q的电平，然后在需要输出高电平的驱动信号时，提供高电平的第三时钟信号CLKC，n为大于零的整数。
另外，在本公开的实施例中，两个信号时序相同指的是位于高电平的时间同步，而并不要求两个信号的幅值相同。
本公开的一些实施例还提供一种显示装置1，如图12所示，该显示装置1包括本公开实施例提供的栅极驱动电路20以及多个呈阵列排布的子像素单元510。例如，该显示装置1还包括显示面板50，多个子像素单元510构成的像素阵列设置在显示面板50中。
栅极驱动电路20中的每一个移位寄存器单元10输出的驱动信号OUT分别提供至不同行的子像素单元510，例如，栅极驱动电路20通过栅线GL与子像素单元510电连接。栅极驱动电路20用于提供驱动信号OUT至像素阵列，例如该驱动信号OUT可以用于驱动子像素单元510中的扫描晶体管 和感测晶体管。
例如，该显示装置1还可以包括数据驱动电路30，该数据驱动电路30用于提供数据信号至像素阵列。例如，数据驱动电路30通过数据线DL与子像素单元510电连接。
需要说明的是，本实施例中的显示装置1可以为：液晶面板、液晶电视、显示器、OLED面板、OLED电视、电子纸显示装置、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开的实施例提供的显示装置1的技术效果可以参考上述实施例中关于栅极驱动电路20的相应描述，这里不再赘述。
本公开的实施例还提供一种驱动方法，可以用于驱动本公开的实施例提供的移位寄存器单元10，多个该移位寄存器单元10可以级联构建本公开一实施例提供的栅极驱动电路，该栅极驱动电路用于驱动显示面板显示至少一帧画面。
该驱动方法包括：第一输入电路110响应于第一输入信号STU1对第一节点Q的电平进行控制；输出电路120在第一节点Q的电平的控制下在输出端OP提供输出信号；第一控制电路130在第一节点Q的电平的控制下，对第二节点QB的电平进行控制；第一复位电路140在第二节点QB的电平的控制下，对第一节点Q以及输出端OP进行复位，例如输出端OP包括移位信号输出端CRT以及驱动信号输出端DST；第二输入电路150响应于选择控制信号OE对第三节点N的电平进行控制；传输电路160根据第三节点N的电平对第一节点Q的电平进行控制；存储电路170稳定第二节点QB的电平。
需要说明的是，关于本公开的实施例提供的驱动方法的详细描述和技术效果可以参考本公开的实施例中对于移位寄存器单元10和栅极驱动电路20的工作原理的描述，这里不再赘述。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以权利要求的保护范围为准。

Claims (19)

  1. 一种移位寄存器单元，包括第一输入电路、输出电路、第一控制电路、第一复位电路、第二输入电路、传输电路和存储电路；其中，
    所述第一输入电路被配置为响应于第一输入信号对第一节点的电平进行控制，
    所述输出电路被配置为在所述第一节点的电平的控制下在输出端提供输出信号，
    所述第一控制电路被配置为在所述第一节点的电平的控制下，对第二节点的电平进行控制，
    所述第一复位电路被配置为在所述第二节点的电平的控制下，对所述第一节点以及所述输出端进行复位，
    所述第二输入电路被配置为响应于选择控制信号对第三节点的电平进行控制，
    所述传输电路被配置为根据所述第三节点的电平对所述第一节点的电平进行控制，
    所述存储电路和所述第二节点电连接，且被配置为稳定所述第二节点的电平。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述第二输入电路包括选择输入电路和传输控制电路，
    所述选择输入电路被配置为响应于所述选择控制信号利用第二输入信号对第四节点的电平进行控制；
    所述传输控制电路和所述第三节点以及所述第四节点连接，且被配置为在所述第四节点的电平的控制下将第一时钟信号传输至所述第三节点。
  3. 根据权利要求2所述的移位寄存器单元，还包括第二复位电路，其中，
    所述第二复位电路被配置为在所述第二节点的电平的控制下对所述第三节点进行复位。
  4. 根据权利要求3所述的移位寄存器单元，其中，所述第二复位电路和所述第二节点以及所述第三节点连接。
  5. 根据权利要求2至4中任一项所述的移位寄存器单元，其中，所述存 储电路包括第一电容，所述选择输入电路包括第一晶体管，所述传输控制电路包括第二晶体管，所述传输电路包括第四晶体管；
    所述第一电容的第一极和所述第四节点连接，所述第一电容的第二极和所述第二节点连接；
    所述第一晶体管的栅极被配置为接收所述选择控制信号，所述第一晶体管的第一极被配置为接收所述第二输入信号，所述第一晶体管的第二极和所述第四节点连接；
    所述第二晶体管的栅极和所述第四节点连接，所述第二晶体管的第一极被配置为接收所述第一时钟信号，所述第二晶体管的第二极和所述第三节点连接；
    所述第四晶体管的栅极被配置为接收所述第一时钟信号，所述第四晶体管的第一极和所述第三节点连接，所述第四晶体管的第二极和所述第一节点连接。
  6. 根据权利要求3所述的移位寄存器单元，其中，所述存储电路包括第一电容，所述选择输入电路包括第一晶体管，所述传输控制电路包括第二晶体管，所述第二复位电路包括第三晶体管，所述传输电路包括第四晶体管；
    所述第一电容的第一极和所述第四节点连接，所述第一电容的第二极和所述第二节点连接；
    所述第一晶体管的栅极被配置为接收所述选择控制信号，所述第一晶体管的第一极被配置为接收所述第二输入信号，所述第一晶体管的第二极和所述第四节点连接；
    所述第二晶体管的栅极和所述第四节点连接，所述第二晶体管的第一极被配置为接收所述第一时钟信号，所述第二晶体管的第二极和所述第三节点连接；
    所述第三晶体管的栅极和所述第二节点连接，所述第三晶体管的第一极和所述第三节点连接，所述第三晶体管的第二极被配置为接收第一电压；
    所述第四晶体管的栅极和所述第三节点连接，所述第四晶体管的第一极被配置为接收所述第一时钟信号或第二电压，所述第四晶体管的第二极和所述第一节点连接。
  7. 根据权利要求3所述的移位寄存器单元，其中，所述存储电路包括第 二电容，所述选择输入电路包括第一晶体管和第一电容，所述传输控制电路包括第二晶体管，所述第二复位电路包括第三晶体管，所述传输电路包括第四晶体管；
    所述第二电容的第一极和所述第二节点连接，所述第二电容的第二极被配置为接收固定电平；
    所述第一晶体管的栅极被配置为接收所述选择控制信号，所述第一晶体管的第一极被配置为接收所述第二输入信号，所述第一晶体管的第二极和所述第四节点连接；
    所述第一电容的第一极和所述第四节点连接，所述第一电容的第二极和所述第三节点连接；
    所述第二晶体管的栅极和所述第四节点连接，所述第二晶体管的第一极被配置为接收所述第一时钟信号，所述第二晶体管的第二极和所述第三节点连接；
    所述第三晶体管的栅极和所述第二节点连接，所述第三晶体管的第一极和所述第三节点连接，所述第三晶体管的第二极被配置为接收第一电压；
    所述第四晶体管的栅极和所述第三节点连接，所述第四晶体管的第一极被配置为接收所述第一时钟信号或第二电压，所述第四晶体管的第二极和所述第一节点连接。
  8. 根据权利要求1至7中任一项所述的移位寄存器单元，其中，
    所述第一控制电路还被配置为在第二时钟信号的控制下，将第二电压传输至所述第二节点；
    所述输出电路还被配置为接收第三时钟信号，并在所述第一节点的电平的控制下将所述第三时钟信号作为所述输出信号提供至所述输出端；
    所述第二时钟信号和所述第三时钟信号均为占空比为三分之一的脉冲信号，且所述第三时钟信号和所述第二时钟信号在时序上间隔第一时间，所述第一时间等于所述脉冲信号的周期的三分之二。
  9. 根据权利要求8所述的移位寄存器单元，其中，所述第一输入电路包括第五晶体管，所述第一控制电路包括第六晶体管和第七晶体管，所述输出电路包括第八晶体管、第九晶体管和第三电容，所述输出端包括移位信号输出端和驱动信号输出端，所述移位信号输出端以及所述驱动信号输出端被配 置为输出所述输出信号；
    所述第五晶体管的栅极被配置为接收所述第一输入信号，所述第五晶体管的第一极被配置为接收所述第一输入信号或所述第二电压，所述第五晶体管的第二极和所述第一节点连接；
    所述第六晶体管的栅极被配置为接收所述第二时钟信号，所述第六晶体管的第一极被配置为接收所述第二电压，所述第六晶体管的第二极和所述第二节点连接；
    所述第七晶体管的栅极和所述第一节点连接，所述第七晶体管的第一极和所述第二节点连接，所述第七晶体管的第二极被配置为接收第一电压；
    所述第八晶体管的栅极和所述第一节点连接，所述第八晶体管的第一极被配置为接收所述第三时钟信号，所述第八晶体管的第二极和所述移位信号输出端连接；
    所述第九晶体管的栅极和所述第一节点连接，所述第九晶体管的第一极被配置为接收所述第三时钟信号，所述第九晶体管的第二极和所述驱动信号输出端连接；
    所述第三电容的第一极和所述第一节点连接，所述第三电容的第二极和所述驱动信号输出端连接。
  10. 根据权利要求2至7中任一项所述的移位寄存器单元，还包括第二控制电路，其中，
    所述第二控制电路被配置为在所述第一时钟信号以及所述第四节点的电平的控制下，对所述第二节点的电平进行控制。
  11. 根据权利要求10所述的移位寄存器单元，其中，所述第二控制电路包括第十晶体管和第十一晶体管，
    所述第十晶体管的栅极被配置为接收所述第一时钟信号，所述第十晶体管的第一极和所述第二节点连接，所述第十晶体管的第二极和所述第十一晶体管的第一极连接，
    所述第十一晶体管的栅极和所述第四节点连接，所述第十一晶体管的第二极被配置为接收第一电压。
  12. 根据权利要求1至11中任一项所述的移位寄存器单元，还包括第三控制电路，其中，
    所述第三控制电路被配置为响应于所述第一输入信号对所述第二节点的电平进行控制。
  13. 根据权利要求12所述的移位寄存器单元，其中，所述第三控制电路包括第十二晶体管，
    所述第十二晶体管的栅极被配置为接收所述第一输入信号，所述第十二晶体管的第一极和所述第二节点连接，所述第十二晶体管的第二极被配置为接收第一电压。
  14. 根据权利要求1至13中任一项所述的移位寄存器单元，还包括第三复位电路和第四复位电路，其中，
    所述第三复位电路被配置为响应于显示复位信号对所述第一节点进行复位，所述第四复位电路被配置为响应于全局复位信号对所述第一节点进行复位。
  15. 根据权利要求14所述的移位寄存器单元，其中，所述第三复位电路包括第十三晶体管，所述第四复位电路包括第十四晶体管；
    所述第十三晶体管的栅极被配置为接收所述显示复位信号，所述第十三晶体管的第一极和所述第一节点连接，所述第十三晶体管的第二极被配置为接收第一电压；
    所述第十四晶体管的栅极被配置为接收所述全局复位信号，所述第十四晶体管的第一极和所述第一节点连接，所述第十四晶体管的第二极被配置为接收所述第一电压。
  16. 一种栅极驱动电路，包括多个级联的如权利要求1-15任一所述的移位寄存器单元。
  17. 根据权利要求16所述的栅极驱动电路，还包括第一子时钟信号线、第二子时钟信号线和第三子时钟信号线；其中，
    第3n-2级移位寄存器单元和所述第一子时钟信号线连接以接收用于所述第3n-2级移位寄存器单元的第二时钟信号，所述第3n-2级移位寄存器单元和所述第三子时钟信号线连接以接收用于所述第3n-2级移位寄存器单元的第三时钟信号；
    第3n-1级移位寄存器单元和所述第二子时钟信号线连接以接收用于所述第3n-1级移位寄存器单元的第二时钟信号，所述第3n-1级移位寄存器单 元和所述第一子时钟信号线连接以接收用于所述第3n-1级移位寄存器单元的第三时钟信号；
    第3n级移位寄存器单元和所述第三子时钟信号线连接以接收用于所述第3n级移位寄存器单元的第二时钟信号，所述第3n级移位寄存器单元和所述第二子时钟信号线连接以接收用于所述第3n级移位寄存器单元的第三时钟信号；
    n为大于0的整数。
  18. 一种显示装置，包括如权利要求16或17所述的栅极驱动电路。
  19. 一种如权利要求1-15任一所述的移位寄存器单元的驱动方法，包括：
    所述第一输入电路响应于第一输入信号对第一节点的电平进行控制；所述输出电路在所述第一节点的电平的控制下在输出端提供输出信号；所述第一控制电路在所述第一节点的电平的控制下，对第二节点的电平进行控制；所述第一复位电路在所述第二节点的电平的控制下，对所述第一节点以及所述输出端进行复位；所述第二输入电路响应于选择控制信号对第三节点的电平进行控制；所述传输电路根据所述第三节点的电平对所述第一节点的电平进行控制；所述存储电路稳定所述第二节点的电平。
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