WO2020001012A1 - 移位寄存器单元、栅极驱动电路、显示装置及驱动方法 - Google Patents

移位寄存器单元、栅极驱动电路、显示装置及驱动方法 Download PDF

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Publication number
WO2020001012A1
WO2020001012A1 PCT/CN2019/072992 CN2019072992W WO2020001012A1 WO 2020001012 A1 WO2020001012 A1 WO 2020001012A1 CN 2019072992 W CN2019072992 W CN 2019072992W WO 2020001012 A1 WO2020001012 A1 WO 2020001012A1
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Prior art keywords
transistor
node
clock signal
signal
pole
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PCT/CN2019/072992
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English (en)
French (fr)
Inventor
冯雪欢
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/485,719 priority Critical patent/US11475825B2/en
Priority to KR1020207017997A priority patent/KR102473024B1/ko
Priority to JP2019547983A priority patent/JP7330892B2/ja
Priority to EP19748643.4A priority patent/EP3816983A4/en
Publication of WO2020001012A1 publication Critical patent/WO2020001012A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels

Definitions

  • Embodiments of the present disclosure relate to a shift register unit, a gate driving circuit, a display device, and a driving method.
  • the gate drive circuit is currently generally integrated in a GATE IC.
  • the area of the chip in the IC design is the main factor affecting the cost of the chip. How to effectively reduce the area of the chip is a technical developer's important consideration.
  • At least one embodiment of the present disclosure provides a shift register unit including a blanking input circuit, a display input circuit, an output circuit, and a coupling circuit.
  • the blanking input circuit is configured to input a blanking input signal to a control node and a blanking signal to a first node in a blanking period of one frame;
  • the display input circuit is configured to respond to a first clock signal A display signal is input to the first node during a display period of one frame;
  • the output circuit is configured to output a composite output signal to an output terminal under the control of the level of the first node;
  • the coupling circuit Is electrically connected to the control node, and is configured to perform coupling control on the level of the control node in response to the blanking signal.
  • the coupling circuit includes a first capacitor, and a first pole of the first capacitor and a third clock signal terminal are connected to receive a third clock signal as the For a blanking signal, the second pole of the first capacitor is connected to the control node.
  • the coupling circuit includes a first capacitor and a first transistor.
  • the gate of the first transistor is connected to the control node, and the first pole of the first transistor and a third clock signal terminal are connected to receive a third clock signal as the blanking signal.
  • a second pole is connected to the first pole of the first capacitor, and a second pole of the first capacitor is connected to the control node.
  • the blanking input circuit includes a charging sub-circuit configured to input the blanking input signal to the control node in response to a second clock signal.
  • a storage sub-circuit configured to store the blanking input signal input by the charging sub-circuit; an isolation sub-circuit configured to control the blanking under the control of a level of the control node and a third clock signal
  • a hidden signal is input to the first node.
  • the charging sub-circuit includes a second transistor, and a gate of the second transistor is connected to a second clock signal terminal to receive the second clock signal, A first pole of the second transistor and a blanking input signal terminal are connected to receive the blanking input signal, a second pole of the second transistor is connected to the control node, and the storage subcircuit includes a second capacitor.
  • a first pole of the second capacitor is connected to the control node, a second pole of the second capacitor is connected to a first voltage terminal to receive a first voltage, and the isolation sub-circuit includes a third transistor and a fourth A transistor, a gate of the third transistor is connected to the control node, a first pole of the third transistor is connected to a third clock signal terminal to receive the third clock signal as the blanking signal, the The second pole of the third transistor is connected to the first pole of the fourth transistor, the gate of the fourth transistor is connected to the third clock signal terminal to receive the third clock signal, and the fourth transistor And a second electrode connected to the first node.
  • the display input circuit includes a fifth transistor; a gate of the fifth transistor is connected to a first clock signal terminal to receive the first clock signal, A first pole of the fifth transistor is connected to a display input signal terminal to receive the display signal, and a second pole of the fifth transistor is connected to the first node.
  • the output terminal includes a shift signal output terminal and a pixel signal output terminal, and the shift signal output terminal and the pixel signal output terminal output the composite signal.
  • An output signal, the output circuit includes a sixth transistor, a seventh transistor, and a third capacitor; a gate of the sixth transistor is connected to the first node, and a first pole of the sixth transistor and a fourth clock signal Terminal connected to receive a fourth clock signal as the composite output signal, the second pole of the sixth transistor is connected to the shift signal output terminal; the gate of the seventh transistor is connected to the first node, A first pole of the seventh transistor is connected to the fourth clock signal terminal to receive the fourth clock signal as the composite output signal, and a second pole of the seventh transistor is connected to the pixel signal output terminal.
  • a first pole of the third capacitor is connected to the first node, and a second pole of the third capacitor is connected to a second pole of the sixth transistor.
  • the shift register unit provided by an embodiment of the present disclosure further includes a noise reduction circuit and a control circuit.
  • the control circuit is configured to control the level of the second node under the control of the level of the first node; the noise reduction circuit is configured to be controlled under the level of the second node , Performing noise reduction on the first node, the shift signal output terminal, and the pixel signal output terminal.
  • the control circuit includes an eighth transistor, a ninth transistor, and a tenth transistor; a gate of the eighth transistor is connected to a first electrode and is configured to Connected to a seventh voltage terminal to receive a seventh voltage, the second electrode of the eighth transistor is connected to the second node; the gate of the ninth transistor is connected to the first electrode and configured to be connected to the eighth voltage Terminal connected to receive the eighth voltage, the second pole of the ninth transistor is connected to the second node; the gate of the tenth transistor is connected to the first node, and the first pole of the tenth transistor Connected to the second node, the second pole of the tenth transistor and a fourth voltage terminal are connected to receive a fourth voltage.
  • the noise reduction circuit includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor; a gate of the eleventh transistor and the first transistor A two-node connection, a first pole of the eleventh transistor is connected to the first node, a second pole of the eleventh transistor is connected to a third voltage terminal to receive a third voltage, and the twelfth transistor
  • the gate of is connected to the second node, the first pole of the twelfth transistor is connected to the shift signal output terminal, and the second pole of the twelfth transistor is connected to a fifth voltage terminal to receive the first node.
  • Five voltages; the gate of the thirteenth transistor is connected to the second node, the first pole of the thirteenth transistor is connected to the pixel signal output terminal, and the second pole of the thirteenth transistor is The sixth voltage terminal is connected to receive a sixth voltage.
  • the shift register unit provided by an embodiment of the present disclosure further includes a display reset circuit configured to reset the first node in response to a display reset signal.
  • the display reset circuit includes a fourteenth transistor; a gate of the fourteenth transistor is connected to a display reset signal terminal to receive the display reset signal, A first pole of the fourteenth transistor is connected to the first node, and a second pole of the fourteenth transistor is connected to a second voltage terminal to receive a second voltage.
  • the shift register unit provided by an embodiment of the present disclosure further includes a global reset circuit configured to reset the control node in response to a global reset signal.
  • the global reset circuit includes a fifteenth transistor; a gate of the fifteenth transistor is connected to a global reset signal terminal to receive the global reset signal, A first pole of the fifteenth transistor is connected to the control node, and a second pole of the fifteenth transistor is connected to a first voltage terminal to receive a first voltage.
  • At least one embodiment of the present disclosure further provides a gate driving circuit, which includes a plurality of cascaded shift register units provided by any of the embodiments of the present disclosure.
  • the gate driving circuit provided by an embodiment of the present disclosure further includes a first sub-clock signal line, a second sub-clock signal line, a third sub-clock signal line, and a fourth sub-clock signal line.
  • the 2n-1 stage shift register unit is connected to the first sub-clock signal line to receive a first clock signal, and the 2n-1 stage shift register unit is connected to the third sub-clock signal line to receive a fourth clock Signals;
  • a 2n-stage shift register unit is connected to the second sub-clock signal line to receive a first clock signal, and a 2n-stage shift register unit is connected to the fourth sub-clock signal line to receive a fourth clock signal;
  • n is an integer greater than 0.
  • the gate driving circuit provided by an embodiment of the present disclosure further includes a fifth sub-clock signal line, a sixth sub-clock signal line, and a seventh sub-clock signal line.
  • the 2n-1 stage shift register unit is connected to the fifth sub-clock signal line to receive a second clock signal, and the 2n-1 stage shift register unit is connected to the sixth sub-clock signal line to receive a third clock Signal;
  • the 2n-stage shift register unit is connected to the sixth sub-clock signal line to receive a second clock signal, and the 2n-stage shift register unit is connected to the fifth sub-clock signal line to receive a third clock signal;
  • Each stage of the shift register unit is connected to the seventh sub-clock signal line to receive a global reset signal; n is an integer greater than 0.
  • At least one embodiment of the present disclosure also provides a display device including any gate driving circuit provided by the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure also provides a method for driving a shift register unit, including:
  • the coupling circuit performs coupling control on the level of the control node in response to the blanking signal, and the blanking input circuit inputs the blanking signal to the first Node, the output circuit outputs the composite output signal under the control of the level of the first node.
  • FIG. 1 is a schematic diagram of a shift register unit provided by some embodiments of the present disclosure
  • FIG. 2 is a schematic diagram of a blanking input circuit provided by some embodiments of the present disclosure.
  • FIG. 3 is a schematic diagram of another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 4 is a circuit diagram of a shift register unit provided by some embodiments of the present disclosure.
  • FIG. 5 is a circuit diagram of another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 6 is a circuit diagram of still another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 7 is a circuit diagram of still another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 8 is a circuit diagram of still another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 9 is a circuit diagram of still another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 10 is a schematic diagram of a gate driving circuit provided by some embodiments of the present disclosure.
  • FIG. 11 is a signal timing diagram corresponding to the operation of the gate driving circuit shown in FIG. 10 provided by some embodiments of the present disclosure.
  • FIG. 12 is a signal simulation diagram of the shift register unit shown in FIG. 4 when the first capacitor is not included; FIG.
  • FIG. 13 is a signal simulation diagram of the shift register unit shown in FIG. 4;
  • FIG. 14 is a signal simulation diagram of the shift register unit shown in FIG. 6;
  • FIG. 15 is a schematic diagram of a display device provided by some embodiments of the present disclosure.
  • pulse-up means charging a node or an electrode of a transistor so that the absolute level of the node or the electrode is The value rises to achieve the operation of the corresponding transistor (for example, turn on);
  • pulse-down means to discharge a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode is reduced to achieve the corresponding Operation of the transistor (e.g. off).
  • pulse-up means discharging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode is reduced, thereby realizing the corresponding transistor.
  • Operation (such as turning on); “pull-down” means charging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode increases, thereby realizing the operation of the corresponding transistor (such as turning off) .
  • pulse-up and pulse-down will also be adjusted accordingly according to the specific type of transistor used, as long as the control of the transistor can be achieved to achieve the corresponding switching function.
  • the gate drive circuit for OLED is usually composed of three sub-circuits, that is, a detection circuit, a display circuit, and a connection circuit (or gate circuit) that outputs a composite pulse of both.
  • a detection circuit a detection circuit
  • a display circuit a display circuit
  • a connection circuit or gate circuit
  • a display period Provides a scan driving signal for a scanning transistor, and a sensing driving signal for a sensing transistor in a blanking period (BL) of one frame.
  • a threshold voltage drift (eg, a negative drift) of a transistor may exist, which may cause a leakage of a control node. For example, during a blanking period of one frame, when a leakage occurs at the control node, the first node is insufficiently charged, which may cause the shift register unit to fail to normally output a sensing driving signal for a sensing transistor.
  • the shift register unit includes a blanking input circuit, a display input circuit, an output circuit, and a coupling circuit.
  • the blanking input circuit is configured to input a blanking input signal to the control node and input the blanking signal to the first node in a blanking period of one frame;
  • the display input circuit is configured to respond to the first clock signal in one frame.
  • the display signal is input to the first node during the display period;
  • the output circuit is configured to output the composite output signal to the output terminal under the control of the level of the first node;
  • the coupling circuit is electrically connected to the control node and is configured to respond to The blanking signal couples and controls the level of the control node.
  • Embodiments of the present disclosure also provide a gate driving circuit, a display device, and a driving method corresponding to the above-mentioned shift register unit.
  • the level of the control node can be coupled and controlled, so that the first node is more fully charged in the blanking period of one frame, so that Avoid output exceptions.
  • the definition of “one frame”, “each frame”, or “a certain frame” includes a display period and a blanking period performed sequentially, for example, in a display period
  • the gate driving circuit outputs a display output signal.
  • the display output signal can drive the display panel to complete a complete scanning display of an image from the first line to the last line.
  • the gate driving circuit outputs a blanking output signal.
  • the blanking output signal can be used to drive a sensing transistor in a row of sub-pixel units in the display panel to complete external compensation of the row of sub-pixel units.
  • the shift register unit 10 includes a blanking input circuit 100, a display input circuit 200, an output circuit 300, and a coupling circuit 400.
  • the blanking input circuit 100, the display input circuit 200, and the output circuit 300 are connected through a first node Q.
  • the blanking input circuit 100 is configured to input a blanking input signal to the control node H and a blanking signal to the first node Q during a blanking period of one frame.
  • the blanking input circuit 100 may be connected to the blanking input signal terminal STU1 and the second clock signal terminal CLKB, so that the blanking may be performed under the control of the second clock signal input to the second clock signal terminal CLKB.
  • the blanking input signal input from the input signal terminal STU1 is input to the control node H.
  • the blanking input circuit 100 may also be connected to the third clock signal terminal CLKC, so that the third clock signal input from the third clock signal terminal CLKC is input as a blanking signal to the first node Q in a blanking period of a frame, so that The first node Q is pulled up to a high level.
  • the blanking input circuit 100 may receive a blanking input signal in a blanking period of one frame and store the blanking input signal, and output a blanking signal to the first node Q according to the blanking input signal in the blanking period of the next frame.
  • the first node Q is pulled up to a high level.
  • the blanking input signal terminal STU1 of the other stages of the shift register unit can be shifted from the previous stage.
  • the output terminal OUTPUT of the bit register unit is electrically connected.
  • the blanking input signal terminal STU1 may be connected to the shift signal output terminal CR.
  • the display input circuit 200 is configured to input a display signal to the first node Q in response to the first clock signal during a display period of one frame.
  • the display input circuit 200 may be connected to the first clock signal terminal CLKA to receive the first clock signal, and the display input circuit 200 may also be connected to the display input signal terminal STU2 to receive the display signal.
  • the display input circuit 200 may input a display signal to the first node Q under the control of the first clock signal during a display period of one frame, thereby pulling the first node Q to a high level.
  • the display input signal terminal STU2 of the other stages of the shift register unit can be shifted from the previous stage.
  • the output terminal OUTPUT of the register unit is electrically connected.
  • the display input signal terminal STU2 may be connected to the shift signal output terminal CR.
  • the display input circuit 200 may also adopt other configurations, as long as the corresponding functions can be implemented, which is not limited in the embodiments of the present disclosure.
  • the output circuit 300 is configured to output a composite output signal to an output terminal OUTPUT under the control of the level of the first node Q.
  • the output circuit 300 may be connected to the fourth clock signal terminal CLKD to receive the fourth clock signal and serve as a composite output signal.
  • the composite output signal may include a display output signal and a blanking output signal.
  • the output circuit 300 outputs the display output signal to the output terminal OUTPUT under the control of the level of the first node Q.
  • the output terminal OUTPUT may include a shift signal output terminal CR and a pixel signal output terminal OUT.
  • the display output signal output from the shift signal output terminal CR may be used for scanning shift of the upper and lower shift register units, and The display output signal output from the pixel signal output terminal OUT can be used to drive a sub-pixel unit in the display panel for scanning display.
  • the output circuit 300 outputs a blanking output signal to the output terminal OUTPUT under the control of the level of the first node Q.
  • the blanking output signal can be used to drive the sensing transistor.
  • the coupling circuit 400 is electrically connected to the control node H, and is configured to perform coupling control on the level of the control node H in response to the blanking signal, for example, to couple and pull up the level of the control node H.
  • the coupling circuit 400 may be connected to the third clock signal terminal CLKC, and use the third clock signal input from the third clock signal terminal CLKC as a blanking signal.
  • the blanking input circuit 100 charges the control node H in the blanking period of one frame, so that the potential of the control node H is pulled up to a high level; then the coupling circuit 400 may respond to the blanking period in the blanking period of the next frame.
  • the hidden signal couples and pulls up the level of the control node H, which can avoid leakage of the control node H, so that the first node Q is fully charged during the blanking period of the frame to avoid output abnormality.
  • the control node H when the control node H is at a high level, the control node H can be further coupled and pulled up, so that the The first node Q is more fully charged to avoid output anomalies.
  • the blanking input circuit 100 includes a charging sub-circuit 110, a storage sub-circuit 120, and an isolation sub-circuit 130.
  • the charging sub-circuit 110 is configured to input a blanking input signal to the control node H in response to a second clock signal.
  • the charging sub-circuit 110 is connected to the blanking input signal terminal STU1 to receive the blanking input signal, and the charging sub-circuit 110 is connected to the second clock signal terminal CLKB to receive the second clock signal.
  • the charging sub-circuit 110 may be turned on under the control of the second clock signal so that the blanking input signal may be input to the control node H.
  • the storage sub-circuit 120 is configured to store a blanking input signal input from the charging sub-circuit 110. For example, during a blanking period of a frame, the control node H is charged to a high level by the input blanking input signal, and the storage sub-circuit 120 may store the blanking input signal, so that the high level of the control node H can be maintained at all times. The blanking period to the next frame.
  • the isolation sub-circuit 130 is configured to input a blanking signal to the first node Q under the control of the level of the control node H and the third clock signal.
  • the isolation sub-circuit 130 is connected to the third clock signal terminal CLKC to receive the third clock signal, and the third clock signal is also used as a blanking signal.
  • the isolation sub-circuit 130 is turned on under the control of the level of the control node H and the third clock signal, so that the blanking signal can be input to the first node Q.
  • the isolation sub-circuit 130 is disposed between the first node Q and the control node H, and is configured to prevent the interaction between the first node Q and the control node H. For example, when it is not necessary to output a blanking signal, the isolation sub-circuit 130 may disconnect the connection between the first node Q and the control node H.
  • the level of the first node Q can be controlled by the blanking input circuit 100 and the display input circuit 200 respectively at different periods, thereby realizing the blanking input circuit 100 and the display input.
  • the circuit 200 shares the same output circuit 300 to realize the output of a composite output signal.
  • the shift register unit 10 may further include a control circuit 500 configured to control the level of the second node QB under the control of the level of the first node Q Take control.
  • the control circuit 500 is connected to the seventh voltage terminal CLKM and the fourth voltage terminal VSS4.
  • the fourth voltage terminal VSS4 may be configured to provide a DC low-level signal, for example, the following embodiments are the same, and details are not described herein again.
  • the control circuit 500 may pull the second node QB to a low level through the fourth voltage terminal VSS4.
  • the control circuit 500 may use a seventh voltage (for example, a high level) input from the seventh voltage terminal CLKM to charge the second node QB to charge the second node QB is pulled high.
  • control circuit 500 may also be connected to the eighth voltage terminal CLKN to receive the eighth voltage (for example, high level).
  • the seventh voltage terminal CLKM and the eighth voltage terminal CLKN may be configured to alternate When inputting a high level, that is, when the seventh voltage terminal CLKM inputs a high level, the eighth voltage terminal CLKN inputs a low level, and when the seventh voltage terminal CLKM inputs a low level, the eighth voltage terminal CLKN inputs a high level.
  • the shift register unit 10 may further include a noise reduction circuit 600 configured to control the first node Q and the first node Q and Q under the control of the level of the second node QB.
  • Output OUTPUT for noise reduction for example, in a case where the output terminal OUTPUT includes a shift signal output terminal CR and a pixel signal output terminal OUT, the noise reduction circuit 600 may perform noise reduction on the shift signal output terminal CR and the pixel signal output terminal OUT at the same time.
  • the noise reduction circuit 600 is connected to the third voltage terminal VSS3, the fifth voltage terminal VSS5, and the sixth voltage terminal VSS6.
  • the noise reduction circuit 600 When the noise reduction circuit 600 is turned on under the control of the level of the second node QB, it can pass the third voltage The terminal VSS3, the fifth voltage terminal VSS5, and the sixth voltage terminal VSS6 respectively pull down the first node Q, the shift signal output terminal CR, and the pixel signal output terminal OUT, thereby achieving noise reduction.
  • the third voltage terminal VSS3, the fifth voltage terminal VSS5, and the sixth voltage terminal VSS6 in the embodiments of the present disclosure may be configured to provide a DC low-level signal, for example, the following embodiments are the same, and are not More details.
  • the shift register unit 10 may further include a display reset circuit 700 configured to reset the first node Q in response to a display reset signal.
  • the display reset circuit 700 may be connected to the display reset signal terminal STD to receive a display reset signal, and at the same time connected to the second voltage terminal VSS2 to receive a low-level second voltage.
  • the display reset circuit 700 may be turned on in response to a display reset signal, so that the first node Q may be reset through the second voltage terminal VSS2.
  • the display reset signal terminal STD of the other stages of the shift register unit can be shifted with the next stage.
  • An output terminal OUTPUT (for example, a shift signal output terminal CR) of the register unit is electrically connected.
  • the second voltage terminal VSS2 in the embodiment of the present disclosure may be configured to provide a DC low-level signal, for example, the following embodiments are the same, and details are not described herein again.
  • the shift register unit 10 may further include a global reset circuit 800 configured to reset the control node H in response to a global reset signal.
  • the global reset circuit 800 is connected to the global reset signal terminal TRST to receive a global reset signal, and at the same time connected to the first voltage terminal VSS1 to receive a low-level first level.
  • the global reset circuit 800 in each stage of the shift register unit 10 is turned on in response to the global reset signal before a display period of one frame.
  • the control node H is reset through the first voltage terminal VSS1, thereby achieving a global reset of the shift register units 10 at all levels.
  • the first voltage terminal VSS1 in the embodiment of the present disclosure may be configured to provide a DC low-level signal, for example, the following embodiments are the same, and are not described again.
  • the first voltage terminal VSS1, the second voltage terminal VSS2, the third voltage terminal VSS3, the fourth voltage terminal VSS4, the fifth voltage terminal VSS5, and the sixth voltage terminal VSS6 can be the same, that is, the above six voltage terminals can be connected to the same signal line to receive the same low-level signal; for example, two, three or more of the above six voltage terminals Can be connected to the same signal line to receive the same low-level signal; for example, the above six voltage terminals can be connected to different signal lines to receive different low-level signals respectively.
  • the embodiments of the present disclosure do not limit the arrangement of the first voltage terminal VSS1, the second voltage terminal VSS2, the third voltage terminal VSS3, the fourth voltage terminal VSS4, the fifth voltage terminal VSS5, and the sixth voltage terminal VSS6.
  • the shift register unit 10 shown in FIG. 3 may be implemented as the circuit structure shown in FIG. 4.
  • the shift register unit 10 includes second to fifteenth transistors M2 to M15, a first capacitor C1, a second capacitor C2, and a third capacitor C3.
  • the output terminal OUTPUT includes a shift signal output terminal CR and a pixel signal output terminal OUT. Both the shift signal output terminal CR and the pixel signal output terminal OUT can output a composite output signal.
  • the transistors shown in FIG. 4 are all described using N-type transistors as an example.
  • the charging sub-circuit 110 in the blanking input circuit 100 may be implemented as a second transistor M2.
  • the gate of the second transistor M2 and the second clock signal terminal CLKB are connected to receive the second clock signal.
  • the second transistor The first pole of M2 is connected to the blanking input signal terminal STU1 to receive the blanking input signal, and the second pole of the second transistor M2 is connected to the control node H.
  • the second clock signal is a high-level on signal
  • the second transistor M2 is turned on under the control of the second clock signal, so that the blanking input signal can be input to the control node H to charge it.
  • the storage sub-circuit 120 in the blanking input circuit 100 may be implemented as a second capacitor C2, a first pole of the second capacitor C2 is connected to the control node H, and a second pole of the second capacitor C2 is connected to the first capacitor C2.
  • the voltage terminal VSS1 is connected to receive a first voltage.
  • the second pole of the second capacitor C2 can be connected to other voltage terminals in addition to the first voltage terminal VSS1, for example, the second pole of the second capacitor C2 is grounded.
  • the embodiments of the present disclosure are not limited thereto.
  • the isolation sub-circuit 130 in the blanking input circuit 100 may be implemented as a third transistor M3 and a fourth transistor M4.
  • the gate of the third transistor M3 is connected to the control node H, and the first of the third transistor M3 is
  • the third clock signal terminal CLKC are connected to receive the third clock signal and serve as a blanking signal.
  • the second electrode of the third transistor M3 and the first electrode of the fourth transistor M4 are connected, and the gate of the fourth transistor M4 and the third transistor M4 are connected.
  • the clock signal terminal CLKC is connected to receive the third clock signal, and the second pole of the fourth transistor M4 is connected to the first node Q.
  • the third transistor M3 is turned on under the control of the control node H.
  • the fourth transistor M4 is turned on under the control of the third clock signal. Therefore, the third clock signal is used as a blanking signal to charge the first node Q through the third transistor M3 and the fourth transistor M4.
  • the display input circuit 200 may be implemented as a fifth transistor M5.
  • the gate of the fifth transistor M5 is connected to the first clock signal terminal CLKA to receive the first clock signal.
  • the input signal terminal STU2 is connected to receive a display signal, and the second pole of the fifth transistor M5 is connected to the first node Q.
  • the fifth transistor M5 is turned on under the control of the first clock signal, thereby charging the first node Q by using the display signal.
  • the output circuit 300 may be implemented to include a sixth transistor M6, a seventh transistor M7, and a third capacitor C3.
  • the gate of the sixth transistor M6 is connected to the first node Q, the first pole of the sixth transistor M6 and the fourth clock signal terminal CLKD are connected to receive the fourth clock signal as a composite output signal, and the second pole of the sixth transistor M6 and The shift signal output terminal CR is connected; the gate of the seventh transistor M7 is connected to the first node Q, and the first pole of the seventh transistor M7 is connected to the fourth clock signal terminal CLKD to receive the fourth clock signal as a composite output signal.
  • the second pole of the seventh transistor M7 is connected to the pixel signal output terminal OUT; the first pole of the third capacitor C3 is connected to the first node Q, and the second pole of the third capacitor C3 is connected to the second pole of the sixth transistor M6.
  • the sixth transistor M6 and the seventh transistor M7 are turned on, so that the fourth clock signal can be output as a composite output signal to the shift signal output terminal CR and the pixel signal output terminal. OUT.
  • the control circuit 500 may be implemented to include an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10.
  • the gate of the eighth transistor M8 is connected to the first pole and is configured to be connected to the seventh voltage terminal CLKM to receive the seventh voltage, and the second pole of the eighth transistor M8 is connected to the second node QB; the gate of the ninth transistor M9
  • the pole is connected to the first pole and is configured to be connected to the eighth voltage terminal CLKN to receive the eighth voltage.
  • the second pole of the ninth transistor M9 is connected to the second node QB; the gate of the tenth transistor M10 and the first node Q Connected, the first pole of the tenth transistor M10 and the second node QB are connected, and the second pole of the tenth transistor M10 and the fourth voltage terminal VSS4 are connected to receive the fourth voltage.
  • the seventh voltage terminal CLKM and the eighth voltage terminal CLKN may be configured to alternately input a high level, that is, when the seventh voltage terminal CLKM inputs a high level, the eighth voltage terminal CLKN inputs a low level, and the seventh voltage terminal CLKM
  • the eighth voltage terminal CLKN inputs a high level, that is, only one of the eighth transistor M8 and the ninth transistor M9 is in an on state, so that performance drift caused by long-term conduction of the transistor can be avoided.
  • the eighth transistor M8 or the ninth transistor M9 is turned on, the seventh or eighth voltage can charge the second node QB, thereby pulling the second node QB to a high level.
  • the tenth transistor M10 When the potential of the first node Q is at a high level, the tenth transistor M10 is turned on.
  • the tenth transistor M10 and the eighth transistor M8 (or the ninth transistor M9) may be configured as (Such as size ratio, threshold voltage, etc.) When both M10 and M8 (M9) are on, the level of the second node QB can be pulled down to a low level, which can make the eleventh transistor M11, the first The twelfth transistor M12 and the thirteenth transistor M13 remain off.
  • the noise reduction circuit 600 may be implemented to include an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13.
  • the gate of the eleventh transistor M11 is connected to the second node QB, the first pole of the eleventh transistor M11 is connected to the first node Q, and the second pole of the eleventh transistor M11 is connected to the third voltage terminal VSS3 to receive the first Three voltages;
  • the gate of the twelfth transistor M12 is connected to the second node QB, the first electrode of the twelfth transistor M12 is connected to the shift signal output terminal CR, and the second electrode of the twelfth transistor M12 is connected to the fifth voltage terminal VSS5 is connected to receive the fifth voltage;
  • the gate of the thirteenth transistor M13 is connected to the second node QB, the first pole of the thirteenth transistor M13 is connected to the pixel signal output terminal OUT, and the second pole of the thirteenth transistor M13 is connected to
  • the sixth voltage terminal VSS6 is connected
  • the eleventh transistor M11, the twelfth transistor M12, and the thirteenth transistor M13 are turned on, so that the third voltage, the fifth voltage, and the sixth voltage can be used to respectively The first node Q, the shift signal output terminal CR, and the pixel signal output terminal OUT are pulled down to reduce noise.
  • the display reset circuit 700 may be implemented as a fourteenth transistor M14.
  • the gate of the fourteenth transistor M14 is connected to the display reset signal terminal STD to receive the display reset signal.
  • the first pole of the fourteenth transistor M14 is connected to the first node Q, and the second pole of the fourteenth transistor M14 and the second voltage are connected.
  • the terminal VSS2 is connected to receive the second voltage. For example, when the display reset signal is high, the fourteenth transistor M14 is turned on, so that the first node Q can be reset by using the second voltage terminal VSS2.
  • the global reset circuit 800 may be implemented as a fifteenth transistor M15.
  • the gate of the fifteenth transistor M15 is connected to the global reset signal terminal TRST to receive the global reset signal.
  • the first pole of the fifteenth transistor M15 is connected to the control node H.
  • the second pole of the fifteenth transistor M15 is connected to the first voltage terminal.
  • VSS1 is connected to receive the first voltage. For example, when the global reset signal is high, the fifteenth transistor M15 is turned on, so that the control node H can be reset by using the first voltage terminal VSS1.
  • the coupling circuit 400 may be implemented as a first capacitor C1.
  • the first pole of the first capacitor C1 and the third clock signal terminal CLKC are electrically connected to receive the third clock signal as a blanking signal.
  • the second pole of the first capacitor C1 is connected to the control node H.
  • the third transistor M3 is turned on, and at the same time when the third clock signal is at a high level, the fourth transistor M4 is turned on, so that the third clock signal at a high level passes as a blanking signal.
  • the third transistor M3 and the fourth transistor M4 are input to the first node Q to charge the first node Q.
  • the third clock signal when the third clock signal is at a high level, the high level can be further coupled and pulled up to the control node H through the first capacitor C1, so that the third transistor M3 is turned on more fully, and the blanking signal is applied to the first node. Q is more fully charged to avoid abnormal output.
  • the first pole of the first capacitor C1 may also be connected to the tenth voltage terminal VDD to receive the tenth voltage, for example, the tenth voltage is a DC high level. It should be noted that, for the same parts of the shift register unit shown in FIG. 5 and the shift register unit shown in FIG. 4, reference may be made to the foregoing description, and details are not described herein again.
  • the coupling circuit 400 may be implemented to include a first transistor M1 and a first capacitor C1.
  • the gate of the first transistor M1 is connected to the control node H
  • the first pole of the first transistor M1 and the third clock signal terminal CLKC are connected to receive the third clock signal as a blanking signal
  • the second pole of the first transistor M1 is connected to the third node.
  • a first pole of a capacitor C1 is connected, and a second pole of the first capacitor C1 is connected to the control node H.
  • the first transistor M1 is turned on, so that the third clock signal provided by the third clock signal terminal CLKC can be applied to the first pole of the first capacitor C1.
  • the high level can be further coupled and pulled up to the control node H through the first capacitor C1, so that the third transistor M3 is more fully turned on, and the blanking signal affects the first node Q. Charge more fully to avoid abnormal output.
  • the shift register unit 10 may further include a twentieth transistor M20 compared to the shift register unit 10 shown in FIG. 6.
  • the gate of the twentieth transistor M20 is connected to the global reset signal terminal TRST to receive the global reset signal
  • the first pole of the twentieth transistor M20 is connected to the first node Q
  • the second pole of the twentieth transistor M20 is connected to the first
  • the voltage terminal VSS1 is connected to receive a first voltage.
  • the fifteenth transistor M15 and the twentieth The transistor M20 is turned on in response to the global reset signal, and the control node H and the first node Q are simultaneously reset through the first voltage terminal VSS1, thereby implementing a global reset of the shift register units 10 at all levels.
  • the second pole of the twentieth transistor M20 is connected to the first voltage terminal VSS1.
  • Embodiments of the present disclosure include, but are not limited to, for example, the second pole of the twentieth transistor M20 may also be It is connected to any one of the second voltage terminal VSS2, the third voltage terminal VSS3, the fourth voltage terminal VSS4, the fifth voltage terminal VSS5, and the sixth voltage terminal VSS6 to receive a DC low-level signal.
  • FIGS. 4 and 6 are further described below with reference to the signal simulation diagrams shown in FIGS. 12, 13, and 14.
  • FIG. 12 shows the shift register unit 10 shown in FIG. 4 without the first capacitor C1.
  • FIG. 13 is a signal simulation diagram of the shift register unit 10 (the coupling circuit 400 includes the first capacitor C1) shown in FIG. 4, and
  • FIG. 14 is a signal simulation diagram of the case where the coupling circuit 400 is not provided.
  • a signal simulation diagram of the shift register unit 10 (the coupling circuit 400 includes a first capacitor C1 and a first transistor M1) shown in FIG. 6.
  • the coupling circuit 400 it can be seen from FIGS. 13 and 14 that when the control node H is at a high level and the third clock signal provided by the third clock signal terminal CLKC is at a high level, the The level is further coupled and pulled up, so that the charging of the first node Q is more sufficient (that is, the potential of the first node Q is higher), so that the output abnormality can be avoided.
  • the coupling circuit 400 includes only the first capacitor C1 and does not include the first transistor M1
  • the control node H becomes a low level and the third clock signal terminal CLKC provides
  • the clock signal is at a high level
  • the high level is coupled to the control node H through the first capacitor C1 (as shown by the dashed ellipse in FIG. 13), thereby introducing noise on the control node H.
  • the coupling circuit 400 includes the first capacitor C1 and the first transistor M1
  • the first transistor M1 when the control node H becomes a low level, the first transistor M1 is turned off, so even at this time, the third clock signal
  • the third clock signal provided by terminal CLKC is high level, and this high level cannot be coupled to the control node H through the first capacitor C1 (refer to the shift register unit shown in FIG. 6), that is, it will not be at the control node. Noise is introduced on H.
  • some embodiments of the present disclosure further provide a shift register unit 10.
  • the shift register unit 10 shown in FIG. 8 has an output circuit.
  • 300 may further include a sixteenth transistor M16, and accordingly, the noise reduction circuit 600 may further include a seventeenth transistor M17.
  • the gate of the sixteenth transistor M16 is connected to the first node Q, the first pole of the sixteenth transistor M16 and the fifth clock signal terminal CLKE are connected to receive the fifth clock signal, and the sixteenth transistor M16
  • the second electrode is connected to another pixel signal output terminal OUT2. For example, when the potential of the first node Q is at a high level, the sixteenth transistor M16 is turned on, thereby outputting the fifth clock signal to the pixel signal output terminal OUT2.
  • the fifth clock signal input at the fifth clock signal terminal CLKE may be configured to be the same as the fourth clock signal input at the fourth clock signal terminal CLKD; for another example, in other embodiments, the fifth The clock signal may be different from the fourth clock signal, so that the pixel signal output terminals OUT and OUT2 can respectively output different signals to improve the driving ability.
  • the gate of the seventeenth transistor M17 is connected to the second node QB, the first pole of the seventeenth transistor M17 is connected to the pixel signal output terminal OUT2, and the second pole of the seventeenth transistor M17 is connected to the sixth node.
  • the voltage terminal VSS6 is connected.
  • the seventeenth transistor M17 is turned on, so that the sixth voltage terminal VSS6 can be used to reduce noise on the pixel signal output terminal OUT2.
  • the second pole of the seventeenth transistor M17 can also be configured to be connected to other signal terminals, as long as the pixel signal output terminal OUT2 can be pulled down to reduce noise, which is not limited in the embodiments of the present disclosure.
  • the potential at the control node H may be maintained by using the second capacitor C2, and the potential at the first node Q may be maintained by using the third capacitor C3.
  • the second capacitor C2 and / or the third capacitor C3 may be a capacitive device manufactured by a process, for example, a capacitive device is realized by manufacturing a special capacitor electrode, and each electrode of the capacitor may pass through a metal layer or a semiconductor layer (for example, doped polysilicon). ), Etc., or the second capacitor C2 and / or the third capacitor C3 can also be implemented by using parasitic capacitance between the various devices.
  • the connection method of the second capacitor C2 and / or the third capacitor C3 is not limited to the method described above, and may be other suitable connection methods as long as it can store the level written to the control node H or the first node Q. .
  • the first node Q and / or the control node H When the potential of the first node Q and / or the control node H is maintained at a high level, there are some transistors (for example, the second transistor M2, the fifteenth transistor M15, the fourth transistor M4, the fifth transistor M5, and the eleventh transistor M11). And the first pole of the fourteenth transistor M14) is connected to the first node Q or the control node H, and the second pole is connected to the low-level signal. Even when a non-conducting signal is input to the gates of these transistors, leakage may occur due to a voltage difference between the first and second poles of the transistors. The effect of the potential maintenance of the node Q and / or the control node H becomes worse.
  • the first pole of the second transistor M2 is connected to the blanking input signal terminal STU1, and the second pole is connected to the control node H.
  • the control node H may leak electricity through the second transistor M2.
  • some embodiments of the present disclosure provide a shift register unit 10 for preventing leakage.
  • the difference between the shift register unit 10 and the shift register unit 10 in FIG. 6 is that a second leakage prevention transistor M2_b, a fourth leakage prevention transistor M4_b, a fifth leakage prevention transistor M5_b, and an eleventh leakage prevention transistor M11_b are added.
  • the working principle of leakage prevention will be described below by taking the second leakage prevention transistor M2_b as an example.
  • the gate of the second leakage prevention transistor M2_b is connected to the second clock signal terminal CLKB, the first pole of the second leakage prevention transistor M2_b is connected to the second pole of the eighteenth transistor M18, and the second pole of the second leakage prevention transistor M2_b Connect to control node H.
  • the gate of the eighteenth transistor M18 is connected to the control node H, and the first pole of the eighteenth transistor M18 is connected to the ninth voltage terminal VA to receive a high-level ninth voltage.
  • the eighteenth transistor M18 When the control node H is at a high level, the eighteenth transistor M18 is turned on under the control of the level of the control node H, so that the high-level signal input from the ninth voltage terminal VA can be input to the second leakage prevention transistor M2_b.
  • the first pole makes the first and second poles of the second leakage prevention transistor M2_b both at a high level, so that the charge at the control node H can be prevented from leaking through the second leakage prevention transistor M2_b.
  • the combination of the second transistor M2 and the second leakage prevention transistor M2_b can achieve the same effect as the aforementioned second transistor M2, and at the same time With anti-leakage effect.
  • the fifteenth leakage prevention transistor M15_b combined with the eighteenth transistor M18 can prevent the charge at the control node H from leaking through the fifteenth leakage prevention transistor M15_b and the fifteenth transistor M15.
  • the fourth leakage prevention transistor M4_b, the fifth leakage prevention transistor M5_b, the eleventh leakage prevention transistor M11_b, and the fourteenth leakage prevention transistor M14_b can be implemented in combination with the nineteenth transistor M19, thereby preventing the first leakage prevention structure.
  • the charge at node Q is leaking.
  • the working principle of preventing the leakage of the first node Q is the same as the above-mentioned working principle of preventing the leakage of the control node H, and is not repeated here.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • the thin film transistors are used as an example for description.
  • the source and drain of the transistor used here can be symmetrical in structure, so there can be no difference in structure of the source and drain of the transistor.
  • one pole is directly described as the first pole and the other pole is the second pole.
  • the transistors can be divided into N-type and P-type transistors according to the characteristics of the transistors.
  • the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V, or other suitable voltage), and the turn-off voltage is a high-level voltage (for example, 5V, 10V, or other suitable voltage) );
  • the turn-on voltage is a high-level voltage (for example, 5V, 10V, or other suitable voltage)
  • the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V, or other suitable voltage) Voltage).
  • the transistors used in the shift register unit 10 provided in the embodiments of the present disclosure are all described using N-type transistors as an example.
  • the embodiments of the present disclosure include, but are not limited to, for example, shifting At least a part of the transistors in the register unit 10 may also be a P-type transistor.
  • the gate driving circuit 20 includes a plurality of cascaded shift register units 10, wherein any one or more shift register units 10
  • the structure of the shift register unit 10 or a modification thereof provided by the embodiments of the present disclosure may be adopted. It should be noted that only the first four stages of the shift register units (A1, A2, A3, and A4) of the gate driving circuit 20 are shown schematically in FIG. 10.
  • the gate driving circuit 20 further includes a first sub-clock signal line CLK_1, a second sub-clock signal line CLK_2, a third sub-clock signal line CLK_3, and a fourth sub-clock signal line CLK_4.
  • the shift register unit is connected to the first clock signal terminal CLKA and the fourth clock signal terminal CLKD
  • the 2n-1 stage shift register unit is connected to the first sub-clock signal line CLK_1 to receive the first clock signal, for example Is connected to the first sub-clock signal line CLK_1 through the first clock signal terminal CLKA
  • the 2n-1 stage shift register unit is connected to the third sub-clock signal line CLK_3 to receive the fourth clock signal, for example, through the fourth clock signal
  • the terminal CLKD is connected to the third sub-clock signal line CLK_3.
  • the 2n-stage shift register unit is connected to the second sub-clock signal line CLK_2 to receive the first clock signal, for example, connected through the first clock signal terminal CLKA and the second sub-clock signal line CLK_2; the 2n-stage shift register unit and The fourth sub-clock signal line CLK_4 is connected to receive the fourth clock signal, for example, it is connected to the fourth sub-clock signal line CLK_4 through the fourth clock signal terminal CLKD; n is an integer greater than 0.
  • the gate driving circuit 20 may further include a fifth sub-clock signal line CLK_5, a sixth sub-clock signal line CLK_6, and a seventh sub-clock signal line CLK_7.
  • the shift register unit is connected to the second clock signal terminal CLKB, the third clock signal terminal CLKC, and the global reset signal terminal TRST, the 2n-1 stage shift register unit is connected to the fifth sub-clock signal line CLK_5 to receive
  • the second clock signal is, for example, connected through the second clock signal terminal CLKB and the fifth sub clock signal line CLK_5; the 2n-1 stage shift register unit and the sixth sub clock signal line CLK_6 are connected to receive the third clock signal, for example Is connected through the third clock signal terminal CLKC and the sixth sub-clock signal line CLK_6.
  • the 2n-stage shift register unit is connected to the sixth sub-clock signal line CLK_6 to receive the second clock signal, for example, connected through the second clock signal terminal CLKB and the sixth sub-clock signal line CLK_6; the 2n-stage shift register unit and The fifth sub-clock signal line CLK_5 is connected to receive the third clock signal, for example, it is connected to the fifth sub-clock signal line CLK_5 through the second clock signal terminal CLKB.
  • Each stage of the shift register unit is connected to the seventh sub-clock signal line CLK_7 to receive the global reset signal, for example, it is connected to the seventh sub-clock signal line CLK_7 through the global reset signal terminal TRST; n is an integer greater than 0.
  • FIG. 11 is a timing chart of signals when the gate driving circuit 20 shown in FIG. 10 is operating.
  • H ⁇ 1> and H ⁇ 2> denote control nodes H in the first and second stage shift register units in the gate driving circuit 20, respectively
  • Q ⁇ 1> and Q ⁇ 2> denote The first node Q in the first and second stage shift register units in the gate driving circuit 20.
  • OUT ⁇ 1> (CR ⁇ 1>) and OUT ⁇ 2> (CR ⁇ 2>) represent the pixel signal output terminals OUT (shift in the first and second stage shift register units in the gate drive circuit 20, respectively).
  • Bit signal output CR). 1F, 2F, 3F, and 4F represent the first frame, the second frame, the third frame, and the fourth frame, respectively.
  • STU1 and STU2 in FIG. 11 respectively indicate a blanking input signal terminal and a display input signal terminal in the first-stage shift register unit, and STD indicates a display reset signal terminal in the last-stage shift register unit.
  • the seventh voltage terminal CLKM is used to input a low level and the eighth voltage
  • the high level of the terminal CLKN is illustrated as an example, but the embodiment of the present disclosure is not limited thereto.
  • the seventh voltage terminal CLKM and the eighth voltage terminal CLKN can be configured to alternately input a high level, that is, in some frames, the seventh voltage terminal CLKM can be input to a high level and the eighth voltage terminal CLKN can be input. Low.
  • the signal levels in the signal timing diagram shown in FIG. 11 are only schematic and do not represent true level values.
  • the seventh sub-clock signal line CLK_7 provides a high level. Since the global reset signal terminal TRST of the shift register unit of each stage is connected to the seventh sub-clock signal line CLK_7, each stage The fifteenth transistor M15 in the shift register unit is turned on, so that the control node H in each stage of the shift register unit can be reset to achieve a global reset.
  • the eighth transistor M8 is turned on, so that the second node QB is charged to a high level.
  • the high level of the second node QB turns on the eleventh transistor M11, thereby pulling down the first node Q to a low level.
  • the display input signal terminal STU2 of the first-stage shift register unit inputs a high level
  • the first clock signal terminal CLKA (connected to the first sub-clock signal line CLK_1) inputs a high level
  • the first The fifth transistor M5 is turned on, so the high level input at the display input signal terminal STU2 can charge the first node Q ⁇ 1> through the fifth transistor M5, so that the first node Q ⁇ 1> is pulled up to a high level and is The third capacitor C3 is held.
  • the sixth transistor M6 and the seventh transistor M7 are turned on under the control of the first node Q ⁇ 1>, but since the fourth clock signal terminal CLKD (connected to the third sub-clock signal line CLK3) inputs a low-level signal at this stage Therefore, both the shift signal output terminal CR ⁇ 1> and the pixel signal output terminal OUT ⁇ 1> output low-level signals. At this stage, pre-charging of the first node Q ⁇ 1> is completed.
  • the fourth clock signal terminal CLKD inputs a high-level signal, and the potential of the first node Q ⁇ 1> is further pulled up due to the bootstrap effect, so the sixth transistor M6 and the seventh transistor M7 remain conductive. ON, so that both the shift signal output terminal CR ⁇ 1> and the pixel signal output terminal OUT ⁇ 1> output high-level signals.
  • the high-level signal output from the shift signal output terminal CR ⁇ 1> can be used for scanning shift of the upper and lower shift register units, and the high-level signal output from the pixel signal output terminal OUT ⁇ 1> can be used
  • the sub-pixel unit in the driving display panel performs display.
  • the second-stage shift register unit Since the display reset signal terminal STD of the first-stage shift register unit is connected to the shift signal output terminal CR ⁇ 2> of the second-stage shift register unit, at this time the second-stage shift register unit The shift signal output terminal CR ⁇ 2> outputs a high level, so the display reset signal terminal STD of the first pole shift register unit inputs a high level, the fourteenth transistor M14 is turned on, and the first node Q ⁇ 1> is turned on. Pull down to low level to finish resetting the first node Q ⁇ 1>.
  • the tenth transistor M10 is turned off, and at the same time, the high level input at the eighth voltage terminal CLKN can charge the second node QB, and the second node QB is charged to a high level, so The eleventh transistor M11 is turned on to further reduce noise at the first node Q ⁇ 1>.
  • the twelfth transistor M12 and the thirteenth transistor M13 are also turned on, and the shift signal output terminal CR ⁇ 1> and the pixel signal output terminal OUT ⁇ 1> are pulled down to a low level to complete the reset.
  • the analogy is performed in turn, and the second-stage and third-stage shift register units drive the sub-pixel units in the display panel row by row to complete a frame. Display driver. So far, the display period of the first frame ends.
  • the blanking input signal terminal STU1 of the first-stage shift register unit inputs a high level
  • the second clock signal terminal CLKB (connected to the fifth sub-clock signal line CLK_5) inputs a high level
  • the second transistor M2 is turned on, so the high level input from the blanking input signal terminal STU1 can charge the control node H ⁇ 1> through the second transistor M2, so that the control node H ⁇ 1> is pulled up to a high level and is The second capacitor C2 is held.
  • the eighth voltage terminal CLKN is input with a high level at this time, the second node QB is charged to the high level by this high level, so the eleventh transistor M11 is turned on, so that the first node Q ⁇ 1> is pulled down to a low level .
  • the third clock signal terminal CLKC (connected to the sixth sub-clock signal line CLK_6) inputs a low level, so the fourth transistor M4 remains off, and the fourth transistor M4 isolates the control node H ⁇ 1> from the first The influence of a node Q ⁇ 1> keeps the first node Q ⁇ 1> at a low level.
  • the pre-charging of the control node H is completed.
  • the gate driving circuit 20 repeats the same operation as that of the display period DS of the first frame 1F, which is not repeated here.
  • the control node H ⁇ 1> remains high due to the storage of the second capacitor C2, and the third transistor M3 is turned on.
  • the third clock signal terminal CLKC (connected to the sixth sub-clock signal line CLK_6) inputs a high level, so that the fourth transistor M4 is turned on, so the high level input from the third clock signal terminal CLKC can be passed through the third transistor M3 and the first
  • the four transistor M4 charges the first node Q ⁇ 1> and pulls the first node Q ⁇ 1> to a high level.
  • the control node H ⁇ 1> is at a high level
  • the first transistor M1 is turned on, and the high level input at the third clock signal terminal CLKC can be coupled up and pulled up by the first capacitor C1, so that The potential of the control node H ⁇ 1> is further pulled up.
  • the third transistor M3 can be more fully turned on, so that the high level input from the third clock signal terminal CLKC can fully charge the first node Q.
  • the sixth transistor M6 and the seventh transistor M7 are turned on, and the high level input from the fourth clock signal terminal CLKD (connected to the third sub-clock signal line CLK_3) can be output to the shift signal.
  • the signal output from the shift signal output terminal CR ⁇ 1> can be used for scanning shift of the upper and lower shift register units, and the signal output from the pixel signal output terminal OUT can be used to drive the sensing in the sub-pixel unit in the display panel. Transistor for external compensation.
  • the blanking input signal terminal STU1 of the second-stage shift register unit is connected to the first
  • the shift signal output terminal CR ⁇ 1> of the first-stage shift register unit is connected, so the second transistor M2 in the second-stage shift register unit is turned on, so that the control node H ⁇ 2> Pulled high and held.
  • the high level input at the eighth voltage terminal CLKN charges the second node QB to a high level, and the high level of the second node QB causes the eleventh transistor M11 to be turned on , Further pull down the level of the first node Q ⁇ 1> to complete the reset of the first node Q ⁇ 1>.
  • the gate driving circuit 20 repeats the same operation as that of the display period DS of the first frame 1F, which is not repeated here.
  • the second clock signal terminal CLKB (connected to the fifth sub-clock signal line CLK_5) is input high level, and the second transistor M2 is turned on, but since at this stage The blanking input signal terminal STU1 is at a low level, so the control node H can be discharged to a low level through the second transistor M2 to complete the reset.
  • the control node H when the control node H is at a high level, the control node H is further coupled and pulled up, so that the first node Q is charged more fully in the blanking period of one frame to avoid occurrence.
  • the output is abnormal.
  • the display device 1 includes a gate driving circuit 20 provided by an embodiment of the present disclosure.
  • the display device 1 further includes a display panel 40 including an array of a plurality of sub-pixel units 410.
  • the display device 1 may further include a data driving circuit 30.
  • the data driving circuit 30 is used to provide a data signal to the pixel array;
  • the gate driving circuit 20 is used to provide a driving signal to the pixel array.
  • the driving signal can drive the scan transistor and the sensing transistor in the sub-pixel unit 410.
  • the data driving circuit 30 is electrically connected to the sub-pixel unit 410 through a data line DL, and the gate driving circuit 20 is electrically connected to the sub-pixel unit 410 through a gate line GL.
  • the display device 1 in this embodiment may be any of: a liquid crystal panel, a liquid crystal television, a display, an OLED panel, an OLED television, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, etc. Products or parts with display capabilities.
  • An embodiment of the present disclosure further provides a driving method that can be used to drive the shift register unit 10 provided by the embodiment of the present disclosure.
  • the driving method includes: a blanking period in one frame, so that the coupling circuit 400 responds to the blanking
  • the signal performs a coupling control on the level of the control node H, for example, a coupling pull-up, the blanking input circuit 100 inputs a blanking signal to the first node Q, and the output circuit outputs a composite under the control of the level of the first node Q of 300. output signal.
  • An embodiment of the present disclosure further provides a driving method that can be used to drive the shift register unit 10 provided by the embodiment of the present disclosure.
  • the driving method includes the following operations.
  • the display input circuit 200 inputs the display signal to the first node Q in response to the first clock signal, and the output circuit 300 outputs the first output signal under the control of the level of the first node Q.
  • the blanking input circuit 100 inputs a blanking input signal to the control node H.
  • the coupling circuit 400 controls the level of the control node H in response to the blanking signal, for example, performs a coupling pull-up, and the blanking input circuit 100 inputs the blanking signal to the first node.
  • the output circuit 300 outputs a second output signal under the control of the level of the first node Q.
  • the composite output signal includes a first output signal and a second output signal.

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Abstract

一种移位寄存器单元、栅极驱动电路、显示装置及驱动方法。该移位寄存器单元(10)包括消隐输入电路(100)、显示输入电路(200)、输出电路(300)和耦合电路(400)。消隐输入电路(100)被配置为将消隐输入信号输入到控制节点(H)并在一帧的消隐时段将消隐信号输入到第一节点(Q)；显示输入电路(200)被配置为响应于第一时钟信号在一帧的显示时段将显示信号输入到第一节点(Q)；输出电路(300)被配置为在第一节点(Q)的电平的控制下，将复合输出信号输出至输出端(OUTPUT)；耦合电路(400)与控制节点(H)电连接，且被配置为响应于消隐信号对控制节点(H)的电平进行耦合控制。该移位寄存器单元(10)可以对控制节点(H)的电平进行耦合控制，从而使得对第一节点(Q)的充电更充分，以避免发生输出异常。

Description

移位寄存器单元、栅极驱动电路、显示装置及驱动方法
本申请要求于2018年6月28日递交的中国专利申请第201810691084.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种移位寄存器单元、栅极驱动电路、显示装置及驱动方法。
背景技术
在显示领域特别是OLED(Organic Light-Emitting Diode，有机发光二极管)显示面板中，栅极驱动电路目前一般集成在GATE IC中。IC设计中芯片的面积是影响芯片成本的主要因素，如何有效地降低芯片面积是技术开发人员需要着重考虑的。
发明内容
本公开至少一实施例提供一种移位寄存器单元，包括消隐输入电路、显示输入电路、输出电路和耦合电路。所述消隐输入电路被配置为将消隐输入信号输入到控制节点并在一帧的消隐时段将消隐信号输入到第一节点；所述显示输入电路被配置为响应于第一时钟信号在一帧的显示时段将显示信号输入到所述第一节点；所述输出电路被配置为在所述第一节点的电平的控制下，将复合输出信号输出至输出端；所述耦合电路与所述控制节点电连接，且被配置为响应于所述消隐信号对所述控制节点的电平进行耦合控制。
例如，在本公开一实施例提供的移位寄存器单元中，所述耦合电路包括第一电容，所述第一电容的第一极和第三时钟信号端连接以接收第三时钟信号作为所述消隐信号，所述第一电容的第二极和所述控制节点连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述耦合电路包括第一电容和第一晶体管。所述第一晶体管的栅极和所述控制节点连接， 所述第一晶体管的第一极和第三时钟信号端连接以接收第三时钟信号作为所述消隐信号，所述第一晶体管的第二极和所述第一电容的第一极连接，所述第一电容的第二极和所述控制节点连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述消隐输入电路包括：充电子电路，被配置为响应于第二时钟信号将所述消隐输入信号输入到所述控制节点；存储子电路，被配置为存储所述充电子电路输入的所述消隐输入信号；隔离子电路，被配置为在所述控制节点的电平和第三时钟信号的控制下，将所述消隐信号输入到所述第一节点。
例如，在本公开一实施例提供的移位寄存器单元中，所述充电子电路包括第二晶体管，所述第二晶体管的栅极和第二时钟信号端连接以接收所述第二时钟信号，所述第二晶体管的第一极和消隐输入信号端连接以接收所述消隐输入信号，所述第二晶体管的第二极和所述控制节点连接；所述存储子电路包括第二电容，所述第二电容的第一极和所述控制节点连接，所述第二电容的第二极和第一电压端连接以接收第一电压；所述隔离子电路包括第三晶体管和第四晶体管，所述第三晶体管的栅极和所述控制节点连接，所述第三晶体管的第一极和第三时钟信号端连接以接收所述第三时钟信号作为所述消隐信号，所述第三晶体管的第二极和所述第四晶体管的第一极连接，所述第四晶体管的栅极和所述第三时钟信号端连接以接收所述第三时钟信号，所述第四晶体管的第二极和所述第一节点连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述显示输入电路包括第五晶体管；所述第五晶体管的栅极和第一时钟信号端连接以接收所述第一时钟信号，所述第五晶体管的第一极和显示输入信号端连接以接收所述显示信号，所述第五晶体管的第二极和所述第一节点连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述输出端包括移位信号输出端和像素信号输出端，所述移位信号输出端和所述像素信号输出端输出所述复合输出信号，所述输出电路包括第六晶体管、第七晶体管和第三电容；所述第六晶体管的栅极和所述第一节点连接，所述第六晶体管的第一极和第四时钟信号端连接以接收第四时钟信号作为所述复合输出信号，所述第六晶体管的第二极和所述移位信号输出端连接；所述第七晶体管的栅极和所述第一节点连接，所述第七晶体管的第一极和所述第四时钟信号端连接以接收所述第四时钟信号作为所述复合输出信号，所述第 七晶体管的第二极和所述像素信号输出端连接；所述第三电容的第一极和所述第一节点连接，所述第三电容的第二极和所述第六晶体管的第二极连接。
例如，本公开一实施例提供的移位寄存器单元还包括降噪电路和控制电路。所述控制电路被配置为在所述第一节点的电平的控制下，对第二节点的电平进行控制；所述降噪电路被配置为在所述第二节点的电平的控制下，对所述第一节点、所述移位信号输出端和所述像素信号输出端进行降噪。
例如，在本公开一实施例提供的移位寄存器单元中，所述控制电路包括第八晶体管、第九晶体管和第十晶体管；所述第八晶体管的栅极和第一极连接且被配置为和第七电压端连接以接收第七电压，所述第八晶体管的第二极和所述第二节点连接；所述第九晶体管的栅极和第一极连接且被配置为和第八电压端连接以接收第八电压，所述第九晶体管的第二极和所述第二节点连接；所述第十晶体管的栅极和所述第一节点连接，所述第十晶体管的第一极和所述第二节点连接，所述第十晶体管的第二极和第四电压端连接以接收第四电压。
例如，在本公开一实施例提供的移位寄存器单元中，所述降噪电路包括第十一晶体管、第十二晶体管和第十三晶体管；所述第十一晶体管的栅极和所述第二节点连接，所述第十一晶体管的第一极和所述第一节点连接，所述第十一晶体管的第二极和第三电压端连接以接收第三电压；所述第十二晶体管的栅极和所述第二节点连接，所述第十二晶体管的第一极和所述移位信号输出端连接，所述第十二晶体管的第二极和第五电压端连接以接收第五电压；所述第十三晶体管的栅极和所述第二节点连接，所述第十三晶体管的第一极和所述像素信号输出端连接，所述第十三晶体管的第二极和第六电压端连接以接收第六电压。
例如，本公开一实施例提供的移位寄存器单元还包括显示复位电路，所述显示复位电路被配置为响应于显示复位信号对所述第一节点进行复位。
例如，在本公开一实施例提供的移位寄存器单元中，所述显示复位电路包括第十四晶体管；所述第十四晶体管的栅极和显示复位信号端连接以接收所述显示复位信号，所述第十四晶体管的第一极和所述第一节点连接， 所述第十四晶体管的第二极和第二电压端连接以接收第二电压。
例如，本公开一实施例提供的移位寄存器单元还包括全局复位电路，所述全局复位电路被配置为响应于全局复位信号对所述控制节点进行复位。
例如，在本公开一实施例提供的移位寄存器单元中，所述全局复位电路包括第十五晶体管；所述第十五晶体管的栅极和全局复位信号端连接以接收所述全局复位信号，所述第十五晶体管的第一极和所述控制节点连接，所述第十五晶体管的第二极和第一电压端连接以接收第一电压。
本公开至少一实施例还提供一种栅极驱动电路，包括多个级联的如本公开的实施例提供的任一移位寄存器单元。
例如，本公开一实施例提供的栅极驱动电路还包括第一子时钟信号线、第二子时钟信号线、第三子时钟信号线和第四子时钟信号线。第2n-1级移位寄存器单元和所述第一子时钟信号线连接以接收第一时钟信号，第2n-1级移位寄存器单元和所述第三子时钟信号线连接以接收第四时钟信号；第2n级移位寄存器单元和所述第二子时钟信号线连接以接收第一时钟信号，第2n级移位寄存器单元和所述第四子时钟信号线连接以接收第四时钟信号；n为大于0的整数。
例如，本公开一实施例提供的栅极驱动电路还包括第五子时钟信号线、第六子时钟信号线和第七子时钟信号线。第2n-1级移位寄存器单元和所述第五子时钟信号线连接以接收第二时钟信号，第2n-1级移位寄存器单元和所述第六子时钟信号线连接以接收第三时钟信号；第2n级移位寄存器单元和所述第六子时钟信号线连接以接收第二时钟信号，第2n级移位寄存器单元和所述第五子时钟信号线连接以接收第三时钟信号；每一级移位寄存器单元和所述第七子时钟信号线连接以接收全局复位信号；n为大于0的整数。
本公开至少一实施例还提供一种显示装置，包括如本公开的实施例提供的任一栅极驱动电路。
本公开至少一实施例还提供一种移位寄存器单元的驱动方法，包括：
在一帧的消隐时段，使得所述耦合电路响应于所述消隐信号对所述控制节点的电平进行耦合控制，所述消隐输入电路将所述消隐信号输入到所述第一节点，所述输出电路在所述第一节点的电平的控制下输出所述复合 输出信号。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一些实施例提供的一种移位寄存器单元的示意图；
图2为本公开一些实施例提供的一种消隐输入电路的示意图；
图3为本公开一些实施例提供的另一种移位寄存器单元的示意图；
图4为本公开一些实施例提供的一种移位寄存器单元的电路图；
图5为本公开一些实施例提供的另一种移位寄存器单元的电路图；
图6为本公开一些实施例提供的再一种移位寄存器单元的电路图；
图7为本公开一些实施例提供的再一种移位寄存器单元的电路图；
图8为本公开一些实施例提供的再一种移位寄存器单元的电路图；
图9为本公开一些实施例提供的又一种移位寄存器单元的电路图；
图10为本公开一些实施例提供的一种栅极驱动电路的示意图；
图11为本公开一些实施例提供的一种对应于图10所示的栅极驱动电路工作时的信号时序图；
图12为图4所示的移位寄存器单元在不包括第一电容的情形下的信号仿真图；
图13为图4所示的移位寄存器单元的信号仿真图；
图14为图6所示的移位寄存器单元的信号仿真图；以及
图15为本公开一些实施例提供的一种显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属 领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本公开的实施例中，例如，当各个电路实现为N型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如截止)。
又例如，当各个电路实现为P型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如截止)。
并且，术语“上拉”、“下拉”的具体含义也将根据所采用的晶体管的具体类型而相应调整，只要能实现对于晶体管的控制以实现相应的开关功能。
目前用于OLED的栅极驱动电路通常要用三个子电路组合而成，即检测电路、显示电路和输出两者复合脉冲的连接电路(或门电路)，这样的电路结构非常复杂，无法满足高分辨率窄边框的要求。
在对OLED显示面板中的子像素单元进行补偿时，除了在子像素单元中设置像素补偿电路进行内部补偿外，还可以通过设置感测晶体管进行外部补偿。在进行外部补偿时，由移位寄存器单元构成的栅极驱动电路需要向显示面板中的子像素单元分别提供用于扫描晶体管和感测晶体管的驱动信号，例如，在一帧的显示时段(DS)提供用于扫描晶体管的扫描驱动信号，在一帧的消隐时段(BL)提供用于感测晶体管的感测驱动信号。
在一种移位寄存器单元中，由于晶体管可能存在阈值电压漂移(例如， 负向漂移)，从而导致控制节点可能会发生漏电。例如在一帧的消隐时段中，在控制节点发生漏电时，对第一节点的充电不充分，从而可能导致该移位寄存器单元无法正常输出用于感测晶体管的感测驱动信号。
针对上述问题，本公开的至少一实施例提供一种移位寄存器单元，该移位寄存器单元包括消隐输入电路、显示输入电路、输出电路和耦合电路。消隐输入电路被配置为将消隐输入信号输入到控制节点并在一帧的消隐时段将消隐信号输入到第一节点；显示输入电路被配置为响应于第一时钟信号在一帧的显示时段将显示信号输入到第一节点；输出电路被配置为在第一节点的电平的控制下，将复合输出信号输出至输出端；耦合电路与控制节点电连接，且被配置为响应于消隐信号对控制节点的电平进行耦合控制。本公开的实施例还提供对应于上述移位寄存器单元的栅极驱动电路、显示装置及驱动方法。
本公开的实施例提供的移位寄存器单元，在控制节点为高电平时，可以对控制节点的电平进行耦合控制，从而在一帧的消隐时段中对第一节点的充电更充分，以避免发生输出异常。
需要说明的是，在本公开的实施例中，为了说明的目的，定义“一帧”、“每帧”或“某一帧”包括依次进行的显示时段和消隐时段，例如在显示时段中栅极驱动电路输出显示输出信号，该显示输出信号可以驱动显示面板从第一行到最后一行完成完整的一幅图像的扫描显示，在消隐时段中栅极驱动电路输出消隐输出信号，该消隐输出信号可以用于驱动显示面板中的某一行子像素单元中的感测晶体管，以完成该行子像素单元的外部补偿。
下面结合附图对本公开的实施例及其示例进行详细说明。
本公开的至少一个实施例提供一种移位寄存器单元10，如图1所示，该移位寄存器单元10包括消隐输入电路100、显示输入电路200、输出电路300和耦合电路400。消隐输入电路100、显示输入电路200以及输出电路300通过第一节点Q相连接。
该消隐输入电路100被配置为将消隐输入信号输入到控制节点H并在一帧的消隐时段将消隐信号输入到第一节点Q。
在一些实施例中，消隐输入电路100可以和消隐输入信号端STU1以及第二时钟信号端CLKB连接，从而可以在第二时钟信号端CLKB输入的第二时钟信号的控制下，将消隐输入信号端STU1输入的消隐输入信号输入到控 制节点H。消隐输入电路100还可以和第三时钟信号端CLKC连接，从而在一帧的消隐时段将第三时钟信号端CLKC输入的第三时钟信号作为消隐信号输入到第一节点Q，从而将第一节点Q上拉至高电平。
例如，消隐输入电路100可以在一帧的消隐时段接收消隐输入信号并存储消隐输入信号，并在下一帧的消隐时段根据消隐输入信号向第一节点Q输出消隐信号，从而将第一节点Q上拉至高电平。
例如，在多个移位寄存器单元10级联形成一栅极驱动电路时，除了第一级移位寄存器单元外，其余各级移位寄存器单元的消隐输入信号端STU1可以和上一级移位寄存器单元的输出端OUTPUT电连接。例如，在输出端OUTPUT包括移位信号输出端CR和像素信号输出端OUT的情形下，消隐输入信号端STU1可以和移位信号输出端CR连接。
该显示输入电路200被配置为响应于第一时钟信号在一帧的显示时段将显示信号输入到第一节点Q。例如，在一些实施例中，显示输入电路200可以和第一时钟信号端CLKA连接以接收第一时钟信号，显示输入电路200还可以和显示输入信号端STU2连接以接收显示信号。例如，显示输入电路200在一帧的显示时段中，在第一时钟信号的控制下可以将显示信号输入到第一节点Q，从而将第一节点Q上拉至高电平。
例如，在多个移位寄存器单元10级联形成一栅极驱动电路时，除了第一级移位寄存器单元外，其余各级移位寄存器单元的显示输入信号端STU2可以和上一级移位寄存器单元的输出端OUTPUT电连接。例如，在输出端OUTPUT包括移位信号输出端CR和像素信号输出端OUT的情形下，显示输入信号端STU2可以和移位信号输出端CR连接。
需要说明的是，在本公开的实施例中，显示输入电路200还可以采用其他配置方式，只要可以实现相应的功能即可，本公开的实施例对此不作限定。
该输出电路300被配置为在第一节点Q的电平的控制下，将复合输出信号输出至输出端OUTPUT。例如，在一些实施例中，输出电路300可以和第四时钟信号端CLKD连接以接收第四时钟信号并作为复合输出信号。例如，复合输出信号可以包括显示输出信号和消隐输出信号，在一帧的显示时段中，输出电路300在第一节点Q的电平的控制下将显示输出信号输出至输出端OUTPUT，例如在一些实施例中，输出端OUTPUT可以包括移位信号输出端CR和像素信号输出端OUT，从移位信号输出端CR输出的显示输出信 号可以用于上下级移位寄存器单元的扫描移位，而从像素信号输出端OUT输出的显示输出信号可以用于驱动显示面板中的子像素单元进行扫描显示。在一帧的消隐时段中，输出电路300在第一节点Q的电平的控制下将消隐输出信号输出至输出端OUTPUT，该消隐输出信号可以用于驱动感测晶体管。
该耦合电路400与控制节点H电连接，且被配置为响应于消隐信号对控制节点H的电平进行耦合控制，例如，对控制节点H的电平进行耦合上拉。例如，在一些实施例中，耦合电路400可以和第三时钟信号端CLKC连接，将第三时钟信号端CLKC输入的第三时钟信号作为消隐信号。例如，在一帧的消隐时段消隐输入电路100对控制节点H进行充电，使得控制节点H的电位被上拉至高电平；然后在下一帧的消隐时段中耦合电路400可以响应于消隐信号对控制节点H的电平进行耦合上拉，可以避免控制节点H发生漏电，从而使得在该帧的消隐时段中对第一节点Q的充电更充分，以避免发生输出异常。
在本公开的实施例提供的移位寄存器单元10中，通过设置耦合电路400，可以在控制节点H为高电平时，对控制节点H进一步耦合上拉，从而在一帧的消隐时段中对第一节点Q的充电更充分，以避免发生输出异常。
在本公开的实施例的一些实施例中，如图2所示，消隐输入电路100包括充电子电路110、存储子电路120以及隔离子电路130。
该充电子电路110被配置为响应于第二时钟信号将消隐输入信号输入到控制节点H。例如，充电子电路110和消隐输入信号端STU1连接以接收消隐输入信号，充电子电路110和第二时钟信号端CLKB连接以接收第二时钟信号。例如，充电子电路110可以在第二时钟信号的控制下而导通从而可以将消隐输入信号输入到控制节点H。
该存储子电路120被配置为存储充电子电路110输入的消隐输入信号。例如，在一帧的消隐时段中，控制节点H被输入的消隐输入信号充电至高电平，存储子电路120可以存储该消隐输入信号，从而使得控制节点H的高电平可以一直保持至下一帧的消隐时段。
该隔离子电路130被配置为在控制节点H的电平和第三时钟信号的控制下，将消隐信号输入到第一节点Q。例如，在一些实施例中，隔离子电路130和第三时钟信号端CLKC连接以接收第三时钟信号，同时还将第三时钟信号作为消隐信号。
例如，在一帧的消隐时段中，隔离子电路130在控制节点H的电平和第三时钟信号的控制下导通，从而可以将消隐信号输入到第一节点Q。又例如，在一些实施例中，隔离子电路130设置在第一节点Q和控制节点H之间，用于防止第一节点Q与控制节点H的相互影响。例如，在不需要输出消隐信号时，隔离子电路130可以断开第一节点Q与控制节点H之间的连接。
根据本公开的实施例提供的移位寄存器单元10，可以实现在不同时段通过消隐输入电路100和显示输入电路200分别控制第一节点Q的电平，从而实现消隐输入电路100和显示输入电路200共用同一个输出电路300实现复合输出信号的输出。
在一些实施例中，如图3所示，移位寄存器单元10还可以包括控制电路500，控制电路500被配置为在第一节点Q的电平的控制下，对第二节点QB的电平进行控制。例如，在一些实施例中，控制电路500和第七电压端CLKM以及第四电压端VSS4连接。需要说明的是，在本公开的实施例中第四电压端VSS4例如可以被配置为提供直流低电平信号，以下各实施例与此相同，不再赘述。
例如，当第一节点Q处于高电平时，控制电路500可以通过第四电压端VSS4将第二节点QB下拉至低电平。又例如，当第一节点Q的电位处于低电平时，控制电路500可以利用第七电压端CLKM输入的第七电压(例如为高电平)对第二节点QB进行充电，以将第二节点QB上拉至高电平。
在另一些实施例中，控制电路500还可以和第八电压端CLKN连接以接收第八电压(例如为高电平)，例如，第七电压端CLKM和第八电压端CLKN可以被配置为交替输入高电平，即第七电压端CLKM输入高电平时，第八电压端CLKN输入低电平，而第七电压端CLKM输入低电平时，第八电压端CLKN输入高电平。
在一些实施例中，如图3所示，移位寄存器单元10还可以包括降噪电路600，降噪电路600被配置为在第二节点QB的电平的控制下，对第一节点Q和输出端OUTPUT进行降噪。例如，在输出端OUTPUT包括移位信号输出端CR和像素信号输出端OUT的情形下，降噪电路600可以对移位信号输出端CR和像素信号输出端OUT同时进行降噪。
例如，降噪电路600和第三电压端VSS3、第五电压端VSS5以及第六电压端VSS6连接，降噪电路600在第二节点QB的电平的控制下导通时，可 以通过第三电压端VSS3、第五电压端VSS5以及第六电压端VSS6分别对第一节点Q、移位信号输出端CR以及像素信号输出端OUT进行下拉，从而实现降噪。需要说明的是，本公开的实施例中的第三电压端VSS3、第五电压端VSS5以及第六电压端VSS6例如可以被配置为提供直流低电平信号，以下各实施例与此相同，不再赘述。
在一些实施例中，如图3所示，移位寄存器单元10还可以包括显示复位电路700，显示复位电路700被配置为响应于显示复位信号对第一节点Q进行复位。例如，在一个示例中，显示复位电路700可以和显示复位信号端STD连接以接收显示复位信号，同时和第二电压端VSS2连接以接收低电平的第二电压。例如，在一帧的显示时段中，显示复位电路700可以响应于显示复位信号而导通，从而可以通过第二电压端VSS2对第一节点Q进行复位。例如，在多个移位寄存器单元10级联形成一栅极驱动电路时，除了最后一级移位寄存器单元外，其余各级移位寄存器单元的显示复位信号端STD可以和下一级移位寄存器单元的输出端OUTPUT(例如移位信号输出端CR)电连接。需要说明的是，在本公开的实施例中的第二电压端VSS2例如可以被配置为提供直流低电平信号，以下各实施例与此相同，不再赘述。
在一些实施例中，如图3所示，移位寄存器单元10还可以包括全局复位电路800，全局复位电路800被配置为响应于全局复位信号对控制节点H进行复位。例如，在一个示例中，全局复位电路800和全局复位信号端TRST连接以接收全局复位信号，同时和第一电压端VSS1连接以接收低电平的第一电平。例如，在多个移位寄存器单元10级联形成一栅极驱动电路时，在一帧的显示时段前，各级移位寄存器单元10中的全局复位电路800响应于全局复位信号而导通，通过第一电压端VSS1对控制节点H进行复位，从而实现对各级移位寄存器单元10的全局复位。需要说明的是，在本公开的实施例中的第一电压端VSS1例如可以被配置为提供直流低电平信号，以下各实施例与此相同，不再赘述。
需要说明的是，在本公开的实施例中，例如，第一电压端VSS1、第二电压端VSS2、第三电压端VSS3、第四电压端VSS4、第五电压端VSS5以及第六电压端VSS6输入的低电平信号可以相同，即可以将上述六个电压端连接到同一根信号线以接收相同的低电平信号；又例如，上述六个电压端中的两个、三个或更多个可以连接到同一根信号线以接收相同的低电平信号； 又例如，上述六个电压端可以分别连接到不同的信号线以分别接收不同的低电平信号。本公开的实施例对第一电压端VSS1、第二电压端VSS2、第三电压端VSS3、第四电压端VSS4、第五电压端VSS5以及第六电压端VSS6的设置方式不作限定。
本领域技术人员可以理解，尽管图3中的移位寄存器单元10示出了控制电路500、降噪电路600、显示复位电路700以及全局复位电路800，然而上述示例并不能限制本公开的保护范围。在实际应用中，技术人员可以根据情况选择使用或不使用上述各电路中的一个或多个，基于前述各电路的各种组合变型均不脱离本公开的原理，对此不再赘述。
在本公开的一些实施例中，图3中所示的移位寄存器单元10可以实现为图4所示的电路结构。如图4所示，该移位寄存器单元10包括：第二至第十五晶体管M2-M15、第一电容C1、第二电容C2以及第三电容C3。输出端OUTPUT包括移位信号输出端CR和像素信号输出端OUT，移位信号输出端CR和像素信号输出端OUT均可以输出复合输出信号。需要说明的是，在图4中所示的晶体管均以N型晶体管为例进行说明。
如图4所示，消隐输入电路100中的充电子电路110可以实现为第二晶体管M2，第二晶体管M2的栅极和第二时钟信号端CLKB连接以接收第二时钟信号，第二晶体管M2的第一极和消隐输入信号端STU1连接以接收消隐输入信号，第二晶体管M2的第二极和控制节点H连接。例如，当第二时钟信号为高电平的导通信号时，第二晶体管M2在第二时钟信号的控制下导通，从而可以将消隐输入信号输入到控制节点H以对其进行充电。
如图4所示，消隐输入电路100中的存储子电路120可以实现为第二电容C2，第二电容C2的第一极和控制节点H连接，第二电容C2的第二极和第一电压端VSS1连接以接收第一电压。通过设置第二电容C2可以保持控制节点H的电位，例如，在一帧的消隐时段中，充电子电路110将控制节点H充电至高电位，第二电容C2可以将控制节点H的高电位保持至下一帧的消隐时段。需要说明的是，在本公开的实施例中，第二电容C2的第二极除了可以和第一电压端VSS1连接外，还可以与其他电压端连接，例如第二电容C2的第二极接地，本公开的实施例对此不作限定。
如图4所示，消隐输入电路100中的隔离子电路130可以实现为第三晶体管M3和第四晶体管M4，第三晶体管M3的栅极和控制节点H连接，第 三晶体管M3的第一极和第三时钟信号端CLKC连接以接收第三时钟信号并作为消隐信号，第三晶体管M3的第二极和第四晶体管M4的第一极连接，第四晶体管M4的栅极和第三时钟信号端CLKC连接以接收第三时钟信号，第四晶体管M4的第二极和第一节点Q连接。例如，在一帧的消隐时段中，第三晶体管M3在控制节点H的控制下导通，当第三时钟信号为高电平时，第四晶体管M4在第三时钟信号的控制下导通，从而第三时钟信号作为消隐信号通过第三晶体管M3和第四晶体管M4对第一节点Q进行充电。
如图4所示，显示输入电路200可以实现为第五晶体管M5，第五晶体管M5的栅极和第一时钟信号端CLKA连接以接收第一时钟信号，第五晶体管M5的第一极和显示输入信号端STU2连接以接收显示信号，第五晶体管M5的第二极和第一节点Q连接。例如，在一帧的显示时段中，第五晶体管M5在第一时钟信号的控制下导通，从而利用显示信号对第一节点Q进行充电。
如图4所示，输出电路300可以实现为包括第六晶体管M6、第七晶体管M7和第三电容C3。第六晶体管M6的栅极和第一节点Q连接，第六晶体管M6的第一极和第四时钟信号端CLKD连接以接收第四时钟信号作为复合输出信号，第六晶体管M6的第二极和移位信号输出端CR连接；第七晶体管M7的栅极和第一节点Q连接，第七晶体管M7的第一极和第四时钟信号端CLKD连接以接收第四时钟信号作为复合输出信号，第七晶体管M7的第二极和像素信号输出端OUT连接；第三电容C3的第一极和第一节点Q连接，第三电容C3的第二极和第六晶体管M6的第二极连接。例如，在第一节点Q的电位为高电平时，第六晶体管M6和第七晶体管M7导通，从而可以将第四时钟信号作为复合输出信号输出至移位信号输出端CR和像素信号输出端OUT。
如图4所示，控制电路500可以实现为包括第八晶体管M8、第九晶体管M9和第十晶体管M10。第八晶体管M8的栅极和第一极连接且被配置为和第七电压端CLKM连接以接收第七电压，第八晶体管M8的第二极和第二节点QB连接；第九晶体管M9的栅极和第一极连接且被配置为和第八电压端CLKN连接以接收第八电压，第九晶体管M9的第二极和第二节点QB连接；第十晶体管M10的栅极和第一节点Q连接，第十晶体管M10的第一极和第二节点QB连接，第十晶体管M10的第二极和第四电压端VSS4连接以 接收第四电压。
例如，第七电压端CLKM和第八电压端CLKN可以被配置为交替输入高电平，即第七电压端CLKM输入高电平时，第八电压端CLKN输入低电平，而第七电压端CLKM输入低电平时，第八电压端CLKN输入高电平，即第八晶体管M8和第九晶体管M9中只有一个晶体管处于导通状态，这样可以避免晶体管长期导通引起的性能漂移。当第八晶体管M8或第九晶体管M9导通时，第七电压或第八电压可以对第二节点QB进行充电，从而将第二节点QB上拉至高电平。当第一节点Q的电位为高电平时，第十晶体管M10导通，例如在晶体管的设计上，可以将第十晶体管M10与第八晶体管M8(或第九晶体管M9)配置为(例如对二者的尺寸比、阈值电压等配置)在M10和M8(M9)均导通时，第二节点QB的电平可以被下拉至低电平，该低电平可以使得第十一晶体管M11、第十二晶体管M12以及第十三晶体管M13保持截止。
如图4所示，降噪电路600可以实现为包括第十一晶体管M11、第十二晶体管M12和第十三晶体管M13。第十一晶体管M11的栅极和第二节点QB连接，第十一晶体管M11的第一极和第一节点Q连接，第十一晶体管M11的第二极和第三电压端VSS3连接以接收第三电压；第十二晶体管M12的栅极和第二节点QB连接，第十二晶体管M12的第一极和移位信号输出端CR连接，第十二晶体管M12的第二极和第五电压端VSS5连接以接收第五电压；第十三晶体管M13的栅极和第二节点QB连接，第十三晶体管M13的第一极和像素信号输出端OUT连接，第十三晶体管M13的第二极和第六电压端VSS6连接以接收第六电压。
例如，当第二节点QB的电位为高电平时，第十一晶体管M11、第十二晶体管M12以及第十三晶体管M13导通，从而可以利用第三电压、第五电压以及第六电压分别对第一节点Q、移位信号输出端CR以及像素信号输出端OUT进行下拉，以降低噪声。
如图4所示，显示复位电路700可以实现为第十四晶体管M14。第十四晶体管M14的栅极和显示复位信号端STD连接以接收显示复位信号，第十四晶体管M14的第一极和第一节点Q连接，第十四晶体管M14的第二极和第二电压端VSS2连接以接收第二电压。例如，当显示复位信号为高电平时，第十四晶体管M14导通，从而可以利用第二电压端VSS2对第一节点Q进 行复位。
如图4所示，全局复位电路800可以实现为第十五晶体管M15。第十五晶体管M15的栅极和全局复位信号端TRST连接以接收全局复位信号，第十五晶体管M15的第一极和控制节点H连接，第十五晶体管M15的第二极和第一电压端VSS1连接以接收第一电压。例如，当全局复位信号为高电平时，第十五晶体管M15导通，从而可以利用第一电压端VSS1对控制节点H进行复位。
在一些实施例中，如图4所示，耦合电路400可以实现为第一电容C1，第一电容C1的第一极和第三时钟信号端CLKC电连接以接收第三时钟信号作为消隐信号，第一电容C1的第二极和控制节点H连接。例如，在控制节点H为高电平时，第三晶体管M3导通，同时在第三时钟信号为高电平时，第四晶体管M4导通，从而高电平的第三时钟信号作为消隐信号通过第三晶体管M3和第四晶体管M4输入到第一节点Q，以对第一节点Q进行充电。同时，在第三时钟信号为高电平时，该高电平可以通过第一电容C1对控制节点H进一步耦合上拉，从而使得第三晶体管M3的导通更充分，消隐信号对第一节点Q的充电更充分，以避免发生输出异常。
在另一些实施例中，如图5所示，第一电容C1的第一极还可以和第十电压端VDD连接以接收第十电压，例如第十电压为直流高电平。需要说明的是，图5中所示的移位寄存器单元和图4中所示的移位寄存器单元相同的部分可以参考上述描述，这里不再赘述。
在又一些实施例中，如图6所示，耦合电路400可以实现为包括第一晶体管M1和第一电容C1。第一晶体管M1的栅极和控制节点H连接，第一晶体管M1的第一极和第三时钟信号端CLKC连接以接收第三时钟信号作为消隐信号，第一晶体管M1的第二极和第一电容C1的第一极连接，第一电容C1的第二极和控制节点H连接。例如，在控制节点H为高电平时，第一晶体管M1导通，从而第三时钟信号端CLKC提供的第三时钟信号可以施加至第一电容C1的第一极。当第三时钟信号为高电平时，该高电平可以通过第一电容C1对控制节点H进一步耦合上拉，从而使得第三晶体管M3导通的更充分，消隐信号对第一节点Q的充电更充分，以避免发生输出异常。
需要说明的是，图6中所示的移位寄存器单元和图4中所示的移位寄存器单元相同的部分可以参考上述描述，这里不再赘述。
在另一些实施例提供的移位寄存器单元10中，如图7所示，该移位寄存器单元10和图6中所示的移位寄存器单元10相比还可以包括第二十晶体管M20。该第二十晶体管M20的栅极和全局复位信号端TRST连接以接收全局复位信号，第二十晶体管M20的第一极和第一节点Q连接，第二十晶体管M20的第二极和第一电压端VSS1连接以接收第一电压。例如，在多个图7中的移位寄存器单元10级联形成一栅极驱动电路时，在一帧的显示时段前，各级移位寄存器单元10中的第十五晶体管M15和第二十晶体管M20响应于全局复位信号而开启，通过第一电压端VSS1对控制节点H和第一节点Q同时进行复位，从而实现对各级移位寄存器单元10的全局复位。
需要说明的是，在图7中第二十晶体管M20的第二极和第一电压端VSS1连接，本公开的实施例包括但不限于此，例如，第二十晶体管M20的第二极还可以和第二电压端VSS2、第三电压端VSS3、第四电压端VSS4、第五电压端VSS5以及第六电压端VSS6中的任意一个连接，以接收直流低电平信号。
下面结合图12、图13以及图14所示的信号仿真图对图4和图6所示的示例进行进一步说明，图12为图4所示的移位寄存器单元10在不包括第一电容C1的情形下(即不设置耦合电路400的情形下)的信号仿真图，图13为图4所示的移位寄存器单元10(耦合电路400包括第一电容C1)的信号仿真图，图14为图6所示的移位寄存器单元10(耦合电路400包括第一电容C1和第一晶体管M1)的信号仿真图。
在设置耦合电路400的情形下，从图13和图14可以看出，当控制节点H为高电平、且第三时钟信号端CLKC提供的第三时钟信号为高电平时，控制节点H的电平被进一步耦合上拉，使得对第一节点Q的充电更充分(即第一节点Q的电位更高)，从而可以避免发生输出异常。
另外，如图13所示，在耦合电路400仅包括第一电容C1而不包括第一晶体管M1的情形下，当控制节点H变为低电平、且第三时钟信号端CLKC提供的第三时钟信号为高电平时，该高电平会通过第一电容C1对控制节点H耦合上拉(如图13中的虚线椭圆所示)，从而在控制节点H上引入了噪声。
如图14所示，在耦合电路400包括第一电容C1和第一晶体管M1的情形下，当控制节点H变为低电平时，会使得第一晶体管M1关闭，所以即使此时第三时钟信号端CLKC提供的第三时钟信号为高电平，该高电平也不能 通过第一电容C1对控制节点H耦合上拉(参考图6所示的移位寄存器单元)，即不会在控制节点H上引入噪声。
如图8所示，本公开的一些实施例还提供一种移位寄存器单元10，图8中所示的移位寄存器单元10和图6中所示的移位寄存器单元10相比，输出电路300还可以包括第十六晶体管M16，相应地，降噪电路600还可以包括第十七晶体管M17。
如图8所示，第十六晶体管M16的栅极和第一节点Q连接，第十六晶体管M16的第一极和第五时钟信号端CLKE连接以接收第五时钟信号，第十六晶体管M16的第二极和另一个像素信号输出端OUT2连接。例如，当第一节点Q的电位为高电平时，第十六晶体管M16导通，从而将第五时钟信号输出至像素信号输出端OUT2。例如，在一些实施例中，第五时钟信号端CLKE输入的第五时钟信号可以配置为和第四时钟信号端CLKD输入的第四时钟信号相同；又例如，在另一些实施例中，第五时钟信号可以与第四时钟信号不同，从而使得像素信号输出端OUT和OUT2分别可以输出不同的信号，以提高驱动能力。
如图8所示，第十七晶体管M17的栅极和第二节点QB连接，第十七晶体管M17的第一极和像素信号输出端OUT2连接，第十七晶体管M17的第二极和第六电压端VSS6连接。例如，当第二节点QB的电位为高电平时，第十七晶体管M17导通，从而可以利用第六电压端VSS6对像素信号输出端OUT2进行降噪。需要说明的是，第十七晶体管M17的第二极还可以配置为和其它信号端连接，只要可以实现对像素信号输出端OUT2下拉降噪即可，本公开的实施例对此不作限定。
尽管以上仅示出了移位寄存器单元包括两个、三个输出端的示例，本领域技术人员可以理解，根据本公开的描述，可以根据实际情况设置更多个输出端，上述示例不应构成对本公开保护范围的限制。
如前所述，在本公开的实施例提供的移位寄存器单元10中，可以利用第二电容C2维持控制节点H处的电位，利用第三电容C3维持第一节点Q处的电位。第二电容C2和/或第三电容C3可以是通过工艺制程制作的电容器件，例如通过制作专门的电容电极来实现电容器件，该电容的各个电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现，或者第二电容C2和/或第三电容C3也可以通过各个器件之间的寄生电容实现。第二电容C2和/ 或第三电容C3的连接方式不局限于上面描述的方式，也可以为其他适用的连接方式，只要能存储写入到控制节点H或第一节点Q的电平即可。
当第一节点Q和/或控制节点H的电位维持在高电平时，存在一些晶体管(例如第二晶体管M2、第十五晶体管M15、第四晶体管M4、第五晶体管M5、第十一晶体管M11以及第十四晶体管M14)的第一极连接第一节点Q或控制节点H，而第二极连接低电平信号。即使当这些晶体管的栅极输入的是非导通信号的情况下，由于其第一极和第二极之间存在电压差，也可能出现漏电的情况，从而使得移位寄存器单元10中对于第一节点Q和/或控制节点H的电位维持的效果变差。
例如，如图6所示，以控制节点H为例，第二晶体管M2的第一极和消隐输入信号端STU1连接，第二极和控制节点H连接。当控制节点H处于高电平，而消隐输入信号端STU1输入的信号为低电平时，控制节点H可能会通过第二晶体管M2漏电。
针对上述问题，如图9所示，本公开的一些实施例提供了一种用于防漏电的移位寄存器单元10。该移位寄存器单元10与图6中的移位寄存器单元10的区别在于增加了第二防漏电晶体管M2_b、第四防漏电晶体管M4_b、第五防漏电晶体管M5_b、第十一防漏电晶体管M11_b、第十四防漏电晶体管M14_b、第十五防漏电晶体管M15_b、第十八晶体管M18以及第十九晶体管M19。下面以第二防漏电晶体管M2_b为例对防漏电的工作原理进行说明。
第二防漏电晶体管M2_b的栅极和第二时钟信号端CLKB连接，第二防漏电晶体管M2_b的第一极和第十八晶体管M18的第二极连接，第二防漏电晶体管M2_b的第二极和控制节点H连接。第十八晶体管M18的栅极和控制节点H连接，第十八晶体管M18的第一极和第九电压端VA连接以接收高电平的第九电压。当控制节点H处于高电平时，第十八晶体管M18在控制节点H的电平的控制下导通，从而可以将第九电压端VA输入的高电平信号输入到第二防漏电晶体管M2_b的第一极，使得第二防漏电晶体管M2_b的第一极和第二极都处于高电平，从而可以防止控制节点H处的电荷通过第二防漏电晶体管M2_b漏电。此时，由于第二防漏电晶体管M2_b的栅极和第二晶体管M2的栅极连接，所以第二晶体管M2和第二防漏电晶体管M2_b的结合可以实现与前述第二晶体管M2相同的效果，同时具有防漏电的效果。
类似地，第十五防漏电晶体管M15_b结合第十八晶体管M18可以防止控制节点H处的电荷通过第十五防漏电晶体管M15_b和第十五晶体管M15漏电。类似地，第四防漏电晶体管M4_b、第五防漏电晶体管M5_b、第十一防漏电晶体管M11_b以及第十四防漏电晶体管M14_b可以分别结合第十九晶体管M19实现防漏电结构，从而可以防止第一节点Q处的电荷发生漏电。防止第一节点Q发生漏电的工作原理和上述防止控制节点H发生漏电的工作原理相同，这里不再赘述。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)，关闭电压为高电平电压(例如，5V、10V或其他合适的电压)；当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其他合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)。
另外，需要说明的是，本公开的实施例中提供的移位寄存器单元10中采用的晶体管均是以N型晶体管为例进行说明的，本公开的实施例包括但不限于此，例如移位寄存器单元10中的至少部分晶体管也可以采用P型晶体管。
本公开的一些实施例提供一种栅极驱动电路20，如图10所示，该栅极驱动电路20包括多个级联的移位寄存器单元10，其中任意一个或多个移位寄存器单元10可以采用本公开的实施例提供的移位寄存器单元10的结构或其变型。需要说明的是，图10中仅示意性的示出了栅极驱动电路20的前四级移位寄存器单元(A1、A2、A3和A4)。
如图10所示，栅极驱动电路20还包括第一子时钟信号线CLK_1、第二子时钟信号线CLK_2、第三子时钟信号线CLK_3和第四子时钟信号线CLK_4。在移位寄存器单元和第一时钟信号端CLKA以及第四时钟信号端CLKD连接的情形下，第2n-1级移位寄存器单元和第一子时钟信号线CLK_1 连接以接收第一时钟信号，例如，通过第一时钟信号端CLKA和第一子时钟信号线CLK_1连接；第2n-1级移位寄存器单元和第三子时钟信号线CLK_3连接以接收第四时钟信号，例如，通过第四时钟信号端CLKD和第三子时钟信号线CLK_3连接。第2n级移位寄存器单元和第二子时钟信号线CLK_2连接以接收第一时钟信号，例如，通过第一时钟信号端CLKA和第二子时钟信号线CLK_2连接；第2n级移位寄存器单元和第四子时钟信号线CLK_4连接以接收第四时钟信号，例如，通过第四时钟信号端CLKD和第四子时钟信号线CLK_4连接；n为大于0的整数。
如图10所示，栅极驱动电路20还可以包括第五子时钟信号线CLK_5、第六子时钟信号线CLK_6和第七子时钟信号线CLK_7。在移位寄存器单元和第二时钟信号端CLKB、第三时钟信号端CLKC以及全局复位信号端TRST连接的情形下，第2n-1级移位寄存器单元和第五子时钟信号线CLK_5连接以接收第二时钟信号，例如，通过第二时钟信号端CLKB和第五子时钟信号线CLK_5连接；第2n-1级移位寄存器单元和第六子时钟信号线CLK_6连接以接收第三时钟信号，例如，通过第三时钟信号端CLKC和第六子时钟信号线CLK_6连接。第2n级移位寄存器单元和第六子时钟信号线CLK_6连接以接收第二时钟信号，例如，通过第二时钟信号端CLKB和第六子时钟信号线CLK_6连接；第2n级移位寄存器单元和第五子时钟信号线CLK_5连接以接收第三时钟信号，例如，通过第二时钟信号端CLKB和第五子时钟信号线CLK_5连接。每一级移位寄存器单元和第七子时钟信号线CLK_7连接以接收全局复位信号，例如，通过全局复位信号端TRST和第七子时钟信号线CLK_7连接；n为大于0的整数。
如图10所示，除了第一级移位寄存器单元外，其余各级移位寄存器单元的消隐输入信号端STU1以及显示输入信号端STU2和上一级移位寄存器单元的移位信号输出端CR连接；除最后一级移位寄存器单元外，其余各级移位寄存器单元的显示复位信号端STD和下一级移位寄存器单元的移位信号输出端CR连接。
图11示出了图10所示的栅极驱动电路20工作时的信号时序图。在图11中，H<1>和H<2>分别表示栅极驱动电路20中第一级和第二级移位寄存器单元中的控制节点H，Q<1>和Q<2>分别表示栅极驱动电路20中第一级和第二级移位寄存器单元中的第一节点Q。OUT<1>(CR<1>)和OUT<2> (CR<2>)分别表示栅极驱动电路20中的第一级和第二级移位寄存器单元中的像素信号输出端OUT(移位信号输出端CR)。1F、2F、3F和4F分别表示第一帧、第二帧、第三帧以及第四帧。DS表示一帧中的显示时段，BL表示一帧中的消隐时段。需要说明的是，图11中的STU1和STU2分别表示第一级移位寄存器单元中的消隐输入信号端和显示输入信号端，STD表示最后一级移位寄存器单元中的显示复位信号端。
另外，需要说明的是，如图11所示，在第一帧1F、第二帧2F、第三帧3F以及第四帧4F中，是以第七电压端CLKM输入低电平而第八电压端CLKN输入高电平为例进行示意的，但本公开的实施例不限于此。如上所述，第七电压端CLKM和第八电压端CLKN可以被配置为交替输入高电平，即在有的帧中也可以使得第七电压端CLKM输入高电平而第八电压端CLKN输入低电平。图11所示的信号时序图中的信号电平只是示意性的，不代表真实电平值。
下面结合图11中的信号时序图，对图10中所示的栅极驱动电路20的工作原理进行说明，例如，图10中所示的栅极驱动电路20中的移位寄存器单元可以采用图6中所示的移位寄存器单元。
在第一帧1F开始前，第七子时钟信号线CLK_7提供高电平，由于每一级移位寄存器单元的全局复位信号端TRST均和第七子时钟信号线CLK_7连接，所以使得每一级移位寄存器单元中的第十五晶体管M15导通，从而可以对每一级移位寄存器单元中的控制节点H进行复位，以实现全局复位。
由于第七电压端CLKM输入高电平，第八晶体管M8导通，使得第二节点QB被充电至高电平。第二节点QB的高电平使得第十一晶体管M11导通，从而将第一节点Q下拉至低电平。
在第一帧1F的显示时段DS中，对第一级的移位寄存器单元的工作过程描述如下。
在第一阶段1中，第一级移位寄存器单元的显示输入信号端STU2输入高电平，同时由于第一时钟信号端CLKA(与第一子时钟信号线CLK_1连接)输入高电平，第五晶体管M5导通，所以显示输入信号端STU2输入的高电平可以通过第五晶体管M5对第一节点Q<1>进行充电，使得第一节点Q<1>被上拉至高电平并被第三电容C3保持。第六晶体管M6和第七晶体管M7在第一节点Q<1>的控制下导通，但由于第四时钟信号端CLKD(与第三 子时钟信号线CLK3连接)在此阶段输入低电平信号，所以移位信号输出端CR<1>和像素信号输出端OUT<1>均输出低电平信号。在此阶段，完成对第一节点Q<1>的预充电。
在第二阶段2中，第四时钟信号端CLKD输入高电平信号，第一节点Q<1>的电位由于自举效应而进一步被拉高，所以第六晶体管M6和第七晶体管M7保持导通，从而移位信号输出端CR<1>和像素信号输出端OUT<1>均输出高电平信号。例如，从移位信号输出端CR<1>输出的高电平信号可以用于上下级移位寄存器单元的扫描移位，而从像素信号输出端OUT<1>输出的高电平信号可以用于驱动显示面板中的子像素单元进行显示。
在第三阶段3中，由于第一级移位寄存器单元的显示复位信号端STD和第二级移位寄存器单元的移位信号输出端CR<2>连接，此时第二级移位寄存器单元的移位信号输出端CR<2>输出高电平，所以第一极移位寄存器单元的显示复位信号端STD输入高电平，第十四晶体管M14导通，第一节点Q<1>被下拉至低电平，完成对第一节点Q<1>的复位。由于第一节点Q<1>为低电平，第十晶体管M10关闭，同时第八电压端CLKN输入的高电平可以对第二节点QB进行充电，第二节点QB被充电至高电平，所以第十一晶体管M11导通，以进一步对第一节点Q<1>进行降噪。同时第十二晶体管M12和第十三晶体管M13也导通，移位信号输出端CR<1>和像素信号输出端OUT<1>被下拉至低电平，完成复位。
第一级移位寄存器单元驱动显示面板中第一行的子像素完成显示后，依次类推，第二级、第三级等移位寄存器单元逐行驱动显示面板中的子像素单元完成一帧的显示驱动。至此，第一帧的显示时段结束。
在第一帧1F的消隐时段BL中，对第一级的移位寄存器单元的工作过程描述如下。
在第四阶段4中，第一级移位寄存器单元的消隐输入信号端STU1输入高电平，同时由于第二时钟信号端CLKB(与第五子时钟信号线CLK_5连接)输入高电平，第二晶体管M2导通，所以消隐输入信号端STU1输入的高电平可以通过第二晶体管M2对控制节点H<1>进行充电，使得控制节点H<1>被上拉至高电平并被第二电容C2保持。由于第八电压端CLKN此时输入高电平，第二节点QB被该高电平充电至高电平，所以第十一晶体管M11导通，使得第一节点Q<1>被下拉至低电平。另外，在此阶段第三时钟信号端CLKC (与第六子时钟信号线CLK_6连接)输入低电平，所以第四晶体管M4保持关闭状态，第四晶体管M4隔离了控制节点H<1>对第一节点Q<1>的影响，使得第一节点Q<1>保持为低电平。在此阶段，完成对控制节点H的预充电。
在第二帧2F的显示时段DS中，栅极驱动电路20重复和第一帧1F的显示时段DS相同的操作，这里不再赘述。
在第二帧2F的消隐时段BL中，对栅极驱动电路20的工作过程描述如下。
在第五阶段5中，对于第一级移位寄存器单元，控制节点H<1>由于第二电容C2的存储而保持高电平，第三晶体管M3导通。第三时钟信号端CLKC(与第六子时钟信号线CLK_6连接)输入高电平，使得第四晶体管M4导通，所以第三时钟信号端CLKC输入的高电平可以通过第三晶体管M3和第四晶体管M4对第一节点Q<1>进行充电，将第一节点Q<1>上拉至高电平。同时由于控制节点H<1>为高电平，第一晶体管M1导通，第三时钟信号端CLKC输入的高电平可以通过第一电容C1对控制节点H<1>进行耦合上拉，使得控制节点H<1>的电位被进一步拉高。通过对控制节点H<1>的耦合上拉，可以使得第三晶体管M3导通的更充分，从而第三时钟信号端CLKC输入的高电平对第一节点Q的充电更充分。
由于第一节点Q为高电平，第六晶体管M6和第七晶体管M7导通，第四时钟信号端CLKD(与第三子时钟信号线CLK_3连接)输入的高电平可以输出至移位信号输出端CR<1>和像素信号输出端OUT<1>。例如，移位信号输出端CR<1>输出的信号可以用于上下级移位寄存器单元的扫描移位，像素信号输出端OUT输出的信号可以用于驱动显示面板中子像素单元中的感测晶体管，以实现外部补偿。
同时，在第五阶段5中，由于第二级移位寄存器单元的第二时钟信号端CLKB与第六子时钟信号线CLK6连接，第二级移位寄存器单元的消隐输入信号端STU1与第一级移位寄存器单元的移位信号输出端CR<1>连接，所以第二级移位寄存器单元中的第二晶体管M2导通，从而使得第二级移位寄存器单元中的控制节点H<2>被上拉至高电平并保持。
在第六阶段6中，对于第一级移位寄存器单元，由于第四时钟信号端CLKD(和第三子时钟信号线CLK_3连接)从高电平变为低电平，所以移位信号输出端CR<1>输出的信号从高电平变为低电平，通过第三电容C3的耦 合作用，第一节点Q<1>的电位被拉低。当第一节点Q<1>变为低电平时，第八电压端CLKN输入的高电平将第二节点QB充电至高电平，第二节点QB的高电平使得第十一晶体管M11导通，进一步拉低第一节点Q<1>的电平，以完成第一节点Q<1>的复位。
在第三帧3F的显示时段DS中，栅极驱动电路20重复和第一帧1F的显示时段DS相同的操作，这里不再赘述。
在第三帧3F的消隐时段BL中，对栅极驱动电路20的工作过程描述如下。
在第七阶段7中，对于第一级移位寄存器单元，第二时钟信号端CLKB(与第五子时钟信号线CLK_5连接)输入高电平，第二晶体管M2导通，但由于在此阶段消隐输入信号端STU1为低电平，所以控制节点H可以通过第二晶体管M2放电至低电平，完成复位。
在第七阶段7中对第二级移位寄存器单元的操作可以参考在第五阶段7中对第一级移位寄存器单元的对应操作，这里不再赘述。
至此，第三帧3F的驱动时序结束。后续在第四帧、第五帧等更多阶段中对栅极驱动电路的驱动可以参考上述描述，这里不再赘述。
如上所述，通过设置耦合电路400可以在控制节点H为高电平时，对控制节点H进一步耦合上拉，从而在一帧的消隐时段中对第一节点Q的充电更充分，以避免发生输出异常。
本公开的实施例还提供一种显示装置1，如图15所示，该显示装置1包括本公开实施例提供的栅极驱动电路20。该显示装置1还包括显示面板40，显示面板40包括由多个子像素单元410构成的阵列。例如，该显示装置1还可以包括数据驱动电路30。数据驱动电路30用于提供数据信号至像素阵列；栅极驱动电路20用于提供驱动信号至像素阵列，例如该驱动信号可以驱动子像素单元410中的扫描晶体管和感测晶体管。数据驱动电路30通过数据线DL与子像素单元410电连接，栅极驱动电路20通过栅线GL与子像素单元410电连接。
需要说明的是，本实施例中的显示装置1可以为：液晶面板、液晶电视、显示器、OLED面板、OLED电视、电子纸显示装置、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开的实施例提供的显示装置1的技术效果可以参考上述实施例中关 于栅极驱动电路20的相应描述，这里不再赘述。
本公开的实施例还提供一种驱动方法，可以用于驱动本公开的实施例提供的移位寄存器单元10，该驱动方法包括：在一帧的消隐时段，使得耦合电路400响应于消隐信号对控制节点H的电平进行耦合控制，例如进行耦合上拉，消隐输入电路100将消隐信号输入到第一节点Q，输出电路在300第一节点Q的电平的控制下输出复合输出信号。
本公开的实施例还提供一种驱动方法，可以用于驱动本公开的实施例提供的移位寄存器单元10，该驱动方法包括如下操作。
在第一帧的显示时段，包括：显示输入电路200响应于第一时钟信号将显示信号输入到第一节点Q，输出电路300在第一节点Q的电平的控制下输出第一输出信号。
在第一帧的消隐时段，包括：消隐输入电路100将消隐输入信号输入到控制节点H。
在第二帧的消隐时段，包括：耦合电路400响应于消隐信号对控制节点H的电平进行耦合控制，例如进行耦合上拉，消隐输入电路100将消隐信号输入到第一节点Q，输出电路300在第一节点Q的电平的控制下输出第二输出信号。复合输出信号包括第一输出信号和第二输出信号。
需要说明的是，关于本公开的实施例提供的驱动方法的详细描述和技术效果可以参考本公开的实施例中对于移位寄存器单元10和栅极驱动电路20的工作原理的描述，这里不再赘述。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以权利要求的保护范围为准。

Claims (19)

  1. 一种移位寄存器单元，包括消隐输入电路、显示输入电路、输出电路和耦合电路；其中，
    所述消隐输入电路被配置为将消隐输入信号输入到控制节点并在一帧的消隐时段将消隐信号输入到第一节点；
    所述显示输入电路被配置为响应于第一时钟信号在一帧的显示时段将显示信号输入到所述第一节点；
    所述输出电路被配置为在所述第一节点的电平的控制下，将复合输出信号输出至输出端；
    所述耦合电路与所述控制节点电连接，且被配置为响应于所述消隐信号对所述控制节点的电平进行耦合控制。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述耦合电路包括第一电容；
    所述第一电容的第一极和第三时钟信号端连接以接收第三时钟信号作为所述消隐信号，所述第一电容的第二极和所述控制节点连接。
  3. 根据权利要求1所述的移位寄存器单元，其中，所述耦合电路包括第一电容和第一晶体管；
    所述第一晶体管的栅极和所述控制节点连接，所述第一晶体管的第一极和第三时钟信号端连接以接收第三时钟信号作为所述消隐信号，所述第一晶体管的第二极和所述第一电容的第一极连接，所述第一电容的第二极和所述控制节点连接。
  4. 根据权利要求1所述的移位寄存器单元，其中，所述消隐输入电路包括：
    充电子电路，被配置为响应于第二时钟信号将所述消隐输入信号输入到所述控制节点；
    存储子电路，被配置为存储所述充电子电路输入的所述消隐输入信号；
    隔离子电路，被配置为在所述控制节点的电平和第三时钟信号的控制下，将所述消隐信号输入到所述第一节点。
  5. 根据权利要求4所述的移位寄存器单元，其中，
    所述充电子电路包括第二晶体管，所述第二晶体管的栅极和第二时钟信号端连接以接收所述第二时钟信号，所述第二晶体管的第一极和消隐输入信号端连接以接收所述消隐输入信号，所述第二晶体管的第二极和所述控制节点连接；
    所述存储子电路包括第二电容，所述第二电容的第一极和所述控制节点连接，所述第二电容的第二极和第一电压端连接以接收第一电压；
    所述隔离子电路包括第三晶体管和第四晶体管，所述第三晶体管的栅极和所述控制节点连接，所述第三晶体管的第一极和第三时钟信号端连接以接收所述第三时钟信号作为所述消隐信号，所述第三晶体管的第二极和所述第四晶体管的第一极连接，所述第四晶体管的栅极和所述第三时钟信号端连接以接收所述第三时钟信号，所述第四晶体管的第二极和所述第一节点连接。
  6. 根据权利要求1-5任一所述的移位寄存器单元，其中，所述显示输入电路包括第五晶体管；
    所述第五晶体管的栅极和第一时钟信号端连接以接收所述第一时钟信号，所述第五晶体管的第一极和显示输入信号端连接以接收所述显示信号，所述第五晶体管的第二极和所述第一节点连接。
  7. 根据权利要求1-6任一所述的移位寄存器单元，其中，所述输出端包括移位信号输出端和像素信号输出端，所述移位信号输出端和所述像素信号输出端输出所述复合输出信号，所述输出电路包括第六晶体管、第七晶体管和第三电容；
    所述第六晶体管的栅极和所述第一节点连接，所述第六晶体管的第一极和第四时钟信号端连接以接收第四时钟信号作为所述复合输出信号，所述第六晶体管的第二极和所述移位信号输出端连接；
    所述第七晶体管的栅极和所述第一节点连接，所述第七晶体管的第一极和所述第四时钟信号端连接以接收所述第四时钟信号作为所述复合输出信号，所述第七晶体管的第二极和所述像素信号输出端连接；
    所述第三电容的第一极和所述第一节点连接，所述第三电容的第二极和所述第六晶体管的第二极连接。
  8. 根据权利要求7所述的移位寄存器单元，还包括降噪电路和控制电路；其中，
    所述控制电路被配置为在所述第一节点的电平的控制下，对第二节点的电平进行控制；
    所述降噪电路被配置为在所述第二节点的电平的控制下，对所述第一节点、所述移位信号输出端和所述像素信号输出端进行降噪。
  9. 根据权利要求8所述的移位寄存器单元，其中，所述控制电路包括第八晶体管、第九晶体管和第十晶体管；
    所述第八晶体管的栅极和第一极连接且被配置为和第七电压端连接以接收第七电压，所述第八晶体管的第二极和所述第二节点连接；
    所述第九晶体管的栅极和第一极连接且被配置为和第八电压端连接以接收第八电压，所述第九晶体管的第二极和所述第二节点连接；
    所述第十晶体管的栅极和所述第一节点连接，所述第十晶体管的第一极和所述第二节点连接，所述第十晶体管的第二极和第四电压端连接以接收第四电压。
  10. 根据权利要求8或9所述的移位寄存器单元，其中，所述降噪电路包括第十一晶体管、第十二晶体管和第十三晶体管；
    所述第十一晶体管的栅极和所述第二节点连接，所述第十一晶体管的第一极和所述第一节点连接，所述第十一晶体管的第二极和第三电压端连接以接收第三电压；
    所述第十二晶体管的栅极和所述第二节点连接，所述第十二晶体管的第一极和所述移位信号输出端连接，所述第十二晶体管的第二极和第五电压端连接以接收第五电压；
    所述第十三晶体管的栅极和所述第二节点连接，所述第十三晶体管的第一极和所述像素信号输出端连接，所述第十三晶体管的第二极和第六电压端连接以接收第六电压。
  11. 根据权利要求1-10任一所述的移位寄存器单元，还包括显示复位电路，其中，所述显示复位电路被配置为响应于显示复位信号对所述第一节点进行复位。
  12. 根据权利要求11所述的移位寄存器单元，其中，所述显示复位电路包括第十四晶体管；
    所述第十四晶体管的栅极和显示复位信号端连接以接收所述显示复位信号，所述第十四晶体管的第一极和所述第一节点连接，所述第十四晶 体管的第二极和第二电压端连接以接收第二电压。
  13. 根据权利要求1-4任一所述的移位寄存器单元，还包括全局复位电路，其中，所述全局复位电路被配置为响应于全局复位信号对所述控制节点进行复位。
  14. 根据权利要求13所述的移位寄存器单元，其中，所述全局复位电路包括第十五晶体管；
    所述第十五晶体管的栅极和全局复位信号端连接以接收所述全局复位信号，所述第十五晶体管的第一极和所述控制节点连接，所述第十五晶体管的第二极和第一电压端连接以接收第一电压。
  15. 一种栅极驱动电路，包括多个级联的如权利要求1-14任一所述的移位寄存器单元。
  16. 根据权利要求15所述的栅极驱动电路，还包括第一子时钟信号线、第二子时钟信号线、第三子时钟信号线和第四子时钟信号线；其中，
    第2n-1级移位寄存器单元和所述第一子时钟信号线连接以接收第一时钟信号，第2n-1级移位寄存器单元和所述第三子时钟信号线连接以接收第四时钟信号；
    第2n级移位寄存器单元的和所述第二子时钟信号线连接以接收第一时钟信号，第2n级移位寄存器单元的和所述第四子时钟信号线连接以接收第四时钟信号；
    n为大于0的整数。
  17. 根据权利要求16所述的栅极驱动电路，还包括第五子时钟信号线、第六子时钟信号线和第七子时钟信号线；其中，
    第2n-1级移位寄存器单元和所述第五子时钟信号线连接以接收第二时钟信号，第2n-1级移位寄存器单元和所述第六子时钟信号线连接以接收第三时钟信号；
    第2n级移位寄存器单元和所述第六子时钟信号线连接以接收第二时钟信号，第2n级移位寄存器单元和所述第五子时钟信号线连接以接收第三时钟信号；
    每一级移位寄存器单元和所述第七子时钟信号线连接以接收全局复位信号；
    n为大于0的整数。
  18. 一种显示装置，包括如权利要求15-17任一所述的栅极驱动电路。
  19. 一种如权利要求1-14任一所述的移位寄存器单元的驱动方法，包括：
    在一帧的消隐时段，使得所述耦合电路响应于所述消隐信号对所述控制节点的电平进行耦合控制，所述消隐输入电路将所述消隐信号输入到所述第一节点，所述输出电路在所述第一节点的电平的控制下输出所述复合输出信号。
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