WO2020147377A1 - 移位寄存器单元、栅极驱动电路、显示装置及驱动方法 - Google Patents

移位寄存器单元、栅极驱动电路、显示装置及驱动方法 Download PDF

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Publication number
WO2020147377A1
WO2020147377A1 PCT/CN2019/115226 CN2019115226W WO2020147377A1 WO 2020147377 A1 WO2020147377 A1 WO 2020147377A1 CN 2019115226 W CN2019115226 W CN 2019115226W WO 2020147377 A1 WO2020147377 A1 WO 2020147377A1
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WIPO (PCT)
Prior art keywords
node
transistor
control
circuit
reset
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PCT/CN2019/115226
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English (en)
French (fr)
Inventor
冯雪欢
李永谦
袁粲
李蒙
丁泽华
袁志东
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Priority to US16/766,450 priority Critical patent/US11238805B2/en
Publication of WO2020147377A1 publication Critical patent/WO2020147377A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared

Definitions

  • the embodiments of the present disclosure relate to a shift register unit, a gate driving circuit, a display device, and a driving method.
  • the gate drive circuit is currently generally integrated in the gate drive chip (GATE IC).
  • GATE IC gate drive chip
  • the area of the chip is the main factor that affects the cost of the chip. How to effectively reduce the area of the chip is a key consideration for technical developers.
  • At least one embodiment of the present disclosure provides a shift register unit including a first subunit and an anti-leakage circuit.
  • the first subunit includes a first input circuit and a first output circuit.
  • the first input circuit is configured to control the level of the first node in response to a first input signal
  • the first output circuit is configured to provide at the output terminal under the control of the level of the first node Output signal
  • the leakage prevention circuit is connected to the first node and the first voltage terminal, and is configured to control the level of the leakage prevention node under the control of the level of the first node, so that the A conductive path is formed between the leakage prevention node and the first voltage terminal, and the circuit connected between the first node and the leakage prevention node is cut off.
  • the leakage prevention circuit includes a first leakage prevention electronic circuit and a second leakage prevention electronic circuit.
  • the first leakage-proof electronic circuit is connected to the first node and the leakage-proof node, and is configured to control the level of the leakage-proof node under the control of the level of the first node;
  • the second anti-leakage electronic circuit is connected to the anti-leakage node and the first voltage terminal, and the second anti-leakage electronic circuit is configured to be at the level of the anti-leakage node or the first node. Under the control of the level, a conductive path is formed between the leakage prevention node and the first voltage terminal.
  • the first leakage prevention electronic circuit includes a first leakage prevention transistor
  • the second leakage prevention electronic circuit includes a second leakage prevention transistor
  • the gate of the leakage prevention transistor is connected to the first node
  • the first pole of the first leakage prevention transistor is configured to receive a second voltage
  • the second pole of the first leakage prevention transistor is connected to the leakage prevention node Connected
  • the gate and the first pole of the second leakage prevention transistor are configured to be connected to the leakage prevention node
  • the second pole of the second leakage prevention transistor is configured to be connected to the first voltage terminal Receiving the first voltage.
  • the first leakage prevention electronic circuit includes a first leakage prevention transistor
  • the second leakage prevention electronic circuit includes a third leakage prevention transistor
  • the first The gate of the leakage prevention transistor is connected to the first node, the first pole of the first leakage prevention transistor is configured to receive a second voltage, and the second pole of the first leakage prevention transistor is connected to the leakage prevention node Connected
  • the gate of the third leakage prevention transistor is connected to the first node, the first pole of the third leakage prevention transistor is connected to the leakage prevention node, and the second pole of the third leakage prevention transistor It is configured to be connected to the first voltage terminal to receive the first voltage.
  • the shift register unit provided by an embodiment of the present disclosure further includes a blanking input subunit, and the blanking input subunit is connected to the first node and is configured to receive a selection control signal and perform control over the first node. The level of the node is controlled.
  • the blanking input subunit includes a selection control circuit, a third input circuit, and a first transmission circuit; the selection control circuit is configured to respond to the The selection control signal uses the second input signal to control the level of the third node and maintains the level of the third node; the third input circuit is configured to be under the control of the level of the third node Transmitting the first clock signal to the fourth node; the first transmission circuit is electrically connected to the first node, the fourth node, and the leakage prevention node, and is configured to respond to the first clock signal The level of the first node and the level of the leakage prevention node are controlled.
  • the shift register unit provided by an embodiment of the present disclosure further includes a second subunit.
  • the second subunit includes a second input circuit and a second output circuit, the second input circuit is configured to control the level of the second node in response to the first input signal, and the second output circuit Is configured to output a second output signal under the control of the level of the second node;
  • the blanking input subunit further includes a second transmission circuit, the second transmission circuit and the second node, and the The leakage prevention node is electrically connected, and is configured to transmit the level of the leakage prevention node to the second node in response to the first clock signal.
  • the first transmission circuit includes a first transmission transistor and a second transmission transistor
  • the second transmission circuit includes a third transmission transistor
  • the gate of the transistor is configured to receive the first clock signal, the first pole of the first transfer transistor is connected to the fourth node, and the second pole of the first transfer transistor is connected to the leakage prevention node
  • the gate of the second transfer transistor is configured to receive the first clock signal, the first pole of the second transfer transistor is connected to the leakage prevention node, and the second pole of the second transfer transistor and The first node is connected
  • the gate of the third transfer transistor is configured to receive the first clock signal, the first pole of the third transfer transistor is connected to the leakage prevention node, and the third transfer The second pole of the transistor is connected to the second node.
  • the first input circuit includes a first input transistor and a second input transistor
  • the second input circuit includes a third input transistor
  • the gate and the first electrode of the transistor are configured to receive the first input signal, the second electrode of the first input transistor is connected to the anti-leakage node
  • the gate of the second input transistor is configured to receive
  • the first pole of the second input transistor is connected to the anti-leakage node
  • the second pole of the second input transistor is connected to the first node
  • the gate is configured to receive the first input signal, the first pole of the third input transistor is connected to the leakage prevention node, and the second pole of the third input transistor is connected to the second node.
  • the second input circuit further includes a fourth input transistor; the gate and the first electrode of the fourth input transistor are configured to receive the first To input a signal, the second pole of the fourth input transistor is connected to the leakage prevention node.
  • the first subunit further includes a first control circuit, a first reset circuit, a second reset circuit, a shift signal output terminal, and a first output signal terminal
  • the second subunit also includes a second control circuit, a third reset circuit, a fourth reset circuit, and a second output signal terminal;
  • the output signal includes a shift signal and a first output signal, and the output terminal includes the The shift signal output terminal and the first output signal terminal, the shift signal output terminal is configured to output the shift signal, and the first output signal terminal is configured to output the first output signal;
  • the second output signal terminal is configured to output the second output signal;
  • the first control circuit is configured to control the level of the fifth node under the control of the level of the first node and the third voltage.
  • the first reset circuit is configured to reset the first node, the shift signal output terminal, and the first output signal terminal under the control of the level of the fifth node;
  • the second reset circuit is configured to reset the first node, the shift signal output terminal, and the first output signal terminal under the control of the level of the sixth node;
  • the second control The circuit is configured to control the level of the sixth node under the control of the level of the second node and the fourth voltage;
  • the third reset circuit is configured to control the level of the sixth node Under the control of the second node and the second output signal terminal;
  • the fourth reset circuit is configured to, under the control of the level of the fifth node, reset the second node and The second output signal terminal is reset.
  • the first subunit further includes a third control circuit, a fourth control circuit, and a common control circuit
  • the second subunit further includes a fifth control circuit.
  • a sixth control circuit the third control circuit is connected to the fifth node and the common control node, and is configured to electrically connect the fifth node and the common control node in response to the first clock signal
  • the common control circuit is electrically connected to the common control node and the first voltage terminal, and is configured to make the common control node and the first voltage under the control of the level of the third node
  • the fourth control circuit is electrically connected to the fifth node and the first voltage terminal, and is configured to control the level of the fifth node in response to the first input signal
  • the fifth control circuit is connected to the sixth node and the common control node, and is configured to electrically connect the sixth node and the common control node in response to the first clock signal, and the first The sixth control circuit is electrically connected to the sixth node and the first voltage terminal,
  • the third control circuit includes a first control transistor
  • the fourth control circuit includes a second control transistor
  • the common control circuit includes a third control transistor.
  • the fifth control circuit includes a fourth control transistor
  • the sixth control circuit includes a fifth control transistor; the gate of the first control transistor is configured to receive the first clock signal, and the first control transistor The first pole of the transistor is connected to the fifth node, the second pole of the first control transistor is connected to the common control node; the gate of the second control transistor is configured to receive a first input signal, so The first pole of the second control transistor is connected to the fifth node, and the second pole of the second control transistor is connected to the first voltage terminal; the gate of the third control transistor is connected to the third Node connection, the first electrode of the third control transistor is connected to the common control node, the second electrode of the third control transistor is connected to the first voltage terminal; the gate of the fourth control transistor is Configured to receive the first clock signal, the first pole of the fourth control transistor is connected to
  • the first subunit further includes a third control circuit, a fourth control circuit, and a common control circuit
  • the second subunit further includes a fifth control circuit.
  • a sixth control circuit the third control circuit is connected to the third node, the fifth node, and the common control node, and is configured to make the first control circuit under the control of the level of the third node
  • the five node is electrically connected to the common control node
  • the common control circuit is electrically connected to the common control node and the first voltage terminal, and is configured to make the common control node in response to the first clock signal Is electrically connected to the first voltage terminal
  • the fourth control circuit is electrically connected to the fifth node and the first voltage terminal, and is configured to respond to the first input signal to the fifth node
  • the fifth control circuit is connected to the third node, the sixth node, and the common control node, and is configured to make all of them under the control of the level of the third node
  • the sixth node is electrically connected to
  • the third control circuit includes a sixth control transistor
  • the fourth control circuit includes a second control transistor
  • the common control circuit includes a seventh control transistor.
  • the fifth control circuit includes an eighth control transistor
  • the sixth control circuit includes a fifth control transistor; the gate of the sixth control transistor is connected to the third node, and the sixth control transistor One pole is connected to the fifth node, and the second pole of the sixth control transistor is connected to the common control node; the gate of the second control transistor is configured to receive a first input signal, and the second The first pole of the control transistor is connected to the fifth node, the second pole of the second control transistor is connected to the first voltage terminal; the gate of the seventh control transistor is configured to receive the first For a clock signal, the first pole of the seventh control transistor is connected to the common control node, and the second pole of the seventh control transistor is connected to the first voltage terminal; the gate of the eighth control transistor is connected to The third node is connected, the first pole of the eighth control transistor is connected to the
  • the first subunit further includes a fifth reset circuit and a sixth reset circuit
  • the second subunit further includes a seventh reset circuit and an eighth reset circuit.
  • the fifth reset circuit is connected to the first node and the leakage prevention node, and is configured to reset the first node in response to a display reset signal
  • the sixth reset circuit and the first node A node is connected to the leakage prevention node, and is configured to reset the first node in response to a global reset signal
  • the seventh reset circuit is connected to the second node and the leakage prevention node, and is Configured to reset the second node in response to the display reset signal
  • the eighth reset circuit is connected to the second node and the leakage prevention node, and is configured to respond to the global reset signal The second node is reset.
  • the fifth reset circuit includes a first reset transistor
  • the sixth reset circuit includes a second reset transistor
  • the seventh reset circuit includes a third reset transistor.
  • the eighth reset circuit includes a fourth reset transistor; the gate of the first reset transistor is configured to receive the display reset signal, and the first pole of the first reset transistor is connected to the first node , The second electrode of the first reset transistor is connected to the leakage prevention node; the gate of the second reset transistor is configured to receive the global reset signal, and the first electrode of the second reset transistor is connected to the The first node is connected, the second electrode of the second reset transistor is connected to the leakage prevention node; the gate of the third reset transistor is configured to receive the display reset signal, and the third reset transistor The first electrode is connected to the second node, the second electrode of the third reset transistor is connected to the leakage prevention node; the gate of the fourth reset transistor is configured to receive the global reset signal, the The first pole of the fourth reset transistor is connected to the second node, and the second pole
  • At least one embodiment of the present disclosure further provides a gate driving circuit including a plurality of cascaded shift register units as provided in the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure further provides a display device, including any gate driving circuit provided in the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure further provides a driving method of a shift register unit, including: the leakage prevention circuit controls the level of the leakage prevention node under the control of the level of the first node, so that the A conductive path is formed between the leakage prevention node and the first voltage terminal, and the circuit connected between the first node and the leakage prevention node is cut off.
  • Figure 1 is a schematic diagram of a shift register unit
  • FIG. 2 is a schematic diagram of a shift register unit provided by some embodiments of the disclosure.
  • FIG. 3 is a circuit diagram of an anti-leakage circuit provided by some embodiments of the present disclosure.
  • FIG. 4 is a circuit diagram of another leakage prevention circuit provided by some embodiments of the disclosure.
  • FIG. 5 is a schematic diagram of another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 6 is a schematic diagram of still another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 7 is a schematic diagram of still another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 8 is a circuit diagram of a blanking input subunit provided by some embodiments of the present disclosure.
  • 9A to 9D are circuit diagrams of four blanking input subunits provided by some embodiments of the present disclosure.
  • FIG. 10 is a schematic diagram of still another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 11 is a schematic diagram of still another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 12 is a schematic diagram of still another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 13 is a circuit diagram of a shift register unit provided by some embodiments of the present disclosure.
  • 14A to 14C are circuit diagrams of three first input circuits provided by some embodiments of the present disclosure.
  • 15 is a circuit diagram of another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 16 is a circuit diagram of still another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 17 is a circuit diagram of still another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 19 is a circuit diagram of still another shift register unit provided by some embodiments of the present disclosure.
  • 20 is a circuit diagram of still another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 21 is a circuit diagram of yet another shift register unit provided by some embodiments of the present disclosure.
  • FIG. 22 is a schematic diagram of a gate driving circuit provided by some embodiments of the present disclosure.
  • FIG. 23 is a signal timing diagram corresponding to the operation of the gate driving circuit shown in FIG. 22 according to some embodiments of the present disclosure.
  • 24 is a schematic diagram of another gate driving circuit provided by some embodiments of the present disclosure.
  • FIG. 25 is a signal timing diagram corresponding to the operation of the gate driving circuit shown in FIG. 24 according to some embodiments of the present disclosure.
  • FIG. 26 is a schematic diagram of a display device provided by some embodiments of the present disclosure.
  • pulse up means charging a node or an electrode of a transistor so that the level of the node or the electrode is absolutely The value increases to achieve the operation of the corresponding transistor (such as turning on); “pull-down” means to discharge a node or an electrode of a transistor, so that the absolute value of the level of the node or the electrode is reduced, thereby achieving the corresponding Operation of the transistor (e.g. off).
  • pulse-up means discharging a node or an electrode of a transistor, so that the absolute value of the level of the node or the electrode is reduced, thereby realizing the corresponding transistor Operation (for example, turn on);
  • pulse down means to charge a node or an electrode of a transistor, so that the absolute value of the level of the node or the electrode is increased, thereby realizing the operation of the corresponding transistor (for example, turning off) .
  • pulse up and pulse down will also be adjusted according to the specific type of transistor used, as long as the transistor can be controlled to achieve the corresponding switching function.
  • the current gate drive circuit used in OLED usually consists of three sub-circuits, namely the detection circuit, the display circuit and the connection circuit (OR gate circuit) that outputs the composite pulse of the two.
  • the detection circuit the display circuit
  • the connection circuit OR gate circuit
  • FIG. 1 shows a shift register unit.
  • the shift register unit includes an input circuit 610 and an output circuit 620.
  • the input circuit 610 is configured to control the level of the first node Q1 in response to the first input signal STU1
  • the output circuit 620 is configured to provide an output signal OUT at the output terminal under the control of the level of the first node Q1.
  • a gate driving circuit can be formed, and the gate driving circuit can be used to drive a display device to perform display operations.
  • the output circuit 620 can provide the output signal OUT under the control of the level of the first node Q1.
  • the output signal OUT can be provided to a row of pixels in the display panel.
  • the unit is used to drive the row of pixel units for display.
  • the reset circuit is used to reset the level of the first node Q1.
  • the reset operation causes the level of the first node Q1 to change from a high level to a low level.
  • the first node Q1 may leak through one or more of these reset circuits, that is, the first node Q1 Leakage occurs through the leakage path indicated by the dashed line in FIG. 1, which will cause the level of the first node Q1 to not be maintained at a higher level when the output circuit 620 is outputting, which may lead to deviations in the output signal OUT, and thus As a result, display failures occur in the display panel using the shift register unit as the gate drive circuit.
  • the circuit path connected to the first node Q1 that may cause leakage of the first node Q1 is called a leakage path, and the leakage path may include one or more circuits ( Or sub-circuit), for example, includes a reset circuit that performs a reset operation on the first node Q1, etc.
  • the leakage path may include one or more circuits ( Or sub-circuit), for example, includes a reset circuit that performs a reset operation on the first node Q1, etc.
  • the shift register unit includes a first subunit and an anti-leakage circuit.
  • the first subunit includes a first input circuit and a first output circuit.
  • the first input circuit is configured to control the level of the first node in response to the first input signal
  • the first output circuit is configured to provide an output signal at the output terminal under the control of the level of the first node
  • the leakage prevention circuit Connected to the first node and the first voltage terminal, and is configured to control the level of the leakage prevention node under the control of the level of the first node, so that a conductive path is formed between the leakage prevention node and the first voltage terminal, And the circuit connected between the first node and the leakage prevention node is cut off.
  • Some embodiments of the present disclosure also provide a gate driving circuit, a display device, and a driving method corresponding to the above-mentioned shift register unit.
  • the shift register unit, the gate drive circuit, the display device and the drive method provided by some embodiments of the present disclosure can prevent leakage of the first node from occurring, and avoid display on the display device using the gate drive circuit formed by the shift register unit Bad problem.
  • some embodiments of the present disclosure can also simplify the circuit structure, thereby reducing the frame size of the display device using the gate driving circuit, and improving the PPI of the display device.
  • At least one embodiment of the present disclosure provides a shift register unit 10.
  • the shift register unit 10 includes a first subunit 100 and an anti-leakage circuit 400, and the first subunit 100 includes a first input circuit. 110 and the first output circuit 120.
  • a plurality of the shift register units 10 can be cascaded to construct a gate driving circuit provided by an embodiment of the present disclosure.
  • the gate driving circuit can be used in a display device to provide a scan signal during the display of one frame of the display device .
  • the first input circuit 110 is configured to control the level of the first node Q1 in response to the first input signal STU1, for example, to charge the first node Q1.
  • the first input circuit 110 may be configured to receive the first input signal STU1 and the second voltage VDD, and the first input circuit 110 is turned on in response to the first input signal STU1, so that the second voltage VDD can be used for the first node Q1 is charging.
  • the first input circuit 110 may not receive the second voltage VDD, and directly use the first input signal STU1 to charge the first node Q1.
  • the second voltage VDD is, for example, a high level.
  • the following embodiments are the same as this, and will not be repeated.
  • the first output circuit 120 is configured to provide an output signal at the output terminal under the control of the level of the first node Q1.
  • the output signal includes a shift signal CR and a first output signal OUT1.
  • the first output circuit 120 may be configured to receive the second clock signal CLKB and the third clock signal CLKC. When the first output circuit 120 is turned on under the control of the level of the first node Q1, the second clock signal CLKB is output as the shift signal CR, and the third clock signal CLKC is output as the first output signal OUT1.
  • the shift signal CR output by the first output circuit 120 may be provided to other shift register units 10 as the first input signal STU1, thereby completing the line-by-line shift of the display scan;
  • the first output signal OUT1 output by the output circuit 120 can drive a certain row of sub-pixel units in the display panel to perform display scanning.
  • some of the shift register units 10 can be connected to a clock signal line to receive the first input signal STU1 provided by the clock signal line; Alternatively, some shift register units 10 may also receive the shift signal CR output by other stages of shift register units 10 as the first input signal STU1.
  • the signal waveforms of the shift signal CR and the first output signal OUT1 output by the first output circuit 120 may be the same or different, which is not limited in the embodiment of the present disclosure.
  • the leakage prevention circuit 400 is connected to the first node Q1 and the first voltage terminal VGL1, and is configured to control the level of the leakage prevention node OF under the control of the level of the first node Q1, so that A conductive path is formed between the leakage prevention node OF and the first voltage terminal VGL1, and the circuit connected between the first node Q1 and the leakage prevention node OF is cut off.
  • the leakage prevention circuit 400 includes a first leakage prevention electronic circuit 410 and a second leakage prevention electronic circuit 420.
  • the first leakage prevention electronic circuit 410 is connected to the first node Q1 and the leakage prevention node OF, and is configured to control the level of the leakage prevention node OF under the control of the level of the first node Q1.
  • the first anti-leakage electronic circuit 410 may be configured to receive the second voltage VDD, and the first anti-leakage electronic circuit uses the second voltage VDD to perform the level of the anti-leakage node OF under the control of the level of the first node Q1. control.
  • the second leakage prevention electronic circuit 420 is connected to the leakage prevention node OF and the first voltage terminal VGL1, and the second leakage prevention electronic circuit 420 is configured to control the level of the leakage prevention node OF or the level of the first node Q1
  • a conductive path is formed between the leakage prevention node OF and the first voltage terminal VGL1.
  • the first voltage terminal VGL1 is configured to provide a first voltage.
  • the first voltage is, for example, a low level. The following embodiments are the same as this, and will not be repeated.
  • the first voltage terminal VGL1 may be configured to be grounded.
  • the first node Q1 when the first node Q1 is at a high level, the first node Q1 may leak through the leakage path shown in FIG.
  • the leakage path may be a reset circuit connected to the first node Q1.
  • the control terminal of the reset circuit can be made to receive the low-level first voltage.
  • the first leakage prevention electronic circuit 410 when the level of the first node Q1 is high, the first leakage prevention electronic circuit 410 is turned on under the control of the level of the first node Q1, so that the level of the leakage prevention node OF becomes high.
  • the second anti-leakage electronic circuit 420 is turned on under the control of the high level of the anti-leakage node OF or the high level of the first node Q1, so that a gap is formed between the anti-leakage node OF and the first voltage terminal VGL1. Therefore, the level of the leakage prevention node OF is higher than the first voltage provided by the first voltage terminal VGL1.
  • the level of the leakage prevention node OF can be made higher than the first voltage, so that the circuit in the leakage path (for example, the reset circuit) is at the level of the leakage prevention node OF and the first voltage. It is cut off under control, that is, the circuit connected between the first node Q1 and the leakage prevention node OF is cut off, so as to prevent the first node Q1 from leaking through the leakage path.
  • the circuit that may cause the leakage of the first node Q1 to be electrically connected to the leakage prevention node OF can avoid the leakage of the first node Q1.
  • the shift register unit 10 provided by some embodiments of the present disclosure can not only prevent leakage of the first node Q1, but also avoid multiple circuits (for example, multiple The reset circuit) leaks, thereby simplifying the circuit structure, reducing the frame size of the display device using the shift register unit, and improving the PPI of the display device.
  • the high level and the low level are relative.
  • the high level indicates a higher voltage range (for example, the high level may be 5V, 10V or other suitable voltages), and multiple high levels may be the same or different.
  • the low level represents a lower voltage range (for example, the low level may adopt 0V, -5V, -10V or other suitable voltages), and multiple low levels may be the same or different.
  • the minimum value of the high level is greater than the maximum value of the low level.
  • controlling the level of a node includes charging the node to increase the level of the node, Or discharge the node to pull down the level of the node.
  • a node for example, the first node Q1, the second node Q2, etc.
  • charging the node means charging the capacitor electrically connected to the node; similarly, discharging the node means charging the capacitor electrically connected to the node. Discharge; the high or low level of the node can be maintained through the capacitor.
  • the first leakage prevention electronic circuit 410 includes a first leakage prevention transistor A1
  • the second leakage prevention electronic circuit 420 includes a second leakage prevention transistor. A2. It should be noted that FIG. 3 and FIG. 4 only illustrate part of the circuit of the shift register unit 10.
  • the gate of the first leakage prevention transistor A1 is connected to the first node Q1, the first pole of the first leakage prevention transistor A1 is configured to receive the second voltage VDD, and the second pole of the first leakage prevention transistor A1 is connected to the leakage prevention node OF connection.
  • the first anti-leakage transistor A1 is turned on, so that the second voltage VDD can be used to control the level of the anti-leakage node OF. The level goes high.
  • the gate and the first electrode of the second leakage prevention transistor A2 are electrically connected to each other and are configured to be connected to the leakage prevention node OF, and the second electrode of the second leakage prevention transistor A2 is configured to be connected to the first voltage terminal VGL1 to receive the One voltage.
  • the second leakage prevention transistor A2 adopts a diode connection.
  • the second leakage prevention transistor A2 is turned on.
  • the second leakage prevention transistor A2 has a unidirectional conduction characteristic. That is, the current direction is from the leakage prevention node OF to the first voltage terminal VGL1, and due to the internal resistance of the second leakage prevention transistor A2, the level of the leakage prevention node OF is greater than the first voltage provided by the first voltage terminal VGL1.
  • the shift register unit 10 further includes a first reset transistor R1 and a second reset transistor R2 that reset the first node Q1.
  • the gate of the first reset transistor R1 is configured to receive the display reset signal STD.
  • the first reset transistor R1 is turned on, so that the first node Q1 passes through the first reset transistor R1.
  • the second leakage prevention transistor A2 is electrically connected to the first voltage terminal VGL1, so that the first node Q1 can be reset by using the low-level first voltage provided by the first voltage terminal VGL1.
  • the gate of the second reset transistor R2 is configured to receive the global reset signal TRST.
  • the global reset signal TRST is at a high level
  • the second reset transistor R2 is turned on, so that the first node Q1 passes through the second reset transistor R2.
  • the second leakage prevention transistor A2 is electrically connected to the first voltage terminal VGL1, so that the first node Q1 can be reset by using the low-level first voltage provided by the first voltage terminal VGL1.
  • the display reset signal STD and the global reset signal TRST will be described in detail below, and will not be repeated here.
  • the display reset signal STD provided to the first reset transistor R1 and the global reset signal TRST provided to the second reset transistor R2 can be made to be the first voltage with a low level at this time.
  • the first reset transistor R1 and the second reset transistor R2 are turned off. If the first reset transistor R1 and the second reset transistor R2 cannot be completely turned off, the first node Q1 may leak through the first reset transistor R1 or the second reset transistor R2.
  • the display reset signal STD or the global reset signal TRST having a predetermined low level makes the Vgs (the voltage difference between the gate and the source) of the first reset transistor R1 and the second reset transistor R2 equal Less than zero, so that both the first reset transistor R1 and the second reset transistor R2 can be kept off, and at the same time, the potential of the leakage prevention node OF becomes higher (higher than the first voltage), so that from the first node Q1 to the leakage prevention node OF
  • the voltage difference of ⁇ becomes smaller (or even negative), so that the first node Q1 cannot leak through the first reset transistor R1 or the second reset transistor R2, or the leakage degree is reduced.
  • the possible leakage path of the first node Q1 only shows the first reset transistor R1 and the second reset transistor R2, when there are other and first reset transistors
  • the node Q1 is connected to the circuit, in order to avoid leakage of the first node Q1 through the circuit, it is only necessary to connect the circuit to the leakage prevention node OF.
  • the shift register unit 10 provided by some embodiments of the present disclosure, by providing the first leakage prevention transistor A1 and the second leakage prevention transistor A2, when the first node Q1 is at a high level, it can be connected to The circuit between the first node Q1 and the leakage prevention node OF is cut off, so that the leakage of the first node Q1 can be avoided.
  • the function of the second leakage prevention transistor A2 is no longer to prevent leakage. Instead, it is reset, that is, the second leakage prevention transistor A2 is multiplexed as a reset transistor.
  • the first leakage prevention electronic circuit 410 includes a first leakage prevention transistor A1
  • the second leakage prevention electronic circuit 420 includes a third leakage prevention transistor A3.
  • the gate of the first leakage prevention transistor A1 is connected to the first node Q1
  • the first pole of the first leakage prevention transistor A1 is configured to receive the second voltage VDD
  • the second pole of the first leakage prevention transistor A1 is connected to the first node Q1.
  • Node OF connection For example, when the level of the first node Q1 is high, the first anti-leakage transistor A1 is turned on, so that the second voltage VDD can be used to control the level of the anti-leakage node OF. The level goes high.
  • the gate of the third leakage prevention transistor A3 is connected to the first node Q1, the first electrode of the third leakage prevention transistor A3 is connected to the leakage prevention node OF, and the second electrode of the third leakage prevention transistor A3 is configured to A voltage terminal VGL1 is connected to receive the first voltage.
  • the third leakage prevention transistor A3 is turned on, so that a conductive path is formed between the leakage prevention node OF and the first voltage terminal VGL1, and the level of the leakage prevention node OF is greater than The first voltage provided by the first voltage terminal VGL1.
  • the shift register unit 10 by providing the first leakage prevention transistor A1 and the third leakage prevention transistor A3, when the first node Q1 is at a high level, the level of the leakage prevention node OF increases High, relative to the display reset signal STD or the global reset signal TRST having a predetermined low level (for example, the first voltage), so that, for example, the first reset transistor R1 and the second reset transistor R2 are kept off, so that the The circuit between the node Q1 and the leakage prevention node OF is cut off, and at the same time, since the potential of the leakage prevention node OF becomes higher (higher than the first voltage), the voltage difference from the first node Q1 to the leakage prevention node OF becomes smaller (even Negative), so as to avoid leakage of the first node Q1, or a decrease in the degree of leakage.
  • a predetermined low level for example, the first voltage
  • transistors shown in FIGS. 3 and 4 are all N-type transistors for illustration.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • thin film transistors are used as examples for description.
  • the source and drain of the transistor used here may be symmetrical in structure, so the source and drain may be indistinguishable in structure.
  • transistors in order to distinguish the two poles of the transistor other than the gate, one pole of the first pole and the other pole of the second pole are directly described.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages), and the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages) );
  • the transistors in the following embodiments are also described by taking N-type transistors as examples, and will not be repeated.
  • the embodiments of the present disclosure include but are not limited thereto.
  • one or more transistors in the shift register unit provided by the embodiments of the present disclosure may also adopt P-type transistors.
  • the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages) ).
  • the gate drive circuit composed of shift register units needs to provide drive signals for scanning transistors and sensing transistors to sub-pixel units in the display panel, for example, for the display period of one frame.
  • a sensing driving signal for the sensing transistor is provided in a blanking period of one frame.
  • the sensing driving signal output by the gate driving circuit is sequentially scanned row by row.
  • the sensing driving signal for the sub-pixel unit of the first row in the display panel is output during the blanking period of the first frame.
  • Measure the drive signal output the sense drive signal for the second row of sub-pixel units in the display panel during the blanking period of the second frame, and so on, output the frequency of the sense drive signal corresponding to one row of sub-pixel units per frame Line-by-line sequential output, which completes the line-by-line sequential compensation of the display panel.
  • the gate driving circuit drives a display panel
  • the gate driving circuit is required not only to output the scan driving signal for the display period, but also to output the blanking period. Sense the drive signal.
  • random compensation refers to an external compensation method that is different from line-by-line sequential compensation. During the blanking period of a certain frame, it can output randomly corresponding to any line in the display panel.
  • the sensing driving signal of the sub-pixel unit is the same in the following embodiments, and will not be repeated here.
  • the definition of "one frame,” “every frame,” or “a certain frame” includes sequential display periods and blanking periods, for example, in the display period.
  • the driving circuit outputs a driving signal, which can drive the display panel from the first row to the last row to complete the scanning and display of a complete image.
  • the gate driving circuit outputs a driving signal, which can be used for driving
  • the sensing transistors in a certain row of sub-pixel units in the display panel complete the external compensation of the row of sub-pixel units.
  • the shift register unit 10 further includes a blanking input subunit 300.
  • the blanking input subunit 300 is connected to the first node Q1, and is configured to receive the selection control signal OE and control the level of the first node Q1, for example, charge the first node Q1.
  • the blanking input sub-unit 300 may charge the first node Q1, so that the first output circuit 120 outputs the first output signal OUT1 under the control of the level of the first node Q1 .
  • the first output signal OUT1 can be used to drive the sensing transistors in a certain row of sub-pixel units in the display panel to complete the external compensation of the row of sub-pixel units.
  • the gate driving circuit of the shift register unit 10 and the display device provided by the embodiments of the present disclosure can realize random compensation, thereby avoiding poor display problems such as scan lines and uneven display brightness caused by line-by-line sequential compensation.
  • the blanking input sub-unit 300 includes a selection control circuit 310, a third input circuit 320 and a first transmission circuit 330.
  • the selection control circuit 310 is configured to use the second input signal STU2 to control the level of the third node H in response to the selection control signal OE, for example, to charge the third node H and maintain the level of the third node H. For example, in the display period of one frame, the selection control circuit 310 may be turned on under the control of the selection control signal OE, so as to charge the third node H using the second input signal STU2.
  • the level (for example, high level) of the third node H can be maintained from the display period of one frame to the blanking period of the frame.
  • the shift register unit 10 of a certain stage may receive the shift signal CR output by the shift register unit 10 of the other stage as the second input signal STU2.
  • the waveforms of the selection control signal OE and the second input signal STU2 provided to the shift register unit 10 of this stage can be made The timing is the same, so that the selection control circuit 310 in the shift register unit 10 of this stage is turned on.
  • the third input circuit 320 is configured to transmit the first clock signal CLKA to the fourth node N under the control of the level of the third node H.
  • the third input circuit 320 may be configured to receive the first clock signal CLKA.
  • the third input circuit 320 is turned on under the control of the level of the third node H, the first clock signal CLKA can be transmitted to the fourth node N, thereby controlling the level of the fourth node N.
  • the third input circuit 320 may transmit the high level to the fourth node N, so that the fourth node N becomes a high level. level.
  • the first transmission circuit 330 is electrically connected to the first node Q1, the fourth node N, and the leakage prevention node OF, and is configured to respond to the level of the first node Q1 and the leakage prevention node OF in response to the first clock signal CLKA. Level control.
  • the first transmission circuit 330 may be configured to receive the first clock signal CLKA, and when the first transmission circuit 330 is turned on under the control of the first clock signal CLKA, the power of the fourth node N may be The signal is transmitted to the first node Q1, so as to control the level of the first node Q1, for example, to charge the first node Q1.
  • the level of the fourth node N can also be transmitted to the leakage prevention node OF, so as to control the level of the leakage prevention node OF.
  • the blanking input sub-unit 300 is provided in the shift register unit 10 to realize that the driving signal can be output during the blanking period of one frame.
  • the "blanking" in the blanking input sub-unit 300 only indicates that it is related to the blanking period in a frame, and does not limit the blanking input sub-unit 300 to only work in the blanking period. The following embodiments are the same. No longer.
  • the shift register unit 10 provided by some embodiments of the present disclosure further includes a second subunit 200.
  • the second subunit 200 includes a second input circuit 210 and a second output circuit 220.
  • the second input circuit 210 is configured to control the level of the second node Q2 in response to the first input signal STU1, for example, to charge the second node Q2.
  • the second input circuit 210 may be configured to receive the first input signal STU1 and the second voltage VDD, and the second input circuit 210 is turned on in response to the first input signal STU1, so that the second voltage VDD can be used for the second node Q2 is charging.
  • the second input circuit 210 may not receive the second voltage VDD, and directly use the first input signal STU1 to charge the second node Q2.
  • the second output circuit 220 is configured to output the second output signal OUT2 under the control of the level of the second node Q2.
  • the second output circuit 220 may be configured to receive the fourth clock signal CLKD.
  • the fourth clock signal CLKD may be used as the second output signal. OUT2 output.
  • the shift register 10 provided by the embodiment of the present disclosure can charge multiple subunits (the first subunit 100 and the second subunit 200, etc.) at the same time, and only one subunit (for example, the first subunit 100) needs to output shift Signal, and other sub-units (such as the second sub-unit 200, etc.) do not need to output shift signals, so that the number of clock signal lines and transistors can be saved, and the frame size of the display device using the shift register unit 10 can be reduced , Improve the PPI of the display device.
  • FIG. 7 is only an example of the present disclosure, and the embodiment of the present disclosure does not limit the number of subunits included in the shift register unit 10, for example, it may also include three, four or more subunits. , The number of sub-units can be set according to the actual situation.
  • the blanking input subunit 300 also includes the second transmission circuit 340.
  • the second transmission circuit 340 is electrically connected to the second node Q2 and the leakage prevention node OF, and is configured to transmit the level of the leakage prevention node OF to the second node Q2 in response to the first clock signal CLKA.
  • the second transmission circuit 340 may be configured to receive the first clock signal CLKA, and when the second transmission circuit 340 is turned on under the control of the first clock signal CLKA, the electrical leakage prevention node OF may be The level is transmitted to the second node Q2, thereby controlling the level of the second node Q2, for example, charging the second node Q2.
  • the second output signal OUT2 output by the second output circuit 220 can drive a certain row of sub-pixel units in the display panel to perform display scanning.
  • the second output signal OUT2 output by the second output circuit 220 can be used to drive the sensing transistors in a certain row of sub-pixel units in the display panel to complete the row of sub-pixel units External compensation.
  • the shift register unit 10 includes three, four or more sub-units, correspondingly, three, four or more transmission circuits need to be provided to realize the function of the blanking input sub-unit 300.
  • the shift register unit 10 when the shift register unit 10 includes multiple subunits (the first subunit 100 and the second subunit 200, etc.), these subunits can share a blanking input subunit 300, so that The area occupied by the shift register unit 10 is reduced, and the frame size of the display device using the shift register unit is reduced, thereby increasing the PPI of the display device.
  • the selection control circuit 310 may be implemented to include a fifth input transistor B5 and a first capacitor C1.
  • the gate of the fifth input transistor B5 is configured to receive the selection control signal OE
  • the first pole of the fifth input transistor B5 is configured to receive the second input signal STU2, the second pole of the fifth input transistor B5 and the third node H connection.
  • the selection control signal OE is a high-level turn-on signal
  • the fifth input transistor B5 is turned on, so that the third node H can be charged by the second input signal STU2.
  • the first pole of the first capacitor C1 is connected to the third node H
  • the second pole of the first capacitor C1 is connected to the first voltage terminal VGL1 to receive the first voltage
  • the second pole of the first capacitor C1 is configured to receive the first voltage.
  • the potential of the third node H can be maintained by setting the first capacitor C1. For example, during the display period of one frame, the selection control circuit 310 charges the third node H so as to pull the third node H to a high potential. C1 can maintain the high potential of the third node H to the blanking period of the frame.
  • the third input circuit 320 may be implemented as a seventh input transistor B7.
  • the gate of the seventh input transistor B7 is connected to the third node H
  • the first electrode of the seventh input transistor B7 is configured to receive the first clock signal CLKA
  • the second electrode of the seventh input transistor B7 is connected to the fourth node N.
  • the seventh input transistor B7 is turned on, so that the first clock signal CLKA can be transmitted to the fourth node N to raise the level of the fourth node N.
  • the first transmission circuit 330 includes a first transmission transistor T1 and a second transmission transistor T2, and the second transmission circuit 340 includes a third transmission transistor T3.
  • the gate of the first transfer transistor T1 is configured to receive the first clock signal CLKA, the first pole of the first transfer transistor T1 is connected to the fourth node N, and the second pole of the first transfer transistor T1 is connected to the leakage prevention node OF;
  • the gate of the second transfer transistor T2 is configured to receive the first clock signal CLKA, the first pole of the second transfer transistor T2 is connected to the leakage prevention node OF, and the second pole of the second transfer transistor T2 is connected to the first node Q1;
  • the gate of the third transfer transistor T3 is configured to receive the first clock signal CLKA, the first pole of the third transfer transistor T3 is connected to the leakage prevention node OF, and the second pole of the third transfer transistor T3 is connected to the second node Q2.
  • the first transfer transistor T1, the second transfer transistor T2, and the third transfer transistor T3 are all turned on, and the turned-on first transfer transistor T1 can turn the fourth node N high.
  • the level is transmitted to the leakage prevention node OF, so that the level of the leakage prevention node OF becomes a high level; then the turned-on second transfer transistor T2 transmits the high level of the leakage prevention node OF to the first node Q1 to achieve Charge the first node Q1; the turned-on third transfer transistor T3 transfers the high level of the leakage prevention node OF to the second node Q2, so as to charge the second node Q2.
  • the first transfer transistor T1 is multiplexed, and at the same time, since the second transfer transistor T2 is connected to the leakage prevention node OF, the second transfer transistor T2 is also The leakage of the first node Q1 can be avoided; since the third transfer transistor T3 is connected to the leakage prevention node OF, the third transfer transistor T3 can also avoid the leakage of the second node Q2.
  • the blanking input subunit 300 provided in FIGS. 9A-9C will be described below. It should be noted that in the following description, the same parts in FIGS. 9A-9C and FIG. 8 will not be repeated.
  • the blanking input subunit 300 further includes a first coupling capacitor CST1.
  • the first pole of the first coupling capacitor CST1 is configured to receive the first clock signal CLKA, and the second pole of the first coupling capacitor CST1 is connected to the third node H.
  • the first clock signal CLKA changes from a low level to a high level
  • the first clock signal CLKA can couple and pull up the third node H through the coupling effect of the first coupling capacitor CST1, so that the power of the third node H The level is further pulled high, so that the seventh input transistor B7 can be turned on more fully.
  • the blanking input subunit 300 further includes a second coupling capacitor CST2, the first pole of the second coupling capacitor CST2 is connected to the third node H, and the second coupling capacitor CST2 The two poles are connected to the fourth node N.
  • the first clock signal CLKA changes from low level to high level
  • the seventh input transistor B7 is turned on at this time
  • the high level first clock signal CLKA can be transmitted to the fourth through the seventh input transistor B7.
  • the potential of the second pole of the second coupling capacitor CST2 is pulled high.
  • the level of the third node H can be further pulled high, thereby ensuring the seventh The conduction of the input transistor B7 is more sufficient.
  • the first transfer circuit 330 includes a first transfer transistor T1 and a second transfer transistor T2, and the second transfer circuit 340 includes a third transfer transistor T3.
  • the gate of the first transfer transistor T1 is connected to the fourth node N, the first pole of the first transfer transistor T1 is configured to receive the high-level second voltage VDD, the second pole of the first transfer transistor T1 and the leakage prevention node OF connection;
  • the gate of the second transfer transistor T2 is connected to the fourth node N, the first pole of the second transfer transistor T2 is connected to the leakage prevention node OF, and the second pole of the second transfer transistor T2 is connected to the first node Q1;
  • the gate of the third transfer transistor T3 is connected to the fourth node N, the first pole of the third transfer transistor T3 is connected to the leakage prevention node OF, and the second pole of the third transfer transistor T3 is connected to the second node Q2.
  • the first clock signal CLKA when the first clock signal CLKA is at a high level, the first clock signal CLKA at a high level is transmitted to the fourth node N through the turned-on seventh input transistor B7, so that the fourth node N becomes a high level,
  • the first transfer transistor T1, the second transfer transistor T2, and the third transfer transistor T3 are all turned on.
  • the turned-on first transfer transistor T1 can transmit the high-level second voltage VDD to the leakage prevention node OF to prevent leakage
  • the level of the node OF changes to a high level
  • the turned-on second transfer transistor T2 transmits the high level of the leakage prevention node OF to the first node Q1, so as to charge the first node Q1
  • the three transfer transistor T3 transfers the high level of the leakage prevention node OF to the second node Q2 to charge the second node Q2.
  • FIG. 9D also provides a blanking input sub-unit 300.
  • the selection control circuit 310 in the blanking input sub-unit 300 includes a sixth input transistor B6 in addition to the fifth input transistor B5.
  • the blanking input sub-unit 300 further includes a fourth leakage prevention transistor A4.
  • the gate of the fourth leakage prevention transistor A4 is connected to the third node H
  • the first pole of the fourth leakage prevention transistor A4 is configured to receive the second voltage VDD
  • the second electrode of the fourth leakage prevention transistor A4 The electrode is connected to the first electrode of the sixth input transistor B6, the gate of the sixth input transistor B6 is configured to receive the selection control signal OE, and the second electrode of the sixth input transistor B6 is connected to the third node H.
  • the anti-leakage transistor A4 and the sixth input transistor B6 cooperate to prevent the third node H from leaking.
  • the first subunit 100 further includes a first control circuit 130, a first reset circuit 140, a second reset circuit 150, and a shift signal The output terminal CRT and the first output signal terminal OP1.
  • the shift signal output terminal CRT is configured to output the shift signal CR
  • the first output signal terminal OP1 is configured to output the first output signal OUT1.
  • the first control circuit 130 is configured to control the level of the fifth node QB_A under the control of the level of the first node Q1 and the third voltage VDD_A.
  • the first control circuit 130 is connected to the first node Q1 and the fifth node QB_A, and is configured to receive the third voltage VDD_A and the first voltage.
  • the first control circuit 130 may use a low-level first voltage to pull the fifth node QB_A down to a low level.
  • the first control circuit 130 may use the third voltage VDD_A (for example, a high level) to charge the fifth node QB_A, so as to pull the fifth node QB_A to a high level .
  • VDD_A for example, a high level
  • the first reset circuit 140 is configured to reset the first node Q1, the shift signal output terminal CRT, and the first output signal terminal OP1 under the control of the level of the fifth node QB_A.
  • the first reset circuit 140 is connected to the first node Q1, the fifth node QB_A, the shift signal output terminal CRT, and the first output signal terminal OP1, and is configured to receive the first voltage and the fifth voltage VGL2.
  • the first reset circuit 140 when the first reset circuit 140 is turned on under the control of the level of the fifth node QB_A, the first node Q1 and the shift signal output terminal CRT can be pulled down and reset by the first voltage, and the fifth The voltage VGL2 pulls down and resets the first output signal terminal OP1.
  • the first output signal terminal OP1 may also be used to pull down and reset the first output signal terminal OP1, which is not limited in the present disclosure.
  • the fifth voltage VGL2 is, for example, a low level. The following embodiments are the same as this, and will not be repeated. In the embodiment of the present disclosure, the fifth voltage VGL2 may be the same as or different from the first voltage.
  • the second reset circuit 150 is configured to reset the first node Q1, the shift signal output terminal CRT, and the first output signal terminal OP1 under the control of the level of the sixth node QB_B.
  • the second reset circuit 150 is connected to the first node Q1, the sixth node QB_B, the shift signal output terminal CRT, and the first output signal terminal OP1, and is configured to receive the first voltage and the fifth voltage VGL2.
  • the first voltage can be used to pull down the first node Q1 and the shift signal output terminal CRT, and the fifth The voltage VGL2 pulls down and resets the first output signal terminal OP1.
  • the second subunit 200 further includes a second control circuit 230, a third reset circuit 240, a fourth reset circuit 250, and a second output signal terminal OP2.
  • the second output signal terminal OP2 is configured to output the second output signal OUT2.
  • the second control circuit 230 is configured to control the level of the sixth node QB_B under the control of the level of the second node Q2 and the fourth voltage VDD_B.
  • the second control circuit 230 is connected to the second node Q2 and the sixth node QB_B, and is configured to receive the fourth voltage VDD_B and the first voltage.
  • the second control circuit 230 may pull down the sixth node QB_B to a low level by using the first voltage at a low level.
  • the second control circuit 230 may use the fourth voltage VDD_B (for example, a high level) to charge the sixth node QB_B, so as to pull the sixth node QB_B high. Level.
  • the third reset circuit 240 is configured to reset the second node Q2 and the second output signal terminal OP2 under the control of the level of the sixth node QB_B.
  • the third reset circuit 240 is connected to the second node Q2, the sixth node QB_B and the second output signal terminal OP2, and is configured to receive the first voltage and the fifth voltage VGL2.
  • Terminal OP2 performs pull-down reset. It should be noted that in some embodiments of the present disclosure, the first voltage may also be used to pull-down reset the second output signal terminal OP2, which is not limited in the present disclosure.
  • the fourth reset circuit 250 is configured to reset the second node Q2 and the second output signal terminal OP2 under the control of the level of the fifth node QB_A.
  • the fourth reset circuit 250 is connected to the second node Q2, the fifth node QB_A, and the second output signal terminal OP2, and is configured to receive the first voltage and the fifth voltage VGL2.
  • the first voltage can be used to pull down and reset the second node Q2
  • the fifth voltage VGL2 can also be used to reset the second output signal.
  • Terminal OP2 performs pull-down reset.
  • the third voltage VDD_A and the fourth voltage VDD_B may be configured to be mutually inverted signals, that is, when the third voltage VDD_A is at a high level, the fourth voltage VDD_B is When the third voltage VDD_A is low, the fourth voltage VDD_B is high. In this way, only one of the first control circuit 130 and the second control circuit 230 can be in working state at the same time, which can avoid performance drift caused by long-term circuit operation, thereby improving the stability of the circuit.
  • each node (first node Q1, second node Q2, third node H, fourth node N, fifth node QB_A, sixth node QB_B, etc.) and each output The terminals (the shift signal output terminal CRT, the first output signal terminal OP1, the second output signal terminal OP2, etc.) are all set to better describe the circuit structure, and do not represent actual components.
  • the node represents the junction of the related circuit connections in the circuit structure, that is, the related circuits connected with the same node identifier are electrically connected to each other.
  • the first control circuit 130, the first reset circuit 140, and the fourth reset circuit 250 are all connected to the fifth node QB_A, which means that these circuits are electrically connected to each other.
  • the first subunit 100 further includes a third control circuit 160, a fourth control circuit 170, and a common control circuit; the second subunit 200 It also includes a fifth control circuit 260 and a sixth control circuit 270.
  • the third control circuit 160 is connected to the fifth node QB_A and the common control node CC, and is configured to electrically connect the fifth node QB_A and the common control node CC in response to the first clock signal CLKA.
  • the common control circuit 161 is electrically connected to the common control node CC and the first voltage terminal VGL1, and is configured to electrically connect the common control node CC and the first voltage terminal VGL1 under the control of the level of the third node H.
  • the fifth control circuit 260 is connected to the sixth node QB_B and the common control node CC, and is configured to electrically connect the sixth node QB_B and the common control node CC in response to the first clock signal CLKA.
  • the third control circuit 160, the common control circuit 161, and the fifth control circuit 260 are all turned on , So that the fifth node QB_A is electrically connected to the first voltage terminal VGL1 through the third control circuit 160 and the common control circuit 161, so that the low-level first voltage can pull down the fifth node QB_A; the sixth node QB_B
  • the fifth control circuit 260 and the common control circuit 161 are electrically connected to the first voltage terminal VGL1, so that the low-level first voltage can pull down the sixth node QB_B. That is, the common control circuit 161 is used to control the level of the fifth node QB_A and the level of the sixth node QB_B, so that the circuit structure can be simplified.
  • some embodiments of the present disclosure also provide a shift register unit 10. Only the difference between the shift register unit 10 shown in FIG. 12 and the shift register unit 10 shown in FIG. 11 will be described below. , The similarities will not be repeated.
  • the third control circuit 160 is connected to the third node H, the fifth node QB_A, and the common control node CC, and is configured to make the fifth node QB_A and the common control node CC under the control of the level of the third node H
  • the control node CC is electrically connected.
  • the common control circuit 161 is electrically connected to the common control node CC and the first voltage terminal VGL1, and is configured to electrically connect the common control node CC and the first voltage terminal VGL1 in response to the first clock signal CLKA.
  • the fifth control circuit 260 is connected to the third node H, the sixth node QB_B, and the common control node CC, and is configured to electrically connect the sixth node QB_B and the common control node CC under the control of the level of the third node H.
  • the third control circuit 160, the common control circuit 161, and the fifth control circuit 260 are all turned on , So that the fifth node QB_A is electrically connected to the first voltage terminal VGL1 through the third control circuit 160 and the common control circuit 161, so that the low-level first voltage can pull down the fifth node QB_A; the sixth node QB_B
  • the fifth control circuit 260 and the common control circuit 161 are electrically connected to the first voltage terminal VGL1, so that the low-level first voltage can pull down the sixth node QB_B. That is, the common control circuit 161 is used to control the level of the fifth node QB_A and the level of the sixth node QB_B, so that the circuit structure can be simplified.
  • the fourth control circuit 170 is electrically connected to the fifth node QB_A and the first voltage terminal VGL1, and is configured to control the level of the fifth node QB_A in response to the first input signal STU1 .
  • the fourth control circuit 170 is turned on in response to the first input signal STU1, so that the fifth node QB_A is pulled down with the first voltage of the low level. Pulling down the fifth node QB_A to a low potential can avoid the influence of the fifth node QB_A on the first node Q1, thereby making the first node Q1 more fully charged during the display period.
  • the sixth control circuit 270 is electrically connected to the sixth node QB_B and the first voltage terminal VGL1, and is configured to control the level of the sixth node QB_B in response to the first input signal STU1. For example, in the display period of one frame, the sixth control circuit 270 is turned on in response to the first input signal STU1, so that the sixth node QB_B is pulled down by the first voltage of the low level. Pulling down the sixth node QB_B to a low potential can avoid the influence of the sixth node QB_B on the second node Q2, thereby making the second node Q2 more fully charged during the display period.
  • the first subunit 100 further includes a fifth reset circuit 180 and a sixth reset circuit 190
  • the second subunit 200 further includes a seventh reset circuit 280 and an eighth reset circuit 290.
  • the fifth reset circuit 180 is connected to the first node Q1 and the leakage prevention node OF, and is configured to reset the first node Q1 in response to the display reset signal STD; the sixth reset circuit 190 and the first node Q1 and leakage prevention The node OF is connected and is configured to reset the first node Q1 in response to the global reset signal TRST.
  • the second leakage-proof electronic circuit 420 remains conductive.
  • the fifth reset circuit 180 is turned on in response to the display reset signal STD, so that the first node Q1 passes through the fifth reset circuit 180, the second leakproof electronic circuit 420, and the first voltage terminal.
  • VGL1 is electrically connected, so that a low-level first voltage can be used to pull down and reset the first node Q1.
  • the shift register unit 10 of a certain stage can receive the shift signal CR output by the shift register unit 10 of the other stage as the display reset signal STD.
  • the sixth reset circuit 190 in the shift register units 10 of each stage is turned on in response to the global reset signal TRST. Therefore, the first node Q1 is electrically connected to the first voltage terminal VGL1 through the sixth reset circuit 190 and the second leak-proof electronic circuit 420, so that the first node Q1 can be pulled down and reset by the low-level first voltage.
  • the fifth reset circuit 180 and the sixth reset circuit 190 are both connected to the leakage prevention node OF.
  • the second leak-proof electronic circuit 420 may be multiplexed.
  • the leakage prevention circuit 400 can also prevent the first node Q1 from leaking through the fifth reset circuit 180 or the sixth reset circuit 190. That is to say, the second leakage-proof electronic circuit 420 can achieve both leakage prevention and reset operation of the first node Q1, so that the circuit structure can be simplified.
  • the seventh reset circuit 280 is connected to the second node Q2 and the leakage prevention node OF, and is configured to reset the second node Q2 in response to the display reset signal STD;
  • the eighth reset circuit 290 is connected to the second node Q2 and the leakage prevention node OF, and is configured to reset the second node Q2 in response to the global reset signal TRST.
  • the seventh reset circuit 280 is turned on in response to the display reset signal STD, so that the second node Q2 passes through the seventh reset circuit 280, the second leak-proof electronic circuit 420, and the first voltage terminal.
  • VGL1 is electrically connected, so that a low-level first voltage can be used to pull down and reset the second node Q2.
  • the eighth reset circuit 290 in the shift register units 10 of each stage is turned on in response to the global reset signal TRST. Therefore, the second node Q2 is electrically connected to the first voltage terminal VGL1 through the eighth reset circuit 290 and the second leak-proof electronic circuit 420, so that the second node Q2 can be pulled down and reset by the low-level first voltage.
  • the seventh reset circuit 280 and the eighth reset circuit 290 are both connected to the leakage prevention node OF, and when the seventh reset circuit 280 or the eighth reset circuit When 290 needs to perform a reset operation on the second node Q2, the second leak-proof electronic circuit 420 can be multiplexed.
  • the anti-leakage circuit 400 can also prevent the second node Q2 from leaking through the seventh reset circuit 280 or the eighth reset circuit 290. That is to say, the second leakage-proof electronic circuit 420 can achieve both leakage prevention and reset operation of the second node Q2, so that the circuit structure can be simplified.
  • the shift register unit 10 may be implemented as the circuit structure shown in FIG. 13. As shown in FIG. 13, the shift register unit 10 includes a first subunit 100 and an anti-leakage circuit 400.
  • the first subunit 100 includes a first input circuit 110, a first output circuit 120, a first control circuit 130, a first reset circuit 140, a fourth control circuit 170, a fifth reset circuit 180, and a sixth reset circuit 190.
  • the first input circuit 110 may be implemented as a first input transistor B1.
  • the gate of the first input transistor B1 is configured to receive the first input signal STU1
  • the first electrode of the first input transistor B1 is configured to receive the first voltage VDD, the second electrode of the first input transistor B1 and the first node Q1 connection.
  • the gate of the first input transistor B1 is connected to the first pole and is configured to receive the first input signal STU1, so that when the first input signal STU1 is at a high level, The high-level first input signal STU1 can be used to charge the first node Q1.
  • the first input circuit 110 further includes a second input transistor B2.
  • the gate and first electrode of the second input transistor B2 are connected to the second electrode of the first input transistor B1, and the second electrode of the second input transistor B2 is connected to the first node Q1. Since the second input transistor B2 adopts a diode connection, the current can only flow from the first pole of the second input transistor B2 to the second pole, but not from the second pole of the second input transistor B2 (ie the first node Q1) to The first pole, thereby avoiding leakage of the first node Q1.
  • the gate of the second input transistor B2 is connected to the gate of the first input transistor B1, and both are configured to receive the first input signal STU1, and the second input transistor B2
  • the first pole of is electrically connected to the leakage prevention node OF.
  • the first input circuit 110 shown in FIG. 14C can prevent leakage of the first node Q1 by being connected to the leakage prevention node OF.
  • the first output circuit 120 may include a first output transistor D1, a second output transistor D2, and a second capacitor C2.
  • the gate of the first output transistor D1 is connected to the first node Q1
  • the first electrode of the first output transistor D1 is configured to receive the second clock signal CLKB as the shift signal CR
  • the second electrode of the first output transistor D1 is
  • the shift signal output terminal CRT is connected and configured to output the shift signal CR.
  • the gate of the second output transistor D2 is connected to the first node Q1, the first pole of the second output transistor D2 is configured to receive the third clock signal CLKC as the first output signal OUT1, and the second pole of the second output transistor D2 It is connected to the first output signal terminal OP1 and is configured to output the first output signal OUT1.
  • the first pole of the second capacitor C2 is connected to the first node Q1, and the second pole of the second capacitor C2 is connected to the second pole of the second output transistor D2 (ie, the first output signal terminal OP1).
  • the first control circuit 130 may be implemented to include a ninth control transistor E9 and a tenth control transistor E10.
  • the gate and the first electrode of the ninth control transistor E9 are configured to receive the third voltage VDD_A, and the second electrode of the ninth control transistor E9 is connected to the fifth node QB_A.
  • the gate of the tenth control transistor E10 is connected to the first node Q1
  • the first electrode of the tenth control transistor E10 is connected to the fifth node QB_A
  • the second electrode of the tenth control transistor E10 is configured to be connected to the first voltage terminal VGL1 To receive the first voltage.
  • the first reset circuit 140 may be implemented to include a seventh reset transistor R7, an eighth reset transistor R8, and a ninth reset transistor R9.
  • the gate of the seventh reset transistor R7 is connected to the fifth node QB_A, the first electrode of the seventh reset transistor R7 is connected to the first node Q1, and the second electrode of the seventh reset transistor R7 is connected to the leakage prevention node OF.
  • the gate of the eighth reset transistor R8 is connected to the fifth node QB_A, the first pole of the eighth reset transistor R8 is connected to the shift signal output terminal CRT, and the second pole of the eighth reset transistor R8 is connected to the first voltage terminal VGL1 to Receive the first voltage.
  • the gate of the ninth reset transistor R9 is connected to the fifth node QB_A, the first pole of the ninth reset transistor R9 is connected to the first output signal terminal OP1, and the second pole of the ninth reset transistor R9 is configured to receive the fifth voltage VGL2 .
  • the fourth control circuit 170 may be implemented as a second control transistor E2.
  • the gate of the second control transistor E2 is configured to receive the first input signal STU1, the first electrode of the second control transistor E2 is connected to the fifth node QB_A, and the second electrode of the second control transistor E2 is connected to the first voltage terminal VGL1 To receive the first voltage.
  • the fifth reset circuit 180 may be implemented as a first reset transistor R1
  • the sixth reset circuit 190 may be implemented as a second reset transistor R2.
  • the gate of the first reset transistor R1 is configured to receive the display reset signal STD
  • the first pole of the first reset transistor R1 is connected to the first node Q1
  • the second pole of the first reset transistor R1 is connected to the leakage prevention node OF.
  • the gate of the second reset transistor R2 is configured to receive the global reset signal TRST
  • the first pole of the second reset transistor R2 is connected to the first node Q1, and the second pole of the second reset transistor R2 is connected to the leakage prevention node OF.
  • the shift register unit 10 may also be implemented as the circuit structure shown in FIG. 15. Only the differences between the shift register unit 10 shown in FIG. 15 and the shift register unit 10 shown in FIG. 13 will be described below, and the similarities will not be repeated here.
  • the first input circuit 110 includes a first input transistor B1 and a second input transistor B2, that is, the first input circuit 110 adopts the circuit structure shown in FIG. 14C.
  • the shift register unit 10 further includes a thirteenth control transistor E13 and a fourteenth control transistor E14.
  • the gate and the first electrode of the thirteenth control transistor E13 are configured to receive the fourth voltage VDD_B, and the second electrode of the thirteenth control transistor E13 is connected to the sixth node QB_B.
  • the gate of the fourteenth control transistor E14 is connected to the first node Q1, the first electrode of the fourteenth control transistor E14 is connected to the sixth node QB_B, and the second electrode of the fourteenth control transistor E14 is configured to be connected to the first voltage
  • the terminal VGL1 is connected to receive the first voltage.
  • the third voltage VDD_A and the fourth voltage VDD_B may be configured to be mutually inverted signals, that is, when the third voltage VDD_A is at a high level, the fourth voltage VDD_B is When the third voltage VDD_A is low, the fourth voltage VDD_B is high.
  • the ninth control transistor E9 and the thirteenth control transistor E13 can be turned on at the same time, which can avoid performance drift caused by the long-term conduction of the transistors, thereby improving the stability of the circuit.
  • the shift register unit 10 further includes a fifth control transistor E5.
  • the gate of the fifth control transistor E5 is configured to receive the first input signal STU1, the first electrode of the fifth control transistor E5 is connected to the sixth node QB_B, and the second electrode of the fifth control transistor E5 is connected to the first voltage terminal VGL1 To receive the first voltage.
  • the shift register unit 10 further includes a tenth reset transistor R10, an eleventh reset transistor R11, and a twelfth reset transistor R12.
  • the gate of the tenth reset transistor R10 is connected to the sixth node QB_B, the first electrode of the tenth reset transistor R10 is connected to the first node Q1, and the second electrode of the tenth reset transistor R10 is connected to the leakage prevention node OF.
  • the gate of the eleventh reset transistor R11 is connected to the sixth node QB_B, the first electrode of the eleventh reset transistor R11 is connected to the shift signal output terminal CRT, and the second electrode of the eleventh reset transistor R11 is connected to the first voltage terminal VGL1 is connected to receive the first voltage.
  • the gate of the twelfth reset transistor R12 is connected to the sixth node QB_B, the first pole of the twelfth reset transistor R12 is connected to the first output signal terminal OP1, and the second pole of the twelfth reset transistor R12 is configured to receive the Five voltage VGL2.
  • the shift register unit 10 shown in FIG. 11 may be implemented as the circuit structure shown in FIG. 16.
  • the shift register unit 10 includes a first sub-unit 100, a second sub-unit 200 and an anti-leakage circuit 400.
  • the first subunit 100 includes a first input circuit 110, a first output circuit 120, a first control circuit 130, a third control circuit 160, a common control circuit 161, a fourth control circuit 170, a first reset circuit 140, and a second reset The circuit 150, the fifth reset circuit 180, and the sixth reset circuit 190.
  • the second subunit 200 includes a second input circuit 210, a second output circuit 220, a second control circuit 230, a fifth control circuit 260, a sixth control circuit 270, a third reset circuit 240, a fourth reset circuit 250, and a seventh The reset circuit 280 and the eighth reset circuit 290.
  • the first input circuit 110 includes a first input transistor B1 and a second input transistor B2.
  • the first output circuit 120 includes a first output transistor D1, a second output transistor D2, and a second capacitor C2.
  • the first reset circuit 140 includes a seventh reset transistor R7, an eighth reset transistor R8, and a ninth reset transistor R9.
  • the fourth control circuit 170 includes a second control transistor E2. Regarding the first input transistor B1, the second input transistor B2, the first output transistor D1, the second output transistor D2, the second capacitor C2, the seventh reset transistor R7, the eighth reset transistor R8, the ninth reset transistor R9, and the second control
  • the transistor E2 reference may be made to the corresponding description in the embodiment shown in FIG. 13, which will not be repeated here.
  • the second input circuit 210 includes a third input transistor B3 and a fourth input transistor B4.
  • the second output circuit 220 includes a third output transistor D3 and a third capacitor C3.
  • the gate of the third input transistor B3 is configured to receive the first input signal STU1, the first electrode of the third input transistor B3 is connected to the leakage prevention node OF, and the second electrode of the third input transistor M3 is connected to the second node Q2.
  • the gate of the fourth input transistor B4 is connected to the first electrode and is configured to receive the first input signal STU1, and the second electrode of the fourth input transistor B4 is connected to the leakage prevention node OF;
  • the gate of the third output transistor D3 is connected to the second node Q2, the first pole of the third output transistor D3 is configured to receive the fourth clock signal CLKD as the second output signal OUT2, and the second pole of the third output transistor D3 It is connected to the second output signal terminal OP2 and is configured to output the second output signal OUT2.
  • the first electrode of the third capacitor C3 is connected to the second node Q2, and the second electrode of the third capacitor C3 is connected to the second electrode of the third output transistor D3 (i.e., the second output signal terminal OP2).
  • the first control circuit 130 includes a ninth control transistor E9, a tenth control transistor E10, an eleventh control transistor E11, and a twelfth control transistor E12.
  • the gate and the first electrode of the ninth control transistor E9 are configured to receive the third voltage VDD_A, and the second electrode of the ninth control transistor E9 and the first electrode of the tenth control transistor E10 are connected.
  • the gate of the tenth control transistor E10 is connected to the first node Q1, and the second electrode of the tenth control transistor E10 is configured to receive the sixth voltage VGL3.
  • the gate of the eleventh control transistor E11 is connected to the second electrode of the ninth control transistor E9, the first electrode of the eleventh control transistor E11 is configured to receive the third voltage VDD_A, and the second electrode of the eleventh control transistor E11 Connect to the fifth node QB_A.
  • the gate of the twelfth control transistor E12 is connected to the first node Q1
  • the first electrode of the twelfth control transistor E12 is connected to the fifth node QB_A
  • the second electrode of the twelfth control transistor E12 is connected to the first voltage terminal VGL1 To receive the first voltage.
  • the sixth voltage VGL3 is, for example, a low level, and the following embodiments are the same as this, and will not be repeated. In the embodiment of the present disclosure, the sixth voltage VGL3 may be the same as or different from the first voltage.
  • the second control circuit 230 includes a thirteenth control transistor E13, a fourteenth control transistor E14, a fifteenth control transistor E15, and a sixteenth control transistor E16.
  • the gate and the first electrode of the thirteenth control transistor E13 are configured to receive the fourth voltage VDD_B, and the second electrode of the thirteenth control transistor E13 and the first electrode of the fourteenth control transistor E14 are connected.
  • the gate of the fourteenth control transistor E14 is connected to the second node Q2, and the second pole of the fourteenth control transistor E14 is configured to receive the sixth voltage VGL3.
  • the gate of the fifteenth control transistor E15 is connected to the second pole of the thirteenth control transistor E13, the first pole of the fifteenth control transistor E15 is configured to receive the fourth voltage VDD_B, and the second pole of the fifteenth control transistor E15 is The pole is connected to the sixth node QB_B.
  • the gate of the sixteenth control transistor E16 is connected to the second node Q2
  • the first electrode of the sixteenth control transistor E16 is connected to the sixth node QB_B
  • the second electrode of the sixteenth control transistor E16 is connected to the first voltage terminal VGL1 To receive the first voltage.
  • the third control circuit 160 includes a first control transistor E1
  • the fourth control circuit 170 includes a second control transistor E2
  • the common control circuit 161 includes a third control transistor E3.
  • the gate of the first control transistor E1 is configured to receive the first clock signal CLKA, the first electrode of the first control transistor E1 is connected to the fifth node QB_A, and the second electrode of the first control transistor E1 is connected to the common control node CC.
  • the gate of the second control transistor E2 is configured to receive the first input signal STU1, the first electrode of the second control transistor E2 is connected to the fifth node QB_A, and the second electrode of the second control transistor E2 is connected to the first voltage terminal VGL1 .
  • the gate of the third control transistor E3 is connected to the third node H, the first electrode of the third control transistor E3 is connected to the common control node CC, and the second electrode of the third control transistor E3 is connected to the first voltage terminal VGL1.
  • the fifth control circuit 260 includes a fourth control transistor E4, and the sixth control circuit 270 includes a fifth control transistor E5.
  • the gate of the fourth control transistor E4 is configured to receive the first clock signal CLKA, the first pole of the fourth control transistor E4 is connected to the sixth node QB_B, and the second pole of the fourth control transistor E4 is connected to the common control node CC.
  • the gate of the fifth control transistor E5 is configured to receive the first input signal STU1, the first electrode of the fifth control transistor E5 is connected to the sixth node QB_B, and the second electrode of the fifth control transistor E5 is connected to the first voltage terminal VGL1 .
  • the third control transistor E3 can be multiplexed by setting the common control node CC, so that the circuit structure can be simplified.
  • the second reset circuit 150 includes a tenth reset transistor R10, an eleventh reset transistor R11, and a twelfth reset transistor R12.
  • the gate of the tenth reset transistor R10 is connected to the sixth node QB_B, the first electrode of the tenth reset transistor R10 is connected to the first node Q1, and the second electrode of the tenth reset transistor R10 is connected to the leakage prevention node OF.
  • the gate of the eleventh reset transistor R11 is connected to the sixth node QB_B, the first electrode of the eleventh reset transistor R11 is connected to the shift signal output terminal CRT, and the second electrode of the eleventh reset transistor R11 is connected to the first voltage terminal VGL1 is connected to receive the first voltage.
  • the gate of the twelfth reset transistor R12 is connected to the sixth node QB_B, the first pole of the twelfth reset transistor R12 is connected to the first output signal terminal OP1, and the second pole of the twelfth reset transistor R12 is configured to receive the Five voltage VGL2.
  • the third reset circuit 240 includes a thirteenth reset transistor R13 and a fourteenth reset transistor R14.
  • the fourth reset circuit 250 includes a fifteenth reset transistor R15 and a sixteenth reset transistor R16.
  • the gate of the thirteenth reset transistor R13 is connected to the sixth node QB_B, the first pole of the thirteenth reset transistor R13 is connected to the second node Q2, and the second pole of the thirteenth reset transistor R13 is connected to the leakage prevention node OF.
  • the gate of the fourteenth reset transistor R14 is connected to the sixth node QB_B, the first pole of the fourteenth reset transistor R14 is connected to the second output signal terminal OP2, and the second pole of the fourteenth reset transistor R14 is configured to receive the Five voltage VGL2.
  • the gate of the fifteenth reset transistor R15 is connected to the fifth node QB_A, the first electrode of the fifteenth reset transistor R15 is connected to the second node Q2, and the second electrode of the fifteenth reset transistor R15 is connected to the leakage prevention node OF.
  • the gate of the sixteenth reset transistor R16 is connected to the fifth node QB_A, the first pole of the sixteenth reset transistor R16 is connected to the second output signal terminal OP2, and the second pole of the sixteenth reset transistor R16 is configured to receive the Five voltage VGL2.
  • the fifth reset circuit 180 includes a first reset transistor R1 and a fifth reset crystal R5, and the seventh reset circuit 280 includes a third reset transistor R3.
  • the gate of the first reset transistor R1 is configured to receive the display reset signal STD, the first pole of the first reset transistor R1 is connected to the first node Q1, and the second pole of the first reset transistor R1 is connected to the leakage prevention node OF.
  • the gate of the fifth reset transistor R5 is configured to receive the display reset signal STD, the first pole of the fifth reset transistor R5 is connected to the leakage prevention node OF, and the second pole of the fifth reset transistor R5 is connected to the first voltage terminal VGL1 to Receive the first voltage.
  • the gate of the third reset transistor R3 is configured to receive the display reset signal STD, the first pole of the third reset transistor R3 is connected to the second node Q2, and the second pole of the third reset transistor R3 is connected to the leakage prevention node OF.
  • connecting the first reset transistor R1 and the leakage prevention node OF can prevent the first node Q1 from leaking through the first reset transistor R1.
  • connecting the third reset transistor R3 and the leakage prevention node OF can prevent the second node Q2 from leaking through the third reset transistor R3.
  • the fifth reset transistor R5 can be multiplexed, so that the circuit structure of the shift register unit 10 can be simplified.
  • the sixth reset circuit 190 includes a second reset transistor R2 and a sixth reset crystal R6, and the eighth reset circuit 290 includes a fourth reset transistor R4.
  • the gate of the second reset transistor R2 is configured to receive the global reset signal TRST, the first pole of the second reset transistor R2 is connected to the first node Q1, and the second pole of the second reset transistor R2 is connected to the leakage prevention node OF.
  • the gate of the sixth reset transistor R6 is configured to receive the global reset signal TRST, the first pole of the sixth reset transistor R6 is connected to the leakage prevention node OF, and the second pole of the sixth reset transistor R6 is connected to the first voltage terminal VGL1 to Receive the first voltage.
  • the gate of the fourth reset transistor R4 is configured to receive the global reset signal TRST, the first pole of the fourth reset transistor R4 is connected to the second node Q2, and the second pole of the fourth reset transistor R4 is connected to the leakage prevention node OF.
  • connecting the second reset transistor R2 and the leakage prevention node OF can prevent the first node Q1 from leaking through the second reset transistor R2.
  • connecting the fourth reset transistor R4 and the leakage prevention node OF can prevent the second node Q2 from leaking through the fourth reset transistor R4.
  • the sixth reset transistor R6 can be multiplexed, so that the circuit structure of the shift register unit 10 can be simplified.
  • the first leakage prevention electronic circuit 410 includes a first leakage prevention transistor A1
  • the second leakage prevention electronic circuit 420 includes a second leakage prevention transistor A2.
  • the gate of the first leakage prevention transistor A1 is connected to the first node Q1, the first pole of the first leakage prevention transistor A1 is configured to receive the second voltage VDD, and the second pole of the first leakage prevention transistor A1 is connected to the leakage prevention node OF connection.
  • the gate and the first electrode of the second leakage prevention transistor A2 are configured to be connected to the leakage prevention node OF, and the second electrode of the second leakage prevention transistor A2 is configured to be connected to the first voltage terminal VGL1 to receive the first voltage.
  • the shift register unit 10 may also be implemented as the circuit structure shown in FIG. 17. Only the differences between the shift register unit 10 shown in FIG. 17 and the shift register unit 10 shown in FIG. 16 will be described below, and the similarities will not be repeated.
  • the second input circuit 210 includes only the third input transistor B3 and does not include the fourth input transistor B4.
  • the first input signal STU1 may charge the first node Q1 through the first input transistor B1 and the second input transistor B2, and the first input signal STU1 may charge the second node Q1 through the first input transistor B1 and the third input transistor B3.
  • Q2 is charged, that is, when the first node Q1 and the second node Q2 are charged, the first input transistor B1 is multiplexed, so that one transistor can be saved, and the circuit structure of the shift register unit 10 is further simplified.
  • the fifth reset circuit 180 includes only the first reset transistor R1 and does not include the fifth reset transistor R5.
  • the first node Q1 can be reset through the first reset transistor R1 and the second leakage prevention transistor A2; at the same time, the third reset transistor R3 and the second leakage prevention transistor A2 can be used.
  • a reset operation is performed on the second node Q2. That is, when the first node Q1 and the second node Q2 are reset, the second leakage prevention transistor A2 is multiplexed, so that one transistor can be saved, and the circuit structure of the shift register unit 10 can be further simplified.
  • the shift register unit 10 may also be implemented as the circuit structure shown in FIG. 18. Only the differences between the shift register unit 10 shown in FIG. 18 and the shift register unit 10 shown in FIG. 17 will be described below, and the similarities will not be repeated.
  • the second leakage prevention electronic circuit 420 includes a third leakage prevention transistor A3.
  • the gate of the third leakage prevention transistor A3 is connected to the first node Q1 or the second node Q2, the first electrode of the third leakage prevention transistor A3 is connected to the leakage prevention node OF, and the second electrode of the third leakage prevention transistor A3 is connected to the A voltage terminal VGL1 is connected to receive the first voltage.
  • the second leakage-proof electronic circuit 420 does not adopt a diode connection.
  • the third anti-leakage transistor A3 is turned on, so that a conductive path is formed between the anti-leakage node OF and the first voltage terminal VGL1, thereby making the anti-leakage node
  • the level of OF is greater than the first voltage provided by the first voltage terminal VGL1.
  • the shift register unit 10 may also be implemented as the circuit structure shown in FIG. 19. Only the differences between the shift register unit 10 shown in FIG. 19 and the shift register unit 10 shown in FIG. 17 will be described below, and the similarities will not be repeated.
  • the third control circuit 160 includes a sixth control transistor E6, the common control circuit 161 includes a seventh control transistor E7, and the fifth control circuit 260 includes an eighth control transistor E8.
  • the gate of the sixth control transistor E6 is connected to the third node H, the first electrode of the sixth control transistor E6 is connected to the fifth node QB_A, and the second electrode of the sixth control transistor E6 is connected to the common control node CC.
  • the gate of the seventh control transistor E7 is configured to receive the first clock signal CLKA, the first electrode of the seventh control transistor E7 is connected to the common control node CC, and the second electrode of the seventh control transistor E7 is connected to the first voltage terminal VGL1 .
  • the gate of the eighth control transistor E8 is connected to the third node H, the first electrode of the eighth control transistor E8 is connected to the sixth node QB_B, and the second electrode of the eighth control transistor E8 is connected to the common control node CC.
  • the seventh control transistor E7 can be multiplexed by setting the common control node CC, so that the circuit structure can be simplified.
  • the shift register unit 10 may also be implemented as the circuit structure shown in FIG. 20. Only the differences between the shift register unit 10 shown in FIG. 20 and the shift register unit 10 shown in FIG. 16 will be described below, and the similarities will not be repeated.
  • the fifth reset circuit 180 includes only the first reset transistor R1 and does not include the fifth reset transistor R5.
  • the sixth reset circuit 190 includes only the second reset transistor R2 and does not include the sixth reset transistor R6.
  • the shift register unit 10 may also be implemented as the circuit structure shown in FIG. 21. Only the differences between the shift register unit 10 shown in FIG. 21 and the shift register unit 10 shown in FIG. 20 will be described below, and the similarities will not be repeated.
  • the second input circuit 210 only includes the third input transistor B3 and does not include the fourth input transistor B4, thereby further saving the number of transistors and further simplifying the circuit structure.
  • the shift register unit provided by the embodiment of the present disclosure can avoid the leakage of the first node Q1 and the second node Q2, and prevent the display device adopting the shift register unit from causing display failure.
  • the circuit structure can be simplified, so that the frame size of the display device adopting the shift register unit can be reduced, and the PPI of the display device can be improved.
  • the first capacitor C1 can be used to maintain the potential at the third node H
  • the second capacitor C2 can be used to maintain the potential at the first node Q1.
  • the third capacitor C3 maintains the potential at the second node Q2.
  • the first capacitor C1, the second capacitor C2, and the third capacitor C3 can be capacitive devices manufactured by a process, for example, a capacitor device can be realized by manufacturing a special capacitor electrode, and each electrode of the capacitor can pass through a metal layer, a semiconductor layer (for example, Doped polysilicon), etc., or in some examples, by designing circuit wiring parameters so that the first capacitor C1, the second capacitor C2, and the third capacitor C3 can also be realized by the parasitic capacitances between the various devices.
  • a capacitor device can be realized by manufacturing a special capacitor electrode, and each electrode of the capacitor can pass through a metal layer, a semiconductor layer (for example, Doped polysilicon), etc., or in some examples, by designing circuit wiring parameters so that the first capacitor C1, the second capacitor C2, and the third capacitor C3 can also be realized by the parasitic capacitances between the various devices.
  • connection mode of the first capacitor C1, the second capacitor C2, and the third capacitor C3 is not limited to the above described mode, and may also be other applicable connection modes, as long as the storage and writing to the third node H, the first node Q1 and The level of the second node Q2 is sufficient.
  • the gate driving circuit 20 includes a plurality of cascaded shift register units 10, of which any one or more shift register units 10 may adopt the structure of the shift register unit 10 provided by the embodiment of the present disclosure or a modification thereof.
  • A1, A2, A3, A4, A5, and A6 in FIG. 22 represent the subunits in the shift register unit 10.
  • A1, A3, and A5 represent the first subunit of the three shift register units 10, A2, A4 and A6 respectively represent the second subunit of the three shift register units 10.
  • each shift register unit 10 includes a first sub-unit and a second sub-unit to output the first output signal OUT1 and the second output signal OUT2, respectively.
  • the gate driving circuit 20 is used to drive a display panel
  • the first output signal OUT1 and the second output signal OUT2 can respectively drive a row of sub-pixel units in the display panel.
  • A1, A2, A3, A4, A5, and A6 can drive the first row, second row, third row, fourth row, fifth row, and sixth row sub-pixel units of the display panel, respectively.
  • the gate driving circuit 20 provided by the embodiment of the present disclosure can share the blanking input subunit, thereby reducing the frame size of the display device using the gate driving circuit and improving the PPI of the display device. At the same time, random compensation can be implemented, so that poor display problems such as scan lines and uneven display brightness caused by line-by-line sequential compensation can be avoided.
  • the following describes the signal lines in the gate driving circuit 20 by taking the gate driving circuit 20 shown in FIG. 22 as an example.
  • the gate driving circuit 20 includes a first sub-clock signal line CLK_1, a second sub-clock signal line CLK_2, and a third sub-clock signal line CLK_3.
  • the first sub-unit in the 3n-2 stage shift register unit is connected to the first sub-clock signal line CLK_1 to receive the second clock signal CLKB of the 3n-2 stage shift register unit; the 3n-1 stage shift register
  • the first sub-unit and the second sub-clock signal line CLK_2 in the unit are connected to receive the second clock signal CLKB of the 3n-1th stage shift register unit; the first and third sub-units in the 3n-th stage shift register unit
  • the sub-clock signal line CLK_3 is connected to receive the second clock signal CLKB of the 3n-th stage shift register unit; n is an integer greater than zero.
  • the shift register units 10 are cascaded, it is only necessary to sequentially provide the second clock signal CLKB to the first sub-units in each stage of the shift register unit 10, and the second clock signal CLKB can be used as The shift signal CR is output to complete the scan shift.
  • the gate driving circuit 20 further includes a fourth sub-clock signal line CLK_4, a fifth sub-clock signal line CLK_5, a sixth sub-clock signal line CLK_6, a seventh sub-clock signal line CLK_7, and an eighth sub-clock signal line.
  • the first subunit in the 3n-2th stage shift register unit and the fourth subclock signal line CLK_4 are connected to receive the third clock signal CLKC of the 3n-2th stage shift register unit, and the 3n-2th stage shift register
  • the second sub-unit in the unit and the fifth sub-clock signal line CLK_5 are connected to receive the fourth clock signal CLKD of the 3n-2th stage shift register unit.
  • the first sub-unit in the 3n-1 stage shift register unit and the sixth sub-clock signal line CLK_6 are connected to receive the third clock signal CLKC of the 3n-1 stage shift register unit, and the 3n-1 stage shift register
  • the second sub-unit in the unit is connected to the seventh sub-clock signal line CLK_7 to receive the fourth clock signal CLKD of the 3n-1 stage shift register unit.
  • the first sub-unit and the eighth sub-clock signal line CLK_8 in the 3n-th stage shift register unit are connected to receive the third clock signal CLKC of the 3n-th stage shift register unit, and the second sub-unit in the 3n-th stage shift register unit
  • the unit is connected to the ninth sub-clock signal line CLK_9 to receive the fourth clock signal CLKD of the 3n-th stage shift register unit.
  • the gate drive circuit 20 provided by the embodiment of the present disclosure can use a 6CLK clock signal, which can make the waveforms of the drive signal output by the gate drive circuit 20 overlap, for example, can increase the precharge time of each row of sub-pixel units , So that the gate drive circuit can be applied to high-frequency scanning display.
  • the embodiment of the present disclosure does not limit the type of clock signal used. For example, clock signals such as 8CLK and 10CLK may also be used.
  • the gate driving circuit 20 further includes a tenth sub-clock signal line CLK_10, an eleventh sub-clock signal line CLK_11, and a twelfth sub-clock signal line CLK_12.
  • the first sub-unit and the second sub-unit in each stage of the shift register unit 10 are connected to the tenth sub-clock signal line CLK_10 to receive the global reset signal TRST.
  • the selection input circuit 310 in each stage of the shift register unit 10 is connected to the eleventh sub-clock signal line CLK_11 to receive the selection control signal OE.
  • the first subunit, the second subunit, and the third input circuit 320 in each stage of the shift register unit 10 are connected to the twelfth subclock signal line CLK_12 to receive the first clock signal CLKA.
  • the gate driving circuit 20 further includes a thirteenth sub-clock signal line CLK_13 and a fourteenth sub-clock signal line CLK_14.
  • the first sub-unit of each stage of shift register unit 10 is connected to the thirteenth sub-clock signal line CLK_13 to receive the third voltage VDD_A; the second sub-unit of each stage of shift register unit 10 is connected to The fourteenth sub-clock signal line CLK_14 is connected to receive the fourth voltage VDD_B.
  • the gate driving circuit 20 further includes a fifteenth sub-clock signal line CLK_15, a first sub-unit and a second sub-unit in the first-stage shift register unit 10, and a fifteenth sub-clock signal line CLK_15 Connect to receive the first input signal STU1.
  • the first subunit and the second subunit in the shift register unit 10 of the other stages are the same as the first subunit in the shift register unit 10 of the previous stage.
  • the first and second subunits in the other stages of shift register units 10 are connected to the first subunit in the last two stages of shift register units 10 to receive shift signals CR and as the display reset signal STD.
  • cascade relationship shown in FIG. 22 is only an example. According to the description of the present disclosure, other cascade manners may also be adopted according to actual conditions.
  • the shift register unit 10 in the gate driving circuit 20 shown in FIG. 22 may adopt the circuit structure shown in FIG. 21, and FIG. 23 shows the gate driving circuit 20 shown in FIG. 22. Signal timing diagram at work.
  • H ⁇ 5> represents the third node H in the third-stage shift register unit 10
  • the third-stage shift register unit 10 corresponds to the fifth and sixth rows of sub-pixel units in the display panel.
  • N ⁇ 5> represents the fourth node N in the third stage shift register unit 10.
  • Q1 ⁇ 1> and Q2 ⁇ 2> respectively represent the first node Q1 and the second node Q2 in the first stage shift register unit 10;
  • Q1 ⁇ 5> and Q2 ⁇ 6> respectively represent the third stage shift register unit 10 In the first node Q1 and the second node Q2.
  • the number in parentheses indicates the number of rows of sub-pixel units in the display panel corresponding to the node, and the following embodiments are the same, and will not be repeated.
  • OUT1 ⁇ 1> and OUT2 ⁇ 2> respectively represent the first output signal OUT1 and the second output signal OUT2 output by the shift register unit 10 of the first stage.
  • OUT1 ⁇ 3> and OUT2 ⁇ 4> respectively represent the first output signal OUT1 and the second output signal OUT2 output by the second stage shift register unit 10;
  • OUT1 ⁇ 5> and OUT2 ⁇ 6> respectively represent the third stage The first output signal OUT1 and the second output signal OUT2 output by the shift register unit 10.
  • CR ⁇ 1>, CR ⁇ 3>, and CR ⁇ 5> are the shift signals CR output by the first, second, and third-stage shift register units 10, respectively.
  • CR ⁇ 1> is the same as OUT1 ⁇ 1>
  • CR ⁇ 3> is the same as OUT1 ⁇ 3>
  • CR ⁇ 5> is the same as OUT1 ⁇ 5>.
  • 1F represents the first frame
  • DS represents the display period in the first frame
  • BL represents the blanking period in the first frame.
  • the third voltage VDD_A is at a low level
  • the fourth voltage VDD_B is at a high level as an example for illustration, but the embodiment of the present disclosure is not limited to this.
  • the signal level in the signal timing diagram shown in FIG. 23 is only schematic and does not represent a true level value.
  • the tenth sub-clock signal line CLK_10 and the eleventh sub-clock signal line CLK_11 provide a high level
  • the second reset transistor R2 and the fourth reset transistor R4 in each stage of the shift register unit 10 Turn on, so that the first node Q1 and the second node Q2 in each stage of the shift register unit 10 can be reset; the fifth input transistor B5 and the sixth input transistor B6 in each stage of the shift register unit 10 are turned on Since the second input signal STU2 received at this time is low, the third node H in each stage of the shift register unit 10 can be reset, so as to realize a global reset before the start of the first frame 1F.
  • the working process of the third-stage shift register unit 10 (that is, the sub-pixel units corresponding to the fifth and sixth rows of the display panel) is described as follows.
  • the shift signal CR ⁇ 3> output by the first sub-unit of the second-stage shift register unit 10 is high, that is, the first input signal received by the third-stage shift register unit 10 STU1 is high, so the first input transistor B1, the second input transistor B2, and the third input transistor B3 are turned on.
  • the high-level first input signal STU1 charges the first node Q1 ⁇ 5> through the first input transistor B1 and the second input transistor B2, thereby pulling up the first node Q1 ⁇ 5> to a high level;
  • the first input signal STU1 can also charge the second node Q2 ⁇ 6> through the first input transistor B1 and the third input transistor B3, thereby pulling the second node Q2 ⁇ 6> to a high level.
  • the second output transistor D2 is turned on under the control of the first node Q1 ⁇ 5>, but because the third clock signal CLKC provided by the eighth sub-clock signal line CLK_8 is low at this time, the third-stage shift register unit 10
  • the first output signal OUT1 ⁇ 5> output is low
  • the third output transistor D3 is turned on under the control of the second node Q2 ⁇ 6>, but at this time, because the fourth sub-clock signal line CLK_9 provides the fourth The clock signal CLKD is low, so the second output signal OUT2 ⁇ 6> output by the third-stage shift register unit 10 is low; at this stage, the first output signal in the third-stage shift register unit 10
  • the third clock signal CLKC provided by the eighth sub-clock signal line CLK_8 becomes a high level, and the potential of the first node Q1 ⁇ 5> is further pulled up due to the bootstrap effect, so the second output The transistor D2 is kept on, so that the first output signal OUT1 ⁇ 5> output by the third-stage shift register unit 10 becomes a high level.
  • the fourth clock signal CLKD provided by the ninth sub-clock signal line CLK_9 is still at a low level at this time, the second output signal OUT2 ⁇ 6> output by the third-stage shift register unit 10 continues to be at a low level.
  • the fourth clock signal CLKD provided by the ninth sub-clock signal line CLK_9 becomes a high level
  • the potential of the second node Q2 ⁇ 6> is further pulled up due to the bootstrap effect
  • the third output transistor D3 remains on, so that the second output signal OUT2 ⁇ 6> output by the third-stage shift register unit 10 becomes a high level.
  • the first node Q1 ⁇ 5> still maintains a high level, so the second output transistor D2 is turned on.
  • the third clock signal CLKC provided by the eighth sub-clock signal line CLK_8 becomes a low level
  • the first output signal OUT1 ⁇ 5> output by the third-stage shift register unit 10 becomes a low level.
  • the potential of the first node Q1 ⁇ 5> will also drop.
  • the second node Q2 ⁇ 6> still maintains a high level, so the third output transistor D3 is turned on.
  • the fourth clock signal CLKD provided by the ninth sub-clock signal line CLK_9 becomes a high level
  • the second output signal OUT2 ⁇ 6> output by the third-stage shift register unit 10 becomes a low level.
  • the potential of the second node Q2 ⁇ 6> will also drop.
  • the output signal of each three-stage shift register unit 10 (each stage outputs the first output signal OUT1 and the second output signal OUT2 in turn) is a cycle, and because The third-stage shift register unit 10 receives the shift signal CR output by the fifth-stage shift register unit 10 as the display reset signal STD, so at this stage when the third clock signal CLKC provided by the sixth sub-clock signal line CLK_6 becomes At a high level, the display reset signal STD received by the third-stage shift register unit 10 is also at a high level, so that the first reset transistor R1 and the third reset transistor R3 are turned on, so that the low-level first voltage can be used.
  • the pull-down reset is completed for the first node Q1 ⁇ 5> and the second node Q2 ⁇ 6>.
  • the third-stage shift register unit 10 drives the sub-pixels in the fifth and sixth rows of the display panel to complete the display, and so on, the fourth-stage and fifth-stage shift register units 10 drive the sub-pixels in the display panel row by row.
  • the unit completes one frame of display drive. So far, the display period of the first frame ends.
  • the third node H is also charged in the display period DS of the first frame 1F.
  • the display period DS of the first frame 1F also proceed as follows.
  • the eleventh sub-clock signal line CLK_11 provides the same signal as the shift signal CR ⁇ 5> output by the third-stage shift register unit 10, so the fifth input transistor B5 And the sixth input transistor B6 is turned on.
  • the second input signal STU2 received by the third-stage shift register unit 10 can be the same as the shift signal CR ⁇ 5>, so that the high-level second input signal STU2 can charge the third node H ⁇ 5>, The third node H ⁇ 5> is pulled up to a high level.
  • the foregoing charging process for the third node H ⁇ 5> is only an example, and the embodiments of the present disclosure include but are not limited to this.
  • the second input signal STU2 received by the third-stage shift register unit 10 may also be the same as the shift signal CR output by the other-stage shift register unit 10, and at the same time, the sum of the signal provided to the eleventh sub-clock signal line CLK_11
  • the signal timing of the second input signal STU2 may be the same.
  • the high potential of the third node H ⁇ 5> can be maintained until the blanking period BL of the first frame 1F.
  • the following operations are performed in the blanking period BL of the first frame 1F.
  • the first clock signal CLKA provided by the twelfth sub-clock signal line CLK_12 is at a high level. Since the third node H ⁇ 5> maintains a high level at this stage, the seventh input transistor B7 is turned on ON, the high-level first clock signal CLKA is transmitted to the fourth node N ⁇ 5> through the seventh input transistor B7, so that the fourth node N ⁇ 5> becomes a high level.
  • the first transfer transistor T1, the second transfer transistor T2, and the third transfer transistor T3 are turned on under the control of the high-level first clock signal CLKA, so the high-level first clock signal CLKA can be connected to the first node Q1. ⁇ 5> and the second node Q2 ⁇ 6> are charged, and the levels of the first node Q1 ⁇ 5> and the second node Q2 ⁇ 6> are pulled up.
  • the third node H ⁇ 5> will be coupled and pulled up, so that The third node H ⁇ 5> can be maintained at a higher high potential to ensure that the seventh input transistor B7 is completely turned on.
  • the first clock signal CLKA provided by the twelfth sub-clock signal line CLK_12 changes from a high level to a low level, so that the fourth node N ⁇ 5> becomes a low level. Due to the coupling effect of the first capacitor C1, The potential of the third node H ⁇ 5> will also drop.
  • the third clock signal CLKC provided by the eighth sub-clock signal line CLK_8 becomes a high level, and the potential of the first node Q1 ⁇ 5> is further pulled up due to the bootstrap effect, so the second output The transistor D2 is kept on, so that the first output signal OUT1 ⁇ 5> output by the third-stage shift register unit 10 becomes a high level.
  • the fourth clock signal CLKD provided by the ninth sub-clock signal line CLK_9 is still low at this time, the second output signal OUT2 ⁇ 6> output by the third-stage shift register unit 10 is low.
  • the first output signal OUT1 ⁇ 5> output in the eighth stage 8 can be used to drive the sensing transistors in the sub-pixel units in the display panel to achieve external compensation.
  • the first node Q1 ⁇ 5> still maintains a high level, so the second output transistor D2 is turned on.
  • the third clock signal CLKC provided by the eighth sub-clock signal line CLK_8 becomes a low level
  • the first output signal OUT1 ⁇ 5> output by the third-stage shift register unit 10 becomes a low level.
  • the potential of the first node Q1 ⁇ 5> will also drop.
  • the tenth sub-clock signal line CLK_10 and the eleventh sub-clock signal line CLK_11 provide a high level, and the second reset transistor R2 and the fourth reset transistor R4 in the shift register unit 10 of each stage are turned on. Therefore, the first node Q1 and the second node Q2 in each stage of the shift register unit 10 can be reset; the fifth input transistor B5 and the sixth input transistor B6 in each stage of the shift register unit 10 are turned on Since the second input signal STU2 received at this time is low, the third node H in each stage of the shift register unit 10 can be reset to complete the global reset.
  • the blanking period of the first frame is used to output driving signals corresponding to the fifth row of sub-pixel units of the display panel as an example. limited. For example, when it is necessary to output the driving signal corresponding to the sub-pixel unit of the nth row of the display panel during the blanking period of a certain frame, the corresponding third node H needs to be pulled up high in the display period DS of the frame.
  • a high-level first clock signal CLKA is provided to raise the potential of the first node Q1 or the second node Q2, and then when a high-level drive signal needs to be output , Provide a high-level third clock signal CLKC or a fourth clock signal CLKD, n is an integer greater than zero.
  • the same timing of two signals refers to time synchronization at a high level, and the amplitude of the two signals is not required to be the same.
  • Some embodiments of the present disclosure also provide a gate driving circuit 20, as shown in FIG. 24, which is a signal timing diagram corresponding to the gate driving circuit 20 shown in FIG. 24 during operation. The following describes the difference between the gate driving circuit 20 shown in FIG. 24 and the gate driving circuit 20 shown in FIG. 22.
  • the gate drive circuit 20 uses a clock signal of 10CLK, the fourth sub-clock signal line CLK_4, the fifth sub-clock signal line CLK_5, the sixth sub-clock signal line CLK_6, Seventh sub-clock signal line CLK_7, eighth sub-clock signal line CLK_8, ninth sub-clock signal line CLK_9, fifteenth sub-clock signal line CLK_15, sixteenth sub-clock signal line CLK_16, seventeenth sub-clock signal line CLK_17 A total of ten clock signal lines and the eighteenth sub-clock signal line CLK_18 provide drive signals output row by row to the shift register units 10 of each stage.
  • the clock signal of 10CLK is used to further increase the precharge time of each row of sub-pixel units, so that the gate driving circuit can be applied to higher frequency scanning display.
  • the other-stage shift register unit 10 in addition to the first two-stage shift register unit 10, is connected to the first subunit in the first two-stage shift register unit 10 to receive the shift register unit 10.
  • the bit signal CR is used as the first input signal STU1.
  • the other-stage shift register unit 10 is connected to the first sub-unit in the last four-stage shift register unit 10 to receive the shift signal CR and serve as the display reset signal STD.
  • the tenth sub-clock signal line CLK_10 is connected to the first and second sub-units (ie, A1, A2, A3, and A4) in the first two-stage shift register unit 10 to provide the first input signal STU1, and the tenth sub-clock signal line CLK_10 is also connected to the shift register unit 10 of other stages to provide a global reset signal TRST.
  • the number of clock signal lines can be saved, so that the frame size of the display device using the gate driving circuit can be reduced, and the PPI of the display device can be improved.
  • the first output signal OUT1 ⁇ 11> can be used to drive the eleventh row of sub-pixel units to complete external compensation.
  • the display device 1 includes the gate driving circuit 20 provided by the embodiments of the present disclosure and a plurality of sub-pixel units 510 arranged in an array.
  • the display device 1 further includes a display panel 50, and a pixel array composed of a plurality of sub-pixel units 510 is arranged in the display panel 50.
  • the first output signal OUT1 and the second output signal OUT2 output by each shift register unit 10 in the gate driving circuit 20 are respectively provided to the sub-pixel units 510 in different rows.
  • the gate driving circuit 20 connects with each other through the gate line GL.
  • the sub-pixel unit 510 is electrically connected.
  • the gate driving circuit 20 is used to provide a driving signal to the pixel array.
  • the driving signal can drive the scan transistor and the sensing transistor in the sub-pixel unit 510.
  • the display device 1 may further include a data driving circuit 30 for providing data signals to the pixel array.
  • the data driving circuit 30 is electrically connected to the sub-pixel unit 510 through the data line DL.
  • the display device 1 in this embodiment can be: liquid crystal panel, liquid crystal TV, display, OLED panel, OLED TV, electronic paper display device, mobile phone, tablet computer, notebook computer, digital photo frame, navigator, etc. Products or parts with display functions.
  • Some embodiments of the present disclosure also provide a driving method, which can be used to drive the shift register unit 10 provided by the embodiment of the present disclosure.
  • a plurality of the shift register units 10 can be cascaded to construct the gate provided by an embodiment of the present disclosure.
  • a pole driving circuit which is used to drive the display panel to display at least one frame.
  • the driving method includes: the leakage prevention circuit 400 controls the level of the leakage prevention node OF under the control of the level of the first node Q1, so that a conductive path is formed between the leakage prevention node OF and the first voltage terminal VGL1, and The circuit connected between the first node Q1 and the leakage prevention node OF is turned off.

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  • Shift Register Type Memory (AREA)

Abstract

一种移位寄存器单元、栅极驱动电路、显示装置及驱动方法。该移位寄存器单元(10)包括第一子单元(100)和防漏电电路(400)，第一子单元(100)包括第一输入电路(110)和第一输出电路(120)。第一输入电路(110)被配置为响应于第一输入信号(STU1)对第一节点(Q1)的电平进行控制，第一输出电路(120)被配置为在第一节点(Q1)的电平的控制下在输出端提供输出信号，防漏电电路(400)和第一节点(Q1)以及第一电压端(VGL1)连接，且被配置为在第一节点(Q1)的电平的控制下对防漏电节点(OF)的电平进行控制，使得防漏电节点(OF)和第一电压端(VGL1)之间形成导电路径，且使得连接于第一节点(Q1)和防漏电节点(OF)之间的电路截止。该移位寄存器单元(10)可以避免第一节点(Q1)发生漏电，同时还可以简化电路结构，从而减小采用该移位寄存器单元(10)的显示装置(1)的边框尺寸。

Description

移位寄存器单元、栅极驱动电路、显示装置及驱动方法
本申请要求于2019年1月18日递交的中国专利申请第201910049743.0号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种移位寄存器单元、栅极驱动电路、显示装置及驱动方法。
背景技术
在显示领域特别是OLED(Organic Light-Emitting Diode，有机发光二极管)显示面板中，栅极驱动电路目前一般集成在栅极驱动芯片(GATE IC)中。集成电路(IC)设计中，芯片的面积是影响芯片成本的主要因素，如何有效地降低芯片面积是技术开发人员需要着重考虑的。
发明内容
本公开至少一实施例提供一种移位寄存器单元，包括第一子单元和防漏电电路，所述第一子单元包括第一输入电路和第一输出电路。所述第一输入电路被配置为响应于第一输入信号对第一节点的电平进行控制，所述第一输出电路被配置为在所述第一节点的电平的控制下在输出端提供输出信号，所述防漏电电路和所述第一节点以及第一电压端连接，且被配置为在所述第一节点的电平的控制下对防漏电节点的电平进行控制，使得所述防漏电节点和所述第一电压端之间形成导电路径，且使得连接于所述第一节点和所述防漏电节点之间的电路截止。
例如，在本公开一实施例提供的移位寄存器单元中，所述防漏电电路包括第一防漏电子电路和第二防漏电子电路。所述第一防漏电子电路和所述第一节点以及所述防漏电节点连接，且被配置为在所述第一节点的电平的控制下对所述防漏电节点的电平进行控制；所述第二防漏电子电路和所述防漏电 节点以及所述第一电压端连接，所述第二防漏电子电路被配置为在所述防漏电节点的电平或所述第一节点的电平的控制下，使得所述防漏电节点和所述第一电压端之间形成导电路径。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一防漏电子电路包括第一防漏电晶体管，所述第二防漏电子电路包括第二防漏电晶体管；所述第一防漏电晶体管的栅极和所述第一节点连接，所述第一防漏电晶体管的第一极被配置为接收第二电压，所述第一防漏电晶体管的第二极和所述防漏电节点连接；所述第二防漏电晶体管的栅极以及第一极被配置为和所述防漏电节点连接，所述第二防漏电晶体管的第二极被配置为和所述第一电压端连接以接收所述第一电压。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一防漏电子电路包括第一防漏电晶体管，所述第二防漏电子电路包括第三防漏电晶体管；所述第一防漏电晶体管的栅极和所述第一节点连接，所述第一防漏电晶体管的第一极被配置为接收第二电压，所述第一防漏电晶体管的第二极和所述防漏电节点连接；所述第三防漏电晶体管的栅极和所述第一节点连接，所述第三防漏电晶体管的第一极和所述防漏电节点连接，所述第三防漏电晶体管的第二极被配置为和所述第一电压端连接以接收所述第一电压。
例如，本公开一实施例提供的移位寄存器单元还包括消隐输入子单元，所述消隐输入子单元和所述第一节点连接，且被配置为接收选择控制信号并对所述第一节点的电平进行控制。
例如，在本公开一实施例提供的移位寄存器单元中，所述消隐输入子单元包括选择控制电路、第三输入电路和第一传输电路；所述选择控制电路被配置为响应于所述选择控制信号利用第二输入信号对第三节点的电平进行控制，并保持所述第三节点的电平；所述第三输入电路被配置为在所述第三节点的电平的控制下将第一时钟信号传输至第四节点；所述第一传输电路和所述第一节点、所述第四节点以及所述防漏电节点电连接，且被配置为响应于所述第一时钟信号对所述第一节点的电平以及所述防漏电节点的电平进行控制。
例如，本公开一实施例提供的移位寄存器单元还包括第二子单元。所述第二子单元包括第二输入电路和第二输出电路，所述第二输入电路被配置为 响应于所述第一输入信号对第二节点的电平进行控制，所述第二输出电路被配置为在所述第二节点的电平的控制下输出第二输出信号；所述消隐输入子单元还包括第二传输电路，所述第二传输电路和所述第二节点以及所述防漏电节点电连接，且被配置为响应于所述第一时钟信号将所述防漏电节点的电平传输至所述第二节点。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一传输电路包括第一传输晶体管和第二传输晶体管，所述第二传输电路包括第三传输晶体管；所述第一传输晶体管的栅极被配置为接收所述第一时钟信号，所述第一传输晶体管的第一极和所述第四节点连接，所述第一传输晶体管的第二极和所述防漏电节点连接；所述第二传输晶体管的栅极被配置为接收所述第一时钟信号，所述第二传输晶体管的第一极和所述防漏电节点连接，所述第二传输晶体管的第二极和所述第一节点连接；所述第三传输晶体管的栅极被配置为接收所述第一时钟信号，所述第三传输晶体管的第一极和所述防漏电节点连接，所述第三传输晶体管的第二极和所述第二节点连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一输入电路包括第一输入晶体管和第二输入晶体管，所述第二输入电路包括第三输入晶体管；所述第一输入晶体管的栅极以及第一极被配置为接收所述第一输入信号，所述第一输入晶体管的第二极和所述防漏电节点连接；所述第二输入晶体管的栅极被配置为接收所述第一输入信号，所述第二输入晶体管的第一极和所述防漏电节点连接，所述第二输入晶体管的第二极和所述第一节点连接；所述第三输入晶体管的栅极被配置为接收所述第一输入信号，所述第三输入晶体管的第一极和所述防漏电节点连接，所述第三输入晶体管的第二极和所述第二节点连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述第二输入电路还包括第四输入晶体管；所述第四输入晶体管的栅极以及第一极被配置为接收所述第一输入信号，所述第四输入晶体管的第二极和所述防漏电节点连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一子单元还包括第一控制电路、第一复位电路、第二复位电路、移位信号输出端以及第一输出信号端；所述第二子单元还包括第二控制电路、第三复位电路、第四复位电路以及第二输出信号端；所述输出信号包括移位信号和第一输出信号， 所述输出端包括所述移位信号输出端和所述第一输出信号端，所述移位信号输出端被配置为输出所述移位信号，所述第一输出信号端被配置为输出所述第一输出信号；所述第二输出信号端被配置为输出所述第二输出信号；所述第一控制电路被配置为在所述第一节点的电平和第三电压的控制下，对第五节点的电平进行控制；所述第一复位电路被配置为在所述第五节点的电平的控制下，对所述第一节点、所述移位信号输出端和所述第一输出信号端进行复位；所述第二复位电路被配置为在第六节点的电平的控制下，对所述第一节点、所述移位信号输出端和所述第一输出信号端进行复位；所述第二控制电路被配置为在所述第二节点的电平和第四电压的控制下，对所述第六节点的电平进行控制；所述第三复位电路被配置为在所述第六节点的电平的控制下，对所述第二节点和所述第二输出信号端进行复位；所述第四复位电路被配置为在所述第五节点的电平的控制下，对所述第二节点和所述第二输出信号端进行复位。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一子单元还包括第三控制电路、第四控制电路和公共控制电路，所述第二子单元还包括第五控制电路和第六控制电路；所述第三控制电路和所述第五节点以及公共控制节点连接，且被配置为响应于所述第一时钟信号使得所述第五节点和所述公共控制节点电连接，所述公共控制电路和所述公共控制节点以及所述第一电压端电连接，且被配置为在所述第三节点的电平的控制下使得所述公共控制节点和所述第一电压端电连接，所述第四控制电路和所述第五节点以及所述第一电压端电连接，且被配置为响应于所述第一输入信号对所述第五节点的电平进行控制；所述第五控制电路和所述第六节点以及所述公共控制节点连接，且被配置为响应于所述第一时钟信号使得所述第六节点和所述公共控制节点电连接，所述第六控制电路和所述第六节点以及所述第一电压端电连接，且被配置为响应于所述第一输入信号对所述第六节点的电平进行控制。
例如，在本公开一实施例提供的移位寄存器单元中，所述第三控制电路包括第一控制晶体管，所述第四控制电路包括第二控制晶体管，所述公共控制电路包括第三控制晶体管，所述第五控制电路包括第四控制晶体管，所述第六控制电路包括第五控制晶体管；所述第一控制晶体管的栅极被配置为接收所述第一时钟信号，所述第一控制晶体管的第一极和所述第五节点连接， 所述第一控制晶体管的第二极和所述公共控制节点连接；所述第二控制晶体管的栅极被配置为接收第一输入信号，所述第二控制晶体管的第一极和所述第五节点连接，所述第二控制晶体管的第二极和所述第一电压端连接；所述第三控制晶体管的栅极和所述第三节点连接，所述第三控制晶体管的第一极和所述公共控制节点连接，所述第三控制晶体管的第二极和所述第一电压端连接；所述第四控制晶体管的栅极被配置为接收所述第一时钟信号，所述第四控制晶体管的第一极和所述第六节点连接，所述第四控制晶体管的第二极和所述公共控制节点连接；所述第五控制晶体管的栅极被配置为接收所述第一输入信号，所述第五控制晶体管的第一极和所述第六节点连接，所述第五控制晶体管的第二极和所述第一电压端连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一子单元还包括第三控制电路、第四控制电路和公共控制电路，所述第二子单元还包括第五控制电路和第六控制电路；所述第三控制电路和所述第三节点、所述第五节点以及公共控制节点连接，且被配置为在所述第三节点的电平的控制下使得所述第五节点和所述公共控制节点电连接，所述公共控制电路和所述公共控制节点以及所述第一电压端电连接，且被配置为响应于所述第一时钟信号使得所述公共控制节点和所述第一电压端电连接，所述第四控制电路和所述第五节点以及所述第一电压端电连接，且被配置为响应于所述第一输入信号对所述第五节点的电平进行控制；所述第五控制电路和所述第三节点、所述第六节点以及所述公共控制节点连接，且被配置为在所述第三节点的电平的控制下使得所述第六节点和所述公共控制节点电连接，所述第六控制电路和所述第六节点以及所述第一电压端电连接，且被配置为响应于所述第一输入信号对所述第六节点的电平进行控制。
例如，在本公开一实施例提供的移位寄存器单元中，所述第三控制电路包括第六控制晶体管，所述第四控制电路包括第二控制晶体管，所述公共控制电路包括第七控制晶体管，所述第五控制电路包括第八控制晶体管，所述第六控制电路包括第五控制晶体管；所述第六控制晶体管的栅极和所述第三节点连接，所述第六控制晶体管的第一极和所述第五节点连接，所述第六控制晶体管的第二极和所述公共控制节点连接；所述第二控制晶体管的栅极被配置为接收第一输入信号，所述第二控制晶体管的第一极和所述第五节点连 接，所述第二控制晶体管的第二极和所述第一电压端连接；所述第七控制晶体管的栅极被配置为接收所述第一时钟信号，所述第七控制晶体管的第一极和所述公共控制节点连接，所述第七控制晶体管的第二极和所述第一电压端连接；所述第八控制晶体管的栅极和所述第三节点连接，所述第八控制晶体管的第一极和所述第六节点连接，所述第八控制晶体管的第二极和所述公共控制节点连接；所述第五控制晶体管的栅极被配置为接收所述第一输入信号，所述第五控制晶体管的第一极和所述第六节点连接，所述第五控制晶体管的第二极和所述第一电压端连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一子单元还包括第五复位电路和第六复位电路，所述第二子单元还包括第七复位电路和第八复位电路；所述第五复位电路和所述第一节点以及所述防漏电节点连接，且被配置为响应于显示复位信号对所述第一节点进行复位，所述第六复位电路和所述第一节点以及所述防漏电节点连接，且被配置为响应于全局复位信号对所述第一节点进行复位；所述第七复位电路和所述第二节点以及所述防漏电节点连接，且被配置为响应于所述显示复位信号对所述第二节点进行复位，所述第八复位电路和所述第二节点以及所述防漏电节点连接，且被配置为响应于所述全局复位信号对所述第二节点进行复位。
例如，在本公开一实施例提供的移位寄存器单元中，所述第五复位电路包括第一复位晶体管，所述第六复位电路包括第二复位晶体管，所述第七复位电路包括第三复位晶体管，所述第八复位电路包括第四复位晶体管；所述第一复位晶体管的栅极被配置为接收所述显示复位信号，所述第一复位晶体管的第一极和所述第一节点连接，所述第一复位晶体管的第二极和所述防漏电节点连接；所述第二复位晶体管的栅极被配置为接收所述全局复位信号，所述第二复位晶体管的第一极和所述第一节点连接，所述第二复位晶体管的第二极和所述防漏电节点连接；所述第三复位晶体管的栅极被配置为接收所述显示复位信号，所述第三复位晶体管的第一极和所述第二节点连接，所述第三复位晶体管的第二极和所述防漏电节点连接；所述第四复位晶体管的栅极被配置为接收所述全局复位信号，所述第四复位晶体管的第一极和所述第二节点连接，所述第四复位晶体管的第二极和所述防漏电节点连接。
本公开至少一实施例还提供一种栅极驱动电路，包括多个级联的如本公 开的实施例提供的任一移位寄存器单元。
本公开至少一实施例还提供一种显示装置，包括如本公开的实施例提供的任一栅极驱动电路。
本公开至少一实施例还提供一种移位寄存器单元的驱动方法，包括：所述防漏电电路在所述第一节点的电平的控制下对防漏电节点的电平进行控制，使得所述防漏电节点和所述第一电压端之间形成导电路径，且使得连接于所述第一节点和所述防漏电节点之间的电路截止。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种移位寄存器单元的示意图；
图2为本公开一些实施例提供的一种移位寄存器单元的示意图；
图3为本公开一些实施例提供的一种防漏电电路的电路图；
图4为本公开一些实施例提供的另一种防漏电电路的电路图；
图5为本公开一些实施例提供的另一种移位寄存器单元的示意图；
图6为本公开一些实施例提供的再一种移位寄存器单元的示意图；
图7为本公开一些实施例提供的再一种移位寄存器单元的示意图；
图8为本公开一些实施例提供的一种消隐输入子单元的电路图；
图9A至图9D为本公开的一些实施例提供的四种消隐输入子单元的电路图；
图10为本公开一些实施例提供的再一种移位寄存器单元的示意图；
图11为本公开一些实施例提供的再一种移位寄存器单元的示意图；
图12为本公开一些实施例提供的再一种移位寄存器单元的示意图；
图13为本公开一些实施例提供的一种移位寄存器单元的电路图；
图14A至图14C为本公开的一些实施例提供的三种第一输入电路的电路图；
图15为本公开一些实施例提供的另一种移位寄存器单元的电路图；
图16为本公开一些实施例提供的再一种移位寄存器单元的电路图；
图17为本公开一些实施例提供的再一种移位寄存器单元的电路图；
图18为本公开一些实施例提供的再一种移位寄存器单元的电路图；
图19为本公开一些实施例提供的再一种移位寄存器单元的电路图；
图20为本公开一些实施例提供的再一种移位寄存器单元的电路图；
图21为本公开一些实施例提供的又一种移位寄存器单元的电路图；
图22为本公开一些实施例提供的一种栅极驱动电路的示意图；
图23为本公开一些实施例提供的一种对应于图22所示的栅极驱动电路工作时的信号时序图；
图24为本公开一些实施例提供的另一种栅极驱动电路的示意图；
图25为本公开一些实施例提供的一种对应于图24所示的栅极驱动电路工作时的信号时序图；以及
图26为本公开一些实施例提供的一种显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本公开的实施例中，例如，当各个电路实现为N型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如截止)。
又例如，当各个电路实现为P型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如截止)。
并且，术语“上拉”、“下拉”的具体含义也将根据所采用的晶体管的具体类型而相应调整，只要能实现对于晶体管的控制以实现相应的开关功能。
目前用于OLED的栅极驱动电路通常要用三个子电路组合而成，即检测电路、显示电路和输出两者复合脉冲的连接电路(或门电路)，但是这样的电路结构非常复杂，无法满足显示面板的高分辨率窄边框的要求。
图1示出了一种移位寄存器单元，例如，该移位寄存器单元包括输入电路610和输出电路620。输入电路610被配置为响应于第一输入信号STU1对第一节点Q1的电平进行控制，输出电路620被配置为在第一节点Q1的电平的控制下在输出端提供输出信号OUT。例如，当多个如图1中所示的移位寄存器单元级联时可以构成一个栅极驱动电路，该栅极驱动电路可以用于驱动显示装置进行显示操作。例如，当第一节点Q1的电平为高电平时，输出电路620在第一节点Q1的电平的控制下可以提供输出信号OUT，例如，该输出信号OUT可以提供至显示面板中的一行像素单元以用于驱动该行像素单元进行显示。
例如，在图1所示的移位寄存器单元中，为了使得该移位寄存器单元更好地工作，还需要设置其它电路来更好地控制第一节点Q1的电平，例如，设置一个或多个和第一节点Q1连接的复位电路。例如，当该移位寄存器单元完成输出信号OUT的输出后，采用复位电路对第一节点Q1的电平进行复位。例如，该复位操作使得第一节点Q1的电平从高电平变为低电平。例如，当第一节点Q1的电平为高电平时，如果上述复位电路不能保持完全地截止， 则第一节点Q1可能会通过这些复位电路中的一个或多个发生漏电，即第一节点Q1通过图1中虚线表示的漏电路径发生漏电，从而会导致在输出电路620进行输出时第一节点Q1的电平不能保持在一个较高的电平，从而可能会导致输出信号OUT出现偏差，进而导致采用该移位寄存器单元作为栅极驱动电路的显示面板发生显示不良。
需要说明的是，在本公开的一些实施例中，将和第一节点Q1连接的、可能使得第一节点Q1发生漏电的电路路径称为漏电路径，该漏电路径可能包括一个或多个电路(或子电路)，例如，包括对第一节点Q1进行复位操作的复位电路等，以下各实施例与此相同，不再赘述。
针对上述漏电问题，本公开的至少一实施例提供一种移位寄存器单元，该移位寄存器单元包括第一子单元和防漏电电路，第一子单元包括第一输入电路和第一输出电路。第一输入电路被配置为响应于第一输入信号对第一节点的电平进行控制，第一输出电路被配置为在第一节点的电平的控制下在输出端提供输出信号，防漏电电路和第一节点以及第一电压端连接，且被配置为在第一节点的电平的控制下对防漏电节点的电平进行控制，使得防漏电节点和第一电压端之间形成导电路径，且使得连接于第一节点和防漏电节点之间的电路截止。
本公开的一些实施例还提供对应于上述移位寄存器单元的栅极驱动电路、显示装置及驱动方法。
本公开的一些实施例提供的移位寄存器单元、栅极驱动电路、显示装置及驱动方法，可以避免第一节点发生漏电，避免采用该移位寄存器单元形成的栅极驱动电路的显示装置发生显示不良问题。同时，本公开的一些实施例还可以简化电路结构，从而可以减小采用栅极驱动电路的显示装置的边框尺寸，提高该显示装置的PPI。
下面结合附图对本公开的一些实施例及其示例进行详细说明。
本公开的至少一个实施例提供一种移位寄存器单元10，如图2所示，该移位寄存器单元10包括第一子单元100和防漏电电路400，第一子单元100包括第一输入电路110和第一输出电路120。多个该移位寄存器单元10可以级联以构建本公开一实施例提供的栅极驱动电路，该栅极驱动电路可以用于显示装置，在显示装置的一帧画面的显示过程中提供扫描信号。
该第一输入电路110被配置为响应于第一输入信号STU1对第一节点Q1的电平进行控制，例如对第一节点Q1进行充电。例如，第一输入电路110可以被配置为接收第一输入信号STU1和第二电压VDD，第一输入电路110响应于第一输入信号STU1而导通，从而可以利用第二电压VDD对第一节点Q1进行充电。又例如，第一输入电路110也可以不接收第二电压VDD，直接利用第一输入信号STU1对第一节点Q1进行充电。
需要说明的是，在本公开的一些实施例中，第二电压VDD例如为高电平，以下各实施例与此相同，不再赘述。
该第一输出电路120被配置为在第一节点Q1的电平的控制下在输出端提供输出信号。例如，如图2所示，在一些实施例中，输出信号包括移位信号CR和第一输出信号OUT1。例如，第一输出电路120可以被配置为接收第二时钟信号CLKB和第三时钟信号CLKC，第一输出电路120在第一节点Q1的电平的控制下导通时，可以将第二时钟信号CLKB作为移位信号CR输出，并将第三时钟信号CLKC作为第一输出信号OUT1输出。
例如，在一帧的显示时段中，第一输出电路120输出的移位信号CR可以提供至其它移位寄存器单元10以作为第一输入信号STU1，从而完成显示扫描的逐行移位；第一输出电路120输出的第一输出信号OUT1可以驱动显示面板中的某一行子像素单元进行显示扫描。
例如，当多个移位寄存器单元10级联构成一栅极驱动电路时，其中有些移位寄存器单元10可以和一个时钟信号线连接，从而接收由该时钟信号线提供的第一输入信号STU1；或者，有些移位寄存器单元10还可以接收其它级移位寄存器单元10输出的移位信号CR作为第一输入信号STU1。
需要说明的是，在一帧的显示时段中，第一输出电路120输出的移位信号CR和第一输出信号OUT1的信号波形可以相同，也可以不同，本公开的实施例对此不作限定。
如图2所示，防漏电电路400和第一节点Q1以及第一电压端VGL1连接，且被配置为在第一节点Q1的电平的控制下对防漏电节点OF的电平进行控制，使得防漏电节点OF和第一电压端VGL1之间形成导电路径，且使得连接于第一节点Q1和防漏电节点OF之间的电路截止。
例如，在一些实施例中，如图2所示，防漏电电路400包括第一防漏电 子电路410和第二防漏电子电路420。
例如，第一防漏电子电路410和第一节点Q1以及防漏电节点OF连接，且被配置为在第一节点Q1的电平的控制下对防漏电节点OF的电平进行控制。例如，第一防漏电子电路410可以被配置为接收第二电压VDD，第一防漏电子电路在第一节点Q1的电平的控制下利用第二电压VDD对防漏电节点OF的电平进行控制。
例如，第二防漏电子电路420和防漏电节点OF以及第一电压端VGL1连接，第二防漏电子电路420被配置为在防漏电节点OF的电平或第一节点Q1的电平的控制下，使得防漏电节点OF和第一电压端VGL1之间形成导电路径。例如，在本公开的实施例中，第一电压端VGL1被配置为提供第一电压。需要说明的是，在本公开的实施例中，第一电压例如为低电平，以下各实施例与此相同，不再赘述。例如，第一电压端VGL1可以被配置为接地。
如图2所示，在本公开的实施例提供的移位寄存器单元10中，例如，当第一节点Q1为高电平时，第一节点Q1可能通过图2中所示的漏电路径发生漏电，该漏电路径可以是和第一节点Q1连接的复位电路。例如，当不需要该复位电路工作时，可以使得该复位电路的控制端接收低电平的第一电压。例如，当第一节点Q1的电平为高电平时，第一防漏电子电路410在第一节点Q1的电平的控制下被导通，从而使得防漏电节点OF的电平变高。同时，第二防漏电子电路420在防漏电节点OF的高电平或第一节点Q1的高电平的控制下被导通，从而使得防漏电节点OF和第一电压端VGL1之间形成一个导电路径，所以使得防漏电节点OF的电平高于第一电压端VGL1提供的第一电压。
经过上述防漏电电路400的控制，就可以使得防漏电节点OF的电平高于第一电压，从而使得漏电路径中的电路(例如，复位电路)在防漏电节点OF的电平和第一电压的控制下被截止，即使得连接于第一节点Q1和防漏电节点OF之间的电路截止，从而可以避免第一节点Q1通过漏电路径发生漏电。在本公开的一些实施例提供的移位寄存器单元10中，将可能使得第一节点Q1发生漏电的电路和防漏电节点OF电连接，就可以避免第一节点Q1发生漏电。
本公开的一些实施例提供的移位寄存器单元10不仅可以实现避免第一 节点Q1发生漏电，而且只通过设置一个防漏电电路400就可以避免和第一节点Q1连接的多个电路(例如多个复位电路)发生漏电，从而可以简化电路结构，减小采用该移位寄存器单元的显示装置的边框尺寸，更有利于提高该显示装置的PPI。
另外，需要说明的是，在本公开的实施例中，高电平和低电平是相对而言的。高电平表示一个较高的电压范围(例如，高电平可以采用5V、10V或其他合适的电压)，且多个高电平可以相同也可以不同。类似地，低电平表示一个较低的电压范围(例如，低电平可以采用0V、-5V、-10V或其他合适的电压)，且多个低电平可以相同也可以不同。例如，高电平的最小值比低电平的最大值大。
需要说明的是，在本公开的实施例中，对一个节点(例如第一节点Q1、第二节点Q2等)的电平进行控制，包括对该节点进行充电以拉高该节点的电平，或者对该节点进行放电以拉低该节点的电平。例如，可以设置一个与该节点电连接的电容，对该节点进行充电即表示对与该节点电连接的电容进行充电；类似地，对该节点进行放电即表示对与该节点电连接的电容进行放电；通过该电容可以维持该节点的高电平或低电平。
在本公开的一些实施例提供的移位寄存器单元10中，如图3所示，第一防漏电子电路410包括第一防漏电晶体管A1，第二防漏电子电路420包括第二防漏电晶体管A2。需要说明的是，图3和图4仅示意出了移位寄存器单元10的部分电路。
第一防漏电晶体管A1的栅极和第一节点Q1连接，第一防漏电晶体管A1的第一极被配置为接收第二电压VDD，第一防漏电晶体管A1的第二极和防漏电节点OF连接。例如，当第一节点Q1的电平为高电平时，第一防漏电晶体管A1被导通，从而可以利用第二电压VDD对防漏电节点OF的电平进行控制，例如使得防漏电节点OF的电平变高。
第二防漏电晶体管A2的栅极以及第一极彼此电连接且被配置为和防漏电节点OF连接，第二防漏电晶体管A2的第二极被配置为和第一电压端VGL1连接以接收第一电压。如图3所示，第二防漏电晶体管A2采用二极管连接方式，当防漏电节点OF处于高电平时，第二防漏电晶体管A2导通，此时第二防漏电晶体管A2具有单向导通特性，即电流方向是从防漏电节点 OF至第一电压端VGL1，并且由于该第二防漏电晶体管A2的内阻，防漏电节点OF的电平大于第一电压端VGL1提供的第一电压。
例如，如图3所示，该移位寄存器单元10还包括对第一节点Q1进行复位的第一复位晶体管R1以及第二复位晶体管R2。
例如，第一复位晶体管R1的栅极被配置为接收显示复位信号STD，当该显示复位信号STD为高电平时，第一复位晶体管R1被导通，使得第一节点Q1通过第一复位晶体管R1以及第二防漏电晶体管A2和第一电压端VGL1电连接，从而可以利用第一电压端VGL1提供的低电平的第一电压对第一节点Q1进行复位。
例如，第二复位晶体管R2的栅极被配置为接收全局复位信号TRST，当该全局复位信号TRST为高电平时，第二复位晶体管R2被导通，使得第一节点Q1通过第二复位晶体管R2以及第二防漏电晶体管A2和第一电压端VGL1电连接，从而可以利用第一电压端VGL1提供的低电平的第一电压对第一节点Q1进行复位。需要说明的是，关于显示复位信号STD和全局复位信号TRST将在下文中进行详细描述，这里不再赘述。
例如，当第一节点Q1为高电平时，此时可以使得提供至第一复位晶体管R1的显示复位信号STD以及提供至第二复位晶体管R2的全局复位信号TRST为低电平的第一电压，从而使得第一复位晶体管R1和第二复位晶体管R2被截止。如果第一复位晶体管R1和第二复位晶体管R2不能被完全地截止，则第一节点Q1可能通过第一复位晶体管R1或者第二复位晶体管R2而发生漏电。
如图3所示，通过设置第一防漏电晶体管A1和第二防漏电晶体管A2，当第一节点Q1的电平为高电平时，使得防漏电节点OF的电位高于第一电压，从而相对于具有预定低电平(例如第一电压)的显示复位信号STD或全局复位信号TRST，使得第一复位晶体管R1和第二复位晶体管R2的Vgs(栅极和源极之间的电压差)均小于零，从而可以使得第一复位晶体管R1和第二复位晶体管R2均保持截止，同时由于防漏电节点OF的电位变高(高于第一电压)，使得从第一节点Q1到防漏电节点OF的电压差变小(甚至为负)，从而使得第一节点Q1不能通过第一复位晶体管R1或第二复位晶体管R2而发生漏电，或漏电程度降低。需要说明的是，在图3中，为了说明防漏电的 工作原理，关于第一节点Q1可能存在的漏电路径仅示意出了第一复位晶体管R1和第二复位晶体管R2，当存在其它和第一节点Q1连接的电路时，为了避免第一节点Q1通过该电路而发生漏电，只要使得该电路和防漏电节点OF连接即可。也就是说，在本公开的一些实施例提供的移位寄存器单元10中，通过设置第一防漏电晶体管A1和第二防漏电晶体管A2，当第一节点Q1为高电平时，可以使得连接于第一节点Q1和防漏电节点OF之间的电路截止，从而可以避免第一节点Q1发生漏电。
需要说明的是，在图3所示的实施例中，当第一复位晶体管R1或第二复位晶体管R2对第一节点Q1进行复位操作时，第二防漏电晶体管A2的作用不再是防止漏电而是复位，即第二防漏电晶体管A2被复用为复位晶体管。
在本公开的另一些实施例中，如图4所示，第一防漏电子电路410包括第一防漏电晶体管A1，第二防漏电子电路420包括第三防漏电晶体管A3。
例如，第一防漏电晶体管A1的栅极和第一节点Q1连接，第一防漏电晶体管A1的第一极被配置为接收第二电压VDD，第一防漏电晶体管A1的第二极和防漏电节点OF连接。例如，当第一节点Q1的电平为高电平时，第一防漏电晶体管A1被导通，从而可以利用第二电压VDD对防漏电节点OF的电平进行控制，例如使得防漏电节点OF的电平变高。
例如，第三防漏电晶体管A3的栅极和第一节点Q1连接，第三防漏电晶体管A3的第一极和防漏电节点OF连接，第三防漏电晶体管A3的第二极被配置为和第一电压端VGL1连接以接收第一电压。例如，当第一节点Q1为高电平时，第三防漏电晶体管A3被导通，从而使得防漏电节点OF和第一电压端VGL1之间形成导电路径，且使得防漏电节点OF的电平大于第一电压端VGL1提供的第一电压。
在本公开的一些实施例提供的移位寄存器单元10中，通过设置第一防漏电晶体管A1和第三防漏电晶体管A3，当第一节点Q1为高电平时，防漏电节点OF的电平升高，相对于具有预定低电平(例如第一电压)的显示复位信号STD或全局复位信号TRST，使得例如第一复位晶体管R1和第二复位晶体管R2均保持截止，从而可以使得连接于第一节点Q1和防漏电节点OF之间的电路截止，同时由于防漏电节点OF的电位变高(高于第一电压)，使得从第一节点Q1到防漏电节点OF的电压差变小(甚至为负)，从而可 以避免第一节点Q1发生漏电，或漏电程度降低。
需要说明的是，在图3和4中所示的晶体管均以N型晶体管为例进行说明。
本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。此外，按照晶体管的特性可以将晶体管分为N型和P型晶体管。当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其他合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)；以下各实施例中的晶体管也均以N型晶体管为例进行说明，不再赘述。但本公开的实施例包括但不限于此，例如本公开的实施例提供的移位寄存器单元中的一个或多个晶体管也可以采用P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)，关闭电压为高电平电压(例如，5V、10V或其他合适的电压)。
在对OLED显示面板中的子像素单元进行补偿时，除了在子像素单元中设置像素补偿电路进行内部补偿外，还可以通过设置感测晶体管进行外部补偿。在进行外部补偿时，由移位寄存器单元构成的栅极驱动电路需要向显示面板中的子像素单元分别提供用于扫描晶体管和感测晶体管的驱动信号，例如，在一帧的显示时段提供用于扫描晶体管的扫描驱动信号，在一帧的消隐时段提供用于感测晶体管的感测驱动信号。
在一种外部补偿方法中，栅极驱动电路输出的感测驱动信号是逐行顺序扫描的，例如，在第一帧的消隐时段输出用于显示面板中第一行的子像素单元的感测驱动信号，在第二帧的消隐时段输出用于显示面板中第二行的子像素单元的感测驱动信号，依次类推，以每帧输出对应一行子像素单元的感测驱动信号的频率逐行顺序输出，即完成对该显示面板的逐行顺序补偿。
但是，在采用上述逐行顺序补偿的方法时，可能会产生显示不良问题：一是在进行多帧的扫描显示过程中有一条逐行移动的扫描线；二是因为进行外部补偿的时间点的差异会造成显示面板不同区域的亮度差异比较大，例如， 在对显示面板的第100行的子像素单元进行外部补偿时，显示面板的第10行的子像素单元虽然已经进行过外部补偿了，但此时第10行的子像素单元的发光亮度可能已经发生变化，例如发光亮度降低，从而会造成显示面板不同区域的亮度不均匀，在大尺寸的显示面板中这种问题会更加明显。
如上所述，在栅极驱动电路驱动一个显示面板时，如果要实现外部补偿，则需要该栅极驱动电路不仅可以输出用于显示时段的扫描驱动信号，同时还需要输出用于消隐时段的感测驱动信号。
需要说明的是，在本公开的一些实施例中，随机补偿指的是区别于逐行顺序补偿的一种外部补偿方法，在某一帧的消隐时段可以随机输出对应于显示面板中任意一行的子像素单元的感测驱动信号，以下各实施例与此相同，不再赘述。
另外，在本公开的一些实施例中，为了说明的目的，定义“一帧”、“每帧”或“某一帧”包括依次进行的显示时段和消隐时段，例如在显示时段中栅极驱动电路输出驱动信号，该驱动信号可以驱动显示面板从第一行到最后一行完成完整的一幅图像的扫描显示，在消隐时段中栅极驱动电路输出驱动信号，该驱动信号可以用于驱动显示面板中的某一行子像素单元中的感测晶体管，以完成该行子像素单元的外部补偿。
为了实现上述随机补偿，如图5所示，在本公开的一些实施例中，移位寄存器单元10还包括消隐输入子单元300。消隐输入子单元300和第一节点Q1连接，且被配置为接收选择控制信号OE并对第一节点Q1的电平进行控制，例如对第一节点Q1进行充电。
例如，在一帧的消隐时段中，消隐输入子单元300可以对第一节点Q1进行充电，从而使得第一输出电路120在第一节点Q1的电平的控制下输出第一输出信号OUT1。第一输出信号OUT1可以用于驱动显示面板中的某一行子像素单元中的感测晶体管，以完成该行子像素单元的外部补偿。
采用本公开的实施例提供的移位寄存器单元10的栅极驱动电路以及显示装置可以实现随机补偿，从而可以避免由于逐行顺序补偿造成的扫描线以及显示亮度不均匀等显示不良问题。
如图6所示，在本公开的一些实施例中，消隐输入子单元300包括选择控制电路310、第三输入电路320和第一传输电路330。
该选择控制电路310被配置为响应于选择控制信号OE利用第二输入信号STU2对第三节点H的电平进行控制，例如对第三节点H进行充电，并保持第三节点H的电平。例如，在一帧的显示时段中，选择控制电路310可以在选择控制信号OE的控制下而导通，从而利用第二输入信号STU2对第三节点H进行充电。第三节点H的电平(例如高电平)可以从一帧的显示时段一直保持到该帧的消隐时段。
例如，当多个移位寄存器单元10级联构成一栅极驱动电路时，某一级移位寄存器单元10可以接收其它级移位寄存器单元10输出的移位信号CR作为第二输入信号STU2。例如，当需要选择某一级移位寄存器单元10在一帧的消隐时段输出驱动信号时，则可以使得提供至该级移位寄存器单元10的选择控制信号OE和第二输入信号STU2的波形时序相同，从而使得该级移位寄存器单元10中的选择控制电路310导通。
该第三输入电路320被配置为在第三节点H的电平的控制下将第一时钟信号CLKA传输至第四节点N。例如，第三输入电路320可以被配置为接收第一时钟信号CLKA。第三输入电路320在第三节点H的电平的控制下导通时可以将第一时钟信号CLKA传输至第四节点N，从而控制第四节点N的电平。例如，在一帧的消隐时段中，当第一时钟信号CLKA为高电平时，第三输入电路320可以将该高电平传输至第四节点N，从而使得第四节点N变为高电平。
该第一传输电路330和第一节点Q1、第四节点N以及防漏电节点OF电连接，且被配置为响应于第一时钟信号CLKA对第一节点Q1的电平以及防漏电节点OF的电平进行控制。例如，在一些实施例中，第一传输电路330可以被配置为接收第一时钟信号CLKA，当第一传输电路330在第一时钟信号CLKA的控制下导通时可以将第四节点N的电平传输至第一节点Q1，从而对第一节点Q1的电平进行控制，例如对第一节点Q1进行充电。另外，当第一传输电路330在第一时钟信号CLKA的控制下导通时还可以将第四节点N的电平传输至防漏电节点OF，从而对防漏电节点OF的电平进行控制。
需要说明的是，在本公开的实施例中，在移位寄存器单元10中设置消隐输入子单元300是为了实现在一帧的消隐时段中可以输出驱动信号。消隐输入子单元300中的“消隐”仅表示和一帧中的消隐时段有关，而并不限定消 隐输入子单元300仅工作在消隐时段中，以下各实施例与此相同，不再赘述。
如图7所示，本公开的一些实施例提供的移位寄存器单元10还包括第二子单元200。该第二子单元200包括第二输入电路210和第二输出电路220。
该第二输入电路210被配置为响应于第一输入信号STU1对第二节点Q2的电平进行控制，例如对第二节点Q2进行充电。例如，第二输入电路210可以被配置为接收第一输入信号STU1和第二电压VDD，第二输入电路210响应于第一输入信号STU1而导通，从而可以利用第二电压VDD对第二节点Q2进行充电。又例如，第二输入电路210也可以不接收第二电压VDD，直接利用第一输入信号STU1对第二节点Q2进行充电。
该第二输出电路220被配置为在第二节点Q2的电平的控制下输出第二输出信号OUT2。例如，第二输出电路220可以被配置为接收第四时钟信号CLKD，第二输出电路220在第一节点Q1的电平的控制下导通时，可以将第四时钟信号CLKD作为第二输出信号OUT2输出。
本公开的实施例提供的移位寄存器10可以对多个子单元(第一子单元100和第二子单元200等)同时进行充电，只有一个子单元(例如第一子单元100)需要输出移位信号，而其它子单元(例如第二子单元200等)不需要输出移位信号，从而可以节省时钟信号线以及晶体管的数量，从而可以减小采用该移位寄存器单元10的显示装置的边框尺寸，提高该显示装置的PPI。
需要说明的是，图7仅是本公开的一种示例，本公开的实施例对移位寄存器单元10包括的子单元的数量不作限定，例如还可以包括三个、四个或更多个子单元，子单元的数量可以根据实际情况进行设置。
当移位寄存器单元10包括第二子单元200时，消隐输入子单元300还包括第二传输电路340。
该第二传输电路340和第二节点Q2以及防漏电节点OF电连接，且被配置为响应于第一时钟信号CLKA将防漏电节点OF的电平传输至第二节点Q2。例如，在一些实施例中，第二传输电路340可以被配置为接收第一时钟信号CLKA，当第二传输电路340在第一时钟信号CLKA的控制下导通时可以将防漏电节点OF的电平传输至第二节点Q2，从而对第二节点Q2的电平进行控制，例如对第二节点Q2进行充电。
例如，在一帧的显示时段中，第二输出电路220输出的第二输出信号 OUT2可以驱动显示面板中的某一行子像素单元进行显示扫描。又例如，在一帧的消隐时段中，第二输出电路220输出的第二输出信号OUT2可以用于驱动显示面板中的某一行子像素单元中的感测晶体管，以完成该行子像素单元的外部补偿。
在本公开的一些实施例提供的移位寄存器单元10中，第一传输电路330和第二传输电路340通过防漏电节点OF实现电连接，当第一传输电路330对第一节点Q1进行充电时，同时通过防漏电节点OF还可以将第四节点N的高电平传输至第二节点Q2，从而实现对第二节点Q2的充电。另外，由于第一传输电路330和第二传输电路340均和防漏电节点OF电连接，所以还可以避免第一节点Q1通过第一传输电路330发生漏电，并且避免第二节点Q2通过第二传输电路340发生漏电。
另外，当移位寄存器单元10包括三个、四个或更多个子单元时，相应地，需要设置三个、四个或更多个传输电路以实现消隐输入子单元300的功能。
在本公开的一些实施例中，当移位寄存器单元10包括多个子单元时(第一子单元100和第二子单元200等)，这些子单元可以共用一个消隐输入子单元300，从而可以减小该移位寄存器单元10占用的面积，减小采用该移位寄存器单元的显示装置的边框尺寸，从而提高该显示装置的PPI。
如图8和图9A-9C所示，在一些实施例中，选择控制电路310可以实现为包括第五输入晶体管B5和第一电容C1。第五输入晶体管B5的栅极被配置为接收选择控制信号OE，第五输入晶体管B5的第一极被配置为接收第二输入信号STU2，第五输入晶体管B5的第二极和第三节点H连接。例如，当选择控制信号OE为高电平的导通信号时，第五输入晶体管B5导通，从而可以利用第二输入信号STU2对第三节点H进行充电。
第一电容C1的第一极和第三节点H连接，第一电容C1的第二极和第一电压端VGL1连接以接收第一电压，或者第一电容C1的第二极被配置为接收第二电压VDD。通过设置第一电容C1可以保持第三节点H的电位，例如，在一帧的显示时段中，选择控制电路310对第三节点H进行充电从而将第三节点H拉高至高电位，第一电容C1可以将第三节点H的高电位保持至该帧的消隐时段。
例如，在如图8所示的实施例中，第三输入电路320可以实现为第七输 入晶体管B7。第七输入晶体管B7的栅极和第三节点H连接，第七输入晶体管B7的第一极被配置为接收第一时钟信号CLKA，第七输入晶体管B7的第二极和第四节点N连接。例如，当第三节点H为高电平时，第七输入晶体管B7导通，从而可以将第一时钟信号CLKA传输至第四节点N以拉高第四节点N的电平。
例如，在如图8所示的实施例中，第一传输电路330包括第一传输晶体管T1和第二传输晶体管T2，第二传输电路340包括第三传输晶体管T3。
第一传输晶体管T1的栅极被配置为接收第一时钟信号CLKA，第一传输晶体管T1的第一极和第四节点N连接，第一传输晶体管T1的第二极和防漏电节点OF连接；第二传输晶体管T2的栅极被配置为接收第一时钟信号CLKA，第二传输晶体管T2的第一极和防漏电节点OF连接，第二传输晶体管T2的第二极和第一节点Q1连接；第三传输晶体管T3的栅极被配置为接收第一时钟信号CLKA，第三传输晶体管T3的第一极和防漏电节点OF连接，第三传输晶体管T3的第二极和第二节点Q2连接。
例如，当第一时钟信号CLKA为高电平时，第一传输晶体管T1、第二传输晶体管T2以及第三传输晶体管T3均导通，导通的第一传输晶体管T1可以将第四节点N的高电平传输至防漏电节点OF，使得防漏电节点OF的电平变为高电平；然后导通的第二传输晶体管T2将防漏电节点OF的高电平传输至第一节点Q1，以实现对第一节点Q1的充电；导通的第三传输晶体管T3将防漏电节点OF的高电平传输至第二节点Q2，以实现对第二节点Q2的充电。如上所述，在对第一节点Q1和第二节点Q2进行充电时，第一传输晶体管T1被复用，同时，由于第二传输晶体管T2和防漏电节点OF连接，所以第二传输晶体管T2还可以避免第一节点Q1发生漏电；由于第三传输晶体管T3和防漏电节点OF连接，所以第三传输晶体管T3还可以避免第二节点Q2发生漏电。
下面对图9A-9C提供的消隐输入子单元300进行描述，需要说明的是，在下面的描述中，对于图9A-9C和图8相同的部分将不再赘述。
例如，如图9A所示，相对于图8，消隐输入子单元300还包括第一耦合电容CST1。第一耦合电容CST1的第一极被配置为接收第一时钟信号CLKA，第一耦合电容CST1的第二极和第三节点H连接。例如，当第一时钟信号 CLKA从低电平变为高电平时，第一时钟信号CLKA通过第一耦合电容CST1的耦合作用可以对第三节点H进行耦合上拉，使得第三节点H的电平被进一步拉高，从而可以保证第七输入晶体管B7的导通更充分。
例如，如图9B所示，相对于图9A，消隐输入子单元300还包括第二耦合电容CST2，第二耦合电容CST2的第一极和第三节点H连接，第二耦合电容CST2的第二极和第四节点N连接。例如，当第一时钟信号CLKA从低电平变为高电平时，此时如果第七输入晶体管B7导通，则高电平的第一时钟信号CLKA可以通过第七输入晶体管B7传输至第四节点N，使得第二耦合电容CST2的第二极的电位被拉高，通过第二耦合电容CST2的自举作用，从而可以使得第三节点H的电平被进一步拉高，从而可以保证第七输入晶体管B7的导通更充分。
例如，如图9C所示，第一传输电路330包括第一传输晶体管T1和第二传输晶体管T2，第二传输电路340包括第三传输晶体管T3。
第一传输晶体管T1的栅极和第四节点N连接，第一传输晶体管T1的第一极被配置为接收高电平的第二电压VDD，第一传输晶体管T1的第二极和防漏电节点OF连接；第二传输晶体管T2的栅极和第四节点N连接，第二传输晶体管T2的第一极和防漏电节点OF连接，第二传输晶体管T2的第二极和第一节点Q1连接；第三传输晶体管T3的栅极和第四节点N连接，第三传输晶体管T3的第一极和防漏电节点OF连接，第三传输晶体管T3的第二极和第二节点Q2连接。
例如，当第一时钟信号CLKA为高电平时，高电平的第一时钟信号CLKA通过导通的第七输入晶体管B7传输至第四节点N，从而使得第四节点N变为高电平，第一传输晶体管T1、第二传输晶体管T2以及第三传输晶体管T3均被导通，导通的第一传输晶体管T1可以将高电平的第二电压VDD传输至防漏电节点OF，使得防漏电节点OF的电平变为高电平；然后导通的第二传输晶体管T2将防漏电节点OF的高电平传输至第一节点Q1，以实现对第一节点Q1的充电；导通的第三传输晶体管T3将防漏电节点OF的高电平传输至第二节点Q2，以实现对第二节点Q2的充电。
例如，图9D还提供了一种消隐输入子单元300，相对于图9B，消隐输入子单元300中的选择控制电路310除了包括第五输入晶体管B5外还包括 第六输入晶体管B6，另外消隐输入子单元300还包括第四防漏电晶体管A4。
如图9D所示，第四防漏电晶体管A4的栅极和第三节点H连接，第四防漏电晶体管A4的第一极被配置为接收第二电压VDD，第四防漏电晶体管A4的第二极和第六输入晶体管B6的第一极连接，第六输入晶体管B6的栅极被配置为接收选择控制信号OE，第六输入晶体管B6的第二极和第三节点H连接。
防漏电晶体管A4和第六输入晶体管B6配合可以防止第三节点H发生漏电，关于防止第三节点H发生漏电的工作原理可以参考上述关于第一节点Q1的相应描述，这里不再赘述。
如图10所示，在本公开的一些实施例提供的移位寄存器单元10中，第一子单元100还包括第一控制电路130、第一复位电路140、第二复位电路150、移位信号输出端CRT以及第一输出信号端OP1。移位信号输出端CRT被配置为输出移位信号CR，第一输出信号端OP1被配置为输出第一输出信号OUT1。
该第一控制电路130被配置为在第一节点Q1的电平和第三电压VDD_A的控制下，对第五节点QB_A的电平进行控制。例如，第一控制电路130和第一节点Q1和第五节点QB_A连接，且被配置为接收第三电压VDD_A和第一电压。例如，当第一节点Q1处于高电平时，第一控制电路130可以利用低电平的第一电压将第五节点QB_A拉低至低电平。又例如，当第一节点Q1处于低电平时，第一控制电路130可以利用第三电压VDD_A(例如为高电平)对第五节点QB_A进行充电，以将第五节点QB_A拉高至高电平。
该第一复位电路140被配置为在第五节点QB_A的电平的控制下，对第一节点Q1、移位信号输出端CRT和第一输出信号端OP1进行复位。例如，第一复位电路140和第一节点Q1、第五节点QB_A、移位信号输出端CRT和第一输出信号端OP1连接，且被配置为接收第一电压和第五电压VGL2。例如，当第一复位电路140在第五节点QB_A的电平的控制下导通时，可以利用第一电压对第一节点Q1和移位信号输出端CRT进行下拉复位，同时还可以利用第五电压VGL2对第一输出信号端OP1进行下拉复位。需要说明的是，在本公开的一些实施例中，也可以利用第一电压对第一输出信号端OP1进行下拉复位，本公开对此不作限制。另外，在本公开的实施例中，第五电 压VGL2例如为低电平，以下各实施例与此相同，不再赘述。在本公开的实施例中，第五电压VGL2可以和第一电压相同，也可以不同。
该第二复位电路150被配置为在第六节点QB_B的电平的控制下，对第一节点Q1、移位信号输出端CRT和第一输出信号端OP1进行复位。例如，第二复位电路150和第一节点Q1、第六节点QB_B、移位信号输出端CRT和第一输出信号端OP1连接，且被配置为接收第一电压和第五电压VGL2。例如，当第二复位电路150在第六节点QB_B的电平的控制下导通时，可以利用第一电压对第一节点Q1和移位信号输出端CRT进行下拉复位，同时还可以利用第五电压VGL2对第一输出信号端OP1进行下拉复位。
如图10所示，第二子单元200还包括第二控制电路230、第三复位电路240、第四复位电路250以及第二输出信号端OP2。第二输出信号端OP2被配置为输出第二输出信号OUT2。
该第二控制电路230被配置为在第二节点Q2的电平和第四电压VDD_B的控制下，对第六节点QB_B的电平进行控制。例如，第二控制电路230和第二节点Q2和第六节点QB_B连接，且被配置为接收第四电压VDD_B和第一电压。例如，当第二节点Q2处于高电平时，第二控制电路230可以利用低电平的第一电压将第六节点QB_B下拉至低电平。又例如，当第二节点Q2的电位处于低电平时，第二控制电路230可以利用第四电压VDD_B(例如为高电平)对第六节点QB_B进行充电，以将第六节点QB_B上拉至高电平。
该第三复位电路240被配置为在第六节点QB_B的电平的控制下，对第二节点Q2、第二输出信号端OP2进行复位。例如，第三复位电路240和第二节点Q2、第六节点QB_B和第二输出信号端OP2连接，且被配置为接收第一电压和第五电压VGL2。例如，当第三复位电路240在第六节点QB_B的电平的控制下导通时，可以利用第一电压对第二节点Q2进行下拉复位，同时还可以利用第五电压VGL2对第二输出信号端OP2进行下拉复位。需要说明的是，在本公开的一些实施例中，也可以利用第一电压对第二输出信号端OP2进行下拉复位，本公开对此不作限制。
该第四复位电路250被配置为在第五节点QB_A的电平的控制下，对第二节点Q2和第二输出信号端OP2进行复位。例如，第四复位电路250和第 二节点Q2、第五节点QB_A和第二输出信号端OP2连接，且被配置为接收第一电压和第五电压VGL2。例如，当第四复位电路250在第五节点QB_A的电平的控制下导通时，可以利用第一电压对第二节点Q2进行下拉复位，同时还可以利用第五电压VGL2对第二输出信号端OP2进行下拉复位。
需要说明的是，在本公开的实施例中，例如，第三电压VDD_A和第四电压VDD_B可以被配置为彼此互为反相信号，即第三电压VDD_A为高电平时，第四电压VDD_B为低电平，而第三电压VDD_A为低电平时，第四电压VDD_B为高电平。采用这种方式可以使得第一控制电路130和第二控制电路230在同一时刻只有一个处于工作状态，可以避免电路长时间工作引起的性能漂移，从而提高电路的稳定性。
需要说明的是，在本公开的实施例中，各个节点(第一节点Q1、第二节点Q2、第三节点H、第四节点N、第五节点QB_A和第六节点QB_B等)和各个输出端(移位信号输出端CRT、第一输出信号端OP1和第二输出信号端OP2等)均是为了更好地描述电路结构而设置的，并非表示实际存在的部件。节点表示电路结构中相关电路连接的汇合点，即与具有相同节点标识连接的相关电路彼此之间是电连接的。例如，如图10所示，第一控制电路130、第一复位电路140以及第四复位电路250都和第五节点QB_A连接，也就是表示这些电路彼此之间是电连接的。
如图11所示，在本公开的一些实施例提供的移位寄存器单元10中，第一子单元100还包括第三控制电路160、第四控制电路170和公共控制电路；第二子单元200还包括第五控制电路260和第六控制电路270。
该第三控制电路160和第五节点QB_A以及公共控制节点CC连接，且被配置为响应于第一时钟信号CLKA使得第五节点QB_A和公共控制节点CC电连接。
该公共控制电路161和公共控制节点CC以及第一电压端VGL1电连接，且被配置为在第三节点H的电平的控制下使得公共控制节点CC和第一电压端VGL1电连接。
该第五控制电路260和第六节点QB_B以及公共控制节点CC连接，且被配置为响应于第一时钟信号CLKA使得第六节点QB_B和公共控制节点CC电连接。
例如，在一帧的消隐时段中，当第一时钟信号CLKA为高电平且第三节点H为高电平时，第三控制电路160、公共控制电路161以及第五控制电路260均导通，从而使得第五节点QB_A通过第三控制电路160和公共控制电路161和第一电压端VGL1实现电连接，从而使得低电平的第一电压可以对第五节点QB_A进行下拉；第六节点QB_B通过第五控制电路260和公共控制电路161和第一电压端VGL1实现电连接，从而使得低电平的第一电压可以对第六节点QB_B进行下拉。也就是说，公共控制电路161既用于控制第五节点QB_A的电平也用于控制第六节点QB_B的电平，从而可以简化电路结构。
如图12所示，本公开的一些实施例还提供一种移位寄存器单元10，下面只描述图12中所示的移位寄存器单元10和图11中所示的移位寄存器单元10的区别，相同之处不再赘述。
如图12所示，第三控制电路160和第三节点H、第五节点QB_A以及公共控制节点CC连接，且被配置为在第三节点H的电平的控制下使得第五节点QB_A和公共控制节点CC电连接。
公共控制电路161和公共控制节点CC以及第一电压端VGL1电连接，且被配置为响应于第一时钟信号CLKA使得公共控制节点CC和第一电压端VGL1电连接。
第五控制电路260和第三节点H、第六节点QB_B以及公共控制节点CC连接，且被配置为在第三节点H的电平的控制下使得第六节点QB_B和公共控制节点CC电连接。
例如，在一帧的消隐时段中，当第一时钟信号CLKA为高电平且第三节点H为高电平时，第三控制电路160、公共控制电路161以及第五控制电路260均导通，从而使得第五节点QB_A通过第三控制电路160和公共控制电路161和第一电压端VGL1实现电连接，从而使得低电平的第一电压可以对第五节点QB_A进行下拉；第六节点QB_B通过第五控制电路260和公共控制电路161和第一电压端VGL1实现电连接，从而使得低电平的第一电压可以对第六节点QB_B进行下拉。也就是说，公共控制电路161既用于控制第五节点QB_A的电平也用于控制第六节点QB_B的电平，从而可以简化电路结构。
如图11和图12所示，该第四控制电路170和第五节点QB_A以及第一电压端VGL1电连接，且被配置为响应于第一输入信号STU1对第五节点QB_A的电平进行控制。例如，在一帧的显示时段中，第四控制电路170响应于第一输入信号STU1而导通，从而利用低电平的第一电压对第五节点QB_A进行下拉。将第五节点QB_A下拉至低电位，可以避免第五节点QB_A对第一节点Q1的影响，从而使得在显示时段中对第一节点Q1的充电更充分。
该第六控制电路270和第六节点QB_B以及第一电压端VGL1电连接，且被配置为响应于第一输入信号STU1对第六节点QB_B的电平进行控制。例如，在一帧的显示时段中，第六控制电路270响应于第一输入信号STU1而导通，从而利用低电平的第一电压对第六节点QB_B进行下拉。将第六节点QB_B下拉至低电位，可以避免第六节点QB_B对第二节点Q2的影响，从而使得在显示时段中对第二节点Q2的充电更充分。
如图11和图12所示，第一子单元100还包括第五复位电路180和第六复位电路190，第二子单元200还包括第七复位电路280和第八复位电路290。
该第五复位电路180和第一节点Q1以及防漏电节点OF连接，且被配置为响应于显示复位信号STD对第一节点Q1进行复位；该第六复位电路190和第一节点Q1以及防漏电节点OF连接，且被配置为响应于全局复位信号TRST对第一节点Q1进行复位。
由上文中描述可知，当第一节点Q1为高电平时，第二防漏电子电路420保持导通。例如，在一帧的显示时段中，第五复位电路180响应于显示复位信号STD而导通，从而使得第一节点Q1通过第五复位电路180以及第二防漏电子电路420和第一电压端VGL1电连接，从而可以利用低电平的第一电压对第一节点Q1进行下拉复位。例如，当多个移位寄存器单元10级联构成一栅极驱动电路时，某一级移位寄存器单元10可以接收其它级移位寄存器单元10输出的移位信号CR作为显示复位信号STD。
例如，当多个移位寄存器单元10级联构成一栅极驱动电路时，在一帧的显示时段前，各级移位寄存器单元10中的第六复位电路190响应于全局复位信号TRST而导通，从而使得第一节点Q1通过第六复位电路190以及第二防漏电子电路420和第一电压端VGL1电连接，从而可以利用低电平的第一电压对第一节点Q1进行下拉复位。
如上所述，在本公开的一些实施例提供的移位寄存器单元10中，第五复位电路180以及第六复位电路190均和防漏电节点OF连接，当第五复位电路180或第六复位电路190需要对第一节点Q1进行复位操作时，第二防漏电子电路420可以被复用。同时，防漏电电路400还可以防止第一节点Q1通过第五复位电路180或第六复位电路190发生漏电。也就是说，第二防漏电子电路420既可以实现防漏电还可以实现对第一节点Q1的复位操作，从而可以简化电路结构。
如图11和图12所示，该第七复位电路280和第二节点Q2以及防漏电节点OF连接，且被配置为响应于显示复位信号STD对第二节点Q2进行复位；该第八复位电路290和第二节点Q2以及防漏电节点OF连接，且被配置为响应于全局复位信号TRST对第二节点Q2进行复位。
例如，在一帧的显示时段中，第七复位电路280响应于显示复位信号STD而导通，从而使得第二节点Q2通过第七复位电路280以及第二防漏电子电路420和第一电压端VGL1电连接，从而可以利用低电平的第一电压对第二节点Q2进行下拉复位。
例如，当多个移位寄存器单元10级联构成一栅极驱动电路时，在一帧的显示时段前，各级移位寄存器单元10中的第八复位电路290响应于全局复位信号TRST而导通，从而使得第二节点Q2通过第八复位电路290以及第二防漏电子电路420和第一电压端VGL1电连接，从而可以利用低电平的第一电压对第二节点Q2进行下拉复位。
如上所述，在本公开的一些实施例提供的移位寄存器单元10中，第七复位电路280以及第八复位电路290均和防漏电节点OF连接，当第七复位电路280或第八复位电路290需要对第二节点Q2进行复位操作时，第二防漏电子电路420可以被复用。同时，防漏电电路400还可以防止第二节点Q2通过第七复位电路280或第八复位电路290发生漏电。也就是说，第二防漏电子电路420既可以实现防漏电还可以实现对第二节点Q2的复位操作，从而可以简化电路结构。
本领域技术人员可以理解，尽管图11和图12中示出了多个控制电路和多个复位电路，然而上述示例并不能限制本公开的保护范围。在实际应用中，技术人员可以根据情况选择使用或不使用上述各电路中的一个或多个，基于 前述各电路的各种组合变型均不脱离本公开的原理，对此不再赘述。
在本公开的一些实施例中，移位寄存器单元10可以实现为图13所示的电路结构。如图13所示，该移位寄存器单元10包括第一子单元100和防漏电电路400。第一子单元100包括第一输入电路110、第一输出电路120、第一控制电路130、第一复位电路140、第四控制电路170、第五复位电路180以及第六复位电路190。
如图13所示，第一输入电路110可以实现为第一输入晶体管B1。第一输入晶体管B1的栅极被配置为接收第一输入信号STU1，第一输入晶体管B1的第一极被配置为接收第一电压VDD，第一输入晶体管B1的第二极和第一节点Q1连接。
例如，在另一个示例中，如图14A所示，第一输入晶体管B1的栅极和第一极连接且被配置为接收第一输入信号STU1，从而在第一输入信号STU1为高电平时，可以利用高电平的第一输入信号STU1对第一节点Q1进行充电。
例如，在又一个示例中，如图14B所示，第一输入电路110还包括第二输入晶体管B2。第二输入晶体管B2的栅极以及第一极和第一输入晶体管B1的第二极连接，第二输入晶体管B2的第二极和第一节点Q1连接。由于第二输入晶体管B2采用二极管连接方式，所以电流只能从第二输入晶体管B2的第一极流向第二极，而不能从第二输入晶体管B2的第二极(即第一节点Q1)流向第一极，从而可以避免第一节点Q1发生漏电。
例如，在又一个示例中，如图14C所示，第二输入晶体管B2的栅极和第一输入晶体管B1的栅极连接，且都被配置为接收第一输入信号STU1，第二输入晶体管B2的第一极和防漏电节点OF电连接。图14C中所示的第一输入电路110通过和防漏电节点OF连接可以避免第一节点Q1发生漏电。
如图13所示，第一输出电路120可以包括第一输出晶体管D1、第二输出晶体管D2和第二电容C2。第一输出晶体管D1的栅极和第一节点Q1连接，第一输出晶体管D1的第一极被配置为接收第二时钟信号CLKB并作为移位信号CR，第一输出晶体管D1的第二极和移位信号输出端CRT连接且被配置为输出移位信号CR。
第二输出晶体管D2的栅极和第一节点Q1连接，第二输出晶体管D2的 第一极被配置为接收第三时钟信号CLKC并作为第一输出信号OUT1，第二输出晶体管D2的第二极和第一输出信号端OP1连接且被配置为输出第一输出信号OUT1。第二电容C2的第一极和第一节点Q1连接，第二电容C2的第二极和第二输出晶体管D2的第二极(即第一输出信号端OP1)连接。
如图13所示，第一控制电路130可以实现为包括第九控制晶体管E9和第十控制晶体管E10。第九控制晶体管E9的栅极和第一极被配置为接收第三电压VDD_A，第九控制晶体管E9的第二极和第五节点QB_A连接。第十控制晶体管E10的栅极和第一节点Q1连接，第十控制晶体管E10的第一极和第五节点QB_A连接，第十控制晶体管E10的第二极被配置为和第一电压端VGL1连接以接收第一电压。
如图13所示，第一复位电路140可以实现为包括第七复位晶体管R7、第八复位晶体管R8和第九复位晶体管R9。
第七复位晶体管R7的栅极和第五节点QB_A连接，第七复位晶体管R7的第一极和第一节点Q1连接，第七复位晶体管R7的第二极和防漏电节点OF连接。第八复位晶体管R8的栅极和第五节点QB_A连接，第八复位晶体管R8的第一极和移位信号输出端CRT连接，第八复位晶体管R8的第二极和第一电压端VGL1连接以接收第一电压。第九复位晶体管R9的栅极和第五节点QB_A连接，第九复位晶体管R9的第一极和第一输出信号端OP1连接，第九复位晶体管R9的第二极被配置为接收第五电压VGL2。
如图13所示，第四控制电路170可以实现为第二控制晶体管E2。第二控制晶体管E2的栅极被配置为接收第一输入信号STU1，第二控制晶体管E2的第一极和第五节点QB_A连接，第二控制晶体管E2的第二极和第一电压端VGL1连接以接收第一电压。
如图13所示，第五复位电路180可以实现为第一复位晶体管R1，第六复位电路190可以实现为第二复位晶体管R2。第一复位晶体管R1的栅极被配置为接收显示复位信号STD，第一复位晶体管R1的第一极和第一节点Q1连接，第一复位晶体管R1的第二极和防漏电节点OF连接。第二复位晶体管R2的栅极被配置为接收全局复位信号TRST，第二复位晶体管R2的第一极和第一节点Q1连接，第二复位晶体管R2的第二极和防漏电节点OF连接。
需要说明的是，关于第一防漏电晶体管A1以及第二防漏电晶体管A2 的描述可以参考图3中的相应描述，这里不再赘述。
在本公开的一些实施例中，移位寄存器单元10还可以实现为图15所示的电路结构。下面只描述图15所示的移位寄存器单元10和图13所示的移位寄存器单元10的区别，相同之处在此不再赘述。
如图15所示，第一输入电路110包括第一输入晶体管B1和第二输入晶体管B2，即第一输入电路110采用图14C所示的电路结构。
如图15所示，该移位寄存器单元10还包括第十三控制晶体管E13、第十四控制晶体管E14。第十三控制晶体管E13的栅极和第一极被配置为接收第四电压VDD_B，第十三控制晶体管E13的第二极和第六节点QB_B连接。第十四控制晶体管E14的栅极和第一节点Q1连接，第十四控制晶体管E14的第一极和第六节点QB_B连接，第十四控制晶体管E14的第二极被配置为和第一电压端VGL1连接以接收第一电压。
需要说明的是，在本公开的实施例中，例如，第三电压VDD_A和第四电压VDD_B可以被配置为彼此互为反相信号，即第三电压VDD_A为高电平时，第四电压VDD_B为低电平，而第三电压VDD_A为低电平时，第四电压VDD_B为高电平。采用这种方式可以使得第九控制晶体管E9和第十三控制晶体管E13在同一时刻只有一个处于导通状态，这样可以避免晶体管长期导通引起的性能漂移，从而可以提高电路的稳定性。
如图15所示，该移位寄存器单元10还包括第五控制晶体管E5。第五控制晶体管E5的栅极被配置为接收第一输入信号STU1，第五控制晶体管E5的第一极和第六节点QB_B连接，第五控制晶体管E5的第二极和第一电压端VGL1连接以接收第一电压。
如图15所示，为了和第六节点QB_B配合，该移位寄存器单元10还包括第十复位晶体管R10、第十一复位晶体管R11和第十二复位晶体管R12。
第十复位晶体管R10的栅极和第六节点QB_B连接，第十复位晶体管R10的第一极和第一节点Q1连接，第十复位晶体管R10的第二极和防漏电节点OF连接。第十一复位晶体管R11的栅极和第六节点QB_B连接，第十一复位晶体管R11的第一极和移位信号输出端CRT连接，第十一复位晶体管R11的第二极和第一电压端VGL1连接以接收第一电压。第十二复位晶体管R12的栅极和第六节点QB_B连接，第十二复位晶体管R12的第一极和第 一输出信号端OP1连接，第十二复位晶体管R12的第二极被配置为接收第五电压VGL2。
在本公开的一些实施例中，图11中所示的移位寄存器单元10可以实现为图16所示的电路结构。如图16所示，该移位寄存器单元10包括第一子单元100、第二子单元200和防漏电电路400。第一子单元100包括第一输入电路110、第一输出电路120、第一控制电路130、第三控制电路160、公共控制电路161、第四控制电路170、第一复位电路140、第二复位电路150、第五复位电路180以及第六复位电路190。第二子单元200包括第二输入电路210、第二输出电路220、第二控制电路230、第五控制电路260、第六控制电路270、第三复位电路240、第四复位电路250、第七复位电路280以及第八复位电路290。
如图16所示，第一输入电路110包括第一输入晶体管B1和第二输入晶体管B2。第一输出电路120包括第一输出晶体管D1、第二输出晶体管D2和第二电容C2。第一复位电路140包括第七复位晶体管R7、第八复位晶体管R8和第九复位晶体管R9。第四控制电路170包括第二控制晶体管E2。关于第一输入晶体管B1、第二输入晶体管B2、第一输出晶体管D1、第二输出晶体管D2、第二电容C2、七复位晶体管R7、第八复位晶体管R8、第九复位晶体管R9、第二控制晶体管E2的描述可以参考图13所示的实施例中的相应描述，这里不再赘述。
如图16所示，第二输入电路210包括第三输入晶体管B3和第四输入晶体管B4。第二输出电路220包括第三输出晶体管D3和第三电容C3。
第三输入晶体管B3的栅极被配置为接收第一输入信号STU1，第三输入晶体管B3的第一极和防漏电节点OF连接，第三输入晶体管M3的第二极和第二节点Q2连接。第四输入晶体管B4的栅极和第一极连接且被配置为接收第一输入信号STU1，第四输入晶体管B4的第二极和防漏电节点OF连接；
第三输出晶体管D3的栅极和第二节点Q2连接，第三输出晶体管D3的第一极被配置为接收第四时钟信号CLKD并作为第二输出信号OUT2，第三输出晶体管D3的第二极和第二输出信号端OP2连接且被配置为输出第二输出信号OUT2。第三电容C3的第一极和第二节点Q2连接，第三电容C3的 第二极和第三输出晶体管D3的第二极(即第二输出信号端OP2)连接。
如图16所示，第一控制电路130包括第九控制晶体管E9、第十控制晶体管E10、第十一控制晶体管E11和第十二控制晶体管E12。第九控制晶体管E9的栅极和第一极被配置为接收第三电压VDD_A，第九控制晶体管E9的第二极和第十控制晶体管E10的第一极连接。第十控制晶体管E10的栅极和第一节点Q1连接，第十控制晶体管E10的第二极被配置为接收第六电压VGL3。第十一控制晶体管E11的栅极和第九控制晶体管E9的第二极连接，第十一控制晶体管E11的第一极被配置为接收第三电压VDD_A，第十一控制晶体管E11的第二极和第五节点QB_A连接。第十二控制晶体管E12的栅极和第一节点Q1连接，第十二控制晶体管E12的第一极和第五节点QB_A连接，第十二控制晶体管E12的第二极和第一电压端VGL1连接以接收第一电压。
在本公开的实施例中，第六电压VGL3例如为低电平，以下各实施例与此相同，不再赘述。在本公开的实施例中，第六电压VGL3可以和第一电压相同，也可以不同。
如图16所示，第二控制电路230包括第十三控制晶体管E13、第十四控制晶体管E14、第十五控制晶体管E15和第十六控制晶体管E16。第十三控制晶体管E13的栅极和第一极被配置为接收第四电压VDD_B，第十三控制晶体管E13的第二极和第十四控制晶体管E14的第一极连接。第十四控制晶体管E14的栅极和第二节点Q2连接，第十四控制晶体管E14的第二极被配置为接收第六电压VGL3。第十五控制晶体管E15的栅极和第十三控制晶体管E13的第二极连接，第十五控制晶体管E15的第一极被配置为接收第四电压VDD_B，第十五控制晶体管E15的第二极和第六节点QB_B连接。第十六控制晶体管E16的栅极和第二节点Q2连接，第十六控制晶体管E16的第一极和第六节点QB_B连接，第十六控制晶体管E16的第二极和第一电压端VGL1连接以接收第一电压。
如图16所示，第三控制电路160包括第一控制晶体管E1，第四控制电路170包括第二控制晶体管E2，公共控制电路161包括第三控制晶体管E3。
第一控制晶体管E1的栅极被配置为接收第一时钟信号CLKA，第一控制晶体管E1的第一极和第五节点QB_A连接，第一控制晶体管E1的第二极 和公共控制节点CC连接。
第二控制晶体管E2的栅极被配置为接收第一输入信号STU1，第二控制晶体管E2的第一极和第五节点QB_A连接，第二控制晶体管E2的第二极和第一电压端VGL1连接。
第三控制晶体管E3的栅极和第三节点H连接，第三控制晶体管E3的第一极和公共控制节点CC连接，第三控制晶体管E3的第二极和第一电压端VGL1连接。
如图16所示，第五控制电路260包括第四控制晶体管E4，第六控制电路270包括第五控制晶体管E5。
第四控制晶体管E4的栅极被配置为接收第一时钟信号CLKA，第四控制晶体管E4的第一极和第六节点QB_B连接，第四控制晶体管E4的第二极和公共控制节点CC连接。
第五控制晶体管E5的栅极被配置为接收第一输入信号STU1，第五控制晶体管E5的第一极和第六节点QB_B连接，第五控制晶体管E5的第二极和第一电压端VGL1连接。
在本公开的一些实施例提供的移位寄存器单元10中，通过设置公共控制节点CC可以使得第三控制晶体管E3被复用，从而可以简化电路结构。
如图16所示，第二复位电路150包括第十复位晶体管R10、第十一复位晶体管R11和第十二复位晶体管R12。
第十复位晶体管R10的栅极和第六节点QB_B连接，第十复位晶体管R10的第一极和第一节点Q1连接，第十复位晶体管R10的第二极和防漏电节点OF连接。第十一复位晶体管R11的栅极和第六节点QB_B连接，第十一复位晶体管R11的第一极和移位信号输出端CRT连接，第十一复位晶体管R11的第二极和第一电压端VGL1连接以接收第一电压。第十二复位晶体管R12的栅极和第六节点QB_B连接，第十二复位晶体管R12的第一极和第一输出信号端OP1连接，第十二复位晶体管R12的第二极被配置为接收第五电压VGL2。
如图16所示，第三复位电路240包括第十三复位晶体管R13和第十四复位晶体管R14。第四复位电路250包括第十五复位晶体管R15和第十六复位晶体管R16。
第十三复位晶体管R13的栅极和第六节点QB_B连接，第十三复位晶体管R13的第一极和第二节点Q2连接，第十三复位晶体管R13的第二极和防漏电节点OF连接。第十四复位晶体管R14的栅极和第六节点QB_B连接，第十四复位晶体管R14的第一极和第二输出信号端OP2连接，第十四复位晶体管R14的第二极被配置为接收第五电压VGL2。第十五复位晶体管R15的栅极和第五节点QB_A连接，第十五复位晶体管R15的第一极和第二节点Q2连接，第十五复位晶体管R15的第二极和防漏电节点OF连接。第十六复位晶体管R16的栅极和第五节点QB_A连接，第十六复位晶体管R16的第一极和第二输出信号端OP2连接，第十六复位晶体管R16的第二极被配置为接收第五电压VGL2。
如图16所示，第五复位电路180包括第一复位晶体管R1和第五复位晶体R5，第七复位电路280包括第三复位晶体管R3。
第一复位晶体管R1的栅极被配置为接收显示复位信号STD，第一复位晶体管R1的第一极和第一节点Q1连接，第一复位晶体管R1的第二极和防漏电节点OF连接。第五复位晶体管R5的栅极被配置为接收显示复位信号STD，第五复位晶体管R5的第一极和防漏电节点OF连接，第五复位晶体管R5的第二极和第一电压端VGL1连接以接收第一电压。第三复位晶体管R3的栅极被配置为接收显示复位信号STD，第三复位晶体管R3的第一极和第二节点Q2连接，第三复位晶体管R3的第二极和防漏电节点OF连接。
在本公开的一些实施例提供的移位寄存器单元10中，使得第一复位晶体管R1和防漏电节点OF连接，可以防止第一节点Q1通过第一复位晶体管R1发生漏电。类似地，使得第三复位晶体管R3和防漏电节点OF连接，可以防止第二节点Q2通过第三复位晶体管R3发生漏电。另外，在对第一节点Q1和第二节点Q2进行复位时，第五复位晶体管R5可以被复用，从而可以简化该移位寄存器单元10的电路结构。
如图16所示，第六复位电路190包括第二复位晶体管R2和第六复位晶体R6，第八复位电路290包括第四复位晶体管R4。
第二复位晶体管R2的栅极被配置为接收全局复位信号TRST，第二复位晶体管R2的第一极和第一节点Q1连接，第二复位晶体管R2的第二极和防漏电节点OF连接。第六复位晶体管R6的栅极被配置为接收全局复位信号 TRST，第六复位晶体管R6的第一极和防漏电节点OF连接，第六复位晶体管R6的第二极和第一电压端VGL1连接以接收第一电压。第四复位晶体管R4的栅极被配置为接收全局复位信号TRST，第四复位晶体管R4的第一极和第二节点Q2连接，第四复位晶体管R4的第二极和防漏电节点OF连接。
在本公开的一些实施例提供的移位寄存器单元10中，使得第二复位晶体管R2和防漏电节点OF连接，可以防止第一节点Q1通过第二复位晶体管R2发生漏电。类似地，使得第四复位晶体管R4和防漏电节点OF连接，可以防止第二节点Q2通过第四复位晶体管R4发生漏电。另外，在对第一节点Q1和第二节点Q2进行复位时，第六复位晶体管R6可以被复用，从而可以简化该移位寄存器单元10的电路结构。
如图16所示，第一防漏电子电路410包括第一防漏电晶体管A1，第二防漏电子电路420包括第二防漏电晶体管A2。
第一防漏电晶体管A1的栅极和第一节点Q1连接，第一防漏电晶体管A1的第一极被配置为接收第二电压VDD，第一防漏电晶体管A1的第二极和防漏电节点OF连接。
第二防漏电晶体管A2的栅极以及第一极被配置为和防漏电节点OF连接，第二防漏电晶体管A2的第二极被配置为和第一电压端VGL1连接以接收第一电压。
需要说明的是，关于图16中的消隐输入子单元300可以参考图8、图9A-9D中的相应描述，这里不再赘述。
在本公开的一些实施例中，移位寄存器单元10还可以实现为图17所示的电路结构。下面只描述图17所示的移位寄存器单元10与图16所示的移位寄存器单元10的区别，相同之处不再赘述。
如图17所示，第二输入电路210只包括第三输入晶体管B3而不包括第四输入晶体管B4。例如，第一输入信号STU1可以通过第一输入晶体管B1和第二输入晶体管B2对第一节点Q1进行充电，第一输入信号STU1可以通过第一输入晶体管B1和第三输入晶体管B3对第二节点Q2进行充电，也就说，当对第一节点Q1和第二节点Q2进行充电时，第一输入晶体管B1被复用，从而可以节省一个晶体管，进一步简化移位寄存器单元10的电路结构。
如图17所示，第五复位电路180只包括第一复位晶体管R1而不包括第 五复位晶体管R5。例如，当显示复位信号STD为高电平时，可以通过第一复位晶体管R1和第二防漏电晶体管A2对第一节点Q1进行复位操作；同时可以通过第三复位晶体管R3和第二防漏电晶体管A2对第二节点Q2进行复位操作。也就是说，当对第一节点Q1和第二节点Q2进行复位操作时，第二防漏电晶体管A2被复用，从而可以节省一个晶体管，进一步简化移位寄存器单元10的电路结构。
在本公开的一些实施例中，移位寄存器单元10还可以实现为图18所示的电路结构。下面只描述图18所示的移位寄存器单元10与图17所示的移位寄存器单元10的区别，相同之处不再赘述。
如图18所示，第二防漏电子电路420包括第三防漏电晶体管A3。第三防漏电晶体管A3的栅极和第一节点Q1或者第二节点Q2连接，第三防漏电晶体管A3的第一极和防漏电节点OF连接，第三防漏电晶体管A3的第二极和第一电压端VGL1连接以接收第一电压。
和其它实施例不同的是，在图18所示的实施例中，第二防漏电子电路420没有采用二极管连接方式。例如，当第一节点Q1或者第二节点Q2为高电平时，第三防漏电晶体管A3被导通，从而使得防漏电节点OF和第一电压端VGL1之间形成导电路径，从而使得防漏电节点OF的电平大于第一电压端VGL1提供的第一电压。
在本公开的一些实施例中，移位寄存器单元10还可以实现为图19所示的电路结构。下面只描述图19所示的移位寄存器单元10与图17所示的移位寄存器单元10的区别，相同之处不再赘述。
如图19所示，在该移位寄存器单元10中，第三控制电路160包括第六控制晶体管E6，公共控制电路161包括第七控制晶体管E7，第五控制电路260包括第八控制晶体管E8。
第六控制晶体管E6的栅极和第三节点H连接，第六控制晶体管E6的第一极和第五节点QB_A连接，第六控制晶体管E6的第二极和公共控制节点CC连接。
第七控制晶体管E7的栅极被配置为接收第一时钟信号CLKA，第七控制晶体管E7的第一极和公共控制节点CC连接，第七控制晶体管E7的第二极和第一电压端VGL1连接。
第八控制晶体管E8的栅极和第三节点H连接，第八控制晶体管E8的第一极和第六节点QB_B连接，第八控制晶体管E8的第二极和公共控制节点CC连接。
在图19所示的移位寄存器单元10中，通过设置公共控制节点CC可以使得第七控制晶体管E7被复用，从而可以简化电路结构。
在本公开的一些实施例中，移位寄存器单元10还可以实现为图20所示的电路结构。下面只描述图20所示的移位寄存器单元10与图16所示的移位寄存器单元10的区别，相同之处不再赘述。
如图20所示，第五复位电路180只包括第一复位晶体管R1而不包括第五复位晶体管R5。第六复位电路190只包括第二复位晶体管R2而不包括第六复位晶体管R6。从而可以节省晶体管数量，简化电路结构。
在本公开的一些实施例中，移位寄存器单元10还可以实现为图21所示的电路结构。下面只描述图21所示的移位寄存器单元10与图20所示的移位寄存器单元10的区别，相同之处不再赘述。
如图21所示，第二输入电路210只包括第三输入晶体管B3而不包括第四输入晶体管B4，从而可以进一步节省晶体管数量，进一步简化电路结构。
本公开的实施例提供的移位寄存器单元，可以避免第一节点Q1和第二节点Q2发生漏电，避免采用该移位寄存器单元的显示装置发生显示不良问题。同时还可以简化电路结构，从而可以减小采用该移位寄存器单元的显示装置的边框尺寸，提高该显示装置的PPI。
如前所述，在本公开的实施例提供的移位寄存器单元10中，可以利用第一电容C1维持第三节点H处的电位，利用第二电容C2维持第一节点Q1处的电位，利用第三电容C3维持第二节点Q2处的电位。第一电容C1、第二电容C2和第三电容C3可以是通过工艺制程制作的电容器件，例如通过制作专门的电容电极来实现电容器件，该电容的各个电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现，或者在一些示例中，通过设计电路布线参数使得第一电容C1、第二电容C2和第三电容C3也可以通过各个器件之间的寄生电容实现。第一电容C1、第二电容C2和第三电容C3的连接方式不局限于上面描述的方式，也可以为其他适用的连接方式，只要能存储写入到第三节点H、第一节点Q1和第二节点Q2的电平即可。
本公开的一些实施例还提供一种栅极驱动电路20，如图22所示，该栅极驱动电路20包括多个级联的移位寄存器单元10，其中任意一个或多个移位寄存器单元10可以采用本公开的实施例提供的移位寄存器单元10的结构或其变型。图22中的A1、A2、A3、A4、A5和A6表示移位寄存器单元10中的子单元，例如A1、A3和A5分别表示三个移位寄存器单元10中的第一子单元，A2、A4和A6分别表示三个移位寄存器单元10中的第二子单元。
例如，如图22所示，每个移位寄存器单元10包括第一子单元和第二子单元，以分别输出第一输出信号OUT1和第二输出信号OUT2。当该栅极驱动电路20用于驱动一显示面板时，第一输出信号OUT1和第二输出信号OUT2可以分别驱动显示面板中的一行子像素单元。例如，A1、A2、A3、A4、A5以及A6可以分别驱动显示面板的第一行、第二行、第三行、第四行、第五行以及第六行子像素单元。
本公开的实施例提供的栅极驱动电路20，可以共用消隐输入子单元，从而可以减小采用该栅极驱动电路的显示装置的边框尺寸，提高该显示装置的PPI。同时，还可以实现随机补偿，从而可以避免由于逐行顺序补偿造成的扫描线以及显示亮度不均匀等显示不良问题。
下面以图22所示的栅极驱动电路20为例，对栅极驱动电路20中的信号线进行说明。
如图22所示，栅极驱动电路20包括第一子时钟信号线CLK_1、第二子时钟信号线CLK_2和第三子时钟信号线CLK_3。第3n-2级移位寄存器单元中的第一子单元和第一子时钟信号线CLK_1连接以接收第3n-2级移位寄存器单元的第二时钟信号CLKB；第3n-1级移位寄存器单元中的第一子单元和第二子时钟信号线CLK_2连接以接收第3n-1级移位寄存器单元的第二时钟信号CLKB；第3n级移位寄存器单元中的第一子单元和第三子时钟信号线CLK_3连接以接收第3n级移位寄存器单元的第二时钟信号CLKB；n为大于零的整数。
如上所述，在移位寄存器单元10进行级联时，只需要向每一级移位寄存器单元10中的第一子单元依次提供第二时钟信号CLKB即可，该第二时钟信号CLKB可以作为移位信号CR输出以完成扫描移位。
如图22所示，栅极驱动电路20还包括第四子时钟信号线CLK_4、第五 子时钟信号线CLK_5、第六子时钟信号线CLK_6、第七子时钟信号线CLK_7、第八子时钟信号线CLK_8和第九子时钟信号线CLK_9。
第3n-2级移位寄存器单元中的第一子单元和第四子时钟信号线CLK_4连接以接收第3n-2级移位寄存器单元的第三时钟信号CLKC，第3n-2级移位寄存器单元中的第二子单元和第五子时钟信号线CLK_5连接以接收第3n-2级移位寄存器单元的第四时钟信号CLKD。
第3n-1级移位寄存器单元中的第一子单元和第六子时钟信号线CLK_6连接以接收第3n-1级移位寄存器单元的第三时钟信号CLKC，第3n-1级移位寄存器单元中的第二子单元和第七子时钟信号线CLK_7连接以接收第3n-1级移位寄存器单元的第四时钟信号CLKD。
第3n级移位寄存器单元中的第一子单元和第八子时钟信号线CLK_8连接以接收第3n级移位寄存器单元的第三时钟信号CLKC，第3n级移位寄存器单元中的第二子单元和第九子时钟信号线CLK_9连接以接收第3n级移位寄存器单元的第四时钟信号CLKD。
如上所述，通过第四子时钟信号线CLK_4、第五子时钟信号线CLK_5、第六子时钟信号线CLK_6、第七子时钟信号线CLK_7、第八子时钟信号线CLK_8以及第九子时钟信号线CLK_9共六条时钟信号线向各级移位寄存器单元10提供逐行输出的驱动信号。即本公开的实施例提供的栅极驱动电路20可以采用6CLK的时钟信号，这样可以使得该栅极驱动电路20输出的驱动信号的波形交叠，例如可以增加每一行子像素单元的预充电时间，从而使得该栅极驱动电路可以适用于高频率的扫描显示。本公开的实施例对采用的时钟信号的类型不作限定，例如还可以采用8CLK、10CLK等时钟信号。
如图22所示，栅极驱动电路20还包括第十子时钟信号线CLK_10、第十一子时钟信号线CLK_11和第十二子时钟信号线CLK_12。
例如，每一级移位寄存器单元10中的第一子单元和第二子单元都和第十子时钟信号线CLK_10连接以接收全局复位信号TRST。每一级移位寄存器单元10中的选择输入电路310都和第十一子时钟信号线CLK_11以接收选择控制信号OE。每一级移位寄存器单元10中的第一子单元、第二子单元以及第三输入电路320都和第十二子时钟信号线CLK_12以接收第一时钟信号CLKA。
如图22所示，栅极驱动电路20还包括第十三子时钟信号线CLK_13和第十四子时钟信号线CLK_14。
例如，每一级移位寄存器单元10中的第一子单元都和第十三子时钟信号线CLK_13连接以接收第三电压VDD_A；每一级移位寄存器单元10中的第二子单元都和第十四子时钟信号线CLK_14连接以接收第四电压VDD_B。
如图22所示，栅极驱动电路20还包括第十五子时钟信号线CLK_15，第一级移位寄存器单元10中的第一子单元以及第二子单元和第十五子时钟信号线CLK_15连接以接收第一输入信号STU1。
如图22所示，除了第一级移位寄存器单元10外，其它级移位寄存器单元10中的第一子单元和第二子单元和前一级移位寄存器单元10中的第一子单元连接以接收移位信号CR并作为第一输入信号STU1。除了最后两级移位寄存器单元10外，其它级移位寄存器单元10中的第一子单元和第二子单元和后两级移位寄存器单元10中的第一子单元连接以接收移位信号CR并作为显示复位信号STD。
需要说明的是，图22中所示的级联关系仅是一种示例，根据本公开的描述，还可以根据实际情况采用其它级联方式。
例如，在一个示例中，图22所示的栅极驱动电路20中的移位寄存器单元10可以采用图21中所示的电路结构，图23示出了图22所示的栅极驱动电路20工作时的信号时序图。
在图23中，H<5>表示第三级移位寄存器单元10中的第三节点H，第三级移位寄存器单元10对应显示面板中第五行和第六行子像素单元。N<5>表示第三级移位寄存器单元10中的第四节点N。
Q1<1>和Q2<2>分别表示第一级移位寄存器单元10中的第一节点Q1和第二节点Q2；Q1<5>和Q2<6>分别表示第三级移位寄存器单元10中的第一节点Q1和第二节点Q2。括号中的数字表示该节点对应的显示面板中的子像素单元的行数，以下各实施例与此相同，不再赘述。
OUT1<1>和OUT2<2>分别表示第一级移位寄存器单元10输出的第一输出信号OUT1和第二输出信号OUT2。类似地，OUT1<3>和OUT2<4>分别表示第二级移位寄存器单元10输出的第一输出信号OUT1和第二输出信号OUT2；OUT1<5>和OUT2<6>分别表示第三级移位寄存器单元10输出的第 一输出信号OUT1和第二输出信号OUT2。CR<1>、CR<3>和CR<5>分别第一级、第二级和第三级移位寄存器单元10输出的移位信号CR。例如，如图23所示，CR<1>和OUT1<1>相同，CR<3>和OUT1<3>相同，CR<5>和OUT1<5>相同。
1F表示第一帧，DS表示第一帧中的显示时段，BL表示第一帧中的消隐时段。另外，需要说明的是，在图23中是以第三电压VDD_A为低电平而第四电压VDD_B为高电平为例进行示意的，但本公开的实施例不限于此。图23所示的信号时序图中的信号电平只是示意性的，不代表真实电平值。
下面结合图23中的信号时序图以及图21所示的移位寄存器单元10，对图22中所示的栅极驱动电路20的工作原理进行说明。
在第一帧1F开始前，第十子时钟信号线CLK_10和第十一子时钟信号线CLK_11提供高电平，每一级移位寄存器单元10中的第二复位晶体管R2和第四复位晶体管R4导通，从而可以对每一级移位寄存器单元10中的第一节点Q1和第二节点Q2进行复位；每一级移位寄存器单元10中的第五输入晶体管B5和第六输入晶体管B6导通，由于此时接收的第二输入信号STU2为低电平，所以可以对每一级移位寄存器单元10中的第三节点H进行复位，从而在第一帧1F开始前实现全局复位。
在第一帧1F的显示时段DS中，针对第三级移位寄存器单元10(即对应显示面板第五行和第六行的子像素单元)的工作过程描述如下。
在第一阶段1中，第二级移位寄存器单元10中的第一子单元输出的移位信号CR<3>为高电平，即第三级移位寄存器单元10接收的第一输入信号STU1为高电平，所以第一输入晶体管B1、第二输入晶体管B2以及第三输入晶体管B3导通。高电平的第一输入信号STU1通过第一输入晶体管B1和第二输入晶体管B2对第一节点Q1<5>充电，从而将第一节点Q1<5>上拉至高电平；高电平的第一输入信号STU1还可以通过第一输入晶体管B1和第三输入晶体管B3对第二节点Q2<6>进行充电，从而将第二节点Q2<6>上拉至高电平。
第二输出晶体管D2在第一节点Q1<5>的控制下导通，但由于此时第八子时钟信号线CLK_8提供的第三时钟信号CLKC为低电平，所以第三级移位寄存器单元10输出的第一输出信号OUT1<5>为低电平；第三输出晶体管 D3在第二节点Q2<6>的控制下导通，但由于此时第九子时钟信号线CLK_9提供的第四时钟信号CLKD为低电平，所以第三级移位寄存器单元10输出的第二输出信号OUT2<6>为低电平；在此阶段，同时对第三级移位寄存器单元10中的第一节点和第二节点完成预充电。
在第二阶段2中，第八子时钟信号线CLK_8提供的第三时钟信号CLKC变为高电平，第一节点Q1<5>的电位由于自举效应而进一步被拉高，所以第二输出晶体管D2保持导通，从而第三级移位寄存器单元10输出的第一输出信号OUT1<5>变为高电平。但由于此时第九子时钟信号线CLK_9提供的第四时钟信号CLKD仍然为低电平，所以第三级移位寄存器单元10输出的第二输出信号OUT2<6>继续保持低电平。
在第三阶段3中，第九子时钟信号线CLK_9提供的第四时钟信号CLKD变为高电平，第二节点Q2<6>的电位由于自举效应而进一步被拉高，第三输出晶体管D3保持导通，从而第三级移位寄存器单元10输出的第二输出信号OUT2<6>变为高电平。
在第四阶段4中，由于第二电容C2的保持作用，第一节点Q1<5>仍然保持高电平，所以第二输出晶体管D2导通。但由于第八子时钟信号线CLK_8提供的第三时钟信号CLKC变为低电平，所以第三级移位寄存器单元10输出的第一输出信号OUT1<5>变为低电平。同时由于第二电容C2的自举作用，第一节点Q1<5>的电位也会下降。
在第五阶段5中，由于第三电容C3的保持作用，第二节点Q2<6>仍然保持高电平，所以第三输出晶体管D3导通。但由于第九子时钟信号线CLK_9提供的第四时钟信号CLKD变为高电平，所以第三级移位寄存器单元10输出的第二输出信号OUT2<6>变为低电平。同时由于第三电容C3的自举作用，第二节点Q2<6>的电位也会下降。
在第六阶段6中，由于采用6CLK的时钟信号，每三级移位寄存器单元10(每一级依次输出第一输出信号OUT1和第二输出信号OUT2)输出的信号为一个循环，同时又因为第三级移位寄存器单元10接收第五级移位寄存器单元10输出的移位信号CR作为显示复位信号STD，所以在此阶段当第六子时钟信号线CLK_6提供的第三时钟信号CLKC变为高电平时，第三级移位寄存器单元10接收的显示复位信号STD也为高电平，从而使得第一复位晶 体管R1和第三复位晶体管R3导通，从而可以利用低电平的第一电压对第一节点Q1<5>和第二节点Q2<6>完成下拉复位。
第三级移位寄存器单元10驱动显示面板中第五行和第六行的子像素完成显示后，依次类推，第四级、第五级等移位寄存器单元10逐行驱动显示面板中的子像素单元完成一帧的显示驱动。至此，第一帧的显示时段结束。
同时在第一帧1F的显示时段DS中还对第三节点H进行充电，例如，当第一帧1F中需要对第五行子像素单元进行补偿时，则在第一帧1F的显示时段DS中还进行如下操作。
在第二阶段2和第三阶段3中，使得第十一子时钟信号线CLK_11提供和第三级移位寄存器单元10输出的移位信号CR<5>相同的信号，所以第五输入晶体管B5和第六输入晶体管B6导通。同时可以使第三级移位寄存器单元10接收的第二输入信号STU2和移位信号CR<5>相同，从而高电平的第二输入信号STU2可以对第三节点H<5>充电，将第三节点H<5>上拉至高电平。
需要说明的是，上述对第三节点H<5>的充电过程仅是一种示例，本公开的实施例包括但不限于此。例如，第三级移位寄存器单元10接收的第二输入信号STU2还可以和其它级移位寄存器单元10输出的移位信号CR相同，同时使得提供至第十一子时钟信号线CLK_11的信号和该第二输入信号STU2的信号时序相同即可。
第三节点H<5>的高电位可以一直保持到第一帧1F的消隐时段BL中。当第一帧1F中需要对第五行子像素单元进行补偿时，则在第一帧1F的消隐时段BL中进行如下操作。
在第七阶段7中，第十二子时钟信号线CLK_12提供的第一时钟信号CLKA为高电平，由于在此阶段第三节点H<5>保持高电平，所以第七输入晶体管B7导通，高电平的第一时钟信号CLKA通过第七输入晶体管B7传输至第四节点N<5>，从而使得第四节点N<5>变为高电平。第一传输晶体管T1、第二传输晶体管T2以及第三传输晶体管T3在高电平的第一时钟信号CLKA的控制下导通，所以高电平的第一时钟信号CLKA可以分别对第一节点Q1<5>和第二节点Q2<6>进行充电，第一节点Q1<5>和第二节点Q2<6>的电平被拉高。
同时，在第七阶段7中，由于第一电容C1的耦合作用，第四节点N<5>由低电平变为高电平时会对第三节点H<5>进行耦合上拉，从而使得第三节点H<5>可以保持在一个较高的高电位上，保证第七输入晶体管B7被完全导通。
然后第十二子时钟信号线CLK_12提供的第一时钟信号CLKA从高电平变为低电平，从而使得第四节点N<5>变为低电平，由于第一电容C1的耦合作用，第三节点H<5>的电位也会下降。
在第八阶段8中，第八子时钟信号线CLK_8提供的第三时钟信号CLKC变为高电平，第一节点Q1<5>的电位由于自举效应而进一步被拉高，所以第二输出晶体管D2保持导通，从而第三级移位寄存器单元10输出的第一输出信号OUT1<5>变为高电平。但由于此时第九子时钟信号线CLK_9提供的第四时钟信号CLKD仍然为低电平，所以第三级移位寄存器单元10输出的第二输出信号OUT2<6>为低电平。
例如，在第八阶段8输出的第一输出信号OUT1<5>可以用于驱动显示面板中的子像素单元中的感测晶体管，以实现外部补偿。
在第九阶段9中，由于第二电容C2的保持作用，第一节点Q1<5>仍然保持高电平，所以第二输出晶体管D2导通。但由于第八子时钟信号线CLK_8提供的第三时钟信号CLKC变为低电平，所以第三级移位寄存器单元10输出的第一输出信号OUT1<5>变为低电平。同时由于第二电容C2的自举作用，第一节点Q1<5>的电位也会下降。
在第十阶段10中，第十子时钟信号线CLK_10和第十一子时钟信号线CLK_11提供高电平，每一级移位寄存器单元10中的第二复位晶体管R2和第四复位晶体管R4导通，从而可以对每一级移位寄存器单元10中的第一节点Q1和第二节点Q2进行复位；每一级移位寄存器单元10中的第五输入晶体管B5和第六输入晶体管B6导通，由于此时接收的第二输入信号STU2为低电平，所以可以对每一级移位寄存器单元10中的第三节点H进行复位，从而完成全局复位。
至此，第一帧的驱动时序结束。后续在第二帧、第三帧等更多阶段中对栅极驱动电路的驱动可以参考上述描述，这里不再赘述。
需要说明是，在上述对随机补偿的工作原理进行描述时，是以第一帧的 消隐时段输出对应于显示面板的第五行子像素单元的驱动信号为例进行说明的，本公开对此不作限定。例如，当在某一帧的消隐时段中需要输出对应于显示面板的第n行子像素单元的驱动信号时，则需要在该帧的显示时段DS中将对应的第三节点H上拉至高电平，同时在该帧的消隐时段BL中，提供高电平的第一时钟信号CLKA以拉高第一节点Q1或第二节点Q2的电位，然后在需要输出高电平的驱动信号时，提供高电平的第三时钟信号CLKC或第四时钟信号CLKD，n为大于零的整数。
另外，在本公开的实施例中，两个信号时序相同指的是位于高电平的时间同步，而不要求两个信号的幅值相同。
本公开的一些实施例还提供一种栅极驱动电路20，如图24所示，图25为对应图24所示的栅极驱动电路20工作时的信号时序图。下面描述图24所示的栅极驱动电路20与图22所示的栅极驱动电路20的区别。
如图24和图25所示，在该实施例中，栅极驱动电路20采用10CLK的时钟信号，第四子时钟信号线CLK_4、第五子时钟信号线CLK_5、第六子时钟信号线CLK_6、第七子时钟信号线CLK_7、第八子时钟信号线CLK_8、第九子时钟信号线CLK_9、第十五子时钟信号线CLK_15、第十六子时钟信号线CLK_16、第十七子时钟信号线CLK_17和第十八子时钟信号线CLK_18共十条时钟信号线向各级移位寄存器单元10提供逐行输出的驱动信号。在本公开的实施例中，采用10CLK的时钟信号，可以进一步增加每一行子像素单元的预充电时间，从而使得该栅极驱动电路可以适用于更高频率的扫描显示。
在图24和图25所示的实施例中，除了前两级移位寄存器单元10外，其它级移位寄存器单元10和前两级移位寄存器单元10中的第一子单元连接以接收移位信号CR并作为第一输入信号STU1。除了最后四级移位寄存器单元10外，其它级移位寄存器单元10和后四级移位寄存器单元10中的第一子单元连接以接收移位信号CR并作为显示复位信号STD。
如图24所示，第十子时钟信号线CLK_10和前两级移位寄存器单元10中的第一子单元和第二子单元(即A1、A2、A3和A4)连接以提供第一输入信号STU1，同时第十子时钟信号线CLK_10还和其它级移位寄存器单元10连接以提供全局复位信号TRST。采用这种方式，可以节省时钟信号线的 数量，从而可以减小采用该栅极驱动电路的显示装置的边框尺寸，提高该显示装置的PPI。
如图25所示，例如，在该实施例中，选择的是对第十一行子像素单元进行补偿(对应第六级移位寄存器单元10)。在第一帧1F的显示时段DS中，对第三节点H<11>进行充电；在消隐时段BL中，提供高电平的第一时钟信号CLKA，完成对第一节点Q1<11>和第二节点Q2<12>的充电，然后第四子时钟信号线CLK_4提供高电平的第三时钟信号，使得第六级移位寄存器单元10输出的第一输出信号OUT1<11>为高电平，该第一输出信号OUT1<11>可以用于驱动第十一行子像素单元完成外部补偿。
本公开的一些实施例还提供一种显示装置1，如图26所示，该显示装置1包括本公开实施例提供的栅极驱动电路20以及多个呈阵列排布的子像素单元510。例如，该显示装置1还包括显示面板50，多个子像素单元510构成的像素阵列设置在显示面板50中。
栅极驱动电路20中的每一个移位寄存器单元10输出的第一输出信号OUT1和第二输出信号OUT2分别提供至不同行的子像素单元510，例如，栅极驱动电路20通过栅线GL与子像素单元510电连接。栅极驱动电路20用于提供驱动信号至像素阵列，例如该驱动信号可以驱动子像素单元510中的扫描晶体管和感测晶体管。
例如，该显示装置1还可以包括数据驱动电路30，该数据驱动电路30用于提供数据信号至像素阵列。例如，数据驱动电路30通过数据线DL与子像素单元510电连接。
需要说明的是，本实施例中的显示装置1可以为：液晶面板、液晶电视、显示器、OLED面板、OLED电视、电子纸显示装置、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开的实施例提供的显示装置1的技术效果可以参考上述实施例中关于栅极驱动电路20的相应描述，这里不再赘述。
本公开的一些实施例还提供一种驱动方法，可以用于驱动本公开的实施例提供的移位寄存器单元10，多个该移位寄存器单元10可以级联构建本公开一实施例提供的栅极驱动电路，该栅极驱动电路用于驱动显示面板显示至少一帧画面。
该驱动方法包括：防漏电电路400在第一节点Q1的电平的控制下对防漏电节点OF的电平进行控制，使得防漏电节点OF和第一电压端VGL1之间形成导电路径，且使得连接于第一节点Q1和防漏电节点OF之间的电路截止。
需要说明的是，关于本公开的实施例提供的驱动方法的详细描述和技术效果可以参考本公开的实施例中对于移位寄存器单元10和栅极驱动电路20的工作原理的描述，这里不再赘述。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以权利要求的保护范围为准。

Claims (20)

  1. 一种移位寄存器单元，包括第一子单元和防漏电电路，所述第一子单元包括第一输入电路和第一输出电路，其中，
    所述第一输入电路被配置为响应于第一输入信号对第一节点的电平进行控制，
    所述第一输出电路被配置为在所述第一节点的电平的控制下在输出端提供输出信号，
    所述防漏电电路和所述第一节点以及第一电压端连接，且被配置为在所述第一节点的电平的控制下对防漏电节点的电平进行控制，使得所述防漏电节点和所述第一电压端之间形成导电路径，且使得连接于所述第一节点和所述防漏电节点之间的电路截止。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述防漏电电路包括第一防漏电子电路和第二防漏电子电路，
    所述第一防漏电子电路和所述第一节点以及所述防漏电节点连接，且被配置为在所述第一节点的电平的控制下对所述防漏电节点的电平进行控制，
    所述第二防漏电子电路和所述防漏电节点以及所述第一电压端连接，所述第二防漏电子电路被配置为在所述防漏电节点的电平或所述第一节点的电平的控制下，使得所述防漏电节点和所述第一电压端之间形成导电路径。
  3. 根据权利要求2所述的移位寄存器单元，其中，所述第一防漏电子电路包括第一防漏电晶体管，所述第二防漏电子电路包括第二防漏电晶体管；
    所述第一防漏电晶体管的栅极和所述第一节点连接，所述第一防漏电晶体管的第一极被配置为接收第二电压，所述第一防漏电晶体管的第二极和所述防漏电节点连接；
    所述第二防漏电晶体管的栅极以及第一极被配置为和所述防漏电节点连接，所述第二防漏电晶体管的第二极被配置为和所述第一电压端连接。
  4. 根据权利要求2所述的移位寄存器单元，其中，所述第一防漏电子电路包括第一防漏电晶体管，所述第二防漏电子电路包括第三防漏电晶体管；
    所述第一防漏电晶体管的栅极和所述第一节点连接，所述第一防漏电晶体管的第一极被配置为接收第二电压，所述第一防漏电晶体管的第二极和所 述防漏电节点连接；
    所述第三防漏电晶体管的栅极和所述第一节点连接，所述第三防漏电晶体管的第一极和所述防漏电节点连接，所述第三防漏电晶体管的第二极被配置为和所述第一电压端连接。
  5. 根据权利要求1-4任一项所述的移位寄存器单元，还包括消隐输入子单元，其中，所述消隐输入子单元和所述第一节点连接，且被配置为接收选择控制信号并对所述第一节点的电平进行控制。
  6. 根据权利要求5所述的移位寄存器单元，其中，所述消隐输入子单元包括选择控制电路、第三输入电路和第一传输电路；
    所述选择控制电路被配置为响应于所述选择控制信号利用第二输入信号对第三节点的电平进行控制，并保持所述第三节点的电平；
    所述第三输入电路被配置为在所述第三节点的电平的控制下将第一时钟信号传输至第四节点；
    所述第一传输电路和所述第一节点、所述第四节点以及所述防漏电节点电连接，且被配置为响应于所述第一时钟信号对所述第一节点的电平以及所述防漏电节点的电平进行控制。
  7. 根据权利要求6所述的移位寄存器单元，还包括第二子单元，其中，
    所述第二子单元包括第二输入电路和第二输出电路，所述第二输入电路被配置为响应于所述第一输入信号对第二节点的电平进行控制，所述第二输出电路被配置为在所述第二节点的电平的控制下输出第二输出信号；
    所述消隐输入子单元还包括第二传输电路，所述第二传输电路和所述第二节点以及所述防漏电节点电连接，且被配置为响应于所述第一时钟信号将所述防漏电节点的电平传输至所述第二节点。
  8. 根据权利要求7所述的移位寄存器单元，其中，所述第一传输电路包括第一传输晶体管和第二传输晶体管，所述第二传输电路包括第三传输晶体管；
    所述第一传输晶体管的栅极被配置为接收所述第一时钟信号，所述第一传输晶体管的第一极和所述第四节点连接，所述第一传输晶体管的第二极和所述防漏电节点连接；
    所述第二传输晶体管的栅极被配置为接收所述第一时钟信号，所述第二 传输晶体管的第一极和所述防漏电节点连接，所述第二传输晶体管的第二极和所述第一节点连接；
    所述第三传输晶体管的栅极被配置为接收所述第一时钟信号，所述第三传输晶体管的第一极和所述防漏电节点连接，所述第三传输晶体管的第二极和所述第二节点连接。
  9. 根据权利要求7或8所述的移位寄存器单元，其中，所述第一输入电路包括第一输入晶体管和第二输入晶体管，所述第二输入电路包括第三输入晶体管；
    所述第一输入晶体管的栅极以及第一极被配置为接收所述第一输入信号，所述第一输入晶体管的第二极和所述防漏电节点连接；
    所述第二输入晶体管的栅极被配置为接收所述第一输入信号，所述第二输入晶体管的第一极和所述防漏电节点连接，所述第二输入晶体管的第二极和所述第一节点连接；
    所述第三输入晶体管的栅极被配置为接收所述第一输入信号，所述第三输入晶体管的第一极和所述防漏电节点连接，所述第三输入晶体管的第二极和所述第二节点连接。
  10. 根据权利要求9所述的移位寄存器单元，其中，所述第二输入电路还包括第四输入晶体管；
    所述第四输入晶体管的栅极以及第一极被配置为接收所述第一输入信号，所述第四输入晶体管的第二极和所述防漏电节点连接。
  11. 根据权利要求7-10任一项所述的移位寄存器单元，其中，所述第一子单元还包括第一控制电路、第一复位电路、第二复位电路、移位信号输出端以及第一输出信号端；所述第二子单元还包括第二控制电路、第三复位电路、第四复位电路以及第二输出信号端；
    所述输出信号包括移位信号和第一输出信号，所述输出端包括所述移位信号输出端和所述第一输出信号端，所述移位信号输出端被配置为输出所述移位信号，所述第一输出信号端被配置为输出所述第一输出信号；所述第二输出信号端被配置为输出所述第二输出信号；
    所述第一控制电路被配置为在所述第一节点的电平和第三电压的控制下，对第五节点的电平进行控制；
    所述第一复位电路被配置为在所述第五节点的电平的控制下，对所述第一节点、所述移位信号输出端和所述第一输出信号端进行复位；
    所述第二复位电路被配置为在第六节点的电平的控制下，对所述第一节点、所述移位信号输出端和所述第一输出信号端进行复位；
    所述第二控制电路被配置为在所述第二节点的电平和第四电压的控制下，对所述第六节点的电平进行控制；
    所述第三复位电路被配置为在所述第六节点的电平的控制下，对所述第二节点和所述第二输出信号端进行复位；
    所述第四复位电路被配置为在所述第五节点的电平的控制下，对所述第二节点和所述第二输出信号端进行复位。
  12. 根据权利要求11所述的移位寄存器单元，其中，所述第一子单元还包括第三控制电路、第四控制电路和公共控制电路，所述第二子单元还包括第五控制电路和第六控制电路；
    所述第三控制电路和所述第五节点以及公共控制节点连接，且被配置为响应于所述第一时钟信号使得所述第五节点和所述公共控制节点电连接，
    所述公共控制电路和所述公共控制节点以及所述第一电压端电连接，且被配置为在所述第三节点的电平的控制下使得所述公共控制节点和所述第一电压端电连接，
    所述第四控制电路和所述第五节点以及所述第一电压端电连接，且被配置为响应于所述第一输入信号对所述第五节点的电平进行控制；
    所述第五控制电路和所述第六节点以及所述公共控制节点连接，且被配置为响应于所述第一时钟信号使得所述第六节点和所述公共控制节点电连接，
    所述第六控制电路和所述第六节点以及所述第一电压端电连接，且被配置为响应于所述第一输入信号对所述第六节点的电平进行控制。
  13. 根据权利要求12所述的移位寄存器单元，其中，所述第三控制电路包括第一控制晶体管，所述第四控制电路包括第二控制晶体管，所述公共控制电路包括第三控制晶体管，所述第五控制电路包括第四控制晶体管，所述第六控制电路包括第五控制晶体管；
    所述第一控制晶体管的栅极被配置为接收所述第一时钟信号，所述第一 控制晶体管的第一极和所述第五节点连接，所述第一控制晶体管的第二极和所述公共控制节点连接；
    所述第二控制晶体管的栅极被配置为接收第一输入信号，所述第二控制晶体管的第一极和所述第五节点连接，所述第二控制晶体管的第二极和所述第一电压端连接；
    所述第三控制晶体管的栅极和所述第三节点连接，所述第三控制晶体管的第一极和所述公共控制节点连接，所述第三控制晶体管的第二极和所述第一电压端连接；
    所述第四控制晶体管的栅极被配置为接收所述第一时钟信号，所述第四控制晶体管的第一极和所述第六节点连接，所述第四控制晶体管的第二极和所述公共控制节点连接；
    所述第五控制晶体管的栅极被配置为接收所述第一输入信号，所述第五控制晶体管的第一极和所述第六节点连接，所述第五控制晶体管的第二极和所述第一电压端连接。
  14. 根据权利要求11所述的移位寄存器单元，其中，所述第一子单元还包括第三控制电路、第四控制电路和公共控制电路，所述第二子单元还包括第五控制电路和第六控制电路；
    所述第三控制电路和所述第三节点、所述第五节点以及公共控制节点连接，且被配置为在所述第三节点的电平的控制下使得所述第五节点和所述公共控制节点电连接，
    所述公共控制电路和所述公共控制节点以及所述第一电压端电连接，且被配置为响应于所述第一时钟信号使得所述公共控制节点和所述第一电压端电连接，
    所述第四控制电路和所述第五节点以及所述第一电压端电连接，且被配置为响应于所述第一输入信号对所述第五节点的电平进行控制；
    所述第五控制电路和所述第三节点、所述第六节点以及所述公共控制节点连接，且被配置为在所述第三节点的电平的控制下使得所述第六节点和所述公共控制节点电连接，
    所述第六控制电路和所述第六节点以及所述第一电压端电连接，且被配置为响应于所述第一输入信号对所述第六节点的电平进行控制。
  15. 根据权利要求14所述的移位寄存器单元，其中，所述第三控制电路包括第六控制晶体管，所述第四控制电路包括第二控制晶体管，所述公共控制电路包括第七控制晶体管，所述第五控制电路包括第八控制晶体管，所述第六控制电路包括第五控制晶体管；
    所述第六控制晶体管的栅极和所述第三节点连接，所述第六控制晶体管的第一极和所述第五节点连接，所述第六控制晶体管的第二极和所述公共控制节点连接；
    所述第二控制晶体管的栅极被配置为接收第一输入信号，所述第二控制晶体管的第一极和所述第五节点连接，所述第二控制晶体管的第二极和所述第一电压端连接；
    所述第七控制晶体管的栅极被配置为接收所述第一时钟信号，所述第七控制晶体管的第一极和所述公共控制节点连接，所述第七控制晶体管的第二极和所述第一电压端连接；
    所述第八控制晶体管的栅极和所述第三节点连接，所述第八控制晶体管的第一极和所述第六节点连接，所述第八控制晶体管的第二极和所述公共控制节点连接；
    所述第五控制晶体管的栅极被配置为接收所述第一输入信号，所述第五控制晶体管的第一极和所述第六节点连接，所述第五控制晶体管的第二极和所述第一电压端连接。
  16. 根据权利要求12-15任一所述的移位寄存器单元，其中，所述第一子单元还包括第五复位电路和第六复位电路，所述第二子单元还包括第七复位电路和第八复位电路；
    所述第五复位电路和所述第一节点以及所述防漏电节点连接，且被配置为响应于显示复位信号对所述第一节点进行复位，所述第六复位电路和所述第一节点以及所述防漏电节点连接，且被配置为响应于全局复位信号对所述第一节点进行复位；
    所述第七复位电路和所述第二节点以及所述防漏电节点连接，且被配置为响应于所述显示复位信号对所述第二节点进行复位，所述第八复位电路和所述第二节点以及所述防漏电节点连接，且被配置为响应于所述全局复位信号对所述第二节点进行复位。
  17. 根据权利要求16所述的移位寄存器单元，其中，所述第五复位电路包括第一复位晶体管，所述第六复位电路包括第二复位晶体管，所述第七复位电路包括第三复位晶体管，所述第八复位电路包括第四复位晶体管；
    所述第一复位晶体管的栅极被配置为接收所述显示复位信号，所述第一复位晶体管的第一极和所述第一节点连接，所述第一复位晶体管的第二极和所述防漏电节点连接；
    所述第二复位晶体管的栅极被配置为接收所述全局复位信号，所述第二复位晶体管的第一极和所述第一节点连接，所述第二复位晶体管的第二极和所述防漏电节点连接；
    所述第三复位晶体管的栅极被配置为接收所述显示复位信号，所述第三复位晶体管的第一极和所述第二节点连接，所述第三复位晶体管的第二极和所述防漏电节点连接；
    所述第四复位晶体管的栅极被配置为接收所述全局复位信号，所述第四复位晶体管的第一极和所述第二节点连接，所述第四复位晶体管的第二极和所述防漏电节点连接。
  18. 一种栅极驱动电路，包括多个级联的如权利要求1-17任一所述的移位寄存器单元。
  19. 一种显示装置，包括如权利要求18所述的栅极驱动电路。
  20. 一种如权利要求1-17任一所述的移位寄存器单元的驱动方法，包括：
    所述防漏电电路在所述第一节点的电平的控制下对防漏电节点的电平进行控制，使得所述防漏电节点和所述第一电压端之间形成导电路径，且使得连接于所述第一节点和所述防漏电节点之间的电路截止。
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