WO2019015267A1 - 移位寄存器单元及其驱动方法、栅极驱动电路 - Google Patents

移位寄存器单元及其驱动方法、栅极驱动电路 Download PDF

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Publication number
WO2019015267A1
WO2019015267A1 PCT/CN2018/071296 CN2018071296W WO2019015267A1 WO 2019015267 A1 WO2019015267 A1 WO 2019015267A1 CN 2018071296 W CN2018071296 W CN 2018071296W WO 2019015267 A1 WO2019015267 A1 WO 2019015267A1
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Prior art keywords
coupled
transistor
pole
pull
voltage
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PCT/CN2018/071296
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English (en)
French (fr)
Inventor
李蒙
李永谦
袁志东
袁粲
蔡振飞
冯雪欢
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to EP18825852.9A priority Critical patent/EP3657485A4/en
Priority to JP2018549790A priority patent/JP6914270B2/ja
Priority to US16/312,101 priority patent/US11087668B1/en
Publication of WO2019015267A1 publication Critical patent/WO2019015267A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register unit and a driving method thereof, a gate driving circuit, an array substrate, and a display device.
  • OLED Organic Light Emitting Diode
  • LCD liquid crystal display
  • a gate switch circuit of a thin film transistor is usually integrated on an array substrate of a display panel by using a Gate Driver on Array (GOA) technology. Scan drive for the display panel.
  • GOA Gate Driver on Array
  • Such a gate drive circuit integrated on an array substrate using GOA technology is also referred to as a GOA circuit or a shift register circuit.
  • the display device using the GOA circuit can reduce the cost from both the material cost and the manufacturing process by eliminating the part that binds the driving circuit.
  • Embodiments of the present disclosure provide a shift register unit and a driving method thereof, a gate driving circuit, a substrate, and a display device.
  • a shift register unit comprising: an input circuit configured to control a pull-up node according to a first clock signal from a first clock signal end and a trigger signal from a trigger signal end a voltage; a lower stage start-up circuit configured to control the lower stage enable signal according to a voltage of the pull-up node, a voltage of the pull-down node, a second clock signal from the second clock signal end, and a first voltage signal from the first voltage signal end a voltage at the output; a control circuit configured to control a voltage of the pull-down node according to a voltage of the pull-up node and a second voltage signal from the second voltage signal terminal, and control the pull-up node according to the voltage of the pull-down node and the second voltage signal a voltage stabilization circuit configured to control a voltage of the pull-up node and a voltage of the pull-down node according to the third clock signal from the third clock signal terminal, the first voltage signal, and the third voltage signal from
  • each of the at least one output circuit includes a pull-up transistor, a pull-down transistor, and a control transistor.
  • the control electrode of the pull-up transistor is coupled to the pull-up node, the first pole is coupled to the control voltage signal terminal, and the second pole is coupled to the signal output terminal.
  • the control electrode of the pull-down transistor is coupled to the pull-down node, the first pole is coupled to the first voltage signal terminal, and the second pole is coupled to the signal output terminal.
  • the control electrode of the control transistor is coupled to the control clock signal terminal, the first pole is coupled to the first voltage signal terminal, and the second pole is coupled to the signal output terminal.
  • the at least one output circuit includes: a first output circuit configured to be configured according to a voltage of the pull-up node, a voltage of the pull-down node, a first voltage signal, a first control from a signal terminal of the first control clock a clock signal, and a first control voltage signal from the first control voltage signal terminal, controlling a voltage of the first signal output; and a second output circuit configured to be based on a voltage of the pull-up node, a voltage of the pull-down node, the first voltage A signal, a second control clock signal from the second control clock signal terminal, and a second control voltage signal from the second control voltage signal terminal control the voltage at the second signal output.
  • the input circuit includes a first transistor, a second transistor, and a twelfth transistor.
  • the control electrode of the first transistor is coupled to the first clock signal terminal, the first pole is coupled to the trigger signal terminal, and the second pole is coupled to the first pole of the second transistor.
  • the control electrode of the second transistor is coupled to the first clock signal terminal, the first pole is coupled to the second pole of the first transistor, and the second pole is coupled to the pull-up node.
  • the control electrode of the twelfth transistor is coupled to the pull-up node, the first pole is coupled to the first pole of the second transistor, and the second pole is coupled to the second clock signal terminal.
  • the lower stage start-up circuit includes a fourth transistor, a fifth transistor, and a first capacitor.
  • the control electrode of the fourth transistor is coupled to the pull-up node, the first pole is coupled to the second clock signal terminal, and the second pole is coupled to the lower-level enable signal output terminal.
  • the control electrode of the fifth transistor is coupled to the pull-down node, the first pole is coupled to the first voltage signal terminal, and the second pole is coupled to the lower-level enable signal output terminal.
  • the first capacitor is coupled between the pull up node and the lower stage enable signal output.
  • the control circuit includes a third transistor and a fifteenth transistor.
  • the control electrode of the third transistor is coupled to the pull-down node, the first pole is coupled to the second voltage signal terminal, and the second pole is coupled to the pull-up node.
  • the control electrode of the fifteenth transistor is coupled to the pull-up node, the first pole is coupled to the second voltage signal terminal, and the second pole is coupled to the pull-down node.
  • the stabilization circuit includes a thirteenth transistor and a fourteenth transistor.
  • the control electrode of the thirteenth transistor is coupled to the third clock signal end, the first pole is coupled to the first voltage signal end, and the second pole is coupled to the pull-up node.
  • the control electrode of the fourteenth transistor is coupled to the third clock signal terminal, the first pole is coupled to the third voltage signal terminal, and the second pole is coupled to the pull-down node.
  • the first output circuit includes a sixth transistor, a seventh transistor, and an eighth transistor.
  • the control electrode of the sixth transistor is coupled to the pull-up node
  • the first pole is coupled to the first control voltage signal terminal
  • the second pole is coupled to the first signal output terminal
  • the control electrode of the seventh transistor is coupled to the pull-down node.
  • the first pole is coupled to the first voltage signal end
  • the second pole is coupled to the first signal output end
  • the control electrode of the eighth transistor is coupled to the first control clock signal end
  • the first pole and the first A voltage signal end is coupled
  • a second pole is coupled to the first signal output end.
  • the aspect ratio of the seventh transistor is an integer multiple of the aspect ratio of the sixth transistor.
  • the second output circuit includes a ninth transistor, a tenth transistor, and an eleventh transistor.
  • the control electrode of the ninth transistor is coupled to the pull-up node
  • the first pole is coupled to the second control voltage signal terminal
  • the second pole is coupled to the second signal output terminal
  • the control electrode of the tenth transistor is coupled to the pull-down node.
  • the first pole is coupled to the first voltage signal end
  • the second pole is coupled to the second signal output terminal
  • the control electrode of the eleventh transistor is coupled to the second control clock signal signal end, and the first pole thereof
  • the second voltage signal is coupled to the first signal terminal, and the second electrode is coupled to the second signal output terminal.
  • the aspect ratio of the tenth transistor is an integer multiple of the aspect ratio of the ninth transistor.
  • the first clock signal, the second clock signal, and the third clock signal have the same clock period, and the duty ratio is 1:2.
  • a shift register unit comprising: a first transistor, a second transistor, a twelfth transistor, a fourth transistor, a fifth transistor, a first capacitor, a third transistor, and a tenth Five transistors, a thirteenth transistor, a fourteenth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor.
  • the control electrode of the first transistor is coupled to the first clock signal terminal, the first pole is coupled to the trigger signal terminal, and the second pole is coupled to the first pole of the second transistor.
  • the control electrode of the second transistor is coupled to the first clock signal terminal, the first pole is coupled to the second pole of the first transistor, and the second pole is coupled to the pull-up node.
  • the control electrode of the twelfth transistor is coupled to the pull-up node, the first pole is coupled to the first pole of the second transistor, and the second pole is coupled to the second clock signal terminal.
  • the control electrode of the fourth transistor is coupled to the pull-up node, the first pole is coupled to the second clock signal terminal, and the second pole is coupled to the lower-level enable signal output terminal.
  • the control electrode of the fifth transistor is coupled to the pull-down node, the first pole is coupled to the first voltage signal terminal, and the second pole is coupled to the lower-level enable signal output terminal.
  • the first capacitor is coupled between the pull up node and the lower stage enable signal output.
  • the control electrode of the third transistor is coupled to the pull-down node, the first pole is coupled to the second voltage signal terminal, and the second pole is coupled to the pull-up node.
  • the control electrode of the fifteenth transistor is coupled to the pull-up node, the first pole is coupled to the second voltage signal terminal, and the second pole is coupled to the pull-down node.
  • the control electrode of the thirteenth transistor is coupled to the third clock signal end, the first pole is coupled to the first voltage signal end, and the second pole is coupled to the pull-up node.
  • the control electrode of the fourteenth transistor is coupled to the third clock signal terminal, the first pole is coupled to the third voltage signal terminal, and the second pole is coupled to the pull-down node.
  • the control electrode of the sixth transistor is coupled to the pull-up node, the first pole is coupled to the first control voltage signal terminal, and the second pole is coupled to the first signal output terminal.
  • the control electrode of the seventh transistor is coupled to the pull-down node, the first pole is coupled to the first voltage signal terminal, and the second pole is coupled to the first signal output terminal.
  • the control electrode of the eighth transistor is coupled to the first control clock signal end, the first pole is coupled to the first voltage signal terminal, and the second pole is coupled to the first signal output terminal.
  • the control electrode of the ninth transistor is coupled to the pull-up node, the first pole is coupled to the second control voltage signal terminal, and the second pole is coupled to the second signal output terminal.
  • the control electrode of the tenth transistor is coupled to the pull-down node, the first pole is coupled to the first voltage signal terminal, and the second pole is coupled to the second signal output terminal.
  • the control electrode of the eleventh transistor is coupled to the second control clock signal terminal, the first pole is coupled to the first voltage signal terminal, and the second pole is coupled to the second signal output terminal.
  • a method for driving the shift register unit described above is provided.
  • the control clock signals of the respective control clock signal terminals of the at least one output circuit are low level signals.
  • the method includes: inputting a first clock signal through a first clock signal end, inputting a trigger signal through a trigger signal end, turning on an input circuit, raising a voltage of a pull-up node, and controlling a circuit to make a voltage of a pull-down node.
  • Low level the lower stage start circuit outputs a low level signal, and each output circuit outputs a low level signal.
  • the second clock signal is input through the second clock signal end, so that the lower-level starting circuit is turned on, and the lower-level starting circuit outputs a high-level signal, and the voltage of the pull-up node rises to a high level again, and the voltage of the pull-down node is pulled. Keeping low, each output circuit outputs a high level signal.
  • the third clock signal is input through the third clock signal end, the stabilization circuit is turned on, the voltage of the pull-up node is changed to a low level, the voltage of the pull-down node becomes a high level, and the output of the lower-level startup circuit is low. Level signals, each output circuit outputs a low level signal.
  • control clock signal of the control clock signal terminal of one or more of the at least one output circuit is a high level signal.
  • the method includes outputting a low level signal to a signal output of the one or more output circuits.
  • a gate driving circuit includes a plurality of cascaded shift register units, each stage shift register unit being a shift register unit as above.
  • the lower stage start signal output end of each stage shift register unit is coupled to the trigger signal end of the next stage shift register unit.
  • a first clock signal end of the 3n+1th stage shift register unit is coupled to a third clock signal end of the 3n+2th stage shift register unit and a second clock signal end of the 3n+3rd stage shift register unit
  • a second clock signal end of the 3n+1th stage shift register unit is coupled to the first clock signal end of the 3n+2th stage shift register unit and the third clock signal end of the 3n+3rd stage shift register unit
  • the third clock signal end of the 3n+1th stage shift register unit is coupled to the second clock signal end of the 3n+2th stage shift register unit and the first clock signal end of the 3n+3rd stage shift register unit .
  • n is an integer greater than zero.
  • an array substrate including the above-described gate driving circuit.
  • a display device comprising the array substrate as above.
  • FIG. 1 is a schematic block diagram of a shift register unit in accordance with an embodiment of the present disclosure
  • FIG. 2 is a schematic block diagram of a shift register unit in accordance with another embodiment of the present disclosure.
  • FIG. 3 is an exemplary circuit diagram of the shift register unit shown in FIG. 2;
  • FIG. 4 is a timing diagram of signals of a shift register unit, in accordance with an embodiment of the present disclosure.
  • FIG. 5 is a timing diagram of signals of a shift register unit in accordance with another embodiment of the present disclosure.
  • FIG. 6 is a schematic flow chart of a method for driving a shift register unit as shown in FIG. 3;
  • Figure 7 is a circuit diagram of a 3T1C pixel circuit
  • FIG. 8 is a schematic diagram of a gate driving circuit in accordance with an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a display device in accordance with an embodiment of the present disclosure.
  • element A is coupled to element B
  • element A is “directly” or “indirectly” connected to element B by one or more other elements, unless otherwise stated.
  • "an," and "said&quot are intended to include the plural.
  • FIG. 1 shows a schematic block diagram of a shift register unit 100 in accordance with an embodiment of the present disclosure.
  • the shift register unit 100 may include an input circuit 110, a lower stage start circuit 120, a control circuit 130, a stabilization circuit 140, and at least one output circuit (in FIG. 1, only one output circuit 150 is shown as an example). Other output circuits are schematically illustrated by dashed boxes).
  • the input circuit 110 can be coupled to the first clock signal terminal CLK1, the trigger signal terminal STU, the pull-up node Q, and the second clock signal terminal CLK2.
  • the input circuit 110 can control the voltage of the pull-up node Q according to the first clock signal from the first clock signal terminal CLK1 and the trigger signal from the trigger signal terminal STU.
  • the input circuit 110 can provide a trigger signal from the trigger signal terminal STU to the pull-up node Q under the control of the first clock signal from the first clock signal terminal CLK1.
  • the lower stage starting circuit 120 can be coupled to the pull-up node Q, the second clock signal terminal CLK2, the pull-down node QB, the first voltage signal terminal VSS, and the lower-level enable signal output terminal CR.
  • the lower stage starting circuit 120 can control the lower level starting signal according to the voltage of the pull-up node Q, the voltage of the pull-down node QB, the second clock signal from the second clock signal terminal CLK2, and the first voltage signal from the first voltage signal terminal VSS.
  • the voltage at the output CR can supply the second clock signal from the second clock signal terminal CLK2 to the lower stage start signal output terminal CR under the control of the voltage of the pull-up node Q.
  • the lower stage starting circuit 120 can also supply the first voltage signal from the first voltage signal terminal VSS to the lower stage start signal output terminal CR under the control of the voltage of the pull-down node QB.
  • the control circuit 130 can be coupled to the pull-up node Q, the pull-down node QB, and the second voltage signal terminal VSSL.
  • the control circuit 130 can control the voltage of the pull-down node QB according to the voltage of the pull-up node Q and the second voltage signal from the second voltage signal terminal VSSL, and control the voltage of the pull-up node Q according to the voltage of the pull-down node QB and the second voltage signal.
  • the control circuit 130 may provide the second voltage signal from the second voltage signal terminal VSSL to the pull-down node QB under the control of the voltage of the pull-up node Q.
  • the control circuit 130 can also provide the second voltage signal from the second voltage signal terminal VSSL to the pull-up node Q under the control of the voltage of the pull-down node QB.
  • the stabilization circuit 140 can be coupled to the third clock signal terminal CLK3, the first voltage signal terminal VSS, the third voltage signal terminal VH, the pull-up node Q, and the pull-down node QB.
  • the stabilization circuit 140 can control the pull-up node according to the third clock signal from the third clock signal terminal CLK3, the first voltage signal VSS from the first voltage signal terminal VSS, and the third voltage signal from the third voltage signal terminal VH.
  • the voltage of Q and the voltage of the pull-down node QB may supply the first voltage signal from the first voltage signal terminal VSS to the pull-up node Q under the control of the third clock signal from the third clock signal terminal CLK3.
  • the stabilization circuit 140 may also supply the third voltage signal from the third voltage signal terminal VH to the pull-down node QB under the control of the third clock signal from the third clock signal terminal CLK3.
  • the shift register unit 100 may include at least one output circuit, each of the at least one output circuit being configured to be based on a voltage of the pull-up node Q, a voltage of the pull-down node QB, and a first voltage signal The VSS, the control clock signals from the respective control clock signal terminals CLK, and the control voltage signals from the respective control voltage signal terminals VG control the voltages of the respective signal output terminals G.
  • the shift register unit 100 includes an output circuit 150 as an example.
  • the output circuit 150 can be coupled to the pull-up node Q, the pull-down node QB, the first voltage signal terminal VSS, the control clock signal terminal CLK, the control voltage signal terminal VG, and the signal output terminal G.
  • the output circuit 150 can control the signal output according to the voltage of the pull-up node Q, the voltage of the pull-down node QB, the first voltage signal VSS, the control clock signal from the control clock signal terminal CLK, and the control voltage signal from the control voltage signal terminal VG.
  • the voltage at terminal G is the voltage at terminal G.
  • the output circuit 150 can supply a control voltage signal from the control voltage signal terminal VG to the signal output terminal G under the control of the voltage of the pull-up node Q.
  • the output circuit 150 can also supply the first voltage signal from the first voltage signal terminal VSS to the signal output terminal G under the control of the pull-down node QB.
  • a high level of the second clock signal starts when the high level of the first clock signal ends, and a high level of the third clock signal when the high level of the second clock signal ends. Start.
  • the shift register unit usually triggers a shift register signal under the control of a trigger signal, that is, outputs a gate drive signal, so that only one row of pixels can be driven.
  • a trigger signal that is, outputs a gate drive signal
  • the entire gate drive circuit uses a large number of shift register units, resulting in a large footprint and high cost.
  • the shift register unit may output at least one gate drive signal under the control of one trigger signal STU, that is, trigger at least one shift register signal.
  • the second clock signal CLK2 for controlling the lower stage start-up circuit 120 does not continuously supply a high level, but provides a high level only during operation, and thus the power consumption of the shift register unit can be reduced.
  • FIG. 2 shows a schematic block diagram of a shift register unit 200 in accordance with another embodiment of the present disclosure.
  • the input circuit 110, the lower stage start circuit 120, the control circuit 130, and the stabilization circuit 140 of the shift register unit 200 are the same as the shift register unit 100 shown in FIG.
  • the shift register unit 200 further includes a first output circuit 151 and a second output circuit 152.
  • the first output circuit 151 can be coupled to the pull-up node Q, the pull-down node QB, the first voltage signal terminal VSS, the first control clock signal terminal CLKA, the first control voltage signal terminal VG1, and the first signal output terminal G1.
  • the first output circuit 151 can be based on the voltage of the pull-up node Q, the voltage of the pull-down node QB, the first voltage signal from the first voltage signal terminal VSS, the first control clock signal from the first control clock signal terminal CLKA, and
  • the first control voltage signal of the first control voltage signal terminal VG1 controls the voltage of the first signal output terminal G1.
  • the first output circuit 151 can provide the first control voltage signal from the first control voltage signal terminal VG1 to the first signal output terminal G1 under the control of the voltage from the pull-up node Q, or at the pull-down node QB.
  • the first voltage signal from the first voltage signal terminal VSS is supplied to the first signal output terminal G1 under the control of the control.
  • the second output circuit 152 can be coupled to the pull-up node Q, the pull-down node QB, the first voltage signal terminal VSS, the second control clock signal terminal CLKB, the second control voltage signal terminal VG2, and the second signal output terminal G2.
  • the second output circuit 152 can be based on the voltage of the pull-up node Q, the voltage of the pull-down node QB, the first voltage signal from the first voltage signal terminal VSS, the second control clock signal from the second control clock signal terminal CLKB, and
  • the second control voltage signal of the second control voltage signal terminal VG2 controls the voltage of the second signal output terminal G2.
  • the second output circuit 152 can provide the second control voltage signal from the second control voltage signal terminal VG2 to the second signal output terminal G2 under the control of the voltage from the pull-up node Q, or at the pull-down node QB.
  • the first voltage signal from the first voltage signal terminal VSS is supplied to the second signal output terminal G2 under the control of the control.
  • the first voltage signal from the first voltage signal terminal VSS and the second voltage signal from the second voltage signal terminal VSSL are low level signals
  • the third voltage from the third voltage signal terminal VH The signal, the first control voltage signal from the first control voltage signal terminal VG1, and the second control voltage signal from the second control voltage signal terminal VG2 are high level signals.
  • the shift register unit may output two gate drive signals (eg, G1 and G2) under the control of one trigger signal STU, that is, trigger two shift register signals through the first control clock
  • the signal CLKA and the second control clock signal CLKB adjust the output signal to have a simple structure and reduce the number of shift register units used in the display device.
  • FIG. 3 shows an exemplary circuit diagram of the shift register unit 200 shown in FIG. 2.
  • the transistor employed may be an N-type transistor or a P-type transistor.
  • the transistor may be an N-type or P-type field effect transistor (MOSFET), or an N-type or P-type bipolar transistor (BJT).
  • MOSFET N-type or P-type field effect transistor
  • BJT N-type or P-type bipolar transistor
  • the gate of the transistor is referred to as a gate. Since the source and the drain of the transistor are symmetrical, the source and the drain are not distinguished, that is, the source of the transistor can be the first pole (or the second pole), and the drain can be the second pole (or the One pole).
  • any controlled switching device having a strobe signal input can be used to implement the function of the transistor, and the controlled intermediate terminal of the switching device for receiving a control signal (eg, for turning the controlled switching device on and off) is referred to as
  • the control pole has the other ends being the first pole and the second pole, respectively.
  • NMOS N-type field effect transistor
  • each of the at least one output circuit includes a pull-up transistor, a pull-down transistor, and a control transistor.
  • the control electrode of the pull-up transistor is coupled to the pull-up node, the first pole is coupled to the control voltage signal terminal, and the second pole is coupled to the signal output terminal.
  • the control electrode of the pull-down transistor is coupled to the pull-down node, the first pole is coupled to the first voltage signal terminal, and the second pole is coupled to the signal output terminal.
  • the control electrode of the control transistor is coupled to the control clock signal terminal, the first pole is coupled to the first voltage signal terminal, and the second pole is coupled to the signal output terminal.
  • the input circuit 110 may include a first transistor T1, a second transistor T2, and a twelfth transistor T12.
  • the control electrode of the first transistor T1 is coupled to the first clock signal terminal CLK1, the first electrode thereof is coupled to the trigger signal terminal STU, and the second electrode thereof is coupled to the first electrode of the second transistor T2.
  • the control electrode of the second transistor T2 is coupled to the first clock signal terminal CLK1, the first electrode thereof is coupled to the second electrode of the first transistor T1, and the second electrode thereof is coupled to the pull-up node Q.
  • the control electrode of the twelfth transistor T12 is coupled to the pull-up node Q, the first pole is coupled to the first pole of the second transistor T2, and the second pole is coupled to the second clock signal terminal CLK2.
  • the lower stage starting circuit 120 includes a fourth transistor T4, a fifth transistor T5, and a first capacitor C.
  • the control electrode of the fourth transistor T4 is coupled to the pull-up node Q, the first pole is coupled to the second clock signal terminal CLK2, and the second pole is coupled to the lower-level enable signal output terminal CR.
  • the control electrode of the fifth transistor T5 is coupled to the pull-down node QB, the first pole is coupled to the first voltage signal terminal VSS, and the second pole is coupled to the lower-level enable signal output terminal CR.
  • the first capacitor C is coupled between the pull-up node Q and the lower-level enable signal output terminal CR.
  • the control circuit 130 includes a third transistor T3 and a fifteenth transistor T15.
  • the control electrode of the third transistor T3 is coupled to the pull-down node QB, the first pole is coupled to the second voltage signal terminal VSSL, and the second pole is coupled to the pull-up node Q.
  • the control electrode of the fifteenth transistor T15 is coupled to the pull-up node Q, the first pole is coupled to the second voltage signal terminal VSSL, and the second pole is coupled to the pull-down node QB.
  • the stabilization circuit 140 includes a thirteenth transistor T13 and a fourteenth transistor T14.
  • the control electrode of the thirteenth transistor T13 is coupled to the third clock signal terminal CLK3, the first pole thereof is coupled to the first voltage signal terminal VSS, and the second pole thereof is coupled to the pull-up node Q.
  • the control electrode of the fourteenth transistor T14 is coupled to the third clock signal terminal CLK3, the first pole is coupled to the third voltage signal terminal VH, and the second pole is coupled to the pull-down node QB.
  • the first output circuit 151 includes a sixth transistor T6 (corresponding to a pull-up transistor), a seventh transistor T7 (corresponding to a pull-down transistor), and an eighth transistor T8 (corresponding to a control transistor).
  • the control electrode of the sixth transistor T6 is coupled to the pull-up node Q, the first pole thereof is coupled to the first control voltage signal terminal VG1, and the second pole thereof is coupled to the first signal output terminal (ie, the second transistor of the seventh transistor T7). Pole coupling.
  • the control electrode of the seventh transistor T7 is coupled to the pull-down node QB, the first pole of which is coupled to the first voltage signal terminal VSS, and the second pole of which is coupled to the second pole of the sixth transistor T6.
  • the control electrode of the eighth transistor T8 is coupled to the first control clock signal terminal CLKA, the first pole thereof is coupled to the first voltage signal terminal VSS, and the second electrode thereof is coupled to the second electrode of the sixth transistor T6.
  • the aspect ratio of the seventh transistor T7 is an integer multiple of the aspect ratio of the sixth transistor T6.
  • the second output circuit 152 includes a ninth transistor T9 (corresponding to a pull-up transistor), a tenth transistor T10 (corresponding to a pull-down transistor), and an eleventh transistor T11 (corresponding to a control transistor).
  • the control electrode of the ninth transistor T9 is coupled to the pull-up node Q, the first pole is coupled to the second control voltage signal terminal VG2, and the second pole and the second signal output terminal (ie, the second transistor of the tenth transistor T10) Pole coupling.
  • the control electrode of the tenth transistor T10 is coupled to the pull-down node QB, the first pole of which is coupled to the first voltage signal terminal VSS, and the second pole of which is coupled to the second pole of the ninth transistor T9.
  • the control electrode of the eleventh transistor T11 is coupled to the second control clock signal signal terminal CLKB, the first electrode of which is coupled to the first voltage signal terminal VSS, and the second electrode of which is coupled to the second electrode of the ninth transistor T9.
  • the aspect ratio of the tenth transistor T10 is an integer multiple of the aspect ratio of the ninth transistor T9.
  • the transistors in the shift register unit are all N-type transistors as an example.
  • the first voltage signal VSS and the second voltage signal VSSL are low level signals
  • the third voltage signal VH, the first control voltage signal VG1, and the second control voltage signal VG2 are high level signals.
  • the first control clock signal CLKA and the second control clock signal CLKB are low level (VGL). Therefore, the eighth transistor T8 and the eleventh transistor T11 are kept in an off state.
  • the first clock signal CLK1 is a high level
  • the second clock signal CLK2 is a low level
  • the third clock signal CLK3 is a low level
  • the trigger signal STU is a high level.
  • the first transistor T1 and the second transistor T2 of the input circuit 110 are turned on, and the trigger signal STU is supplied to the pull-up node Q, causing the voltage of the pull-up node Q to rise.
  • the fifteenth transistor T15 is turned on, and the second voltage signal VSSL is supplied to the pull-down node QB, that is, the voltage of the pull-down node QB is pulled down, so that the third transistor T3, the fifth transistor T5, the seventh transistor T7, and the tenth transistor T10 cutoff.
  • the first signal is controlled by controlling the ratio of the aspect ratio of the seventh transistor T7 to the sixth transistor T6 and the ratio of the aspect ratio of the tenth transistor T10 to the ninth transistor T9 under the control of the voltage of the pull-up node Q.
  • Both the output terminal G1 and the second signal output terminal G2 output a low level signal.
  • the fourth transistor T4 is turned on, and the second clock signal CLK2 is supplied to the lower-level enable signal output terminal CR, that is, the lower-level enable signal output terminal CR also outputs a low-level signal.
  • the signals output by the lower-level enable signal output terminal CR, the first signal output terminal G1, and the second signal output terminal G2 are slightly floating, but can still be regarded as a low-level signal.
  • the aspect ratio of the seventh transistor T7 is set to be an integral multiple of the aspect ratio of the sixth transistor T6, and the aspect ratio of the tenth transistor T10 is set to be an integral multiple of the aspect ratio of the ninth transistor T9.
  • the first clock signal CLK1 is a low level
  • the second clock signal CLK2 is a high level
  • the third clock signal CLK3 is a low level
  • the trigger signal STU is a low level. Since the voltage of the pull-up node Q rises enough to turn on the fourth transistor T4 during P1, the second clock signal CLK2 is transmitted to the lower-level enable signal output terminal CR through the fourth transistor T4, so the lower-level enable signal output terminal CR Output a high level signal. Through the capacitor C, the voltage of the pull-up node Q is further pulled up to a high level due to bootstrapping.
  • the twelfth transistor T12 is turned on, and the second clock signal CLK2 is supplied to the node between the first transistor T1 and the second transistor T2, so that the second transistor T2 is turned off more thoroughly, further reducing the leakage current of the pull-up node Q. . Further, the sixth transistor T6 and the ninth transistor T9 are turned on, and the first control voltage signal VG1 and the second control voltage signal VG2 are supplied to the first signal output terminal G1 and the second signal output terminal G2, respectively.
  • the fifteenth transistor T15 remains turned on, and the voltage of the pull-down node QB is controlled to be a low level, and therefore, the fifth transistor T5, the seventh transistor T7, and the tenth transistor T10 remains cut off.
  • the lower stage start signal output terminal CR, the first signal output terminal G1, and the second signal output terminal G2 output a stable high level signal.
  • the first clock signal CLK1 is a low level
  • the second clock signal CLK2 is a low level
  • the third clock signal CLK3 is a high level
  • the trigger signal STU is a low level.
  • the thirteenth transistor T13 and the fourteenth transistor T14 are turned on, providing the first voltage signal VSS to the pull-up node Q, and the third voltage signal VH to the pull-down node QB, that is, the pull-up node Q The voltage is pulled low and the voltage at the pull-down node QB is pulled high.
  • the fourth transistor T4, the sixth transistor T6, and the ninth transistor T9 are turned off, and the fifth transistor T5, the seventh transistor T7, and the tenth transistor T10 are turned on.
  • the lower-level start signal output terminal CR outputs a low-level signal
  • the first signal output terminal G1 outputs a low-level signal
  • the second signal output terminal G2 outputs a low-level signal.
  • the high levels of the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 are sequentially supplied, the trigger signal STU is kept at a low level, and the lower stage enable signal output terminal CR, the first signal The output terminal G1 and the second signal output terminal G2 maintain an output low level signal.
  • one of the first control clock signal CLKA and the second control clock signal CLKB is a low level, and the other is a high level.
  • the first control clock signal CLKA is a low level (VGL)
  • the second control clock signal CLKB is a high level (VGH). Therefore, the eighth transistor T8 is turned off, and the eleventh transistor T11 is turned on.
  • the first output signal outputted by the first signal output terminal G1 is the same as that of FIG. 4, and the second signal output terminal G2 keeps outputting a low level signal.
  • the eighth transistor T8 is turned on, and the eleventh transistor T11 is turned off.
  • the first signal output terminal G1 outputs a hold low level signal
  • the second signal output terminal G2 outputs a second output signal identical to that of FIG.
  • the two output signals can be controlled by correspondingly adjusting the first control clock signal CLKA and the second control clock signal CLKB.
  • the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 may have the same clock period, and the duty ratio is 1:2.
  • FIG. 6 is a schematic flowchart of a method for driving a shift register unit according to an embodiment of the present disclosure, wherein a control clock signal of a control clock signal terminal of each of the at least one output circuit is a low level signal .
  • the first voltage signal VSS and the second voltage signal VSSL are low level signals
  • the third voltage signal VH and each of the at least one output circuit VG are high level signals.
  • step S610 in the first time period, the first clock signal (for example, a high level signal) is input through the first clock signal end, and the input signal is turned on by the trigger signal inputting the trigger signal, and the voltage of the pull-up node is raised. High, the control circuit makes the voltage of the pull-down node low, and the lower-level start signal output end of the lower-level start circuit outputs a low-level signal, and the signal output end of each output circuit outputs a low-level signal.
  • the first clock signal for example, a high level signal
  • step S620 in the second time period, the second clock signal (for example, a high level signal) is input through the second clock signal end, so that the lower stage start circuit is turned on, and the lower stage start signal output end of the lower stage start circuit outputs a high level.
  • step S630 in the third time period, the third clock signal (for example, a high level signal) is input through the third clock signal terminal, the stabilization circuit is turned on, and the voltage of the pull-up node is turned to a low level, and the pull-down node is The voltage becomes a high level, and the lower stage start signal output end of the lower stage start circuit outputs a low level signal, and the signal output end of each output circuit outputs a low level signal.
  • the third clock signal for example, a high level signal
  • control clock signal of the control clock signal terminal of one or more of the at least one output circuit is a high level signal.
  • the signal output of the one or more output circuits outputs a low level signal.
  • one or more driving signals can be output under the control of one trigger signal by changing a control clock signal of a control clock signal terminal of one or more of the at least one output circuits. Furthermore, leakage currents and device power consumption can be reduced in accordance with embodiments of the present disclosure.
  • the threshold voltage Vth may be unstable, and in this case, the shift of the threshold voltage Vth may occur for a long time of operation. Therefore, the pixel circuit design of the OLED display panel needs to consider threshold voltage Vth compensation, mobility compensation, and optical compensation.
  • a shift register unit according to an embodiment of the present disclosure can be applied to, for example, an AMOLED 3T1C pixel circuit to better perform external compensation.
  • Fig. 7 shows a circuit diagram of a 3T1C pixel circuit.
  • the 3T1C circuit includes a switching transistor TFT1, a sensing transistor TFT2, a driving transistor TFT3, a storage capacitor CST, and a light emitting diode OLED.
  • the switching transistor TFT1, the sensing transistor TFT2, and the driving transistor TFT3 are all N-type transistor TFTs.
  • the control electrode of the switching transistor TFT1 is coupled to the first signal output terminal G1 of the shift register unit 200 shown in FIG. 2, the first electrode of which is coupled to the data write signal Data, and the second electrode of which is coupled to the control electrode of the driving transistor TFT3. .
  • the control electrode of the sensing transistor TFT2 is coupled to the second signal output terminal G2 of the shift register unit shown in FIG. 2, the first electrode of which is coupled to the sensing signal Sense, and the second electrode of which is coupled to the second electrode of the driving transistor TFT3.
  • the first electrode of the driving transistor TFT3 is coupled to the high level signal VDD.
  • the storage capacitor CST is coupled between the second electrode of the switching transistor TFT1 and the second electrode of the driving transistor TFT3.
  • the anode of the LED OLED is coupled to the second pole of the driving transistor TFT3, and the cathode is coupled to the low level signal VSS.
  • the first output signal G1 and the second output signal G2 are first set, that is, the first control clock signal CLKA and the second control clock signal CLKB are both low. .
  • the first output signal G1 and the second output signal G2 are both at a high level.
  • the first control clock signal CLKA is held low
  • the second control clock signal CLKB is set to a high level, so that the first output signal G1 is maintained at a high level, and the second output signal G2 is changed to a low level.
  • Level for data writing Under the control of the first output signal G1, the data write signal Data is transmitted to the switching transistor TFT1, that is, the gate electrode of the driving transistor TFT3. Further, under the control of the data write signal Data, the high level signal VDD is transmitted to the second electrode of the driving transistor TFT3, thereby driving the light emitting diode OLED to emit light.
  • the sensing compensation phase the first control clock signal CLKA and the second control clock signal CLKB are both at a low level, whereby the first output signal G1 and the second output signal G2 are both maintained at a high level during the second period of time level.
  • the sensing compensation signal Sense is transferred to the sensing transistor under the control of the second output signal G2.
  • the second pole of the TFT 2 that is, the second pole of the driving transistor TFT3, passes through the storage capacitor CST, and the voltage of the gate of the driving transistor TFT3 is pulled up to the voltage of the second pole of the driving transistor TFT3, thereby further controlling the driving of the light emitting diode The current of the OLED.
  • the shift register unit outputs two drive signals, that is, the first output signal G1 and the second output signal G2, under the control of one trigger signal STU to better control the 3T1C pixel circuit.
  • the shift register unit of the embodiment of the present disclosure has a simple structure and can reduce power consumption and leakage current.
  • FIG. 8 shows a schematic structural diagram of a gate driving circuit 800 according to an embodiment of the present disclosure.
  • the gate driving circuit 800 may include a plurality of cascaded shift register units SR1, SR2, ..., SRn, SR(n+1), .
  • Each stage shift register unit can adopt the structure of the shift register unit 100 as shown in FIG.
  • the port of each stage of the shift register unit may include: a first voltage signal terminal VSS, a second voltage signal terminal VSSL, a third voltage signal terminal VH, and at least one control voltage signal terminal VG (shown only One), the first clock signal terminal CLK1, the second clock signal terminal CLK2, the third clock signal terminal CLK3, at least one control clock signal terminal CLK (only one shown), the trigger signal terminal STU, the lower-level enable signal output terminal CR And at least one signal output G (only one shown).
  • the lower stage start signal output terminal CR of each stage shift register unit SR(n) is coupled to the trigger signal terminal STU of the next stage shift register unit SR(n+1).
  • a first clock signal end of the 3n+1th stage shift register unit is coupled to a third clock signal end of the 3n+2th stage shift register unit and a second clock signal end of the 3n+3rd stage shift register unit
  • a second clock signal end of the 3n+1th stage shift register unit is coupled to the first clock signal end of the 3n+2th stage shift register unit and the third clock signal end of the 3n+3rd stage shift register unit
  • the third clock signal end of the 3n+1th stage shift register unit is coupled to the second clock signal end of the 3n+2th stage shift register unit and the first clock signal end of the 3n+3rd stage shift register unit .
  • n is an integer greater than zero.
  • each signal output terminal G can be outputted in full swing to realize output rail to rail.
  • the high level of the second clock signal begins when the high level of the first clock signal ends, and the high level of the third clock signal begins when the high level of the second clock signal ends.
  • the first clock signal, the second clock signal, and the third clock signal may have the same clock period, and the duty ratio is 1:2.
  • FIG. 9 shows a schematic diagram of a display device 900 in accordance with an embodiment of the present disclosure.
  • the display device 900 includes an array substrate 950, wherein the array substrate 950 includes the gate driving circuit 800 shown in FIG.
  • Display device 900 can be, for example, a mobile phone, a tablet computer, a display screen, a wearable device, or the like.
  • the shift register unit can output at least one gate drive signal under control of one trigger signal using only a small number of components, and perform respective output signals through control clock signals of the respective output circuits. Adjustment. Therefore, it can be better applied to the pixel circuit and reduce the complexity and area of the wiring of the gate driving circuit. Furthermore, the shift register unit according to an embodiment of the present disclosure can also reduce signal noise, reduce power consumption, and reduce leakage current.

Abstract

一种移位寄存器单元及其驱动方法、栅极驱动电路。移位寄存器单元包括输入电路（110）、下级启动电路（120）、控制电路（130）、稳定电路（140）、至少一个输出电路（150）。至少一个输出电路（150）可根据上拉节点的电压、下拉节点的电压、第一电压信号、来自各自的控制时钟信号端的控制时钟信号、以及来自各自的控制电压信号端的控制电压信号，控制各自的信号输出端的电压。在第一时钟信号的高电平结束时，第二时钟信号的高电平开始，在第二时钟信号的高电平结束时，第三时钟信号的高电平开始。

Description

移位寄存器单元及其驱动方法、栅极驱动电路
相关申请的交叉引用
本申请要求于2017年7月20日递交的中国专利申请第201710594509.7号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，具体地，涉及移位寄存器单元及其驱动方法、栅极驱动电路、阵列基板以及显示装置。
背景技术
随着显示技术的进步，相对于传统的液晶显示(Liquid Crystal Display，LCD)装置，新一代的有机发光二极管(Organic Light Emitting Diode，OLED)显示装置具有更低的制造成本，更快的反应速度，更高的对比度，更广的视角，更大的工作温度范围，不需要背光单元，色彩鲜艳及轻薄等优点。因此，OLED显示技术成为当前发展最快的显示技术。
为了提高OLED面板的工艺集成度并降低成本，通常采用阵列基板行驱动(Gate Driver on Array，简称GOA)技术而将薄膜晶体管(TFT)的栅极开关电路集成在显示面板的阵列基板上以形成对显示面板的扫描驱动。这种利用GOA技术而集成在阵列基板上的栅极驱动电路也称为GOA电路或移位寄存器电路。采用GOA电路的显示装置由于省去了绑定驱动电路的部分，可以从材料成本和制作工艺两方面降低成本。
发明内容
本公开的实施例提供了一种移位寄存器单元及其驱动方法、栅极驱动电路、基板以及显示装置。
根据本公开的第一个方面，提供了一种移位寄存器单元，包括：输入 电路，其被配置为根据来自第一时钟信号端的第一时钟信号和来自触发信号端的触发信号，控制上拉节点的电压；下级启动电路，其被配置为根据上拉节点的电压、下拉节点的电压、来自第二时钟信号端的第二时钟信号、以及来自第一电压信号端的第一电压信号，控制下级启动信号输出端的电压；控制电路，其被配置为根据上拉节点的电压和来自第二电压信号端的第二电压信号控制下拉节点的电压，以及根据下拉节点的电压和第二电压信号控制上拉节点的电压；稳定电路，其被配置为根据来自第三时钟信号端的第三时钟信号、第一电压信号、以及来自第三电压信号端的第三电压信号，控制上拉节点的电压和下拉节点的电压；以及至少一个输出电路，其被配置为根据上拉节点的电压、下拉节点的电压、第一电压信号、来自各自的控制时钟信号端的控制时钟信号、以及来自各自的控制电压信号端的控制电压信号，控制各自的信号输出端的电压。在第一时钟信号的高电平结束时，第二时钟信号的高电平开始，在第二时钟信号的高电平结束时，第三时钟信号的高电平开始。
在本公开的实施例中，至少一个输出电路中的每个输出电路包括上拉晶体管、下拉晶体管和控制晶体管。上拉晶体管的控制极与上拉节点耦接，其第一极与控制电压信号端耦接，其第二极与信号输出端耦接。下拉晶体管的控制极与下拉节点耦接，其第一极与第一电压信号端耦接，其第二极与信号输出端耦接。控制晶体管的控制极与控制时钟信号端耦接，其第一极与第一电压信号端耦接，其第二极与信号输出端耦接。
在本公开的实施例中，至少一个输出电路包括：第一输出电路，其被配置为根据上拉节点的电压、下拉节点的电压、第一电压信号、来自第一控制时钟信号端的第一控制时钟信号、以及来自第一控制电压信号端的第一控制电压信号，控制第一信号输出端的电压；以及第二输出电路，其被配置为根据上拉节点的电压、下拉节点的电压、第一电压信号、来自第二控制时钟信号端的第二控制时钟信号、以及来自第二控制电压信号端的第二控制电压信号，控制第二信号输出端的电压。
在本公开的实施例中，输入电路包括第一晶体管、第二晶体管和第十 二晶体管。第一晶体管的控制极与第一时钟信号端耦接，其第一极与触发信号端耦接，其第二极与第二晶体管的第一极耦接。第二晶体管的控制极与第一时钟信号端耦接，其第一极与第一晶体管的第二极耦接，其第二极与上拉节点耦接。第十二晶体管的控制极与上拉节点耦接，其第一极与第二晶体管的第一极耦接，其第二极与第二时钟信号端耦接。
在本公开的实施例中，下级启动电路包括第四晶体管、第五晶体管和第一电容器。第四晶体管的控制极与上拉节点耦接，其第一极与第二时钟信号端耦接，其第二极与下级启动信号输出端耦接。第五晶体管的控制极与下拉节点耦接，其第一极与第一电压信号端耦接，其第二极与下级启动信号输出端耦接。第一电容器被耦接在上拉节点和下级启动信号输出端之间。
在本公开的实施例中，控制电路包括第三晶体管和第十五晶体管。第三晶体管的控制极与下拉节点耦接，其第一极与第二电压信号端耦接，其第二极与上拉节点耦接。第十五晶体管的控制极与上拉节点耦接，其第一极与第二电压信号端耦接，其第二极与下拉节点耦接。
在本公开的实施例中，稳定电路包括第十三晶体管和第十四晶体管。第十三晶体管的控制极与第三时钟信号端耦接，其第一极与第一电压信号端耦接，其第二极与上拉节点耦接。第十四晶体管的控制极与第三时钟信号端耦接，其第一极与第三电压信号端耦接，其第二极与下拉节点耦接。
在本公开的实施例中，第一输出电路包括第六晶体管、第七晶体管和第八晶体管。第六晶体管的控制极与上拉节点耦接，其第一极与第一控制电压信号端耦接，其第二极与第一信号输出端耦接；第七晶体管的控制极与下拉节点耦接，其第一极与第一电压信号端耦接，其第二极与第一信号输出端耦接；第八晶体管的控制极与第一控制时钟信号端耦接，其第一极与第一电压信号端耦接，其第二极与第一信号输出端耦接。
在本公开的实施例中，第七晶体管的宽长比是第六晶体管的宽长比的整数倍。
在本公开的实施例中，第二输出电路包括第九晶体管、第十晶体管和 第十一晶体管。第九晶体管的控制极与上拉节点耦接，其第一极与第二控制电压信号端耦接，其第二极与第二信号输出端耦接；第十晶体管的控制极与下拉节点耦接，其第一极与第一电压信号端耦接，其第二极与第二信号输出端耦接；第十一晶体管的控制极与第二控制时钟信号信号端耦接，其第一极与第一电压信号端耦接，其第二极与第二信号输出端耦接。
在本公开的实施例中，第十晶体管的宽长比是第九晶体管的宽长比的整数倍。
在本公开的实施例中，第一时钟信号、第二时钟信号和第三时钟信号具有相同的时钟周期，并且占空比均为1:2。
根据本公开的第二方面，提供了一种移位寄存器单元，包括：第一晶体管、第二晶体管、第十二晶体管、第四晶体管、第五晶体管、第一电容器、第三晶体管、第十五晶体管、第十三晶体管、第十四晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管和第十一晶体管。第一晶体管的控制极与第一时钟信号端耦接，其第一极与触发信号端耦接，其第二极与第二晶体管的第一极耦接。第二晶体管的控制极与第一时钟信号端耦接，其第一极与第一晶体管的第二极耦接，其第二极与上拉节点耦接。第十二晶体管的控制极与上拉节点耦接，其第一极与第二晶体管的第一极耦接，其第二极与第二时钟信号端耦接。第四晶体管的控制极与上拉节点耦接，其第一极与第二时钟信号端耦接，其第二极与下级启动信号输出端耦接。第五晶体管的控制极与下拉节点耦接，其第一极与第一电压信号端耦接，其第二极与下级启动信号输出端耦接。第一电容器被耦接在上拉节点和下级启动信号输出端之间。第三晶体管的控制极与下拉节点耦接，其第一极与第二电压信号端耦接，其第二极与上拉节点耦接。第十五晶体管的控制极与上拉节点耦接，其第一极与第二电压信号端耦接，其第二极与下拉节点耦接。第十三晶体管的控制极与第三时钟信号端耦接，其第一极与第一电压信号端耦接，其第二极与上拉节点耦接。第十四晶体管的控制极与第三时钟信号端耦接，其第一极与第三电压信号端耦接，其第二极与下拉节点耦接。第六晶体管的控制极与上拉节点耦接，其第一极与第一控制电压信号端耦接，其第二极与第一信号输出端耦接。第七晶体管的控制 极与下拉节点耦接，其第一极与第一电压信号端耦接，其第二极与第一信号输出端耦接。第八晶体管的控制极与第一控制时钟信号端耦接，其第一极与第一电压信号端耦接，其第二极与第一信号输出端耦接。第九晶体管的控制极与上拉节点耦接，其第一极与第二控制电压信号端耦接，其第二极与第二信号输出端耦接。第十晶体管的控制极与下拉节点耦接，其第一极与第一电压信号端耦接，其第二极与第二信号输出端耦接。第十一晶体管的控制极与第二控制时钟信号端耦接，其第一极与第一电压信号端耦接，其第二极与第二信号输出端耦接。
根据本公开的第三方面，提供了一种用于驱动上述移位寄存器单元的方法。至少一个输出电路的各自的控制时钟信号端的控制时钟信号为低电平信号。方法包括：在第一时间段，通过第一时钟信号端输入第一时钟信号，通过触发信号端输入触发信号，使输入电路导通，上拉节点的电压升高，控制电路使下拉节点的电压为低电平，下级启动电路输出低电平信号，各个输出电路输出低电平信号。在第二时间段，通过第二时钟信号端输入第二时钟信号，使下级启动电路导通，下级启动电路输出高电平信号，上拉节点的电压再次升高至高电平，下拉节点的电压保持为低电平，各个输出电路输出高电平信号。在第三时间段，通过第三时钟信号端输入第三时钟信号，稳定电路导通，使上拉节点的电压变为低电平，下拉节点的电压变为高电平，下级启动电路输出低电平信号，各个输出电路输出低电平信号。
在本公开的实施例中，至少一个输出电路中的一个或多个输出电路的控制时钟信号端的控制时钟信号为高电平信号。方法包括：该一个或多个输出电路的信号输出端输出低电平信号。
根据本公开的第四方面，提供了一种栅极驱动电路。该栅极驱动电路包括多个级联的移位寄存器单元，每级移位寄存器单元是如上的移位寄存器单元。各级移位寄存器单元的下级启动信号输出端与下一级移位寄存器单元的触发信号端耦接。第3n+1级移位寄存器单元的第一时钟信号端与第3n+2级移位寄存器单元的第三时钟信号端和第3n+3级移位寄存器单元的 第二时钟信号端耦接，第3n+1级移位寄存器单元的第二时钟信号端与第3n+2级移位寄存器单元的第一时钟信号端和第3n+3级移位寄存器单元的第三时钟信号端耦接，以及第3n+1级移位寄存器单元的第三时钟信号端与第3n+2级移位寄存器单元的第二时钟信号端和第3n+3级移位寄存器单元的第一时钟信号端耦接。n是大于0的整数。
根据本公开的第五方面，提供了一种阵列基板，其包括如上的栅极驱动电路。
根据本公开的第六方面，提供了一种显示装置，其包括如上的阵列基板。
附图说明
为了更清楚地说明本公开的技术方案，下面将对实施例的附图进行简单说明。应当知道，以下描述的附图仅仅是本公开的一些实施例，而非对本公开的限制，其中：
图1是根据本公开的实施例的移位寄存器单元的示意性框图；
图2是根据本公开的另一实施例的移位寄存器单元的示意性框图；
图3是图2所示的移位寄存器单元的示例性电路图；
图4是根据本公开的实施例的移位寄存器单元的各信号的时序图；
图5是根据本公开的另一实施例的移位寄存器单元的各信号的时序图；
图6是用于驱动如图3所示的移位寄存器单元的方法的示意性流程图；
图7是3T1C像素电路的电路图；
图8是根据本公开的实施例的栅极驱动电路的示意图；
图9是根据本公开的实施例的显示装置的示意图。
具体实施方式
为了使本公开的实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本公开的实施例的技术方案进行清楚、完整的描述。显然，所描述的实施例仅仅是本公开的一部分实施例，而并非全部的实施例。基于 所描述的实施例，本领域的普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，也都属于本公开的范围。
在下文中，除非特别说明，表述“元件A耦接到元件B”意为元件A“直接”或通过一个或多个其它元件“间接”连接到元件B。
如本文中使用的，除非另外明确陈述，单数形式的“一个”、“该”和“所述”旨在同样包括复数形式。
如本文中使用的，术语“包括”、“包含”特指所述特征，整数，步骤，操作，元件和/或部分的存在，但不排除一个或多个其它特征，整数，步骤，操作，元件，部件和/或其组合的存在或附加。
如本文中使用的，“第一”、“第二”等的表述均是为了区分两个相同名称非相同的实体或者非相同的参量，因此“第一”、“第二”等仅是为了表述的方便，不应理解为对本公开的实施例的限定。
图1示出了根据本公开的实施例的移位寄存器单元100的示意性框图。如图1所示，移位寄存器单元100可包括输入电路110、下级启动电路120、控制电路130、稳定电路140、以及至少一个输出电路(在图1中，仅示出一个输出电路150作为示例，其它输出电路采用虚线框示意性地示出)。
输入电路110可与第一时钟信号端CLK1、触发信号端STU、上拉节点Q和第二时钟信号端CLK2耦接。输入电路110可根据来自第一时钟信号端CLK1的第一时钟信号和来自触发信号端STU的触发信号，控制上拉节点Q的电压。具体地，输入电路110可在来自第一时钟信号端CLK1的第一时钟信号的控制下，将来自触发信号端STU的触发信号提供至上拉节点Q。
下级启动电路120可与上拉节点Q、第二时钟信号端CLK2、下拉节点QB、第一电压信号端VSS和下级启动信号输出端CR耦接。下级启动电路120可根据上拉节点Q的电压、下拉节点QB的电压、来自第二时钟信号端CLK2的第二时钟信号、以及来自第一电压信号端VSS的第一电压信号，控制下级启动信号输出端CR的电压。具体地，下级启动电路120可在上拉节点Q的电压的控制下，将来自第二时钟信号端CLK2的第二时 钟信号提供至下级启动信号输出端CR。此外，下级启动电路120还可在下拉节点QB的电压的控制下，将来自第一电压信号端VSS的第一电压信号提供至下级启动信号输出端CR。
控制电路130可与上拉节点Q、下拉节点QB和第二电压信号端VSSL耦接。控制电路130可根据上拉节点Q的电压和来自第二电压信号端VSSL的第二电压信号控制下拉节点QB的电压，以及根据下拉节点QB的电压和第二电压信号控制上拉节点Q的电压。具体地，控制电路130可在上拉节点Q的电压的控制下，将来自第二电压信号端VSSL的第二电压信号提供至下拉节点QB。此外，控制电路130还可在下拉节点QB的电压的控制下，将来自第二电压信号端VSSL的第二电压信号提供至上拉节点Q。
稳定电路140可与第三时钟信号端CLK3、第一电压信号端VSS、第三电压信号端VH、上拉节点Q和下拉节点QB耦接。稳定电路140可根据来自第三时钟信号端CLK3的第三时钟信号、来自第一电压信号端VSS的第一电压信号VSS、以及来自第三电压信号端VH的第三电压信号，控制上拉节点Q的电压和下拉节点QB的电压。具体地，稳定电路140可在来自第三时钟信号端CLK3的第三时钟信号的控制下，将来自第一电压信号端VSS的第一电压信号提供至上拉节点Q。此外，稳定电路140还可在来自第三时钟信号端CLK3的第三时钟信号的控制下，将来自第三电压信号端VH的第三电压信号提供至下拉节点QB。
根据本公开的实施例的移位寄存器单元100可包括至少一个输出电路，至少一个输出电路中的每个输出电路被配置为根据上拉节点Q的电压、下拉节点QB的电压、第一电压信号VSS、来自各自的控制时钟信号端CLK的控制时钟信号、以及来自各自的控制电压信号端VG的控制电压信号，控制各自的信号输出端G的电压。
如图1所示，以移位寄存器单元100包括一个输出电路150为例。输出电路150可与上拉节点Q、下拉节点QB、第一电压信号端VSS、控制时钟信号端CLK、控制电压信号端VG和信号输出端G耦接。输出电路150可根据上拉节点Q的电压、下拉节点QB的电压、第一电压信号VSS、 来自控制时钟信号端CLK的控制时钟信号、以及来自控制电压信号端VG的控制电压信号，控制信号输出端G的电压。具体地，输出电路150可在上拉节点Q的电压的控制下，将来自控制电压信号端VG的控制电压信号提供至信号输出端G。此外，输出电路150还可在下拉节点QB的控制下，将来自第一电压信号端VSS的第一电压信号提供至信号输出端G。
在本公开的实施例中，在第一时钟信号的高电平结束时，第二时钟信号的高电平开始，在第二时钟信号的高电平结束时，第三时钟信号的高电平开始。
目前，移位寄存器单元通常在一个触发信号的控制下触发一个移位寄存信号，即输出一路栅极驱动信号，因此仅能满足一行像素的驱动。整个栅极驱动电路使用的移位寄存器单元较多，导致占用面积大且成本高。
根据本公开的实施例，移位寄存器单元可以在一个触发信号STU的控制下，输出至少一个栅极驱动信号，即触发至少一个移位寄存信号。通过控制各自的控制时钟信号对各自的输出信号进行调整，结构简单，减小显示装置中所使用的移位寄存器单元的数量。
应注意的是，用于控制下级启动电路120的第二时钟信号CLK2并不是持续提供高电平，而仅在工作时提供高电平，因此可以降低移位寄存器单元的功耗。
图2示出了根据本公开的另一实施例的移位寄存器单元200的示意性框图。如图2所示，移位寄存器单元200的输入电路110、下级启动电路120、控制电路130、稳定电路140与图1所示的移位寄存器单元100相同。此外，移位寄存器单元200还包括第一输出电路151和第二输出电路152。
第一输出电路151可与上拉节点Q、下拉节点QB、第一电压信号端VSS、第一控制时钟信号端CLKA、第一控制电压信号端VG1和第一信号输出端G1耦接。第一输出电路151可根据上拉节点Q的电压、下拉节点QB的电压、来自第一电压信号端VSS的第一电压信号、来自第一控制时钟信号端CLKA的第一控制时钟信号、以及来自第一控制电压信号端VG1的第一控制电压信号，控制第一信号输出端G1的电压。具体地，第一输 出电路151可在来自上拉节点Q的电压的控制下，将来自第一控制电压信号端VG1的第一控制电压信号提供至第一信号输出端G1，或者在下拉节点QB的控制下，将来自第一电压信号端VSS的第一电压信号提供至第一信号输出端G1。
第二输出电路152可与上拉节点Q、下拉节点QB、第一电压信号端VSS、第二控制时钟信号端CLKB、第二控制电压信号端VG2和第二信号输出端G2耦接。第二输出电路152可根据上拉节点Q的电压、下拉节点QB的电压、来自第一电压信号端VSS的第一电压信号、来自第二控制时钟信号端CLKB的第二控制时钟信号、以及来自第二控制电压信号端VG2的第二控制电压信号，控制第二信号输出端G2的电压。具体地，第二输出电路152可在来自上拉节点Q的电压的控制下，将来自第二控制电压信号端VG2的第二控制电压信号提供至第二信号输出端G2，或者在下拉节点QB的控制下，将来自第一电压信号端VSS的第一电压信号提供至第二信号输出端G2。
在本公开的实施例中，来自第一电压信号端VSS的第一电压信号和来自第二电压信号端VSSL的第二电压信号是低电平信号，来自第三电压信号端VH的第三电压信号、来自第一控制电压信号端VG1的第一控制电压信号和来自第二控制电压信号端VG2的第二控制电压信号是高电平信号。
根据本公开的实施例，移位寄存器单元可以在一个触发信号STU的控制下，输出两个栅极驱动信号(例如，G1和G2)，即触发两个移位寄存信号，通过第一控制时钟信号CLKA和第二控制时钟信号CLKB对输出信号进行调整，结构简单，减小显示装置中所使用的移位寄存器单元的数量。
图3示出了图2所示的移位寄存器单元200的示例性电路图。在实施例中，所采用的晶体管可以是N型晶体管或者P型晶体管。具体地，晶体管可以是N型或P型场效应晶体管(MOSFET)，或者N型或P型双极性晶体管(BJT)。在本公开的实施例中，晶体管的栅极被称为控制极。由于晶体管的源极和漏极是对称的，因此对源极和漏极不做区分，即晶体管的源极可以为第一极(或第二极)，漏极可以为第二极(或第一极)。进一步， 可以采用具有选通信号输入的任何受控开关器件来实现晶体管的功能，将用于接收控制信号(例如用于开启和关断受控开关器件)的开关器件的受控中间端称为控制极，另外两端分别为第一极和第二极。以下，以N型场效应晶体管(NMOS)为例进行详细的描述。
在本公开的实施例中，至少一个输出电路中的每个输出电路包括上拉晶体管、下拉晶体管和控制晶体管。上拉晶体管的控制极与上拉节点耦接，其第一极与控制电压信号端耦接，其第二极与信号输出端耦接。下拉晶体管的控制极与下拉节点耦接，其第一极与第一电压信号端耦接，其第二极与信号输出端耦接。控制晶体管的控制极与控制时钟信号端耦接，其第一极与第一电压信号端耦接，其第二极与信号输出端耦接。
如图3所示，输入电路110可包括第一晶体管T1、第二晶体管T2和第十二晶体管T12。第一晶体管T1的控制极与第一时钟信号端CLK1耦接，其第一极与触发信号端STU耦接，其第二极与第二晶体管T2的第一极耦接。第二晶体管T2的控制极与第一时钟信号端CLK1耦接，其第一极与第一晶体管T1的第二极耦接，其第二极与上拉节点Q耦接。第十二晶体管T12的控制极与上拉节点Q耦接，其第一极与第二晶体管T2的第一极耦接，其第二极与第二时钟信号端CLK2耦接。
下级启动电路120包括第四晶体管T4、第五晶体管T5和第一电容器C。第四晶体管T4的控制极与上拉节点Q耦接，其第一极与第二时钟信号端CLK2耦接，其第二极与下级启动信号输出端CR耦接。第五晶体管T5的控制极与下拉节点QB耦接，其第一极与第一电压信号端VSS耦接，其第二极与下级启动信号输出端CR耦接。第一电容器C被耦接在上拉节点Q和下级启动信号输出端CR之间。
控制电路130包括第三晶体管T3和第十五晶体管T15。第三晶体管T3的控制极与下拉节点QB耦接，其第一极与第二电压信号端VSSL耦接，其第二极与上拉节点Q耦接。第十五晶体管T15的控制极与上拉节点Q耦接，其第一极与第二电压信号端VSSL耦接，其第二极与下拉节点QB耦接。
稳定电路140包括第十三晶体管T13和第十四晶体管T14。第十三晶体管T13的控制极与第三时钟信号端CLK3耦接，其第一极与第一电压信号端VSS耦接，其第二极与上拉节点Q耦接。第十四晶体管T14的控制极与第三时钟信号端CLK3耦接，其第一极与第三电压信号端VH耦接，其第二极与下拉节点QB耦接。
第一输出电路151包括第六晶体管T6(相当于上拉晶体管)、第七晶体管T7(相当于下拉晶体管)和第八晶体管T8(相当于控制晶体管)。第六晶体管T6的控制极与上拉节点Q耦接，其第一极与第一控制电压信号端VG1耦接，其第二极与第一信号输出端(即，第七晶体管T7的第二极)耦接。第七晶体管T7的控制极与下拉节点QB耦接，其第一极与第一电压信号端VSS耦接，其第二极与第六晶体管T6的第二极耦接。第八晶体管T8的控制极与第一控制时钟信号端CLKA耦接，其第一极与第一电压信号端VSS耦接，其第二极与第六晶体管T6的第二极耦接。在本公开的实施例中，第七晶体管T7的宽长比是第六晶体管T6的宽长比的整数倍。
第二输出电路152包括第九晶体管T9(相当于上拉晶体管)、第十晶体管T10(相当于下拉晶体管)和第十一晶体管T11(相当于控制晶体管)。第九晶体管T9的控制极与上拉节点Q耦接，其第一极与第二控制电压信号端VG2耦接，其第二极与第二信号输出端(即，第十晶体管T10的第二极)耦接。第十晶体管T10的控制极与下拉节点QB耦接，其第一极与第一电压信号端VSS耦接，其第二极与第九晶体管T9的第二极耦接。第十一晶体管T11的控制极与第二控制时钟信号信号端CLKB耦接，其第一极与第一电压信号端VSS耦接，其第二极与第九晶体管T9的第二极耦接。在本公开的实施例中，第十晶体管T10的宽长比是第九晶体管T9的宽长比的整数倍。
下面结合图4所示的时序图，对如图3所示的移位寄存器单元的工作过程进行详细描述。在以下的描述中，以移位寄存器单元中的晶体管均是N型晶体管为例。第一电压信号VSS和第二电压信号VSSL是低电平信号，第三电压信号VH、第一控制电压信号VG1和第二控制电压信号VG2是高 电平信号。
在图4所示的示例中，第一控制时钟信号CLKA和第二控制时钟信号CLKB是低电平(VGL)。因此，第八晶体管T8和第十一晶体管T11保持截止状态。
在第一时间段(P1)，第一时钟信号CLK1是高电平，第二时钟信号CLK2是低电平，第三时钟信号CLK3是低电平，触发信号STU是高电平。在P1期间，输入电路110的第一晶体管T1和第二晶体管T2导通，触发信号STU被提供至上拉节点Q，使上拉节点Q的电压升高。第十五晶体管T15导通，第二电压信号VSSL被提供至下拉节点QB，即下拉节点QB的电压被拉低，使得第三晶体管T3、第五晶体管T5、第七晶体管T7和第十晶体管T10截止。在上拉节点Q的电压的控制下，通过控制第七晶体管T7与第六晶体管T6的宽长比的比例、以及第十晶体管T10与第九晶体管T9的宽长比的比例，使第一信号输出端G1和第二信号输出端G2均输出低电平信号。第四晶体管T4导通，将第二时钟信号CLK2提供至下级启动信号输出端CR，即下级启动信号输出端CR也输出低电平信号。在实际的仿真中，在P1期间，下级启动信号输出端CR、第一信号输出端G1和第二信号输出端G2所输出的信号略有浮动，但仍可认为是低电平信号。在示例中，设定第七晶体管T7的宽长比为第六晶体管T6的宽长比的整数倍，设定第十晶体管T10的宽长比为第九晶体管T9的宽长比的整数倍。
在第二时间段(P2)，第一时钟信号CLK1是低电平，第二时钟信号CLK2是高电平，第三时钟信号CLK3是低电平，触发信号STU是低电平。由于在P1期间，上拉节点Q的电压升高到足以使第四晶体管T4导通，因此第二时钟信号CLK2通过第四晶体管T4传递至下级启动信号输出端CR，因此下级启动信号输出端CR输出高电平信号。通过电容器C，上拉节点Q的电压由于自举作用(bootstrapping)而被进一步上拉至高电平。第十二晶体管T12导通，将第二时钟信号CLK2提供至第一晶体管T1和第二晶体管T2之间的节点，从而使第二晶体管T2关闭地更彻底，进一步降低上拉节点Q的漏电流。此外，第六晶体管T6和第九晶体管T9导通，将第一控 制电压信号VG1和第二控制电压信号VG2分别提供至第一信号输出端G1和第二信号输出端G2。在上拉节点Q处于第三电平信号的情况下，第十五晶体管T15保持导通，控制下拉节点QB的电压为低电平，因此，第五晶体管T5、第七晶体管T7和第十晶体管T10保持截止。下级启动信号输出端CR、第一信号输出端G1和第二信号输出端G2输出稳定的高电平信号。
在第三时间段(P3)，第一时钟信号CLK1是低电平，第二时钟信号CLK2是低电平，第三时钟信号CLK3是高电平，触发信号STU是低电平。在P3期间，第十三晶体管T13和第十四晶体管T14导通，将第一电压信号VSS提供至上拉节点Q，将第三电压信号VH提供至下拉节点QB，也就是说，上拉节点Q的电压被拉低，下拉节点QB的电压被拉高。第四晶体管T4、第六晶体管T6和第九晶体管T9截止，第五晶体管T5、第七晶体管T7和第十晶体管T10导通。下级启动信号输出端CR输出低电平信号，第一信号输出端G1输出低电平信号，第二信号输出端G2输出低电平信号。
在随后的时间段，第一时钟信号CLK1、第二时钟信号CLK2和第三时钟信号CLK3的高电平依次被提供，触发信号STU保持为低电平，下级启动信号输出端CR、第一信号输出端G1和第二信号输出端G2保持输出低电平信号。
在本公开的另一实施例中，第一控制时钟信号CLKA和第二控制时钟信号CLKB中的一者是低电平，另一者是高电平。例如，第一控制时钟信号CLKA是低电平(VGL)，并且第二控制时钟信号CLKB是高电平(VGH)。因此，第八晶体管T8截止，第十一晶体管T11导通。如图5所示，第一信号输出端G1输出的第一输出信号与图4相同，第二信号输出端G2保持输出低电平信号。
可选地，在第一控制时钟信号CLKA是高电平(VGH)，并且第二控制时钟信号CLKB是低电平(VGL)时，第八晶体管T8导通，第十一晶体管T11截止。第一信号输出端G1输出保持低电平信号，第二信号输出端G2输出的第二输出信号与图4相同。
因此，可以通过对第一控制时钟信号CLKA和第二控制时钟信号CLKB进行对应调整，来控制两个输出信号。
在本公开的实施例中，第一时钟信号CLK1、第二时钟信号CLK2和第三时钟信号CLK3可具有相同的时钟周期，并且占空比均为1:2。
图6是用于驱动根据本公开的实施例的移位寄存器单元的方法的示意性流程图，其中，至少一个输出电路中的每个输出电路的控制时钟信号端的控制时钟信号为低电平信号。在本公开的实施例中，第一电压信号VSS和第二电压信号VSSL是低电平信号，第三电压信号VH和至少一个输出电路中的各个控制电压信号VG是高电平信号。
在步骤S610，在第一时间段，通过第一时钟信号端输入第一时钟信号(例如，高电平信号)，通过触发信号端输入触发信号，使输入电路导通，上拉节点的电压升高，控制电路使下拉节点的电压为低电平，下级启动电路的下级启动信号输出端输出低电平信号，各个输出电路的信号输出端输出低电平信号。
在步骤S620，在第二时间段，通过第二时钟信号端输入第二时钟信号(例如，高电平信号)，使下级启动电路导通，下级启动电路的下级启动信号输出端输出高电平信号，上拉节点的电压再次升高至高电平，下拉节点的电压保持为低电平，各个输出电路的信号输出端输出高电平信号。
在步骤S630，在第三时间段，通过第三时钟信号端输入第三时钟信号(例如，高电平信号)，稳定电路导通，使上拉节点的电压变为低电平，下拉节点的电压变为高电平，下级启动电路的下级启动信号输出端输出低电平信号，各个输出电路的信号输出端输出低电平信号。
在本公开的另一实施例中，至少一个输出电路中的一个或多个输出电路的控制时钟信号端的控制时钟信号为高电平信号。在这种情况下，该一个或多个输出电路的信号输出端输出低电平信号。
由上，根据本公开的实施例可以通过改变至少一个输出电路中的一个或多个输出电路的控制时钟信号端的控制时钟信号，在一个触发信号的控制下，输出一个或多个驱动信号。此外，根据本公开的实施例还可减小漏 电流、降低器件功耗。
通常，OLED显示面板正常工作时可能出现阈值电压Vth不稳定的情况，在这种情况下长时间工作会出现阈值电压Vth的偏移。因此，OLED显示面板的像素电路设计需要考虑阈值电压Vth补偿、迁移率补偿和光学补偿。根据本公开的实施例的移位寄存器单元可应用于诸如AMOLED3T1C像素电路，以更好地进行外部补偿。
图7示出了3T1C像素电路的电路图。如图4所示，3T1C电路包括开关晶体管TFT1、感测晶体管TFT2、驱动晶体管TFT3、存储电容器CST和发光二极管OLED。开关晶体管TFT1、感测晶体管TFT2、驱动晶体管TFT3均为N型晶体管TFT。
开关晶体管TFT1的控制极耦接图2所示的移位寄存器单元200的第一信号输出端G1，其第一极耦接数据写入信号Data，其第二极耦接驱动晶体管TFT3的控制极。感测晶体管TFT2的控制极耦接图2所示的移位寄存器单元的第二信号输出端G2，其第一极耦接感测信号Sense，其第二极耦接驱动晶体管TFT3的第二极。驱动晶体管TFT3的第一极耦接高电平信号VDD。存储电容器CST被耦接在开关晶体管TFT1的第二极和驱动晶体管TFT3的第二极之间。发光二极管OLED的阳极耦接驱动晶体管TFT3的第二极，阴极耦接低电平信号VSS。
在本公开的实施例中，在正常写入阶段，先对第一输出信号G1和第二输出信号G2进行置位，即第一控制时钟信号CLKA和第二控制时钟信号CLKB均为低电平。由此，在上述第二时间段，使第一输出信号G1和第二输出信号G2均为高电平。较短时间后，第一控制时钟信号CLKA保持低电平，将第二控制时钟信号CLKB设置为高电平，以使第一输出信号G1保持为高电平，第二输出信号G2改变为低电平，以进行数据写入。在第一输出信号G1的控制下，将数据写入信号Data传递至开关晶体管TFT1，即驱动晶体管TFT3的控制极。进而，在数据写入信号Data的控制下，将高电平信号VDD传递至驱动晶体管TFT3的第二极，由此来驱动发光二极管OLED发光。
在感测补偿阶段，第一控制时钟信号CLKA和第二控制时钟信号CLKB均为低电平，由此在上述第二时间段，第一输出信号G1和第二输出信号G2均保持为高电平。除上述正常写入阶段中将数据写入信号DATA传递至驱动晶体管TFT3的控制极以写入数据的操作外，在第二输出信号G2的控制下，将感测补偿信号Sense传递至感测晶体管TFT2的第二极，即驱动晶体管TFT3的第二极，通过存储电容器CST，驱动晶体管TFT3的控制极的电压被上拉至驱动晶体管TFT3的第二极的电压，从而进一步控制用于驱动发光二极管OLED的电流。
在本公开的实施例中，移位寄存器单元仅在一个触发信号STU的控制下，输出两个驱动信号，即第一输出信号G1和第二输出信号G2，以更好地控制3T1C像素电路。本公开的实施例的移位寄存器单元结构简单，并可以降低功耗和漏电流。
图8示出根据本公开的实施例的栅极驱动电路800的示意性结构图。如图8所示，栅极驱动电路800可包括多个级联的移位寄存器单元SR1、SR2、…、SRn、SR(n+1)、...。每级移位寄存器单元可以采用如图1所示的移位寄存器单元100的结构。
在栅极驱动电路800中，每级移位寄存器单元的端口可包括：第一电压信号端VSS、第二电压信号端VSSL、第三电压信号端VH、至少一个控制电压信号端VG(仅示出一个)、第一时钟信号端CLK1、第二时钟信号端CLK2、第三时钟信号端CLK3、至少一个控制时钟信号端CLK(仅示出一个)、触发信号端STU、下级启动信号输出端CR、以及至少一个信号输出端G(仅示出一个)。
各级移位寄存器单元SR(n)的下级启动信号输出端CR与下一级移位寄存器单元SR(n+1)的触发信号端STU耦接。第3n+1级移位寄存器单元的第一时钟信号端与第3n+2级移位寄存器单元的第三时钟信号端和第3n+3级移位寄存器单元的第二时钟信号端耦接，第3n+1级移位寄存器单元的第二时钟信号端与第3n+2级移位寄存器单元的第一时钟信号端和第3n+3级移位寄存器单元的第三时钟信号端耦接，以及第3n+1级移位寄 存器单元的第三时钟信号端与第3n+2级移位寄存器单元的第二时钟信号端和第3n+3级移位寄存器单元的第一时钟信号端耦接。n是大于0的整数。
向第一电压信号端VSS输入低电平的第一电压信号(例如，-8V)，向第二电压信号端VSSL输入低电平的第二电压信号(例如，-10V)，向第三电压信号端VH输入高电平的第三电压信号(例如，25V)。由此，各个信号输出端G可全摆幅输出，实现输出轨到轨。
在本公开的实施例中，第一时钟信号的高电平结束时第二时钟信号的高电平开始，以及第二时钟信号的高电平结束时第三时钟信号的高电平开始。进一步地，第一时钟信号、第二时钟信号和第三时钟信号可具有相同的时钟周期，并且占空比均为1:2。
图9示出了根据本公开的实施例的显示装置900的示意图。显示装置900包括阵列基板950，其中阵列基板950包括图8所示的栅极驱动电路800。显示装置900例如可以是移动电话、平板计算机、显示屏、可穿戴设备等。
根据本公开的实施例的移位寄存器单元能够仅采用较少的元件，在一个触发信号的控制下输出至少一级栅极驱动信号，并通过各个输出电路的控制时钟信号对各自的输出信号进行调整。因此，可以更好地应用于像素电路，并降低栅极驱动电路的布线的复杂度和面积。此外，根据本公开的实施例的移位寄存器单元还可降低信号噪声、降低功耗、减少漏电流。
以上对本公开的若干实施方式进行了详细描述，但本公开的保护范围并不限于此。显然，对于本领域的普通技术人员来说，在不脱离本公开的精神和范围的情况下，可以对本公开的实施例进行各种修改、替换或变形。本公开的保护范围由所附权利要求限定。

Claims (18)

  1. 一种移位寄存器单元，包括：
    输入电路，其被配置为根据来自第一时钟信号端的第一时钟信号和来自触发信号端的触发信号，控制上拉节点的电压；
    下级启动电路，其被配置为根据所述上拉节点的电压、下拉节点的电压、来自第二时钟信号端的第二时钟信号、以及来自第一电压信号端的第一电压信号，控制下级启动信号输出端的电压；
    控制电路，其被配置为根据所述上拉节点的电压和来自第二电压信号端的第二电压信号控制所述下拉节点的电压，以及根据所述下拉节点的电压和所述第二电压信号控制所述上拉节点的电压；
    稳定电路，其被配置为根据来自第三时钟信号端的第三时钟信号、所述第一电压信号、以及来自第三电压信号端的第三电压信号，控制所述上拉节点的电压和所述下拉节点的电压；以及
    至少一个输出电路，其被配置为根据所述上拉节点的电压、所述下拉节点的电压、所述第一电压信号、来自各自的控制时钟信号端的控制时钟信号、以及来自各自的控制电压信号端的控制电压信号，控制各自的信号输出端的电压；
    其中，在所述第一时钟信号的高电平结束时，所述第二时钟信号的高电平开始，在所述第二时钟信号的高电平结束时，所述第三时钟信号的高电平开始。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述至少一个输出电路中的每个输出电路包括上拉晶体管、下拉晶体管和控制晶体管，其中，
    所述上拉晶体管的控制极与所述上拉节点耦接，其第一极与所述控制电压信号端耦接，其第二极与所述信号输出端耦接；
    所述下拉晶体管的控制极与所述下拉节点耦接，其第一极与所述第一电压信号端耦接，其第二极与所述信号输出端耦接；
    所述控制晶体管的控制极与所述控制时钟信号端耦接，其第一极与所述第一电压信号端耦接，其第二极与所述信号输出端耦接。
  3. 根据权利要求1所述的移位寄存器单元，其中，所述至少一个输出电路包括：
    第一输出电路，其被配置为根据所述上拉节点的电压、所述下拉节点的电压、所述第一电压信号、来自第一控制时钟信号端的第一控制时钟信号、以及来自第一控制电压信号端的第一控制电压信号，控制第一信号输出端的电压；以及
    第二输出电路，其被配置为根据所述上拉节点的电压、所述下拉节点的电压、所述第一电压信号、来自第二控制时钟信号端的第二控制时钟信号、以及来自第二控制电压信号端的第二控制电压信号，控制第二信号输出端的电压。
  4. 根据权利要求1至3中的任一项所述的移位寄存器单元，其中，所述输入电路包括第一晶体管、第二晶体管和第十二晶体管，其中，
    所述第一晶体管的控制极与所述第一时钟信号端耦接，其第一极与所述触发信号端耦接，其第二极与所述第二晶体管的第一极耦接；
    所述第二晶体管的控制极与所述第一时钟信号端耦接，其第一极与所述第一晶体管的第二极耦接，其第二极与所述上拉节点耦接；以及，
    所述第十二晶体管的控制极与所述上拉节点耦接，其第一极与所述第二晶体管的第一极耦接，其第二极与所述第二时钟信号端耦接。
  5. 根据权利要求1至3中的任一项所述的移位寄存器单元，其中，所述下级启动电路包括第四晶体管、第五晶体管和第一电容器，其中，
    所述第四晶体管的控制极与所述上拉节点耦接，其第一极与所述第二时钟信号端耦接，其第二极与所述下级启动信号输出端耦接；
    所述第五晶体管的控制极与所述下拉节点耦接，其第一极与所述第一电压信号端耦接，其第二极与所述下级启动信号输出端耦接；以及，
    所述第一电容器被耦接在所述上拉节点和所述下级启动信号输出端之间。
  6. 根据权利要求1至3中的任一项所述的移位寄存器单元，其中，所述控制电路包括第三晶体管和第十五晶体管，其中，
    所述第三晶体管的控制极与所述下拉节点耦接，其第一极与所述第二电压信号端耦接，其第二极与所述上拉节点耦接；以及，
    所述第十五晶体管的控制极与所述上拉节点耦接，其第一极与所述第二电压信号端耦接，其第二极与所述下拉节点耦接。
  7. 根据权利要求1至3中的任一项所述的移位寄存器单元，其中，所述稳定电路包括第十三晶体管和第十四晶体管，其中，
    所述第十三晶体管的控制极与所述第三时钟信号端耦接，其第一极与所述第一电压信号端耦接，其第二极与所述上拉节点耦接；以及，
    所述第十四晶体管的控制极与所述第三时钟信号端耦接，其第一极与所述第三电压信号端耦接，其第二极与所述下拉节点耦接。
  8. 根据权利要求3所述的移位寄存器单元，其中，所述第一输出电路包括第六晶体管、第七晶体管和第八晶体管，其中，
    所述第六晶体管的控制极与所述上拉节点耦接，其第一极与所述第一控制电压信号端耦接，其第二极与所述第一信号输出端耦接；
    所述第七晶体管的控制极与所述下拉节点耦接，其第一极与所述第一电压信号端耦接，其第二极与所述第一信号输出端耦接；以及，
    所述第八晶体管的控制极与所述第一控制时钟信号端耦接，其第一极与所述第一电压信号端耦接，其第二极与所述第一信号输出端耦接。
  9. 根据权利要求8所述的移位寄存器单元，其中，
    所述第七晶体管的宽长比是所述第六晶体管的宽长比的整数倍。
  10. 根据权利要求3所述的移位寄存器单元，其中，所述第二输出电路包括第九晶体管、第十晶体管和第十一晶体管，其中，
    所述第九晶体管的控制极与所述上拉节点耦接，其第一极与所述第二控制电压信号端耦接，其第二极与所述第二信号输出端耦接；
    所述第十晶体管的控制极与所述下拉节点耦接，其第一极与所述第一电压信号端耦接，其第二极与所述第二信号输出端耦接；以及，
    所述第十一晶体管的控制极与所述第二控制时钟信号端耦接，其第一极与所述第一电压信号端耦接，其第二极与所述第二信号输出端耦接。
  11. 根据权利要求10所述的移位寄存器单元，其中，
    所述第十晶体管的宽长比是所述第九晶体管的宽长比的整数倍。
  12. 根据权利要求1至3中的任一项所述的移位寄存器单元，其中，
    所述第一时钟信号、所述第二时钟信号和所述第三时钟信号具有相同的时钟周期，并且占空比均为1:2。
  13. 一种移位寄存器单元，包括：第一晶体管、第二晶体管、第十二晶体管、第四晶体管、第五晶体管、第一电容器、第三晶体管、第十五晶体管、第十三晶体管、第十四晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管和第十一晶体管，其中，
    所述第一晶体管的控制极与第一时钟信号端耦接，其第一极与触发信号端耦接，其第二极与所述第二晶体管的第一极耦接；
    所述第二晶体管的控制极与所述第一时钟信号端耦接，其第一极与所述第一晶体管的第二极耦接，其第二极与上拉节点耦接；
    所述第十二晶体管的控制极与所述上拉节点耦接，其第一极与所述第二晶体管的第一极耦接，其第二极与第二时钟信号端耦接；
    所述第四晶体管的控制极与所述上拉节点耦接，其第一极与所述第二时钟信号端耦接，其第二极与下级启动信号输出端耦接；
    所述第五晶体管的控制极与下拉节点耦接，其第一极与第一电压信号端耦接，其第二极与所述下级启动信号输出端耦接；
    所述第一电容器被耦接在所述上拉节点和所述下级启动信号输出端之间；
    所述第三晶体管的控制极与所述下拉节点耦接，其第一极与第二电压信号端耦接，其第二极与所述上拉节点耦接；
    所述第十五晶体管的控制极与所述上拉节点耦接，其第一极与所述第二电压信号端耦接，其第二极与所述下拉节点耦接；
    所述第十三晶体管的控制极与第三时钟信号端耦接，其第一极与所述第一电压信号端耦接，其第二极与所述上拉节点耦接；
    所述第十四晶体管的控制极与所述第三时钟信号端耦接，其第一极与第三电压信号端耦接，其第二极与所述下拉节点耦接；
    所述第六晶体管的控制极与所述上拉节点耦接，其第一极与第一控制电压信号端耦接，其第二极与第一信号输出端耦接；
    所述第七晶体管的控制极与所述下拉节点耦接，其第一极与所述第一电压信号端耦接，其第二极与所述第一信号输出端耦接；
    所述第八晶体管的控制极与第一控制时钟信号端耦接，其第一极与所述第一电压信号端耦接，其第二极与所述第一信号输出端耦接；
    所述第九晶体管的控制极与所述上拉节点耦接，其第一极与第二控制电压信号端耦接，其第二极与第二信号输出端耦接；
    所述第十晶体管的控制极与所述下拉节点耦接，其第一极与所述第一电压信号端耦接，其第二极与所述第二信号输出端耦接；以及，
    所述第十一晶体管的控制极与第二控制时钟信号端耦接，其第一极与所述第一电压信号端耦接，其第二极与所述第二信号输出端耦接。
  14. 一种用于驱动如权利要求1至12中的任一项所述的移位寄存器单元的方法，其中，至少一个输出电路的各自的控制时钟信号端的控制时钟信号为低电平信号，所述方法包括：
    在第一时间段，通过第一时钟信号端输入第一时钟信号，通过触发信号端输入触发信号，使输入电路导通，上拉节点的电压升高，控制电路使下拉节点的电压为低电平，下级启动电路输出低电平信号，各个输出电路输出低电平信号；
    在第二时间段，通过第二时钟信号端输入第二时钟信号，使下级启动电路导通，所述下级启动电路输出高电平信号，所述上拉节点的电压再次升高至高电平，所述下拉节点的电压保持为低电平，各个输出电路输出高电平信号；
    在第三时间段，通过第三时钟信号端输入第三时钟信号，稳定电路导通，使所述上拉节点的电压变为低电平，所述下拉节点的电压变为高电平，所述下级启动电路输出低电平信号，各个输出电路输出低电平信号。
  15. 根据权利要求14所述的方法，其中，所述至少一个输出电路中的一个或多个输出电路的控制时钟信号端的控制时钟信号为高电平信号，所述方法包括：
    所述一个或多个输出电路的信号输出端输出低电平信号。
  16. 一种栅极驱动电路，包括：多个级联的移位寄存器单元，其中，每级移位寄存器单元是如权利要求1至13中的任一项所述的移位寄存器单元，
    其中，各级移位寄存器单元的下级启动信号输出端与下一级移位寄存器单元的触发信号端耦接，
    第3n+1级移位寄存器单元的第一时钟信号端与第3n+2级移位寄存器单元的第三时钟信号端和第3n+3级移位寄存器单元的第二时钟信号端耦接；
    第3n+1级移位寄存器单元的第二时钟信号端与第3n+2级移位寄存器单元的第一时钟信号端和第3n+3级移位寄存器单元的第三时钟信号端耦接；以及
    第3n+1级移位寄存器单元的第三时钟信号端与第3n+2级移位寄存器单元的第二时钟信号端和第3n+3级移位寄存器单元的第一时钟信号端耦接，
    其中，n是正整数。
  17. 一种阵列基板，包括如权利要求16所述的栅极驱动电路。
  18. 一种显示装置，包括如权利要求17所述的阵列基板。
PCT/CN2018/071296 2017-07-20 2018-01-04 移位寄存器单元及其驱动方法、栅极驱动电路 WO2019015267A1 (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113711298A (zh) * 2020-03-18 2021-11-26 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109698006B (zh) * 2019-02-19 2021-01-26 京东方科技集团股份有限公司 移位寄存器及其驱动方法、级联驱动电路和显示装置
CN109830256B (zh) * 2019-03-22 2020-12-04 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、栅极驱动电路
CN110114817B (zh) * 2019-03-25 2022-09-13 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN110007628B (zh) * 2019-04-10 2022-02-01 深圳市华星光电半导体显示技术有限公司 Goa电路及显示面板
CN110517619B (zh) * 2019-08-30 2023-04-21 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
KR20210051551A (ko) * 2019-10-30 2021-05-10 엘지디스플레이 주식회사 박막 트랜지스터, 그를 포함한 게이트 구동부, 및 그를 포함한 표시장치
CN110969977A (zh) * 2019-12-02 2020-04-07 深圳市华星光电半导体显示技术有限公司 一种栅极驱动电路、其控制方法及显示装置
CN111540313B (zh) * 2020-05-11 2021-10-08 京东方科技集团股份有限公司 移位寄存器及驱动方法、驱动电路、显示基板和装置
CN112542140B (zh) 2020-12-16 2022-05-31 合肥京东方卓印科技有限公司 一种移位寄存器、栅极驱动电路以及驱动方法
CN112967652B (zh) * 2021-03-08 2023-05-02 武汉天马微电子有限公司 扫描信号电路、显示面板、显示装置及驱动方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102654982A (zh) * 2011-05-16 2012-09-05 京东方科技集团股份有限公司 移位寄存器单元电路、移位寄存器、阵列基板及液晶显示器
KR20140098880A (ko) * 2013-01-31 2014-08-11 엘지디스플레이 주식회사 쉬프트 레지스터
CN104134430A (zh) * 2014-07-04 2014-11-05 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路及显示装置
CN104464665A (zh) * 2014-12-08 2015-03-25 深圳市华星光电技术有限公司 一种扫描驱动电路
CN104517575A (zh) * 2014-12-15 2015-04-15 深圳市华星光电技术有限公司 移位寄存器及级传栅极驱动电路
CN105609135A (zh) * 2015-12-31 2016-05-25 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101697284B (zh) * 2009-08-24 2013-08-07 友达光电股份有限公司 移位寄存器电路
KR101340197B1 (ko) * 2011-09-23 2013-12-10 하이디스 테크놀로지 주식회사 쉬프트 레지스터 및 이를 이용한 게이트 구동회로
KR102003439B1 (ko) * 2012-12-18 2019-07-24 엘지디스플레이 주식회사 게이트 쉬프트 레지스터와 이를 이용한 표시장치
CN103413514A (zh) * 2013-07-27 2013-11-27 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器和显示装置
CN104282287B (zh) * 2014-10-31 2017-03-08 合肥鑫晟光电科技有限公司 一种goa单元及驱动方法、goa电路和显示装置
KR102281753B1 (ko) * 2015-04-14 2021-07-27 삼성디스플레이 주식회사 스테이지 회로 및 이를 이용한 주사 구동부
CN104835476B (zh) * 2015-06-08 2017-09-15 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及其驱动方法、阵列基板
CN205050536U (zh) * 2015-10-23 2016-02-24 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器和显示装置
CN105609137B (zh) * 2016-01-05 2019-06-07 京东方科技集团股份有限公司 移位寄存器、栅线集成驱动电路、阵列基板及显示装置
CN106887217B (zh) * 2017-05-04 2020-06-26 京东方科技集团股份有限公司 移位寄存器单元及其控制方法、栅极驱动电路、显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102654982A (zh) * 2011-05-16 2012-09-05 京东方科技集团股份有限公司 移位寄存器单元电路、移位寄存器、阵列基板及液晶显示器
KR20140098880A (ko) * 2013-01-31 2014-08-11 엘지디스플레이 주식회사 쉬프트 레지스터
CN104134430A (zh) * 2014-07-04 2014-11-05 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路及显示装置
CN104464665A (zh) * 2014-12-08 2015-03-25 深圳市华星光电技术有限公司 一种扫描驱动电路
CN104517575A (zh) * 2014-12-15 2015-04-15 深圳市华星光电技术有限公司 移位寄存器及级传栅极驱动电路
CN105609135A (zh) * 2015-12-31 2016-05-25 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3657485A4 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113711298A (zh) * 2020-03-18 2021-11-26 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN113711298B (zh) * 2020-03-18 2023-02-07 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置

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