WO2022183489A1 - 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置 - Google Patents

移位寄存器单元及其驱动方法、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2022183489A1
WO2022183489A1 PCT/CN2021/079324 CN2021079324W WO2022183489A1 WO 2022183489 A1 WO2022183489 A1 WO 2022183489A1 CN 2021079324 W CN2021079324 W CN 2021079324W WO 2022183489 A1 WO2022183489 A1 WO 2022183489A1
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WIPO (PCT)
Prior art keywords
transistor
coupled
node
terminal
voltage
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PCT/CN2021/079324
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English (en)
French (fr)
Inventor
卢江楠
商广良
殷新社
刘利宾
奉轲
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京东方科技集团股份有限公司
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Priority to CN202180000419.5A priority Critical patent/CN115398519A/zh
Priority to GB2217259.7A priority patent/GB2609871A/en
Priority to PCT/CN2021/079324 priority patent/WO2022183489A1/zh
Priority to US17/631,780 priority patent/US11915655B2/en
Publication of WO2022183489A1 publication Critical patent/WO2022183489A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • Embodiments of the present disclosure relate to a shift register unit and a driving method thereof, a gate driving circuit, and a display device.
  • pixel arrays such as OLED and liquid crystal displays generally include multiple rows of gate lines and multiple columns of data lines staggered therewith.
  • the driving of the gate lines can be realized by the attached integrated driving circuit.
  • the gate line driver circuit can also be directly integrated on the thin film transistor array substrate to form a GOA (Gate Driver On Array) to drive the gate line.
  • GOA Gate Driver On Array
  • a GOA composed of multiple cascaded shift register units can be used to provide on-off voltage signals for multiple rows of gate lines in the pixel array, so as to control the multiple rows of gate lines to be turned on in sequence, and the data lines to the pixel array corresponding to The pixel units of the row provide data signals to form grayscale voltages required for displaying each grayscale of an image, thereby displaying each frame of image.
  • At least one embodiment of the present disclosure provides a shift register unit including: an input control circuit, a first control circuit, a second control circuit, an output circuit, and a first reset circuit.
  • the input control circuit is coupled to a first node, an input terminal, a first clock signal terminal, a second clock signal terminal, and a third clock signal terminal, and is configured as an input signal at the input terminal, an input signal at the first clock signal terminal Under the control of the first clock signal, the second clock signal at the second clock signal terminal, and the third clock signal at the third clock signal terminal, the level of the first node is controlled;
  • the first control circuit is connected to the The first node and the second node are coupled and configured to control the level of the second node under the control of the level of the first node.
  • the second control circuit is coupled to the fourth clock signal terminal, the second node and the output terminal, and is configured to control the fourth clock signal of the fourth clock signal terminal and the output signal of the output terminal under the control of the output terminal.
  • the level of the second node the output circuit is coupled to the first node, the second node and the output terminal, and is configured to be at the level of the first node and the level of the second node Under the control of the level, the level of the output terminal is controlled;
  • the first reset circuit is coupled to the output terminal and the first enable signal terminal, and the first enable signal terminal is connected by the first enable signal line A first enable signal is provided, and the first reset circuit is configured to control the level of the output terminal under the control of the first enable signal, so as to output a non-operating level stably in the detection phase.
  • the shift register unit provided by at least one embodiment of the present disclosure further includes: a second reset circuit.
  • the second reset circuit is coupled to the second node and a second enable signal terminal, the second enable signal terminal is provided with a second enable signal by a second enable signal line, and is configured to Under the control of the second enable signal, the level of the second node is controlled.
  • the first enable signal and the second enable signal are the same enable signal.
  • the first reset circuit includes a first transistor, and the gate of the first transistor is coupled to the first enable signal terminal to receive the For the first enable signal, a first electrode of the first transistor is coupled to a first voltage terminal to receive a first voltage, and a second electrode of the first transistor is coupled to the output end.
  • the second reset circuit includes a second transistor, and the gate of the second transistor is coupled to the second enable signal terminal to receive the For the second enable signal, the first electrode of the second transistor is coupled to the second node, and the second electrode of the second transistor is coupled to the second voltage terminal to receive the second voltage.
  • the input control circuit includes an input circuit, and the input circuit is connected to the first clock signal terminal, the input terminal, the third node, and the fourth node.
  • the node is coupled and configured to control the levels of the third node and the fourth node in response to an input signal at the input terminal and a first clock signal at the first clock signal terminal.
  • the input control circuit includes a third control circuit, and the third control circuit is connected to the second clock signal terminal, the first node and the first node.
  • the three-node coupling is configured to provide a second clock signal at the second clock signal terminal to the first node under the control of the level of the third node.
  • the input control circuit includes a third reset circuit
  • the third reset circuit is connected to the third clock signal terminal, the first node, the third reset circuit, and the The three nodes are coupled and configured to control the levels of the third node and the first node in response to a third clock signal at the third clock signal terminal.
  • the first control circuit includes a third transistor, a gate of the third transistor is coupled to the first node, and the third transistor The first electrode of the transistor is coupled to the third voltage terminal to receive a third voltage, and the second electrode of the third transistor is coupled to the second node.
  • the second control circuit includes a sixth transistor, a seventh transistor, and a first capacitor.
  • the gate of the sixth transistor is coupled to the fourth clock signal terminal to receive the fourth clock signal, the first pole of the sixth transistor is coupled to the second node, the sixth transistor
  • the second pole of the transistor is coupled to the fifth voltage terminal to receive a fifth voltage;
  • the gate of the seventh transistor is coupled to the output terminal, and the first pole and the sixth voltage terminal of the seventh transistor are coupled to A sixth voltage is received, and the second pole of the seventh transistor is coupled to the second node.
  • the first pole of the first capacitor is coupled to the output terminal, and the second pole of the first capacitor is coupled to the second node.
  • the output circuit includes a fourth transistor, a fifth transistor, an eighth transistor, and a ninth transistor.
  • a gate of the fourth transistor is coupled to the first node, a first electrode of the fourth transistor is coupled to a fourth voltage terminal to receive a fourth voltage, and a second electrode of the fourth transistor is coupled to the fourth voltage terminal.
  • the first pole of the fifth transistor is coupled; the gate of the fifth transistor is coupled to the first node, and the second pole of the fifth transistor is coupled to the output terminal.
  • the gate of the eighth transistor is coupled to the second node, the first pole of the eighth transistor is coupled to the output terminal, and the second pole of the eighth transistor is coupled to the seventh voltage terminal to receive the seventh voltage;
  • the gate of the ninth transistor is coupled to the output terminal, the first pole of the ninth transistor is coupled to the first pole of the fifth transistor, and the The second pole and the eighth voltage terminal are coupled to receive the eighth voltage.
  • the input circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor, and the tenth transistor
  • the gate of the transistor is coupled to the input terminal to receive the input signal
  • the first electrode of the tenth transistor is coupled to the second electrode of the eleventh transistor
  • the second electrode of the tenth transistor is coupled and the ninth voltage terminal is coupled to receive the ninth voltage
  • the gate of the eleventh transistor is coupled to the first clock signal terminal to receive the first clock signal
  • the first clock signal of the eleventh transistor is
  • the gate of the twelfth transistor is coupled to the input terminal to receive the input signal
  • the first pole of the twelfth transistor is coupled to the tenth voltage terminal
  • the second pole of the twelfth transistor is coupled to the fourth node
  • the gate of the thirteenth transistor is coupled to the first pole of the fourteenth transistor, and the The first electrode of the
  • the third control circuit includes a fifteenth transistor, a second capacitor, and a third capacitor.
  • the gate of the fifteenth transistor is coupled to the third node, the first electrode of the fifteenth transistor is coupled to the first node, and the second electrode of the fifteenth transistor is coupled to the first node
  • the second clock signal terminal is coupled to receive the second clock signal; the first pole of the second capacitor is coupled to the first node, and the second pole of the second capacitor is coupled to the third node
  • the first pole of the third capacitor is coupled to the third node, and the second pole of the third capacitor is coupled to the thirteenth voltage terminal to receive the thirteenth voltage.
  • the third reset circuit includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, and a fourth capacitor.
  • the gate of the sixteenth transistor is coupled to the third clock signal terminal to receive the third clock signal, and the first electrode of the sixteenth transistor is coupled to the fourteenth voltage terminal to receive the tenth Four voltages, the second pole of the sixteenth transistor is coupled to the gate of the seventeenth transistor; the first pole of the seventeenth transistor is coupled to the fifteenth voltage terminal to receive the fifteenth voltage , the second pole of the seventeenth transistor is coupled to the first pole of the nineteenth transistor; the gate of the eighteenth transistor is coupled to the fourth node, and the The first pole and the sixteenth voltage terminal are coupled to receive the sixteenth voltage, the second pole of the eighteenth transistor is coupled to the first node; the gate of the nineteenth transistor is connected to the seventeenth The voltage terminal is coupled to receive the seventeenth voltage, the second pole of the nineteenth transistor is coupled to the
  • the nineteenth transistor and the fourteenth transistor are the same transistor.
  • At least one embodiment of the present disclosure further provides a shift register unit, including: first to eighteenth transistors, and first to fourth capacitors.
  • the gate of the first transistor is coupled to the first enable signal terminal to receive the first enable signal, the first electrode of the first transistor is coupled to the first voltage terminal to receive the first voltage, the first The second pole of a transistor is coupled to the output terminal; the gate of the second transistor is coupled to the second enable signal terminal to receive the second enable signal, the first pole of the second transistor and the second node coupled, the second pole of the second transistor is coupled to the second voltage terminal to receive the second voltage;
  • the gate of the third transistor is coupled to the first node, the first pole of the third transistor and
  • the third voltage terminal is coupled to receive a third voltage, the second electrode of the third transistor is coupled to the second node;
  • the gate of the fourth transistor is coupled to the first node, the first node
  • the first electrode and the fourth voltage terminal of the four transistors are coupled to receive the fourth voltage, the second electrode of the fourth transistor is coupled
  • At least one embodiment of the present disclosure further provides a gate driving circuit, including a plurality of cascaded shift register units described in any of the above embodiments.
  • the input terminal of the Nth stage shift register unit is coupled to the first node of the N ⁇ 1th stage shift register unit; N is greater than 2 Integer.
  • At least one embodiment of the present disclosure further provides a display device, including the shift register unit described in any of the foregoing embodiments or the gate driving circuit described in any of the foregoing embodiments.
  • At least one embodiment of the present disclosure further provides a method for driving a shift register unit according to any of the above embodiments, comprising: in a driving stage, in the input signal, the first clock signal, the second Under the control of the clock signal, the third clock signal, the fourth clock signal and the enable signal, the level of the output terminal is controlled to output the driving signal in the driving stage; in the detection stage, the The input control circuit controls the level of the first node to be a non-working level under the control of the input signal, the first clock signal, the second clock signal and the third clock signal; the The first control circuit controls the level of the second node under the control of the level of the first node; the second control circuit controls the level of the second node under the control of the fourth clock signal and the output signal the level of the second node; the output circuit controls the level of the output terminal under the control of the level of the first node and the level of the second node; the first reset circuit is Under the control of the first enable signal, the level of the output terminal is controlled to stably output the
  • FIG. 1 is a schematic diagram of an external compensation current detection system provided by at least one embodiment of the present disclosure
  • FIG. 2 is a schematic block diagram of a shift register unit provided by at least one embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of another shift register unit provided by at least one embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of an input control circuit provided by at least one embodiment of the present disclosure.
  • 5A is a circuit structure diagram of a shift register unit provided by at least one embodiment of the present disclosure.
  • 5B is a circuit structure diagram of another shift register unit provided by at least one embodiment of the present disclosure.
  • FIG. 6 is a circuit structure diagram of another shift register unit provided by at least one embodiment of the present disclosure.
  • FIG. 7 is a signal timing diagram of a shift register unit provided by at least one embodiment of the present disclosure.
  • FIG. 8 is a schematic block diagram of a gate driving circuit provided by at least one embodiment of the present disclosure.
  • FIG. 9 is a schematic block diagram of a display device according to at least one embodiment of the present disclosure.
  • FIG. 10 is a flowchart of a method for driving a shift register unit provided by at least one embodiment of the present disclosure.
  • an organic light emitting diode (Organic Light Emitting Diode, OLED) display device generally includes a plurality of pixel units arranged in an array, and each pixel unit may include, for example, a pixel circuit.
  • OLED Organic Light Emitting Diode
  • the threshold voltage of the driving transistor in each pixel circuit may be different, and the threshold voltage of the driving transistor may drift due to the influence of temperature change, for example.
  • an OLED display device usually adopts a pixel circuit with a compensation function, for example, adding transistors and/or capacitances on the basis of a basic pixel circuit (eg, 2T1C, ie, two transistors and a capacitor), so as to provide a compensation function.
  • a basic pixel circuit eg, 2T1C, ie, two transistors and a capacitor
  • the compensation function can be realized by voltage compensation, current compensation or hybrid compensation
  • the pixel circuit with compensation function is, for example, a common 4T1C or 4T2C circuit.
  • the current sensing stage and the driving stage are separated.
  • the EM signal in FIG. 1 needs to keep a low level all the time, so that the transistor T4 is turned off, so that the OLED does not emit light, and in the driving stage, the EM signal needs to work normally. Therefore, the EM signal needs to satisfy two functions of maintaining a non-operating level (eg, a low level) for a long time and working normally.
  • the signal provided by the conventional GOA circuit cannot achieve the function of maintaining a non-operating level (eg, a low level) for a long time.
  • a shift register unit including an input control circuit, a first control circuit, a second control circuit, an output circuit, and a first reset circuit.
  • the input control circuit is coupled to the first node, the input terminal, the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal, and is configured as the input signal at the input terminal, the first clock signal at the first clock signal terminal, and the third clock signal terminal.
  • the level of the first node is controlled under the control of the second clock signal at the second clock signal terminal and the third clock signal at the third clock signal terminal.
  • the first control circuit is coupled to the first node and the second node, and is configured to control the level of the second node under the control of the level of the first node.
  • the second control circuit is coupled to the fourth clock signal terminal, the second node and the output terminal, and is configured to control the level of the second node under the control of the fourth clock signal at the fourth clock signal terminal and the output signal at the output terminal.
  • the output circuit is coupled to the first node, the second node and the output terminal, and is configured to control the level of the output terminal under the control of the level of the first node and the level of the second node.
  • the first reset circuit is coupled to the output terminal and the first enable signal terminal, the first enable signal terminal is provided with the first enable signal by the first enable signal line, and the first reset circuit is configured to be in the first enable signal. Under the control, the level of the output terminal is controlled to stably output the non-working level in the detection stage.
  • At least one embodiment of the present disclosure further provides a driving method, a gate driving circuit, and a display device according to the above-mentioned shift register unit.
  • the shift register unit provided by the embodiments of the present disclosure can ensure that under low frequency driving (eg, 1-120 Hz), the output noise interference can be removed in time, so as to ensure that the GOA can stably output a non-operating level (eg, low level) in the detection stage .
  • the shift register unit can not only achieve a long-term low-level stable output in the detection stage to meet the requirements of the external compensation detection stage, but also provide a normally working driving signal in the driving stage to meet the requirements of the display panel driving stage.
  • the term "pull-up” means charging a node or an electrode of a transistor, so that the node or the electrode is charged The absolute value of the level is raised to achieve the operation of the corresponding transistor (eg, turn-on); “pulling down” means to discharge a node or an electrode of a transistor, so that the absolute value of the level of the node or electrode reduced, thereby enabling operation (eg, cut-off) of the corresponding transistor;
  • active level means that the node is at a high level, so that when the gate of a transistor is coupled to the node, the transistor is on;
  • the term “non-operating level” Level” means that the node is at a low level, so that when the gate of a transistor is coupled to the node, the transistor is off.
  • the term "pull-up” means to discharge a node or an electrode of a transistor, so that the absolute value of the level of the node or the electrode decreases, thereby realizing the corresponding transistor
  • "Pull-down” means to charge a node or an electrode of a transistor, so that the absolute value of the level of the node or the electrode rises, so as to realize the operation of the corresponding transistor (such as cut-off)
  • the term "operating level” means that the node is at a low level, so that when the gate of a transistor is coupled to the node, the transistor conducts
  • the term “non-operating potential” means that the node is at a high level, so that when When the gate of a transistor is coupled to the node, the transistor is turned off.
  • FIG. 2 is a schematic diagram of a shift register unit 10 according to at least one embodiment of the present disclosure.
  • the shift register unit 10 includes: an input control circuit 100 , a first control circuit 200 , a second control circuit 300 , a first reset circuit 400 and an output circuit 500 .
  • the input control circuit 100 is coupled to the first node N1, the input terminal INN, the first clock signal terminal CLK1, the second clock signal terminal CLK2, and the third clock signal terminal CLK3, It is configured to be controlled by the input signal of the input terminal INN, the first clock signal of the first clock signal terminal CLK1, the second clock signal of the second clock signal terminal CLK2, and the third clock signal of the third clock signal terminal CLK3.
  • the first control circuit 200 is coupled to the first node N1 and the second node N2, and is configured to control the level of the second node N2 under the control of the level of the first node N1.
  • the second control circuit 300 is coupled to the fourth clock signal terminal CLK4, the second node N2 and the output terminal OT, and is configured to be under the control of the fourth clock signal of the fourth clock signal terminal CLK4 and the output signal of the output terminal OT , to control the level of the second node N2.
  • the output circuit 500 is coupled to the first node N1, the second node N2 and the output terminal OT, and is configured to control the level of the output terminal OT under the control of the level of the first node N1 and the level of the second node N2 .
  • the first reset circuit 400 is coupled to the output terminal OT and the first enable signal terminal EN1, the first enable signal terminal EN1 is provided with the first enable signal by the first enable signal line, and the first reset circuit 400 is configured as Under the control of the first enable signal EN1, the level of the output terminal OT is controlled to stably output the non-working level in the detection stage.
  • the shift register unit 10 by setting the first reset circuit 400, it can be ensured that the output noise interference can be removed in time under low-frequency driving, thereby ensuring that the shift register unit 10 can stably output a non-operating level (eg, a non-operating level) in the detection stage. , low level).
  • a non-operating level eg, a non-operating level
  • the output terminal OT of the shift register unit 10 can stably output a non-operating level for a long time in the detection phase, so as to meet the needs of external Compensating for the detection stage requirements, when the first enable signal EN1 is at an inactive level, the output terminal OT of the shift register unit 10 can output a normal driving driving signal in the driving stage to meet the display panel driving stage requirements.
  • CLK1 may represent either the first clock signal terminal or the first clock signal provided by the first clock signal terminal; similarly, CLK2 is both It can represent the second clock signal terminal or the second clock signal provided by the second clock signal terminal; CLK3 can represent either the third clock signal terminal or the third clock signal provided by the third clock signal terminal; CLK4 can either represent It can represent the fourth clock signal terminal or the fourth clock signal provided by the fourth clock signal terminal; EN1 can represent either the first enable signal terminal or the first enable signal provided by the first enable signal terminal , INN can represent both the input terminal and the input signal provided by the input terminal, and OT can represent both the output terminal and the output signal provided by the output terminal.
  • the first node N1, the second node N2, the third node N3, the fourth node N4, and the fifth node N5 appearing later do not mean that they actually exist components, but rather represent the junctions of related electrical couplings in a circuit diagram.
  • FIG. 3 is a schematic diagram of another shift register unit provided by at least one embodiment of the present disclosure.
  • the shift register unit 11 may further include a second reset circuit 600.
  • the second reset circuit 600 is coupled to the second node N2 and the second enable signal terminal EN2, and the second enable signal terminal EN2 is provided with a second enable signal by the second enable signal line, It is configured to control the level of the second node N2 under the control of the second enable signal EN2.
  • the shift register unit 11 can simultaneously control the first enable signal EN1 and the second enable signal EN2 by setting the first reset circuit 400 and the second reset circuit 600. Control the level of the output terminal OT and the level of the second node N2, so as to better ensure that the output noise interference can be removed in time under low frequency driving, and ensure that the shift register unit 11 stably outputs a non-operating level (for example, a low level) in the detection stage. level).
  • a non-operating level for example, a low level
  • the first enable signal of the first enable signal terminal EN1 and the second enable signal of the second enable signal terminal EN2 may be the same enable signal EN. Accordingly, the first enable signal The terminal EN1 and the second enable signal terminal EN2 may be the same signal terminal.
  • the first enable signal of the first enable signal terminal EN1 and the second enable signal of the second enable signal terminal EN2 may also be different enable signals independent of each other.
  • the first enable signal terminal EN1 and the second enable signal terminal EN2 may be different signal terminals, which are not specifically limited in the embodiment of the present disclosure.
  • EN2 may represent either the second enable signal terminal or the second enable signal provided by the second enable signal terminal; It can represent the enable signal terminal or the enable signal provided by the enable signal terminal.
  • FIG. 4 is a schematic diagram of an input control circuit according to at least one embodiment of the present disclosure.
  • the input control circuit 100 may include an input circuit 101 , a third control circuit 102 and a third reset circuit 103 .
  • the input circuit 101 is coupled to the first clock signal terminal CLK1, the input terminal INN, the third node N3 and the fourth node N4, and is configured to respond to the input signal of the input terminal INN and the first clock signal terminal
  • the first clock signal of CLK1 controls the levels of the third node N3 and the fourth node N4.
  • the third control circuit 102 is coupled to the second clock signal terminal CLK2, the first node N1 and the third node N3, and is configured to, under the control of the level of the third node N3, connect the second clock The second clock signal of the signal terminal CLK2 is supplied to the first node N1.
  • the third reset circuit 103 is coupled to the third clock signal terminal CLK3, the first node N1 and the third node N3, and is configured to control the third clock signal at the third clock signal terminal CLK3 in response to the third clock signal at the third clock signal terminal CLK3.
  • FIG. 5A is a schematic diagram of a circuit structure of a shift register unit 10 provided by at least one embodiment of the present disclosure. It should be noted that, although each transistor is an N-type transistor as an example to describe the embodiments of the present disclosure below, this does not constitute a limitation to the embodiments of the present disclosure.
  • the first reset circuit 400 may include a first transistor T1 .
  • the gate of the first transistor T1 is coupled to the first enable signal terminal EN1 to receive the first enable signal
  • the first electrode of the first transistor T1 is coupled to the first voltage terminal VDD_1 to receive the first voltage
  • the second pole of the first transistor T1 is coupled to the output terminal OT.
  • the first transistor T1 when the first enable signal EN1 is active, the first transistor T1 is turned on, and the first voltage terminal VDD_1 is coupled to the output terminal OT.
  • the first voltage provided by the first voltage terminal VDD_1 is a non-operating level, that is, a low level, noise reduction can be performed on the output terminal OT.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors, field effect transistors, or other switching devices with the same characteristics, and thin film transistors are used as examples in the embodiments of the present disclosure.
  • the source and drain of the transistor used here may be symmetrical in structure, so the source and drain of the transistor may be indistinguishable in structure.
  • one pole is directly described as the first pole, and the other pole is the second pole.
  • the transistors in the embodiments of the present disclosure are all described by taking an N-type transistor as an example.
  • the first electrode of the transistor is the drain electrode
  • the second electrode is the source electrode.
  • the present disclosure includes but is not limited to this.
  • one or more transistors in the shift register unit 10 provided by the embodiments of the present disclosure may also adopt P-type transistors.
  • the first electrode of the transistor is the source electrode
  • the second electrode is the drain electrode.
  • Each pole of a transistor of a certain type is coupled correspondingly with reference to each pole of the corresponding transistor in the embodiment of the present disclosure, and the corresponding high voltage or low voltage may be provided at the corresponding voltage terminal.
  • Indium Gallium Zinc Oxide (IGZO) can be used as the active layer of the thin film transistor. As the active layer of the thin film transistor, it can effectively reduce the size of the transistor and prevent leakage current.
  • IGZO Indium Gallium Zinc Oxide
  • the first control circuit 200 includes a third transistor T3.
  • the gate of the third transistor T3 is coupled to the first node N1
  • the first electrode of the third transistor T3 is coupled to the third voltage terminal VDD_3 to receive the third voltage
  • the second electrode of the third transistor T3 is coupled to the second node VDD_3.
  • Node N2 is coupled.
  • the third transistor T3 when the first node N1 is at an active level (eg, a high level), the third transistor T3 is turned on, and through the third transistor T3, the third voltage provided by the third voltage terminal VDD_3 can be A voltage (eg, a low level) is input to the second node N2 to pull down the level of the second node N2 to a non-operating level (eg, a low level).
  • an active level eg, a high level
  • the third voltage provided by the third voltage terminal VDD_3 can be A voltage (eg, a low level) is input to the second node N2 to pull down the level of the second node N2 to a non-operating level (eg, a low level).
  • the second control circuit 300 may include a sixth transistor T6 , a seventh transistor T7 and a first capacitor C1 .
  • the gate of the sixth transistor T6 is coupled to the fourth clock signal terminal CLK4 to receive the fourth clock signal
  • the first electrode of the sixth transistor T6 is coupled to the second node N2
  • the second electrode of the sixth transistor T6 is coupled to the second node N2.
  • the fifth voltage terminal VDD_5 is coupled to receive the fifth voltage.
  • the gate of the seventh transistor T7 is coupled to the output terminal OT
  • the first electrode of the seventh transistor T7 is coupled to the sixth voltage terminal VDD_6 to receive the sixth voltage
  • the second electrode of the seventh transistor T7 is coupled to the second node N2 coupling.
  • the first pole of the first capacitor C1 is coupled to the output terminal OT, and the second pole of the first capacitor C1 is coupled to the second node N2.
  • the fourth clock signal provided by the fourth clock signal terminal CLK4 is at an active level (eg, a high level), and the sixth transistor T6 is turned on, then through the sixth transistor T6, the fifth voltage can be
  • the fifth voltage (eg, high level) provided by the terminal VDD_5 is input to the second node N2 to pull up the level of the second node N2 to the working level (eg, high level).
  • the seventh transistor T7 is turned on, then through the seventh transistor T7, the sixth voltage (for example, the sixth voltage terminal VDD_6 provided by the sixth voltage terminal VDD_6 can be converted to , high level) is input to the second node N2, so that the second node N2 maintains a high level, and the output terminal OT maintains a high level due to the bootstrapping effect of the first capacitor C1.
  • the storage capacitors for example, the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 in FIG. 5A, FIG. 5B, and FIG.
  • each electrode of the storage capacitor can be realized by metal layers, semiconductor layers (eg, doped polysilicon) and the like.
  • the storage capacitance can also be a parasitic capacitance between transistors, which can be implemented by the transistor itself and other devices and lines.
  • the output circuit 500 may include a fourth transistor T4 , a fifth transistor T5 , an eighth transistor T8 and a ninth transistor T9 .
  • the gate of the fourth transistor T4 is coupled to the first node N1
  • the first electrode of the fourth transistor T4 is coupled to the fourth voltage terminal VDD_4 to receive the fourth voltage
  • the second electrode of the fourth transistor T4 is coupled to the fifth
  • the first pole of the transistor T5 is coupled.
  • the gate of the fifth transistor T5 is coupled to the first node N1, and the second electrode of the fifth transistor T5 is coupled to the output terminal OT.
  • the gate of the eighth transistor T8 is coupled to the second node N2, the first pole of the eighth transistor T8 is coupled to the output terminal OT, and the second pole of the eighth transistor T8 is coupled to the seventh voltage terminal VDD_7 for receiving seventh voltage.
  • the gate of the ninth transistor T9 is coupled to the output terminal OT
  • the first pole of the ninth transistor T9 is coupled to the first pole of the fifth transistor T5
  • the second pole of the ninth transistor T9 is coupled to the eighth voltage terminal Connect to VDD_8 to receive the eighth voltage.
  • the fourth transistor T4 and the fifth transistor T5 are both turned on, and through the fourth transistor T4 and the fifth transistor T5, the The fourth voltage (eg, low level) provided by the fourth voltage terminal VDD_4 is input to the output terminal OT to pull down the level of the output terminal OT to a non-operating level (eg, low level).
  • an active level e.g, a high level
  • the fourth transistor T4 and the fifth transistor T5 are both turned on, and through the fourth transistor T4 and the fifth transistor T5, the The fourth voltage (eg, low level) provided by the fourth voltage terminal VDD_4 is input to the output terminal OT to pull down the level of the output terminal OT to a non-operating level (eg, low level).
  • the eighth transistor T8 when the level of the second node N2 is at a working level (eg, a high level), and the eighth transistor T8 is turned on, then the seventh voltage (eg, the seventh voltage terminal VDD_7 provided by the seventh voltage terminal VDD_7 can be changed to the eighth transistor T8 through the eighth transistor T8 ). , high level) is input to the output terminal OT, and the level of the output terminal OT is pulled up to the working level (eg, high level).
  • a working level eg, a high level
  • the ninth transistor T9 is turned on, and through the ninth transistor T9, the eighth voltage provided by the eighth voltage terminal VDD_8 (eg, high level) is input to the second pole of the fourth transistor T4 to prevent the fourth transistor T4 from leaking at this time.
  • a working level e.g. a high level
  • the input circuit 101 includes a tenth transistor T10 , an eleventh transistor T11 , a twelfth transistor T12 , a thirteenth transistor T13 and a fourteenth transistor T14 .
  • the gate of the tenth transistor T10 is coupled to the input terminal INN to receive the input signal
  • the first electrode of the tenth transistor T10 is coupled to the second electrode of the eleventh transistor T11
  • the second electrode of the tenth transistor T10 and the The ninth voltage terminal VDD_9 is coupled to receive the ninth voltage.
  • the gate of the eleventh transistor T11 is coupled to the first clock signal terminal CLK1 to receive the first clock signal, and the first pole of the eleventh transistor T11 is coupled to the third node N3.
  • the gate of the twelfth transistor T12 is coupled to the input terminal INN to receive the input signal
  • the first electrode of the twelfth transistor T12 is coupled to the tenth voltage terminal VDD_10 to receive the tenth voltage
  • the twelfth transistor T12 has a The second pole is coupled to the fourth node N4.
  • the gate of the thirteenth transistor T13 is coupled to the first electrode of the fourteenth transistor T14, the first electrode of the thirteenth transistor T13 is coupled to the eleventh voltage terminal VDD_11 to receive the eleventh voltage, the tenth The second pole of the three transistors T13 is coupled to the fourth node N4.
  • the gate of the fourteenth transistor T14 is coupled to the twelfth voltage terminal VDD_12 to receive the twelfth voltage, and the second pole of the fourteenth transistor T14 is coupled to the third node N3.
  • the ninth voltage provided by the ninth voltage terminal VDD_9 (for example, high level) is input to the third node N3 to pull up the level of the third node N3 to a working level (eg, a high level).
  • the fourteenth transistor T14 is turned on, and the third node can be coupled to the thirteenth transistor T13
  • the gate that is, the fifth node N5
  • the thirteenth transistor T13 is turned on.
  • the tenth voltage (eg, low level) provided by the tenth voltage terminal VDD_10 and the eleventh voltage (eg, low level) provided by the eleventh voltage terminal VDD_11 may be respectively connected.
  • low level is input to the fourth node N4 to pull down the level of the fourth node N4 to a non-operating level (eg, low level).
  • the third control circuit 102 includes a fifteenth transistor T15 , a second capacitor C2 and a third capacitor C3 .
  • the gate of the fifteenth transistor T15 is coupled to the third node N3, the first electrode of the fifteenth transistor T15 is coupled to the first node N1, and the second electrode of the fifteenth transistor T15 is coupled to the second clock signal terminal CLK2 is coupled to receive the second clock signal.
  • the first pole of the second capacitor C2 is coupled to the first node N1
  • the second pole of the second capacitor C2 is coupled to the third node N3.
  • the first pole of the third capacitor C3 is coupled to the third node N3, and the second pole of the third capacitor C3 is coupled to the thirteenth voltage terminal VDD_13 to receive the thirteenth voltage.
  • the third node N3 when the third node N3 is at an active level (for example, a high level), the fifteenth transistor T15 is turned on, and the second clock signal terminal CLK2 may be provided by the fifteenth transistor T15 through the fifteenth transistor T15.
  • the second clock signal is input to the first node N1.
  • the first node N1 when the second clock signal is at an active level (eg, a high level), the first node N1 is pulled up to a working level (eg, a high level).
  • the second clock signal when the second clock signal is at an inactive level (eg, a low level), the first node N1 may be pulled down to a non-operating level (eg, a low level).
  • the third reset circuit 103 includes a sixteenth transistor T16 , a seventeenth transistor T17 , an eighteenth transistor T18 , a nineteenth transistor T19 and a fourth capacitor C4.
  • the gate of the sixteenth transistor T16 is coupled to the third clock signal terminal CLK3 to receive the third clock signal
  • the first pole of the sixteenth transistor T16 is coupled to the fourteenth voltage terminal VDD_14 to receive the fourteenth voltage
  • the second pole of the sixteenth transistor T16 and the gate of the seventeenth transistor T17 are coupled.
  • the first pole of the seventeenth transistor T17 is coupled to the fifteenth voltage terminal VDD_15 to receive the fifteenth voltage
  • the second pole of the seventeenth transistor T17 is coupled to the first pole of the nineteenth transistor T19.
  • the gate of the eighteenth transistor T18 is coupled to the fourth node N4, the first electrode of the eighteenth transistor T18 is coupled to the sixteenth voltage terminal VDD_16 to receive the sixteenth voltage, and the The diode is coupled to the first node N1.
  • the gate of the nineteenth transistor T19 is coupled to the seventeenth voltage terminal VDD_17 to receive the seventeenth voltage, and the second pole of the nineteenth transistor T19 is coupled to the third node N3.
  • the first electrode of the fourth capacitor C4 is coupled to the gate of the seventeenth transistor T17, and the second electrode of the fourth capacitor C4 is coupled to the first electrode of the seventeenth transistor T17.
  • the sixteenth transistor T16 when the third clock signal provided by the third clock signal terminal CLK3 is at an active level (eg, a high level), the sixteenth transistor T16 is turned on, and the sixteenth transistor T16 can The fourteenth voltage (eg, high level) provided by the fourteenth voltage terminal VDD_14 is input to the fourth node N4, and the fourth node N4 is pulled up to the working level (eg, high level).
  • an active level eg, a high level
  • the seventeenth transistor T17 and the eighteenth transistor T18 are turned on, and then through the seventeenth transistor T17, the voltage provided by the fifteenth voltage terminal VDD_15 can be
  • the fifteenth voltage (eg, a low level) is input to the gate of the thirteenth transistor T13 , that is, the fifth node N5 to pull down the level of the fifth node N5 to a non-operating level (eg, a low level) .
  • the nineteenth transistor T19 is turned on, the third node N3 and the fifth node N5 are coupled, and the third node N3 can be pulled down to a non- Operating level (eg, low level). It is also possible to input the sixteenth voltage (eg, low level) provided by the sixteenth voltage terminal VDD_16 to the first node N1 through the turned-on eighteenth transistor T18 to pull down the first node N1 to an inactive level, i.e. low level.
  • a non- Operating level eg, low level
  • the nineteenth transistor T19 and the fourteenth transistor T14 may be the same transistor, and the seventeenth voltage terminal VDD_17 and the twelfth voltage terminal VDD_12 may be the same voltage terminal, for example, to provide effective power flat, that is, high level.
  • FIG. 5B is a schematic diagram of a circuit structure of a shift register unit 11 according to at least one embodiment of the present disclosure. It should be noted that, compared with the shift register unit 10 in FIG. 5A , the shift register unit 11 in FIG. 5B further includes the circuit structure of the second reset circuit 600 . In addition, the shift register in FIG. 5B The circuit structure of the unit 11 is basically the same as that of the shift register unit 10 in FIG. 5A .
  • the second reset circuit 600 may include a second transistor T2.
  • the gate of the second transistor T2 is coupled to the second enable signal terminal EN2 to receive the second enable signal
  • the first electrode of the second transistor T2 is coupled to the second node N2
  • the second terminal of the second transistor T2 is coupled to the second node N2.
  • the pole is coupled to the second voltage terminal VDD_2 to receive the second voltage.
  • the second transistor T2 when the second enable signal EN2 is active, the second transistor T2 is turned on, and the second voltage terminal VDD_2 is coupled to the second node N2.
  • the second voltage provided by the second voltage terminal VDD_2 is a non-operating level, that is, a low level, noise reduction can be performed on the second node N2.
  • the first enable signal EN1 and the second enable signal EN2 may be the same enable signal EN.
  • the level of the output terminal OT and the second node N2 can be controlled at the same time, so as to remove the output noise in time and ensure that the shift register The unit 10 stably outputs an inactive level (eg, a low level) during the detection phase.
  • FIG. 6 is a circuit structure diagram of another shift register unit 12 provided by at least one embodiment of the present disclosure.
  • the shift register unit 12 includes: first to eighteenth transistors T1 to T18 , and first to fourth capacitors C1 to C4 .
  • all transistors are N-type transistors as an example, and the fourteenth transistor T14 and the nineteenth transistor T19 are the same transistor, and the first enable The signal terminal EN1 and the second enable signal terminal EN2 are the same enable signal terminal EN.
  • the circuit structure of the shift register unit 12 in FIG. 6 is basically the same as that of the shift register unit 11 in FIG. 5B . Consistent.
  • the first voltage terminal VDD_1 , the second voltage terminal VDD_2 , the third voltage terminal VDD_3 , the fourth voltage terminal VDD_4 , the tenth voltage terminal VDD_10 , and the eleventh voltage terminal VDD_11 , the thirteenth voltage terminal VDD_13 , the fifteenth voltage terminal VDD_15 and the sixteenth voltage terminal VDD_16 all provide a voltage at a non-operating level, for example, a low-level voltage VGL.
  • these voltage terminals may all be coupled to the voltage terminal VGL, eg, the voltage terminal VGL may be configured to maintain an input DC low level signal, such as ground.
  • the fifth voltage terminal VDD_5, the sixth voltage terminal VDD_6, the seventh voltage terminal VDD_7, the eighth voltage terminal VDD_8, the ninth voltage terminal VDD_9, the twelfth voltage terminal VDD_12 and the fourteenth voltage terminal VDD_14 all provide the voltage, for example, the high-level voltage VGH.
  • the voltage terminals may all be coupled to the voltage terminal VGH, for example, the voltage terminal VGH may be configured to maintain an input DC high level signal.
  • each voltage terminal may be a separately provided voltage terminal, which is not limited in the embodiment of the present disclosure.
  • the gate of the first transistor T1 is coupled to the first enable signal terminal EN1 to receive the first enable signal (that is, coupled to the enable signal terminal EN to receive the first enable signal) receiving an enable signal), the first electrode of the first transistor T1 is coupled to the first voltage terminal to receive a first voltage (eg, a low-level voltage VGL), and the second electrode of the first transistor T1 is coupled to the output end OT .
  • the first enable signal terminal EN1 to receive the first enable signal (that is, coupled to the enable signal terminal EN to receive the first enable signal) receiving an enable signal)
  • the first electrode of the first transistor T1 is coupled to the first voltage terminal to receive a first voltage (eg, a low-level voltage VGL)
  • the second electrode of the first transistor T1 is coupled to the output end OT .
  • the gate of the second transistor T2 is coupled to the second enable signal terminal EN2 to receive the second enable signal (ie, coupled to the enable signal terminal EN to receive the enable signal), and the first The pole is coupled to the second node N2, and the second pole of the second transistor T2 is coupled to the second voltage terminal to receive a second voltage (eg, a low-level voltage VGL).
  • the gate of the third transistor T3 is coupled to the first node N1, the first electrode of the third transistor T3 is coupled to the third voltage terminal to receive a third voltage (eg, a low-level voltage VGL), and the third transistor T3 has a The second pole is coupled to the second node N2.
  • the gate of the fourth transistor T4 is coupled to the first node N1, the first electrode of the fourth transistor T4 is coupled to the fourth voltage terminal to receive a fourth voltage (eg, a low-level voltage VGL), and the fourth transistor T4 has a
  • the second electrode is coupled to the first electrode of the fifth transistor T5.
  • the gate of the fifth transistor T5 is coupled to the first node N1, and the second pole of the fifth transistor T5 is coupled to the output terminal OT.
  • the gate of the sixth transistor T6 is coupled to the fourth clock signal terminal CLK4 to receive the fourth clock signal, the first pole of the sixth transistor T6 is coupled to the second node N2, the second pole of the sixth transistor T6 is coupled to the fifth
  • the voltage terminal is coupled to receive a fifth voltage (eg, the high-level voltage VGH).
  • the gate of the seventh transistor T7 is coupled to the output terminal OT, the first pole of the seventh transistor T7 is coupled to the sixth voltage terminal to receive the sixth voltage (eg, the high-level voltage VGH), and the sixth voltage of the seventh transistor T7
  • the diode is coupled to the second node N2.
  • the gate of the eighth transistor T8 is coupled to the second node N2, the first pole of the eighth transistor T8 is coupled to the output terminal OT, and the second pole of the eighth transistor T8 is coupled to the seventh voltage terminal to receive the seventh voltage (eg, high-level voltage VGH).
  • the gate of the ninth transistor T9 is coupled to the output terminal OT, the first pole of the ninth transistor T9 is coupled to the first pole of the fifth transistor T5, the second pole of the ninth transistor T9 is coupled to the eighth voltage terminal An eighth voltage (eg, a high-level voltage VGH) is received.
  • the first pole of the first capacitor C1 is coupled to the output terminal OT, and the second pole of the first capacitor C1 is coupled to the second node N2.
  • the gate of the tenth transistor T10 is coupled to the input terminal INN to receive the input signal, the first electrode of the tenth transistor T10 is coupled to the second electrode of the eleventh transistor T11, and the second electrode of the tenth transistor T10 is coupled to the ninth electrode of the tenth transistor T10.
  • the voltage terminal is coupled to receive a ninth voltage (eg, a high-level voltage VGH).
  • the gate of the eleventh transistor T11 is coupled to the first clock signal terminal CLK1 to receive the first clock signal, and the first pole of the eleventh transistor T11 is coupled to the third node N3.
  • the gate of the twelfth transistor T12 is coupled to the input terminal INN to receive the input signal, the first electrode of the twelfth transistor T12 is coupled to the tenth voltage terminal to receive the tenth voltage (eg, the low-level voltage VGL), The second pole of the twelfth transistor T12 is coupled to the fourth node N4.
  • the gate of the thirteenth transistor T13 is coupled to the first electrode of the fourteenth transistor T14, and the first electrode of the thirteenth transistor T13 is coupled to the eleventh voltage terminal to receive the eleventh voltage (eg, a low level). voltage VGL), the second pole of the thirteenth transistor T13 is coupled to the fourth node N4.
  • the gate of the fourteenth transistor T14 is coupled to the twelfth voltage terminal to receive the twelfth voltage (eg, the high-level voltage VGH), and the second electrode of the fourteenth transistor T14 is coupled to the third node N3.
  • the gate of the fifteenth transistor T15 is coupled to the third node N3, the first electrode of the fifteenth transistor T15 is coupled to the first node N1, and the second electrode of the fifteenth transistor T15 is coupled to the second clock signal terminal CLK2 connected to receive the second clock signal.
  • the first pole of the second capacitor C2 is coupled to the first node N1, and the second pole of the second capacitor C2 is coupled to the third node N3.
  • the first pole of the third capacitor C3 is coupled to the third node N3, and the second pole of the third capacitor C3 is coupled to the thirteenth voltage terminal to receive the thirteenth voltage (eg, the low-level voltage VGL).
  • the gate of the sixteenth transistor T16 is coupled to the third clock signal terminal CLK3 to receive the third clock signal, and the first pole of the sixteenth transistor T16 is coupled to the fourteenth voltage terminal (eg, the high-level voltage VGH)
  • the second pole of the sixteenth transistor T16 and the gate of the seventeenth transistor T17 are coupled to receive the fourteenth voltage.
  • the first pole and the fifteenth voltage terminal of the seventeenth transistor T17 are coupled to receive the fifteenth voltage (eg, the low-level voltage VGL), the second pole of the seventeenth transistor T17 and the gate of the thirteenth transistor T13 extremely coupled.
  • the gate of the eighteenth transistor T18 is coupled to the fourth node N4, the first electrode of the eighteenth transistor T18 is coupled to the sixteenth voltage terminal to receive the sixteenth voltage (eg, the low-level voltage VGL), the The second pole of the eighteen transistor T18 is coupled to the first node N1.
  • the first electrode of the fourth capacitor C4 is coupled to the gate of the seventeenth transistor T17, and the second electrode of the fourth capacitor C4 is coupled to the first electrode of the seventeenth transistor T17.
  • FIG. 7 is a signal timing diagram of a shift register unit according to an embodiment of the present disclosure.
  • the operation principle of the shift register unit 12 shown in FIG. 6 will be described below with reference to the signal timing diagram shown in FIG. 7 .
  • the level of the potential in the signal timing diagram shown in FIG. 7 is only schematic, and does not represent the actual potential value.
  • the operation principles of the shift register units 10 and 11 in FIG. 5A and FIG. 5B are basically the same as the shift register unit 12 in FIG. 6 , and for brevity, the embodiments of the present disclosure will not repeat them.
  • the signal timing diagram includes a first phase P1 , a second phase P2 , a third phase P3 , a fourth phase P4 and a fifth phase P5 .
  • the driving phase includes a first phase P1, a second phase P2, a third phase P3, and a fourth phase P4, and the detection phase (also referred to as a non-operating level holding phase) includes a fifth phase Stage P5.
  • the enable signal EN is at an inactive level (eg, a low level), and the shift register unit is in a normal operating state, that is, a normal driving state stage, and in the fifth stage P5, that is, the detection stage (eg, the low level hold stage), the enable signal EN is at an active level (eg, a high level).
  • the input signal provided by the input terminal INN and the first clock signal provided by the first clock signal terminal CLK1 are at the active level (eg, high level) at the same time, the second clock signal CLK2, the third clock signal The signal CLK3 and the fourth clock signal CLK4 are at an inactive level (eg, a low level), the tenth transistor T10 and the eleventh transistor T11 are turned on, and the ninth voltage (eg, a high level) provided by the ninth voltage terminal VDD_9 is turned on. ) is input to the third node N3 to pull up the level of the third node N3 to a working level (eg, a high level).
  • a working level eg, a high level
  • the fifteenth transistor T15 is turned on, and the second clock signal provided by the second clock signal terminal CLK2 (in the first stage P1, CLK2 is at a low level) can be provided to the first node N1, then the first node N1 at a non-operating level (ie, a low level).
  • the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are all turned off, and the output terminal OT is at an active level, that is, a high level.
  • the second clock signal provided by the second clock signal terminal CLK2 changes from a low level to a high level, and the input signal provided by the input terminal INN and the first clock signal provided by the first clock signal terminal CLK1 are changed from high level.
  • the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are all turned on, and the output terminal OT is pulled down to a low level.
  • the third clock signal CLK3 changes from a low level to a high level, and the input signal INN, the first clock signal CLK1, the second clock signal CLK2 and the fourth clock signal CLK4 are at a low level.
  • the sixteenth transistor T16 is turned on, inputs the fourteenth voltage (eg, high level) provided by the fourteenth voltage terminal VDD_14 to the fourth node N4, and pulls up the fourth node N4 to the working level (eg, high level) level).
  • the eighteenth transistor T18 is turned on, the sixteenth voltage (eg, low level) provided by the sixteenth voltage terminal VDD_16 is input to the first node N1, and the first node N1 is pulled down to a low level.
  • the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are all turned off, and the output terminal OT is maintained at a low level.
  • the fourth clock signal provided by the fourth clock signal terminal CLK4 changes from a low level to a high level, and the input signal, the first clock signal CLK1, the second clock signal CLK2 and the third clock signal provided by the input terminal INN
  • the clock signal CLK3 is at a low level.
  • the first node N1 is kept at a low level, and the sixth transistor T6 is turned on.
  • the fifth voltage (eg, a high level) provided by the fifth voltage terminal VDD_5 can be input to the second node N2 , the level of the second node N2 is pulled up to a working level (eg, a high level).
  • the eighth transistor T8 is turned on, and the seventh voltage (eg, high level) provided by the seventh voltage terminal VDD_7 is input to the output terminal OT through the eighth transistor T8, and the level of the output terminal OT is pulled up. to an operating level (eg, high). Moreover, due to the bootstrap effect of the first capacitor C1, the level of the output terminal OT can be maintained at the high level VGH.
  • the shift register unit 12 can work normally, realize the normal driving function, and meet the requirements in the driving stage of the display panel.
  • the input signal INN, the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3 and the fourth clock signal CLK4 are all at an inactive level, ie a low level, and the enable signal EN is at Active level, that is, high level.
  • the first transistor T1 and the second transistor T2 are turned on, and the first voltage (eg, low level) provided by the first voltage terminal VDD_1 can be input to the output terminal OT through the first transistor T1, and the output terminal OT can be connected to the output terminal OT. Noise reduction is performed to ensure that the output terminal OT outputs a low level stably.
  • the second voltage (eg, a low level) provided by the second voltage terminal VDD_2 can be input to the second node N2 through the second transistor T2 to ensure that the second node N2 is at a non-operating level, and that the eighth transistor T8 is turned off, The leakage of electricity of the eighth transistor T8 is prevented.
  • the first transistor T1 is not set, in the fifth stage P5, the first node N1 keeps a low level, the fourth transistor T4 and the fifth transistor T5 are turned off, and the output terminal OT is in a floating state, which cannot output a low level stably.
  • the sixth transistor T6 may leak, so that the potential of the second node N2 is gradually raised, which in turn causes the leakage of the eighth transistor T8 to increase, and finally causes the output terminal OT potential to gradually increase, which cannot be stabilized. output low level.
  • the shift register unit 12 can stably output a non-operating level (eg, a low level) for a long time.
  • a non-operating level eg, a low level
  • the shift register unit 10/11/12 provided by the embodiments of the present disclosure can ensure that the output noise interference can be removed in time under low frequency driving, so as to ensure that the GOA can stably output a non-operating level (eg, a low level) in the detection stage Therefore, the shift register unit 10/11/12 can not only realize the normal driving function in the driving stage, but also ensure the stable output of the non-working level for a long time in the detection stage.
  • a non-operating level eg, a low level
  • At least one embodiment of the present disclosure further provides a gate driving circuit, where the gate driving circuit includes a plurality of cascaded shift register units provided in any embodiment of the present disclosure.
  • the gate driving circuit can ensure that the output noise interference is removed in time under low frequency driving, thereby ensuring a stable output non-operating level (eg, low level) in the detection stage. Therefore, the normal driving function can be realized in the driving stage, and the stable output of the non-working level for a long time can also be guaranteed in the detection stage.
  • FIG. 8 is a schematic block diagram of a gate driving circuit according to at least one embodiment of the present disclosure.
  • the gate driving circuit 20 includes a plurality of cascaded shift register units (eg, A1 , A2 , A3 , etc.).
  • the number of multiple shift register units is not limited and can be determined according to actual needs.
  • the shift register unit adopts the shift register unit 10/11/12 described in any embodiment of the present disclosure.
  • some or all of the shift register units may adopt the shift register units 10/11/12 described in any embodiment of the present disclosure.
  • the gate driving circuit 20 can be directly integrated on the array substrate of the display device using the same process as that of the thin film transistor to form a GOA, which can realize, for example, a progressive scan driving function.
  • each shift register unit may have a first node N1, an input terminal INN, a first clock signal terminal CLK1, a second clock signal terminal CLK2, and a third clock signal terminal CLK3 , the fourth clock signal terminal CLK4, the signal enable terminal EN and the output terminal OT.
  • the input terminal INN of the Nth stage shift register unit is coupled to the first node N1 of the N ⁇ 1th stage shift register unit;
  • the first node N1 of the bit register unit is coupled to the input terminal INN of the N+1 th shift register unit;
  • N is an integer greater than 2.
  • the input terminal INN of the shift register unit is coupled. Except for the shift register unit of the first stage (eg, the first shift register unit A1 ), the input terminal INN of the shift register unit of the other stages is coupled to the first node N1 of the shift register unit of the previous stage.
  • the input terminal INN of the first-stage shift register unit may be configured to receive the trigger signal STV, which is not specifically limited in the embodiment of the present disclosure.
  • the gate driving circuit 20 may further include a first clock signal line CLK1_L, a second clock signal line CLK2_L, a third clock signal line CLK3_L and a fourth clock signal line CLK4_L.
  • CLK1_L a first clock signal line
  • CLK2_L a second clock signal line
  • CLK3_L a third clock signal line
  • CLK4_L a fourth clock signal line
  • the first clock signal terminal CLK1 of the first-stage shift register unit A1, the fourth clock signal terminal CLK4 of the second-stage shift register unit A2, and the third clock signal terminal CLK3 of the third-stage shift register unit A3 and The first clock signal line CLK1-L is coupled; the second clock signal terminal CLK2 of the first stage shift register unit A1, the first clock signal terminal CLK1 of the second stage shift register unit A2 and the third stage shift register unit
  • the fourth clock signal terminal CLK4 of A3 is coupled to the second clock signal line CLK2-L;
  • the third clock signal terminal CLK3 of the first-stage shift register unit A1 and the second clock signal terminal of the second-stage shift register unit A2 CLK2 and the first clock signal terminal CLK1 of the third-stage shift register unit A3 are coupled to the third clock signal line CLK3-L;
  • the fourth clock signal terminal CLK4 of the first-stage shift register unit A1, the second-stage shift register unit A1 is coupled to the third clock signal line CLK3-L;
  • the embodiments of the present disclosure include but are not limited to the above-mentioned coupling manners.
  • the first clock signal terminal CLK1 , the second clock signal terminal CLK2 , the third clock signal terminal CLK3 and the fourth clock signal terminal CLK4 of each shift register unit in the gate driving circuit 20 can also be connected to A plurality of clock signal lines provided separately are coupled, such as more than 4 clock signal lines, and not all the first clock signal terminals CLK1 are coupled to the same clock signal line, and not all the second clock signal lines.
  • the signal terminals CLK2 are all coupled to the same clock signal line, not all the third clock signal terminals CLK3 are coupled to the same clock signal line, and not all the fourth clock signal terminals CLK4 are coupled to the same clock signal line , which can be determined according to actual requirements, which is not limited by the embodiments of the present disclosure.
  • the clock signal timings provided on the first clock signal line CLK1_L, the second clock signal line CLK2_L, the third clock signal line CLK3_L and the fourth clock signal line CLK4_L may adopt the signal timing shown in FIG. 7 to realize the gate
  • the driving circuit 20 is not used for a long time in the detection phase to stabilize the output of the operating level.
  • the display device to which the gate driving circuit 20 is applied may further include a timing controller T-CON.
  • the timing controller T-CON is configured to be coupled to the first clock signal line CLK1_L, the second clock signal line CLK2_L, the third clock signal line CLK3_L, and the fourth clock signal line CLK4_L, so as to connect to the shift register unit of each stage Each clock signal is provided.
  • the timing controller T-CON may also be configured to provide the trigger signal STV. It should be noted that the phase relationship between the multiple clock signals provided by the timing controller T-CON may be determined according to actual requirements. In different examples, according to different configurations, more clock signals may also be provided.
  • the gate driving circuit 20 when used to drive the display panel, the gate driving circuit 20 may be disposed on one side of the display panel.
  • the gate driving circuit 20 can be directly integrated on the array substrate of the display panel using the same process as the thin film transistor to form a GOA, thereby realizing the driving function.
  • the gate driving circuit 20 may also be arranged on both sides of the display panel to realize bilateral driving, and the embodiment of the present disclosure does not limit the arrangement of the gate driving circuit 20 .
  • the working principle of the gate driving circuit 20 reference may be made to the corresponding description of the working principle of the shift register unit 10/11/12 in the embodiments of the present disclosure, which will not be repeated here.
  • At least one embodiment of the present disclosure also provides a display device.
  • the display device includes the shift register unit described in any embodiment of the present disclosure or the gate driving circuit described in any embodiment of the present disclosure.
  • FIG. 9 is a schematic block diagram of a display device according to at least one embodiment of the present disclosure.
  • the display device 30 includes a gate driving circuit 20
  • the gate driving circuit 20 can be the gate driving circuit 20 provided in any embodiment of the present disclosure.
  • the display device 30 in this embodiment may be a liquid crystal display panel, a liquid crystal television, an OLED display panel, an OLED television, an OLED display, a Quantum Dot Light Emitting Diode (QLED) display panel, etc., or an electronic Any product or component with a display function, such as a book, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, and a navigator, is not limited by the embodiments of the present disclosure.
  • a display device 30 reference may be made to the corresponding descriptions of the shift register units 10 / 11 / 12 and the gate driving circuit 20 in the above embodiments, which will not be repeated here.
  • the display device 30 includes a display panel 3000 , a gate driver 3010 , and a data driver 3030 .
  • the display panel 3000 includes a plurality of pixel units P defined according to the intersection of a plurality of scan lines GL and a plurality of data lines DL; the gate driver 3010 is used for driving the plurality of scan lines GL, and the gate driver 3010 can be any embodiment of the present disclosure
  • the provided gate driving circuit 20; the data driver 3030 is used to drive a plurality of data lines DL.
  • the data driver 3030 is electrically coupled to the pixel unit P through the data line DL, and the gate driver 3010 is electrically coupled to the pixel unit P through the scan line GL.
  • the gate driver 3010 and the data driver 3030 may be implemented as semiconductor chips.
  • the gate driver 3010 (gate driver circuit 20) may also be implemented as a GOA circuit.
  • the display device 30 may also include other components, such as a timing controller, a signal decoding circuit, a voltage conversion circuit, etc., for example, these components may adopt existing conventional components, which will not be described in detail here.
  • FIG. 10 is a flowchart of a method 1000 for driving a shift register unit provided by at least one embodiment of the present disclosure.
  • the driving method 1000 of the shift register unit may include:
  • Step S1001 In the driving stage, under the control of the input signal INN, the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, the fourth clock signal CLK4 and the enable signal EN, control the power of the output terminal OT. level to output the drive signal during the drive stage; and
  • Step S1002 In the detection stage, the input control circuit 100 controls the level of the first node N1 to be a non-operating level under the control of the input signal INN, the first clock signal CLK1, the second clock signal CLK2 and the third clock signal CLK3 , the first control circuit 200 controls the level of the second node N2 under the control of the level of the first node N1, and the second control circuit 300 controls the second node under the control of the fourth clock signal CLK4 and the output signal OT
  • the level of N2; the output circuit 500 controls the level of the output terminal OT under the control of the level of the first node N1 and the level of the second node N2;
  • the first reset circuit 400 is under the control of the first enable signal EN1 , to control the level of the output terminal OT to stably output a non-operating level (eg, a low level) during the detection phase.
  • a non-operating level eg, a low level

Abstract

一种移位寄存器单元及其驱动方法、栅极驱动电路以及显示装置。该移位寄存器单元包括：输入控制电路(100)，配置为在输入信号(INN)、第一时钟信号(CLK1)、第二时钟信号(CLK2)、第三时钟信号(CLK3)的控制下，控制第一节点(N1)的电平；第一控制电路(200)，配置为在第一节点(N1)的电平的控制下，控制第二节点(N2)的电平；第二控制电路(300)，配置为在第四时钟信号(CLK4)和输出信号(OT)的控制下，控制第二节点(N2)的电平；输出电路(500)在第一节点(N1)的电平和第二节点(N2)的电平的控制下，控制输出端(OT)的电平；第一复位电路(400)在第一使能信号(EN1)的控制下，控制输出端(OT)的电平，以在检测阶段稳定输出非工作电平。

Description

移位寄存器单元及其驱动方法、栅极驱动电路和显示装置 技术领域
本公开的实施例涉及一种移位寄存器单元及其驱动方法、栅极驱动电路以及显示装置。
背景技术
在显示技术领域，例如OLED、液晶显示的像素阵列通常包括多行栅线和与之交错的多列数据线。对栅线的驱动可以通过贴附的集成驱动电路实现。近几年随着非晶硅薄膜工艺的不断提高，也可以将栅线驱动电路直接集成在薄膜晶体管阵列基板上构成GOA(Gate driver On Array)来对栅线进行驱动。
例如，可以采用由多个级联的移位寄存器单元构成的GOA为像素阵列的多行栅线提供开关态电压信号，从而控制多行栅线依序打开，并由数据线向像素阵列中对应行的像素单元提供数据信号，以形成显示图像的各灰阶所需要的灰度电压，进而显示每一帧图像。
发明内容
本公开至少一个实施例提供一种移位寄存器单元，包括：输入控制电路、第一控制电路、第二控制电路、输出电路和第一复位电路。所述输入控制电路与第一节点、输入端、第一时钟信号端、第二时钟信号端、第三时钟信号端耦接，配置为在所述输入端的输入信号、所述第一时钟信号端的第一时钟信号、所述第二时钟信号端的第二时钟信号、所述第三时钟信号端的第三时钟信号的控制下，控制所述第一节点的电平；所述第一控制电路与所述第一节点和第二节点耦接，配置为在所述第一节点的电平的控制下，控制所述第二节点的电平。所述第二控制电路与第四时钟信号端、所述第二节点和输出端耦接，配置为在所述第四时钟信号端的第四时钟信号和所述输出端的输出信号的控制下，控制所述第二节点的电平；所述输出电路与所述第一节点、所述第二节点和所述输出端耦接，配置为在所述第一节点的电平和所述第二节点的电平的控制下，控制所述输出端的电平；所述第一复位电路与所述输出端和第一使能信号端耦接，所述第一使能信号端由第一使能信号线提供第一使能信号，所述第一复位电路配置为在所述第一使能信号的控制下，控制所述输出端的电平，以在检测阶段稳定输出非工作电平。
例如，本公开至少一个实施例提供的移位寄存器单元还包括：第二复位电路。所述第二复位电路与所述第二节点和第二使能信号端耦接，所述第二使能信号端由第二使能信号线提供第二使能信号，配置为在所述第二使能信号的控制下，控制所述第二节点的电平。
例如，在本公开至少一个实施例提供的移位寄存器单元中，所述第一使能信号和所述第二使能信号为同一使能信号。
例如，在本公开至少一个实施例提供的移位寄存器单元中，所述第一复位电路包括第 一晶体管，所述第一晶体管的栅极和所述第一使能信号端耦接以接收所述第一使能信号，所述第一晶体管的第一极和第一电压端耦接以接收第一电压，所述第一晶体管的第二极和所述输出端耦接。
例如，在本公开至少一个实施例提供的移位寄存器单元中，所述第二复位电路包括第二晶体管，所述第二晶体管的栅极和所述第二使能信号端耦接以接收所述第二使能信号，所述第二晶体管的第一极和所述第二节点耦接，所述第二晶体管的第二极和第二电压端耦接以接收第二电压。
例如，在本公开至少一个实施例提供的移位寄存器单元中，所述输入控制电路包括输入电路，所述输入电路与所述第一时钟信号端、所述输入端、第三节点和第四节点耦接，配置为响应于所述输入端的输入信号和所述第一时钟信号端的第一时钟信号，控制所述第三节点和所述第四节点的电平。
例如，在本公开至少一个实施例提供的移位寄存器单元中，所述输入控制电路包括第三控制电路，所述第三控制电路与所述第二时钟信号端、所述第一节点和第三节点耦接，配置为在所述第三节点的电平的控制下，将所述第二时钟信号端的第二时钟信号提供至所述第一节点。
例如，在本公开至少一个实施例提供的移位寄存器单元中，所述输入控制电路包括第三复位电路，所述第三复位电路与所述第三时钟信号端、所述第一节点、第三节点耦接，配置为响应于所述第三时钟信号端的第三时钟信号，控制所述第三节点和所述第一节点的电平。
例如，在本公开至少一个实施例提供的移位寄存器单元中，所述第一控制电路包括第三晶体管，所述第三晶体管的栅极和所述第一节点耦接，所述第三晶体管的第一极和第三电压端耦接以接收第三电压，所述第三晶体管的第二极和所述第二节点耦接。
例如，在本公开至少一个实施例提供的移位寄存器单元中，所述第二控制电路包括第六晶体管、第七晶体管和第一电容。所述第六晶体管的栅极和所述第四时钟信号端耦接以接收所述第四时钟信号，所述第六晶体管的第一极和所述第二节点耦接，所述第六晶体管的第二极和第五电压端耦接以接收第五电压；所述第七晶体管的栅极和所述输出端耦接，所述第七晶体管的第一极和第六电压端耦接以接收第六电压，所述第七晶体管的第二极和所述第二节点耦接。所述第一电容的第一极和所述输出端耦接，所述第一电容的第二极和所述第二节点耦接。
例如，在本公开至少一个实施例提供的移位寄存器单元中，所述输出电路包括第四晶体管、第五晶体管、第八晶体管和第九晶体管。所述第四晶体管的栅极和所述第一节点耦接，所述第四晶体管的第一极和第四电压端耦接以接收第四电压，所述第四晶体管的第二极和所述第五晶体管的第一极耦接；所述第五晶体管的栅极和所述第一节点耦接，所述第五晶体管的第二极和所述输出端耦接。所述第八晶体管的栅极和所述第二节点耦接，所述第八晶体管的第一极和所述输出端耦接，所述第八晶体管的第二极和第七电压端耦接以接收第七电压；所述第九晶体管的栅极和所述输出端耦接，所述第九晶体管的第一极和所述 第五晶体管的第一极耦接，所述第九晶体管的第二极和第八电压端耦接以接收第八电压。
例如，在本公开至少一个实施例提供的移位寄存器单元中，所述输入电路包括第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管和第十四晶体管，所述第十晶体管的栅极和所述输入端耦接以接收所述输入信号，所述第十晶体管的第一极和所述第十一晶体管的第二极耦接，所述第十晶体管的第二极和第九电压端耦接以接收第九电压；所述第十一晶体管的栅极和所述第一时钟信号端耦接以接收所述第一时钟信号，所述第十一晶体管的第一极和所述第三节点耦接；所述第十二晶体管的栅极和所述输入端耦接以接收所述输入信号，所述第十二晶体管的第一极和第十电压端耦接以接收第十电压，所述第十二晶体管的第二极和所述第四节点耦接；所述第十三晶体管的栅极和所述第十四晶体管的第一极耦接，所述第十三晶体管的第一极和第十一电压端耦接以接收第十一电压，所述第十三晶体管的第二极和所述第四节点耦接；所述第十四晶体管的栅极和第十二电压端耦接以接收第十二电压，所述第十四晶体管的第二极和所述第三节点耦接。
例如，在本公开至少一个实施例提供的移位寄存器单元中，所述第三控制电路包括第十五晶体管、第二电容和第三电容。所述第十五晶体管的栅极和所述第三节点耦接，所述第十五晶体管的第一极和所述第一节点耦接，所述第十五晶体管的第二极和所述第二时钟信号端耦接以接收所述第二时钟信号；所述第二电容的第一极和所述第一节点耦接，所述第二电容的第二极和所述第三节点耦接；所述第三电容的第一极和所述第三节点耦接，所述第三电容的第二极和第十三电压端耦接以接收第十三电压。
例如，在本公开至少一个实施例提供的移位寄存器单元中，所述第三复位电路包括第十六晶体管、第十七晶体管、第十八晶体管、第十九晶体管和第四电容。所述第十六晶体管的栅极和所述第三时钟信号端耦接以接收所述第三时钟信号，所述第十六晶体管的第一极和第十四电压端耦接以接收第十四电压，所述第十六晶体管的第二极和所述第十七晶体管的栅极耦接；所述第十七晶体管的第一极和第十五电压端耦接以接收第十五电压，所述第十七晶体管的第二极和所述第十九晶体管的第一极耦接；所述第十八晶体管的栅极和所述第四节点耦接，所述第十八晶体管的第一极和第十六电压端耦接以接收第十六电压，所述第十八晶体管的第二极和所述第一节点耦接；所述第十九晶体管的栅极和第十七电压端耦接以接收第十七电压，所述第十九晶体管的第二极和所述第三节点耦接；所述第四电容的第一极和所述第十七晶体管的栅极耦接，所述第四电容的第二极和所述第十七晶体管的第一极耦接。
例如，在本公开至少一个实施例提供的移位寄存器单元中，所述第十九晶体管和所述第十四晶体管为同一晶体管。
本公开至少一个实施例还提供一种移位寄存器单元，包括：第一晶体管至第十八晶体管、第一电容至第四电容。所述第一晶体管的栅极和第一使能信号端耦接以接收第一使能信号，所述第一晶体管的第一极和第一电压端耦接以接收第一电压，所述第一晶体管的第二极和输出端耦接；所述第二晶体管的栅极和第二使能信号端耦接以接收第二使能信号，所述第二晶体管的第一极和第二节点耦接，所述第二晶体管的第二极和第二电压端耦接以 接收第二电压；所述第三晶体管的栅极和第一节点耦接，所述第三晶体管的第一极和第三电压端耦接以接收第三电压，所述第三晶体管的第二极和所述第二节点耦接；所述第四晶体管的栅极和所述第一节点耦接，所述第四晶体管的第一极和第四电压端耦接以接收第四电压，所述第四晶体管的第二极和所述第五晶体管的第一极耦接；所述第五晶体管的栅极和所述第一节点耦接，所述第五晶体管的第二极和所述输出端耦接；所述第六晶体管的栅极和第四时钟信号端耦接以接收第四时钟信号，所述第六晶体管的第一极和所述第二节点耦接，所述第六晶体管的第二极和第五电压端耦接以接收第五电压；所述第七晶体管的栅极和所述输出端耦接，所述第七晶体管的第一极和第六电压端耦接以接收第六电压，所述第七晶体管的第二极和所述第二节点耦接；所述第八晶体管的栅极和所述第二节点耦接，所述第八晶体管的第一极和所述输出端耦接，所述第八晶体管的第二极和第七电压端耦接以接收第七电压；所述第九晶体管的栅极和所述输出端耦接，所述第九晶体管的第一极和所述第五晶体管的第一极耦接，所述第九晶体管的第二极和第八电压端耦接以接收第八电压；所述第一电容的第一极和所述输出端耦接，所述第一电容的第二极和所述第二节点耦接；所述第十晶体管的栅极和输入端耦接以接收输入信号，所述第十晶体管的第一极和所述第十一晶体管的第二极耦接，所述第十晶体管的第二极和第九电压端耦接以接收第九电压；所述第十一晶体管的栅极和第一时钟信号端耦接以接收第一时钟信号，所述第十一晶体管的第一极和第三节点耦接；所述第十二晶体管的栅极和所述输入端耦接以接收所述输入信号，所述第十二晶体管的第一极和第十电压端耦接以接收第十电压，所述第十二晶体管的第二极和第四节点耦接；所述第十三晶体管的栅极和所述第十四晶体管的第一极耦接，所述第十三晶体管的第一极和第十一电压端耦接以接收第十一电压，所述第十三晶体管的第二极和所述第四节点耦接；所述第十四晶体管的栅极和第十二电压端耦接以接收第十二电压，所述第十四晶体管的第二极和所述第三节点耦接；所述第十五晶体管的栅极和所述第三节点耦接，所述第十五晶体管的第一极和所述第一节点耦接，所述第十五晶体管的第二极和第二时钟信号端耦接以接收第二时钟信号；所述第二电容的第一极和所述第一节点耦接，所述第二电容的第二极和所述第三节点耦接；所述第三电容的第一极和所述第三节点耦接，所述第三电容的第二极和第十三电压端耦接以接收第十三电压；所述第十六晶体管的栅极和第三时钟信号端耦接以接收第三时钟信号，所述第十六晶体管的第一极和第十四电压端耦接以接收第十四电压，所述第十六晶体管的第二极和所述第十七晶体管的栅极耦接；所述第十七晶体管的第一极和第十五电压端耦接以接收第十五电压，所述第十七晶体管的第二极和所述第十三晶体管的栅极耦接；所述第十八晶体管的栅极和所述第四节点耦接，所述第十八晶体管的第一极和第十六电压端耦接以接收第十六电压，所述第十八晶体管的第二极和所述第一节点耦接；所述第四电容的第一极和所述第十七晶体管的栅极耦接，所述第四电容的第二极和所述第十七晶体管的第一极耦接。
本公开至少一个实施例还提供一种栅极驱动电路，包括多个级联的上述任一实施例所述的移位寄存器单元。
例如，在本公开至少一个实施例提供的移栅极驱动电路中，第N级移位寄存器单元 的输入端和第N-1级移位寄存器单元的第一节点耦接；N为大于2的整数。
本公开至少一个实施例还提供一种显示装置，包括如上述任一实施例所述的移位寄存器单元或如上述任一实施例所述的栅极驱动电路。
本公开至少一个实施例还提供一种如上述任一实施例所述的移位寄存器单元的驱动方法，包括：在驱动阶段，在所述输入信号、所述第一时钟信号、所述第二时钟信号、所述第三时钟信号、所述第四时钟信号和所述使能信号的控制下，控制所述输出端的电平，以在所述驱动阶段输出驱动信号；在检测阶段，所述输入控制电路在所述输入信号、所述第一时钟信号、所述第二时钟信号和所述第三时钟信号的控制下，控制所述第一节点的电平为非工作电平；所述第一控制电路在所述第一节点的电平的控制下，控制所述第二节点的电平；所述第二控制电路在所述第四时钟信号和所述输出信号的控制下，控制所述第二节点的电平；所述输出电路在所述第一节点的电平和所述第二节点的电平的控制下，控制所述输出端的电平；所述第一复位电路在所述第一使能信号的控制下，控制所述输出端的电平，以在所述检测阶段稳定输出所述非工作电平。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开至少一个实施例提供的一种外部补偿电流检测系统的示意图；
图2为本公开至少一个实施例提供的一种移位寄存器单元的示意框图；
图3为本公开至少一个实施例提供的另一种移位寄存器单元的示意图；
图4为本公开至少一个实施例提供的一种输入控制电路的示意图；
图5A为本公开至少一个实施例提供的一种移位寄存器单元的电路结构图；
图5B为本公开至少一个实施例提供的另一种移位寄存器单元的电路结构图；
图6为本公开至少一个实施例提供的另一种移位寄存器单元的电路结构图；
图7为本公开至少一个实施例提供的一种移位寄存器单元的信号时序图；
图8为本公开至少一个实施例提供的一种栅极驱动电路的示意框图；
图9为本公开至少一个实施例提供的一种显示装置的示意框图；以及
图10为本公开至少一个实施例提供的一种移位寄存器单元的驱动方法的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不 表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“耦接”或者“连接”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
为了减少显示面板的功耗，降低刷新频率是比较有效的方法。在降低刷新频率的同时，还需要保证显示面板的显示质量，因此，需要GOA电路在较低的刷新频率下保持低噪声的稳定输出。此外，有机发光二极管(Organic Light Emitting Diode，OLED)显示装置通常包括多个阵列排布的像素单元，每个像素单元例如可以包括像素电路。在OLED显示装置中，由于制备工艺的限制，各个像素电路中的驱动晶体管的阈值电压可能存在差异，而且由于例如温度变化的影响，驱动晶体管的阈值电压可能会产生漂移现象。因此，各个驱动晶体管的阈值电压的不同可能会导致显示不良(例如显示不均匀)，所以需要对阈值电压进行补偿。并且，在驱动晶体管处于关态(也即截止状态)时，由于漏电流的存在，也可能会导致显示不良。因此，OLED显示装置通常采用具有补偿功能的像素电路，例如，在基本像素电路(例如，2T1C，即两个晶体管和一个电容)的基础上增加晶体管和/或电容，从而提供补偿功能。例如，补偿功能可以通过电压补偿、电流补偿或混合补偿来实现，具有补偿功能的像素电路例如为常见的4T1C或4T2C电路等。
通常，在外部补偿电流检测系统中，如图1所示，电流检测阶段和驱动阶段是分开的。例如，在电流检测阶段，图1中的EM信号需一直维持低电平，使晶体管T4关闭，从而使OLED不发光，而在驱动阶段，EM信号需正常工作。因此，EM信号需要满足长时间保持非工作电平(例如低电平)和正常驱动工作两种功能。然而，常规的GOA电路所提供的信号无法实现长时间保持非工作电平(例如低电平)的功能。
因此，本公开至少一个实施例提供一种移位寄存器单元，该移位寄存器单元包括：输入控制电路、第一控制电路、第二控制电路、输出电路和第一复位电路。输入控制电路与第一节点、输入端、第一时钟信号端、第二时钟信号端和第三时钟信号端耦接，配置为在输入端的输入信号、第一时钟信号端的第一时钟信号、第二时钟信号端的第二时钟信号、第三时钟信号端的第三时钟信号的控制下，控制第一节点的电平。第一控制电路与第一节点和第二节点耦接，配置为在第一节点的电平的控制下，控制第二节点的电平。第二控制电路与第四时钟信号端、第二节点和输出端耦接，配置为在第四时钟信号端的第四时钟信号和输出端的输出信号的控制下，控制第二节点的电平。输出电路与第一节点、第二节点和输出端耦接，配置为在第一节点的电平和第二节点的电平的控制下，控制输出端的电平。第一复位电路与输出端和第一使能信号端耦接，第一使能信号端由第一使能信号线提供第一使能信号，第一复位电路配置为在第一使能信号的控制下，控制输出端的电平，以在检测阶段稳定输出非工作电平。
相应地，本公开至少一个实施例还提供一种根据上述移位寄存器单元的驱动方法、栅极驱动电路以及显示装置。
本公开的实施例提供的移位寄存器单元可确保在低频驱动下(例如，1-120Hz)，及时去除输出噪声干扰，从而确保GOA在检测阶段稳定输出非工作电平(例如，低电平)。该移位寄存器单元既可以在检测阶段实现长时间低电平的稳定输出，以满足外部补偿检测阶段需求，也可以在驱动阶段提供正常工作的驱动信号以满足显示面板驱动阶段需求。
下面结合附图对本公开的实施例及其示例进行详细说明。应当注意的是，不同的附图中相同的附图标记将用于指代已描述的相同的元件。
需要说明的是，在本公开的实施例中，例如，当各个电路实现为N型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如截止)；术语“工作电平”表示该节点处于高电平，从而当一个晶体管的栅极耦接到该节点时，该晶体管导通；术语“非工作电平”表示该节点处于低电平，从而当一个晶体管的栅极耦接到该节点时，该晶体管截止。又例如，当各个电路实现为P型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如截止)；术语“工作电平”表示该节点处于低电平，从而当一个晶体管的栅极耦接到该节点时，该晶体管导通；术语“非工作电位”表示该节点处于高电平，从而当一个晶体管的栅极耦接到该节点时，该晶体管截止。
本公开的至少一个实施例提供一种移位寄存器单元10，如图2所示。图2为根据本公开至少一个实施例的一种移位寄存器单元10的示意图。该移位寄存器单元10，包括：输入控制电路100、第一控制电路200、第二控制电路300、第一复位电路400和输出电路500。
例如，如图2所示，在一个示例中，输入控制电路100与第一节点N1、输入端INN、第一时钟信号端CLK1、第二时钟信号端CLK2、第三时钟信号端CLK3耦接，配置为在输入端INN的输入信号、第一时钟信号端CLK1的第一时钟信号、第二时钟信号端CLK2的第二时钟信号、第三时钟信号端CLK3的第三时钟信号的控制下，控制第一节点N1的电平。
例如，第一控制电路200与第一节点N1和第二节点N2耦接，配置为在第一节点N1的电平的控制下，控制第二节点N2的电平。
例如，第二控制电路300与第四时钟信号端CLK4、第二节点N2和输出端OT耦接，配置为在第四时钟信号端CLK4的第四时钟信号和输出端OT的输出信号的控制下，控制第二节点N2的电平。
例如，输出电路500与第一节点N1、第二节点N2和输出端OT耦接，配置为在第一 节点N1的电平和第二节点N2的电平的控制下，控制输出端OT的电平。
例如，第一复位电路400与输出端OT和第一使能信号端EN1耦接，第一使能信号端EN1由第一使能信号线提供第一使能信号，第一复位电路400配置为在第一使能信号EN1的控制下，控制输出端OT的电平，以在检测阶段稳定输出非工作电平。
例如，在本公开至少一个实施例中，通过设置第一复位电路400，可以确保在低频驱动下，及时去除输出噪声干扰，从而确保移位寄存器单元10在检测阶段稳定输出非工作电平(例如，低电平)。例如，通过引入第一使能信号EN1，在第一使能信号EN1为有效电平时，该移位寄存器单元10的输出端OT可以在检测阶段长时间稳定地输出非工作电平，以满足外部补偿检测阶段需求，在第一使能信号EN1为无效电平时，该移位寄存器单元10的输出端OT可以在驱动阶段输出正常工作的驱动信号，以满足显示面板驱动阶段需求。
需要说明的是，为了描述方便和简洁，在本公开的各个实施例中，CLK1既可以代表第一时钟信号端，也可以代表第一时钟信号端提供的第一时钟信号；类似的，CLK2既可以代表第二时钟信号端，也可以代表第二时钟信号端提供的第二时钟信号；CLK3既可以代表第三时钟信号端，也可以代表第三时钟信号端提供的第三时钟信号；CLK4既可以代表第四时钟信号端，也可以代表第四时钟信号端提供的第四时钟信号；EN1既可以代表第一使能信号端，也可以代表第一使能信号端提供的第一使能信号，INN既可以代表输入端，也可以代表输入端提供的输入信号，OT既可以代表输出端，也可以代表输出端提供的输出信号。
还需要说明的是，在本公开的各个实施例的说明中，第一节点N1、第二节点N2、后文中出现的第三节点N3、第四节点N4和第五节点N5并非表示实际存在的部件，而是表示电路图中相关电耦接的汇合点。
图3为本公开至少一个实施例提供的另一种移位寄存器单元的示意图。例如，如图3所示，移位寄存器单元11除了上述输入控制电路100、第一控制电路200、第二控制电路300、第一复位电路400和输出电路500以外，还可以包括第二复位电路600。
如图3所示，例如，第二复位电路600与第二节点N2和第二使能信号端EN2耦接，第二使能信号端EN2由第二使能信号线提供第二使能信号，配置为在第二使能信号EN2的控制下，控制第二节点N2的电平。
例如，在本公开至少一个实施例中，移位寄存器单元11通过设置第一复位电路400和第二复位电路600，在第一使能信号EN1和第二使能信号EN2的控制下，可以同时控制输出端OT的电平和第二节点N2的电平，从而更好地确保在低频驱动下，及时去除输出噪声干扰，确保移位寄存器单元11在检测阶段稳定输出非工作电平(例如，低电平)。
例如，在一个示例中，第一使能信号端EN1的第一使能信号和第二使能信号端EN2的第二使能信号可以为同一使能信号EN，相应地，第一使能信号端EN1和第二使能信号端EN2可以为同一信号端。当然，第一使能信号端EN1的第一使能信号和第二使能信号端EN2的第二使能信号也可以是彼此独立的不同的使能信号，相应地，第一使能信号端 EN1和第二使能信号端EN2可以为不同的信号端，本公开的实施例对此不作具体限制。
需要说明的是，为了描述方便和简洁，在本公开的各个实施例中，EN2既可以代表第二使能信号端，也可以代表第二使能信号端提供的第二使能信号；EN既可以代表使能信号端，也可以代表使能信号端提供的使能信号。
图4为本公开至少一个实施例的一种输入控制电路的示意图。例如，在本公开至少一个实施例中，如图4所示，输入控制电路100可以包括输入电路101、第三控制电路102和第三复位电路103。
例如，在一个示例中，输入电路101与第一时钟信号端CLK1、输入端INN、第三节点N3和第四节点N4耦接，配置为响应于输入端INN的输入信号和第一时钟信号端CLK1的第一时钟信号，控制第三节点N3和第四节点N4的电平。
例如，在一个示例中，第三控制电路102与第二时钟信号端CLK2、第一节点N1和第三节点N3耦接，配置为在第三节点N3的电平的控制下，将第二时钟信号端CLK2的第二时钟信号提供至第一节点N1。
例如，在一个示例中，第三复位电路103与第三时钟信号端CLK3、第一节点N1和第三节点N3耦接，配置为响应于第三时钟信号端CLK3的第三时钟信号，控制第三节点N3和第一节点N1的电平。
下面结合图5A详细介绍本公开至少一个实施例提供的一种移位寄存器单元10的电路结构。图5A为本公开至少一个实施例提供的一种移位寄存器单元10的电路结构示意图。需要说明的是，虽然下面以各晶体管为N型晶体管为例对本公开的实施例进行说明，但这并不构成对本公开的实施例的限制。
例如，在本公开至少一个实施例中，如图5A所示，第一复位电路400可以包括第一晶体管T1。例如，该第一晶体管T1的栅极和第一使能信号端EN1耦接以接收第一使能信号，第一晶体管T1的第一极和第一电压端VDD_1耦接以接收第一电压，第一晶体管T1的第二极和输出端OT耦接。
例如，在一个示例中，当第一使能信号EN1有效时，第一晶体管T1导通，第一电压端VDD_1耦接到输出端OT。例如，当第一电压端VDD_1提供的第一电压为非工作电平，即低电平时，可以对输出端OT进行降噪。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管、场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
另外，本公开的实施例中的晶体管均以N型晶体管为例进行说明，此时，晶体管的第一极是漏极，第二极是源极。需要说明的是，本公开包括但不限于此。例如，本公开的实施例提供的移位寄存器单元10中的一个或多个晶体管也可以采用P型晶体管，此时，晶体管第一极是源极，第二极是漏极，只需将选定类型的晶体管的各极参照本公开的实施 例中的相应晶体管的各极相应耦接，并且使相应的电压端提供对应的高电压或低电压即可。当采用N型晶体管时，可以采用氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)作为薄膜晶体管的有源层，相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及防止漏电流。
例如，在本公开至少一个实施例中，如图5A所示，第一控制电路200包括第三晶体管T3。
例如，第三晶体管T3的栅极和第一节点N1耦接，第三晶体管T3的第一极和第三电压端VDD_3耦接以接收第三电压，第三晶体管T3的第二极和第二节点N2耦接。
例如，在一个示例中，当第一节点N1处于有效电平(例如，高电平)时，第三晶体管T3导通，则通过第三晶体管T3，可以将第三电压端VDD_3提供的第三电压(例如，低电平)输入第二节点N2，以将第二节点N2的电平下拉至非工作电平(例如，低电平)。
例如，在本公开至少一个实施例中，如图5A所示，第二控制电路300可以包括第六晶体管T6、第七晶体管T7和第一电容C1。
例如，第六晶体管T6的栅极和第四时钟信号端CLK4耦接以接收第四时钟信号，第六晶体管T6的第一极和第二节点N2耦接，第六晶体管T6的第二极和第五电压端VDD_5耦接以接收第五电压。
例如，第七晶体管T7的栅极和输出端OT耦接，第七晶体管T7的第一极和第六电压端VDD_6耦接以接收第六电压，第七晶体管T7的第二极和第二节点N2耦接。
例如，第一电容C1的第一极和输出端OT耦接，第一电容C1的第二极和第二节点N2耦接。
例如，在一个示例中，第四时钟信号端CLK4提供的第四时钟信号为有效电平(例如，高电平)，第六晶体管T6导通，则通过第六晶体管T6，可以将第五电压端VDD_5提供的第五电压(例如，高电平)输入至第二节点N2，将第二节点N2的电平上拉到工作电平(例如，高电平)。例如，在输出端OT的电平处于工作电平(例如，高电平)时，第七晶体管T7导通，则通过第七晶体管T7，可以将第六电压端VDD_6提供的第六电压(例如，高电平)输入至第二节点N2，使得第二节点N2保持高电平，由于第一电容C1的自举作用，进而使得输出端OT保持高电平。需要说明的是，本公开的各实施例中，存储电容(例如，图5A、图5B和图6中的第一电容C1、第二电容C2、第三电容C3和第四电容C4)可以是通过工艺制作的电容器件，例如通过制作专门的电容电极来实现的电容器件，该存储电容的各个电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现。存储电容也可以是晶体管之间的寄生电容，可以通过晶体管本身与其他器件、线路来实现。
例如，在本公开至少一个实施例中，如图5A所示，输出电路500可以包括第四晶体管T4、第五晶体管T5、第八晶体管T8和第九晶体管T9。
例如，第四晶体管T4的栅极和第一节点N1耦接，第四晶体管T4的第一极和第四电压端VDD_4耦接以接收第四电压，第四晶体管T4的第二极和第五晶体管T5的第一极耦 接。
例如，第五晶体管T5的栅极和第一节点N1耦接，第五晶体管T5的第二极和输出端OT耦接。
例如，第八晶体管T8的栅极和第二节点N2耦接，第八晶体管T8的第一极和输出端OT耦接，第八晶体管T8的第二极和第七电压端VDD_7耦接以接收第七电压。
例如，第九晶体管T9的栅极和输出端OT耦接，第九晶体管T9的第一极和第五晶体管T5的第一极耦接，第九晶体管T9的第二极和第八电压端耦接VDD_8以接收第八电压。
例如，在一个示例中，当第一节点N1处于有效电平(例如，高电平)时，第四晶体管T4和第五晶体管T5均导通，通过第四晶体管T4和第五晶体管T5，可以将第四电压端VDD_4提供的第四电压(例如，低电平)输入至输出端OT，以将输出端OT的电平下拉至非工作电平(例如，低电平)。例如，当第二节点N2的电平处于工作电平(例如，高电平)，第八晶体管T8导通，则通过第八晶体管T8，可以将第七电压端VDD_7提供的第七电压(例如，高电平)输入至输出端OT，将输出端OT的电平上拉到工作电平(例如，高电平)。例如，当输出端OT的电平处于工作电平(例如，高电平)时，第九晶体管T9导通，通过第九晶体管T9，可以将第八电压端VDD_8提供的第八电压(例如，高电平)输入至第四晶体管T4的第二极，以防止第四晶体管T4此时漏电。
例如，在本公开至少一个实施例中，如图5A所示，输入电路101包括第十晶体管T10、第十一晶体管T11、第十二晶体管T12、第十三晶体管T13和第十四晶体管T14。
例如，第十晶体管T10的栅极和输入端INN耦接以接收输入信号，第十晶体管T10的第一极和第十一晶体管T11的第二极耦接，第十晶体管T10的第二极和第九电压端VDD_9耦接以接收第九电压。
例如，第十一晶体管T11的栅极和第一时钟信号端CLK1耦接以接收第一时钟信号，第十一晶体管T11的第一极和第三节点N3耦接。
例如，第十二晶体管T12的栅极和输入端INN耦接以接收输入信号，第十二晶体管T12的第一极和第十电压端VDD_10耦接以接收第十电压，第十二晶体管T12的第二极和第四节点N4耦接。
例如，第十三晶体管T13的栅极和第十四晶体管T14的第一极耦接，第十三晶体管T13的第一极和第十一电压端VDD_11耦接以接收第十一电压，第十三晶体管T13的第二极和第四节点N4耦接。
例如，第十四晶体管T14的栅极和第十二电压端VDD_12耦接以接收第十二电压，第十四晶体管T14的第二极和第三节点N3耦接。
例如，在一个示例中，当输入端INN提供的输入信号为有效电平(例如，高电平)并且第一时钟信号端CLK1提供的第一时钟信号为有效电平(例如，高电平)时，第十晶体管T10、第十一晶体管T11、第十二晶体管T12均导通，则可以通过第十晶体管T10和第十一晶体管T11，将第九电压端VDD_9提供的第九电压(例如，高电平)输入至第三节点N3，以将第三节点N3的电平上拉至工作电平(例如，高电平)。例如，在第十二电 压端VDD_12提供的第十二电压为有效电平(例如，高电平)时，第十四晶体管T14导通，可以将第三节点耦接至第十三晶体管T13的栅极，即第五节点N5，以将第五节点N5的电平上拉至工作电平(例如，高电平)，则第十三晶体管T13导通。还可以通过第十二晶体管T12和第十三晶体管T13，分别将第十电压端VDD_10提供的第十电压(例如，低电平)和将第十一电压端VDD_11提供的第十一电压(例如，低电平)输入至第四节点N4，以将第四节点N4的电平下拉至非工作电平(例如，低电平)。
例如，在本公开至少一个实施例中，如图5A所示，第三控制电路102包括第十五晶体管T15、第二电容C2和第三电容C3。
例如，第十五晶体管T15的栅极和第三节点N3耦接，第十五晶体管T15的第一极和第一节点N1耦接，第十五晶体管T15的第二极和第二时钟信号端CLK2耦接以接收第二时钟信号。
例如，第二电容C2的第一极和第一节点N1耦接，第二电容C2的第二极和第三节点N3耦接。
例如，第三电容C3的第一极和第三节点N3耦接，第三电容C3的第二极和第十三电压端VDD_13耦接以接收第十三电压。
例如，在一个示例中，当第三节点N3处于有效电平(例如，高电平)时，第十五晶体管T15导通，则通过第十五晶体管T15可以将第二时钟信号端CLK2提供的第二时钟信号输入至第一节点N1。例如，当第二时钟信号为有效电平(例如，高电平)时，将第一节点N1上拉至工作电平(例如，高电平)。例如，当第二时钟信号为无效电平(例如，低电平)时，可以将第一节点N1下拉至非工作电平(例如，低电平)。
例如，在本公开至少一个实施例中，如图5A所示，第三复位电路103包括第十六晶体管T16、第十七晶体管T17、第十八晶体管T18、第十九晶体管T19和第四电容C4。
例如，第十六晶体管T16的栅极和第三时钟信号端CLK3耦接以接收第三时钟信号，第十六晶体管T16的第一极和第十四电压端VDD_14耦接以接收第十四电压，第十六晶体管T16的第二极和第十七晶体管T17的栅极耦接。
例如，第十七晶体管T17的第一极和第十五电压端VDD_15耦接以接收第十五电压，第十七晶体管T17的第二极和第十九晶体管T19的第一极耦接。
例如，第十八晶体管T18的栅极和第四节点N4耦接，第十八晶体管T18的第一极和第十六电压端VDD_16耦接以接收第十六电压，第十八晶体管T18的第二极和第一节点N1耦接。
例如，第十九晶体管T19的栅极和第十七电压端VDD_17耦接以接收第十七电压，第十九晶体管T19的第二极和第三节点N3耦接。
例如，第四电容C4的第一极和第十七晶体管T17的栅极耦接，第四电容C4的第二极和第十七晶体管T17的第一极耦接。
例如，在一个示例中，当第三时钟信号端CLK3提供的第三时钟信号处于有效电平(例如，高电平)时，第十六晶体管T16导通，可以通过第十六晶体管T16将第十四电压端 VDD_14提供的第十四电压(例如，高电平)输入至第四节点N4，将第四节点N4上拉至工作电平(例如，高电平)。响应于第四节点N4处于工作电平(例如，高电平)，第十七晶体管T17和第十八晶体管T18导通，则通过第十七晶体管T17，可以将第十五电压端VDD_15提供的第十五电压(例如，低电平)输入至第十三晶体管T13的栅极，即第五节点N5，以将第五节点N5的电平下拉至非工作电平(例如，低电平)。例如，当第十七电压端VDD_17提供的第十七电压为有效电平时，第十九晶体管T19导通，则第三节点N3和第五节点N5耦接，可以将第三节点N3下拉至非工作电平(例如，低电平)。还可以通过导通的第十八晶体管T18，将第十六电压端VDD_16提供的第十六电压(例如，低电平)输入至第一节点N1，将第一节点N1下拉至无效电平，即低电平。
例如，在本公开至少一个实施例中，第十九晶体管T19和第十四晶体管T14可以为同一晶体管，则第十七电压端VDD_17和第十二电压端VDD_12为同一电压端，例如提供有效电平，即高电平。
图5B为本公开至少一个实施例提供的一种移位寄存器单元11的电路结构示意图。需要说明的是，与图5A的移位寄存器单元10相比，在图5B中的移位寄存器单元11还包括第二复位电路600的电路结构，除此之外，图5B中的移位寄存器单元11的电路结构与图5A中的移位寄存器单元10的电路结构基本一致。
例如，在本公开至少一个实施例中，如图5B所示，第二复位电路600可以包括第二晶体管T2。例如，第二晶体管T2的栅极和第二使能信号端EN2耦接以接收第二使能信号，第二晶体管T2的第一极和第二节点N2耦接，第二晶体管T2的第二极和第二电压端VDD_2耦接以接收第二电压。
例如，在一个示例中，当第二使能信号EN2有效时，第二晶体管T2导通，第二电压端VDD_2耦接到第二节点N2。例如，当第二电压端VDD_2提供的第二电压为非工作电平，即低电平时，可以对第二节点N2进行降噪。
例如，在一个示例中，第一使能信号EN1和第二使能信号EN2可以为同一使能信号EN。例如，当第一使能信号EN1和第二使能信号EN2同时为有效信号时，则可以同时对输出端OT和第二节点N2的电平进行控制，及时去除输出噪声干扰，确保移位寄存器单元10在检测阶段稳定地输出非工作电平(例如，低电平)。
本公开至少一个实施例还提供一种移位寄存器单元12。图6为本公开至少一个实施例提供的另一种移位寄存器单元12的电路结构图。如图6所示，在一个示例中，该移位寄存器单元12包括：第一晶体管T1至第十八晶体管T18、第一电容C1至第四电容C4。例如，与图5B的移位寄存器单元11相比，在图6中是以所有晶体管都为N型晶体管为示例，并且第十四晶体管T14和第十九晶体管T19为同一晶体管，第一使能信号端EN1和第二使能信号端EN2为同一使能信号端EN，除此之外，图6中的移位寄存器单元12的电路结构与图5B中的移位寄存器单元11的电路结构基本一致。
需要说明的是，在图6所示的示例中，第一电压端VDD_1、第二电压端VDD_2、第三电压端VDD_3、第四电压端VDD_4、第十电压端VDD_10、第十一电压端VDD_11、 第十三电压端VDD_13、第十五电压端VDD_15和第十六电压端VDD_16均提供处于非工作电平的电压，例如，低电平电压VGL。例如，在一个示例中，这些电压端可以均耦接到电压端VGL，例如，电压端VGL可以被配置为保持输入直流低电平信号，例如接地。第五电压端VDD_5、第六电压端VDD_6、第七电压端VDD_7、第八电压端VDD_8、第九电压端VDD_9、第十二电压端VDD_12和第十四电压端VDD_14均提供处于工作电平的电压，例如，高电平电压VGH。例如，在一个示例中，这些电压端可以均耦接到电压端VGH，例如，电压端VGH可以被配置为保持输入直流高电平信号。当然，在本公开的实施例中，各个电压端均可以是另行提供的电压端，本公开的实施例对此不作限制。
例如，在一个示例中，如图6所示，第一晶体管T1的栅极和第一使能信号端EN1耦接以接收第一使能信号(也即，与使能信号端EN耦接以接收使能信号)，第一晶体管T1的第一极和第一电压端耦接以接收第一电压(例如，低电平电压VGL)，第一晶体管T1的第二极和输出端OT耦接。第二晶体管T2的栅极和第二使能信号端EN2耦接以接收第二使能信号(也即，与使能信号端EN耦接以接收使能信号)，第二晶体管T2的第一极和第二节点N2耦接，第二晶体管T2的第二极和第二电压端耦接以接收第二电压(例如，低电平电压VGL)。第三晶体管T3的栅极和第一节点N1耦接，第三晶体管T3的第一极和第三电压端耦接以接收第三电压(例如，低电平电压VGL)，第三晶体管T3的第二极和第二节点N2耦接。第四晶体管T4的栅极和第一节点N1耦接，第四晶体管T4的第一极和第四电压端耦接以接收第四电压(例如，低电平电压VGL)，第四晶体管T4的第二极和第五晶体管T5的第一极耦接。第五晶体管T5的栅极和第一节点N1耦接，第五晶体管T5的第二极和输出端OT耦接。第六晶体管T6的栅极和第四时钟信号端CLK4耦接以接收第四时钟信号，第六晶体管T6的第一极和第二节点N2耦接，第六晶体管T6的第二极和第五电压端耦接以接收第五电压(例如，高电平电压VGH)。第七晶体管T7的栅极和输出端OT耦接，第七晶体管T7的第一极和第六电压端耦接以接收第六电压(例如，高电平电压VGH)，第七晶体管T7的第二极和第二节点N2耦接。第八晶体管T8的栅极和第二节点N2耦接，第八晶体管T8的第一极和输出端OT耦接，第八晶体管T8的第二极和第七电压端耦接以接收第七电压(例如，高电平电压VGH)。第九晶体管T9的栅极和输出端OT耦接，第九晶体管T9的第一极和第五晶体管T5的第一极耦接，第九晶体管T9的第二极和第八电压端耦接以接收第八电压(例如，高电平电压VGH)。第一电容C1的第一极和输出端OT耦接，第一电容C1的第二极和第二节点N2耦接。第十晶体管T10的栅极和输入端INN耦接以接收输入信号，第十晶体管T10的第一极和第十一晶体管T11的第二极耦接，第十晶体管T10的第二极和第九电压端耦接以接收第九电压(例如，高电平电压VGH)。第十一晶体管T11的栅极和第一时钟信号端CLK1耦接以接收第一时钟信号，第十一晶体管T11的第一极和第三节点N3耦接。第十二晶体管T12的栅极和输入端INN耦接以接收输入信号，第十二晶体管T12的第一极和第十电压端耦接以接收第十电压(例如，低电平电压VGL)，第十二晶体管T12的第二极和第四节点N4耦接。第十三晶体管T13的栅极和第十四晶体管T14的第一极耦接，第十三晶体管T13的第一极和 第十一电压端耦接以接收第十一电压(例如，低电平电压VGL)，第十三晶体管T13的第二极和第四节点N4耦接。第十四晶体管T14的栅极和第十二电压端耦接以接收第十二电压(例如，高电平电压VGH)，第十四晶体管T14的第二极和第三节点N3耦接。第十五晶体管T15的栅极和第三节点N3耦接，第十五晶体管T15的第一极和第一节点N1耦接，第十五晶体管T15的第二极和第二时钟信号端CLK2耦接以接收第二时钟信号。第二电容C2的第一极和第一节点N1耦接，第二电容C2的第二极和第三节点N3耦接。第三电容C3的第一极和第三节点N3耦接，第三电容C3的第二极和第十三电压端耦接以接收第十三电压(例如，低电平电压VGL)。第十六晶体管T16的栅极和第三时钟信号端CLK3耦接以接收第三时钟信号，第十六晶体管T16的第一极和第十四电压端(例如，高电平电压VGH)耦接以接收第十四电压，第十六晶体管T16的第二极和第十七晶体管T17的栅极耦接。第十七晶体管T17的第一极和第十五电压端耦接以接收第十五电压(例如，低电平电压VGL)，第十七晶体管T17的第二极和第十三晶体管T13的栅极耦接。第十八晶体管T18的栅极和第四节点N4耦接，第十八晶体管T18的第一极和第十六电压端耦接以接收第十六电压(例如，低电平电压VGL)，第十八晶体管T18的第二极和第一节点N1耦接。第四电容C4的第一极和第十七晶体管T17的栅极耦接，第四电容C4的第二极和第十七晶体管T17的第一极耦接。
图7为本公开一实施例提供的一种移位寄存器单元的信号时序图。下面结合图7所示的信号时序图，对图6所示的移位寄存器单元12的工作原理进行说明。需要说明的是，图7中所示的信号时序图的电位的高低仅是示意性的，不代表真实电位值。还需要说明的是，图5A和图5B中的移位寄存器单元10和11的工作原理与图6中移位寄存器单元12基本一致，为了简洁，本公开的实施例对此不再赘述。
如图7所示，该信号时序图包括第一阶段P1、第二阶段P2、第三阶段P3、第四阶段P4和第五阶段P5。例如，在本公开的实施例中，驱动阶段包括第一阶段P1、第二阶段P2、第三阶段P3和第四阶段P4，而检测阶段(也称为非工作电平保持阶段)包括第五阶段P5。例如，在第一阶段P1至第四阶段P4期间(即，在驱动阶段期间)，使能信号EN处于无效电平(例如，低电平)，移位寄存器单元处于正常工作状态，即正常驱动阶段，而在第五阶段P5，即检测阶段(例如，低电平保持阶段)，使能信号EN处于有效电平(例如，高电平)。
例如，在第一阶段P1，输入端INN提供的输入信号和第一时钟信号端CLK1提供的第一时钟信号同时处于有效电平(例如，高电平)，第二时钟信号CLK2、第三时钟信号CLK3和第四时钟信号CLK4处于无效电平(例如，低电平)，第十晶体管T10、第十一晶体管T11导通，将第九电压端VDD_9提供的第九电压(例如，高电平)输入至第三节点N3，以将第三节点N3的电平上拉至工作电平(例如，高电平)。此时，第十五晶体管T15导通，可以将第二时钟信号端CLK2提供的第二时钟信号(在第一阶段P1，CLK2为低电平)提供至第一节点N1，则第一节点N1处于非工作电平(即，低电平)。此时，第三晶体管T3、第四晶体管T4和第五晶体管T5均截止，输出端OT为有效电平，即高电 平。
在第二阶段P2，第二时钟信号端CLK2提供的第二时钟信号由低电平变为高电平，输入端INN提供的输入信号和第一时钟信号端CLK1提供的第一时钟信号由高电平变为低电平，第三时钟信号CLK3和第四时钟信号CLK4处于低电平，此时，第十五晶体管T15将第二时钟信号CLK2的高电平输入至第一节点N1，由于第一电容C1的自举作用，第十五晶体管T15更加充分导通，将第二时钟信号CLK2的高电平输入至第一节点N1，将第一节点N1的电平上拉至工作电平，即高电平。此时，第三晶体管T3、第四晶体管T4和第五晶体管T5均导通，输出端OT被下拉至低电平。
在第三阶段P3，第三时钟信号CLK3由低电平变为高电平，输入信号INN、第一时钟信号CLK1、第二时钟信号CLK2和第四时钟信号CLK4处于低电平。第十六晶体管T16导通，将第十四电压端VDD_14提供的第十四电压(例如，高电平)输入至第四节点N4，将第四节点N4上拉至工作电平(例如，高电平)。此时，第十八晶体管T18导通，将第十六电压端VDD_16提供的第十六电压(例如，低电平)输入至第一节点N1，将第一节点N1下拉至低电平。此时，第三晶体管T3、第四晶体管T4和第五晶体管T5均截止，输出端OT为维持低电平。
在第四阶段P4，第四时钟信号端CLK4提供的第四时钟信号由低电平变为高电平，输入端INN提供的输入信号、第一时钟信号CLK1、第二时钟信号CLK2和第三时钟信号CLK3处于低电平。此时，第一节点N1保持低电平，第六晶体管T6导通，通过第六晶体管T6，可以将第五电压端VDD_5提供的第五电压(例如，高电平)输入至第二节点N2，将第二节点N2的电平上拉到工作电平(例如，高电平)。此时，第八晶体管T8导通，则通过第八晶体管T8，将第七电压端VDD_7提供的第七电压(例如，高电平)输入至输出端OT，将输出端OT的电平上拉到工作电平(例如，高电平)。并且，由于第一电容C1的自举作用，输出端OT的电平可保持在高电平VGH。
在上述第一阶段P1至第四阶段P4，即驱动阶段，移位寄存器单元12可以正常工作，实现正常的驱动功能，满足显示面板驱动阶段的需求。
在第五阶段P5，输入信号INN、第一时钟信号CLK1、第二时钟信号CLK2、第三时钟信号CLK3和第四时钟信号CLK4均处于无效电平，即低电平，并且使能信号EN处于有效电平，即高电平。此时，第一晶体管T1和第二晶体管T2导通，则通过第一晶体管T1可以将第一电压端VDD_1提供的第一电压(例如，低电平)输入至输出端OT，对输出端OT进行降噪，以保证输出端OT稳定输出低电平。通过第二晶体管T2可以将第二电压端VDD_2提供的第二电压(例如，低电平)输入至第二节点N2，以保证第二节点N2为非工作电平，保证第八晶体管T8截止，防止第八晶体管T8漏电。
例如，如果不设置第一晶体管T1，在第五阶段P5，第一节点N1保持低电平，第四晶体管T4和第五晶体管T5截止，输出端OT处于浮动状态，无法稳定输出低电平。例如，如果不设置第二晶体管T2，第六晶体管T6可能漏电，使得第二节点N2的电位逐渐抬高，进而导致第八晶体管T8漏电增加，最终导致输出端OT电位逐渐抬高，也无法稳定输出 低电平。
在上述第五阶段P5，即检测阶段，移位寄存器单元12可以长时间稳定地输出非工作电平(例如，低电平)。
因此，本公开的实施例提供的移位寄存器单元10/11/12可确保在低频驱动下，及时去除输出噪声干扰，从而确保GOA在检测阶段稳定输出非工作电平(例如，低电平)，从而，移位寄存器单元10/11/12既可以在驱动阶段实现正常驱动功能，还可以在检测阶段保证长时间非工作电平的稳定输出。
本公开至少一个实施例还提供一种栅极驱动电路，该栅极驱动电路包括多个级联的本公开任一实施例提供的移位寄存器单元。该栅极驱动电路可以确保在低频驱动下，及时去除输出噪声干扰，从而确保在检测阶段稳定输出非工作电平(例如，低电平)。因此，既可以在驱动阶段实现正常驱动功能，还可以在检测阶段保证长时间非工作电平的稳定输出。
图8为本公开至少一实施例提供的一种栅极驱动电路的示意框图。如图8所示，该栅极驱动电路20包括多个级联的移位寄存器单元(例如，A1、A2、A3等)。多个移位寄存器单元的数量不受限制，可以根据实际需求而定。例如，移位寄存器单元采用本公开任一实施例所述的移位寄存器单元10/11/12。例如，在栅极驱动电路20中，可以部分或全部移位寄存器单元采用本公开任一实施例所述的移位寄存器单元10/11/12。例如，该栅极驱动电路20可以采用与薄膜晶体管同样制程的工艺直接集成在显示装置的阵列基板上，以构成GOA，可以实现例如逐行扫描驱动功能。
例如，在一些示例中，如图8所示，每个移位寄存器单元可以具有第一节点N1、输入端INN、第一时钟信号端CLK1、第二时钟信号端CLK2、第三时钟信号端CLK3、第四时钟信号端CLK4、信号使能端EN和输出端OT。
例如，在本公开一个实施例提供的栅极驱动电路20中，第N级移位寄存器单元的输入端INN和第N-1级移位寄存器单元的第一节点N1耦接；第N级移位寄存器单元的第一节点N1和第N+1级移位寄存器单元的输入端INN耦接；N为大于2的整数。
例如，在一些示例中，如图8所示，除最后一级移位寄存器单元(例如，第三移位寄存器单元A3)外，其余各级移位寄存器单元的第一节点N1和下一级移位寄存器单元的输入端INN耦接。除第一级移位寄存器单元(例如，第一移位寄存器单元A1)外，其余各级移位寄存器单元的输入端INN和上一级移位寄存器单元的第一节点N1耦接。例如，第一级移位寄存器单元的输入端INN可以被配置为接收触发信号STV，本公开的实施例对此不做具体限制。
如图8所示，该栅极驱动电路20还可以包括第一时钟信号线CLK1_L、第二时钟信号线CLK2_L、第三时钟信号线CLK3_L和第四时钟信号线CLK4_L。例如，如图8所示，各级移位寄存器单元与上述各子时钟信号线的耦接方式如下并以此类推。例如，第一级移位寄存器单元A1的第一时钟信号端CLK1、第二级移位寄存器单元A2的第四时钟信号端CLK4和第三级移位寄存器单元A3的第三时钟信号端CLK3与第一时钟信号线CLK1-L 耦接；第一级移位寄存器单元A1的第二时钟信号端CLK2、第二级移位寄存器单元A2的第一时钟信号端CLK1和第三级移位寄存器单元A3的第四时钟信号端CLK4与第二时钟信号线CLK2-L耦接；第一级移位寄存器单元A1的第三时钟信号端CLK3、第二级移位寄存器单元A2的第二时钟信号端CLK2和第三级移位寄存器单元A3的第一时钟信号端CLK1与第三时钟信号线CLK3-L耦接；第一级移位寄存器单元A1的第四时钟信号端CLK4、第二级移位寄存器单元A2的第三时钟信号端CLK3和第三级移位寄存器单元A3的第二时钟信号端CLK2与第四时钟信号线CLK4-L耦接，以此类推。需要说明的是，本公开的实施例包括但不限于上述耦接方式。例如，在其他示例中，也可以使栅极驱动电路20中各个移位寄存器单元的第一时钟信号端CLK1、第二时钟信号端CLK2、第三时钟信号端CLK3和第四时钟信号端CLK4与另行提供的多条时钟信号线耦接，该多条时钟信号线例如多于4条，并且，并非所有的第一时钟信号端CLK1都耦接到同一条时钟信号线，并非所有的第二时钟信号端CLK2都耦接到同一条时钟信号线，并非所有的第三时钟信号端CLK3都耦接到同一条时钟信号线，并非所有的第四时钟信号端CLK4都耦接到同一条时钟信号线，这可以根据实际需求而定，本公开的实施例对此不作限制。
例如，第一时钟信号线CLK1_L、第二时钟信号线CLK2_L和第三时钟信号线CLK3_L和第四时钟信号线CLK4_L上提供的时钟信号时序可以采用图7中所示的信号时序，以实现栅极驱动电路20在检测阶段长时间非工作电平稳定输出的功能。
例如，应用该栅极驱动电路20的显示装置还可以包括时序控制器T-CON。例如，时序控制器T-CON被配置为和第一时钟信号线CLK1_L、第二时钟信号线CLK2_L、第三时钟信号线CLK3_L和第四时钟信号线CLK4_L耦接，以向各级移位寄存器单元提供各个时钟信号。时序控制器T-CON还可以被配置为提供触发信号STV。需要说明的是，时序控制器T-CON提供的多个时钟信号彼此之间的相位关系可以根据实际需求而定。在不同的示例中，根据不同的配置，还可以提供更多的时钟信号。
例如，在一些示例中，当采用该栅极驱动电路20驱动显示面板时，可以将该栅极驱动电路20设置于显示面板的一侧。例如，该栅极驱动电路20可以采用与薄膜晶体管同样制程的工艺直接集成在显示面板的阵列基板上，以构成GOA，从而实现驱动功能。当然，还可以分别在显示面板的两侧设置该栅极驱动电路20，以实现双边驱动，本公开的实施例对该栅极驱动电路20的设置方式不作限制。该栅极驱动电路20的工作原理可参考本公开的实施例中对于移位寄存器单元10/11/12的工作原理的相应描述，这里不再赘述。
本公开至少一个实施例还提供一种显示装置。该显示装置包括本公开任一实施例所述的移位寄存器单元或者本公开任一实施例所述的栅极驱动电路。
图9为本公开至少一个实施例提供的一种显示装置的示意框图。例如，如图9所示，该显示装置30包括栅极驱动电路20，该栅极驱动电路20可以为本公开的任一实施例提供的栅极驱动电路20。例如，本实施例中的显示装置30可以为液晶显示面板、液晶电视、OLED显示面板、OLED电视、OLED显示器、量子点发光二极管(Quantum Dot Light Emitting Diode，QLED)显示面板等，也可以为电子书、手机、平板电脑、笔记本电脑、 数码相框、导航仪等任意具有显示功能的产品或部件，本公开的实施例对此不作限制。显示装置30的技术效果可以参考上述实施例中关于移位寄存器单元10/11/12和栅极驱动电路20的相应描述，这里不再赘述。
例如，在一些示例中，显示装置30包括显示面板3000、栅极驱动器3010、和数据驱动器3030。显示面板3000包括根据多条扫描线GL和多条数据线DL交叉限定的多个像素单元P；栅极驱动器3010用于驱动多条扫描线GL，栅极驱动器3010可以为本公开任一实施例提供的栅极驱动电路20；数据驱动器3030用于驱动多条数据线DL。数据驱动器3030通过数据线DL与像素单元P电耦接，栅极驱动器3010通过扫描线GL与像素单元P电耦接。
例如，栅极驱动器3010和数据驱动器3030可以实现为半导体芯片。例如，栅极驱动器3010(栅极驱动电路20)也可以实现为GOA电路。该显示装置30还可以包括其他部件，例如时序控制器、信号解码电路、电压转换电路等，这些部件例如可以采用已有的常规部件，这里不再详述。
图10为本公开至少一个实施例提供的一种移位寄存器单元的驱动方法1000的流程图。例如，如图10所示，该移位寄存器单元的驱动方法1000可以包括：
步骤S1001：在驱动阶段，在输入信号INN、第一时钟信号CLK1、第二时钟信号CLK2、第三时钟信号CLK3、第四时钟信号CLK4和使能信号EN的控制下，控制输出端OT的电平，以在驱动阶段输出驱动信号；以及
步骤S1002：在检测阶段，输入控制电路100在输入信号INN、第一时钟信号CLK1、第二时钟信号CLK2和第三时钟信号CLK3的控制下，控制第一节点N1的电平为非工作电平，第一控制电路200在第一节点N1的电平的控制下，控制第二节点N2的电平，第二控制电路300在第四时钟信号CLK4和输出信号OT的控制下，控制第二节点N2的电平；输出电路500在第一节点N1的电平和第二节点N2的电平的控制下，控制输出端OT的电平；第一复位电路400在第一使能信号EN1的控制下，控制输出端OT的电平，以在检测阶段稳定输出非工作电平(例如，低电平)。
关于本公开的实施例提供的驱动方法的详细描述以及技术效果可以参考本公开的实施例中对于移位寄存器单元10/11/12和栅极驱动电路20的相应描述，这里不再赘述。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种移位寄存器单元，包括：输入控制电路、第一控制电路、第二控制电路、输出电路和第一复位电路；其中，
    所述输入控制电路与第一节点、输入端、第一时钟信号端、第二时钟信号端、第三时钟信号端耦接，配置为在所述输入端的输入信号、所述第一时钟信号端的第一时钟信号、所述第二时钟信号端的第二时钟信号、所述第三时钟信号端的第三时钟信号的控制下，控制所述第一节点的电平；
    所述第一控制电路与所述第一节点和第二节点耦接，配置为在所述第一节点的电平的控制下，控制所述第二节点的电平；
    所述第二控制电路与第四时钟信号端、所述第二节点和输出端耦接，配置为在所述第四时钟信号端的第四时钟信号和所述输出端的输出信号的控制下，控制所述第二节点的电平；
    所述输出电路与所述第一节点、所述第二节点和所述输出端耦接，配置为在所述第一节点的电平和所述第二节点的电平的控制下，控制所述输出端的电平；
    所述第一复位电路与所述输出端和第一使能信号端耦接，所述第一使能信号端由第一使能信号线提供第一使能信号，所述第一复位电路配置为在所述第一使能信号的控制下，控制所述输出端的电平，以在检测阶段稳定输出非工作电平。
  2. 根据权利要求1所述的移位寄存器单元，还包括：第二复位电路；其中，
    所述第二复位电路与所述第二节点和第二使能信号端耦接，所述第二使能信号端由第二使能信号线提供第二使能信号，配置为在所述第二使能信号的控制下，控制所述第二节点的电平。
  3. 根据权利要求2所述的移位寄存器单元，其中，所述第一使能信号和所述第二使能信号为同一使能信号。
  4. 根据权利要求1-3中任一项所述的移位寄存器单元，其中，所述第一复位电路包括第一晶体管，
    所述第一晶体管的栅极和所述第一使能信号端耦接以接收所述第一使能信号，所述第一晶体管的第一极和第一电压端耦接以接收第一电压，所述第一晶体管的第二极和所述输出端耦接。
  5. 根据权利要求2或3中所述的移位寄存器单元，其中，所述第二复位电路包括第二晶体管，
    所述第二晶体管的栅极和所述第二使能信号端耦接以接收所述第二使能信号，所述第二晶体管的第一极和所述第二节点耦接，所述第二晶体管的第二极和第二电压端耦接以接收第二电压。
  6. 根据权利要求1-5中任一项所述的移位寄存器单元，其中，所述输入控制电路包括输入电路，
    所述输入电路与所述第一时钟信号端、所述输入端、第三节点和第四节点耦接，配置为响应于所述输入端的输入信号和所述第一时钟信号端的第一时钟信号，控制所述第三节点和所述第四节点的电平。
  7. 根据权利要求6所述的移位寄存器单元，其中，所述输入控制电路包括第三控制电路，
    所述第三控制电路与所述第二时钟信号端、所述第一节点和所述第三节点耦接，配置为在所述第三节点的电平的控制下，将所述第二时钟信号端的第二时钟信号提供至所述第一节点。
  8. 根据权利要求7所述的移位寄存器单元，其中，所述输入控制电路包括第三复位电路，
    所述第三复位电路与所述第三时钟信号端、所述第一节点、所述第三节点耦接，配置为响应于所述第三时钟信号端的第三时钟信号，控制所述第三节点和所述第一节点的电平。
  9. 根据权利要求1-8中任一项所述的移位寄存器单元，其中，所述第一控制电路包括第三晶体管，
    所述第三晶体管的栅极和所述第一节点耦接，所述第三晶体管的第一极和第三电压端耦接以接收第三电压，所述第三晶体管的第二极和所述第二节点耦接。
  10. 根据权利要求1-9中任一项所述的移位寄存器单元，其中，所述第二控制电路包括第六晶体管、第七晶体管和第一电容，
    所述第六晶体管的栅极和所述第四时钟信号端耦接以接收所述第四时钟信号，所述第六晶体管的第一极和所述第二节点耦接，所述第六晶体管的第二极和第五电压端耦接以接收第五电压；
    所述第七晶体管的栅极和所述输出端耦接，所述第七晶体管的第一极和第六电压端耦接以接收第六电压，所述第七晶体管的第二极和所述第二节点耦接；
    所述第一电容的第一极和所述输出端耦接，所述第一电容的第二极和所述第二节点耦接。
  11. 根据权利要求1-10中任一项所述的移位寄存器单元，其中，所述输出电路包括第四晶体管、第五晶体管、第八晶体管和第九晶体管，
    所述第四晶体管的栅极和所述第一节点耦接，所述第四晶体管的第一极和第四电压端耦接以接收第四电压，所述第四晶体管的第二极和所述第五晶体管的第一极耦接；
    所述第五晶体管的栅极和所述第一节点耦接，所述第五晶体管的第二极和所述输出端耦接、
    所述第八晶体管的栅极和所述第二节点耦接，所述第八晶体管的第一极和所述输出端耦接，所述第八晶体管的第二极和第七电压端耦接以接收第七电压；
    所述第九晶体管的栅极和所述输出端耦接，所述第九晶体管的第一极和所述第五晶体管的第一极耦接，所述第九晶体管的第二极和第八电压端耦接以接收第八电压。
  12. 根据权利要求8所述的移位寄存器单元，其中，所述输入电路包括第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管和第十四晶体管，
    所述第十晶体管的栅极和所述输入端耦接以接收所述输入信号，所述第十晶体管的第一极和所述第十一晶体管的第二极耦接，所述第十晶体管的第二极和第九电压端耦接以接收第九电压；
    所述第十一晶体管的栅极和所述第一时钟信号端耦接以接收所述第一时钟信号，所述第十一晶体管的第一极和所述第三节点耦接；
    所述第十二晶体管的栅极和所述输入端耦接以接收所述输入信号，所述第十二晶体管的第一极和第十电压端耦接以接收第十电压，所述第十二晶体管的第二极和所述第四节点耦接；
    所述第十三晶体管的栅极和所述第十四晶体管的第一极耦接，所述第十三晶体管的第一极和第十一电压端耦接以接收第十一电压，所述第十三晶体管的第二极和所述第四节点耦接；
    所述第十四晶体管的栅极和第十二电压端耦接以接收第十二电压，所述第十四晶体管的第二极和所述第三节点耦接。
  13. 根据权利要求7或8所述的移位寄存器单元，其中，所述第三控制电路包括第十五晶体管、第二电容和第三电容，其中，
    所述第十五晶体管的栅极和所述第三节点耦接，所述第十五晶体管的第一极和所述第一节点耦接，所述第十五晶体管的第二极和所述第二时钟信号端耦接以接收所述第二时钟信号；
    所述第二电容的第一极和所述第一节点耦接，所述第二电容的第二极和所述第三节点耦接；
    所述第三电容的第一极和所述第三节点耦接，所述第三电容的第二极和第十三电压端耦接以接收第十三电压。
  14. 根据权利要求12所述的移位寄存器单元，其中，所述第三复位电路包括第十六晶体管、第十七晶体管、第十八晶体管、第十九晶体管和第四电容，其中，
    所述第十六晶体管的栅极和所述第三时钟信号端耦接以接收所述第三时钟信号，所述第十六晶体管的第一极和第十四电压端耦接以接收第十四电压，所述第十六晶体管的第二极和所述第十七晶体管的栅极耦接；
    所述第十七晶体管的第一极和第十五电压端耦接以接收第十五电压，所述第十七晶体管的第二极和所述第十九晶体管的第一极耦接；
    所述第十八晶体管的栅极和所述第四节点耦接，所述第十八晶体管的第一极和第十六电压端耦接以接收第十六电压，所述第十八晶体管的第二极和所述第一节点耦接；
    所述第十九晶体管的栅极和第十七电压端耦接以接收第十七电压，所述第十九晶体管的第二极和所述第三节点耦接；
    所述第四电容的第一极和所述第十七晶体管的栅极耦接，所述第四电容的第二极和所 述第十七晶体管的第一极耦接。
  15. 根据权利要求14所述的移位寄存器单元，其中，所述第十九晶体管和所述第十四晶体管为同一晶体管。
  16. 一种移位寄存器单元，包括：第一晶体管至第十八晶体管、第一电容至第四电容，其中，
    所述第一晶体管的栅极和第一使能信号端耦接以接收第一使能信号，所述第一晶体管的第一极和第一电压端耦接以接收第一电压，所述第一晶体管的第二极和输出端耦接；
    所述第二晶体管的栅极和第二使能信号端耦接以接收第二使能信号，所述第二晶体管的第一极和第二节点耦接，所述第二晶体管的第二极和第二电压端耦接以接收第二电压；
    所述第三晶体管的栅极和第一节点耦接，所述第三晶体管的第一极和第三电压端耦接以接收第三电压，所述第三晶体管的第二极和所述第二节点耦接；
    所述第四晶体管的栅极和所述第一节点耦接，所述第四晶体管的第一极和第四电压端耦接以接收第四电压，所述第四晶体管的第二极和所述第五晶体管的第一极耦接；
    所述第五晶体管的栅极和所述第一节点耦接，所述第五晶体管的第二极和所述输出端耦接；
    所述第六晶体管的栅极和第四时钟信号端耦接以接收第四时钟信号，所述第六晶体管的第一极和所述第二节点耦接，所述第六晶体管的第二极和第五电压端耦接以接收第五电压；
    所述第七晶体管的栅极和所述输出端耦接，所述第七晶体管的第一极和第六电压端耦接以接收第六电压，所述第七晶体管的第二极和所述第二节点耦接；
    所述第八晶体管的栅极和所述第二节点耦接，所述第八晶体管的第一极和所述输出端耦接，所述第八晶体管的第二极和第七电压端耦接以接收第七电压；
    所述第九晶体管的栅极和所述输出端耦接，所述第九晶体管的第一极和所述第五晶体管的第一极耦接，所述第九晶体管的第二极和第八电压端耦接以接收第八电压；
    所述第一电容的第一极和所述输出端耦接，所述第一电容的第二极和所述第二节点耦接；
    所述第十晶体管的栅极和输入端耦接以接收输入信号，所述第十晶体管的第一极和所述第十一晶体管的第二极耦接，所述第十晶体管的第二极和第九电压端耦接以接收第九电压；
    所述第十一晶体管的栅极和第一时钟信号端耦接以接收第一时钟信号，所述第十一晶体管的第一极和第三节点耦接；
    所述第十二晶体管的栅极和所述输入端耦接以接收所述输入信号，所述第十二晶体管的第一极和第十电压端耦接以接收第十电压，所述第十二晶体管的第二极和第四节点耦接；
    所述第十三晶体管的栅极和所述第十四晶体管的第一极耦接，所述第十三晶体管的第一极和第十一电压端耦接以接收第十一电压，所述第十三晶体管的第二极和所述第四节点 耦接；
    所述第十四晶体管的栅极和第十二电压端耦接以接收第十二电压，所述第十四晶体管的第二极和所述第三节点耦接；
    所述第十五晶体管的栅极和所述第三节点耦接，所述第十五晶体管的第一极和所述第一节点耦接，所述第十五晶体管的第二极和第二时钟信号端耦接以接收第二时钟信号；
    所述第二电容的第一极和所述第一节点耦接，所述第二电容的第二极和所述第三节点耦接；
    所述第三电容的第一极和所述第三节点耦接，所述第三电容的第二极和第十三电压端耦接以接收第十三电压；
    所述第十六晶体管的栅极和第三时钟信号端耦接以接收第三时钟信号，所述第十六晶体管的第一极和第十四电压端耦接以接收第十四电压，所述第十六晶体管的第二极和所述第十七晶体管的栅极耦接；
    所述第十七晶体管的第一极和第十五电压端耦接以接收第十五电压，所述第十七晶体管的第二极和所述第十三晶体管的栅极耦接；
    所述第十八晶体管的栅极和所述第四节点耦接，所述第十八晶体管的第一极和第十六电压端耦接以接收第十六电压，所述第十八晶体管的第二极和所述第一节点耦接；
    所述第四电容的第一极和所述第十七晶体管的栅极耦接，所述第四电容的第二极和所述第十七晶体管的第一极耦接。
  17. 一种栅极驱动电路，包括多个级联的如权利要求1-16中任一项所述的移位寄存器单元。
  18. 根据权利要求17所述的栅极驱动电路，其中，第N级移位寄存器单元的输入端和第N-1级移位寄存器单元的第一节点耦接；
    N为大于2的整数。
  19. 一种显示装置，包括如权利要求1-16中任一项所述的移位寄存器单元或如权利要求17或18所述的栅极驱动电路。
  20. 一种如权利要求1-15中任一项所述的移位寄存器单元的驱动方法，包括：
    在驱动阶段，在所述输入信号、所述第一时钟信号、所述第二时钟信号、所述第三时钟信号、所述第四时钟信号和所述使能信号的控制下，控制所述输出端的电平，以在所述驱动阶段输出驱动信号；
    在检测阶段，所述输入控制电路在所述输入信号、所述第一时钟信号、所述第二时钟信号和所述第三时钟信号的控制下，控制所述第一节点的电平为非工作电平；所述第一控制电路在所述第一节点的电平的控制下，控制所述第二节点的电平；所述第二控制电路在所述第四时钟信号和所述输出信号的控制下，控制所述第二节点的电平；所述输出电路在所述第一节点的电平和所述第二节点的电平的控制下，控制所述输出端的电平；所述第一复位电路在所述第一使能信号的控制下，控制所述输出端的电平，以在所述检测阶段稳定输出所述非工作电平。
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