WO2018209937A1 - 移位寄存器及其驱动方法、栅极驱动电路、显示装置 - Google Patents

移位寄存器及其驱动方法、栅极驱动电路、显示装置 Download PDF

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Publication number
WO2018209937A1
WO2018209937A1 PCT/CN2017/115959 CN2017115959W WO2018209937A1 WO 2018209937 A1 WO2018209937 A1 WO 2018209937A1 CN 2017115959 W CN2017115959 W CN 2017115959W WO 2018209937 A1 WO2018209937 A1 WO 2018209937A1
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WIPO (PCT)
Prior art keywords
pull
node
transistor
circuit
shift register
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PCT/CN2017/115959
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English (en)
French (fr)
Inventor
马明超
樊君
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to US16/068,278 priority Critical patent/US11295645B2/en
Publication of WO2018209937A1 publication Critical patent/WO2018209937A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04166—Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared

Definitions

  • Embodiments of the present disclosure relate to a shift register and a driving method thereof, a gate driving circuit, and a display device.
  • a pixel array such as a liquid crystal display typically includes a plurality of rows of gate lines and a plurality of columns of data lines interleaved therewith.
  • the driving of the gate lines can be realized by attaching an integrated driving circuit chip.
  • the gate line driving circuit can be directly integrated on the thin film transistor array substrate to form a GOA (Gate driver On Array) to drive the gate line.
  • GOA Gate driver On Array
  • a GOA composed of a plurality of cascaded shift registers may be used to provide a switching state voltage signal for a plurality of rows of gate lines of the pixel array, thereby controlling the plurality of rows of gate lines to be sequentially turned on, and from the data lines to the corresponding rows in the pixel array.
  • the pixel unit provides a data signal to form a gray voltage required to display each gray level of the image, thereby displaying each frame of the image.
  • At least one embodiment of the present disclosure provides a shift register including an input circuit, a pull-up node charging circuit, and an output circuit.
  • the input circuit is coupled to the first input terminal, the first control terminal, and the pull-up node charging circuit, and configured to respond to the first control signal provided by the first control terminal to set the first input terminal Providing a first input signal output;
  • the pull-up node charging circuit is coupled to the first voltage terminal, the second voltage terminal, the input circuit, and the pull-up node, and configured to be under the control of the first input signal Charging the pull-up node and maintaining a level of the pull-up node;
  • the output circuit is coupled to the pull-up node, the first clock signal end, and the output, and configured to be pulled up Under the control of the level of the node, the first time
  • a first clock signal provided by the clock signal terminal is output to the output terminal.
  • a shift register provided by an embodiment of the present disclosure further includes a pull-down node control circuit, an output reset circuit, and a pull-up node reset circuit.
  • the pull-down node control circuit is coupled to the second clock signal terminal, the second voltage terminal, the pull-down node, the input circuit, and the pull-up node charging circuit, and is configured to be responsive to the second clock signal terminal Providing a second clock signal or the first input signal to control a level of the pull-down node; the pull-up node reset circuit and the pull-down node, the second voltage terminal, and the pull-up node charging circuit Connected, and configured to pull-down reset the pull-up node under control of a level of the pull-down node; the output reset circuit and the output, the pull-down node, and the second voltage terminal Connected, and configured to reset the noise reduction of the output under the control of the level of the pull-down node.
  • the pull-down node control circuit includes a first pull-down node charging circuit and a first pull-down node reset circuit.
  • the first pull-down node charging circuit is coupled to the second clock signal terminal, the second voltage terminal, and the pull-down node, and configured to be responsive to the second clock signal provided by the second clock signal terminal Charging the pull-down node;
  • the first pull-down node reset circuit is coupled to the second voltage terminal, the pull-down node, the input circuit, and the pull-up node charging circuit, and configured to respond And the first input signal is used to perform pull-down reset on the pull-down node.
  • the shift register provided by an embodiment of the present disclosure further includes a second pull-down node reset circuit.
  • the second pull-down node reset circuit is connected to the pull-down node, the output terminal, and the second voltage terminal, and is configured to perform pull-down reset on the pull-down node under control of a level of the output terminal .
  • the shift register provided by an embodiment of the present disclosure further includes a second pull-down node charging circuit.
  • the second pull-down node charging circuit is coupled to the pull-down node and the reset terminal, and is configured to charge the pull-down node in response to a reset signal provided by the reset terminal.
  • the shift register provided by an embodiment of the present disclosure further includes a touch reset circuit.
  • the touch reset circuit is connected to the output end, the second voltage end, and the touch enable end, and is configured to respond to the touch enable signal provided by the touch enable end to The output is reset and noise-reduced.
  • the input circuit includes a first transistor.
  • a gate of the first transistor is configured to be coupled to the first control terminal to receive the first control signal, and a first pole of the first transistor is configured to be coupled to the first input terminal To receive the first input signal, the second pole of the first transistor is coupled to the pull-up node charging circuit.
  • the input circuit further includes a second transistor.
  • a gate of the second transistor is configured to be coupled to the second control terminal to receive a second control signal
  • a first pole of the second transistor is coupled to the pull-up node charging circuit
  • a second transistor is coupled to the second transistor The pole is configured to be coupled to the second input to receive the second input signal.
  • the first transistor and the second transistor are not turned on at the same time.
  • the output circuit includes a third transistor and a first storage capacitor.
  • a gate of the third transistor is connected to the pull-up node, a first pole of the third transistor is configured to be connected to the first clock signal terminal to receive the first clock signal, the third transistor The second pole is connected to the output.
  • the first pole of the first storage capacitor is connected to the pull-up node, and the second pole of the first storage capacitor is connected to the output end.
  • the pull-up node charging circuit includes a fourth transistor, a fifth transistor, and a second storage capacitor.
  • the gate of the fourth transistor is connected to the input circuit, the first pole of the fourth transistor is connected to the first voltage terminal, and the second pole of the fourth transistor is connected to the pull-up control node.
  • a gate of the fifth transistor is connected to the first voltage terminal, a first pole of the fifth transistor is connected to the pull-up control node, a second pole of the fifth transistor, and the pull-up node connection.
  • the first pole of the second storage capacitor is connected to the pull-up control node, and the second pole of the second storage capacitor is connected to the second voltage terminal.
  • the first pull-down node reset circuit includes a sixth transistor. a gate of the sixth transistor is connected to the input circuit and the pull-up node charging circuit, a first pole of the sixth transistor is connected to the pull-down node, and a second pole of the sixth transistor The second voltage terminal is connected.
  • the first pull-down node charging circuit includes a seventh transistor and a third storage capacitor.
  • the gate and the first pole of the seventh transistor are configured to be connected to the second clock signal terminal to receive the second clock signal, and the second pole of the seventh transistor is connected to the pull-down node.
  • the first pole of the third storage capacitor is connected to the pull-down node, and the second pole of the third storage capacitor is connected to the second voltage terminal.
  • the pull-up node resets the power
  • the road includes an eighth transistor.
  • the gate of the eighth transistor is connected to the pull-down node, the first pole of the eighth transistor is connected to the pull-up control node, and the second pole of the eighth transistor is connected to the second voltage terminal.
  • the output reset circuit includes a ninth transistor.
  • the gate of the ninth transistor is connected to the pull-down node, the first pole of the ninth transistor is connected to the output terminal, and the second pole of the ninth transistor is connected to the second voltage terminal.
  • the second pull-down node reset circuit includes a tenth transistor.
  • the gate of the tenth transistor is connected to the output terminal, the first pole of the tenth transistor is connected to the pull-down node, and the second pole of the tenth transistor is connected to the second voltage terminal.
  • the second pull-down node charging circuit includes an eleventh transistor.
  • the gate and the first pole of the eleventh transistor are configured to be connected to the reset terminal to receive the reset signal, and the second pole of the eleventh transistor is connected to the pull-down node.
  • the touch reset circuit includes a twelfth transistor.
  • a gate of the twelfth transistor is configured to be connected to the touch enable end to receive the touch enable signal, and a first pole of the twelfth transistor is connected to the output end, and the A second pole of the twelve transistors is coupled to the second voltage terminal.
  • At least one embodiment of the present disclosure also provides a gate driving circuit including a plurality of cascaded shift registers as in the embodiments of the present disclosure.
  • the first input of the remaining stages of shift registers is coupled to the output of the shift register of the previous stage.
  • At least one embodiment of the present disclosure also provides a gate driving circuit including a plurality of cascaded shift registers as in the embodiments of the present disclosure.
  • the first input of the remaining stages of the shift register is connected to the output of the shift register of the previous stage; except for the last stage shift register, the second stage of the shift register of the other stages The input is connected to the output of the next stage shift register.
  • At least one embodiment of the present disclosure further provides a display device including the gate driving circuit according to any one of the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure also provides a driving method of a shift register, comprising: a first stage, the input circuit is responsive to the first control signal to output the first input signal, The pull-up node charging circuit charges the pull-up node under control of the first input signal; in a second stage, the pull-up node charging circuit maintains a level of the pull-up node, the output The circuit outputs the first clock signal to the output terminal under the control of the level of the pull-up node.
  • At least one embodiment of the present disclosure also provides a driving method of a shift register, comprising: a first stage, the input circuit is responsive to the first control signal to output the first input signal, the pull-up node a charging circuit charging the pull-up node under control of the first input signal, the first pull-down node reset circuit responsive to the first input signal to perform pull-down reset on the pull-down node; a phase, the pull-up node charging circuit maintains a level of the pull-up node, and the output circuit outputs the first clock signal to the output terminal under the control of a level of the pull-up node; In a third stage, the first pull-down node charging circuit is configured to charge the pull-down node in response to the second clock signal, the pull-up node reset circuit is under the control of a level of the pull-down node, The pull-up node performs a pull-down reset, and the output reset circuit performs reset noise reduction on the output end under the control of the level of the pull-down node.
  • At least one embodiment of the present disclosure also provides a driving method of a shift register, including: when the first control signal is at a first level and the second control signal is at a second level, the shift register operates in a positive sweep mode; when the first control signal is the second level and the second control signal is the first level, the shift register operates in an anti-sweep mode. Wherein one of the first level and the second level is a high level and the other is a low level.
  • 1 is a circuit diagram of a shift register
  • FIG. 2 is a schematic block diagram of a shift register according to an example of an embodiment of the present disclosure
  • FIG. 3 is a schematic block diagram of a shift register according to another example of an embodiment of the present disclosure.
  • FIG. 4 is a schematic block diagram of a shift register according to still another example of an embodiment of the present disclosure.
  • FIG. 5 is a circuit diagram showing a specific implementation example of the shift register shown in FIG. 4;
  • Figure 6 is a signal timing diagram corresponding to the operation of the shift register shown in Figure 5;
  • Figure 7 is another signal timing diagram corresponding to the operation of the shift register shown in Figure 5;
  • FIG. 8 is a simulation of a gate drive circuit G1 composed of a plurality of cascaded shift registers as shown in FIG. 1 and a gate drive circuit G2 composed of a plurality of cascaded shift registers as shown in FIG. Waveform comparison chart;
  • FIG. 9 is a schematic circuit diagram of a shift register according to another embodiment of the present disclosure.
  • FIG. 10A is a schematic diagram of a simulation waveform of the shift register shown in FIG. 9; FIG.
  • 10B is a schematic diagram of a simulation waveform of the shift register shown in FIG. 5;
  • FIG. 11 is a schematic diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of another gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of still another gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 14 is a schematic block diagram of a display device according to an embodiment of the present disclosure.
  • the display panel in order to achieve low cost and narrow border, GOA (Gate can be used) Driver On Array technology, which integrates the gate drive circuit into the display panel through a thin film transistor process, thereby achieving advantages such as narrow bezel and reduced assembly cost.
  • the display panel may be a liquid crystal display (LCD) panel or an organic light emitting diode (OLED) display panel.
  • Figure 1 shows a circuit schematic of a shift register that can be cascaded to form a gate drive circuit.
  • the shift register adopts an 11T3C structure, that is, includes eleven transistors (T1 to T11) and three capacitors (C1, C2, and C3).
  • a forward scan (positive sweep) is taken as an example (for example, the first control terminal)
  • the CN is at a high level and the second control terminal CNB is at a low level
  • a positive sweep is implemented, and the high level input by the first control terminal CN charges the pull-up node PU.
  • the second control terminal CNB is at a low level, the voltage difference between the source and the drain of the second transistor T2 is large, and the pull-up node PU leaks through the second transistor T2, especially when the transistor has a large leakage current under high temperature conditions.
  • the pull-up node PU When the pull-up node PU has a drop, which causes a voltage drop at the output of the stage, and may even result in an output that does not meet the requirements.
  • the gate driving circuit is used in a TDDI (Touch and Display Driver Integration) product, after a touch scanning phase, the leakage current of the pull-up node PU is high under high temperature conditions.
  • the pull-up node PU has a large voltage drop, and the bootstrap voltage of the pull-up node PU cannot reach a higher level at the output of the current stage, thereby causing a voltage drop at the output of the current stage.
  • the voltage drop due to the pull-up node PU when a display panel is driven by the gate drive circuit formed by the shift register cascade shown in FIG. 1, the voltage drop due to the pull-up node PU, especially at a high temperature, causes a shift register. There is also a voltage drop in the output, which may cause problems such as poor display and poor high-temperature reliability.
  • At least one embodiment of the present disclosure provides a shift register including an input circuit, a pull-up node charging circuit, and an output circuit.
  • the input circuit is coupled to the first input terminal, the first control terminal, and the pull-up node charging circuit, and configured to output the first input signal provided by the first input terminal in response to the first control signal provided by the first control terminal .
  • the pull-up node charging circuit is coupled to the first voltage terminal, the second voltage terminal, the input circuit, and the pull-up node, and configured to charge the pull-up node and maintain the pull-up node under control of the first input signal Level.
  • the output circuit is connected to the pull-up node, the first clock signal terminal and the output terminal, and is configured to output the first clock signal provided by the first clock signal terminal to the output terminal under the control of the level of the pull-up node.
  • At least one embodiment of the present disclosure also provides a gate driving circuit, a display device, and a driving method corresponding to the shift register described above.
  • the shift register provided by at least one embodiment of the present disclosure, the driving method thereof, the gate driving circuit, and the display device can better maintain the level of the pull-up node PU, and reduce or eliminate the voltage drop of the pull-up node PU. Therefore, when the leakage current of the transistor is large under high temperature conditions, the output of the current stage has no normal voltage drop. At the same time, there is no output at other times than the output of this level, so as to avoid multiple output problems. Therefore, at least one embodiment of the present disclosure can solve the problem of display failure and the like when applied to a touch display product, and particularly has a significant improvement effect in terms of high temperature reliability.
  • One example of an embodiment of the present disclosure provides a shift register 100 that includes an input circuit 110, a pull-up node charging circuit 130, and an output circuit 120, as shown in FIG.
  • the input circuit 110 is coupled to the first input terminal IN1, the first control terminal CN, and the pull-up node charging circuit 130, and is configured to provide the first input terminal IN1 in response to the first control signal provided by the first control terminal CN.
  • the first input signal is output.
  • the input circuit 110 can be turned on under the control of the first control signal provided by the first control terminal CN, thereby outputting the first input signal provided by the first input terminal IN1 to the pull-up node charging circuit 130.
  • the input circuit 110 can also be connected to the second input terminal IN2 and the second control terminal CNB, so that bidirectional scanning (ie, forward scanning and reverse) can be implemented. To scan) function.
  • the input circuit 110 can also be configured to output a second input signal provided by the second input terminal IN2 in response to the second control signal provided by the second control terminal CNB.
  • the shift register 100 operates in the positive sweep mode; the first control signal is at the second level and the second control signal is the first power Normally, shift register 100 operates in an anti-sweep mode.
  • first level and the second level is a high level and the other is a low level.
  • first level may be a high level, for example, 3.3V to 5V
  • second level is a low level, for example, 0V to 0.4V.
  • Embodiments of the present disclosure include, but are not limited to, such an arrangement, for example, the first level may be a low level and the second level a high level. The following embodiments are the same as those described herein and will not be described again.
  • the pull-up node charging circuit 130 is coupled to the first voltage terminal VGH, the second voltage terminal VGL, the input circuit 110, and the pull-up node PU, and is configured to be under the control of the first input signal.
  • the pull-up node PU is charged and maintains the level of the pull-up node PU.
  • the pull-up node charging circuit 130 can electrically connect the first voltage terminal VGH and the pull-up node PU under the control of the first input signal, so that the first voltage terminal VGH inputs the first voltage (for example, a high level).
  • the pull-up node PU can be charged.
  • the pull-up node charging circuit 130 can maintain the level of the pull-up node PU better under the control of the first input signal, thereby making the output of the current stage normal without voltage drop.
  • the output circuit 120 is connected to the pull-up node PU, the first clock signal terminal CK and the output terminal OUT, and is configured to provide the first clock provided by the first clock signal terminal CK under the control of the level of the pull-up node PU.
  • the signal is output to the output terminal OUT.
  • the output circuit 120 can electrically connect the first clock signal terminal CK and the output terminal OUT under the control of the level of the pull-up node PU, so that the first clock signal input by the first clock signal terminal CK can be output to Output OUT.
  • the shift register 100 may further include a pull-down node control circuit 140, a pull-up node reset circuit 150, and an output reset circuit 160.
  • the pull-down node control circuit 140 is connected to the second clock signal terminal CKB, the second voltage terminal VGL, the pull-down node PD, the input circuit 110, and the pull-up node charging circuit 130, and is configured to be provided in response to the second clock signal terminal CKB.
  • the second clock signal or the first input signal output by the input circuit 110 controls the level of the pull-down node PD.
  • the pull-down node control circuit 140 can include a first pull-down node reset circuit 141 and a first pull-down node charging circuit 142.
  • the first pull-down node charging circuit 142 is connected to the second clock signal terminal CKB, the second voltage terminal VGL, and the pull-down node PD, and is configured to respond to the second clock signal provided by the second clock signal terminal CKB to the pull-down node.
  • the PD is charged.
  • the first pull-down node charging circuit 142 can be turned on under the control of the second clock signal provided by the second clock signal terminal CKB, so that the second clock signal terminal CKB and the pull-down node PD can be electrically connected, for example, When the second clock signal is a high level signal, the second clock signal can charge the pull-down node PD.
  • the first pull-down node reset circuit 141 is connected to the second voltage terminal VGL, the pull-down node PD, the input circuit 110, and the pull-up node charging circuit 130, and is configured to perform pull-down reset on the pull-down node PD in response to the first input signal.
  • the first pull-down node reset circuit 141 can electrically connect the pull-down node PD and the second voltage terminal VGL under the control of the first input signal output by the input circuit 110, for example, the second voltage terminal VGL maintains the input DC low voltage.
  • the signal is flat so that the pull-down node PD can be pulled down and reset.
  • first voltage terminal VGH in the embodiment of the present disclosure maintains, for example, an input DC high level signal, and the DC high level is referred to as a first voltage; and the second voltage terminal VGL maintains an input DC low level, for example.
  • the signal which is referred to as the second voltage.
  • the pull-up node reset circuit 150 is connected to the pull-down node PD, the second voltage terminal VGL, and the pull-up node charging circuit 130, and is configured to be under the control of the level of the pull-down node PD.
  • the pull node PU performs a pull-down reset.
  • the pull-up node reset circuit 150 can be turned on under the control of the level of the pull-down node PD, while the pull-up node charging circuit 130 causes the pull-up node PU and the pull-up node reset circuit 150 to be electrically controlled under the control of the first voltage.
  • the connection is such that the pull-up node PU and the second voltage terminal VGL are electrically connected, and the second voltage terminal VGL can perform pull-down reset on the pull-up node PU.
  • the output reset circuit 160 is connected to the output terminal OUT, the pull-down node PD, and the second voltage terminal VGL, and is configured to perform reset noise reduction on the output terminal OUT under the control of the level of the pull-down node PD.
  • the output reset circuit 160 can electrically connect the output terminal OUT and the second voltage terminal VGL under the control of the level of the pull-down node PD, so that the low level input by the second voltage terminal VGL can reset the output terminal OUT. Noise reduction.
  • the shift register 100 may further include a second pull-down node reset circuit 170.
  • the second pull-down node reset circuit 170 is connected to the pull-down node PD, the output terminal OUT, and the second voltage terminal VGL, and is configured to perform pull-down reset on the pull-down node PD under the control of the level of the output terminal OUT.
  • the second pull-down node reset circuit 170 can electrically connect the pull-down node PD and the second voltage terminal VGL under the control of the level of the output terminal OUT, so that the second voltage terminal VGL can perform pull-down reset on the pull-down node PD. In this way, the output terminal OUT of the shift register 100 can be pulled down and reset by the pull-down node PD when the normal output is performed, and the normal output of the output terminal OUT can be further ensured.
  • the shift register 100 may further include a second pull-down node charging circuit 180.
  • the second pull-down node charging circuit 180 is connected to the pull-down node PD and the reset terminal Reset, and is configured to charge the pull-down node PD in response to a reset signal provided by the reset terminal Reset.
  • the second pull-down node charging circuit 180 can be turned on under the control of the reset signal, so that the reset terminal Reset and the pull-down node PD are electrically connected, for example, the reset signal can be a high level signal.
  • the high level reset signal can charge the pull-down node PD to increase the potential of the pull-down node PD.
  • the pull-up node reset circuit 150 and the output reset circuit 160 can be turned on under the control of the high level of the pull-down node PD, thereby further implementing the reset operation of the pull-up node PU and the output terminal OUT.
  • a plurality of cascaded shift registers 100 can be used to form a gate driving circuit. When the display panel is driven by the gate driving circuit, it can be simultaneously turned into the gate driving circuit when the display panel is powered on.
  • the shift registers of each stage provide a reset signal to simultaneously perform a reset operation on the pull-up node PU and the output terminal OUT in the shift registers of each stage, thereby realizing the initialization of the entire gate drive circuit.
  • the shift register 100 may further include a touch reset circuit 190.
  • the touch reset circuit 190 is connected to the output terminal OUT, the second voltage terminal VGL, and the touch enable terminal EN_Touch, and is configured to respond to the touch enable signal provided by the touch enable terminal EN_Touch to perform the output terminal OUT.
  • Reset noise reduction For example, the touch reset circuit 190 can be turned on under the control of the touch enable signal, so that the output terminal OUT and the second voltage terminal are electrically connected, so that the low level signal input by the second voltage terminal can be performed on the output terminal OUT.
  • Reset noise reduction For example, a plurality of cascaded shift registers 100 may be used to form a gate driving circuit.
  • the touch enable signal is generated to reset and reduce the noise of the output terminals OUT of the shift registers of each stage to avoid display failure and interference between the display operation and the touch operation.
  • the shift register 100 provided by the embodiment of the present disclosure can make the level of the pull-up node PU better maintained, reduce the voltage drop of the pull-up node PU, and thus make the output of the current stage when the transistor leakage current is large under high temperature conditions. Normal no pressure drop. It solves the problem of poor display, especially in terms of high temperature reliability, and has obvious improvement effect.
  • the shift register 100 shown in FIG. 4 can be embodied in one example as the circuit structure shown in FIG. As shown in FIG. 5, the shift register 100 includes first to twelfth transistors T1-T12 and a first storage capacitor C1, a second storage capacitor C2, and a third storage capacitor C3.
  • the input circuit 110 can be implemented to include a first transistor T1 and a second transistor T2.
  • the gate of the first transistor T1 is configured to be connected to the first control terminal CN to receive the first control signal, and the first pole configuration of the first transistor T1
  • the second pole of the first transistor T1 and the pull-up node charging circuit 130 are connected to output the first input signal to the pull-up node charging circuit 130.
  • the gate of the second transistor T2 is configured to be connected to the second control terminal CNB to receive the second control signal, and the second electrode of the second transistor T2 is configured to be coupled to the second input terminal IN2 to receive the second input signal, the second transistor The first pole of T2 is coupled to the pull-up node charging circuit 130 to output a second input signal to the pull-up node charging circuit 130.
  • the first transistor T1 and the second transistor T2 are not turned on at the same time.
  • the first transistor T1 can be turned on under the control of the first control signal (when the second transistor T2 is in the off state), thereby outputting the first input signal to the pull-up.
  • Node charging circuit 130 when the shift register 100 operates in the anti-sweep mode, the second transistor T2 can be turned on under the control of the second control signal (when the first transistor T1 is in the off state), so that the second input signal can be output.
  • the node charging circuit 130 is pulled up.
  • the switching of the positive sweep and the reverse sweep mode can be achieved by the cooperation of the first control signal and the second control signal.
  • the input circuit 110 may not include the second transistor T2 in the case where the bidirectional scanning is not required, which is not limited by the embodiment of the present disclosure.
  • the output circuit 120 can be implemented to include a third transistor T3 and a first storage capacitor C1.
  • the gate of the third transistor T3 is connected to the pull-up node PU, the first pole of the third transistor T3 is configured to be connected to the first clock signal terminal CK to receive the first clock signal, and the second pole and the output end of the third transistor T3 OUT connection.
  • the first pole of the first storage capacitor C1 is connected to the pull-up node PU, and the second pole of the first storage capacitor C1 is connected to the output terminal OUT.
  • the pull-up node charging circuit 130 can be implemented to include a fourth transistor T4, a fifth transistor T5, and a second storage capacitor C2.
  • the gate of the fourth transistor T4 is connected to the input circuit 110, the first pole of the fourth transistor T4 is connected to the first voltage terminal VGH to receive the first voltage, and the second pole of the fourth transistor T4 is connected to the pull-up control node PU_CN.
  • the gate of the fifth transistor T5 is connected to the first voltage terminal VGH to receive the first voltage and remains normally open, the first pole of the fifth transistor T5 is connected to the pull-up control node PU_CN, and the second pole of the fifth transistor T5 is connected to Pull the node PU connection.
  • the first pole of the second storage capacitor C2 is connected to the pull-up control node PU_CN, and the second pole of the second storage capacitor C2 is connected to the second voltage terminal VGL.
  • the first pull-down node reset circuit 141 can be implemented as a sixth transistor T6.
  • the gate of the sixth transistor T6 is connected to the input circuit 110 and the pull-up node charging circuit 130.
  • the first electrode of the sixth transistor T6 is connected to the pull-down node PD, and the second and second voltage terminals of the sixth transistor T6 are connected. VGL connection.
  • the first pull-down node charging circuit 142 can be implemented to include a seventh transistor T7 and a third storage capacitor C3.
  • the gate and the first electrode of the seventh transistor T7 are configured to be connected to the second clock signal terminal CKB to receive the second clock signal, and the second electrode of the seventh transistor T7 is connected to the pull-down node PD.
  • the first pole of the third storage capacitor is connected to the pull-down node, and the second pole of the third storage capacitor is connected to the second voltage terminal.
  • the pull-up node reset circuit 150 can be implemented as an eighth transistor T8.
  • the gate of the eighth transistor T8 is connected to the pull-down node PD, the first pole of the eighth transistor T8 and the pull-up control node are connected to PU_CN, and the second pole of the eighth transistor T8 is connected to the second voltage terminal VGL.
  • the output reset circuit 160 can be implemented as a ninth transistor T9.
  • the gate of the ninth transistor T9 is connected to the pull-down node PD, the first pole of the ninth transistor T9 is connected to the output terminal OUT, and the second pole of the ninth transistor T9 is connected to the second voltage terminal VGL.
  • the second pull-down node reset circuit 170 can be implemented as a tenth transistor T10.
  • the gate of the tenth transistor T10 is connected to the output terminal OUT, the first electrode of the tenth transistor T10 is connected to the pull-down node PD, and the second electrode of the tenth transistor T10 is connected to the second voltage terminal VGL.
  • the second pull-down node charging circuit 180 can be implemented as the eleventh transistor T11.
  • the gate and the first electrode of the eleventh transistor T11 are configured to be connected to the reset terminal Reset to receive a reset signal, and the second electrode of the eleventh transistor T11 is connected to the pull-down node PD.
  • the touch reset circuit 190 can be implemented as the twelfth transistor T12.
  • the gate of the twelfth transistor T12 is configured to be connected to the touch enable terminal EN_Touch to receive the touch enable signal, the first pole of the twelfth transistor T12 is connected to the output terminal OUT, and the second pole of the twelfth transistor T12 is connected. Connected to the second voltage terminal VGL.
  • the transistors used in the embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other switching device having the same characteristics.
  • a thin film transistor is taken as an example for description.
  • the source and drain of the transistor used here may be structurally symmetrical, so that the source and the drain may be structurally indistinguishable.
  • the embodiment of the present disclosure in order to distinguish the two poles of the transistor except the gate, one of the first poles and the other pole are directly described.
  • the transistors in the embodiments of the present disclosure are all described by taking an N-type transistor as an example.
  • the first electrode may be a drain and the second electrode may be a source.
  • the present disclosure includes but is not limited thereto.
  • one or more of the shift registers provided by embodiments of the present disclosure The transistor may also be a P-type transistor.
  • the first pole may be the source and the second pole may be the drain.
  • the polarity of each pole of the selected type of transistor is only required according to the embodiment in the present disclosure. The polarity of each pole of the transistor can be connected accordingly.
  • the transistors in the shift register 100 each adopt an N-type transistor, the first voltage terminal VGH maintains a first voltage input to a DC high level, and the second voltage terminal VGL maintains an input DC low level.
  • the second voltage, the first clock signal terminal CK inputs a first clock signal, and the second clock signal terminal CKB inputs a second clock signal different from the first clock signal.
  • the first control terminal CN inputs a first control signal of a high level
  • the second control terminal CNB inputs a second control signal of a low level
  • the operation principle of the shift register 100 shown in FIG. 5 will be described with reference to the signal timing diagram shown in FIG. 6.
  • the shift register 100 performs the following operations.
  • the first input terminal IN1 inputs a high level
  • the first clock signal terminal CK inputs a low level
  • the second clock signal terminal CKB inputs a high level. Since the first transistor T1 remains turned on, the first input signal of the high level input by the first input terminal IN1 can be transmitted to the gate of the pull-up node charging circuit 130, that is, the gate of T4 of the fourth transistor, through the first transistor T1.
  • the fourth transistor T4 is turned on, and the high level input by the first voltage terminal VGH can charge the second storage capacitor C2 through the fourth transistor T4, that is, the pull-up control node PU_CN is charged.
  • the fifth transistor T5 since the fifth transistor T5 is kept on, the high level input by the first voltage terminal VGH can also charge the first storage capacitor C1 through the fifth transistor T5, that is, the pull-up node PU is charged, so that the pull-up is performed.
  • the potential of the node PU is pulled up to a first high level. Since the pull-up node PU is at a high level, the third transistor T3 is turned on, thereby outputting the low level input by the first clock signal signal terminal CK to the output terminal OUT.
  • the seventh transistor T7 is turned on, so that the second clock signal can charge the third storage capacitor C3, that is, to the pull-down node PD. Charge it.
  • the sixth transistor T6 is turned on by the first input signal of the high level, so the low level signal input by the second voltage terminal VGL is pulled down to the pull-down node PD.
  • the sixth transistor T6 and the seventh transistor T7 can be configured (for example, the size ratio of the two, the threshold voltage, etc.). When both T6 and T7 are turned on, the level of the pull-down node PD can be Stay low without being pulled up.
  • the first input terminal IN1 inputs a low level
  • the first clock signal terminal CK inputs a high level
  • the second clock signal terminal CKB inputs a low level. Since the first transistor T1 remains on, the first input signal of the low level input by the first input terminal IN1 can be transmitted to the gates of the fourth transistor T4 and the sixth transistor T6 through the first transistor T1, thereby making the fourth The transistor T4 and the sixth transistor T6 are turned off. Since the second clock signal terminal CKB is input to a low level, the seventh transistor T7 is turned off, that is, the charging path of the pull-down node PD is turned off, and the pull-down node PD can maintain the low level of the previous stage.
  • the pull-up node PU maintains a high level, so that the third transistor T3 continues to be turned on. Since the first clock signal terminal CK inputs a high level at this stage, the output terminal OUT outputs the high level signal. Due to the bootstrap effect of the first storage capacitor C1, the potential of the pull-up node PU is further pulled high to reach the second high level, so that the conduction of the third transistor T3 is more sufficient.
  • the fourth transistor T4 is turned off, and there is no voltage difference across the first pole and the second pole (ie, the source and drain poles) of the second transistor T2, which can reduce the leakage current of the pull-up node PU due to the transistor.
  • the resulting voltage drop can also cause the bootstrap voltage of the pull-up node PU to reach a higher level, thereby ensuring the normal output of the output terminal OUT.
  • the first input terminal IN1 still inputs a low level
  • the first clock signal terminal CK inputs a low level
  • the second clock signal terminal CKB inputs a high level.
  • the fourth transistor T4 and the sixth transistor T6 remain off. Since the second clock signal terminal CKB is input to the high level, the seventh transistor T7 is turned on, so the second clock signal of the high level can charge the third storage capacitor C3 through the seventh transistor T7, that is, the pull-down node PD is charged. The potential of the pull-down node PD is pulled up to a high level.
  • the eighth transistor T8 Since the pull-down node PD is at a high level, the eighth transistor T8 is turned on, and the first storage capacitor C1 and the second storage capacitor C2 can be discharged by the eighth transistor T8, so that the pull-up control node PU_CN and the pull-up node PU can be realized. Pulldown reset. Similarly, the ninth transistor T9 is also turned on, thereby achieving a pull-down reset of the output terminal OUT.
  • a plurality of cascaded shift registers 100 as shown in FIG. 5 may be used to form a gate driving circuit.
  • the display panel When the display panel is driven by the gate driving circuit, the display panel may be powered on simultaneously.
  • Each stage shift register 100 in the gate drive circuit provides a high level reset signal.
  • the reset signal causes the eleventh transistor T11 to be turned on, thereby the reset signal of the high level
  • the pull-down node PD may be charged by the eleventh transistor T11 to pull up the potential of the pull-down node PD to a high level.
  • the eighth transistor T8 and the ninth transistor T9 are turned on, so that the pull-up node PU and the output terminal in the shift register 100 can be simultaneously realized. OUT performs a reset operation.
  • the gate driving circuit when the gate driving circuit is used in a TDDI (Touch and Display Driver Integration) product, for example, when the touch scanning phase is entered, a touch enable signal is generated, and the touch enable is enabled.
  • the signal can turn on the twelfth transistor T12, so that the output terminal OUT of each stage shift register can be reset and noise-reduced to avoid display failure.
  • timing signals on the first clock signal terminal CK and the second clock signal terminal CKB shown in FIG. 6 are exemplified by a 50% duty signal, and embodiments of the present disclosure include Not limited to this, for example, a timing signal of 25% duty ratio shown in FIG. 7 can also be employed. The corresponding other timing signals are shown in Figure 7, and will not be described here.
  • the shift register 100 provided by the embodiment of the present disclosure includes 12 transistors and 3 capacitors.
  • the shift register (11 transistors and 3 capacitors) shown in FIG. 1 by adding a transistor T4, And changing the connection manner of the first transistor T1 and the second transistor T2, the level of the pull-up node PU can be better maintained, the voltage drop of the pull-up node PU is lowered, and then the transistor leakage current is high under high temperature conditions. Make the output of this stage normal without pressure drop. At the same time, there is no output at other times than the output of this level, so as to avoid multiple output problems. It solves the problem of poor display, especially in terms of high temperature reliability, and has obvious improvement effect.
  • a plurality of cascaded shift registers as shown in FIG. 1 constitute a gate driving circuit, and the gate driving circuit is referred to as G1; similarly, a plurality of cascaded shift registers as shown in FIG. 5 are employed.
  • a gate driving circuit is formed, and the gate driving circuit is referred to as G2. The following embodiments are the same as those described herein and will not be described again.
  • the bootstrap voltage of the pull-up node PU of the shift register in G1 is higher than the pull-up node of the shift register in G2.
  • the bootstrap voltage of the PU is low.
  • the bootstrap voltage drop of the pull-up node PU of the shift register shown in FIG. Bootstrapping of the pull-up node PU of the shift register 100 shown in FIG. The voltage drop is 3V smaller.
  • the bootstrap voltage of the pull-up node PU drops to 6V, so that the third transistor T3 cannot be fully turned on, and thus the output of the shift register of the latter stage of the touch is pressed. Drop (1.5V).
  • the bootstrap voltage drop of the pull-up node PU is smaller than G1, so that the output of the stage can be made without voltage drop.
  • the shift register in G2 has basically no voltage drop (maintaining 3.8V in the normal case, basically before the touch) In the case of the first level, the 0.23V is kept basically unchanged).
  • the shift register in G1 has a voltage drop (1.2V) at the hold voltage of the pull-up node PU at Normal.
  • the voltage drop of the pull-up node PU of the shift register in G2 It is 1.7V smaller than that in G1, that is, the holding voltage of the pull-up node PU of the shift register in G2 is better than G1, thus facilitating the output of the shift register of the latter stage after the touch.
  • the first control terminal CN is at a high level due to the positive sweep, and the second control terminal CNB is at a low level when the current pull-up node PU is charged.
  • the voltage difference between the source and the drain of T2 is large, and the pull-up node PU will leak through the second transistor T2.
  • the pull-up node PU will have a voltage drop, which leads to the present.
  • the stage output has a voltage drop.
  • the bootstrap voltage and output of the pull-up node PU are greatly improved.
  • the pull-up node PU is at a high level, and when the shift register of the current stage is output, the fourth transistor T4 is turned off, and the second transistor is at this time.
  • the source-drain diode of T2 has no voltage difference, which can reduce the voltage drop caused by the leakage current of the pull-up node PU due to the leakage current of the transistor, and can make the bootstrap voltage of the pull-up node PU in the shift register of the touch one stage higher. The level of the output can thus ensure the normal output of the output OUT.
  • the shift register provided by the embodiment of the present disclosure has no output at other times than the output of the current stage, thereby avoiding multiple output problems.
  • the shift register in which the connection manner of the first transistor T1 and the second transistor T2 is not changed is as shown in FIG.
  • the shift shown in FIG. 9 is known.
  • the bit register when the leakage current of the transistor is large under high temperature conditions, can be seen from the simulation waveform shown in FIG. 10A, there is a Multi (multiple) output problem at the output terminal OUT.
  • the first control terminal CN is at a high level, and at other times than the output of the current stage, the off current Ioff is large due to the large voltage difference between the source and the drain of the first transistor T1, so The four-transistor T4 cannot be completely turned off, and the high-level signal input from the first voltage terminal VGH charges the pull-up node PU through the fourth transistor T4 and the fifth transistor T5, so that the potential of the pull-up node PU is raised, thereby
  • the shift register has multiple output problems.
  • the shift register provided by the embodiment of the present disclosure can make the level of the pull-up node PU better by adding one transistor (fourth transistor T4) and by changing the connection manner of the first transistor T1 and the second transistor T2.
  • the ground maintains, reducing the voltage drop of the pull-up node PU, and then the output of the current stage has no normal voltage drop when the transistor leakage current is large under high temperature conditions.
  • there is no output at other times than the output of this level so as to avoid multiple output problems. Solved the display failure, etc.
  • the problem, especially in terms of high temperature reliability, has a significant improvement effect.
  • At least one embodiment of the present disclosure provides a gate driving circuit 10, as shown in FIGS. 11, 12, and 13, the gate driving circuit 10 includes a plurality of cascaded shift registers 100, the shift register 100 The shift register 100 provided in the above embodiment can be employed.
  • the gate driving circuit 10 can be directly integrated on the array substrate of the display device by using the same process as the thin film transistor to realize the progressive scan driving function.
  • the first input terminals of the remaining stages of shift registers IN1 is connected to the output OUT of the upper shift register.
  • the first input IN1 of the first stage shift register can be configured to receive the trigger signal STV.
  • the gate drive circuit shown in FIG. 11 cannot achieve bidirectional scanning.
  • the shift register 100 includes the second input terminal IN2 and the second control terminal CNB, except for the first stage shift register
  • the first input terminal IN1 of the remaining stages of shift registers It is connected to the output terminal OUT of the shift register of the upper stage
  • the second input terminal IN2 of the shift registers of the other stages is connected with the output terminal OUT of the shift register of the next stage, except for the last stage shift register.
  • the first input IN1 of the first stage shift register and the second input IN2 of the last stage shift register may be configured to receive the trigger signal STV.
  • the gate drive circuit shown in Figure 12 can implement bidirectional scanning.
  • the reset terminal Reset of each stage shift register 100 can be connected, for example, to the clock controller 200 to receive the reset signal RST.
  • the reset signal RST can be simultaneously supplied to the shift registers 100 in the gate driving circuit 10 when the display panel is powered on. Initialization of the entire gate drive circuit 10 is achieved.
  • the gate driving circuit 10 when used to drive a display panel, the gate driving circuit 10 may be disposed on one side of the display panel in one example.
  • the display panel includes 2N row gate lines 300 (N is an integer greater than zero), and the output terminals OUT of the shift registers 100 in the gate driving circuit 10 may be configured to sequentially and the 2N row gate lines 300 ( As shown in Figures 11 and 12, the 1, 2, ..., 2N-1, 2N marks, N is an integer greater than zero) connection for outputting a progressive scan signal.
  • two system clock signals CLK1 can be passed.
  • CLK2 supplies a clock signal to the clock signal terminals (the first clock signal terminal CK and the second clock signal terminal CKB) in each shift register 100.
  • the first clock signal terminal CK of the first stage shift register 100 is input to CLK2
  • the second clock signal terminal CKB is input to CLK1.
  • the first clock signal terminal CK of the second stage shift register 100 is input to CLK1, and the second clock signal terminal is CKB.
  • the gate driving circuit 10 may be symmetrically disposed on both sides of the display panel, so that two The output terminal OUT in the gate driving circuit 10 is connected to both ends of the corresponding gate line, thereby achieving bilateral driving.
  • the bilateral driving method can be applied to driving a large-sized display panel to solve the problem of large load on the gate line.
  • a gate driving circuit 10 may be disposed on one side of the display panel for driving gates of odd rows.
  • the line is simultaneously provided with another gate drive circuit 10 on the other side of the display panel for driving the gate lines of the even rows.
  • CLK1 and CLK2 can use a 25% duty cycle timing signal.
  • the gate driving circuit 10 may further include a timing controller 200.
  • the timing controller 200 is configured, for example, to provide clock signals (CLK1, CLK2) to the shift registers 100 of the stages, and the timing controller 200 can also be configured to provide the trigger signal STV, the reset signal RST, and the touch enable signal.
  • At least one embodiment of the present disclosure also provides a display device 1, as shown in FIG. 14, which includes any of the gate drive circuits 10 provided in the above embodiments.
  • the display device in this embodiment may be: a liquid crystal panel, a liquid crystal television, a display, an OLED panel, an OLED television, an electronic paper, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigation device, etc., having any display function.
  • the display device 1 may further include other conventional components such as a display panel, and embodiments of the present disclosure are not limited thereto.
  • At least one embodiment of the present disclosure also provides a driving method that can be used to drive the shift register 100 provided in the embodiments of the present disclosure.
  • the driving method includes the following operations.
  • the input circuit 110 outputs the first input signal in response to the first control signal, and the pull-up node charging circuit 130 charges the pull-up node PU under the control of the first input signal, and the first pull-down node is reset.
  • the circuit 141 is responsive to the first input signal to perform a discharge reset on the pull down node PU.
  • the pull-up node charging circuit 130 maintains the level of the pull-up node PU, and the output circuit 120 outputs the first clock signal to the output terminal OUT under the control of the level of the pull-up node PU.
  • the first pull-down node charging circuit 142 charges the pull-down node PD in response to the second clock signal, and the pull-up node reset circuit 150 performs the pull-up node PU under the control of the level of the pull-down node PD.
  • the output reset circuit 160 resets and denoises the output terminal OUT under the control of the level of the pull-down node PD.
  • one of the first clock signal and the second clock signal is a high level signal, and the other is a low level signal.
  • At least one embodiment of the present disclosure also provides a driving method that can be used to drive a shift register 100 including a second input terminal IN2 and a second control terminal CNB in an embodiment of the present disclosure.
  • the driving method includes the following operations.
  • the shift register 100 When the first control signal is at the first level and the second control signal is at the second level, the shift register 100 operates in the positive sweep mode.
  • the shift register 100 When the first control signal is at the second level and the second control signal is at the first level, the shift register 100 operates in the reverse sweep mode.
  • one of the first level and the second level is a high level and the other is a low level.

Abstract

一种移位寄存器(100)及其驱动方法、栅极驱动电路(10)、显示装置(1)。移位寄存器(100)包括输入电路(110)、上拉节点充电电路(130)和输出电路(120)。输入电路(110)和第一输入端(IN1)、第一控制端(CN)以及上拉节点充电电路(130)连接，且被配置为响应于第一控制端(CN)提供的第一控制信号以将第一输入端(IN1)提供的第一输入信号输出。上拉节点充电电路(130)和第一电压端(VGH)、第二电压端(VGL)、输入电路(110)以及上拉节点(PU)连接，且被配置为在第一输入信号的控制下，对上拉节点(PU)进行充电并保持上拉节点(PU)的电平。输出电路(120)和上拉节点(PU)、第一时钟信号端(CK)以及输出端(OUT)连接，且被配置为在上拉节点(PU)的电平的控制下，将第一时钟信号端(CK)提供的第一时钟信号输出至输出端(OUT)。

Description

移位寄存器及其驱动方法、栅极驱动电路、显示装置
本申请要求于2017年5月16日递交的中国专利申请第201710344494.9号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开实施例涉及一种移位寄存器及其驱动方法、栅极驱动电路、显示装置。
背景技术
在显示技术领域，例如液晶显示的像素阵列通常包括多行栅线和与之交错的多列数据线。对栅线的驱动可以通过贴附的集成驱动电路芯片实现。近几年，随着非晶硅薄膜工艺的不断提高，也可以将栅线驱动电路直接集成在薄膜晶体管阵列基板上构成GOA(Gate driver On Array)来对栅线进行驱动。
例如，可以采用由多个级联的移位寄存器构成的GOA为像素阵列的多行栅线提供开关态电压信号，从而控制多行栅线依序打开，并由数据线向像素阵列中对应行的像素单元提供数据信号，以形成显示图像的各灰阶所需要的灰度电压，进而显示每一帧图像。
发明内容
本公开至少一实施例提供一种移位寄存器，包括输入电路、上拉节点充电电路和输出电路。所述输入电路和第一输入端、第一控制端以及所述上拉节点充电电路连接，且被配置为响应于所述第一控制端提供的第一控制信号以将所述第一输入端提供的第一输入信号输出；所述上拉节点充电电路和第一电压端、第二电压端、所述输入电路以及上拉节点连接，且被配置为在所述第一输入信号的控制下，对所述上拉节点进行充电并保持所述上拉节点的电平；所述输出电路和所述上拉节点、第一时钟信号端以及输出端连接，且被配置为在所述上拉节点的电平的控制下，将所述第一时 钟信号端提供的第一时钟信号输出至所述输出端。
例如，本公开一实施例提供的移位寄存器还包括下拉节点控制电路、输出复位电路和上拉节点复位电路。所述下拉节点控制电路和第二时钟信号端、所述第二电压端、下拉节点、所述输入电路以及所述上拉节点充电电路连接，且被配置为响应于所述第二时钟信号端提供的第二时钟信号或所述第一输入信号以控制所述下拉节点的电平；所述上拉节点复位电路和所述下拉节点、所述第二电压端以及所述上拉节点充电电路连接，且被配置为在所述下拉节点的电平的控制下，对所述上拉节点进行下拉复位；所述输出复位电路和所述输出端、所述下拉节点以及所述第二电压端连接，且被配置为在所述下拉节点的电平的控制下，对所述输出端进行复位降噪。
例如，在本公开一实施例提供的移位寄存器中，所述下拉节点控制电路包括第一下拉节点充电电路和第一下拉节点复位电路。所述第一下拉节点充电电路和所述第二时钟信号端、所述第二电压端以及所述下拉节点连接，且被配置为响应于所述第二时钟信号端提供的第二时钟信号以对所述下拉节点进行充电；所述第一下拉节点复位电路和所述第二电压端、所述下拉节点、所述输入电路以及所述上拉节点充电电路连接，且被配置为响应于所述第一输入信号以对所述下拉节点进行下拉复位。
例如，本公开一实施例提供的移位寄存器还包括第二下拉节点复位电路。所述第二下拉节点复位电路和所述下拉节点、所述输出端以及所述第二电压端连接，且被配置为在所述输出端的电平的控制下，对所述下拉节点进行下拉复位。
例如，本公开一实施例提供的移位寄存器还包括第二下拉节点充电电路。所述第二下拉节点充电电路和所述下拉节点以及复位端连接，且被配置为响应于所述复位端提供的复位信号以对所述下拉节点进行充电。
例如，本公开一实施例提供的移位寄存器还包括触控复位电路。所述触控复位电路和所述输出端、所述第二电压端以及触控使能端连接，且被配置为响应于所述触控使能端提供的触控使能信号以对所述输出端进行复位降噪。
例如，在本公开一实施例提供的移位寄存器中，所述输入电路包括第一晶体管。所述第一晶体管的栅极配置为和所述第一控制端连接以接收所述第一控制信号，所述第一晶体管的第一极配置为和所述第一输入端连接 以接收第一输入信号，所述第一晶体管的第二极和所述上拉节点充电电路连接。
例如，在本公开一实施例提供的移位寄存器中，所述输入电路还包括第二晶体管。所述第二晶体管的栅极配置为和第二控制端连接以接收第二控制信号，所述第二晶体管的第一极和所述上拉节点充电电路连接，所述第二晶体管的第二极配置为和第二输入端连接以接收第二输入信号。其中，所述第一晶体管和第二晶体管不同时开启。
例如，在本公开一实施例提供的移位寄存器中，所述输出电路包括第三晶体管和第一存储电容。所述第三晶体管的栅极和所述上拉节点连接，所述第三晶体管的第一极配置为和所述第一时钟信号端连接以接收所述第一时钟信号，所述第三晶体管的第二极和所述输出端连接。所述第一存储电容的第一极和所述上拉节点连接，所述第一存储电容的第二极和所述输出端连接。
例如，在本公开一实施例提供的移位寄存器中，所述上拉节点充电电路包括第四晶体管、第五晶体管和第二存储电容。所述第四晶体管的栅极和所述输入电路连接，所述第四晶体管的第一极和第一电压端连接，所述第四晶体管的第二极和上拉控制节点连接。所述第五晶体管的栅极和所述第一电压端连接，所述第五晶体管的第一极和所述上拉控制节点连接，所述第五晶体管的第二极和所述上拉节点连接。所述第二存储电容的第一极和所述上拉控制节点连接，所述第二存储电容的第二极和所述第二电压端连接。
例如，在本公开一实施例提供的移位寄存器中，所述第一下拉节点复位电路包括第六晶体管。所述第六晶体管的栅极和所述输入电路以及所述上拉节点充电电路连接，所述第六晶体管的第一极和所述下拉节点连接，所述第六晶体管的第二极和所述第二电压端连接。
例如，在本公开一实施例提供的移位寄存器中，所述第一下拉节点充电电路包括第七晶体管和第三存储电容。所述第七晶体管的栅极和第一极配置为与所述第二时钟信号端连接以接收所述第二时钟信号，所述第七晶体管的第二极和所述下拉节点连接。所述第三存储电容的第一极和所述下拉节点连接，所述第三存储电容的第二极和所述第二电压端连接。
例如，在本公开一实施例提供的移位寄存器中，所述上拉节点复位电 路包括第八晶体管。所述第八晶体管的栅极和所述下拉节点连接，所述第八晶体管的第一极和上拉控制节点连接，所述第八晶体管的第二极和所述第二电压端连接。
例如，在本公开一实施例提供的移位寄存器中，所述输出复位电路包括第九晶体管。所述第九晶体管的栅极和所述下拉节点连接，所述第九晶体管的第一极和所述输出端连接，所述第九晶体管的第二极和所述第二电压端连接。
例如，在本公开一实施例提供的移位寄存器中，所述第二下拉节点复位电路包括第十晶体管。所述第十晶体管的栅极和所述输出端连接，所述第十晶体管的第一极和所述下拉节点连接，所述第十晶体管的第二极和所述第二电压端连接。
例如，在本公开一实施例提供的移位寄存器中，所述第二下拉节点充电电路包括第十一晶体管。所述第十一晶体管的栅极和第一极配置为与所述复位端连接以接收所述复位信号，所述第十一晶体管的第二极和所述下拉节点连接。
例如，在本公开一实施例提供的移位寄存器中，所述触控复位电路包括第十二晶体管。所述第十二晶体管的栅极配置为和所述触控使能端连接以接收所述触控使能信号，所述第十二晶体管的第一极和所述输出端连接，所述第十二晶体管的第二极和所述第二电压端连接。
本公开至少一实施例还提供一种栅极驱动电路，包括多个级联的如本公开实施例所述的移位寄存器。除第一级移位寄存器外，其余各级移位寄存器的第一输入端和上一级移位寄存器的输出端连接。
本公开至少一实施例还提供一种栅极驱动电路，包括多个级联的如本公开实施例所述的移位寄存器。除第一级移位寄存器外，其余各级移位寄存器的第一输入端和上一级移位寄存器的输出端连接；除最后一级移位寄存器外，其余各级移位寄存器的第二输入端和下一级移位寄存器的输出端连接。
本公开至少一实施例还提供一种显示装置，包括本公开任一实施例所述的栅极驱动电路。
本公开至少一实施例还提供一种移位寄存器的驱动方法，包括：第一阶段，所述输入电路响应于所述第一控制信号以将所述第一输入信号输出， 所述上拉节点充电电路在所述第一输入信号的控制下对所述上拉节点进行充电；第二阶段，所述上拉节点充电电路保持所述上拉节点的电平，所述输出电路在所述上拉节点的电平的控制下，将所述第一时钟信号输出至所述输出端。
本公开至少一实施例还提供一种移位寄存器的驱动方法，包括：第一阶段，所述输入电路响应于所述第一控制信号以将所述第一输入信号输出，所述上拉节点充电电路在所述第一输入信号的控制下对所述上拉节点进行充电，所述第一下拉节点复位电路响应于所述第一输入信号以对所述下拉节点进行下拉复位；第二阶段，所述上拉节点充电电路保持所述上拉节点的电平，所述输出电路在所述上拉节点的电平的控制下，将所述第一时钟信号输出至所述输出端；第三阶段，所述第一下拉节点充电电路响应于所述第二时钟信号以对所述下拉节点进行充电，所述上拉节点复位电路在所述下拉节点的电平的控制下，对所述上拉节点进行下拉复位，所述输出复位电路在所述下拉节点的电平的控制下，对所述输出端进行复位降噪。其中，在所述第一阶段、所述第二阶段以及所述第三阶段中，所述第一时钟信号和所述第二时钟信号中的一个为高电平信号，另一个为低电平信号。
本公开至少一实施例还提供一种移位寄存器的驱动方法，包括：所述第一控制信号为第一电平且所述第二控制信号为第二电平时，所述移位寄存器工作在正扫模式；所述第一控制信号为所述第二电平且所述第二控制信号为所述第一电平时，所述移位寄存器工作在反扫模式。其中，所述第一电平和所述第二电平中的一个为高电平，另一个为低电平。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种移位寄存器的电路示意图；
图2为本公开一实施例的一个示例提供的一种移位寄存器的示意框图；
图3为本公开一实施例的另一个示例提供的一种移位寄存器的示意框图；
图4为本公开一实施例的又一个示例提供的一种移位寄存器的示意框图；
图5为图4中所示的移位寄存器的一种具体实现示例的电路示意图；
图6为对应于图5中所示的移位寄存器工作时的一种信号时序图；
图7为对应于图5中所示的移位寄存器工作时的另一种信号时序图；
图8为采用多个级联的如图1所示的移位寄存器构成的栅极驱动电路G1和采用多个级联的如图5所示的移位寄存器构成的栅极驱动电路G2的仿真波形对比图；
图9为本公开另一实施例提供的一种移位寄存器的电路示意图；
图10A为如图9所示的移位寄存器的仿真波形示意图；
图10B为如图5所示的移位寄存器的仿真波形示意图；
图11为本公开一实施例提供的一种栅极驱动电路的示意图；
图12为本公开一实施例提供的另一种栅极驱动电路的示意图；
图13为本公开一实施例提供的又一种栅极驱动电路的示意图；
图14为本公开一实施例提供的一种显示装置的示意框图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在显示面板技术中，为了实现低成本和窄边框，可以采用GOA(Gate  driver On Array)技术，即将栅极驱动电路通过薄膜晶体管工艺集成在显示面板上，从而可以实现窄边框和降低装配成本等优势。例如，该显示面板可以为液晶显示(LCD)面板或有机发光二极管(OLED)显示面板。
图1示出了一种移位寄存器的电路示意图，该移位寄存器可以被级联以形成栅极驱动电路。如图1所示，该移位寄存器采用11T3C结构，即包括十一个晶体管(T1～T11)和三个电容(C1、C2和C3)。
例如，当图1中所示的移位寄存器级联形成一个栅极驱动电路时，对于其中的一级移位寄存器，例如以正向扫描(正扫)为例进行说明(例如第一控制端CN为高电平时且第二控制端CNB为低电平时实现正扫)，第一控制端CN输入的高电平对上拉节点PU进行充电。由于第二控制端CNB为低电平，第二晶体管T2的源漏极两端的电压差较大，上拉节点PU会通过第二晶体管T2漏电，尤其是在高温条件下晶体管的漏电流较大时，上拉节点PU会存在压降(drop)，进而导致本级输出有压降，甚至可能导致不符合要求的输出。另外，当该栅极驱动电路用于TDDI(Touch and Display Driver Integration，触控与显示驱动器集成)产品时，经过一段触控扫描阶段后，由于上拉节点PU在高温条件下漏电流较大，使得上拉节点PU会有较大的压降，在本级输出时上拉节点PU的自举电压也不能达到较高电平，从而导致本级输出存在压降。如上所述，采用图1中所示的移位寄存器级联形成的栅极驱动电路驱动一显示面板时，由于上拉节点PU存在的压降，尤其是在高温条件下，会导致移位寄存器的输出也存在压降，进而可能导致显示不良、高温信赖性差等问题。
本公开至少一实施例提供一种移位寄存器，其包括输入电路、上拉节点充电电路和输出电路。该输入电路和第一输入端、第一控制端以及上拉节点充电电路连接，且被配置为响应于第一控制端提供的第一控制信号以将第一输入端提供的第一输入信号输出。该上拉节点充电电路和第一电压端、第二电压端、输入电路以及上拉节点连接，且被配置为在第一输入信号的控制下，对上拉节点进行充电并保持上拉节点的电平。该输出电路和上拉节点、第一时钟信号端以及输出端连接，且被配置为在上拉节点的电平的控制下，将第一时钟信号端提供的第一时钟信号输出至输出端。
本公开至少一实施例还提供对应于上述移位寄存器的栅极驱动电路、显示装置以及驱动方法。
本公开的至少一实施例提供的移位寄存器及其驱动方法、栅极驱动电路、显示装置，可以使得上拉节点PU的电平得到更好地保持，降低或消除上拉节点PU的压降，进而在高温条件下晶体管漏电流较大时使得本级输出正常无压降。同时在本级输出之外的其他时刻无输出，即可以避免多次输出问题。从而，本公开的至少一实施例在应用于触控显示产品时，可以解决显示不良等问题，尤其是在高温信赖性方面，具有明显的改善效果。
下面结合附图对本公开的实施例进行详细说明。
本公开实施例的一个示例提供一种移位寄存器100，如图2所示，该移位寄存器100包括输入电路110、上拉节点充电电路130和输出电路120。
该输入电路110和第一输入端IN1、第一控制端CN以及上拉节点充电电路130连接，且被配置为响应于第一控制端CN提供的第一控制信号以将第一输入端IN1提供的第一输入信号输出。例如，输入电路110可以在第一控制端CN提供的第一控制信号的控制下而开启，从而将第一输入端IN1提供的第一输入信号输出至上拉节点充电电路130。
需要说明的是，在一些示例中，如图3和图4所示，输入电路110还可以和第二输入端IN2以及第二控制端CNB连接，从而可以实现双向扫描(即正向扫描以及反向扫描)功能。例如，输入电路110还可以配置为响应于第二控制端CNB提供的第二控制信号以将第二输入端IN2提供的第二输入信号输出。例如，第一控制信号为第一电平且第二控制信号为第二电平时，移位寄存器100工作在正扫模式；第一控制信号为第二电平且第二控制信号为第一电平时，移位寄存器100工作在反扫模式。第一电平和第二电平中的一个为高电平，另一个为低电平。例如，第一电平可以是高电平，例如为3.3V～5V，同时第二电平是低电平，例如为0V～0.4V。本公开的实施例包括但不限于这种设置方式，例如还可以使第一电平为低电平，而第二电平为高电平。以下各实施例与此相同，不再赘述。
继续参见图2所示，该上拉节点充电电路130和第一电压端VGH、第二电压端VGL、输入电路110以及上拉节点PU连接，且被配置为在第一输入信号的控制下，对上拉节点PU进行充电并保持上拉节点PU的电平。例如，上拉节点充电电路130可以在第一输入信号的控制下，使得第一电压端VGH和上拉节点PU电连接，从而第一电压端VGH输入的第一电压(例如为高电平)可以对上拉节点PU进行充电。又例如，在移位寄存器 100输出逐行扫描信号时，上拉节点充电电路130可以在第一输入信号的控制下，使得上拉节点PU的电平更好地保持，进而可以使得本级输出正常无压降。
该输出电路120和上拉节点PU、第一时钟信号端CK以及输出端OUT连接，且被配置为在上拉节点PU的电平的控制下，将第一时钟信号端CK提供的第一时钟信号输出至输出端OUT。例如，该输出电路120可以在上拉节点PU的电平的控制下，使得第一时钟信号端CK和输出端OUT电连接，从而可以将第一时钟信号端CK输入的第一时钟信号输出至输出端OUT。
例如，在本公开实施例的另一个示例中，如图3所示，移位寄存器100还可以包括下拉节点控制电路140、上拉节点复位电路150和输出复位电路160。
该下拉节点控制电路140和第二时钟信号端CKB、第二电压端VGL、下拉节点PD、输入电路110以及上拉节点充电电路130连接，且被配置为响应于第二时钟信号端CKB提供的第二时钟信号或输入电路110输出的第一输入信号以控制下拉节点PD的电平。
例如，在一个示例中，如图4所示，下拉节点控制电路140可以包括第一下拉节点复位电路141和第一下拉节点充电电路142。
该第一下拉节点充电电路142和第二时钟信号端CKB、第二电压端VGL以及下拉节点PD连接，且被配置为响应于第二时钟信号端CKB提供的第二时钟信号以对下拉节点PD进行充电。例如，该第一下拉节点充电电路142可以在第二时钟信号端CKB提供的第二时钟信号的控制下而开启，从而可以使得第二时钟信号端CKB和下拉节点PD电连接，例如在第二时钟信号为高电平信号时，该第二时钟信号可以对下拉节点PD进行充电。
该第一下拉节点复位电路141和第二电压端VGL、下拉节点PD、输入电路110以及上拉节点充电电路130连接，且被配置为响应于第一输入信号以对下拉节点PD进行下拉复位。例如，该第一下拉节点复位电路141可以在输入电路110输出的第一输入信号的控制下，使得下拉节点PD和第二电压端VGL电连接，例如第二电压端VGL保持输入直流低电平信号，从而可以对下拉节点PD进行下拉复位。
需要说明的是，本公开的实施例中的第一电压端VGH例如保持输入直流高电平信号，将该直流高电平称为第一电压；第二电压端VGL例如保持输入直流低电平信号，将该直流低电平称为第二电压。以下各实施例与此相同，不再赘述。
继续参见图3所示，该上拉节点复位电路150和下拉节点PD、第二电压端VGL以及上拉节点充电电路130连接，且被配置为在下拉节点PD的电平的控制下，对上拉节点PU进行下拉复位。例如，该上拉节点复位电路150可以在下拉节点PD的电平的控制下而开启，同时上拉节点充电电路130在第一电压的控制下使得上拉节点PU和上拉节点复位电路150电连接，从而可以使得上拉节点PU和第二电压端VGL电连接，第二电压端VGL可以对上拉节点PU进行下拉复位。
该输出复位电路160和输出端OUT、下拉节点PD以及第二电压端VGL连接，且被配置为在下拉节点PD的电平的控制下，对输出端OUT进行复位降噪。例如，该输出复位电路160可以在下拉节点PD的电平的控制下，使得输出端OUT和第二电压端VGL电连接，从而第二电压端VGL输入的低电平可以对输出端OUT进行复位降噪。
例如，在本公开实施例的另一个示例中，如图4所示，移位寄存器100还可以包括第二下拉节点复位电路170。
该第二下拉节点复位电路170和下拉节点PD、输出端OUT以及第二电压端VGL连接，且被配置为在输出端OUT的电平的控制下，对下拉节点PD进行下拉复位。例如，该第二下拉节点复位电路170可以在输出端OUT的电平的控制下，使得下拉节点PD和第二电压端VGL电连接，从而第二电压端VGL可以对下拉节点PD进行下拉复位。采用这种方式可以使得移位寄存器100的输出端OUT在进行正常输出时，可以对下拉节点PD的电位进行下拉复位，可以进一步保证输出端OUT的正常输出。
例如，在本公开实施例的另一个示例中，如图4所示，移位寄存器100还可以包括第二下拉节点充电电路180。
该第二下拉节点充电电路180和下拉节点PD以及复位端Reset连接，且被配置为响应于复位端Reset提供的复位信号以对下拉节点PD进行充电。例如，该第二下拉节点充电电路180可以在复位信号的控制下而开启，使得复位端Reset和下拉节点PD电连接，例如复位信号可以是高电平信号， 从而该高电平的复位信号可以对下拉节点PD进行充电以提高下拉节点PD的电位。例如，上拉节点复位电路150和输出复位电路160可以在下拉节点PD的高电平的控制下而开启，从而进一步实现上拉节点PU和输出端OUT的复位操作。例如，可以采用多个级联的移位寄存器100构成一栅极驱动电路，当采用该栅极驱动电路驱动一显示面板时，可以在该显示面板上电时，同时向栅极驱动电路中的各级移位寄存器提供复位信号，以实现对各级移位寄存器中的上拉节点PU和输出端OUT同时进行复位操作，从而实现整个栅极驱动电路的初始化。
例如，在本公开实施例的另一个示例中，如图4所示，移位寄存器100还可以包括触控复位电路190。
该触控复位电路190和输出端OUT、第二电压端VGL以及触控使能端EN_Touch连接，且被配置为响应于触控使能端EN_Touch提供的触控使能信号以对输出端OUT进行复位降噪。例如，该触控复位电路190可以在触控使能信号的控制下而开启，使得输出端OUT和第二电压端电连接，从而第二电压端输入的低电平信号可以对输出端OUT进行复位降噪。例如，可以采用多个级联的移位寄存器100构成一栅极驱动电路，当该栅极驱动电路用于TDDI(Touch and Display Driver Integration，触控与显示驱动器集成)产品时，例如可以在进入触控扫描阶段时，生成上述触控使能信号，以对各级移位寄存器的输出端OUT进行复位降噪，以避免发生显示不良，以及显示操作和触控操作之间的干扰。
本公开的实施例提供的移位寄存器100可以使得上拉节点PU的电平得到更好地保持，降低上拉节点PU的压降，进而在高温条件下晶体管漏电流较大时使得本级输出正常无压降。解决了显示不良等问题，尤其是在高温信赖性方面，具有明显的改善效果。
例如，图4中所示的移位寄存器100在一个示例中可以具体实现为图5所示的电路结构。如图5所示，该移位寄存器100包括：第一至第十二晶体管T1-T12以及第一存储电容C1、第二存储电容C2和第三存储电容C3。
例如，如图5所示，在该示例中，更详细地，输入电路110可以实现为包括第一晶体管T1和第二晶体管T2。第一晶体管T1的栅极配置为和第一控制端CN连接以接收第一控制信号，第一晶体管T1的第一极配置 为和第一输入端IN1连接以接收第一输入信号，第一晶体管T1的第二极和上拉节点充电电路130连接以将第一输入信号输出至上拉节点充电电路130。第二晶体管T2的栅极配置为和第二控制端CNB连接以接收第二控制信号，第二晶体管T2的第二极配置为和第二输入端IN2连接以接收第二输入信号，第二晶体管T2的第一极和上拉节点充电电路130连接以将第二输入信号输出至上拉节点充电电路130。
第一晶体管T1和第二晶体管T2不同时开启。例如，移位寄存器100工作在正扫模式时，可以使第一晶体管T1在第一控制信号的控制下而开启(此时第二晶体管T2处于关闭状态)，从而将第一输入信号输出至上拉节点充电电路130。又例如，移位寄存器100工作在反扫模式时，可以使第二晶体管T2在第二控制信号的控制下而开启(此时第一晶体管T1处于关闭状态)，从而可以将第二输入信号输出至上拉节点充电电路130。通过第一控制信号和第二控制信号的配合可以实现正扫和反扫模式的切换。
需要说明的是，在一些实施例中，在不需要支持双向扫描的情形下，输入电路110也可以不包括第二晶体管T2，本公开的实施例对此不作限定。
输出电路120可以实现为包括第三晶体管T3和第一存储电容C1。第三晶体管T3的栅极和上拉节点PU连接，第三晶体管T3的第一极配置为和第一时钟信号端CK连接以接收第一时钟信号，第三晶体管T3的第二极和输出端OUT连接。第一存储电容C1的第一极和上拉节点PU连接，第一存储电容C1的第二极和输出端OUT连接。
上拉节点充电电路130可以实现为包括第四晶体管T4、第五晶体管T5和第二存储电容C2。第四晶体管T4的栅极和输入电路110连接，第四晶体管T4的第一极和第一电压端VGH连接以接收第一电压，第四晶体管T4的第二极和上拉控制节点PU_CN连接。第五晶体管T5的栅极和第一电压端VGH连接以接收第一电压而保持常开，第五晶体管T5的第一极和上拉控制节点PU_CN连接，第五晶体管T5的第二极和上拉节点PU连接。第二存储电容C2的第一极和上拉控制节点PU_CN连接，第二存储电容C2的第二极和第二电压端VGL连接。
第一下拉节点复位电路141可以实现为第六晶体管T6。第六晶体管T6的栅极和输入电路110以及上拉节点充电电路130连接，第六晶体管T6的第一极和下拉节点PD连接，第六晶体管T6的第二极和第二电压端 VGL连接。
第一下拉节点充电电路142可以实现为包括第七晶体管T7和第三存储电容C3。第七晶体管T7的栅极和第一极配置为与第二时钟信号端CKB连接以接收第二时钟信号，第七晶体管T7的第二极和下拉节点PD连接。第三存储电容的第一极和下拉节点连接，第三存储电容的第二极和第二电压端连接。
上拉节点复位电路150可以实现为第八晶体管T8。第八晶体管T8的栅极和下拉节点PD连接，第八晶体管T8的第一极和上拉控制节点连接PU_CN，第八晶体管T8的第二极和第二电压端VGL连接。
输出复位电路160可以实现为第九晶体管T9。第九晶体管T9的栅极和下拉节点PD连接，第九晶体管T9的第一极和输出端OUT连接，第九晶体管T9的第二极和第二电压端VGL连接。
第二下拉节点复位电路170可以实现为第十晶体管T10。第十晶体管T10的栅极和输出端OUT连接，第十晶体管T10的第一极和下拉节点PD连接，第十晶体管T10的第二极和第二电压端VGL连接。
第二下拉节点充电电路180可以实现为第十一晶体管T11。第十一晶体管T11的栅极和第一极配置为与复位端Reset连接以接收复位信号，第十一晶体管T11的第二极和下拉节点PD连接。
触控复位电路190可以实现为第十二晶体管T12。第十二晶体管T12的栅极配置为和触控使能端EN_Touch连接以接收触控使能信号，第十二晶体管T12的第一极和输出端OUT连接，第十二晶体管T12的第二极和第二电压端VGL连接。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
另外，在本公开的实施例中的晶体管均以N型晶体管为例进行说明，此时，第一极可以是漏极，第二极可以是源极。需要说明的是，本公开包括但不限于此。例如，本公开的实施例提供的移位寄存器中的一个或多个 晶体管也可以采用P型晶体管，此时，第一极可以是源极，第二极可以是漏极，只需将选定类型的晶体管的各极的极性按照本公开的实施例中的相应晶体管的各极的极性相应连接即可。
例如，如图5所示，该移位寄存器100中的晶体管均采用N型晶体管，第一电压端VGH保持输入直流高电平的第一电压，第二电压端VGL保持输入直流低电平的第二电压，第一时钟信号端CK输入第一时钟信号，第二时钟信号端CKB输入与第一时钟信号不同的第二时钟信号。
下面以正扫模式为例，即第一控制端CN输入高电平的第一控制信号，第二控制端CNB输入低电平的第二控制信号(第一晶体管T1保持开启状态，第二晶体管T2保持关闭状态)，并结合图6所示的信号时序图，对图5所示的移位寄存器100的工作原理进行说明。在图6所示的第一阶段A、第二阶段B以及第三阶段C共三个阶段中，该移位寄存器100进行如下操作。
在第一阶段A，第一输入端IN1输入高电平，第一时钟信号端CK输入低电平，第二时钟信号端CKB输入高电平。由于第一晶体管T1保持导通，第一输入端IN1输入的高电平的第一输入信号可以通过第一晶体管T1传输至上拉节点充电电路130即第四晶体管的T4的栅极。第四晶体管T4导通，第一电压端VGH输入的高电平可以通过第四晶体管T4对第二存储电容C2充电，即对上拉控制节点PU_CN进行充电。同时，由于第五晶体管T5保持导通，所以第一电压端VGH输入的高电平还可以通过第五晶体管T5对第一存储电容C1进行充电，即对上拉节点PU进行充电，使得上拉节点PU的电位被上拉至第一高电平。由于上拉节点PU为高电平，第三晶体管T3导通，从而将第一时钟信号信号端CK输入的低电平输出至输出端OUT。
需要说明的是，在第一阶段A中，由于第二时钟信号端CKB输入高电平，第七晶体管T7导通，从而第二时钟信号可以对第三存储电容C3充电，即对下拉节点PD进行充电。同时，第六晶体管T6由于高电平的第一输入信号而导通，所以第二电压端VGL输入的低电平信号对下拉节点PD进行下拉。例如在晶体管的设计上，可以将第六晶体管T6与第七晶体管T7配置为(例如对二者的尺寸比、阈值电压等配置)在T6和T7均导通时，下拉节点PD的电平可以保持在低电平而不被上拉。
在第二阶段B，第一输入端IN1输入低电平，第一时钟信号端CK输入高电平，第二时钟信号端CKB输入低电平。由于第一晶体管T1依然保持导通，第一输入端IN1输入的低电平的第一输入信号可以通过第一晶体管T1传输至第四晶体管T4和第六晶体管T6的栅极，从而使得第四晶体管T4和第六晶体管T6截止。由于第二时钟信号端CKB输入低电平，第七晶体管T7截止，即下拉节点PD的充电路径被截止，下拉节点PD可以保持上一阶段的低电平。上拉节点PU保持高电平，使得第三晶体管T3继续导通，由于在此阶段第一时钟信号端CK输入高电平，所以输出端OUT输出该高电平信号。由于第一存储电容C1的自举效应，上拉节点PU的电位被进一步拉高，达到第二高电平，使得第三晶体管T3的导通更充分。
由于输出端OUT为高电平，第十晶体管T10导通，下拉节点PD和第二电压端VGL电连接，从而使得下拉节点PD的电位被进一步拉低，以避免下拉节点PD上的噪声影响输出端OUT的正常输出。
在第二阶段B中，第四晶体管T4截止，同时第二晶体管T2的第一极和第二极(即源漏两极)两端无压差，可以降低上拉节点PU由于晶体管的漏电流而造成的压降，而且可以使得上拉节点PU的自举电压可以达到较高的电平，从而可以保证输出端OUT的正常输出。
在第三阶段C，第一输入端IN1依然输入低电平，第一时钟信号端CK输入低电平，第二时钟信号端CKB输入高电平。和上一阶段相同，第四晶体管T4和第六晶体管T6依然保持截止。由于第二时钟信号端CKB输入高电平，第七晶体管T7导通，所以高电平的第二时钟信号可以通过第七晶体管T7对第三存储电容C3充电，即对下拉节点PD进行充电，下拉节点PD的电位被上拉至高电平。
由于下拉节点PD为高电平，第八晶体管T8导通，第一存储电容C1和第二存储电容C2均可以第八晶体管T8进行放电，从而可以实现对上拉控制节点PU_CN和上拉节点PU的下拉复位。同样的，第九晶体管T9也导通，从而实现对输出端OUT的下拉复位。
例如，可以采用多个级联的如图5所示的移位寄存器100构成一栅极驱动电路，当采用该栅极驱动电路驱动一显示面板时，可以在该显示面板上电时，同时向栅极驱动电路中的各级移位寄存器100提供高电平的复位信号。该复位信号使得第十一晶体管T11导通，从而该高电平的复位信号 可以通过第十一晶体管T11对下拉节点PD进行充电，以将下拉节点PD的电位上拉至高电平。和上述第三阶段C中描述相同，下拉节点PD为高电平时，第八晶体管T8和第九晶体管T9导通，进而可以实现同时对各级移位寄存器100中的上拉节点PU和输出端OUT进行复位操作。
例如，当上述栅极驱动电路用于TDDI(Touch and Display Driver Integration，触控与显示驱动器集成)产品时，例如可以在进入触控扫描阶段时，生成触控使能信号，该触控使能信号可以使得第十二晶体管T12导通，从而可以对各级移位寄存器的输出端OUT进行复位降噪，以避免发生显示不良。
需要说明的是，图6中所示的第一时钟信号端CK和第二时钟信号端CKB上的时序信号是以50％占空比的信号为例进行说明的，本公开的实施例包括但不限于此，例如还可以采用图7中所示的25％占空比的时序信号。相应的其他时序信号如图7所示，这里不再赘述。
综上所述，本公开实施例提供的移位寄存器100包括12个晶体管和3个电容，对比图1中所示的移位寄存器(11个晶体管和3个电容)，通过增加一个晶体管T4，并且改变第一晶体管T1和第二晶体管T2的连接方式，可以使得上拉节点PU的电平得到更好地保持，降低上拉节点PU的压降，进而在高温条件下晶体管漏电流较大时使得本级输出正常无压降。同时在本级输出之外的其他时刻无输出，即可以避免多次输出问题。解决了显示不良等问题，尤其是在高温信赖性方面，具有明显的改善效果。
采用多个级联的如图1所示的移位寄存器构成一栅极驱动电路，将该栅极驱动电路记作G1；同样地，采用多个级联的如图5所示的移位寄存器构成一栅极驱动电路，将该栅极驱动电路记作G2。以下各实施例与此相同，不再赘述。
在高温条件晶体管漏电流较大的情形下，对G1和G2的仿真对比结果如表1和图8所示。
结合表1和图8所示，从两种栅极驱动电路的仿真波形可以看出，G1中的移位寄存器的上拉节点PU的自举电压要比G2中的移位寄存器的上拉节点PU的自举电压低，对于Normal(正常显示状态)及Touch(触控扫描)前一级的移位寄存器，图5中所示的移位寄存器的上拉节点PU的自举电压压降相比于图1中所示的移位寄存器100的上拉节点PU的自举 电压压降要小3V。对于G1，在Touch后一级的移位寄存器中，上拉节点PU的自举电压下降到6V，使得第三晶体管T3不能完全导通，进而Touch后一级的的移位寄存器的输出有压降(1.5V)。而对于G2，在Touch后一级的移位寄存器中，上拉节点PU的自举电压压降要小于G1，从而可以使得本级输出无压降。
表1
Figure PCTCN2017115959-appb-000001
在Normal及Touch前一级的移位寄存器中，对于上拉节点PU充电完成后的保持电压，G2中的移位寄存器基本无压降(在Normal情况下保持3.8V基本不变，在Touch前一级的情况下保持0.23V基本不变)。G1中的移位寄存器在Normal时的上拉节点PU的保持电压存在压降(1.2V)，在Touch后一级的移位寄存器中，G2中的移位寄存器的上拉节点PU的压降比G1中的要小1.7V，即G2中的移位寄存器的上拉节点PU的保持电压要好于G1，因此有利于Touch后一级移位寄存器的输出。
具体地，对于G1中的移位寄存器，由于正扫时，第一控制端CN为高电平，在给本级上拉节点PU充电时，第二控制端CNB为低电平，第二晶体管T2的源漏极两端电压差较大，上拉节点PU会通过第二晶体管T2漏电，尤其是在高温条件下晶体管的漏电流较大时，上拉节点PU会存在压降，进而导致本级输出有压降。另外，当G1用于TDDI产品时，由图8里的After Touch仿真波形可以看出上拉节点PU经过一段Touch时间后会有较大的压降，在本级输出时上拉节点PU的自举电压也不能达到较高的电平，从而导致本级输出存在压降，再显示时可能会出现显示不良等问题。
而对于G2中的移位寄存器，从表1和图8的仿真结果可以看出，上拉节点PU的自举电压及输出都有很大改善。例如在正扫时，上级移位寄存器给本级移位寄存器充电完成后，上拉节点PU为高电平，本级移位寄存器在输出时，第四晶体管T4截止，且此时第二晶体管T2的源漏两极无电压差，可以降低上拉节点PU由于晶体管的漏电流而造成的压降，而且使得Touch后一级的移位寄存器中的上拉节点PU的自举电压可以达到较高的电平，从而可以保证输出端OUT的正常输出。
此外，通过改变第一晶体管T1和第二晶体管T2的连接方式，本公开的实施例提供的移位寄存器在本级输出之外的其他时刻无输出，即可以避免多次输出问题。其中，未改变第一晶体管T1和第二晶体管T2的连接方式的移位寄存器如图9所示。
具体地，通过对比图9所示的移位寄存器的仿真波形(如图10A所示)与图5所示的移位寄存器的仿真波形(如图10B所示)可知，图9所示的移位寄存器，在高温条件下晶体管的漏电流较大时，从图10A中所示的仿真波形可以看出，输出端OUT存在Multi(多次)输出问题。例如在正扫时，第一控制端CN为高电平，在本级输出之外的其他时刻，由于第一晶体管T1源漏极两端电压差较大而导致关闭电流Ioff较大，故第四晶体管T4不能完全关闭，第一电压端VGH输入的高电平信号会通过第四晶体管T4和第五晶体管T5给上拉节点PU充电，使得上拉节点PU的电位被升高，从而本级移位寄存器会有多次输出问题。
而从图10B中所示的仿真波形可以看出，图5所示的移位寄存器在高温条件下晶体管的漏电流较大时，则没有多次输出的问题。例如在正扫时，在本级输出之外的其他时刻，第一晶体管T1的源漏两极无电压差，第一晶体管T1的关闭电路Ioff很小，故第四晶体管T4可以完全关闭，使得在其他时刻上拉节点PU的电位不会升高，从而本级移位寄存器没有多次输出问题。
本公开的实施例提供的移位寄存器，通过增加一个晶体管(第四晶体管T4)，并且通过改变第一晶体管T1与第二晶体管T2的连接方式，可以使得上拉节点PU的电平得到更好地保持，降低上拉节点PU的压降，进而在高温条件下晶体管漏电流较大时本级输出正常无压降。同时在本级输出之外的其他时刻无输出，即可以避免多次输出问题。解决了显示不良等 问题，尤其是在高温信赖性方面，具有明显的改善效果。
本公开的至少一实施例提供一种栅极驱动电路10，如图11、图12和图13所示，该栅极驱动电路10包括多个级联的移位寄存器100，该移位寄存器100可以采用上述实施例中提供的移位寄存器100。该栅极驱动电路10可以采用与薄膜晶体管同样制程的工艺直接集成在显示装置的阵列基板上，实现逐行扫描驱动功能。
例如，如图11所示，在移位寄存器100不包括第二输入端IN2和第二控制端CNB的情形下，除第一级移位寄存器外，其余各级移位寄存器的第一输入端IN1和上一级移位寄存器的输出端OUT连接。例如，第一级移位寄存器的第一输入端IN1可以被配置为接收触发信号STV。图11中所示的栅极驱动电路不能实现双向扫描。
例如，如图12所示，在移位寄存器100包括第二输入端IN2和第二控制端CNB的情形下，除第一级移位寄存器外，其余各级移位寄存器的第一输入端IN1和上一级移位寄存器的输出端OUT连接，除最后一级移位寄存器外，其余各级移位寄存器的第二输入端IN2和下一级移位寄存器的输出端OUT连接。例如，第一级移位寄存器的第一输入端IN1和最后一级移位寄存器的第二输入端IN2可以被配置为接收触发信号STV。图12中所示的栅极驱动电路可以实现双向扫描。
例如，如图13所示，在移位寄存器100包括复位端Reset的情形下，各级移位寄存器100的复位端Reset例如可以连接到时钟控制器200上，以接收复位信号RST。例如，当采用图13所示的栅极驱动电路10驱动一显示面板时，可以在该显示面板上电时，同时向栅极驱动电路10中的各级移位寄存器100提供复位信号RST，以实现整个栅极驱动电路10的初始化。
例如，如图11、图12和图13所示，当采用该栅极驱动电路10驱动一显示面板时，在一个示例中可以将该栅极驱动电路10设置于显示面板的一侧。例如，该显示面板包括2N行栅线300(N为大于零的整数)，栅极驱动电路10中的各级移位寄存器100的输出端OUT可以配置为依序和该2N行栅线300(如图11和图12中1，2，…，2N-1，2N标记所示，N为大于零的整数)连接，以用于输出逐行扫描信号。
例如，如图11、图12和图13所示，可以通过两个系统时钟信号CLK1 和CLK2向每个移位寄存器100中的时钟信号端(第一时钟信号端CK和第二时钟信号端CKB)提供时钟信号。例如第一级移位寄存器100的第一时钟信号端CK输入CLK2，第二时钟信号端CKB输入CLK1；第二级移位寄存器100的第一时钟信号端CK输入CLK1，第二时钟信号端CKB输入CLK2；以此类推，第2N-1级移位寄存器100的第一时钟信号端CK输入CLK2，第二时钟信号端CKB输入CLK1；第2N级移位寄存器100的第一时钟信号端CK输入CLK1，第二时钟信号端CKB输入CLK2。例如，在这种配置方式中，CLK1和CLK2可以采用50％占空比的时序信号。
需要说明的是，在采用如图11、图12和图13所示的栅极驱动电路10驱动一显示面板时，还可以分别在显示面板的两侧对称的设置栅极驱动电路10，使两个栅极驱动电路10中的输出端OUT连接到对应的栅线的两端，从而实现双边驱动。例如，双边驱动方式可以应用在对中大尺寸的显示面板的驱动中，以解决栅线上负载较大的问题。
另外，在采用如图11、图12和图13所示的栅极驱动电路10驱动一显示面板时，还可以在显示面板的一侧设置一个栅极驱动电路10以用于驱动奇数行的栅线，同时在显示面板的另一侧设置另一个栅极驱动电路10以用于驱动偶数行的栅线。例如，在这种配置方式中，CLK1和CLK2可以采用25％占空比的时序信号。
例如，如图11、图12和图13所示，栅极驱动电路10还可以包括时序控制器200。该时序控制器200例如被配置为向各级移位寄存器100提供时钟信号(CLK1，CLK2)，时序控制器200还可以被配置为提供触发信号STV、复位信号RST以及触控使能信号。
本公开的实施例提供的栅极驱动电路10的技术效果，可以参考上述实施例中关于移位寄存器100的相应描述，这里不再赘述。
本公开的至少一实施例还提供一种显示装置1，如图14所示，该显示装置1包括上述实施例中提供的任一栅极驱动电路10。
需要说明的是，本实施例中的显示装置可以为：液晶面板、液晶电视、显示器、OLED面板、OLED电视、电子纸、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置1还可以包括显示面板等其他常规部件，本公开的实施例对此不作限制。
本公开的实施例提供的显示装置1的技术效果，可以参考上述实施例 中关于移位寄存器100的相应描述，这里不再赘述。
本公开的至少一实施例还提供一种驱动方法，可以用于驱动本公开的实施例中提供的移位寄存器100。例如，该驱动方法包括如下操作。
在第一阶段，输入电路110响应于第一控制信号以将第一输入信号输出，上拉节点充电电路130在第一输入信号的控制下对上拉节点PU进行充电，第一下拉节点复位电路141响应于第一输入信号以对下拉节点PU进行放电复位。
在第二阶段，上拉节点充电电路130保持上拉节点PU的电平，输出电路120在上拉节点PU的电平的控制下，将第一时钟信号输出至输出端OUT。
在第三阶段，第一下拉节点充电电路142响应于第二时钟信号以对下拉节点PD进行充电，上拉节点复位电路150在下拉节点PD的电平的控制下，对上拉节点PU进行放电复位，输出复位电路160在下拉节点PD的电平的控制下，对输出端OUT进行复位降噪。
在上述第一阶段、第二阶段以及第三阶段中，第一时钟信号和第二时钟信号中的一个为高电平信号，另一个为低电平信号。
需要说明的是，关于该驱动方法的详细描述以及技术效果可以参考本公开实施例中对于移位寄存器100的工作原理的描述，这里不再赘述。
本公开的至少一实施例还提供一种驱动方法，可以用于驱动本公开的实施例中包括第二输入端IN2和第二控制端CNB的移位寄存器100。例如，该驱动方法包括如下操作。
第一控制信号为第一电平且第二控制信号为第二电平时，移位寄存器100工作在正扫模式。
第一控制信号为第二电平且第二控制信号为第一电平时，移位寄存器100工作在反扫模式。
其中，第一电平和第二电平中的一个为高电平，另一个为低电平。
需要说明的是，关于该驱动方法的详细描述以及技术效果可以参考本公开实施例中对于移位寄存器100的工作原理的描述，这里不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (23)

  1. 一种移位寄存器，包括：输入电路、上拉节点充电电路和输出电路；其中，
    所述输入电路和第一输入端、第一控制端以及所述上拉节点充电电路连接，且被配置为响应于所述第一控制端提供的第一控制信号以将所述第一输入端提供的第一输入信号输出；
    所述上拉节点充电电路和第一电压端、第二电压端、所述输入电路以及上拉节点连接，且被配置为在所述第一输入信号的控制下，对所述上拉节点进行充电并保持所述上拉节点的电平；
    所述输出电路和所述上拉节点、第一时钟信号端以及输出端连接，且被配置为在所述上拉节点的电平的控制下，将所述第一时钟信号端提供的第一时钟信号输出至所述输出端。
  2. 如权利要求1所述的移位寄存器，还包括下拉节点控制电路、输出复位电路和上拉节点复位电路；其中，
    所述下拉节点控制电路和第二时钟信号端、所述第二电压端、下拉节点、所述输入电路以及所述上拉节点充电电路连接，且被配置为响应于所述第二时钟信号端提供的第二时钟信号或所述第一输入信号以控制所述下拉节点的电平；
    所述上拉节点复位电路和所述下拉节点、所述第二电压端以及所述上拉节点充电电路连接，且被配置为在所述下拉节点的电平的控制下，对所述上拉节点进行下拉复位；
    所述输出复位电路和所述输出端、所述下拉节点以及所述第二电压端连接，且被配置为在所述下拉节点的电平的控制下，对所述输出端进行复位降噪。
  3. 如权利要求2所述的移位寄存器，其中，所述下拉节点控制电路包括第一下拉节点充电电路和第一下拉节点复位电路；
    所述第一下拉节点充电电路和所述第二时钟信号端、所述第二电压端以及所述下拉节点连接，且被配置为响应于所述第二时钟信号端提供的第二时钟信号以对所述下拉节点进行充电；
    所述第一下拉节点复位电路和所述第二电压端、所述下拉节点、所述 输入电路以及所述上拉节点充电电路连接，且被配置为响应于所述第一输入信号以对所述下拉节点进行下拉复位。
  4. 如权利要求2所述的移位寄存器，还包括第二下拉节点复位电路；其中，
    所述第二下拉节点复位电路和所述下拉节点、所述输出端以及所述第二电压端连接，且被配置为在所述输出端的电平的控制下，对所述下拉节点进行下拉复位。
  5. 如权利要求2所述的移位寄存器，还包括第二下拉节点充电电路；其中，
    所述第二下拉节点充电电路和所述下拉节点以及复位端连接，且被配置为响应于所述复位端提供的复位信号以对所述下拉节点进行充电。
  6. 如权利要求2所述的移位寄存器，还包括触控复位电路；其中，
    所述触控复位电路和所述输出端、所述第二电压端以及触控使能端连接，且被配置为响应于所述触控使能端提供的触控使能信号以对所述输出端进行复位降噪。
  7. 如权利要求1-6任一所述的移位寄存器，其中，所述输入电路包括第一晶体管；
    所述第一晶体管的栅极配置为和所述第一控制端连接以接收所述第一控制信号，所述第一晶体管的第一极配置为和所述第一输入端连接以接收第一输入信号，所述第一晶体管的第二极和所述上拉节点充电电路连接。
  8. 如权利要求7所述的移位寄存器，其中，所述输入电路还包括第二晶体管；
    所述第二晶体管的栅极配置为和第二控制端连接以接收第二控制信号，所述第二晶体管的第一极和所述上拉节点充电电路连接，所述第二晶体管的第二极配置为和第二输入端连接以接收第二输入信号，
    其中，所述第一晶体管和第二晶体管不同时开启。
  9. 如权利要求1-6任一所述的移位寄存器，其中，所述输出电路包括第三晶体管和第一存储电容；
    所述第三晶体管的栅极和所述上拉节点连接，所述第三晶体管的第一极配置为和所述第一时钟信号端连接以接收所述第一时钟信号，所述第三晶体管的第二极和所述输出端连接；
    所述第一存储电容的第一极和所述上拉节点连接，所述第一存储电容的第二极和所述输出端连接。
  10. 如权利要求1-6任一所述的移位寄存器，其中，所述上拉节点充电电路包括第四晶体管、第五晶体管和第二存储电容；
    所述第四晶体管的栅极和所述输入电路连接，所述第四晶体管的第一极和第一电压端连接，所述第四晶体管的第二极和上拉控制节点连接；
    所述第五晶体管的栅极和所述第一电压端连接，所述第五晶体管的第一极和所述上拉控制节点连接，所述第五晶体管的第二极和所述上拉节点连接；
    所述第二存储电容的第一极和所述上拉控制节点连接，所述第二存储电容的第二极和所述第二电压端连接。
  11. 如权利要求3所述的移位寄存器，其中，所述第一下拉节点复位电路包括第六晶体管；
    所述第六晶体管的栅极和所述输入电路以及所述上拉节点充电电路连接，所述第六晶体管的第一极和所述下拉节点连接，所述第六晶体管的第二极和所述第二电压端连接。
  12. 如权利要求3所述的移位寄存器，其中，所述第一下拉节点充电电路包括第七晶体管和第三存储电容；
    所述第七晶体管的栅极和第一极配置为与所述第二时钟信号端连接以接收所述第二时钟信号，所述第七晶体管的第二极和所述下拉节点连接；
    所述第三存储电容的第一极和所述下拉节点连接，所述第三存储电容的第二极和所述第二电压端连接。
  13. 如权利要求2-6任一所述的移位寄存器，其中，所述上拉节点复位电路包括第八晶体管；
    所述第八晶体管的栅极和所述下拉节点连接，所述第八晶体管的第一极和上拉控制节点连接，所述第八晶体管的第二极和所述第二电压端连接。
  14. 如权利要求2-6任一所述的移位寄存器，其中，所述输出复位电路包括第九晶体管；
    所述第九晶体管的栅极和所述下拉节点连接，所述第九晶体管的第一极和所述输出端连接，所述第九晶体管的第二极和所述第二电压端连接。
  15. 如权利要求4所述的移位寄存器，其中，所述第二下拉节点复位 电路包括第十晶体管；
    所述第十晶体管的栅极和所述输出端连接，所述第十晶体管的第一极和所述下拉节点连接，所述第十晶体管的第二极和所述第二电压端连接。
  16. 如权利要求5所述的移位寄存器，其中，所述第二下拉节点充电电路包括第十一晶体管；
    所述第十一晶体管的栅极和第一极配置为与所述复位端连接以接收所述复位信号，所述第十一晶体管的第二极和所述下拉节点连接。
  17. 如权利要求6所述的移位寄存器，其中，所述触控复位电路包括第十二晶体管；
    所述第十二晶体管的栅极配置为和所述触控使能端连接以接收所述触控使能信号，所述第十二晶体管的第一极和所述输出端连接，所述第十二晶体管的第二极和所述第二电压端连接。
  18. 一种栅极驱动电路，包括多个级联的如权利要求1-7、9-17任一所述的移位寄存器，其中，
    除第一级移位寄存器外，其余各级移位寄存器的第一输入端和上一级移位寄存器的输出端连接。
  19. 一种栅极驱动电路，包括多个级联的如权利要求8所述的移位寄存器，其中，
    除第一级移位寄存器外，其余各级移位寄存器的第一输入端和上一级移位寄存器的输出端连接；
    除最后一级移位寄存器外，其余各级移位寄存器的第二输入端和下一级移位寄存器的输出端连接。
  20. 一种显示装置，包括如权利要求18或19所述的栅极驱动电路。
  21. 一种权利要求1所述的移位寄存器的驱动方法，包括：
    第一阶段，所述输入电路响应于所述第一控制信号以将所述第一输入信号输出，所述上拉节点充电电路在所述第一输入信号的控制下对所述上拉节点进行充电；
    第二阶段，所述上拉节点充电电路保持所述上拉节点的电平，所述输出电路在所述上拉节点的电平的控制下，将所述第一时钟信号输出至所述输出端。
  22. 一种权利要求3所述的移位寄存器的驱动方法，包括：
    第一阶段，所述输入电路响应于所述第一控制信号以将所述第一输入信号输出，所述上拉节点充电电路在所述第一输入信号的控制下对所述上拉节点进行充电，所述第一下拉节点复位电路响应于所述第一输入信号以对所述下拉节点进行下拉复位；
    第二阶段，所述上拉节点充电电路保持所述上拉节点的电平，所述输出电路在所述上拉节点的电平的控制下，将所述第一时钟信号输出至所述输出端；
    第三阶段，所述第一下拉节点充电电路响应于所述第二时钟信号以对所述下拉节点进行充电，所述上拉节点复位电路在所述下拉节点的电平的控制下，对所述上拉节点进行下拉复位，所述输出复位电路在所述下拉节点的电平的控制下，对所述输出端进行复位降噪，
    其中，在所述第一阶段、所述第二阶段以及所述第三阶段中，所述第一时钟信号和所述第二时钟信号中的一个为高电平信号，另一个为低电平信号。
  23. 一种权利要求8所述的移位寄存器的驱动方法，包括：
    所述第一控制信号为第一电平且所述第二控制信号为第二电平时，所述移位寄存器工作在正扫模式；
    所述第一控制信号为所述第二电平且所述第二控制信号为所述第一电平时，所述移位寄存器工作在反扫模式；
    其中，所述第一电平和所述第二电平中的一个为高电平，另一个为低电平。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114217857A (zh) * 2022-02-21 2022-03-22 深圳云豹智能有限公司 一种数据处理电路、系统及数据处理方法
CN114217858A (zh) * 2022-02-21 2022-03-22 深圳云豹智能有限公司 一种数据处理电路、系统及数据处理方法

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106940977B (zh) * 2017-05-16 2019-07-19 京东方科技集团股份有限公司 移位寄存器、阵列基板栅极驱动电路和显示装置
CN107742509A (zh) * 2017-10-31 2018-02-27 武汉华星光电技术有限公司 一种单型goa电路及显示装置
CN109903729B (zh) * 2017-12-08 2024-04-16 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及驱动方法、显示装置
CN108172163B (zh) * 2018-01-02 2021-01-26 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器电路及其显示面板
CN108399902A (zh) * 2018-03-27 2018-08-14 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路及显示装置
CN110503927B (zh) * 2018-05-16 2020-11-10 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN110875002B (zh) * 2018-08-30 2021-04-13 合肥鑫晟光电科技有限公司 栅极驱动单元及其驱动方法、栅极驱动电路、显示装置
CN111161689B (zh) * 2020-02-12 2021-07-06 武汉华星光电技术有限公司 一种goa电路及其显示面板
EP4152305A4 (en) 2020-05-13 2023-07-26 BOE Technology Group Co., Ltd. DISPLAY SUBSTRATE, METHOD OF MANUFACTURE AND DISPLAY DEVICE
CN114495783A (zh) * 2020-10-27 2022-05-13 京东方科技集团股份有限公司 栅极驱动单元、栅极驱动电路、栅极驱动方法和显示装置
US11694629B2 (en) * 2021-05-12 2023-07-04 LG Display Co., Lid. Gate driver and electroluminescent display apparatus including the same
WO2024065077A1 (en) * 2022-09-26 2024-04-04 Boe Technology Group Co., Ltd. Scan circuit and display apparatus

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020075729A1 (en) * 2000-12-20 2002-06-20 Hynix Semiconductor Inc. Bitline pull-up circuit for compensating leakage current
US20100177082A1 (en) * 2009-01-13 2010-07-15 Soong-Yong Joo Gate driving circuit and display apparatus having the same
CN105118417A (zh) * 2015-09-25 2015-12-02 京东方科技集团股份有限公司 一种移位寄存器、其驱动方法、栅极驱动电路及显示装置
CN106128347A (zh) * 2016-07-13 2016-11-16 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN106486049A (zh) * 2017-01-04 2017-03-08 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、goa电路和显示装置
CN106940977A (zh) * 2017-05-16 2017-07-11 京东方科技集团股份有限公司 移位寄存器、阵列基板栅极驱动电路和显示装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI421872B (zh) * 2009-03-24 2014-01-01 Au Optronics Corp 能降低耦合效應之移位暫存器
CN103065578B (zh) * 2012-12-13 2015-05-13 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路和显示装置
CN103198783B (zh) * 2013-04-01 2015-04-29 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器和显示装置
TWI512703B (zh) * 2014-03-06 2015-12-11 Au Optronics Corp 移位暫存電路及移位暫存器
CN105528983B (zh) * 2016-01-25 2018-07-17 武汉华星光电技术有限公司 扫描驱动电路及具有该电路的平面显示装置
CN105609040A (zh) * 2016-03-22 2016-05-25 京东方科技集团股份有限公司 移位寄存单元、移位寄存器及方法、驱动电路、显示装置
CN105741802B (zh) * 2016-03-28 2018-01-30 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN106023919B (zh) * 2016-06-30 2019-01-18 京东方科技集团股份有限公司 移位寄存器及其驱动方法、驱动电路和显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020075729A1 (en) * 2000-12-20 2002-06-20 Hynix Semiconductor Inc. Bitline pull-up circuit for compensating leakage current
US20100177082A1 (en) * 2009-01-13 2010-07-15 Soong-Yong Joo Gate driving circuit and display apparatus having the same
CN105118417A (zh) * 2015-09-25 2015-12-02 京东方科技集团股份有限公司 一种移位寄存器、其驱动方法、栅极驱动电路及显示装置
CN106128347A (zh) * 2016-07-13 2016-11-16 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN106486049A (zh) * 2017-01-04 2017-03-08 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、goa电路和显示装置
CN106940977A (zh) * 2017-05-16 2017-07-11 京东方科技集团股份有限公司 移位寄存器、阵列基板栅极驱动电路和显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114217857A (zh) * 2022-02-21 2022-03-22 深圳云豹智能有限公司 一种数据处理电路、系统及数据处理方法
CN114217858A (zh) * 2022-02-21 2022-03-22 深圳云豹智能有限公司 一种数据处理电路、系统及数据处理方法

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