US10643729B2 - Shift register and method of driving the same, gate driving circuit, and display device - Google Patents
Shift register and method of driving the same, gate driving circuit, and display device Download PDFInfo
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- US10643729B2 US10643729B2 US16/144,707 US201816144707A US10643729B2 US 10643729 B2 US10643729 B2 US 10643729B2 US 201816144707 A US201816144707 A US 201816144707A US 10643729 B2 US10643729 B2 US 10643729B2
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- 238000000034 method Methods 0.000 title claims description 31
- 238000004146 energy storage Methods 0.000 claims description 23
- 239000003990 capacitor Substances 0.000 claims description 12
- 238000010586 diagram Methods 0.000 description 11
- 230000000694 effects Effects 0.000 description 8
- 238000001514 detection method Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
- G11C19/287—Organisation of a multiplicity of shift registers
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
Definitions
- the present disclosure relates to the field of display technologies, and in particular, to a shift register and a method of driving the same, a gate driving circuit, and a display device.
- a shift register in an aspect, includes a pull-up node, a pull-down node, and a compensation sub-circuit.
- the pull-up node is configured to control a signal output terminal of the shift register to output a gate scanning signal
- the pull-down node is configured to stop the signal output terminal of the shift register from outputting the gate scanning signal.
- the compensation sub-circuit is connected to the pull-up node and/or the pull-down node, a compensation signal terminal, and a common voltage terminal.
- the compensation sub-circuit is configured to output a voltage from the compensation signal terminal to an output terminal of the compensation sub-circuit under the control of a signal from the pull-up node and/or a signal from the pull-down node.
- the output terminal of the compensation sub-circuit is connected to the common voltage terminal.
- the shift register further includes a compensation control sub-circuit connected to a compensation control terminal.
- the compensation control sub-circuit is further connected between the output terminal of the compensation sub-circuit and the common voltage terminal, and the compensation control sub-circuit is configured to output a voltage from the output terminal of the compensation sub-circuit to the common voltage terminal under the control of a signal from the compensation control terminal.
- the compensation sub-circuit includes a first transistor.
- a gate electrode of the first transistor is connected to the pull-down node or the pull-up node, a first electrode of the first transistor is connected to the compensation signal terminal, and a second electrode of the first transistor is connected to the common voltage terminal as the output terminal of the compensation sub-circuit.
- the compensation sub-circuit includes a first transistor and a second transistor.
- a gate electrode of the first transistor is connected to the pull-down node, a first electrode of the first transistor is connected to the compensation signal terminal, and a second electrode of the first transistor is connected to the common voltage terminal as the output terminal of the compensation sub-circuit.
- a gate electrode of the second transistor is connected to the pull-up node, a first electrode of the second transistor is connected to the compensation signal terminal, and a second electrode of the second transistor is connected to the common voltage terminal as the output terminal of the compensation sub-circuit.
- the compensation control sub-circuit includes a third transistor.
- a gate electrode of the third transistor is connected to the compensation control terminal, a first electrode of the third transistor is connected to the output terminal of the compensation sub-circuit, and a second electrode of the third transistor is connected to the common voltage terminal.
- the shift register further includes an output sub-circuit, a pull-down sub-circuit, a pull-up control sub-circuit, a reset sub-circuit, a first pull-down control sub-circuit, a second pull-down control sub-circuit, and an energy storage sub-circuit.
- the output sub-circuit is connected to a clock signal terminal, the pull-up node, and the signal output terminal, and the output sub-circuit is configured to output a voltage from the clock signal terminal to the signal output terminal under the control of a signal from the pull-up node.
- the pull-down sub-circuit is connected to the pull-down node, a first voltage terminal, and the signal output terminal, and the pull-down sub-circuit is configured to output a voltage from the first voltage terminal to the signal output terminal under the control of a signal from the pull-down node.
- the pull-up control sub-circuit is connected to the pull-up node, a signal input terminal, and a second voltage terminal, and the pull-up control sub-circuit is configured to output a voltage from the second voltage terminal to the pull-up node under the control of a signal from the signal input terminal.
- the reset sub-circuit is connected to a reset signal terminal, a third voltage terminal, and the pull-up node, and the reset sub-circuit is configured to output a voltage from the third voltage terminal to the pull-up node under the control of a signal from the reset signal terminal.
- the first pull-down control sub-circuit is connected to the first voltage terminal, the pull-up node, and the pull-down node, and the first pull-down control sub-circuit is configured to output a voltage from the first voltage terminal to the pull-down node under the control of a signal from the pull-up node.
- the second pull-down control sub-circuit is connected to the first voltage terminal, a fourth voltage terminal, the pull-up node, and the pull-down node, and the second pull-down control sub-circuit is configured to output a voltage from the fourth voltage terminal to the pull-down node under the control of a signal from the fourth voltage terminal; or, the second pull-down control sub-circuit is configured to receive a signal from the first voltage terminal and stop outputting the voltage from the fourth voltage terminal to the pull-down node under the control of the pull-up node.
- the energy storage sub-circuit is connected between the pull-up node and the signal output terminal, and the energy storage sub-circuit is configured to store a voltage of the pull-up node or to charge the pull-up node.
- the shift register further comprises a first noise-removal sub-circuit, and/or a second noise-removal sub-circuit.
- the first noise-removal sub-circuit is connected to the first voltage terminal, the pull-up node, and the pull-down node, and the first noise-removal sub-circuit is configured to output a voltage from the first voltage terminal to the pull-up node under the control of a signal from the pull-down node.
- the second noise-removal sub-circuit is connected to an initial signal terminal, the first voltage terminal, and the pull-up node, and the second noise-removal sub-circuit is configured to output a voltage from the first voltage terminal to the pull-up node under the control of a signal from the initial signal terminal.
- the output sub-circuit comprises a fourth transistor; a gate electrode of the fourth transistor is connected to the pull-up node, a first electrode of the fourth transistor is connected to the clock signal terminal, and a second electrode of the fourth transistor is connected to the signal output terminal.
- the pull-down sub-circuit comprises a fifth transistor; a gate electrode of the fifth transistor is connected to the pull-down node, a first electrode of the fifth transistor is connected to the first voltage terminal, and a second electrode of the fifth transistor is connected to the signal output terminal.
- the pull-up control sub-circuit comprises a sixth transistor; a gate electrode of the sixth transistor is connected to the signal input terminal, a first electrode of the sixth transistor is connected to the second voltage terminal, and a second electrode of the sixth transistor is connected to the pull-up node.
- the reset sub-circuit comprises a seventh transistor; a gate electrode of the seventh transistor is connected to the reset signal terminal, a first electrode of the seventh transistor is connected to the third voltage terminal, and a second electrode of the seventh transistor is connected to the pull-up node.
- the first pull-down control sub-circuit comprises an eighth transistor; a gate electrode of the eighth transistor is connected to the pull-up node, a first electrode of the eighth transistor is connected to the first voltage terminal, and a second electrode of the eighth transistor is connected to the pull-down node.
- the second pull-down control sub-circuit comprises a ninth transistor, a tenth transistor, and an eleventh transistor. A gate electrode of the ninth transistor is connected to the pull-up node, a first electrode of the ninth transistor is connected to the first voltage terminal, and a second electrode of the ninth transistor is connected to a gate electrode of the eleventh transistor.
- a gate electrode and a first electrode of the tenth transistor are connected to the fourth voltage terminal, and a second electrode of the tenth transistor is connected to the gate electrode of the eleventh transistor.
- a first electrode of the eleventh transistor is connected to the fourth voltage terminal, and a second electrode of the eleventh transistor is connected to the pull-down node.
- the energy storage sub-circuit comprises a first capacitor; one end of the first capacitor is connected to the pull-up node, and an opposite end of the first capacitor is connected to the signal output terminal.
- the first noise-removal sub-circuit comprises a twelfth transistor.
- a gate electrode of the twelfth transistor is connected to the pull-down node, a first electrode of the twelfth transistor is connected to the first voltage terminal, and a second electrode of the twelfth transistor is connected to the pull-up node.
- the second noise-removal sub-circuit comprises a thirteenth transistor. A gate electrode of the thirteenth transistor is connected to the initial signal terminal, a first electrode of the thirteenth transistor is connected to the first voltage terminal, and a second electrode of the thirteenth transistor is connected to the pull-up node.
- a gate driving circuit in another aspect, includes at least two shift registers described in the above aspect connected in cascade.
- a signal input terminal of a first-stage shift register is connected to a start signal terminal. Except for the first-stage shift register, a signal output terminal of a shift register in a previous stage is connected to a signal input terminal of a shift register in a next stage. Except for a last-stage shift register, a signal output terminal of a shift register in a next stage is connected to a reset signal terminal of a shift register in a previous stage.
- a reset signal terminal of the last-stage shift register is connected to the start signal terminal.
- a display device in yet another aspect, includes at least one common electrode and the gate driving circuit described above. And at least one of common voltage terminals of the gate driving circuit is connected to at least one of the at least one common electrode.
- a method of driving the shift register described in the above aspect includes: in a first phase, outputting, by the pull-up control sub-circuit, a voltage from the second voltage terminal to the pull-up node under a control of a signal from the input signal terminal, and storing the voltage from the second voltage terminal to the energy storage sub-circuit; in a second phase, outputting, by the energy storage sub-circuit, the voltage stored in the first phase to the pull-up node, controlling, by the pull-up node, the output sub-circuit to be turned on, and outputting, by the output sub-circuit, a voltage from the clock signal terminal to the signal output terminal; in a third phase, outputting, by the reset sub-circuit, a voltage from the third voltage terminal to the pull-up node under the control of a signal from the reset signal terminal; outputting, by the second pull-down control sub-circuit, a voltage from the fourth voltage terminal to the pull-down node under the
- the compensation sub-circuit In a case where the compensation sub-circuit is connected to the pull-up node, in the first phase and the second phase, the compensation sub-circuit is turned on under the control of a signal from the pull-up node, and outputs a voltage from the compensation signal terminal to an output terminal of the compensation sub-circuit. In a case where the compensation sub-circuit is connected to the pull-down node, from the third phase to the start of the next image frame, the compensation sub-circuit is turned on under the control of a signal from the pull-down node, and outputs a voltage from the compensation signal terminal to an output terminal of the compensation sub-circuit.
- the method further comprises: determining whether a voltage of the common voltage terminal needs to be compensated; and outputting, by the compensation control sub-circuit, a voltage from the output terminal of the compensation sub-circuit to the common voltage terminal if compensation is required.
- FIG. 1 is a schematic diagram showing a structure of a shift register according to some embodiments of the present disclosure
- FIG. 2 is a schematic diagram showing a structure of another shift register according to some embodiments of the present disclosure
- FIG. 3 is a schematic diagram showing a structure of yet another shift register according to some embodiments of the present disclosure.
- FIG. 4 is a schematic diagram showing a structure of yet another shift register according to some embodiments of the present disclosure.
- FIG. 5 is a schematic diagram showing a structure of yet another shift register according to some embodiments of the present disclosure.
- FIG. 6 a is a schematic diagram showing a structure of yet another shift register according to some embodiments of the present disclosure.
- FIG. 6 b is a schematic diagram showing a structure of yet another shift register according to some embodiments of the present disclosure.
- FIG. 7 is a schematic diagram showing a structure of a gate driving circuit according to some embodiments of the present disclosure.
- FIG. 8 is a timing diagram of control signals of a shift register according to some embodiments of the present disclosure.
- FIG. 9 is a flowchart of a compensation process according to some embodiments of the present disclosure.
- FIG. 10 is a flowchart of another compensation process according to some embodiments of the present disclosure.
- FIG. 11 is a schematic diagram of an arrangement manner of a common electrode according to some embodiments of the present disclosure.
- FIG. 12 a is a variation curve of common voltages from a distal end to a proximal end when a common electrode is not compensated according to some embodiments of the present disclosure
- FIG. 12 b is a variation curve of common voltages from a distal end to a proximal end after a common electrode is compensated according to some embodiments of the present disclosure.
- FIG. 13 is a schematic diagram of another arrangement manner of common electrodes according to some embodiments of the present disclosure.
- the supply load of a common electrode in such display devices is higher than that in common display devices, and the distances between different positions on the common electrode and the voltage source for supplying the voltage are not the same.
- the voltages applied to different positions on the common electrode are different, thereby affecting the display effect of the display devices.
- the display screen may appear greenish; or, for a touch and display driver integration (TDDI) product, there may be horizontal lines corresponding to the touch pattern on the display screen.
- TDDI touch and display driver integration
- the shift register includes a pull-up node PU and a pull-down node PD.
- the pull-up node PU is configured to control a signal output terminal Output of the shift register to output a gate scanning signal
- the pull-down node PD is configured to stop the signal output terminal Output of the shift register from outputting the gate scanning signal.
- the shift register further includes a compensation sub-circuit 101 .
- the compensation sub-circuit 101 is connected to the pull-up node PU and/or the pull-down node PD, and a compensation signal terminal Vcp.
- the compensation sub-circuit 101 is configured to output a voltage from the compensation signal terminal Vcp (i.e., a compensation voltage) to an output terminal O of the compensation sub-circuit under the control of a signal from the pull-up node and/or the pull-down node.
- the output terminal O of the compensation sub-circuit is connected to a common voltage terminal Vcom.
- the pull-up node PU is connected to an output sub-circuit 102 .
- the output sub-circuit 102 is turned on through the pull-up node PU, so as to output a gate scanning signal (for example, a high level signal) through the signal output terminal Output.
- the pull-down node PD is connected to a pull-down sub-circuit 103 .
- the pull-down sub-circuit 103 is turned on through the pull-down node PD, so as to output a termination signal (for example, a low level signal) through the signal output terminal Output.
- the common voltage terminal Vcom is generally electrically connected to a common electrode line of the display device, and the common electrode line is electrically connected to a common electrode.
- the compensation voltage of the compensation signal terminal Vcp output to the output terminal O of the compensation sub-circuit 101 is transmitted to a common electrode corresponding to the output terminal O through the common electrode line, so as to compensate a common voltage of the common electrode.
- the common electrode corresponding to the output terminal O of the compensation sub-circuit 101 refers to a common electrode located at a position of a row of sub-pixels controlled by a gate line connected to the signal output terminal Output of the shift register where the compensation sub-circuit 101 is located.
- the common electrodes at the locations of all sub-pixels are the same common electrode.
- the display panel has a planar common electrode 200 as shown in FIG. 11 .
- a circle of common electrode lines 201 and a voltage source 202 for supplying a common voltage to the common electrode 200 through the common electrode lines 201 are provided on the periphery of the common electrode 200 .
- a common voltage received by a common electrode line 201 close to the voltage source 202 (at a lower end, that is, the common electrode line 201 at a proximal end) is relatively stable, and a common voltage received by a common electrode line 201 away from the voltage source 202 (at an upper end, that is, the common electrode line 201 at a distal end) differs greatly from a voltage provided by the voltage source 202 , and is thus subjected to a larger pull.
- the common voltage VCOM on the common electrode line 201 at a distal end is pulled to a greater extent. The closer to the proximal end, the common voltage VCOM on the common electrode line 201 is pulled to a smaller extent.
- the common voltage terminal Vcom connected to the output terminal O of the compensation sub-circuit 101 of the shift register may be connected to the common electrode line 201 at the distal end, so as to compensate the common voltage on a portion of the common electrode 200 that is away from the voltage source 202 .
- the common voltage terminal Vcom connected to the output terminal O of the compensation sub-circuit 101 of the shift register may be connected to the common electrode lines 201 at the proximal end and the distal end to realize compensation of the common voltage, so that after compensation, the common voltages on the common electrode lines 201 from the proximal end to the distal end form approximately a straight line as shown in FIG. 12 b.
- the common electrodes 200 at the locations of the sub-pixels are not the same common electrode 200 .
- the display panel has a plurality of block-shaped touch electrodes TX, and each touch electrode TX is also used as the common electrode 200 in a display phase.
- TDDI touch and display driver integration
- the common voltage terminal Vcom connected to the output terminal O of the compensation sub-circuit 101 in the shift register is connected to a touch lead which is also used as the common electrode line 201 , so that a common voltage of a common electrode 200 that needs to be compensated, for example, a common voltage of the common electrode 200 at the distal end, is compensated through the common electrode line 201 .
- the description “the compensation sub-circuit 101 is connected to the pull-up node PU and/or the pull-down node PD, and a compensation signal terminal Vcp” refers to that the compensation sub-circuit 101 is connected to the pull-up node PU and the compensation signal terminal Vcp, so that the compensation sub-circuit 101 is able to output a voltage from the compensation signal terminal Vcp (i.e., a compensation voltage) to the output terminal O of the compensation sub-circuit under the control of a signal from the pull-up node PU.
- this description refers to that the compensation sub-circuit 101 is connected to the pull-down node PD and the compensation signal terminal Vcp, so that the compensation sub-circuit 101 is able to output a voltage from the compensation signal terminal Vcp (i.e., a compensation voltage) to the output terminal O of the compensation sub-circuit under the control of a signal from the pull-down node PD.
- a voltage from the compensation signal terminal Vcp i.e., a compensation voltage
- the description refers to that the compensation sub-circuit 101 is connected to the pull-up node PU, the pull-down node PD and the compensation signal terminal Vcp, so that the compensation sub-circuit 101 is able to output a voltage of the compensation signal terminal Vcp (i.e., a compensation voltage) to the output terminal O of the compensation sub-circuit under the control of signals from the pull-up node PU and the pull-down node PD.
- a voltage of the compensation signal terminal Vcp i.e., a compensation voltage
- the pull-up node PU and the pull-down node PD in the shift register are generally in opposite states. For example, when the pull-up node PU is in an active state (e.g., a high level state), the pull-down node PD is in an inactive state (e.g., a low level state). Alternatively, when the pull-up node PU is in an inactive state (e.g., a low level state), the pull-down node PD is in an active state (e.g., a high level state).
- the shift register in a case where the shift register is applied to a display device, in the process of scanning the plurality of gate lines line by line through the plurality of shift registers connected in cascade, in a time period of an image frame, when one gate line receives a gate scanning signal output by the shift register via the signal output terminal Output, all remaining gate lines do not receive gate scanning signals, therefore when a pull-up node PU of a shift register in a certain stage in the plurality of shift registers connected in cascade is in an active state, the pull-up nodes PU of most of remaining shift registers are in an inactive state. Therefore, in the time period of an image frame, the pull-up node PU in the shift register is in an active state for a much shorter time than the pull-down node PD.
- the compensation sub-circuit 101 is connected to the pull-up node PU, the pull-down node PD, and the compensation signal terminal Vcp, so that in the time period of an image frame, the common electrode may be compensated via the compensation signal terminal Vcp under the action of the pull-up node PU when the pull-up node PU is in an active state.
- the common electrode may be compensated via the compensation signal terminal Vcp under the action of the pull-down node PD that is in an active state.
- the compensation sub-circuit 101 is connected to the pull-down node PD and the compensation signal terminal Vcp, so that the common electrode may be compensated for a long time during a long period in which the pull-down node PD is in an active state.
- a potential of the pull-up node PU may be prevented from being pulled by the clock signal terminal CLK via the output sub-circuit 102 , which may lead the pull-up node PU not to be affected by external coupling, and thus the voltage of the pull-up node PU may be stable, thereby enhancing a compensation effect of the compensation sub-circuit 101 .
- the compensation sub-circuit 101 may be turned on via the pull-up node PU and/or the pull-down node PD, so that the compensation voltage of the compensation signal terminal Vcp may be output to a corresponding common electrode at positions of a corresponding row of sub-pixels in the display device to perform voltage compensation according to actually detected voltage of the common electrode.
- the shift register further includes a compensation control sub-circuit 1011 connected to a compensation control terminal SW.
- the compensation control sub-circuit 1011 is further connected between the output terminal O of the compensation sub-circuit 101 and the common voltage terminal Vcom, and the compensation control sub-circuit 1011 is configured to output a voltage from the output terminal O of the compensation sub-circuit to the common voltage terminal Vcom under the control of a signal from the compensation control terminal SW.
- the compensation sub-circuit 101 may be disposed in the following manner.
- the compensation sub-circuit 101 includes a first transistor M 1 .
- a gate electrode of the first transistor M 1 is connected to the pull-down node PD (or the pull-up node PU), a first electrode of the first transistor M 1 is connected to the compensation signal terminal Vcp, and a second electrode of the first transistor M 1 is connected to the common voltage terminal Vcom as the output terminal O of the compensation sub-circuit.
- the arrangement manner of the compensation sub-circuit 101 is only described by taking an example in which the gate electrode of the first transistor M 1 is connected to the pull-down node PD. In some other embodiments, the gate electrode of the first transistor M 1 is connected to the pull-up node PU, which is not described with reference to a drawing herein again.
- the compensation sub-circuit 101 includes a first transistor M 1 and a second transistor M 2 .
- a gate electrode of the first transistor M 1 is connected to the pull-down node PD, a first electrode of the first transistor M 1 is connected to the compensation signal terminal Vcp, and a second electrode of the first transistor M 1 is connected to the common voltage terminal Vcom as the output terminal O of the compensation sub-circuit.
- a gate electrode of the second transistor M 2 is connected to the pull-up node PU, a first electrode of the second transistor M 2 is connected to the compensation signal terminal Vcp, and a second electrode of the second transistor M 2 is connected to the common voltage terminal Vcom as the output terminal O of the compensation sub-circuit.
- the compensation control sub-circuit 1011 includes a third transistor M 3 .
- a gate electrode of the third transistor M 3 is connected to the compensation control terminal SW, a first electrode of the third transistor M 3 is connected to the output terminal O of the compensation sub-circuit, and a second electrode of the third transistor M 3 is connected to the common voltage terminal Vcom.
- the shift register includes a compensation control sub-circuit 1011
- a structure of the shift register is only described in FIG. 6 a by taking an example in which the compensation sub-circuit 101 is connected to the pull-up node PU, the pull-down node PD, and the compensation signal terminal Vcp.
- the compensation control sub-circuit 1011 may be arranged in a same manner as the compensation control sub-circuit 1011 shown in FIG. 6 a , which will not be described with reference to a drawing herein again.
- connection manner of the compensation sub-circuit 101 and the compensation control sub-circuit 1011 and exemplary arrangement manners of the two sub-circuits can be applied to any shift register. Therefore, any arrangement manners including the connection manner of the compensation sub-circuit 101 and the compensation control sub-circuit 1011 and the exemplary arrangements of the two sub-circuits described above shall be included in the protection scope of the present disclosure.
- a shift register including a compensation sub-circuit 101 (an example is taken in which the compensation sub-circuit 101 is connected to the pull-up node PU, the pull-down node PD, and the compensation signal terminal Vcp) and a compensation control sub-circuit 1011 is provided.
- the shift register further includes an output sub-circuit 102 , a pull-down sub-circuit 103 , a pull-up control sub-circuit 104 , a reset sub-circuit 105 , a first pull-down control sub-circuit 106 , a second pull-down control sub-circuit 107 , and an energy storage sub-circuit 108 .
- the output sub-circuit 102 is connected to a clock signal terminal CLK, the pull-up node PU, and the signal output terminal Output.
- the output sub-circuit 102 is configured to output a voltage from the clock signal terminal CLK to the signal output terminal Output under the control of a signal from the pull-up node PU.
- the pull-down sub-circuit 103 is connected to the pull-down node PD, a first voltage terminal VGL, and the signal output terminal Output.
- the pull-down sub-circuit 103 is configured to output a voltage from the first voltage terminal VGL to the signal output terminal Output under the control of a signal from the pull-down node PD.
- a constant DC low level is input via the first voltage terminal VGL.
- a potential of the signal output terminal Output may be pulled down to the low level provided via the first voltage terminal VGL.
- the pull-up control sub-circuit 104 is connected to the pull-up node PU, a signal input terminal Input, and a second voltage terminal VDD.
- the pull-up control sub-circuit 104 is configured to output a voltage from the second voltage terminal VDD to the pull-up node PU under the control of a signal from the signal input terminal Input.
- a constant DC high level is input via the second voltage terminal VDD.
- the pull-up control sub-circuit 104 when the pull-up control sub-circuit 104 is turned on under the control of the signal input terminal Input, the high level provided via the second voltage terminal VDD may be output to the pull-up node PU, so as to charge the pull-up node PU.
- the reset sub-circuit 105 is connected to a reset signal terminal RESET, a third voltage terminal VSS, and the pull-up node PU.
- the reset sub-circuit 105 is configured to output a voltage from the third voltage terminal VSS to the pull-up node PU under the control of a signal from the reset signal terminal RESET.
- a constant DC low level is input via the third voltage terminal VSS.
- the reset sub-circuit 105 is turned on under the control of the reset signal terminal RESET, so that the low level provided via the third voltage terminal VSS may be transmitted to the pull-up node PU to reset a potential of the pull-up node PU.
- the first pull-down control sub-circuit 106 is connected to the first voltage terminal VGL, the pull-up node PU, and the pull-down node PD.
- the first pull-down control sub-circuit 106 is configured to output the voltage from the first voltage terminal VGL to the pull-down node PD under the control of a signal from the pull-up node PU. In a case where a low level is input via the first voltage terminal VGL, a potential of the pull-down node PD may be reset.
- the second pull-down control sub-circuit 107 is connected to the first voltage terminal VGL, a fourth voltage terminal VGH, the pull-up node PU, and the pull-down node PD.
- the second pull-down control sub-circuit 107 is configured to output a voltage from the fourth voltage terminal VGH to the pull-down node PD under the control of a signal from the fourth voltage terminal VGH.
- the second pull-down control sub-circuit 107 is configured to receive a signal from the first voltage terminal VGL under the control of the pull-up node PU and stop outputting the voltage from the fourth voltage terminal VGH to the pull-down node PD.
- the energy storage sub-circuit 108 is connected between the pull-up node PU and the signal output terminal Output.
- the energy storage sub-circuit 108 is configured to store a voltage from the pull-up node PU, or to charge the pull-up node PU.
- the shift register further includes a first noise-removal sub-circuit 109 , and/or, a second noise-removal sub-circuit 1010 .
- the first noise-removal sub-circuit 109 is connected to the first voltage terminal VGL, the pull-up node PU, and the pull-down node PD.
- the first noise-removal sub-circuit 109 is configured to output a voltage from the first voltage terminal VGL to the pull-up node PU under the control of a signal from the pull-down node PD, so as to remove noise of the pull-up node PU.
- the second noise-removal sub-circuit 1010 is connected to an initial signal terminal STV, the first voltage terminal VGL, and the pull-up node PU.
- the second noise-removal sub-circuit 1010 is configured to output a voltage from the first voltage terminal VGL to the pull-up node PU under the control of a signal from the initial signal terminal STV, so as to remove noise of the pull-up node PU.
- the output sub-circuit 102 includes a fourth transistor M 4 .
- a gate electrode of the fourth transistor M 4 is connected to the pull-up node PU, a first electrode of the fourth transistor M 4 is connected to the clock signal terminal CLK, and a second electrode of the fourth transistor M 4 is connected to the signal output terminal Output.
- the pull-down sub-circuit 103 includes a fifth transistor M 5 .
- a gate electrode of the fifth transistor M 5 is connected to the pull-down node PD, a first electrode of the fifth transistor M 5 is connected to the first voltage terminal VGL, and a second electrode of the fifth transistor M 5 is connected to the signal output terminal Output.
- the pull-up control sub-circuit 104 includes a sixth transistor M 6 .
- a gate electrode of the sixth transistor M 6 is connected to the signal input terminal Input, a first electrode of the sixth transistor M 6 is connected to the second voltage terminal VDD, and a second electrode of the sixth transistor M 6 is connected to the pull-up node PU.
- the reset sub-circuit 105 includes a seventh transistor M 7 .
- a gate electrode of the seventh transistor M 7 is connected to the reset signal terminal RESET, a first electrode of the seventh transistor M 7 is connected to the third voltage terminal VSS, and a second electrode of the seventh transistor M 7 is connected to the pull-up node PU.
- the first pull-down control sub-circuit 106 includes an eighth transistor M 8 .
- a gate electrode of the eighth transistor M 8 is connected to the pull-up node PU, a first electrode of the eighth transistor M 8 is connected to the first voltage terminal VGL, and a second electrode of the eighth transistor M 8 is connected to the pull-down node PD.
- the second pull-down control sub-circuit 107 includes a ninth transistor M 9 , a tenth transistor M 10 , and an eleventh transistor M 11 .
- a gate electrode of the ninth transistor M 9 is connected to the pull-up node PU, a first electrode of the ninth transistor M 9 is connected to the first voltage terminal VGL, and a second electrode of the ninth transistor M 9 is connected to a gate electrode of the eleventh transistor M 11 .
- a gate electrode and a first electrode of the tenth transistor M 10 are connected to the fourth voltage terminal VGH, and a second electrode of the tenth transistor M 10 is connected to the gate electrode of the eleventh transistor M 11 .
- a first electrode of the eleventh transistor M 11 is connected to the fourth voltage terminal VGH, and a second electrode of the eleventh transistor M 11 is connected to the pull-down node PD.
- the energy storage sub-circuit 108 includes a first capacitor C 1 .
- One end of the first capacitor C 1 is connected to the pull-up node PU, and an opposite end of the first capacitor C 1 is connected to the signal output terminal Output.
- the first noise-removal sub-circuit 109 includes a twelfth transistor M 12 .
- a gate electrode of the twelfth transistor M 12 is connected to the pull-down node PD, a first electrode of the twelfth transistor M 12 is connected to the first voltage terminal VGL, and a second electrode of the twelfth transistor M 12 is connected to the pull-up node PU.
- the second noise-removal sub-circuit 1010 includes a thirteenth transistor M 13 .
- a gate electrode of the thirteenth transistor M 13 is connected to the initial signal terminal STV, a first electrode of the thirteenth transistor M 13 is connected to the first voltage terminal VGL, and a second electrode of the thirteenth transistor M 13 is connected to the pull-up node PU.
- Some embodiments of the present disclosure provide a gate driving circuit fabricated using a gate-on-array (GOA) technology.
- the gate driving circuit includes at least two shift registers described above connected in cascade, and has the same structure and advantageous effects as the shift register provided by the foregoing embodiments. Since the structure and advantageous effects of the shift register have been described in detail in the foregoing embodiments, the structure and advantageous effects of the gate driving circuit will not be repeated herein.
- a signal input terminal Input of a first-stage shift register RS 1 is connected to a start signal terminal STV.
- a signal output terminal Output of a shift register in a previous stage RS(n ⁇ 1) is connected to a signal input terminal Input of a shift register in a next stage RS(n).
- a start signal is input via the start signal terminal STV.
- the entire gate driving circuit starts to scan gate lines (G 1 , G 2 . . . Gn) line by line.
- a signal output terminal Output of a shift register in a next stage RS(n) is connected to a reset signal terminal RESET of a shift register in a previous stage RS(n ⁇ 1).
- a reset signal terminal RESET of the last-stage shift register is connected to the start signal terminal STV.
- a signal terminal for providing a reset signal for the reset signal terminal RESET of the last-stage shift register is independently provided, and the signal terminal is connected to the reset signal terminal RESET of the last-stage shift register.
- the shift register includes the second noise-removal sub-circuit 1010
- the noise on pull-up nodes PD in other shift registers may be removed when the first-stage shift register in the gate driving circuit is turned on through the initial signal terminal STV. That is to say, at the start of an image frame, noise of the entire screen may be removed through the second noise-removal sub-circuit 1010 , so that the coupled noise generated by signals from the clock signal terminal CLK received by pull-up nodes PU in the entire gate driving circuit and the noise caused by external factors may be eliminated or reduced, thereby ensuring the stability of the signal output terminal Output.
- the actual first voltage terminal VGL and the third voltage terminal VSS may be the same voltage terminal
- the second voltage terminal VDD and the fourth voltage terminal VGH may be the same voltage terminal
- FIGS. 4 to 6 a enable forward scanning (e.g., scanning the gate lines line by line from top to bottom).
- the gate electrode of the sixth transistor M 6 is connected to the reset signal terminal RESET, and the first electrode of the sixth transistor M 6 is connected to the third voltage terminal VSS.
- the gate electrode of the seventh transistor M 7 is connected to the signal input terminal Input, and the first electrode of the seventh transistor M 7 is connected to the second voltage terminal VDD.
- Forward scanning is described above by taking the structure shown in FIG. 6 a as an example. Arrangement manners shown in FIGS. 4 and 5 are similarly available, and will not be further described herein.
- Some embodiments of the present disclosure provide a display device, which includes at least one common electrode and the gate driving circuit described above. At least one of common voltage terminals in the gate driving circuit is connected to at least one of the at least one common electrode (through at least one common electrode line). Since the display device includes the gate driving circuit described above, it has the same structure and advantageous effects as the gate driving circuit provided in the foregoing embodiments. Since the structure and advantageous effects of the gate driving circuit have been described in detail in the foregoing embodiments, the structure and advantageous effects of the display device will not be repeated herein.
- the display device includes at least a liquid crystal display panel or an organic light-emitting diode display panel.
- the display device is any product or component having a display function such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, or a tablet computer.
- Some embodiments of the present disclosure provide a method of driving the shift register described above. Steps of the method of driving the shift register in different phases of an image frame are described in detail below with reference to FIG. 8 and in combination with practical applications of the shift registers in the gate driving circuit and the display device, and turned-on and cut-off states of each transistor in each sub-circuit in the shift register shown in FIG. 6 a.
- the method is described by taking an example in which a high level is input via the second voltage terminal VDD and the fourth voltage terminal VGH, and a low level is input via the first voltage terminal VGL and the third voltage terminal VSS.
- turn-on and cut-off processes of transistors are described by taking an example in which all transistors are N-type transistors.
- the method of driving the shift register includes the following four steps described in detail below.
- a first phase P 1 of the image frame is a first phase P 1 of the image frame
- the pull-up control sub-circuit 104 outputs a voltage from the second voltage terminal VDD to the pull-up node PU under the control of a signal from the input signal terminal Input, and the voltage from the second voltage terminal VDD is stored to the energy storage sub-circuit 108 .
- the compensation sub-circuit 101 is turned on under the control of the pull-up node PU and the compensation control sub-circuit 1011 , and outputs a voltage from the compensation signal terminal Vcp to the common voltage terminal Vcom.
- a high level is input via the signal input terminal Input, and a low level is input via the clock signal terminal CCK.
- a high level is input to the signal input terminal Input via the initial signal terminal STV, so as to make the gate driving circuit enter an active state.
- the first-stage shift register RS 1 enters a charging state (i.e., charging the pull-up node PU), and shift registers RSn other than the first-stage shift register RS 1 are in an inactive state.
- the sixth transistor M 6 in the pull-up control sub-circuit 104 is turned on and outputs the high level from the second voltage terminal VDD to the pull-up node PU to charge the pull-up node PU. Moreover, the high level from the second voltage terminal VDD is stored in the first capacitor C 1 in the energy storage sub-circuit 108 .
- the second transistor M 2 of the compensation sub-circuit 101 is turned on and outputs a compensation voltage from the compensation signal terminal Vcp to the output terminal O of the compensation sub-circuit 101 .
- whether or not the signal of the output terminal O of the compensation sub-circuit 101 is output to the common voltage terminal Vcom may be controlled depending on whether an actually detected voltage of the common voltage terminal Vcom (i.e., the common electrode) needs to be compensated.
- a detection result indicates that the voltage of the common voltage terminal Vcom needs to be compensated
- a high level is input to the compensation control terminal SW, so that the third transistor M 3 is turned on, and the compensation voltage from the output terminal O of the compensation sub-circuit 101 (i.e., the voltage of the compensation signal terminal Vcp) is output to the common voltage terminal Vcom via the third transistor M 3 for voltage compensation.
- the detection result indicates that the voltage of the common voltage terminal Vcom does not need to be compensated
- a low level is input to the compensation control terminal SW, so that the third transistor M 3 is cut off.
- the fourth transistor M 4 is turned on. Since a low level is input via the clock signal terminal CLK in this phase, the shift register outputs a low level via the signal output terminal Output. Therefore, there is no gate scanning signal output via the signal output terminal Output in this phase.
- the eighth transistor M 8 is turned on and pulls down a voltage of the pull-down node PD to a potential of the first voltage terminal VGL. Moreover, a width-to-length ratio of a channel of the ninth transistor M 9 is set to greater than a width-to-length ratio of a channel of the tenth transistor M 10 , so that a conduction capability of the ninth transistor M 9 is greater than a conduction capability of the tenth transistor M 10 .
- the ninth transistor M 9 is turned on under the control of the pull-up node PU, therefore even if the tenth transistor M 10 is also turned on, a voltage of the second electrode of the tenth transistor M 10 will be pulled down to a potential of the first voltage terminal VGL via the ninth transistor M 9 having a greater conduction capability, so that the eleventh transistor M 11 is in a cut-off state.
- the pull-down node PD is at a low level, and the twelfth transistor M 12 and the fifth transistor M 5 are cut off. In this phase, a low level is input via the reset signal terminal RESET, and the seventh transistor M 7 is cut off.
- the thirteenth transistor M 13 is turned on under the control of the initial signal terminal STV, so as to remove noise of a pull-up node PU in each stage of shift register. After entering the first phase P 1 , a low level is input via the initial signal terminal STV, and the thirteenth transistor M 13 is cut off.
- the energy storage sub-circuit 108 outputs the voltage stored in the first phase P 1 to the pull-up node PU so that the output sub-circuit 102 is turned on, and the output sub-circuit 102 outputs a voltage from the clock signal terminal CLK to the signal output terminal Output.
- the compensation sub-circuit 101 maintains in a turned-on state under the control of the pull-up node PU and the compensation control sub-circuit 1011 , and outputs a voltage from the compensation signal terminal Vcp to the common voltage terminal Vcom.
- a high level is input via the clock signal terminal CLK, and a low level is input via the signal input terminal Input.
- a first capacitor C 1 in the energy storage sub-circuit 108 outputs the high level stored in the first phase P 1 to the pull-up node PU, and under the control of the high level of the pull-up node PU, the fourth transistor M 4 in the output sub-circuit 102 is turned on and outputs the high level from the clock signal terminal CLK to the signal output terminal Output.
- a potential of the pull-up node PU may be further pulled up, so as to ensure that the fourth transistor M 4 maintains in a stable turned-on state and continuously outputs the high level from the clock signal terminal CLK to the signal output terminal Output.
- the sixth transistor M 6 Since a low level is input via the signal input terminal Input, the sixth transistor M 6 is cut off. Turned-on and cut-off states of remaining transistors are similarly available, and are not described herein again.
- a high level i.e., a gate scanning signal
- Output the signal output terminal Output in this phase.
- a third phase P 3 of the image frame is
- the reset sub-circuit 105 outputs a voltage from the third voltage terminal VSS to the pull-up node PU under the control of the reset signal terminal RESET.
- the second pull-down control sub-circuit 107 outputs a voltage from the fourth voltage terminal VGH to the pull-down node PD under the control of the fourth voltage terminal VGH.
- the pull-down sub-circuit 103 is turned on under the control of the pull-down node PD, and outputs a voltage from the first voltage terminal VGL to the signal output terminal Output.
- the compensation sub-circuit 101 is turned on under the control of the pull-down node PD and the compensation control sub-circuit 1011 , and outputs a voltage from the compensation signal terminal Vcp to the common voltage terminal Vcom.
- a high level is input via the reset signal terminal RESET in this phase.
- the high level output by a shift register in a next stage RS(n+1) via its signal output terminal Output(n+1) is input to the reset signal terminal RESET of the shift register RSn.
- a high level may be input to the reset signal terminal RESET of the last-stage shift register separately or via the start signal terminal STV.
- the seventh transistor M 7 in the reset sub-circuit 105 is turned on and outputs the low level from third voltage terminal VSS to the pull-up node PU.
- the eighth transistor M 8 in the first pull-down control sub-circuit 106 is in a cut-off state
- the ninth transistor M 9 in the second pull-down control sub-circuit 107 is in a cut-off state.
- the tenth transistor M 10 and the eleventh transistor M 11 are turned on, and the eleventh transistor M 11 outputs the high level from the fourth voltage terminal VGH to the pull-down node PD.
- the fifth transistor M 5 in the pull-down sub-circuit 103 is turned on and outputs the low level from the first voltage terminal VGL to the signal output terminal Output.
- the first transistor M 1 in the compensation sub-circuit 101 is turned on and outputs the compensation voltage from the compensation signal terminal Vcp to the output terminal O of the compensation sub-circuit 101 .
- whether the signal from the output terminal O of the compensation sub-circuit 101 is output to the common voltage terminal Vcom may be controlled depending on whether an actually detected voltage of the common voltage terminal Vcom (i.e., the common electrode) needs to be compensated.
- a high level is input via the compensation control terminal SW, so that the third transistor M 3 is turned on, and the compensation voltage from the output terminal O of the compensation sub-circuit 101 is output to the common voltage terminal Vcom via the third transistor M 3 for voltage compensation. If compensation is not needed, a low level is input via the compensation control terminal SW, so that the third transistor M 3 is cut off.
- the twelfth transistor M 12 in the first noise-removal sub-circuit 109 is turned on so as to output the low level from the first voltage terminal VGL to the pull-up node PU.
- the fourth transistor M 4 is cut off.
- a fourth phase P 4 of the image frame is
- the pull-down sub-circuit 103 maintains in a turned-on state under the control of the pull-down node PD, and outputs a voltage from the first voltage terminal VGL to the signal output terminal Output.
- the compensation sub-circuit 101 is turned on under the control of the pull-down node PD and the compensation control sub-circuit 1011 , and outputs a voltage from the compensation signal terminal Vcp to the common voltage terminal Vcom.
- the pull-up node PU maintains at a low level
- the eighth transistor M 8 in the first pull-down control sub-circuit 106 maintains in a cut-off state
- the ninth transistor M 9 in the second pull-down control sub-circuit 107 maintains in a cut-off state.
- the tenth transistor M 10 and the eleventh transistor M 11 are turned on and the eleventh transistor M 11 outputs the high level from the fourth voltage terminal VGH to the pull-down node PD.
- the fifth transistor M 5 in the pull-down sub-circuit 103 is turned on and outputs the low level from the first voltage terminal VGL to the signal output terminal Output.
- the twelfth transistor M 12 in the first noise-removal sub-circuit 109 is turned on, so as to output the low level of the first voltage terminal VGL to the pull-up node PU for noise removal.
- the fourth phase P 4 is repeated, so that the low level from the first voltage terminal VGL is continuously output via the signal output terminal Output, and the pull-down node PD maintains at a high level.
- the turned-on and cut-off states of the transistors in the compensation sub-circuit 101 and the compensation control sub-circuit 1011 are the same as in the fourth phase P 4 , and the compensation process is also the same as in the fourth phase P 4 , and details are not described herein again.
- transistors in the above embodiments are N-type transistors.
- all control signals in FIG. 8 need to be flipped, and sub-circuits or transistors connected to the second voltage terminal VDD and the fourth voltage terminal VGH in FIG. 6 a need to be connected to voltage terminals that output a low level.
- Sub-circuits or transistors connected to the first voltage terminal VGL and the third voltage terminal VSS need to be connected to voltage terminals that output a high level.
- the method of driving the shift register is described by taking an example in which the compensating sub-circuit 101 in the shift register is connected to both the pull-up node PU and the pull-down node PD, as shown in FIG. 6 a .
- the compensation sub-circuit 101 is connected to the pull-down node PD (as shown in FIG. 4 )
- the shift register includes a compensation control sub-circuit 1011
- the voltage of the output terminal of the compensation sub-circuit is output to the common voltage terminal Vcom under the control of the compensation control sub-circuit 1011 , as shown in FIG. 6 a .
- the shift register may not include a compensation control sub-circuit 1011 , as shown in FIGS. 1, 2, 4, and 5 .
- the exemplary compensation process of outputting the voltage of the output terminal of the compensation sub-circuit to the common voltage terminal Vcom under two circumstances in which the shift register of the gate driving circuit includes a compensation control sub-circuit 1011 and in which the shift register does not include a compensation control sub-circuit 1011 is further explained below.
- the shift register includes a compensation control sub-circuit 1011 , and as shown in FIG. 9 , the compensation process includes the following steps.
- step 1 the gate driving circuit is turned on, and the compensation control sub-circuits 1011 in each stage of shift register in the gate driving circuit is turned on (i.e., a high level is input via the compensation control terminal SW to turn on the third transistor M 3 , as shown in FIGS. 6 a and 6 b ).
- step 2 whether any common electrode in the display device needs to be compensated is detected.
- a compensation voltage is input to the common electrode via a compensation signal terminal Vcp in the shift register of the gate driving circuit corresponding to the common electrode if compensation is needed, and the compensation control sub-circuit 1011 is turned off (i.e., a low level is input via the compensation control terminal SW to cut off the third transistor M 3 ) if compensation is not needed.
- the shift register does not include a compensation control sub-circuit 1011 , and as shown in FIG. 10 , the compensation process includes the following steps.
- step 1 the gate driving circuit is turned on.
- step 2 whether any common electrode in the display device needs to be compensated is detected.
- a compensation voltage is input to the common electrode via a compensation signal terminal Vcp in the shift register in the gate driving circuit corresponding to the common electrode if compensation is needed, and an actual common voltage is input to the common electrode via a compensation signal terminal Vcp in the shift register in the gate driving circuit corresponding to the common electrode if compensation is not needed, so as to improve a driving capability of the common electrode.
- the detection may be an overall detection of the display device before the gate driving circuit is turned on, or the detection may be performed line by line according to how the common voltage terminal Vcom is pulled after the gate driving circuit is turned on, which is not limited in the present disclosure, and an appropriate detection mode may be selected according to actual needs.
- the compensation control sub-circuit 1011 when the gate driving circuit is turned on, the compensation control sub-circuit 1011 is also turned on.
- the compensation sub-circuit 101 it is first detected whether the voltage of the common voltage terminal Vcom (i.e., the common electrode) needs to be compensated. If compensation is needed, a compensation voltage is input to the common electrode via the compensation signal terminal Vcp. If compensation is not needed, the compensation control sub-circuit 1011 is turned off.
- Vcom common voltage terminal
- Vcp compensation signal terminal
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Also Published As
Publication number | Publication date |
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US20190096500A1 (en) | 2019-03-28 |
CN107578741B (en) | 2020-03-27 |
CN107578741A (en) | 2018-01-12 |
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