CN110164381B - Gate driving device - Google Patents

Gate driving device Download PDF

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Publication number
CN110164381B
CN110164381B CN201910436567.6A CN201910436567A CN110164381B CN 110164381 B CN110164381 B CN 110164381B CN 201910436567 A CN201910436567 A CN 201910436567A CN 110164381 B CN110164381 B CN 110164381B
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China
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signal
control signal
terminal
control
voltage regulator
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CN201910436567.6A
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CN110164381A (en
Inventor
林志隆
曾金贤
赖柏君
郑贸薰
陈奕冏
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AU Optronics Corp
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AU Optronics Corp
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The gate driving device includes a plurality of shift register circuits. In the shift register circuit of the Nth stage, the output stage circuit generates a gate driving signal of the Nth stage according to the first control signal, the second control signal and the first mode selection signal. The first voltage regulator regulates the first control signal according to the third control signal. The second voltage regulator regulates the first control signal according to a second mode selection signal, a preceding stage gate driving signal or a start pulse signal. The third voltage regulator regulates the second control signal according to the first mode selection signal. The fourth voltage regulator regulates the third control signal according to the second clock signal and the first control signal. The isolation circuit determines whether to block the second control terminal and the third control terminal according to the second mode selection signal.

Description

Gate driving device
Technical Field
The present invention relates to a gate driving device, and more particularly, to a gate driving device for driving a display panel.
Background
In the active light emitting diode pixel circuit with synchronous light emission, all pixels need to be turned on simultaneously in the compensation stage so as to compensate the variation of the on-voltage of the thin film transistors in the pixels simultaneously. In the next data writing stage, the pixel circuits are turned on column by column to write data into the pixel circuits column by column.
In the prior art, the pixel circuits emitting light synchronously have several problems. Firstly, special signals are required to be set in the pixel circuits which synchronously emit light to indicate the progress of a compensation stage and a data writing stage; second, when applied to a high-resolution display panel, a sufficiently long data writing time is required; third, when the thin film transistor is manufactured by applying the low temperature poly-silicon process in the gate driving circuit, the thin film transistor still has a relatively high electron mobility when it is turned off, and the leakage phenomenon is easily generated at the circuit node.
Disclosure of Invention
The invention provides a gate driving device which can be applied to a display panel with high resolution.
The gate driving device of the invention comprises a plurality of shift register circuits. The shift register circuits are coupled in series and respectively generate a plurality of gate driving signals, wherein the shift register circuit of the Nth stage comprises an output stage circuit, a first voltage regulator, a second voltage regulator, a third voltage regulator, a fourth voltage regulator and an isolation circuit. The output stage circuit has a first control terminal and a second control terminal for receiving the first control signal and the second control signal respectively. The output stage circuit provides a first clock pulse signal, a grid high voltage or a grid low voltage to charge an output end according to the first control signal, the second control signal and the first mode selection signal so as to generate an Nth stage grid driving signal. The first voltage regulator is coupled between the first control terminal and the third control terminal, and provides a very high voltage to regulate the first control signal according to the third control signal. The second voltage regulator is coupled to the first control end and regulates the first control signal according to a second mode selection signal, a preceding stage grid driving signal or a starting pulse signal. The third voltage regulator is coupled to the second control terminal and provides a gate high voltage to regulate the second control signal according to the first mode selection signal. The fourth voltage regulator is coupled to the third control terminal and provides the second clock signal or the gate high voltage to regulate the third control signal according to the second clock signal and the first control signal. The isolation circuit is coupled between the third control terminal and the second control terminal, and determines whether to block the second control terminal and the third control terminal according to the second mode selection signal.
Based on the above, the gate driving apparatus of the present invention adjusts the control signal on the control terminal through the plurality of voltage regulators, and controls the output stage circuit to generate the gate driving signal according to the control signal. Therefore, the grid driver can generate a plurality of grid driving signals with consistent waveforms in the compensation stage and generate a plurality of grid driving signals which are respectively enabled in sequence in the later writing stage.
The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.
Drawings
Fig. 1 shows a schematic diagram of a gate driving device according to an embodiment of the invention.
Fig. 2 is a waveform diagram illustrating an operation of the gate driving apparatus according to the embodiment of the present invention.
Fig. 3A to 3G show equivalent circuit diagrams of the shift register circuit according to the embodiment of the invention.
Wherein the accompanying drawings illustrate:
100: shift register circuit
110: output stage circuit
120-150: voltage regulator
160: isolation circuit
C1: capacitor with a capacitor element
CE1, CE2, CE 3: control terminal
CK1, CK2, CK 3: clock pulse signal
G[N]: nth stage gate drive signal
G[N-1]: preceding stage gate drive signal
OE: output end
Q[N]、P[N]、R[N]: control signal
SS, SR: mode selection signal
ST: initial pulse signal
T1-T11: transistor with a metal gate electrode
TA 0-TA 6: time interval
VGH: high voltage of gate
VGL: very low voltage of gate
Δ V1, Δ V2, Δ V3: offset value
Detailed Description
The invention will be described in detail with reference to the following drawings, which are provided for illustration purposes and the like:
referring to fig. 1, fig. 1 is a schematic diagram illustrating a gate driving device according to an embodiment of the invention. The gate driving device comprises a plurality of shift register circuits which are mutually coupled in series and respectively generate a plurality of gate driving signals. Taking the shift register circuit 100 of the Nth stage as an example, the shift register circuit 100 includes an output stage circuit 110, voltage regulators 120-150, and an isolation circuit 160. The output stage circuit 110 has a first control terminal CE1 and a second control terminal CE 2. The first control terminal CE1 and the second control terminal CE2 respectively receive the first control signal Q [ N ] and the second control signal R [ N ]. The output stage circuit 110 provides the clock signal CK3, the gate high voltage VGH or the gate low voltage VGL to charge the output terminal OE according to the first control signal Q [ N ], the second control signal R [ N ] and the mode selection signal SS, and generates the Nth stage gate driving signal G [ N ]. When the mode selection signal SS is at a low voltage level, the output stage circuit 110 can provide the gate low voltage VGL to charge the output terminal to pull down the voltage value of the nth stage gate driving signal G [ N ]. In the present embodiment, the mode selection signals SS and SR are used to indicate whether the shift register circuit 100 operates in the compensation phase or the write phase.
In detail, the output stage circuit 110 of the present embodiment includes transistors T3, T4, T10 and a capacitor C1. The first terminal of the transistor T3 receives the clock signal CK3, the second terminal of the transistor T3 is coupled to the output terminal OE, and the control terminal of the transistor T3 receives the first control signal Q [ N ]. The first terminal of the transistor T4 receives the gate low voltage VGL, the second terminal of the transistor T4 is coupled to the output terminal OE, and the control terminal of the transistor T4 receives the mode selection signal SS. The first terminal of the transistor T10 is coupled to the output terminal OE, the second terminal of the transistor T10 receives the gate high voltage VGH, and the control terminal of the transistor T10 receives the second control signal R [ N ]. In addition, the capacitor C1 is connected in series between the control terminal of the transistor T3 and the output terminal OE.
The voltage regulator 120 is coupled between the first control terminal CE1 and the third control terminal CE 3. The voltage regulator 120 provides a gate high voltage VGH to regulate the first control signal QN according to the third control signal P [ N ], wherein the voltage regulator 120 provides the gate high voltage VGH to pull up the voltage of the first control signal QN when the third control signal P [ N ] is at a low voltage level.
In the present embodiment, the voltage regulator 120 includes transistors T7 and T11, and the transistors T7 and T11 are sequentially connected in series between the first control terminal CE1 and the gate high voltage VGH. The control terminals of the transistors T7 and T11 commonly receive the third control signal P [ N ].
In other embodiments of the present invention, the voltage regulator 120 may include only a single transistor. In fact, one or more transistors may be disposed in series with each other in the voltage regulator 120, and the number of the transistors is not limited. And through the circuit structure of a plurality of transistors connected in series, the leakage phenomenon between nodes can be reduced.
The voltage regulator 130 is coupled to the first control terminal CE 1. The voltage regulator 130 regulates the first control signal Q [ N ] according to the mode selection signal SR, the previous gate driving signal G [ N-1] or the start pulse signal ST, wherein the voltage regulator 130 pulls down the voltage value of the first control signal Q [ N ] according to the previous gate driving signal G [ N-1] or the start pulse signal ST when the previous gate driving signal G [ N-1] or the start pulse signal ST is at a low voltage level and the mode selection signal SR is at a low voltage level.
In the embodiment, the voltage regulator 130 includes transistors T1 and T2, and the control terminal of the transistor T1 is coupled to the first terminal of the transistor T1 and forms a diode configuration. In the present embodiment, the diode constructed by the transistor T1 has a cathode receiving the previous stage gate driving signal G [ N-1] or the start pulse signal ST, and an anode coupled to the first terminal of the transistor T2. The first terminal of the transistor T2 is coupled to the second terminal of the transistor T1, the second terminal of the transistor T2 is coupled to the first control terminal CE1, and the control terminal of the transistor T2 receives the mode selection signal SR.
The voltage regulator 140 is coupled to the second control terminal CE 2. The voltage regulator 140 provides a gate high voltage VGH to regulate the second control signal R [ N ] according to the mode selection signal SS, wherein the voltage regulator 140 provides the gate high voltage VGH to pull up the voltage value of the second control signal R [ N ] when the mode selection signal SS is at a low voltage level.
In the present embodiment, the voltage regulator 140 includes a transistor T9. The transistor T9 is connected in series between the second control terminal CE2 and the gate high voltage VGH, and the control terminal of the transistor T9 receives the mode selection signal SS. It should be noted that the number of transistors included in the voltage regulator 140 may be one or more. Fig. 1 is merely an illustrative example, and is not intended to limit the scope of the present invention.
The voltage regulator 150 is coupled to the third control terminal CE 3. The voltage regulator 150 provides the clock signal CK1 or the gate high voltage VGH to regulate the third control signal P [ N ] according to the clock signal CK1 and the first control signal Q [ N ]. The voltage regulator 150 includes transistors T5 and T6, wherein the control terminal of the transistor T5 is coupled to the first terminal of the transistor T5 and forms a diode configuration. In the present embodiment, the cathode of the diode constructed by the transistor T5 receives the clock signal CK1, and the anode thereof is coupled to the third control terminal CE 3. The first terminal of the transistor T6 is coupled to the anode of the diode constructed by the transistor T5, the second terminal of the transistor T6 receives the gate high voltage VGH, and the control terminal of the transistor T6 receives the first control signal Q [ N ].
The isolation circuit 160 is coupled between the third control terminal CE3 and the second control terminal CE 2. The isolation circuit 160 determines whether to block the second control terminal CE2 and the third control terminal CE3 according to the mode selection signal SR, wherein when the mode selection signal SR is at a high voltage level, the blocked isolation circuit 160 blocks the second control terminal CE2 and the third control terminal CE 3. On the other hand, when the mode selection signal SR is at a low voltage level, the isolation circuit 160 is turned on to connect the second control terminal CE2 and the third control terminal CE 3.
In the embodiment, the isolation circuit 160 includes a transistor T8, a transistor T8 is coupled between the second control terminal CE2 and the third control terminal CE3, and a control terminal of the transistor T8 receives the mode selection signal SR. It should be noted that the number of transistors included in the isolation circuit 160 may be one or more. Fig. 1 is merely an illustrative example, and is not intended to limit the scope of the present invention.
Referring to fig. 2 and fig. 3A to 3G together, please refer to the operation details of the shift register circuit 100, wherein fig. 2 shows an operation waveform diagram of the gate driving device according to the embodiment of the invention, and fig. 3A to 3G show equivalent circuit diagrams of the shift register circuit according to the embodiment of the invention.
Referring to fig. 2 and fig. 3A, in the initial time interval TA0, the gate driving device is in a normal operation stage, where the mode selection signal SS is at a high voltage level (equal to the gate high voltage VGH) and the mode selection signal SR is at a low voltage level (equal to the gate low voltage VGL). When the clock signal CK1 is at a low voltage level (equal to the gate low voltage VGL), the transistor T5 of the voltage regulator 150 is turned on in reverse direction, and the voltage of the third control signal P [ N ] is equal to VGL + | VTH _ T5|, wherein VTH _ T5 is the turn-on voltage of the transistor T5. The transistors T11 and T7 of the voltage regulator 120 are turned on according to the third control signal P [ N ] with the voltage value VGL + | VTH _ T5| to provide the gate high voltage VGH to pull up the voltage value of the first control signal Q [ N ]. Meanwhile, the transistor T8 in the isolation circuit 160 is turned on according to the mode selection signal SR being at a low voltage level (equal to the gate low voltage VGL) such that the second control terminal CE2 is connected to the third control terminal CE3 and the voltage values of the third control signal P [ N ] and the second control signal R [ N ] are substantially equal (equal to the voltage value VGL + | VTH _ T5 |).
At this time, the transistor T10 in the output stage circuit 110 is turned on according to the second control signal R [ N ], the transistor T3 in the output stage circuit 110 is turned off according to the first control signal Q [ N ], and the output stage circuit 110 generates the Nth stage gate driving signal G [ N ] with a high voltage level (equal to the gate high voltage VGH). In addition, when the output stage circuit 110 is not a shift register circuit belonging to the first stage, the previous stage gate driving signal G [ N-1] generated by the previous stage shift register is also at a high voltage level.
It should be noted that the voltage regulator 130 may receive the start pulse signal ST, or may also receive the previous stage gate driving signal G [ N-1 ]. The voltage regulator 130 can determine to receive the start pulse signal ST or the previous stage gate driving signal G [ N-1] according to the position of the shift register circuit. Briefly, when the voltage regulator 130 belongs to the shift register circuit of the first stage, the voltage regulator 130 may receive the start pulse signal ST, and when the voltage regulator 130 does not belong to the shift register circuit of the first stage, the voltage regulator 130 may receive the gate driving signal G [ N-1] of the previous stage.
Incidentally, in the initial time interval TA0, the transistor T1 of the voltage regulator 130 is turned off according to the start pulse signal ST or the previous stage gate driving signal G [ N-1] at a high voltage level (equal to the gate high voltage VGH). The transistor T6 in the voltage regulator 150 is turned off according to the first control signal Q [ N ] equal to the high voltage level (equal to the gate high voltage VGH). The transistor T9 in the voltage regulator 140 and the transistor T4 in the output stage circuit 110 are turned off according to the mode selection signal SS equal to the high voltage potential (equal to the gate high voltage VGH). It should be noted that when the clock signal CK1 transitions to a high voltage level (equal to the gate high voltage VGH), the transistor T5 of the voltage regulator 150 is turned off according to the transitioned clock signal CK1, and the voltage of the third control signal P [ N ] is maintained to be equal to the voltage VGL + | VTH _ T5 |.
Please refer to fig. 2 and fig. 3B. In a time interval TA1 after the initial time interval TA0, the gate driving device enters a compensation phase. Meanwhile, the mode selection signal SR transitions to a high voltage level (equal to the gate high voltage VGH), and the mode selection signal SS transitions from the gate high voltage VGH to a voltage level VGL _ L, wherein the voltage level VGL _ L is lower than the gate low voltage VGL. Based on the mode selection signal SS transitioning to be equal to the voltage value VGL _ L, the transistor T4 in the output stage circuit 110 is turned on according to the mode selection signal SS to provide the gate low voltage VGL to charge the output terminal OE, and pull down the voltage value of the nth stage gate driving signal G [ N ] to generate the nth stage gate driving signal G [ N ] equal to the gate low voltage VGL.
It is noted that the transistor T5 in the voltage regulator 150 can be turned on or off according to the clock signal CK1, and the voltage value of the third control signal P [ N ] is maintained equal to VGL + | VTH _ T5 |. The voltage regulator 120 is turned on according to the third control signal P [ N ] equal to the voltage value VGL + | VTH _ T5| and provides the gate high voltage VGH to pull up the voltage value of the first control signal Q [ N ]. Incidentally, at this time, the transistor T2 in the voltage regulator 130 is turned off according to the mode selection signal SR at the high voltage level.
Meanwhile, the isolation circuit 160 is turned off according to the mode selection signal SR to block the second control terminal CE2 and the third control terminal CE 3. The voltage regulator 140 is turned on according to the mode selection signal SS and provides the gate high voltage VGH to pull up the second control signal R [ N ]. At this time, the transistor T10 in the output stage circuit 110 is turned off according to the second control signal R [ N ] being pulled high, and the transistor T3 in the output stage circuit 110 is continuously turned off according to the first control signal Q [ N ].
On the other hand, since the mode selection signals SS received by all the shift register circuits are the same, the voltage value of the N-1 th stage gate driving signal G [ N-1] is pulled down to the gate low voltage VGL synchronously according to the mode selection signal SS during the time interval TA 1. In this way, the gate driving device can enable (pull down) all the gate driving signals at the same time, and can perform the compensation operation of the thin film transistors of all the pixel circuits.
It is noted that after the time interval TA1, the gate driving device is reset to transition the mode selection signal SS to the high voltage level (equal to the gate high voltage VGH) and transition the mode selection signal SR to the low voltage level (equal to the gate low voltage VGL) to end the compensation phase of the gate driving device.
Please refer to fig. 2 and fig. 3C. In the time interval TA2, the gate driving device is in a normal operation phase. In the time interval TA2, the mode selection signal SS is at a high voltage level (equal to the gate high voltage VGH), the mode selection signal SR is at a low voltage level (equal to the gate low voltage VGL), the clock signal CK1 is at a low voltage level (equal to the gate low voltage VGL), and the clock signal CK3 is at a high voltage level (equal to the gate high voltage VGH). At this time, the transistor T5 of the voltage regulator 150 is turned on according to the clock signal CK1 to maintain the voltage of the third control signal P [ N ] equal to VGL + | VTH _ T5 |. The transistor T10 in the output stage circuit 110 is turned on according to the second control signal R [ N ] and generates the Nth stage gate driving signal G [ N ] with a high voltage level (equal to the gate high voltage VGH). The operation waveform and operation mode of the gate driving device in this time interval TA2 are similar to the operation waveform and operation mode in the initial time interval TA0 (also in the normal operation phase), and are not repeated herein.
Please refer to fig. 2 and fig. 3D. At time interval TA3, the gate driving device enters the first sub-phase of the writing phase. During the time interval TA3, the mode selection signal SS is maintained at a high voltage level (equal to the gate high voltage VGH), and the mode selection signal SR is maintained at a low voltage level (equal to the gate low voltage VGL). The transistor T2 of the voltage regulator 130 is turned on according to the mode selection signal SR at a low voltage level, and at the same time, the transistor T1 of the voltage regulator 130 is turned on according to the start pulse signal ST or the previous stage of the gate driving signal G [ N-1] at a low voltage level (equal to the gate low voltage VGL) to pull down the voltage value of the first control signal Q [ N ] by transmitting the start pulse signal ST or the previous stage of the gate driving signal G [ N-1] through the turned-on transistors T1 and T2, at which time the voltage value of the first control signal Q [ N ] is equal to VGL + | VTH _ T1|, wherein VTH _ T1 is the turn-on voltage of the transistor T1.
As the voltage value of the first control signal Q [ N ] is pulled low, the transistor T6 in the voltage regulator 150 is turned on. Thus, the voltage of the third control signal P [ N ] is pulled high according to the gate high voltage VGH, and the transistor T5 is turned off according to the clock signal CK1 transitioning from the gate low voltage VGL to the gate high voltage VGH. At the same time, the voltage regulator 120 is turned off according to the third control signal P [ N ] that is pulled high. The isolation circuit 160 is turned on according to the mode selection signal SR, such that the second control terminal CE2 is connected to the third control terminal CE3, and transmits the pulled-up third control signal P [ N ] as the second control signal R [ N ]. Incidentally, the voltage regulator 140 remains turned off according to the mode selection signal SS.
At the same time, the transistor T3 in the output stage circuit 110 is turned on according to the first control signal Q [ N ] pulled low, so that the clock signal CK3 equal to the gate high voltage VGH charges the output terminal OE, the transistor T10 is turned off according to the second control signal R [ N ] equal to the gate high voltage VGH, and the transistor T4 remains turned off according to the mode selection signal SS. Therefore, the voltage value of the Nth stage gate driving signal G [ N ] is maintained to be equal to the gate high voltage VGH.
Please refer to fig. 2 and fig. 3E. At time interval TA4, the gate driving device enters the second sub-phase of the writing phase. In the time interval TA4, the voltage value of the start pulse signal ST or the previous stage gate driving signal G [ N-1] is pulled up to be equal to the gate high voltage VGH. The transistor T1 in the voltage regulator 130 is turned off according to the pulled-up start pulse signal ST or the previous stage gate driving signal G N-1. On the other hand, the clock pulse signal CK3 transits from the gate high voltage VGH to the gate low voltage VGL. By maintaining the transistor T3 turned on, the output stage circuit 110 provides the clock signal CK3 to charge the output terminal OE, so that the voltage value of the nth stage gate driving signal G [ N ] is pulled down to the gate low voltage VGL.
Please note that, based on the pull-down of the voltage of the Nth stage of the gate driving signal G [ N ], the first control signal Q [ N ] is pulled down by a first offset value V1 according to the pulled-down clock signal CK 3. To elaborate, the voltage level of the first control signal Q [ N ] can be further pulled down to VGL + | VTH _ T1| -V1 by the coupling effect generated by the capacitor C1, wherein the magnitude of the first offset value V1 is determined according to the ratio of the capacitance of the capacitor C1 and the equivalent capacitance of the first control terminal CE 1. Under the condition that the voltage of the first control signal QN can be further pulled down, the transistor T6 in the voltage regulator 150 can be turned on continuously, and the voltage of the third control signal PN can be pulled up continuously to maintain the gate high voltage VGH. Therefore, the transistors T7, T11 of the voltage regulator 120 are turned off continuously according to the third control signal P [ N ].
Additionally, the voltage regulator 140 remains turned off according to the mode selection signal SS, and the isolation circuit 160 continues to remain turned on according to the mode selection signal SR, so as to transmit the third control signal P [ N ] as the second control signal R [ N ]. The transistor T10 in the output stage 110 remains turned off according to the second control signal R [ N ] being the gate high voltage VGH.
Please refer to fig. 2 and fig. 3F. At time interval TA5, the gate driving device enters the third sub-phase of the writing phase. In the time interval TA5, the clock signal CK3 transitions from the gate low voltage VGL to the gate high voltage VGH, and the clock signal CK1 transitions from the gate high voltage VGH to the gate low voltage VGL. At this time, by maintaining the turned-on transistor T3, the output stage circuit 110 provides the clock signal CK3 to charge the output terminal OE, so that the voltage value of the nth stage gate driving signal G [ N ] is pulled up to the gate high voltage VGH.
It is noted that, based on the pull-up of the voltage value of the Nth stage of the gate driving signal G [ N ], the first control signal Q [ N ] is pulled up to a voltage value VGL + | VTH _ T1| + V2 according to the pulled-up clock signal CK3, wherein V2 is a second offset value. In detail, due to the coupling effect generated by the capacitor C1, in the embodiment, the first control signal Q [ N ] can be pulled up to a voltage value VGL + | VTH _ T1| + V2 slightly higher than the voltage value VGL + | VTH _ T1| in the time interval TA5, where VGL + | VTH _ T1| + V2 > VGL + | VTH _ T1| > VGL + | VTH _ T1| -V1. It should be noted that the magnitude of the pulled-up voltage of the first control signal Q [ N ] in the time interval TA5 (i.e. the first offset value V1+ the second offset value V2) can be determined according to the ratio of the capacitance of the capacitor C1 to the equivalent capacitance of the first control terminal CE1, wherein the magnitude of the pulled-up voltage and the magnitude of the first offset value V1 can be the same or different, i.e. the magnitude of the second offset value V2 can be zero or not, and fig. 2 is only an illustrative example, and is not intended to limit the scope of the present invention.
Meanwhile, the transistor T5 in the voltage regulator 150 is turned on according to the pulled-down clock signal CK1, and the transistor T6 is turned on according to the first control signal Q [ N ], so that the third control signal P [ N ] is pulled down by a third offset value V3 according to the clock signal CK1 and the gate high voltage VGH, wherein the magnitude of the third offset value V3 may be the same as or different from the magnitude of the second offset value V2, and fig. 2 is only an illustrative example, and does not limit the scope of the present invention. In the present embodiment, the third control signal P [ N ] can be pulled down to a voltage value VGH-V3 that is slightly lower than the gate high voltage VGH during the time interval TA 5. Wherein VGH > VGH-V3 > VGL + | VTH _ T5 |. At the same time, the voltage regulator 120 is turned on according to the third control signal P [ N ] to pull up the first control signal Q [ N ]. Incidentally, the voltage regulators 130 and 140 continue to remain switched off at this time.
On the other hand, the isolation circuit 160 remains turned on according to the mode selection signal SR to transmit the pulled-down third control signal P [ N ] as the second control signal R [ N ]. The transistor T10 of the output stage circuit 110 is turned on according to the second control signal R [ N ] and provides the gate high voltage VGH to the output terminal OE, so as to charge the output terminal OE simultaneously with the transistor T3, so that the output stage circuit 110 generates the Nth stage gate driving signal G [ N ] equal to the gate high voltage VGH.
Please refer to fig. 2 and fig. 3G. During time interval TA6, the gate driving device enters a voltage holding phase. During the time interval TA6, the transistor T5 of the voltage regulator 150 is periodically turned on according to the clock signal CK1 that periodically transits (when the clock signal CK1 transits to equal to the gate low voltage VGL), and charges the third control signal P [ N ] periodically, so as to drive the voltage value of the third control signal P [ N ] to fall and maintain at VGL + | VTH _ T5|, and the voltage regulator 120 continues to be turned on according to the pulled-down third control signal P [ N ] to charge the first control signal Q [ N ], so as to drive the voltage value of the first control signal Q [ N ] to be pulled up and maintain at the gate high voltage VGH.
Incidentally, the transistor T6 in the voltage regulator 150 is turned off according to the pulled-down first control signal QN, and the transistor T3 in the output stage 110 is also turned off according to the pulled-down first control signal QN. The voltage regulator 130 continues to be turned off according to the previous stage gate driving signal G [ N-1] or the start pulse signal ST. The voltage regulator 140 continues to be turned off according to the mode selection signal SS.
It is noted that the isolation circuit 160 is turned on according to the mode selection signal SR, and transmits the third control signal P [ N ] as the second control signal R [ N ], so that the transistor T10 in the output stage circuit 110 is kept turned on according to the second control signal R [ N ]. In this way, the output stage circuit 110 charges the output terminal OE with the gate high voltage VGH through the turned-on transistor T10, so that the voltage value of the nth stage gate driving signal G [ N ] is maintained equal to the gate high voltage VGH.
As can be readily understood from the above description, in the writing stage, the gate driving device can generate sequentially enabled (pulled down) gate driving signals and sequentially perform data writing operations on a plurality of pixels by sequentially transmitting the pulled down gate driving signals.
In summary, the present invention provides a shift register circuit, and a gate driving signal is formed by a plurality of shift register circuits connected in series. The gate driving signals provided by the invention can provide a plurality of commonly enabled gate driving signals in the compensation stage and generate sequentially enabled gate driving signals in the writing stage so as to provide enough time to execute data writing action. The display panel can be effectively matched with a synchronous active organic light emitting diode to compensate the variation of the threshold voltage in the compensation time without being limited by the resolution of the panel, and is applied to the display panel with high resolution. In addition, in the embodiment of the invention, the voltage regulator is constructed by a plurality of transistors connected in series, so that the leakage phenomenon of internal nodes can be reduced, and the power consumption is saved.
The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (19)

1. A gate driving apparatus, comprising:
a plurality of shift register circuits, these shift register circuits are connected in series each other, produce a plurality of grid drive signals respectively, wherein the shift register circuit of Nth level includes:
an output stage circuit having a first control terminal and a second control terminal for receiving a first control signal and a second control signal respectively, and providing a first clock signal, a gate high voltage or a gate low voltage according to the first control signal, the second control signal and a first mode selection signal to charge an output terminal to generate an nth stage gate driving signal;
a first voltage regulator coupled between the first control terminal and a third control terminal for providing the gate high voltage according to a third control signal to regulate the first control signal;
a second voltage regulator coupled to the first control terminal for regulating the first control signal according to a second mode selection signal, a previous stage gate driving signal or a start pulse signal;
a third voltage regulator coupled to the second control terminal for providing the gate high voltage to regulate the second control signal according to the first mode selection signal;
a fourth voltage regulator coupled to the third control terminal for providing the second clock signal or the gate high voltage to regulate the third control signal according to a second clock signal and the first control signal; and
an isolation circuit coupled between the third control terminal and the second control terminal for determining whether to block the second control terminal from the third control terminal according to the second mode selection signal.
2. The gate driving apparatus of claim 1, wherein during a compensation phase, the second voltage regulator is turned off according to the second mode selection signal, the first voltage regulator is turned on according to the third control signal, and the gate high voltage is provided to pull up the first control signal.
3. The gate driving device as claimed in claim 2, wherein during the compensation phase, the third voltage regulator is turned on according to the first mode selection signal and provides the gate high voltage to pull up the second control signal, the fourth voltage regulator is turned on according to the second clock signal and asserts the third control signal, and the isolation circuit is turned off according to the second mode selection signal to block the second control terminal from the third control terminal.
4. The gate driving device as claimed in claim 3, wherein the output stage circuit provides the gate low voltage to charge the output terminal according to the first mode selection signal and generates the Nth stage gate driving signal during the compensation phase.
5. The gate driving apparatus as claimed in claim 2, wherein the second voltage regulator is turned on according to the second mode selection signal and the previous gate driving signal or the start pulse signal and transmits the previous gate driving signal or the start pulse signal to pull down the first control signal during a first sub-phase of a writing phase, and the first voltage regulator is turned off according to the third control signal.
6. The gate driving apparatus as claimed in claim 5, wherein the third voltage regulator is turned off according to the first mode selection signal, the fourth voltage regulator is turned on according to the first control signal and provides the gate high voltage to pull up the third control signal, and the isolation circuit is turned on according to the second mode selection signal and transmits the third control signal as the second control signal in the first sub-phase of the write phase.
7. The gate driving apparatus as claimed in claim 5, wherein in a second sub-phase of the writing phase, the second voltage regulator is turned off according to the previous gate driving signal or the start pulse signal being pulled up, the first voltage regulator is turned off according to the third control signal, and the first control signal is pulled down by a first offset value according to the first clock pulse signal being pulled down.
8. The gate driving apparatus as claimed in claim 7, wherein the third voltage regulator remains turned off during the second sub-phase of the write phase, the fourth voltage regulator continues to be turned on according to the first control signal and provides the gate high voltage to pull up the third control signal, and the isolation circuit is turned on according to the second mode selection signal to transmit the third control signal as the second control signal.
9. The gate driving device as claimed in claim 8, wherein the output stage circuit provides the first clock signal according to the first control signal to charge the output terminal and generate the nth stage gate driving signal.
10. The gate driving apparatus of claim 9, wherein the second voltage regulator and the third voltage regulator are turned off in a third sub-phase of the write phase, the first voltage regulator is turned on according to a third control signal to pull up the first control signal, the fourth voltage regulator is turned on according to the second clock signal and the first control signal to pull down the third control signal, and the isolation circuit remains turned on according to the second mode selection signal to transmit the third control signal as the second control signal.
11. The gate driving device as claimed in claim 2, wherein during a voltage holding period, the second voltage regulator is turned off according to the previous gate driving signal or the start pulse signal, the third voltage regulator is turned off according to the first mode selection signal, the first voltage regulator is turned on according to a third control signal being pulled down and charging the first control signal, the fourth voltage regulator is periodically turned on according to the second clock signal and charging the third control signal, and the isolation circuit is turned on according to the second mode selection signal to transmit the third control signal as the second control signal.
12. The gate driving device as claimed in claim 11, wherein the output stage circuit provides the gate high voltage to generate the nth stage gate driving signal according to the second control signal during the voltage holding stage.
13. A gate driver according to claim 1, wherein the output stage circuit comprises:
a first transistor, a first terminal of which receives the first clock signal, a second terminal of which is coupled to the output terminal, and a control terminal of which receives the first control signal;
a first capacitor coupled between the control terminal of the first transistor and the output terminal;
a second transistor, a first terminal of which is coupled to the output terminal, a second terminal of which receives the gate high voltage, and a control terminal of which receives the second control signal; and
a third transistor, a first terminal of which receives the gate low voltage, a second terminal of which is coupled to the output terminal, and a control terminal of which receives the first mode selection signal.
14. The gate driving apparatus of claim 1, wherein the first voltage regulator comprises:
at least one transistor coupled to the first control terminal for receiving the gate high voltage, and the control terminal of the at least one transistor receiving the third control signal.
15. The gate driving apparatus of claim 1, wherein the second voltage regulator comprises:
a diode, the cathode of which receives the preceding stage gate driving signal or the start pulse signal; and
a first transistor, a first terminal of which is coupled to the anode of the diode, a second terminal of which is coupled to the first control terminal, and a control terminal of which receives the second mode selection signal.
16. A gate driver according to claim 1, wherein the third voltage regulator comprises:
at least one transistor coupled to the second control terminal for receiving the gate high voltage, wherein the control terminal of the at least one transistor receives the first mode selection signal.
17. A gate driver according to claim 1, wherein the fourth voltage regulator comprises:
a diode, a cathode of which receives the second clock signal, and an anode of which is coupled to the third control terminal; and
a first transistor, a first terminal of which is coupled to the anode of the diode, a second terminal of which receives the gate high voltage, and a control terminal of which receives the first control signal.
18. A gate driver according to claim 1, wherein the isolation circuit comprises:
at least one transistor coupled between the second control terminal and the third control terminal, wherein the control terminal of the at least one transistor receives the second mode selection signal.
19. The gate driving device of claim 1, wherein the gate driving signals are enabled simultaneously during a compensation phase, sequentially enabled during a write phase, and maintained at a disabled voltage during a voltage hold phase,
wherein the compensation phase, the write phase and the voltage holding phase occur sequentially.
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