WO2018137326A1 - 移位寄存器及其驱动方法、栅极驱动电路和显示装置 - Google Patents

移位寄存器及其驱动方法、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2018137326A1
WO2018137326A1 PCT/CN2017/095289 CN2017095289W WO2018137326A1 WO 2018137326 A1 WO2018137326 A1 WO 2018137326A1 CN 2017095289 W CN2017095289 W CN 2017095289W WO 2018137326 A1 WO2018137326 A1 WO 2018137326A1
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Prior art keywords
pull
potential
terminal
shift register
node
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PCT/CN2017/095289
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English (en)
French (fr)
Inventor
郝学光
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京东方科技集团股份有限公司
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Priority to BR112018069848A priority Critical patent/BR112018069848A2/pt
Priority to US15/749,975 priority patent/US10777118B2/en
Priority to EP17835573.1A priority patent/EP3576082B1/en
Publication of WO2018137326A1 publication Critical patent/WO2018137326A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3433—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices
    • G09G3/3453—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices based on rotating particles or microelements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present disclosure relates to a shift register and a method of driving the same, a gate driving circuit including the shift register, and a display device.
  • GOA Gate on Array
  • the gate driving circuit is formed on the display substrate of the display device by an array process.
  • the use of GOA technology can save cost, and can realize the symmetrical aesthetic design of the two sides of the display panel, and can eliminate the binding area of the gate driving circuit and the wiring space of the fanout, thereby realizing the design of the narrow bezel.
  • GOA technology can eliminate the bonding process of the gate scan line direction, thereby providing capacity and yield.
  • one end of the capacitance of the pull-up node is usually connected to a low potential, causing the bootstrap function of the capacitor to fail during the output gate signal phase, so that the pull-up node
  • the potential cannot guarantee that the output transistor can be fully turned on. For example, during high and low temperature reliability testing, the threshold voltage of the output transistor will drift. In such a case, the potential of the pull-up node cannot be maintained at a high potential, causing an abnormality in the output of the gate drive signal, thereby causing display failure or abnormality of the display screen.
  • a shift register comprising: a pull-up node control circuit for receiving a first input signal according to a first signal input terminal and a second signal input terminal respectively via a shift register a second input signal that causes a potential of a pull-up node inside the shift register to become a high potential; a first capacitor connected between the signal output end of the shift register and the pull-up node; and a pull-down node control circuit for respectively a second clock signal terminal of the shift register, a second clock signal and a third clock signal received by the third clock signal terminal, and a potential of the pull-up node, controlling a potential of the pull-down node; and an output circuit for the potential of the pull-up node And controlling the gate driving signal at the signal output end via the first clock signal received by the first clock signal terminal of the shift register And a pull-down circuit for making the potential of the pull-up node and the signal output terminal low according to the potential of the pull-down node.
  • the shift register may further include a second capacitor connected between the low potential terminal of the shift register and the pull-down node.
  • the pull-up node control circuit may include: a first transistor having a control electrode connected to the first signal input terminal, a first pole connected to the first reference potential terminal of the shift register, and a second pole connected to the upper terminal a pull-up node; and a second transistor having a control electrode coupled to the second signal input terminal, a first terminal coupled to the second reference potential terminal of the shift register, and a second terminal coupled to the pull-up node.
  • the pull-down node control circuit may include: a third transistor having a control electrode connected to a first reference potential terminal of the shift register, a first electrode connected to the second clock signal terminal, and a fourth transistor having a gate connection To a second reference potential end of the shift register, the first pole thereof is connected to the third clock signal terminal; the fifth transistor has a control electrode connected to the second pole of the third transistor and the fourth transistor, the first pole of which is connected to The high potential end of the shift register has a second pole connected to the pull-down node; and a sixth transistor whose gate is connected to the pull-up node, the first pole of which is connected to the pull-down node, and the second pole of which is connected to the low potential terminal.
  • the output circuit may include a seventh transistor having a control electrode connected to the pull-up node, a first pole connected to the first clock signal terminal, and a second pole connected to the signal output terminal.
  • the output circuit further includes: an eighth transistor having a control electrode connected to the high potential end of the shift register, a first electrode connected to the pull-up node, and a second electrode connected to the control electrode of the eighth transistor .
  • the pull-down circuit may include: a ninth transistor having a control electrode connected to the pull-down node, a first pole connected to the low potential terminal, a second pole connected to the pull-up node, and a tenth transistor having a control electrode connected thereto
  • a pull-down node has a first pole connected to the low potential terminal and a second pole connected to the signal output terminal.
  • all transistors are N-type transistors.
  • a gate driving circuit comprising a plurality of cascaded ones of any of the above shift registers, wherein a first signal input of each stage of shift registers other than the last stage Connected to the signal output of its next stage shift register, and the second signal input of each stage of the shift register other than the first stage is connected to the signal output of its previous stage shift register.
  • a display device that includes any of the gate drive circuits described above.
  • a driving method that can be used to drive any of the above shift registers.
  • the driving method includes: receiving a first input signal, causing a potential of the pull-up node to become a high potential, and charging the first capacitor; receiving the first clock signal, further pulling the potential of the pull-up node through the first capacitor, and simultaneously The signal output terminal outputs a gate drive signal; the second clock signal and the second input signal are received to make the potential of the pull-up node and the signal output terminal low; and the pull-down node is maintained at a high potential.
  • the first reference potential end and the second reference potential end of the shift register are respectively set to a high potential and a low potential; in the forward scan, the first reference potential end and the second reference are The potential terminals are set to a low potential and a high potential, respectively.
  • FIG. 1 illustrates a circuit included in a shift register in accordance with an embodiment of the present disclosure.
  • FIG. 2 illustrates an exemplary implementation of circuitry included in a shift register in accordance with an embodiment of the present disclosure.
  • FIG. 3 illustrates a driving method of a shift register according to an embodiment of the present disclosure.
  • FIG. 4 illustrates an exemplary operational sequence of a shift register in accordance with an embodiment of the present disclosure.
  • FIG. 5 illustrates another exemplary operational sequence of a shift register in accordance with an embodiment of the present disclosure.
  • FIG. 6 illustrates a partial schematic view of a gate drive circuit in accordance with an embodiment of the present disclosure.
  • FIG. 7 illustrates a clock signal of a gate driving circuit in the case of reverse scanning, according to an embodiment of the present disclosure.
  • FIG. 8 illustrates a clock signal of a gate driving circuit in the case of forward scanning, according to an embodiment of the present disclosure.
  • FIG. 9 shows a schematic diagram of a display device in accordance with an embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a shift register and a driving method thereof, a gate driving circuit including the shift register, and a display device to ensure that a bootstrap function of a capacitor of a pull-up node is always effective at a stage of outputting a gate signal. Thereby ensuring that the potential of the pull-up node is maintained at a high potential during the output gate signal phase, so that the output transistor is fully turned on during the output gate signal phase. Thereby, the normal output of the gate drive signal is ensured, and the normal display of the display screen is further ensured.
  • a shift register may be provided with a first signal input terminal INPUT1 for receiving a first input signal, and a second signal input terminal INPUT2 for receiving a second input signal for a second clock signal terminal CK2 receiving the second clock signal, a third clock signal terminal CK3 for receiving the third clock signal, and a first clock signal terminal CK1 for receiving the first clock signal for setting the first reference potential
  • the first reference potential terminal CNB, the second reference potential terminal CN for setting the second reference potential, the signal output terminal OUTPUT for outputting the gate driving signal, the high potential terminal VGH, and the low potential terminal VGL.
  • a pull-up node PU and a pull-down node PD may include a pull-up node control circuit 101, a capacitor C1, a pull-down node control circuit 102, an output circuit 103, and a pull-down circuit 104.
  • the pull-up node control circuit 101 can be provided with a first control terminal, a second control terminal, and a first input. End, second input and output.
  • first control terminal a first control terminal
  • second control terminal a second control terminal
  • first input terminal a first input terminal
  • second input terminal a second input terminal
  • the first input terminal and the output terminal are connected such that the potential of the output terminal becomes the same as the potential of the first input terminal.
  • the second input terminal and the output terminal are connected such that the potential of the output terminal becomes the same as the potential of the second input terminal.
  • the first control terminal, the second control terminal, the first input terminal, the second input terminal, and the output terminal of the pull-up node control circuit 101 can be respectively connected to the first signal input terminal INPUT1 of the shift register.
  • the pull-up node control circuit 101 can set the potential of the pull-up node PU to, for example, a high potential based on the received first input signal and second input signal.
  • one end of the capacitor C1 is connected to the pull-up node PU, and the other end is connected to the signal output terminal OUTPUT.
  • the pull-down node control circuit 102 can be provided with a first control selection terminal, a second control selection terminal, a first control terminal, a second control terminal, a third control terminal, a first input terminal, a second input terminal, and an output terminal.
  • a first control selection terminal in a case where the potential of the first control selection terminal is high, the connection between the first input terminal and the output terminal is controlled according to the potential of the first control terminal, wherein the first input terminal and the output terminal are The potential of the potential of the first control terminal is turned off when the potential of the potential is low, and is communicated when the potential of the potential of the first control terminal is high, so that the potential of the output terminal becomes the same as the potential of the first input terminal.
  • the connection between the first input terminal and the output terminal is controlled according to the potential of the second control terminal, wherein the first input terminal and the output terminal are The potential of the potential of the second control terminal is turned off when the potential of the potential is low, and is communicated when the potential of the potential of the second control terminal is high, so that the potential of the output terminal becomes the same as the potential of the first input terminal.
  • the second input terminal and the output terminal are connected in a case where the potential of the third control terminal is high, so that the potential of the output terminal becomes the same as the potential of the second input terminal.
  • the first control selection terminal, the second control selection terminal, the first control terminal, the second control terminal, the third control terminal, the first input terminal, the second input terminal, and the pull-down node control circuit 102 The output terminals can be respectively connected to the first reference potential CNB of the shift register and the second reference potential end CN, second clock signal terminal CK2, third clock signal terminal CK3, pull-up node PU, high potential terminal VGH, low potential terminal VGL, and pull-down node PD.
  • the connection between the high potential terminal VGH and the pull-down node PD is controlled according to the second clock signal received via the second clock signal terminal CK2.
  • the pull-down node control circuit 102 can control the potential of the pull-down node based on the received second clock signal or the third clock signal or the potential of the pull-up node.
  • the output circuit 103 can be provided with a control terminal, an input terminal and an output terminal, wherein, for example, the input terminal and the output terminal are connected in a case where the potential of the control terminal is high, so that the potential of the output terminal is the same as the potential of the input terminal.
  • the control terminal, the input terminal and the output terminal of the output circuit 103 can be respectively connected to the pull-up node PU of the shift register, the first clock signal terminal CK1 and the signal output terminal OUTPUT, so that the pull-up node PU In the case where the potential is high, the signal output terminal OUTPUT can output the gate drive signal in accordance with the first clock signal received via the first clock signal terminal CK1. Thereby, the output of the gate driving signal at the signal output terminal OUTPUT can be controlled by the output circuit 103 in accordance with the potential of the pull-up node PU and the first clock signal.
  • the pull-down circuit 104 may be provided with a control terminal, an input terminal, a first output terminal and a second output terminal, wherein, for example, in the case where the potential of the first control terminal of the pull-down circuit 104 is high, the input terminal of the pull-down circuit 104 and the first An output is connected, and the input of the pull-down circuit 104 is in communication with the second output such that the potential of the first output of the pull-down circuit 104 and the potential of the second output are both the same as the potential of its input.
  • the control terminal, the input terminal, the first output terminal, and the second output terminal of the pull-down circuit 104 can be respectively connected to the pull-down node PD of the shift register, the low potential terminal VGL, the pull-up node PU, and the signal output.
  • Terminal OUTPUT such that the potential of the pull-down node PD is high
  • the potential of the pull-up node PU and the signal output terminal OUTPUT can be made low.
  • a shift register may further include a capacitor C2.
  • one end of the capacitor C2 is connected to the pull-down node PD, and the other end is connected to the low potential terminal VGL of the shift register.
  • FIG. 2 illustrates an exemplary implementation of the various circuits included in the shift register of FIG. 1 in accordance with an embodiment of the present disclosure.
  • the pull-up node control circuit 101 can include a transistor M3 and a transistor M4.
  • the control electrode of the transistor M3 can serve as a first control terminal of the pull-up node control circuit 101 and is connected to the first signal input terminal INPUT1 of the shift register, the first pole of which can serve as the first input terminal of the pull-up node control circuit 101 and Connected to the first reference signal terminal CNB of the shift register.
  • the control electrode of the transistor M4 can serve as the second control terminal of the pull-up node control circuit 101 and is connected to the second signal input terminal INPUT2 of the shift register, the first pole of which can serve as the second input terminal of the pull-up node control circuit 101 and Connected to the first reference signal terminal CN of the shift register.
  • Transistor M3 and the second pole of transistor M4 may be connected together and as an output of pull-up node control circuit 101, and further connected to pull-up node PU.
  • the transistor M3 and the transistor M4 may both be N-type transistors such that each transistor is turned on when the potential of its gate is high. It should be appreciated that the pull-up node control circuit 101 can also be implemented in other implementations.
  • the pull up node control circuit 101 can be implemented as an integrated circuit module.
  • the overall layout of the shift register circuit eg, the exemplary circuit configuration of the shift register shown in FIG. 2 may also be considered, and the various components in the pull-up node control circuit 101 are respectively disposed. The different positions of the shift register circuit while maintaining the connection between these elements to achieve the corresponding function of the pull-up node control circuit 101.
  • the pull-down node control circuit 102 can include a transistor M1, a transistor M2, a transistor M5, and a transistor M6.
  • the control electrode of the transistor M1 can serve as a first control select terminal of the pull-down node control circuit 102 and is connected to the first reference potential CNB of the shift register, the first pole of which can serve as the first control terminal of the pull-down node control circuit 102 and is connected to The second clock signal terminal CK2 of the shift register.
  • the control electrode of the transistor M2 can serve as a second control select terminal of the pull-down node control circuit 102 and is connected to the second reference potential CN of the shift register, the first pole of which can serve as the second control terminal of the pull-down node control circuit 102 and is connected to The third clock signal terminal CK3 of the shift register.
  • the first pole of transistor M5 can be the first of pull-down node control circuit 102 The input is coupled to the high potential terminal VGH of the shift register, the second pole of which can be used as the output of the pull-down node control circuit 102 and to the pull-down node PD of the shift register.
  • the second poles of the transistors M1 and M2 can be connected together and both connected to the gate of the transistor M5, so that the turn-on and turn-off of the transistor M5 can be controlled according to the second clock signal or the third clock signal.
  • the gate of the transistor M6 can serve as the third control terminal of the pull-down node control circuit 102 and is connected to the pull-up node PU, the second pole of which can serve as the second input of the pull-down node control circuit 102 and is connected to the low potential of the shift register.
  • the terminal VGL, its first pole can be connected to the second pole of transistor M5 (ie as the output of pull-down node control circuit 102) and further connected to pull-down node PD.
  • Different sized transistors M5 and M6 can be set as needed to control the potential of the pull-down node PD in the case where both of the transistors M5 and M6 are turned on. For example, if the potential of the pull-down node PD in the case where the transistors M5 and M6 are both turned on is low, it is possible to select transistors M5 and M6 of different sizes so that the on-resistance of the transistor M6 is relative to the transistor M5.
  • the on-resistance is much smaller; if the potential of the pull-down node PD in the case where the transistors M5 and M6 are both turned on is high, it is possible to select transistors M5 and M6 of different sizes so that the on-resistance of the transistor M6 is relative to The on-resistance of transistor M5 is much larger.
  • the transistor M1, the transistor M2, the transistor M5, and the transistor M6 may all be N-type transistors such that each transistor is turned on when the potential of its gate is high. It should be appreciated that the pull-down node control circuit 102 can also be implemented in other implementations.
  • the pull-down node control circuit 102 can be implemented as an integrated circuit module.
  • the overall layout of the shift register circuit eg, the exemplary circuit configuration of the shift register shown in FIG. 2 may also be considered, with the various components in the pull-up node control circuit 102 being separately disposed The different positions of the shift register circuit maintain the manner of connection between these elements to achieve the corresponding function of the pull-up node control circuit 102.
  • the output circuit 103 can include a transistor M10 whose control, first and second poles can serve as the control, input and output of the output circuit 103, respectively.
  • the transistor M10 may be an N-type transistor such that the transistor is turned on when the potential of its gate is high. It should be appreciated that the output circuit 103 can also be implemented in other implementations.
  • the output circuit 103 may further include a transistor M8. The gate of transistor M8 can be connected to the high potential terminal such that transistor M8 is always on, the first pole of transistor M8 is connected as the control terminal of output circuit 103, and the second pole of transistor M8 is coupled to transistor M10. The control poles are connected.
  • Setting M8 may cause the change in voltage of the PU node to not directly affect the voltage of the gate of transistor M10 in output circuit 103, such that the potential at the gate of transistor M10 is more stable, providing a more stable output.
  • the transistor M8 may also be an N-type transistor such that the transistor is turned on when the potential of its gate is high.
  • output circuit 103 can be implemented as an integrated circuit module.
  • the overall layout of the shift register circuit eg, the exemplary circuit configuration of the shift register shown in FIG. 2 may also be considered, and the various components in the output circuit 103 may be separately arranged to the shift register. The different positions of the circuit, while maintaining the connection between these elements to achieve the corresponding function of the output circuit 103.
  • the pull-down circuit 104 can include a transistor M7 and a transistor M9.
  • the gate of transistor M7 and the gate of transistor M9 can be connected together as the control terminal of pull-down circuit 104 and further connected to pull-down node PD.
  • the first poles of the transistor M7 and the transistor M9 may be connected together as an input terminal of the pull-down circuit 104, and further connected to the low potential terminal VGL.
  • the second pole of transistor M7 can be used as the first output of pull-down circuit 104 and connected to pull-up node PU, and the second pole of transistor M9 can be used as the second output of pull-down circuit 104 and connected to the signal of the shift register Output OUTPUT_N.
  • the transistor M7 and the transistor M9 may both be N-type transistors such that each transistor is turned on when the potential of its gate is high. It should be appreciated that the pull down circuit 104 can also be implemented in other implementations.
  • pull down circuit 104 can be implemented as an integrated circuit module.
  • the overall layout of the shift register circuit eg, the exemplary circuit configuration of the shift register shown in FIG. 2 may also be considered, and the various components in the pull-down circuit 104 may be separately arranged to the shift register.
  • the different functions of the pull-down circuit 104 are implemented at different locations of the circuit while maintaining the manner of connection between these components.
  • the gate of the transistor can be the gate of the transistor, the first pole of which can be one of the source and the drain of the transistor, and the second pole can be the source and drain of the transistor The other of the poles.
  • the first pole of transistor M1 can be its source and the second pole can be its drain; and the first pole of transistor M7 can be its drain and the second pole can be its source.
  • the first and second poles of the transistor are used interchangeably and no distinction is made herein.
  • a shift register may implement bidirectional scanning.
  • the first reference potential terminal CNB and the second reference potential terminal CN of the shift register can be set to a high potential and a low potential, respectively.
  • the first reference potential terminal CNB and the second reference potential terminal CN of the shift register can be set to a low potential and a high potential, respectively.
  • FIG. 3 illustrates a driving method of a shift register in the case of reverse scanning, which may include steps 300, 305, 310, and 315, according to an embodiment of the present disclosure.
  • step S300 the pull-up node control circuit 101 receives the first input signal via the first signal input terminal INPUT1 of the shift register, causes the potential of the pull-up node PU to be high, and charges the capacitor C1.
  • This step may correspond to the input phase of the shift register.
  • step S305 the output circuit 103 receives the first clock signal via the first clock signal terminal CK1 of the shift register.
  • the capacitor C1 is caused by the bootstrap action so that the potential of the pull-up node PU continues to rise, ensuring that the transistor M10 of the output circuit 103 is sufficiently turned on, thereby outputting the gate drive signal at the signal output terminal OUTPUT of the shift register.
  • This step may correspond to the output stage of the shift register.
  • step S310 the pull-down node control circuit 102 receives the second clock signal and the second input signal via the second clock signal terminal CK2 and the second signal input terminal INPUT2 of the shift register, respectively, so that the potential of the pull-down node PD becomes a high potential, and The potential of the pull-up node PU and the signal output terminal OUTPUT becomes a low potential.
  • This step may correspond to the reset phase of the shift register.
  • step S315 the pull-down node PD is maintained at a high potential until the next first input signal is received.
  • This step may correspond to the sustain phase of the shift register.
  • the first reference potential terminal CNB and the second reference potential terminal CN are set to a low potential and a high potential, respectively.
  • the pull-up node control circuit 101 receives the second input signal via the second signal input terminal INPUT2 of the shift register.
  • the pull-down node control circuit 102 receives the third clock signal and the first input signal via the third clock signal terminal CK3 of the shift register and the first signal input terminal INPUT1, respectively. Others are similar to the case of reverse scanning and will not be repeated here.
  • FIG. 4 shows the operation timing of the shift register in the case of reverse scanning as shown in FIG. 2 according to an embodiment of the present disclosure.
  • the potential of the first reference potential terminal CNB is high, and the potential of the second reference potential terminal CN is low, so that the transistor M1 in the pull-down node control circuit 102 is always turned on, and the transistor M2 Always shut down. Therefore, in the case of reverse scanning, the third The clock signal does not work.
  • the shift register receives the first input signal via the first signal input terminal INPUT1, and the second signal input terminal INPUT2, the second clock signal terminal CK2 and the first clock signal terminal CK1 have no signal input.
  • the transistor M3 in the pull-up node control circuit 101 is turned on, so that the potential of the pull-up node PU is the same as the potential of the first reference potential terminal CNB, that is, becomes a high potential. Capacitor C1 is charged.
  • the second clock signal is not received, that is, the potential of the second clock signal terminal CK2 is low, and therefore the transistor M5 in the pull-down node control circuit 102 is turned off.
  • the transistor M6 in the pull-down node control circuit 102 is turned on because the potential of the pull-up node PU is high, so that the potential of the pull-down node PD is the same as the potential of the low-potential terminal VGL, that is, becomes a low potential. Further, the potential of the pull-up node PU becomes a high potential and the transistor M10 in the output circuit 103 is turned on. However, since the first clock signal CK1 is not received at this time, there is no gate drive signal output at the signal output terminal OUTPUT.
  • the shift register receives the first clock signal via the first clock signal terminal CK1, and the first signal input terminal INPUT1, the second signal input terminal INPUT2, and the second clock signal terminal CK2 have no signal input. .
  • the transistor M3 and the transistor M4 in the pull-up node control circuit 101 are both turned off.
  • the potential of the pull-up node PU continues to rise due to the bootstrap action of the capacitor C1.
  • the potential of the pull-down node PD continues to remain low due to the conduction of the transistor M6 in the pull-down node control circuit 102.
  • the transistor M10 in the output circuit 103 is turned on, and outputs a gate drive signal at the signal output terminal OUTPUT due to the reception of the first clock signal.
  • the potential of the pull-up node PU continues to rise due to the bootstrap action of the capacitor C1. Therefore, even if the threshold voltage of the transistor in the output circuit 103 will drift, the potential of the pull-up node PU can be guaranteed to the output circuit 103.
  • the transistor in the transistor is fully turned on to ensure the normal output of the gate drive signal.
  • the shift register receives the second input signal and the second clock signal via the second signal input terminal INPUT2 and the second clock signal terminal CK2, respectively, and the first signal input terminal INPUT1 and the first clock signal There is no signal input at terminal CK1.
  • the transistor M4 in the pull-up node control circuit 101 is turned on, so that the potential of the pull-up node PU becomes the same as the potential of the second reference potential terminal CN, that is, becomes a low potential, so that the transistor 10 in the output circuit 103 is turned off.
  • the transistor M1 and the transistor M5 in the pull-down node control circuit 102 are turned on, and the transistor M6 is turned off, so that the potential of the pull-down node PD becomes the same as the potential of the high-potential terminal VGH, that is, becomes a high potential.
  • Capacitor C2 begins to charge.
  • the pull-down circuit 104 Since the potential of the pull-down node PD becomes a high potential, the pull-down circuit 104 The transistor M7 and the transistor M9 are turned on, respectively, respectively, the pull-up node PU and the signal output terminal OUTPUT are connected to the low-potential terminal VGL, so that the potential of the pull-up node PU and the signal output terminal OUTPUT becomes a low potential, thereby completing the pull-up node PU. And reset of the potential of the signal output terminal OUTPUT.
  • the transistor M5 in the pull-down node control circuit 102 is turned on, so that the pull-down node PD communicates with the high potential terminal VGH to maintain the high potential state, thereby causing the pull-down circuit
  • the transistor M7 and the transistor M9 in 104 are turned on, thereby keeping the potential of the pull-up node PU and the signal output terminal OUTPUT low.
  • the transistor M5 in the pull-down node control circuit 102 is turned off, and the pull-down node PD is maintained at a high potential state due to the bootstrap action of the capacitor C2, thereby causing the transistor M7 in the pull-down circuit 104.
  • the transistor M9 is turned on to keep the potential of the pull-up node PU and the signal output terminal OUTPUT low.
  • the potential of the pull-down node PD is always high before the next input stage, thereby ensuring that the potential of the pull-up node PU and the signal output terminal OUTPUT is low, effectively avoiding the introduction of noise in the non-operating state.
  • FIG. 5 illustrates an operation timing of a shift register in the case of forward scanning according to an embodiment of the present disclosure, the process of which is similar to that in the case of reverse scanning, and is not repeated herein.
  • a plurality of the above-described shift registers may be cascaded together to form a gate drive circuit.
  • Fig. 6 is a partial schematic view showing the gate driving circuit showing the connection relationship between three shift registers of the adjacent N-1th stage, Nth stage, and N+1th stage.
  • each stage shift register other than the last stage can be connected to the signal output end of the next stage shift register, and the levels other than the first stage are shifted.
  • the second signal input of the bit register is coupled to the signal output of its previous stage shift register.
  • the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal of the N-1th stage shift register may be respectively connected to the clock signal lines CKL3, CKL1, and CKL2; the Nth stage shift The first clock signal end, the second clock signal end and the third clock signal end of the register may be respectively connected to the clock signal lines CKL2, CKL4 and CKL1; the first clock signal end of the N+1th stage shift register, the second clock The signal terminal and the third clock signal terminal may be connected to the clock signal lines CKL1, CKL3, and CKL4, respectively.
  • the clock signals supplied via the clock signal line CKL1, the clock signal line CKL2, the clock signal line CKL3, and the clock signal line CKL4, respectively, in the case of reverse scanning are as shown in FIG.
  • the clock signals supplied via the clock signal line CKL1, the clock signal line CKL2, the clock signal line CKL3, and the clock signal line CKL4, respectively, in the case of forward scanning are as shown in FIG.
  • the display device 10 includes a gate driving circuit 11 and a pixel array 12 according to any of the above embodiments.
  • the driving circuit 11 is for supplying a gate scan signal to each row of pixel units 13 in the pixel array 11.
  • An example of the display device is a liquid crystal display device in which an array substrate and a counter substrate are opposed to each other to form a liquid crystal cell in which a liquid crystal material is filled.
  • the pixel electrode of each pixel unit of the array substrate is used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • a gate driving circuit is formed on the array substrate.
  • OLED organic electroluminescence display device
  • a pixel electrode of each pixel unit serves as an anode or a cathode for driving the organic light emitting material to emit light for display.
  • a gate driving circuit is formed on the array substrate.
  • Still another example of the display device is an electronic paper display device in which an electronic ink layer is formed on an array substrate, and a pixel electrode of each pixel unit serves as a voltage for applying a charged microparticle moving in the driving electronic ink to perform a display operation .
  • a gate driving circuit is formed on the array substrate.
  • Such a display device may be a smart phone, a notebook computer, a tablet computer, a personal digital assistant (PDA), or any other display device using GOA technology.
  • PDA personal digital assistant
  • the embodiment of the shift register and its driving method, the gate driving circuit, and the display device according to the present disclosure has been described above. According to the shift register and the driving method thereof of the embodiments of the present disclosure, it is possible to ensure that the bootstrap function of the capacitor at the output gate signal stage is always effective, thereby ensuring that the potential of the pull-up node maintains a high potential during the output gate signal phase, so that the output The transistor is fully active at the output gate signal stage Open. Thereby, the normal output of the gate drive signal can be ensured, and the normal display of the display screen is further ensured. In addition, it is also possible to prevent the gate drive circuit from introducing noise in a non-operating state.

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Abstract

一种移位寄存器及其驱动方法、栅极驱动电路（11）和显示装置（10）。该移位寄存器包括：上拉节点控制电路（101），根据由第一信号输入端（INPUT1）和第二信号输入端（INPUT2）接收的第一输入信号和第二输入信号，使上拉节点（PU）的电位成为高电位；第一电容器（C1），连接在移位寄存器的信号输出端（OUTPUT）和上拉节点（PU）之间；下拉节点控制电路（102），根据由第二时钟信号端（CK2）和第三时钟信号端（CK3）接收的第二时钟信号和第三时钟信号以及上拉节点（PU）的电位，控制下拉节点（PD）的电位；输出电路（103），根据上拉节点（PU）的电位以及由第一时钟信号端（CK1）接收的第一时钟信号，控制在信号输出端（OUTPUT）处的栅极驱动信号的输出；以及下拉电路（104），根据下拉节点（PD）的电位，使上拉节点（PU）和信号输出端（OUTPUT）的电位成为低电位。

Description

移位寄存器及其驱动方法、栅极驱动电路和显示装置 技术领域
本公开涉及一种移位寄存器及其驱动方法、包括该移位寄存器的栅极驱动电路以及显示装置。
背景技术
随着显示技术的不断发展，越来越多的显示装置采用GOA(Gate on Array，阵列基板栅极驱动)技术，即通过阵列工艺将栅极驱动电路形成在显示装置的陈列基板上。采用GOA技术可以节省成本，并且可以实现显示面板的两边对称的美观设计，同时可以省去栅极驱动电路的绑定区域以及扇出的布线空间，从而可以实现窄边框的设计。另外GOA技术还可以省去栅极扫描线方向的绑定工艺，从而提供产能和良率。
在N型双向扫描GOA电路中的每一级的移位寄存器中，上拉节点的电容的一端通常连接低电位，导致在输出栅极信号阶段，该电容的自举功能失效，使上拉节点的电位无法保征输出晶体管能够充分开启。例如，在高低温可靠性测试过程中，输出晶体管的阈值电压将发生漂移。在这样的情况下，上拉节点的电位无法维持高电位，造成栅极驱动信号输出异常，进而造成显示屏的显示不良或异常。
发明内容
根据本公开的一方面，提供一种移位寄存器，其包括：上拉节点控制电路，用于根据分别经由移位寄存器的第一信号输入端和第二信号输入端接收的第一输入信号和第二输入信号，使移位寄存器内部的上拉节点的电位成为高电位；第一电容器，连接在移位寄存器的信号输出端和上拉节点之间；下拉节点控制电路，用于根据分别经由移位寄存器的第二时钟信号端、第三时钟信号端接收的第二时钟信号和第三时钟信号以及上拉节点的电位，控制下拉节点的电位；输出电路，用于根据上拉节点的电位以及经由移位寄存器的第一时钟信号端接收的第一时钟信号，控制在信号输出端处的栅极驱动信号 的输出；以及下拉电路，用于根据下拉节点的电位，使上拉节点和信号输出端的电位成为低电位。
例如，所述移位寄存器还可以包括第二电容器，其连接在移位寄存器的低电位端与下拉节点之间。
例如，所述上拉节点控制电路可以包括：第一晶体管，其控制极连接到第一信号输入端，其第一极连接到移位寄存器的第一参考电位端，其第二极连接到上拉节点；以及第二晶体管，其控制极连接到第二信号输入端，其第一极连接到移位寄存器的第二参考电位端，其第二极连接到上拉节点。
例如，所述下拉节点控制电路可以包括：第三晶体管，其控制极连接到移位寄存器的第一参考电位端，其第一极连接到第二时钟信号端；第四晶体管，其控制极连接到移位寄存器的第二参考电位端，其第一极连接到第三时钟信号端；第五晶体管，其控制极连接到第三晶体管和第四晶体管的第二极，其第一极连接到移位寄存器的高电位端，其第二极连接到下拉节点；以及第六晶体管，其控制极连接到上拉节点，其第一极连接到下拉节点，其第二极连接到低电位端。
例如，所述输出电路可以包括：第七晶体管，其控制极连接到上拉节点，其第一极连接到第一时钟信号端，其第二极连接到信号输出端。
例如，所述输出电路还包括：第八晶体管，其控制极连接到移位寄存器的高电位端，其第一极连接到上拉节点，其第二极连接到所述第八晶体管的控制极。
例如，所述下拉电路可以包括：第九晶体管，其控制极连接到下拉节点，其第一极连接到低电位端，其第二极连接到上拉节点；第十晶体管，其控制极连接到下拉节点，其第一极连接到低电位端，其第二极连接到信号输出端。
例如，所有的晶体管为N型晶体管。
根据本公开的另一方面，提供一种栅极驱动电路，其包括多个级联的上述任意一种移位寄存器，其中，最后一级之外的各级移位寄存器的第一信号输入端连接到其下一级移位寄存器的信号输出端，并且第一级之外的各级移位寄存器的第二信号输入端连接到其上一级移位寄存器的信号输出端。
根据本公开的另一方面，提供一种显示装置，其包括如上所述的任一意种栅极驱动电路。
根据本公开的另一方面，提供一种驱动方法，可以用于驱动上述任意一种移位寄存器。该驱动方法包括：接收第一输入信号，使上拉节点的电位成为高电位，并对第一电容器充电；接收第一时钟信号，通过第一电容器将上拉节点的电位进一步拉高，同时在信号输出端输出栅极驱动信号；接收第二时钟信号和第二输入信号，使上拉节点和信号输出端的电位成为低电位；以及维持下拉节点处于高电位。
在该方法中，反向扫描时，将移位寄存器的第一参考电位端和第二参考电位端分别置为高电位和低电位；正向扫描时，将第一参考电位端和第二参考电位端分别置为低电位和高电位。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1示出根据本公开的实施例的移位寄存器所包括的电路。
图2示出根据本公开的实施例的移位寄存器所包括的电路的示例性的实现方式。
图3示出根据本公开的实施例的移位寄存器的驱动方法。
图4示出根据本公开的实施例的移位寄存器的一个示例性的工作时序。
图5示出根据本公开的实施例的移位寄存器的另一个示例性的工作时序。
图6示出根据本公开的实施例的栅极驱动电路的局部示意图。
图7示出根据本公开的实施例的栅极驱动电路在反向扫描的情况下的时钟信号。
图8示出根据本公开的实施例的栅极驱动电路在正向扫描的情况下的时钟信号。
图9示出根据本公开的实施例的显示装置的示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
下面参照附图并结合实施例来描述根据本公开的移位寄存器及其驱动方法、栅极驱动电路和显示装置。
本公开的实施例提供一种移位寄存器及其驱动方法、包含该移位寄存器的栅极驱动电路以及显示装置，以确保上拉节点的电容在输出栅极信号阶段的自举功能始终有效，从而保证上拉节点的电位在输出栅极信号阶段维持高电位，使得输出晶体管在输出栅极信号阶段充分开启。由此，确保栅极驱动信号的正常输出，并且进一步地确保显示屏的正常显示。
如图1所示，根据本公开的实施例的移位寄存器可以设置有用于接收第一输入信号的第一信号输入端INPUT1、用于接收第二输入信号的第二信号输入端INPUT2、用于接收第二时钟信号的第二时钟信号端CK2、用于接收第三时钟信号的第三时钟信号端CK3、用于接收第一时钟信号的第一时钟信号端CK1、用于设置第一参考电位的第一参考电位端CNB、用于设置第二参考电位的第二参考电位端CN、用于输出栅极驱动信号的信号输出端OUTPUT、高电位端VGH和低电位端VGL。在移位寄存器的内部，存在上拉节点PU和下拉节点PD，并且可以包含上拉节点控制电路101、电容器C1、下拉节点控制电路102、输出电路103和下拉电路104。
上拉节点控制电路101可以设置有第一控制端、第二控制端、第一输入 端、第二输入端和输出端。例如，在第一控制端的电位为高电位的情况下，第一输入端和输出端连通，使得输出端的电位变成与第一输入端的电位相同。例如，在第二控制端的电位为高电位的情况下，第二输入端和输出端连通，使得输出端的电位变成与第二输入端的电位相同。
在图1的示例中，上拉节点控制电路101的第一控制端、第二控制端、第一输入端、第二输入端和输出端可以分别连接到移位寄存器的第一信号输入端INPUT1、第二信号输入端INPUT2、第一参考电位CNB、第二参考电位端CN和上拉节点PU。在该示例中，在移位寄存器经由第一信号输入端INPUT1接收到第一输入信号的情况下，上拉节点PU的电位可以变成与第一参考电位CNB的电位相同；经由第二信号输入端INPUT2接收到第二输入信号的情况下，上拉节点PU的电位可以变成与第二参考电位CN的电位相同。由此，通过上拉节点控制电路101，能够根据所接收的第一输入信号和第二输入信号，使上拉节点PU的电位成为例如高电位。
在图1的示例中，电容器C1的一端连接到上拉节点PU，另一端连接到信号输出端OUTPUT。
下拉节点控制电路102可以设置有第一控制选择端、第二控制选择端、第一控制端、第二控制端、第三控制端、第一输入端、第二输入端和输出端。例如，在第一控制选择端的电位为高电位的情况下，选择根据第一控制端的电位来控制第一输入端和输出端之间的连通和断开，其中，第一输入端和输出端在第一控制端的电位的电位为低电位的情况下断开，而在第一控制端的电位的电位为高电位的情况下连通，使得输出端的电位变成与第一输入端的电位相同。例如，在第二控制选择端的电位为高电位的情况下，选择根据第二控制端的电位来控制第一输入端和输出端之间的连通和断开，其中，第一输入端和输出端在第二控制端的电位的电位为低电位的情况下断开，而在第二控制端的电位的电位为高电位的情况下连通，使得输出端的电位变成与第一输入端的电位相同。第二输入端和输出端在第三控制端的电位为高电位的情况下连通，使得输出端的电位变成与第二输入端的电位相同。
在图1的示例中，下拉节点控制电路102的第一控制选择端、第二控制选择端、第一控制端、第二控制端、第三控制端、第一输入端、第二输入端和输出端可以分别连接到移位寄存器的第一参考电位CNB、第二参考电位端 CN、第二时钟信号端CK2、第三时钟信号端CK3、上拉节点PU、高电位端VGH、低电位端VGL和下拉节点PD。在该示例中，在第一参考电位CNB的电位为高电位的情况下，选择根据经由第二时钟信号端CK2所接收的第二时钟信号来控制高电位端VGH与下拉节点PD之间的连通和断开，其中，高电位端VGH与下拉节点PD在接收到第二时钟信号的情况下连通，使得下拉节点PD的电位成为高电位；在第二参考电位CN的电位为高电位的情况下，选择根据经由第三时钟信号端CK3所接收的第三时钟信号来控制高电位端VGH与下拉节点PD之间的连通和断开，其中，高电位端VGH与下拉节点PD在接收到第三时钟信号的情况下连通，使得下拉节点PD的电位成为高电位。另外，在上拉节点PU的电位为高电位的情况下，下拉节点PD与低电位端VGL连通，使得下拉节点PD的电位成为低电位。由此，通过下拉节点控制电路102，能够根据所接收的第二时钟信号或第三时钟信号或上拉节点的电位来控制的下拉节点的电位。
输出电路103可以设置有控制端、输入端和输出端，其中，例如输入端和输出端在控制端的电位为高电位的情况下连通，使得输出端的电位与输入端的电位相同。
在图1的示例中，输出电路103的控制端、输入端和输出端可以分别连接到移位寄存器的上拉节点PU、第一时钟信号端CK1和信号输出端OUTPUT，使得在上拉节点PU的电位为高电位的情况下，信号输出端OUTPUT能够根据经由第一时钟信号端CK1所接收到的第一时钟信号来输出栅极驱动信号。由此，通过输出电路103，能够根据上拉节点PU的电位以及第一时钟信号来控制在信号输出端OUTPUT处的栅极驱动信号的输出。
下拉电路104可以设置有控制端、输入端、第一输出端和第二输出端，其中，例如在下拉电路104的第一控制端的电位为高电位的情况下，下拉电路104的输入端和第一输出端连通，并且下拉电路104的输入端和第二输出端连通，使得下拉电路104的第一输出端的电位和第二输出端的电位均与其输入端的电位相同。
在图1的示例中，下拉电路104的控制端、输入端、第一输出端和第二输出端可以分别连接到移位寄存器的下拉节点PD、低电位端VGL、上拉节点PU和信号输出端OUTPUT，使得在下拉节点PD的电位为高电位的情况 下，上拉节点PU和信号输出端OUTPUT的电位能够成为低电位。
如图1所示，根据本公开的实施例的移位寄存器还可以包括电容器C2。在图1的示例中，电容器C2的一端连接到下拉节点PD，另一端连接到移位寄存器的低电位端VGL。
图2示出图1所示的根据本公开的实施例的移位寄存器所包含的各个电路的示例性的实现方式。
在图2的示例中，上拉节点控制电路101可以包含晶体管M3和晶体管M4。晶体管M3的控制极可以作为上拉节点控制电路101的第一控制端并且连接到移位寄存器的第一信号输入端INPUT1，其第一极可以作为上拉节点控制电路101的第一输入端并且连接到移位寄存器的第一参考信号端CNB。晶体管M4的控制极可以作为上拉节点控制电路101的第二控制端并且连接到移位寄存器的第二信号输入端INPUT2，其第一极可以作为上拉节点控制电路101的第二输入端并且连接到移位寄存器的第一参考信号端CN。可以将晶体管M3和晶体管M4的第二极连接到一起，且作为上拉节点控制电路101的输出端，并且进一步地连接到上拉节点PU。例如，晶体管M3和晶体管M4可以均为N型晶体管，使得各晶体管在其控制极的电位高电位时导通。应当意识到，上拉节点控制电路101也可以通过其他的实现方式来实现。
在一个实施例中，可以将上拉节点控制电路101实现为一个集成电路模块。在另外的实施例中，也可以考虑移位寄存器电路的整体布局(例如，图2所示的移位寄存器的示例性的电路结构)，将上拉节点控制电路101中的各个元件分别布置到移位寄存器电路的不同位置处，同时保持这些元件之间的连接方式以实现上拉节点控制电路101的相应的功能。
在图2的示例中，下拉节点控制电路102可以包含晶体管M1、晶体管M2、晶体管M5和晶体管M6。晶体管M1的控制极可以作为下拉节点控制电路102的第一控制选择端并且连接到移位寄存器的第一参考电位CNB，其第一极可以作为下拉节点控制电路102的第一控制端并且连接到移位寄存器的第二时钟信号端CK2。晶体管M2的控制极可以作为下拉节点控制电路102的第二控制选择端并且连接到移位寄存器的第二参考电位CN，其第一极可以作为下拉节点控制电路102的第二控制端并且连接到移位寄存器的第三时钟信号端CK3。晶体管M5的第一极可以作为下拉节点控制电路102的第一 输入端并且连接到移位寄存器的高电位端VGH，其第二极可以作为下拉节点控制电路102的输出端并且连接到移位寄存器的下拉节点PD。可以将晶体管M1和M2的第二极连接到一起，并且都连接到晶体管M5的控制极，使得能够根据第二时钟信号或第三时钟信号控制晶体管M5的导通和关断。晶体管M6的控制极可以作为下拉节点控制电路102的第三控制端并且连接到上拉节点PU，其第二极可以作为下拉节点控制电路102的第二输入端并且连接到移位寄存器的低电位端VGL，其第一极可以连接到晶体管M5的第二极(即作为下拉节点控制电路102的输出端)并且进一步地连接到下拉节点PD。可以根据需要来设置不同尺寸的晶体管M5和M6，以便控制下拉节点PD在晶体管M5和M6均导通的情况下的电位。例如，如果想要使下拉节点PD在晶体管M5和M6均导通的情况下的电位为低电位，可以选择采用不同尺寸的晶体管M5和M6，使得晶体管M6的导通电阻相对于晶体管M5的导通电阻小得多；如果想要使下拉节点PD在晶体管M5和M6均导通的情况下的电位为高电位，可以选择采用不同尺寸的晶体管M5和M6，使得晶体管M6的导通电阻相对于晶体管M5的导通电阻大得多。例如，晶体管M1、晶体管M2、晶体管M5和晶体管M6可以均为N型晶体管，使得各晶体管在其控制极的电位高电位时导通。应当意识到，下拉节点控制电路102也可以通过其他的实现方式来实现。
在一个实施例中，可以将下拉节点控制电路102实现为一个集成电路模块。在另外的实施例中，也可以考虑移位寄存器电路的整体布局(例如，图2所示的移位寄存器的示例性的电路结构)，将上拉节点控制电路102中的各个元件分别布置到移位寄存器电路的不同位置处，同时保持这些元件之间的连接方式以实现上拉节点控制电路102的相应的功能。
在图2的示例中，输出电路103可以包括晶体管M10，其控制极、第一极和第二极可以分别作为输出电路103的控制端、输入端和输出端。例如，晶体管M10可以为N型晶体管，使得该晶体管在其控制极的电位高电位时导通。应当意识到，输出电路103也可以通过其他的实现方式来实现。例如，如图2所示，输出电路103还可以包括晶体管M8。可以将晶体管M8的控制极连接到高电位端以使得晶体管M8一直导通，将晶体管M8的第一极连接作为输出电路103的控制端，并且将晶体管M8的第二极与晶体管M10的 控制极相连。设置M8可以使得PU节点的电压的变化不会直接影响到输出电路103中的晶体管M10的栅极的电压，使得晶体管M10的栅极处的电位更加稳定，从而提供更稳定的输出。例如，晶体管M8也可以为N型晶体管，使得该晶体管在其控制极的电位高电位时导通。
在一个实施例中，可以将输出电路103实现为一个集成电路模块。在另外的实施例中，也可以考虑移位寄存器电路的整体布局(例如，图2所示的移位寄存器的示例性的电路结构)，将输出电路103中的各个元件分别布置到移位寄存器电路的不同位置处，同时保持这些元件之间的连接方式以实现输出电路103的相应的功能。
在图2的示例中，下拉电路104可以包括晶体管M7和晶体管M9。可以将晶体管M7的控制极和晶体管M9的控制极连接到一起，作为下拉电路104的控制端，并且进一步地连接到下拉节点PD。可以将晶体管M7和晶体管M9的第一极连接到一起，作为下拉电路104的输入端，并且进一步地连接到低电位端VGL。可以将晶体管M7的第二极作为下拉电路104的第一输出端并且连接到上拉节点PU，并且将晶体管M9的第二极作为下拉电路104的第二输出端并且连接到移位寄存器的信号输出端OUTPUT_N。例如，晶体管M7和晶体管M9可以均为N型晶体管，使得各晶体管在其控制极的电位高电位时导通。应当意识到，下拉电路104也可以通过其他的实现方式来实现。
在一个实施例中，可以将下拉电路104实现为一个集成电路模块。在另外的实施例中，也可以考虑移位寄存器电路的整体布局(例如，图2所示的移位寄存器的示例性的电路结构)，将下拉电路104中的各个元件分别布置到移位寄存器电路的不同位置处，同时保持这些元件之间的连接方式以实现下拉电路104的相应的功能。
就每个晶体管而言，该晶体管的控制极可以是该晶体管的栅极，其第一极可以是该晶体管的源极和漏极中的一个，第二极可以是该晶体管的源极和漏极中的另一个。例如，晶体管M1的第一极可以是其源极，第二极可以是其漏极；而晶体管M7的第一极可以是其漏极，第二极可以是其源极。通常，晶体管的第一极和第二极可以互换地使用，本文对此不作区分。
根据本公开的实施例的移位寄存器可以实现双向扫描。在反向扫描的情 况下，可以将移位寄存器的第一参考电位端CNB和第二参考电位端CN分别置为高电位和低电位。在正向扫描的情况下，可以将移位寄存器的第一参考电位端CNB和第二参考电位端CN分别置为低电位和高电位。
图3示出根据本公开的实施例的移位寄存器的在反向扫描的情况下的驱动方法，可以包括步骤300、305、310和315。
在步骤S300，上拉节点控制电路101经由移位寄存器的第一信号输入端INPUT1接收第一输入信号，使上拉节点PU的电位成为高电位，并对电容器C1进行充电。该步骤可以对应于移位寄存器的输入阶段。
在步骤S305，输出电路103经由移位寄存器的第一时钟信号端CK1接收第一时钟信号。在此期间，电容器C1通过自举作用，使得上拉节点PU的电位继续上升，确保输出电路103的晶体管M10充分开启，从而在移位寄存器的信号输出端OUTPUT处输出栅极驱动信号。该步骤可以对应于移位寄存器的输出阶段。
在步骤S310，下拉节点控制电路102分别经由移位寄存器的第二时钟信号端CK2和第二信号输入端INPUT2接收第二时钟信号和第二输入信号，使得下拉节点PD的电位成为高电位，并且上拉节点PU和信号输出端OUTPUT的电位成为低电位。该步骤可以对应于移位寄存器的复位阶段。
在步骤S315，维持下拉节点PD处于高电位，直至接收到下一个第一输入信号为止。该步骤可以对应于移位寄存器的维持阶段。
在正向扫描的情况下，第一参考电位端CNB和第二参考电位端CN分别置为低电位和高电位。在输入阶段，上拉节点控制电路101经由移位寄存器的第二信号输入端INPUT2接收第二输入信号。在复位阶段，下拉节点控制电路102分别经由移位寄存器的第三时钟信号端CK3和第一信号输入端INPUT1接收第三时钟信号和第一输入信号。其他与反向扫描的情况下相似，在此不再重复。
图4示出如图2所示的根据本公开的实施例的移位寄存器在反向扫描的情况下的工作时序。
在反向扫描的情况下，第一参考电位端CNB的电位为高电位，而第二参考电位端CN的电位为低电位，使得下拉节点控制电路102中的晶体管M1始终导通，而晶体管M2始终关断。因此，在反向扫描的情况下，第三 时钟信号不起作用。
在输入阶段，移位寄存器经由第一信号输入端INPUT1接收到第一输入信号，而第二信号输入端INPUT2、第二时钟信号端CK2和第一时钟信号端CK1均无信号输入。上拉节点控制电路101中的晶体管M3导通，使得上拉节点PU的电位与第一参考电位端CNB的电位相同，即成为高电位。电容器C1充电。此时，未接收到第二时钟信号，即第二时钟信号端CK2的电位为低电位，因此下拉节点控制电路102中的晶体管M5关断。同时，下拉节点控制电路102中的晶体管M6由于上拉节点PU的电位为高电位而导通，使得下拉节点PD的电位与低电位端VGL的电位相同，即成为低电位。另外，上拉节点PU的电位成为高电位还使得输出电路103中的晶体管M10导通。然而，由于此时未接收到第一时钟信号CK1，所以在信号输出端OUTPUT没有栅极驱动信号输出。
在输入阶段之后的输出阶段，移位寄存器经由第一时钟信号端CK1接收到第一时钟信号，而第一信号输入端INPUT1、第二信号输入端INPUT2、第二时钟信号端CK2均无信号输入。上拉节点控制电路101中的晶体管M3和晶体管M4均关断。上拉节点PU的电位由于电容器C1的自举作用而继续上升。下拉节点PD的电位由于下拉节点控制电路102中的晶体管M6的导通而继续保持为低电位。输出电路103中的晶体管M10导通，并且由于接收到第一时钟信号而在信号输出端OUTPUT输出栅极驱动信号。在输出阶段，上拉节点PU的电位由于电容器C1的自举作用而继续上升，因此，即使输出电路103中的晶体管的阈值电压将发生漂移，上拉节点PU的电位也能够保征输出电路103中的晶体管充分开启，从而确保栅极驱动信号的正常输出。
在输出阶段之后的复位阶段，移位寄存器分别经由第二信号输入端INPUT2和第二时钟信号端CK2接收到第二输入信号和第二时钟信号，而第一信号输入端INPUT1和第一时钟信号端CK1均无信号输入。上拉节点控制电路101中的晶体管M4导通，使得上拉节点PU的电位变成与第二参考电位端CN的电位相同，即成为低电位，使得输出电路103中的晶体管10关断。下拉节点控制电路102中的晶体管M1和晶体管M5导通，晶体管M6关断，使得下拉节点PD的电位变成与高电位端VGH的电位相同，即成为高电位。电容器C2开始充电。由于下拉节点PD的电位成为高电位，下拉电路104 中的晶体管M7和晶体管M9导通，分别使上拉节点PU和信号输出端OUTPUT与低电位端VGL连通，使得上拉节点PU和信号输出端OUTPUT的电位成为低电位，从而完成上拉节点PU和信号输出端OUTPUT的电位的复位。
在复位阶段之后、下一个输入阶段之前，第一信号输入端INPUT1和第二信号输入端INPUT2均无信号输入。在经由第二时钟信号端CK2接收到第二时钟信号的情况下，下拉节点控制电路102中的晶体管M5导通，使得下拉节点PD与高电位端VGH连通以保持高电位状态，进而使得下拉电路104中的晶体管M7和晶体管M9导通，从而保持上拉节点PU和信号输出端OUTPUT的电位为低电位。在没有接收到第二时钟信号的情况下，下拉节点控制电路102中的晶体管M5关断，下拉节点PD由于电容器C2的自举作用而保持在高电位状态，从而使得下拉电路104中的晶体管M7和晶体管M9导通，以保持上拉节点PU和信号输出端OUTPUT的电位为低电位。由此，下拉节点PD的电位在下一个输入阶段之前始终为高电位，从而确保上拉节点PU和信号输出端OUTPUT的电位为低电位，有效地避免了在非工作状态引入噪声。
在正向扫描的情况下，第一参考电位端CNB的电位为低电位，而第二参考电位端CN的电位为高电位，使得下拉节点控制电路102中的晶体管M2始终导通，而晶体管M1始终关断。因此，在正向扫描的情况下，第二时钟信号不起作用。图5示出根据本公开的实施例的移位寄存器在正向扫描的情况下的工作时序，其过程与在反向扫描的情况下的相似，在本文中不再重复。
在本公开的一个实施例中，可以将多个上述的移位寄存器级联在一起以形成栅极驱动电路。
图6示出该栅极驱动电路的局部示意图，其中示出相邻的第N-1级、第N级和第N+1级的三个移位寄存器之间的连接关系。
如图6所示，可以将最后一级之外的各级移位寄存器的第一信号输入端连接到其下一级移位寄存器的信号输出端，并且将第一级之外的各级移位寄存器的第二信号输入端连接到其上一级移位寄存器的信号输出端。
可以经由时钟信号线CKL1、时钟信号线CKL2、时钟信号线CKL3和 时钟信号线CKL4分别提供四个时钟信号。如图6所示，第N-1级移位寄存器的第一时钟信号端、第二时钟信号端和第三时钟信号端可以分别连接到时钟信号线CKL3、CKL1和CKL2；第N级移位寄存器的第一时钟信号端、第二时钟信号端和第三时钟信号端可以分别连接到时钟信号线CKL2、CKL4和CKL1；第N+1级移位寄存器的第一时钟信号端、第二时钟信号端和第三时钟信号端可以分别连接到时钟信号线CKL1、CKL3和CKL4。在反向扫描的情况下的分别经由时钟信号线CKL1、时钟信号线CKL2、时钟信号线CKL3和时钟信号线CKL4提供的时钟信号如图7所示。在正向扫描的情况下的分别经由时钟信号线CKL1、时钟信号线CKL2、时钟信号线CKL3和时钟信号线CKL4提供的时钟信号如图8所示。
另外，在本公开的另一个实施例中，提供了一种显示装置，如图9所示，该显示装置10包括根据上述任一实施例的栅极驱动电路11以及像素阵列12，该栅极驱动电路11用于为像素阵列11中各行像素单元13提供栅极扫描信号。
该显示装置的一个示例为液晶显示装置，其中，阵列基板与对置基板彼此对置以形成液晶盒，在液晶盒中填充有液晶材料。阵列基板的每个像素单元的像素电极用于施加电场对液晶材料的旋转的程度进行控制从而进行显示操作。栅极驱动电路形成在阵列基板上。
该显示装置的另一个示例为有机电致发光显示装置(OLED)，阵列基板上形成有有机发光材料叠层，每个像素单元的像素电极作为阳极或阴极用于驱动有机发光材料发光以进行显示操作。栅极驱动电路形成在阵列基板上。
该显示装置的再一个示例为电子纸显示装置，其中，阵列基板上形成有电子墨水层，每个像素单元的像素电极作为用于施加驱动电子墨水中的带电微颗粒移动以进行显示操作的电压。栅极驱动电路形成在阵列基板上。
这样的显示装置可以是智能电话、笔机本电脑、平板计算机、个人数字助理(PDA)或者其他任何一种采用GOA技术的显示装置。
以上描述了根据本公开的移位寄存器及其驱动方法、栅极驱动电路和显示装置的实施例。根据本公开的实施例的移位寄存器及其驱动方法，能够确保电容在输出栅极信号阶段的自举功能始终有效，从而保证上拉节点的电位在输出栅极信号阶段维持高电位，使得输出晶体管在输出栅极信号阶段充分 开启。由此，能够确保栅极驱动信号的正常输出，并且进一步地确保显示屏的正常显示。另外，还可以避免栅极驱动电路在非工作状态引入噪声。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2017年1月24日递交的中国专利申请第201710059304.9号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (12)

  1. 一种移位寄存器，包括：
    上拉节点控制电路，用于根据分别经由移位寄存器的第一信号输入端和第二信号输入端接收的第一输入信号和第二输入信号，使移位寄存器内部的上拉节点的电位成为高电位；
    第一电容器，连接在移位寄存器的信号输出端和上拉节点之间；
    下拉节点控制电路，用于根据分别经由移位寄存器的第二时钟信号端、第三时钟信号端接收的第二时钟信号和第三时钟信号以及上拉节点的电位，控制下拉节点的电位；
    输出电路，用于根据上拉节点的电位以及经由移位寄存器的第一时钟信号端接收的第一时钟信号，控制在信号输出端处的栅极驱动信号的输出；以及
    下拉电路，用于根据下拉节点的电位，使上拉节点和信号输出端的电位成为低电位。
  2. 如权利要求1所述的移位寄存器，还包括：
    第二电容器，连接在移位寄存器的低电位端与下拉节点之间。
  3. 如权利要求1或2所述的移位寄存器，其中，所述上拉节点控制电路包括：
    第一晶体管，其控制极连接到第一信号输入端，其第一极连接到移位寄存器的第一参考电位端，其第二极连接到上拉节点；以及
    第二晶体管，其控制极连接到第二信号输入端，其第一极连接到移位寄存器的第二参考电位端，其第二极连接到上拉节点。
  4. 如权利要求1至3中的任一项所述的移位寄存器，其中，所述下拉节点控制电路包括：
    第三晶体管，其控制极连接到移位寄存器的第一参考电位端，其第一极连接到第二时钟信号端；
    第四晶体管，其控制极连接到移位寄存器的第二参考电位端，其第一极连接到第三时钟信号端；
    第五晶体管，其控制极连接到第三晶体管和第四晶体管的第二极，其第 一极连接到移位寄存器的高电位端，其第二极连接到下拉节点；以及
    第六晶体管，其控制极连接到上拉节点，其第一极连接到下拉节点，其第二极连接到低电位端。
  5. 如权利要求1至4中的任一项所述的移位寄存器，其中，所述输出电路包括：
    第七晶体管，其控制极连接到上拉节点，其第一极连接到第一时钟信号端，其第二极连接到信号输出端。
  6. 如权利要求5所述的移位寄存器，其中，所述输出电路还包括：
    第八晶体管，其控制极连接到移位寄存器的高电位端，其第一极连接到上拉节点，其第二极连接到所述第八晶体管的控制极。
  7. 如权利要求1至6中的任一项所述的移位寄存器，其中，所述下拉电路包括：
    第九晶体管，其控制极连接到下拉节点，其第一极连接到低电位端，其第二极连接到上拉节点；
    第十晶体管，其控制极连接到下拉节点，其第一极连接到低电位端，其第二极连接到信号输出端。
  8. 如权利要求3至7中的任一项所述的移位寄存器，其中，所有的晶体管为N型晶体管。
  9. 一种栅极驱动电路，包括多个级联的如权利要求1至8中的任一项所述的移位寄存器，其中，
    最后一级之外的各级移位寄存器的第一信号输入端连接到其下一级移位寄存器的信号输出端，并且
    第一级之外的各级移位寄存器的第二信号输入端连接到其上一级移位寄存器的信号输出端。
  10. 一种显示装置，包括如权利要求9所述的栅极驱动电路。
  11. 一种驱动方法，用于驱动如权利要求1至8中的任一项所述的移位寄存器，包括：
    接收所述第一输入信号，使所述上拉节点的电位成为高电位，并对所述第一电容器充电；
    接收所述第一时钟信号，通过所述第一电容器进一步拉高所述上拉节点 的电位，同时在所述信号输出端输出所述栅极驱动信号；
    接收所述第二时钟信号和所述第二输入信号，使所述上拉节点和所述信号输出端的电位成为低电位；以及
    维持所述下拉节点处于高电位。
  12. 如权利要求11所述的驱动方法，其中，
    反向扫描时，将所述移位寄存器的第一参考电位端和第二参考电位端分别置为高电位和低电位，
    正向扫描时，将所述第一参考电位端和所述第二参考电位端分别置为低电位和高电位。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110060645A (zh) * 2019-05-07 2019-07-26 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、栅极驱动电路、显示装置

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107154244B (zh) * 2017-07-10 2019-08-02 深圳市华星光电技术有限公司 Goa电路及液晶显示装置
KR102523066B1 (ko) * 2017-11-21 2023-04-17 엘지디스플레이 주식회사 게이트 구동부 및 이를 포함한 전계발광 표시장치
CN208834749U (zh) * 2018-09-17 2019-05-07 北京京东方技术开发有限公司 一种移位寄存器、栅极驱动电路及显示装置
CN110223623B (zh) * 2019-06-18 2022-12-16 京东方科技集团股份有限公司 栅极驱动单元及其控制方法、栅极驱动电路、显示装置
CN110379352B (zh) * 2019-08-07 2022-02-01 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、栅极驱动电路
CN111477156A (zh) * 2020-05-13 2020-07-31 深圳市华星光电半导体显示技术有限公司 Goa电路及显示面板

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130127807A1 (en) * 2011-11-18 2013-05-23 Yong-Jae Kim Scan driver and driving method thereof
CN103714792A (zh) * 2013-12-20 2014-04-09 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路及显示装置
CN104282255A (zh) * 2014-09-25 2015-01-14 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路及其驱动方法、显示装置
CN104299583A (zh) * 2014-09-26 2015-01-21 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、驱动电路和显示装置
CN104575430A (zh) * 2015-02-02 2015-04-29 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN104700803A (zh) * 2015-03-26 2015-06-10 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路、显示面板及显示装置
CN104778928A (zh) * 2015-03-26 2015-07-15 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路、显示面板及显示装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4425547B2 (ja) * 2003-01-17 2010-03-03 株式会社半導体エネルギー研究所 パルス出力回路、シフトレジスタ、および電子機器
CN104318886B (zh) * 2014-10-31 2017-04-05 京东方科技集团股份有限公司 一种goa单元及驱动方法，goa电路和显示装置
CN105047160B (zh) * 2015-08-24 2017-09-19 武汉华星光电技术有限公司 一种扫描驱动电路
CN105096803B (zh) * 2015-08-26 2017-11-14 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN105118416B (zh) * 2015-09-23 2018-01-05 深圳市华星光电技术有限公司 一种goa电路、显示装置和goa电路的驱动方法
CN105118418B (zh) * 2015-09-25 2017-08-11 京东方科技集团股份有限公司 一种移位寄存器、其驱动方法、栅极驱动电路及显示装置
CN105118417B (zh) * 2015-09-25 2017-07-25 京东方科技集团股份有限公司 一种移位寄存器、其驱动方法、栅极驱动电路及显示装置
CN105206246B (zh) * 2015-10-31 2018-05-11 武汉华星光电技术有限公司 扫描驱动电路及具有该电路的液晶显示装置
CN105405406B (zh) * 2015-12-29 2017-12-22 武汉华星光电技术有限公司 栅极驱动电路和使用栅极驱动电路的显示器
CN105469766B (zh) * 2016-01-04 2019-04-30 武汉华星光电技术有限公司 Goa电路
CN105489180B (zh) * 2016-01-04 2018-06-01 武汉华星光电技术有限公司 Goa电路
CN106128348B (zh) * 2016-08-24 2018-03-13 武汉华星光电技术有限公司 扫描驱动电路
CN106128392A (zh) * 2016-08-29 2016-11-16 武汉华星光电技术有限公司 Goa驱动电路和嵌入式触控显示面板
CN106128403B (zh) * 2016-09-05 2018-10-23 京东方科技集团股份有限公司 移位寄存器单元、栅极扫描电路

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130127807A1 (en) * 2011-11-18 2013-05-23 Yong-Jae Kim Scan driver and driving method thereof
CN103714792A (zh) * 2013-12-20 2014-04-09 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路及显示装置
CN104282255A (zh) * 2014-09-25 2015-01-14 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路及其驱动方法、显示装置
CN104299583A (zh) * 2014-09-26 2015-01-21 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、驱动电路和显示装置
CN104575430A (zh) * 2015-02-02 2015-04-29 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN104700803A (zh) * 2015-03-26 2015-06-10 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路、显示面板及显示装置
CN104778928A (zh) * 2015-03-26 2015-07-15 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路、显示面板及显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110060645A (zh) * 2019-05-07 2019-07-26 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、栅极驱动电路、显示装置

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