WO2019062265A1 - 移位寄存器单元、栅极驱动电路及驱动方法、显示装置 - Google Patents

移位寄存器单元、栅极驱动电路及驱动方法、显示装置 Download PDF

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Publication number
WO2019062265A1
WO2019062265A1 PCT/CN2018/094849 CN2018094849W WO2019062265A1 WO 2019062265 A1 WO2019062265 A1 WO 2019062265A1 CN 2018094849 W CN2018094849 W CN 2018094849W WO 2019062265 A1 WO2019062265 A1 WO 2019062265A1
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WIPO (PCT)
Prior art keywords
pull
signal
node
voltage
terminal
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PCT/CN2018/094849
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English (en)
French (fr)
Inventor
米磊
李彦辰
薛艳娜
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京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US16/336,274 priority Critical patent/US11315472B2/en
Publication of WO2019062265A1 publication Critical patent/WO2019062265A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • Embodiments of the present disclosure relate to a shift register unit, a gate driving circuit, a driving method thereof, and a display device.
  • a gate switching circuit that integrates a gate driving circuit on an array substrate using GOA technology is also referred to as a GOA circuit or a shift register circuit, and the GOA circuit includes a plurality of cascaded shift register units.
  • the pull-up control structure and the pull-down control structure in each shift register unit in the GOA circuit each include a Thin Film Transistor (TFT). Due to the characteristics of the leakage current of the TFT itself, the GOA circuit often has various defects.
  • TFT Thin Film Transistor
  • At least one embodiment of the present disclosure provides a shift register unit, including: a first input circuit, a second input circuit, an output circuit, and a pull-up node reset circuit; the first input circuit is connected to the first signal end, the first voltage a terminal, a pull-up node, configured to output a voltage of the first voltage terminal to the pull-up node under control of the first signal end; the second input circuit is connected to the second signal end and the second voltage end The pull-up node is configured to output a voltage of the second voltage terminal to the pull-up node under control of the second signal end; the output circuit is connected to a clock signal end, the pull-up node, a signal output end, configured to output a clock signal of the clock signal end to the signal output end under the control of the pull-up node; the pull-up node reset circuit is connected to the third signal end, the third voltage end, The pull-up node is configured to output the voltage of the third voltage terminal to the pull-up node under the control of the third signal end.
  • a shift register unit further includes a signal output reset circuit; the signal output reset circuit is connected to the third signal terminal, the third voltage terminal, and the signal output terminal. And outputting the voltage of the third voltage terminal to the signal output terminal under the control of the third signal terminal.
  • a shift register unit further includes a pull-down control circuit, a pull-down circuit, and a noise reduction circuit;
  • the pull-down control circuit is connected to the third voltage terminal, the fourth voltage terminal, the pull-up node, a pull-down node, configured to control a level of the pull-down node;
  • the pull-down circuit is connected to the pull-down node, the third voltage end, and the signal output end, under the control of the pull-down node, Outputting a voltage of the third voltage terminal to the signal output end;
  • the noise reduction circuit is connected to the pull-down node, the third voltage terminal, and the pull-up node, for controlling under the pull-down node The voltage of the third voltage terminal is output to the pull-up node.
  • the pull-up node reset circuit includes a first transistor; a gate of the first transistor is connected to the third signal terminal, and a first pole is connected to the The third voltage terminal, the second pole is connected to the pull-up node.
  • the signal output reset circuit includes a second transistor; a gate of the second transistor is connected to the third signal end, and a first pole is connected to the The third voltage terminal is connected to the signal output terminal.
  • the first input circuit includes a third transistor; a gate of the third transistor is connected to the first signal end, and a first pole is connected to the first A voltage terminal, the second pole is connected to the pull-up node.
  • the second input circuit includes a fourth transistor; a gate of the fourth transistor is connected to the second signal end, and the first pole is connected to the first The second voltage terminal is connected to the pull-up node.
  • the output circuit includes a fifth transistor and a capacitor; a gate of the fifth transistor is connected to the pull-up node, and a first pole is connected to the clock signal. And a second pole is connected to the signal output end and the second end of the capacitor; a first end of the capacitor is connected to the pull-up node, and a second end is further connected to the signal output end.
  • the pull-down control circuit includes a sixth transistor and a seventh transistor; a gate of the sixth transistor is connected to the fourth voltage terminal, and the first pole is connected.
  • the fourth voltage terminal, the second pole is connected to the pull-down node; the gate of the seventh transistor is connected to the pull-up node, the first pole is connected to the third voltage end, and the second pole is connected to the pull-down node .
  • the pull-down control circuit further includes an eighth transistor and a ninth transistor; a gate of the eighth transistor is connected to the fourth voltage terminal, the first pole Connecting the fourth voltage terminal, the second pole is connected to the gate of the sixth transistor; the gate of the ninth transistor is connected to the pull-up node, and the first pole is connected to the third voltage terminal, the second pole A gate of the sixth transistor is connected.
  • the pull-down circuit includes a tenth transistor; a gate of the tenth transistor is connected to the pull-down node, and a first pole is connected to the third voltage end, A second pole is coupled to the signal output.
  • the noise reduction circuit includes an eleventh transistor; a gate of the eleventh transistor is connected to the pull-down node, and a first pole is connected to the third At the voltage end, the second pole is connected to the pull-up node.
  • At least one embodiment of the present disclosure further provides a gate driving circuit comprising at least two stages of the shift register unit according to any one of the above; the first signal end and the start of the first stage shift register unit The signal terminals are connected; except for the first stage shift register unit, the first signal end of the shift register unit of the current stage is connected to the signal output end of the shift register unit of the previous stage; except for the last stage shift register unit
  • the second signal end of the shift register unit of the current stage is connected to the signal output end of the shift register unit of the next stage; the second signal end of the shift register unit of the last stage is connected to the start signal end .
  • At least one embodiment of the present disclosure also provides a display device comprising the gate driving circuit of any of the above.
  • At least one embodiment of the present disclosure further provides a driving method for driving the shift register unit according to any one of the above, comprising: an input stage: under the control of the first signal end, the first input circuit is to be at the first voltage end The voltage is output to the pull-up node; the output circuit stores the potential of the pull-up node, and under the control of the pull-up node, the output circuit outputs the clock signal of the clock signal end to the signal output end; the output stage: Under the control of the pull-up node, the output circuit outputs a clock signal of the clock signal end to the signal output end, and the signal output end outputs a gate scan signal.
  • the shift register unit further includes a pull-down control circuit, a pull-down circuit, and a noise reduction circuit.
  • the method further includes: a pull-down phase: under the control of the second signal end, a second input circuit outputs a voltage of the second voltage terminal to the pull-up node to control the output circuit to be turned off; under the control of the pull-up node, the pull-down control circuit outputs a voltage of the fourth voltage terminal to the pull-down a node; under the control of the pull-down node, the pull-down circuit outputs a voltage of the third voltage terminal to the signal output end, and the noise reduction circuit outputs the voltage of the third voltage terminal to the pull-up node.
  • the driving method provided by an embodiment of the present disclosure further includes: a reset phase: the pull-up node reset circuit outputs the voltage of the third voltage terminal to the pull-up node under the control of the third signal terminal.
  • At least one embodiment of the present disclosure further provides a driving method for driving the gate driving circuit according to any one of the above, comprising: receiving a first stage shift register unit of a gate driving circuit in a scanning phase of one frame a start signal of the start signal end, stepping on the shift register unit in the gate drive circuit; in a field blanking phase of one frame: under the control of the third signal end, the voltage of the third voltage segment Output to the pull-up node of all cascaded shift register cells to simultaneously reset the pull-up nodes of all cascaded shift register cells.
  • 1 is a waveform diagram of a pull-up node in a gate driving circuit
  • FIG. 2(a) is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 2(b) is a schematic structural diagram of another shift register unit according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic view showing a specific structure of each circuit in FIG. 2(b);
  • FIG. 4 is a schematic diagram showing another specific structure of each circuit in FIG. 2(b);
  • Figure 5 is a signal timing diagram for controlling the shift register unit shown in Figure 3 or 4;
  • FIG. 6 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic block diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 8 is a flowchart of a driving method of a gate driving circuit according to an embodiment of the present disclosure
  • FIG. 9 is a flowchart of a method for driving a shift register unit according to an embodiment of the present disclosure.
  • FIG. 10 is a waveform diagram of a pull-up node in a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 1 is a waveform diagram of a pull-up node in a gate driving circuit.
  • one frame time can be divided into a display phase and a field blanking phase (the time of the field blanking phase is shorter than the time of the display phase), and in the gate driving circuit, the pull-up nodes of each stage of the shift register unit are It is pulled low under the control of the output signal of the shift register unit of the next stage, and the pull-up node of the last stage shift register unit is pulled low under the control of the turn-on signal of the next frame.
  • the pull-up node of the last row of shift register cells remains at a high potential for a much longer time than the pull-up nodes of other row shift register cells, thereby outputting the last row of shift register cells.
  • the operation time of the transistors in the circuit is much longer than that of other row shift register units.
  • the threshold voltage of the transistors in the output circuit of the last row of shift register units drifts in the output circuit of other row shift register units. The threshold voltage drift of the transistor is more severe.
  • Embodiments of the present disclosure provide a shift register unit, a gate driving circuit and a driving method, and a display device, which can improve a problem that a dark line appears on a display screen due to a threshold voltage drift of a transistor.
  • FIG. 2( a ) is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 2( b ) is another embodiment of the present disclosure. Schematic diagram of the structure of the shift register unit.
  • the shift register unit may include a first input circuit 10, a second input circuit 20, an output circuit 30, and a pull-up node reset circuit 40.
  • the first input circuit 10 is connected to the first signal terminal IN1, the first voltage terminal V1, and the pull-up node PU for outputting the voltage of the first voltage terminal V1 to the pull-up node PU under the control of the first signal terminal IN1.
  • the second input circuit 20 is connected to the second signal terminal IN2, the second voltage terminal V2, and the pull-up node PU for outputting the voltage of the second voltage terminal V2 to the pull-up node PU under the control of the second signal terminal IN2.
  • the output circuit 30 is connected to the clock signal terminal CLK, the pull-up node PU, and the signal output terminal OUTPUT for outputting the clock signal of the clock signal terminal CLK to the signal output terminal OUTPUT under the control of the pull-up node PU.
  • the pull-up node reset circuit 40 is connected to the third signal terminal IN3, the third voltage terminal V3, and the pull-up node PU for outputting the voltage of the third voltage terminal V3 to the pull-up node PU under the control of the third signal terminal IN3.
  • the shift register unit provided by the embodiment of the present disclosure increases the pull-up node reset circuit 40, controls the pull-up node reset circuit 40 to be turned on after the signal output end outputs the gate scan signal, and pulls up the node reset circuit 40 to pull up the node output.
  • a low level signal causes output circuit 30 to turn off.
  • the output circuit 30 can be turned off under the control of the pull-up node reset circuit 40 without waiting for the start of the next frame, thereby shortening the operating time of the output circuit 30.
  • the potential of the signal output terminal OUTPUT can be reset by the low level input by the clock signal terminal CLK.
  • the shift register unit further includes a signal output reset circuit 50.
  • the signal output terminal reset circuit 50 is connected to the third signal terminal IN3, the third voltage terminal V3, and the signal output terminal OUTPUT for outputting the voltage of the third voltage terminal V3 to the signal output terminal OUTPUT under the control of the third signal terminal IN3. .
  • the shift register unit further includes a pull-down control circuit 60, a pull-down circuit 70, and a noise reduction circuit 80.
  • the pull-down control circuit 60 is connected to the third voltage terminal V3, the fourth voltage terminal V4, the pull-up node PU, and the pull-down node PD for controlling the level of the pull-down node PD.
  • pull-down control circuit 60 is configured to output the voltage of third voltage terminal V3 to pull-down node PD under control of pull-up node PU; or, in other examples, pull-down control circuit 60
  • the voltage of the fourth voltage terminal V4 is output to the pull-down node PD under the control of the pull-up node PU.
  • the pull-down circuit 70 is connected to the pull-down node PD, the third voltage terminal V3, and the signal output terminal OUTPUT for outputting the voltage of the third voltage terminal V3 to the signal output terminal OUTPUT under the control of the pull-down node PD.
  • the noise reduction circuit 80 is connected to the pull-down node PD, the third voltage terminal V3, and the pull-up node PU for outputting the voltage of the third voltage terminal V3 to the pull-up node PU under the control of the pull-down node PD.
  • the pull-down control circuit 60 can control the potential of the pull-down node PD, so that the pull-down node PD can control the noise reduction circuit 80 to pull down the potential of the pull-up node PU to the potential of the voltage output by the third voltage terminal V3, thereby pulling up the node PU. Perform noise reduction.
  • the signal output by the first signal terminal IN1 and the signal output by the second signal terminal IN2 are inverted, that is, if the signal output by the first signal terminal IN1 is a high level signal, Then, the signal outputted by the second signal terminal IN2 is a low level signal; if the signal outputted by the first signal terminal IN1 is a low level signal, the signal outputted by the second signal terminal IN2 is a high level signal.
  • the first power voltage outputted by the first voltage terminal V1 is a high level signal
  • the second power voltage outputted by the second voltage terminal V2 and the third power voltage output by the third voltage terminal V3 are both The low level signal, or the second voltage terminal V2 and the third voltage terminal V3 are grounded as an example.
  • the first input circuit 10 can output the voltage of the first voltage terminal V1 to the pull-up node PU under the control of the first signal terminal IN1, and further, the second input circuit 20 can be under the control of the second signal terminal IN2.
  • the voltage of the second voltage terminal V2 is output to the pull-up node PU.
  • the shift register unit adopts forward scanning
  • the first power supply voltage outputted by the first voltage terminal V1 is a high level signal
  • the second power supply voltage outputted by the second voltage terminal V2 is a low level signal.
  • the voltage of the first voltage terminal V1 is used to charge the pull-up node PU
  • the voltage of the second voltage terminal V2 is used to reset the pull-up node PU.
  • the first power supply voltage outputted by the first voltage terminal V1 is a low level signal
  • the second power supply voltage outputted by the second voltage terminal V2 is a high level signal
  • the second voltage is The voltage of terminal V2 is used to charge the pull-up node PU
  • the voltage of the first voltage terminal V1 is used to reset the pull-up node PU.
  • the output circuit 30 can output the clock signal of the clock signal terminal CLK to the signal output terminal OUTPUT under the control of the pull-up node PU, so that the signal output terminal OUTPUT is in the output stage.
  • a gate scan signal can be output to the gate line connected to the signal output terminal OUTPUT.
  • the second input circuit 20 outputs the voltage of the second voltage terminal V2 to the pull-up node PU under the control of the second signal terminal IN2 to control the potential of the pull-down node PD through the pull-down control circuit 60, so that the pull-down circuit 70 is at the pull-down node. Under the control of the PD, the potential of the signal output terminal OUTPUT is pulled down to the potential of the third voltage terminal V3.
  • the pull-up node reset circuit 40 can pull down the potential of the pull-up node PU to the potential of the third voltage terminal V3 under the control of the third signal terminal IN3 to control the output circuit 30 to be turned off; the signal output terminal reset circuit 50 The potential of the signal output terminal OUTPUT can also be pulled down to the potential of the third voltage terminal V3 under the control of the third signal terminal IN3.
  • the control pull-up node reset circuit 40 is turned on, and the pull-up node reset circuit 40 pulls up the node PU to output a low-level signal.
  • the output circuit 30 is turned off.
  • the output circuit 30 can be turned off under the control of the pull-up node reset circuit 40 without waiting for the start of the next frame, thereby shortening the output circuit 30 of the last stage shift register unit. operating hours.
  • a low potential can be output to the signal output terminal OUTPUT through the signal output reset circuit 50 before the start of the next frame, so that the shift register unit can be used for noise reduction.
  • the pull-up node reset circuit 40 includes a first transistor M1.
  • the gate of the first transistor M1 is connected to the third signal terminal IN3, the first pole is connected to the third voltage terminal V3, and the second pole is connected to the pull-up node PU.
  • the signal output reset circuit 50 includes a second transistor M2.
  • the gate of the second transistor M2 is connected to the third signal terminal IN3, the first pole is connected to the third voltage terminal V3, and the second pole is connected to the signal output terminal OUTPUT.
  • the first input circuit 10 includes a third transistor M3.
  • the gate of the third transistor M3 is connected to the first signal terminal IN1, the first pole is connected to the first voltage terminal V1, and the second pole is connected to the pull-up node PU.
  • the second input circuit 20 includes a fourth transistor M4.
  • the gate of the fourth transistor M4 is connected to the second signal terminal IN2, the first pole is connected to the second voltage terminal V2, and the second pole is connected to the pull-up node PU.
  • the output circuit 30 includes a fifth transistor M5 and a capacitor C.
  • the gate of the fifth transistor M5 is connected to the pull-up node PU, the first pole is connected to the clock signal terminal CLK, and the second pole is connected to the signal output terminal OUTPUT and the second end of the capacitor C.
  • the first end of the capacitor C is connected to the pull-up node PU, and the second end is also connected to the signal output terminal OUTPUT.
  • pull-down control circuit 60 includes a sixth transistor M6, a seventh transistor M7.
  • the gate of the sixth transistor M6 is connected to the fourth voltage terminal V4, the first pole is connected to the fourth voltage terminal V4, and the second pole is connected to the pull-down node PD.
  • the gate of the seventh transistor M7 is connected to the pull-up node PU, the first pole is connected to the third voltage terminal V3, and the second pole is connected to the pull-down node PD.
  • the pull-down control circuit 60 further includes an eighth transistor M8 and a ninth transistor M9.
  • the gate of the eighth transistor M8 is connected to the fourth voltage terminal V4, the first pole is connected to the fourth voltage terminal V4, and the second pole is connected to the gate of the sixth transistor M6.
  • the gate of the ninth transistor M9 is connected to the pull-up node PU, the first pole is connected to the third voltage terminal V3, and the second pole is connected to the gate of the sixth transistor M6.
  • the pull-down circuit 70 includes a tenth transistor M10.
  • the gate of the tenth transistor M10 is connected to the pull-down node PD, the first pole is connected to the third voltage terminal V3, and the second pole is connected to the signal output terminal OUTPUT.
  • the noise reduction circuit 80 includes an eleventh transistor M11.
  • the gate of the eleventh transistor M11 is connected to the pull-down node PD, the first pole is connected to the third voltage terminal V3, and the second pole is connected to the pull-up node PU.
  • the transistors used in the embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other switching devices having the same characteristics.
  • the source and drain of the transistor used here may be structurally symmetrical, so that the source and the drain may be structurally indistinguishable.
  • one of the first poles and the other pole are directly described, so the first pole of all or part of the transistors in the embodiment of the present disclosure
  • the second pole is interchangeable as needed.
  • the first pole of the transistor may be a source, and the second pole may be a drain.
  • the first pole of the transistor may be a drain and the second pole may be a source.
  • the transistor may be an N-type transistor or a P-type transistor; it may be an enhancement transistor or a depletion transistor; for the sake of clarity, the embodiment of the present disclosure exemplifies the transistor by using an N-type transistor as an example.
  • the disclosed technical solution, however, the transistor of the embodiment of the present disclosure is not limited to the N-type transistor, and those skilled in the art can also implement the function of one or more transistors in the embodiments in the present disclosure by using a P-type transistor according to actual needs.
  • FIG. 3 is a schematic view showing a specific structure of each circuit in FIG. 2(b);
  • FIG. 4 is another schematic structural view of each circuit in FIG. 2(b);
  • FIG. 5 is a control shift shown in FIG. 3 or 4.
  • a signal timing diagram for a register unit Hereinafter, the case of the different stages of the shift register unit shown in FIGS. 3 and 4 will be described in detail in conjunction with the signal timing chart shown in FIG. 5.
  • the first power voltage outputted by the first voltage terminal V1 is a high level signal
  • the signal output from the first signal terminal IN1 is the input signal INPUT and the signal output from the second signal terminal IN2 is the reset signal RESET. It should be noted that in the following description, “1" indicates a high level signal, and “0" indicates a low level signal.
  • the input signal INPUT is a high level signal
  • the reset signal RESET is a low level signal
  • the clock signal CLK outputted by the clock signal terminal CLK is a low level.
  • the signal, the pull-up node reset signal Ctrl outputted by the third signal terminal IN3 is a low-level signal
  • the third transistor M3 is turned on, thereby outputting the first power source voltage of the high level outputted by the first voltage terminal V1 to the pull-up node PU, thereby pulling up the node.
  • the voltage of the PU is a high level signal.
  • the fifth transistor M5 is turned on, thereby outputting the low-level clock signal CLKA of the clock signal terminal CLK to the signal output terminal OUTPUT.
  • the seventh transistor M7 under the control of the high potential of the pull-up node PU, the seventh transistor M7 is turned on, and under the control of the fourth power supply voltage Vd4 of the high level outputted by the fourth voltage terminal V4, the sixth The transistor M6 is turned on, but since the width to length ratio of the channel of the seventh transistor M7 is larger than the width to length ratio of the channel of the sixth transistor M6, the potential of the pull-down node PD is still pulled down to the third voltage terminal V3 through the seventh transistor M7.
  • the third supply voltage In this case, the voltage of the pull-down node PD is a low level signal, so that the tenth transistor M10 and the eleventh transistor M11 are both in an off state.
  • the seventh transistor M7 and the ninth transistor M9 are turned on, and the fourth power supply voltage Vd4 of the high level outputted at the fourth voltage terminal V4 is Under control, the eighth transistor M8 is turned on, but since the width to length ratio of the channel of the ninth transistor M9 is larger than the width to length ratio of the channel of the eighth transistor M8, the gate of the sixth transistor M6 is at a low level, thereby controlling the sixth transistor. M6 is turned off, and the potential of the pull-down node PD is pulled down to the third power supply voltage outputted by the third voltage terminal V3 through the seventh transistor M7. In this case, the voltage of the pull-down node PD is a low level signal, so that the tenth transistor M10 and the eleventh transistor M11 are both in an off state.
  • the third signal terminal IN3 outputs a low level signal such that both the first transistor M1 and the second transistor M2 are turned off; the second signal terminal IN2 outputs a low level signal, so that the fourth transistor M4 is turned off.
  • the signal output terminal OUTPUT outputs a low level in the above input phase P1.
  • the input signal INPUT is a low level signal
  • the reset signal RESET is a low level signal
  • the clock signal CLK outputted by the clock signal terminal CLK is a high level signal
  • the third signal end pull-up node reset signal Ctrl IN3 output a low level signal
  • the third transistor M3 is in an off state. Due to the holding action of the capacitor C, the capacitor C continues to charge the pull-up node PU, thereby keeping the fifth transistor M5 in an on state. In this case, the high-level clock signal CLKA of the output of the clock signal terminal CLK is output to the signal output terminal OUTPUT through the fifth transistor M5. In addition, under the action of the bootstrap of the capacitor C, the potential of the pull-up node PU is further increased (the potential of the end of the capacitor C connected to the signal output terminal OUTPUT is changed from 0 to 1 and the node is pulled up at the capacitor C).
  • the potential of the pull-up node PU is further shifted to a high potential 1) to maintain the fifth transistor M5 in an on state, so that the clock signal CLKA outputted by the clock signal terminal CLK can be used as The gate scan signal is output to a gate line connected to the signal output terminal OUTPUT.
  • the seventh transistor M7 under control of the pull-up node PU high potential, the seventh transistor M7 is turned on, under the control of a high level of the fourth voltage V4 output terminal of the power supply voltage V d4 of the fourth, the sixth transistor 3 M6 is turned on, but since the aspect ratio of the channel of the seventh transistor M7 is larger than the aspect ratio of the channel of the sixth transistor M6, the potential of the pull-down node PD is still pulled down through the seventh transistor M7 to the output of the third voltage terminal V3.
  • the voltage of the pull-down node PD is a low level signal, so that the tenth transistor M10 and the eleventh transistor M11 are both in an off state.
  • the seventh transistor M7 and the ninth transistor M9 are turned on, and the fourth power supply voltage Vd4 of the high level outputted at the fourth voltage terminal V4 is Under control, the eighth transistor M8 is turned on, but since the width to length ratio of the channel of the ninth transistor M9 is larger than the width to length ratio of the channel of the eighth transistor M8, the gate of the sixth transistor M6 is at a low level, so that the sixth transistor M6 As a result, the potential of the pull-down node PD is pulled down to the third power supply voltage outputted by the third voltage terminal V3 through the seventh transistor M7. In this case, the voltage of the pull-down node PD is a low level signal, so that the tenth transistor M10 and the eleventh transistor M11 are both in an off state.
  • the third signal terminal IN3 outputs a low level signal such that both the first transistor M1 and the second transistor M2 are turned off, and the second signal terminal IN2 outputs a low level signal, so that the fourth transistor M4 is turned off.
  • the signal output terminal OUTPUT outputs a high level in the output phase P2 to output a gate scan signal to the gate line connected to the signal output terminal OUTPUT.
  • the input signal INPUT is a low level signal
  • the reset signal RESET is a high level signal
  • the clock signal CLK outputted by the clock signal terminal CLK is a low level signal
  • the third signal end pull-up node reset signal Ctrl IN3 output a low level signal
  • V d4 1.
  • the fourth transistor M4 is turned on, and the potential of the pull-up node PU is pulled down to the second power supply voltage outputted by the second voltage terminal V2, so that the fifth transistor M5 is turned off. status.
  • the seventh transistor M7 is turned off, the sixth transistor M6 under the control of the fourth power source voltage V d4 fourth voltage V4 output terminal 3 is turned on, and The fourth power supply voltage V d4 outputted from the fourth voltage terminal V4 is output to the pull-down node PD, whereby the voltage of the pull-down node PD is a high level signal, and under the control of the high potential of the pull-down node PD, the tenth transistor M10 and the The eleven transistors M11 are both turned on, the potential of the pull-up node PU is pulled down to the third power supply voltage outputted by the third voltage terminal V3 through the eleventh transistor M11, and the potential of the signal output terminal OUTPUT is pulled down through the tenth transistor M10.
  • the seventh transistor M7 and the ninth transistor M9 are turned off, the fourth power supply voltage V d4 eighth transistor M8 in the fourth terminal voltage V4 outputted Controlling the conduction, and outputting the fourth power voltage V d4 outputted by the fourth voltage terminal V4 to the gate of the sixth transistor M6, controlling the sixth transistor M6 to be turned on, and the sixth transistor M6 outputting the fourth voltage terminal V4.
  • the fourth power supply voltage V d4 is output to the pull-down node PD, whereby the voltage of the pull-down node PD is a high level signal, and under the control of the high potential of the pull-down node PD, the tenth transistor M10 and the eleventh transistor M11 are both turned on.
  • the potential of the pull-up node PU is pulled down to the third power supply voltage outputted by the third voltage terminal V3 through the eleventh transistor M11, and the potential of the signal output terminal OUTPUT is pulled down to the third voltage terminal V3 through the tenth transistor M10.
  • the first signal terminal IN1 outputs a low level signal, so that the third transistor M3 is turned off; the third signal terminal IN3 outputs a low level signal, so that the first transistor M1 and the second transistor M2 are both turned off.
  • the input signal INPUT is a low level signal
  • the reset signal RESET is a low level signal
  • the pull-up node reset signal Ctrl outputted by the third signal terminal IN3 is a high level signal.
  • the third signal terminal IN3 outputs a high level signal, so that the first transistor M1 and the second transistor M2 are both turned on, and the first transistor M1 outputs the third power voltage outputted by the third voltage terminal V3 to the pull-up node PU, The pull-up node PU is reset.
  • the voltage of the pull-up node PU is a low level signal, and the fifth transistor M5 is turned off.
  • the second transistor M2 outputs the third power voltage outputted by the third voltage terminal V3 to The signal output terminal OUTPUT is used to reset the signal output terminal OUTPUT.
  • the third signal terminal IN3 may output a high level signal for the entire reset phase P4, or may output a high level signal for each of the start and/or end of the reset phase P4.
  • the operation of the shift register unit described above is an example in which the gate drive circuit formed by cascading the plurality of shift register units is forward-scanned as an example.
  • the first signal terminal IN1 outputs a reset signal RESET
  • the second signal terminal IN2 outputs an input signal INPUT.
  • the first voltage terminal V1 outputs a low level signal
  • the second voltage terminal V2 outputs a high level signal.
  • FIG. 6 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • the gate driving circuit includes a plurality of cascaded shift register units (RS1, RS2, ..., RSn) as described in any of the above.
  • the first signal terminal IN1 of the first stage shift register unit RS1 is connected to the start signal terminal STV, and the first signal of the shift register unit RS(n-1) of the present stage is other than the first stage shift register unit RS1.
  • the terminal IN1 is connected to the signal output terminal OUTPUT of the shift register unit RS(n-2) of the previous stage.
  • the start signal terminal STV is used to output a start signal, and the first stage shift register unit RS1 of the gate drive circuit starts to scan the gate lines (G1, G2, ..., Gn) line by line after receiving the above start signal. .
  • the second signal terminal IN2 of the shift register unit RS(n-1) of the present stage is connected to the signal output terminal OUTPUT of the shift register unit RSn of the next stage, and the last stage.
  • the second signal terminal IN2 of the shift register unit RSn is connected to the above-mentioned start signal terminal STV.
  • the start signal of the start signal terminal STV is input to the first signal terminal IN1 of the first stage shift register unit RS1
  • the second signal terminal IN2 of the last stage shift register unit RSn may start from the start signal terminal STV.
  • the start signal is used as a reset signal to reset the signal output terminal OUTPUT of the last stage shift register unit RSn.
  • the first voltage terminal V1 of each stage of the shift register unit is connected to the high level VDD
  • the second voltage terminal V2 is connected to the low level VSS
  • the third voltage terminal V3 is connected to the low level VGL.
  • the gate driving circuit provides a first clock signal CLKA and a second clock signal CLKB, and the first clock signal CLKA is applied to the clock signal terminal CLK of the 2N-1th stage shift register unit;
  • the clock signal CLKB is applied to the clock signal terminal CLK of the 2Nth stage shift register unit;
  • N is a positive integer, and N is greater than or equal to 1.
  • the gate driving circuit shown in FIG. 6 is a method of connecting respective control signals when the gate lines are forward-scanned.
  • the second signal terminal IN2 of the first stage shift register unit RS1 is connected to the start signal terminal STV, except for the first stage shift register unit RS1.
  • the second signal terminal IN2 of the shift register unit RS(n-1) is connected to the signal output terminal OUTPUT of the shift register unit RS(n-2) of the previous stage, and the shift register unit RS(n-1) of the previous stage
  • the signal output terminal OUTPUT is connected to the second signal terminal IN2 of the next stage shift register unit RS(n).
  • the first signal terminal IN1 of the shift register unit RS(n-1) of the present stage is connected to the signal output terminal OUTPUT of the shift register unit RSn of the previous stage, except for the last stage shift register unit RSn.
  • the first signal terminal IN1 of the last stage shift register unit RSn is connected to the above-mentioned start signal terminal STV.
  • the first voltage terminal V1 of each stage shift register unit is connected to the low level VSS
  • the second voltage terminal V2 is connected to the high level VDD
  • the third voltage terminal V3 is connected to the low level VGL.
  • each shift register unit in the gate driving circuit is connected to the same third signal terminal IN3, and when the third signal terminal IN3 outputs a high level signal, all shift register units in the gate driving circuit A reset of the signal output terminal OUTPUT and the pull-up node PU is implemented.
  • the pull-up node reset circuit may be only disposed in the last-stage shift register unit of the gate driving circuit; or the pull-up may be set in all the shift register units of the gate driving circuit.
  • the node reset circuit is not limited in this disclosure.
  • FIG. 7 is a schematic block diagram of a display device according to an embodiment of the present disclosure.
  • the display device 100 includes any of the gate driving circuits 50 as described above, which has the same advantageous effects as the gate driving circuit provided in the foregoing embodiments. Since the foregoing embodiment has been described in detail for the structure and advantageous effects of the gate driving circuit, details are not described herein again.
  • FIG. 8 is a flowchart of a driving method of the gate driving circuit according to an embodiment of the present disclosure.
  • the driving method includes:
  • the first stage shift register unit of the gate driving circuit receives the start signal of the start signal end, and turns on the shift register unit in the gate driving circuit step by step.
  • the pull-down of the pull-up node PU potential of each shift register unit is the signal of the third input terminal 20 under the control of the second signal terminal IN2 to the third voltage terminal V3.
  • the signal of the third voltage terminal V3 is input to the pull-up node PU under the control of the three signal terminals IN3.
  • FIG. 9 is a flowchart of a method for driving a shift register unit according to an embodiment of the present disclosure.
  • the driving method includes:
  • the output circuit In the output stage, under the control of the pull-up node, the output circuit outputs a clock signal of the clock signal end to the signal output end, and the signal output end outputs a gate scan signal.
  • step S10 in the input phase P1:
  • the first input circuit 10 Under the control of the first signal terminal IN1, the first input circuit 10 outputs the first power supply voltage of the first voltage terminal V1 to the pull-up node PU. Under the control of the pull-up node PU, the output circuit 30 outputs a clock signal (low level signal) of the clock signal terminal CLK to the signal output terminal OUTPUT.
  • each circuit in the above shift register unit is as shown in FIG. 3 or FIG. 4, and the transistors in the respective circuits are all N-type transistors, as shown in FIG. 5, in the input phase P1, the clock signal
  • the clock signal CLKA outputted by the terminal CLK is a low level signal
  • the first signal terminal IN1 outputs a high level signal
  • the second signal terminal IN2 outputs a low level signal
  • the third signal terminal IN3 outputs a low level signal
  • the fourth signal terminal outputs a low level signal
  • the fourth voltage terminal V4 outputs a high voltage
  • the voltage of the pull-up node PU is high.
  • the signal output terminal OUTPUT outputs a low level signal.
  • the first signal terminal IN1 outputs a high-level signal, so that the first input circuit 10 outputs the first power supply voltage (high-level signal) of the first voltage terminal V1 under the control of the high level of the first signal terminal IN1.
  • the third transistor M3 is turned on, thereby outputting the first power voltage outputted by the first voltage terminal V1 to the pull-up node PU, thereby pulling up the node PU.
  • the voltage is a high level signal.
  • the fifth transistor M5 is turned on, and the low-level clock signal CLKA of the clock signal terminal CLK is output to the signal output terminal OUTPUT.
  • the third signal terminal IN3 outputs a low level signal such that both the first transistor M1 and the second transistor M2 are turned off, and the second signal terminal IN2 outputs a low level signal, so that the fourth transistor M4 is turned off.
  • step S20 in the output phase P2, under the control of the pull-up node PU, the output circuit 30 outputs the clock signal CLKA (high level signal) of the clock signal terminal CLK to the signal output terminal.
  • the signal output terminal OUTPUT outputs the gate scan signal.
  • each circuit in the above shift register unit is as shown in FIG. 3 or FIG. 4, and the transistors in each circuit are N-type transistors, as shown in FIG. 5, in the output stage P2, the clock signal terminal CLK
  • the output clock signal CLKA is a high level signal
  • the first signal terminal IN1 outputs a low level signal
  • the second signal terminal IN2 outputs a low level signal
  • the third signal terminal IN3 outputs a low level signal
  • the fourth signal terminal IN3 outputs a low level signal
  • the fourth signal terminal V4 outputs The high level signal
  • the voltage of the pull-up node PU is high level, at this time, the signal output terminal OUTPUT outputs a high level signal.
  • the output circuit 30 outputs the clock signal CLKA output from the clock signal terminal CLK to the signal output terminal OUTPUT.
  • the third transistor M3 is in an off state.
  • Capacitor C will continue to charge the pull-up node PU such that the fifth transistor M5 remains on.
  • the high-level clock signal CLKA output from the clock signal terminal CLK is output to the signal output terminal OUTPUT through the fifth transistor M5.
  • the potential of the pull-up node PU is further increased to maintain the fifth transistor M5 in an on state, so that the clock signal CLKA outputted by the clock signal terminal CLK can be used as a gate.
  • the pole scan signal is output to a gate line connected to the signal output terminal OUTPUT.
  • the third signal terminal IN3 outputs a low level signal such that both the first transistor M1 and the second transistor M2 are turned off, and the second signal terminal IN2 outputs a low level signal, so that the fourth transistor M4 is turned off.
  • the shift register unit further includes a signal output reset circuit 50, a pull-down control circuit 60, a pull-down circuit 70, and a noise reduction circuit 80, as shown in FIG. 5, in the input phase P1, at the Under the control of a signal terminal IN1, the first input circuit 10 outputs the first power supply voltage of the first voltage terminal V1 to the pull-up node PU. Under the control of the pull-up node PU, the output circuit 30 outputs the clock signal CLKA (low level signal) of the clock signal terminal CLK to the signal output terminal OUTPUT.
  • CLKA low level signal
  • the pull-down control circuit 60 pulls down the potential of the pull-down node PD to the third power supply voltage outputted by the third voltage terminal V3 under the control of the pull-up node PU high potential.
  • the second input circuit 20, the pull-down circuit 70, the noise reduction circuit 80, and the pull-up node reset circuit 40 are not turned on.
  • each circuit in the above shift register unit is as shown in FIG. 3 or FIG. 4, and the transistors in each circuit are N-type transistors, as shown in FIG. 5, in the input phase P1, the clock signal terminal CLK Output low-level signal (CLKA), the first signal terminal IN1 outputs a high-level signal, the second signal terminal IN2 outputs a low-level signal, the third signal terminal IN3 outputs a low-level signal, and the fourth signal terminal IN3 outputs a low-level signal, and the fourth voltage terminal V4 outputs a high-voltage signal.
  • the voltage of the pull-up node PU is a high level
  • the voltage of the pull-down node PD is a low level.
  • the signal output terminal OUTPUT outputs a low level signal.
  • the first signal terminal IN1 outputs a high level signal
  • the first input circuit 10 outputs the high level of the first voltage terminal V1 to the pull-up node PU under the control of the high level of the first signal terminal IN1.
  • the third transistor M3 is turned on, thereby outputting the first power voltage outputted by the first voltage terminal V1 to the pull-up node PU, thereby pulling up the node.
  • the voltage of the PU is a high level signal.
  • the fifth transistor M5 is turned on, and the low-level clock signal CLKA of the clock signal terminal CLK is output to the signal output terminal OUTPUT.
  • the seventh transistor M7 under the control of the high potential of the pull-up node PU, the seventh transistor M7 is turned on, and under the control of the high-level fourth power supply voltage outputted by the fourth voltage terminal V4, the sixth transistor M6 is turned on.
  • the aspect ratio of the channel of the seventh transistor M7 is greater than the aspect ratio of the channel of the sixth transistor M6, the potential of the pull-down node PD is still pulled down through the seventh transistor M7 to the third power output of the third voltage terminal V3.
  • the voltage of the pull-down node PD is a low level signal, so that the tenth transistor M10 and the eleventh transistor M11 are both in an off state.
  • the seventh transistor M7 and the ninth transistor M9 are turned on, under the control of the fourth power supply voltage of the high level outputted by the fourth voltage terminal V4.
  • the eighth transistor M8 is turned on, but since the width to length ratio of the channel of the ninth transistor M9 is larger than the width to length ratio of the channel of the eighth transistor M8, the gate of the sixth transistor M6 is at a low level, so that the sixth transistor M6 is turned off.
  • the potential of the pull-down node PD is pulled down to the third power supply voltage outputted by the third voltage terminal V3 through the seventh transistor M7. In this case, the voltage of the pull-down node PD is a low level signal, so that the tenth transistor M10 and the eleventh transistor M11 are both in an off state.
  • the third signal terminal IN3 outputs a low level signal such that both the first transistor M1 and the second transistor M2 are turned off, and the second signal terminal IN2 outputs a low level signal, so that the fourth transistor M4 is turned off.
  • the output circuit 30 outputs the clock signal CLKA (high level signal) of the clock signal terminal CLK to the signal output terminal OUTPUT, and the signal output terminal OUTPUT outputs the gate scan signal.
  • the pull-down control circuit 60 pulls down the potential of the pull-down node PD to the third power supply voltage outputted by the third voltage terminal V3 under the control of the pull-up node PU high potential.
  • the first input circuit 10, the second input circuit 20, the noise reduction circuit 80, the pull-down circuit 70, and the pull-up node reset circuit 40 are not turned on.
  • each circuit in the above shift register unit is as shown in FIG. 3 or FIG. 4, and the transistors in each circuit are N-type transistors, as shown in FIG. 5, in the output stage P2, the clock signal terminal CLK Output high level signal (CLKA), the first signal terminal IN1 outputs a low level signal, the second signal terminal IN2 outputs a low level signal, the third signal terminal IN3 outputs a low level signal, and the fourth signal terminal IN3 outputs a low level signal, and the fourth signal terminal V4 outputs a low voltage signal, and the fourth voltage terminal V4 outputs a high voltage signal.
  • the voltage of the pull-up node PU is high, and the voltage of the pull-down node PD is low.
  • the signal output terminal OUTPUT outputs a high level signal.
  • the output circuit 30 outputs the clock signal CLKA (high level signal) output from the clock signal terminal CLK to the signal output terminal OUTPUT.
  • CLKA high level signal
  • the third transistor M3 is in an off state.
  • Capacitor C charges the pull-up node PU such that the fifth transistor M5 remains on.
  • the clock signal CLKA output from the clock signal terminal CLK is output to the signal output terminal OUTPUT through the fifth transistor M5.
  • the potential of the pull-up node PU is further increased to maintain the fifth transistor M5 in an on state, so that the clock signal CLKA outputted by the clock signal terminal CLK can be used as a gate.
  • the pole scan signal is output to a gate line connected to the signal output terminal OUTPUT.
  • the seventh transistor M7 under the control of the high potential of the pull-up node PU, the seventh transistor M7 is turned on, and under the control of the high-level fourth power supply voltage outputted by the fourth voltage terminal V4, the sixth transistor M6 is guided.
  • the aspect ratio of the channel of the seventh transistor M7 is greater than the aspect ratio of the channel of the sixth transistor M6, the potential of the pull-down node PD is still pulled down through the seventh transistor M7 to the third output of the third voltage terminal V3. voltage.
  • the voltage of the pull-down node PD is a low level signal, so that the tenth transistor M10 and the eleventh transistor M11 are both in an off state.
  • the seventh transistor M7 and the ninth transistor M9 are turned on, under the control of the fourth power supply voltage of the high level outputted by the fourth voltage terminal V4.
  • the eighth transistor M8 is turned on, but since the width to length ratio of the channel of the ninth transistor M9 is larger than the width to length ratio of the channel of the eighth transistor M8, the gate of the sixth transistor M6 is at a low level, so that the sixth transistor M6 is turned off.
  • the potential of the pull-down node PD is pulled down to the third power supply voltage outputted by the third voltage terminal V3 through the seventh transistor M7. In this case, the voltage of the pull-down node PD is a low level signal, so that the tenth transistor M10 and the eleventh transistor M11 are both in an off state.
  • the third signal terminal IN3 outputs a low level signal such that both the first transistor M1 and the second transistor M2 are turned off, and the second signal terminal IN2 outputs a low level signal, so that the fourth transistor M4 is turned off.
  • the driving method further includes: a pull-down phase, under the control of the second signal terminal, the second input circuit outputs the voltage of the second voltage terminal to the pull-up node to control the output circuit to be turned off; at the pull-up node Under control, the pull-down control circuit outputs the voltage of the fourth voltage terminal to the pull-down node; under the control of the pull-down node, the pull-down circuit outputs the voltage of the third voltage terminal to the signal output end, and the noise reduction circuit outputs the voltage of the third voltage terminal Pull up the node.
  • the second input circuit 20 outputs the second power voltage of the second voltage terminal V2 to the pull-up node PU to control the output circuit 30.
  • the pull-down control circuit 60 outputs the fourth power supply voltage (high-level signal) outputted by the fourth voltage terminal V4 to the pull-down node PD;
  • the pull-down circuit 70 The third power supply voltage of the third voltage terminal V3 is output to the signal output terminal OUTPUT, and at the same time, the noise reduction circuit 80 outputs the third power supply voltage of the third voltage terminal V3 to the pull-up node PU.
  • the first input circuit 10 the second input circuit 20, and the pull-up node reset circuit 40 are not turned on.
  • each circuit in the above shift register unit is as shown in FIG. 3 or FIG. 4, and the transistors in each circuit are N-type transistors, as shown in FIG. 5, in the pull-down phase P3, the clock signal terminal CLK
  • the output clock signal CLKA is a low level signal
  • the first signal terminal IN1 outputs a low level signal
  • the second signal terminal IN2 outputs a high level signal
  • the voltage of the pull-up node PU is a low level signal
  • the voltage of the pull-down node PD It is high level.
  • the signal output terminal OUTPUT outputs a low level signal.
  • the pull-down control circuit 60 outputs the fourth power supply voltage (high level) of the fourth voltage terminal V4 to the pull-down node PD, and under the control of the pull-down node PD, the pull-down circuit 70 sets the third power supply voltage of the third voltage terminal V3. (Low level) is output to the signal output terminal OUTPUT, and the noise reduction circuit 80 outputs the third power source voltage (low level) of the third voltage terminal V3 to the pull-up node PU.
  • the fourth transistor M4 is turned on, thereby pulling down the potential of the pull-up node PU to the second power supply voltage of the second voltage terminal V2 (low level) ), whereby the fifth transistor M5 is in an off state.
  • the seventh transistor M7 is turned off, and the sixth transistor M6 is turned on under the control of the fourth power supply voltage outputted by the fourth voltage terminal V4, and will be turned
  • the fourth power supply voltage outputted by the four voltage terminals V4 is output to the pull-down node PD, whereby the voltage of the pull-down node PD is a high level signal, and under the control of the high potential of the pull-down node PD, the tenth transistor M10 and the eleventh transistor M11 Turning on, the potential of the pull-up node PU is pulled down to the third power supply voltage (low level) outputted by the third voltage terminal V3 through the eleventh transistor M11, and the potential of the signal output terminal OUTPUT is pulled down through the tenth transistor M10.
  • the seventh transistor M7 and the ninth transistor M9 are both turned off, and the fourth power supply voltage of the eighth transistor M8 is outputted at the fourth voltage terminal V4 (high power).
  • the control is turned on, and the fourth power supply voltage outputted from the fourth voltage terminal V4 is output to the gate of the sixth transistor M6, the sixth transistor M6 is controlled to be turned on, and the sixth transistor M6 outputs the fourth voltage terminal V4.
  • the fourth power supply voltage is output to the pull-down node PD, whereby the voltage of the pull-down node PD is a high level signal, and under the control of the high potential of the pull-down node PD, the tenth transistor M10 and the eleventh transistor M11 are both turned on, The eleventh transistor M11 pulls down the potential of the pull-up node PU to the third power supply voltage (low level) outputted by the third voltage terminal V3, and pulls the potential of the signal output terminal OUTPUT to the third voltage terminal through the tenth transistor M10.
  • the third supply voltage of the V3 output is output to the pull-down node PD, whereby the voltage of the pull-down node PD is a high level signal, and under the control of the high potential of the pull-down node PD, the tenth transistor M10 and the eleventh transistor M11 are both turned on, The eleventh transistor M11 pulls down the potential of the pull-up node PU to the third power supply voltage (low level) outputted by the
  • the first signal terminal IN1 outputs a low level signal such that the third transistor M3 is turned off; the third signal terminal IN3 outputs a low level signal such that both the first transistor M1 and the second transistor M2 are turned off.
  • the driving method further includes: in the reset phase, under the control of the third signal terminal, the pull-up node reset circuit outputs the voltage of the third voltage terminal to the pull-up node.
  • the pull-up node reset circuit 40 outputs the voltage of the third voltage terminal V3 to the pull-up node PU to perform the pull-up node PU.
  • Reset thereby controlling the output circuit 30 to be turned off; the signal output reset circuit 50 outputs the voltage of the third voltage terminal V3 to the signal output terminal OUTPUT, and resets the signal output terminal OUTPUT.
  • the first input circuit 10 the second input circuit 20, the pull-down control circuit 60, the pull-down circuit 70, and the noise reduction circuit 80 are not turned on.
  • each circuit in the above shift register unit is as shown in FIG. 3 or FIG. 4, and the transistors in each circuit are N-type transistors, as shown in FIG. 5, in the reset phase P4, the first signal end IN1 outputs a low level signal, the second signal terminal IN2 outputs a low level signal, the third signal terminal IN3 outputs a high level signal, and the fourth voltage terminal V4 outputs a low level signal; the pull-up node PU voltage is a low level Signal, the voltage of the pull-down node PD is a low level signal. At this time, the signal output terminal OUTPUT outputs a low level signal.
  • the pull-up node reset circuit 40 pulls down the voltage of the pull-up node PU to the third power supply voltage of the third voltage terminal V3, so that the output circuit 30 is turned off, and the clock signal terminal CLK A high level signal cannot be output.
  • the third signal terminal IN3 outputs a high level signal, so that the first transistor M1 is turned on, and the first transistor M1 inputs the third power voltage of the third voltage terminal V3 to the pull-up node PU to The pull node PU performs resetting.
  • the fifth transistor M5 is turned off under the control of the pull-up node PU; the third signal terminal IN3 outputs a high level signal, so that the second transistor M2 is turned on, and the second transistor M2 turns on the third voltage.
  • the third power supply voltage of the terminal V3 is input to the signal output terminal OUTPUT to reset the signal output terminal OUTPUT.
  • the remaining transistors are in an off state.
  • the second signal terminal IN2 can output high until the next frame starts.
  • the level signal that is, the last stage shift register unit, in the above four stages, after the input stage P1 and the output stage P2 are executed, the reset stage P4 is performed first, and then the pull-down stage P3 is performed;
  • the other stage shift register units are sequentially executed from the input phase P1 to the reset phase P4. Therefore, the waveform diagram of the PU point potential of the pull-up node is as shown in FIG. 10, and the pull-up node of the last stage shift register unit does not need to wait until the next frame scan starts to be pulled low, but resets after the end of the frame scan. Phase P4 is pulled down directly.

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Abstract

一种移位寄存器单元、栅极驱动电路及驱动方法、显示装置。移位寄存器单元包括第一输入电路(10)，用于在第一信号端(IN1)的控制下，将第一电压端(V1)的电压输出至上拉节点(PU)；第二输入电路(20)，用于在第二信号端(IN2)的控制下，将第二电压端(V2)的电压输出至上拉节点(PU)；输出电路(30)，用于在上拉节点(PU)的控制下，将时钟信号端(CLK)的时钟信号输出至信号输出端(OUTPUT)；上拉节点复位电路(40)，用于在第三信号端(IN3)的控制下，将第三电压端(V3)的电压输出至上拉节点(PU)。

Description

移位寄存器单元、栅极驱动电路及驱动方法、显示装置
本申请要求于2017年09月29日递交的中国专利申请第201710910077.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种移位寄存器单元、栅极驱动电路及其驱动方法、显示装置。
背景技术
近年来，显示器的发展呈现出高集成度、低成本的发展趋势。GOA(Gate Driver on Array，集成栅极驱动电路)技术量产化的实现非常重要。利用GOA技术将栅极驱动电路集成在显示面板的阵列基板上，从而可以从材料成本和制作工艺两方面降低产品成本。利用GOA技术将栅极驱动电路集成在阵列基板上的栅极开关电路也称为GOA电路或移位寄存器电路，该GOA电路包括多个级联的移位寄存器单元。目前，GOA电路中的每个移位寄存器单元中的上拉控制结构和下拉控制结构均包括薄膜晶体管(Thin Film Transistor，TFT)。由于TFT自身存在漏电电流的特性，GOA电路常常会出现多种不良。
发明内容
本公开至少一实施例提供一种移位寄存器单元，包括：第一输入电路、第二输入电路、输出电路和上拉节点复位电路；所述第一输入电路连接第一信号端、第一电压端、上拉节点，用于在所述第一信号端的控制下，将所述第一电压端的电压输出至所述上拉节点；所述第二输入电路连接第二信号端、第二电压端、所述上拉节点，用于在所述第二信号端的控制下，将所述第二电压端的电压输出至所述上拉节点；所述输出电路连接时钟信号端、所述上拉节点、信号输出端，用于在所述上拉节点的控制下，将所述时钟信号端的时钟信号输出至所述信号输出端；所述上拉节点复位电路连接第三信号端、第三电压端、所述上拉节点，用于在所述第三信号端的控制下，将所述第三电压端的电压输出至所述上拉节点。
例如，本公开一实施例提供的移位寄存器单元还包括信号输出端复位电路；所述信号输出端复位电路连接所述第三信号端、所述第三电压端、所述信号输出端，用于在所述第三信号端的控制下，将所述第三电压端的电压输出至所述信号输出端。
例如，本公开一实施例提供的移位寄存器单元还包括下拉控制电路、下拉电路、降噪电路；所述下拉控制电路连接所述第三电压端、第四电压端、所述上拉节点、下拉节点，用于对所述下拉节点的电平进行控制；所述下拉电路连接所述下拉节点、所述第三电压端、所述信号输出端，用于在所述下拉节点的控制下，将所述第三电压端的电压输出至所述信号输出端；所述降噪电路连接所述下拉节点、所述第三电压端、所述上拉节点，用于在所述下拉节点的控制下将所述第三电压端的电压输出至所述上拉节点。
例如，在本公开一实施例提供的移位寄存器单元中，所述上拉节点复位电路包括第一晶体管；所述第一晶体管的栅极连接所述第三信号端，第一极连接所述第三电压端，第二极连接所述上拉节点。
例如，在本公开一实施例提供的移位寄存器单元中，所述信号输出端复位电路包括第二晶体管；所述第二晶体管的栅极连接所述第三信号端，第一极连接所述第三电压端，第二极连接所述信号输出端。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一输入电路包括第三晶体管；所述第三晶体管的栅极连接所述第一信号端，第一极连接所述第一电压端，第二极连接所述上拉节点。
例如，在本公开一实施例提供的移位寄存器单元中，所述第二输入电路包括第四晶体管；所述第四晶体管的栅极连接所述第二信号端，第一极连接所述第二电压端，第二极连接所述上拉节点。
例如，在本公开一实施例提供的移位寄存器单元中，所述输出电路包括第五晶体管和电容；所述第五晶体管的栅极连接所述上拉节点，第一极连接所述时钟信号端，第二极连接所述信号输出端和所述电容的第二端；所述电容的第一端连接所述上拉节点，第二端还连接所述信号输出端。
例如，在本公开一实施例提供的移位寄存器单元中，所述下拉控制电路包括第六晶体管、第七晶体管；所述第六晶体管的栅极连接所述第四电压端，第一极连接所述第四电压端，第二极连接所述下拉节点；所述第七晶体管的栅极连接所述上拉节点，第一极连接所述第三电压端，第二极连接所述下拉节点。
例如，在本公开一实施例提供的移位寄存器单元中，所述下拉控制电路还包括第八晶体管、第九晶体管；所述第八晶体管的栅极连接所述第四电压端，第一极连接所述第四电压端，第二极连接所述第六晶体管的栅极；所述第九晶体管的栅极连接所述上拉节点，第一极连接所述第三电压端，第二极连接所述第六晶体管的栅极。
例如，在本公开一实施例提供的移位寄存器单元中，所述下拉电路包括第十晶体管；所述第十晶体管的栅极连接所述下拉节点，第一极连接所述第三电压端，第二极连接所述信号输出端。
例如，在本公开一实施例提供的移位寄存器单元中，所述降噪电路包括第十一晶体管；所述第十一晶体管的栅极连接所述下拉节点，第一极连接所述第三电压端，第二极连接所述上拉节点。
本公开至少一实施例还提供一种栅极驱动电路，包括至少两级级联的如上述任一项所述的移位寄存器单元；第一级移位寄存器单元的第一信号端与起始信号端相连接；除了所述第一级移位寄存器单元以外，本级移位寄存器单元的第一信号端与上一级移位寄存器单元的信号输出端连接；除了最后一级移位寄存器单元以外，所述本级移位寄存器单元的第二信号端与下一级移位寄存器单元的信号输出端连接；所述最后一级移位寄存器单元的第二信号端连接所述起始信号端。
本公开至少一实施例还提供一种显示装置，包括上述任一项所述的栅极驱动电路。
本公开至少一实施例还提供一种用于驱动上述任一项所述的移位寄存器单元的驱动方法，包括：输入阶段：在第一信号端的控制下，第一输入电路将第一电压端的电压输出至上拉节点；输出电路将所述上拉节点的电位进行存储，并在所述上拉节点的控制下，所述输出电路将时钟信号端的时钟信号输出至信号输出端；输出阶段：在所述上拉节点的控制下，所述输出电路将所述时钟信号端的时钟信号输出至所述信号输出端，所述信号输出端输出栅极扫描信号。
例如，在本公开一实施例提供的驱动方法中，所述移位寄存器单元还包括下拉控制电路、下拉电路、降噪电路；所述方法还包括：下拉阶段：在第二信号端的控制下，第二输入电路将第二电压端的电压输出至所述上拉节点，以控制所述输出电路关闭；在所述上拉节点的控制下，所述下拉控制电路将第四电 压端的电压输出至下拉节点；在所述下拉节点的控制下，所述下拉电路将第三电压端的电压输出至信号输出端，所述降噪电路将所述第三电压端的电压输出至所述上拉节点。
例如，本公开一实施例提供的驱动方法还包括：复位阶段：在所述第三信号端的控制下，所述上拉节点复位电路将所述第三电压端的电压输出至所述上拉节点。
本公开至少一实施例还提供一种用于驱动上述任一项所述的栅极驱动电路的驱动方法，包括：在一帧的扫描阶段：栅极驱动电路的第一级移位寄存器单元接收起始信号端的起始信号，逐级开启栅极驱动电路中的移位寄存器单元；在一帧的场消隐阶段：在所述第三信号端的控制下，将所述第三电压段的电压输出至所有级联的移位寄存器单元的上拉结点，以同时复位所有级联的移位寄存器单元的上拉节点。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，并非对本公开的限制。
图1为一种栅极驱动电路中的上拉节点的波形示意图；
图2(a)为本公开一实施例提供的一种移位寄存器单元的结构示意图；
图2(b)为本公开实施例提供的另一种移位寄存器单元的结构示意图；
图3为图2(b)中各个电路的一种具体结构示意图；
图4为图2(b)中各个电路的另一种具体结构示意图；
图5为控制图3或4所示的移位寄存器单元的一种信号时序图；
图6为本公开实施例提供的一种栅极驱动电路的结构示意图；
图7为本公开一实施例提供的一种显示装置的示意框图；
图8为本公开一实施例提供的一种栅极驱动电路的驱动方法的流程图；
图9为本公开一实施例提供的一种移位寄存器单元的驱动方法的流程图；
图10为本公开一实施例提供的一种栅极驱动电路中的上拉节点的波形图。
附图标记：
10-第一输入电路；20-第二输入电路；30-输出电路；40-上拉节点复位电路；50-信号输出端复位电路；60-下拉控制电路；70-下拉电路；80-降噪电路； IN1-第一信号端；IN2-第二信号端；IN3-第三信号端；CLK-时钟信号端；OUTPUT-信号输出端；V1-第一电压端；V2-第二电压端；V3-第三电压端；V4-第四电压端；PU-上拉节点；PD-下拉节点；C-电容。
具体实施方式
为了使得本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1为一种栅极驱动电路中的上拉节点的波形示意图。例如，一帧时间可以被分为显示阶段和场消隐阶段(场消隐阶段的时间比显示阶段的时间短)，在栅极驱动电路中，每一级移位寄存器单元的上拉节点均是在下一级移位寄存器单元的输出信号的控制下被拉低，而最后一级移位寄存器单元的上拉节点则在下一帧的开启信号的控制下被拉低。如图1所示的上拉节点的波形示意图，最后一行移位寄存器单元的上拉节点保持高电位的时间远大于其他行移位寄存器单元的上拉节点，从而最后一行移位寄存器单元的输出电路中的晶体管的工作时长远大于其他行移位寄存器单元，随着工作时间的增加，最后一行移位寄存器单元的输出电路中的晶体管的阈值电压漂移比其他行移位寄存器单元的输出电路中的晶体管的阈值电压漂移更严重。当反向扫描时，最后一行移位寄存器单元作为第一行，由于阈值电压漂移严重，导致该行移位寄存器单元的输出电压会低于正常的栅极驱动信号的电压，因此会在显示屏上出现一行由于 显示亮度较暗形成的暗线，最终用户会在显示屏上看到多条暗线，影响显示效果。
本公开的实施例提供一种移位寄存器单元、栅极驱动电路及驱动方法、显示装置，可改善因晶体管的阈值电压漂移导致显示屏上出现暗线的问题。
本公开实施例提供一种移位寄存器单元，图2(a)为本公开一实施例提供的一种移位寄存器单元的结构示意图；图2(b)为本公开实施例提供的另一种移位寄存器单元的结构示意图。例如，如图2(a)所示，移位寄存器单元可以包括第一输入电路10、第二输入电路20、输出电路30和上拉节点复位电路40。
第一输入电路10连接第一信号端IN1、第一电压端V1、上拉节点PU，用于在第一信号端IN1的控制下，将第一电压端V1的电压输出至上拉节点PU。
第二输入电路20连接第二信号端IN2、第二电压端V2、上拉节点PU，用于在第二信号端IN2的控制下，将第二电压端V2的电压输出至上拉节点PU。
输出电路30连接时钟信号端CLK、上拉节点PU、信号输出端OUTPUT，用于在上拉节点PU的控制下，将时钟信号端CLK的时钟信号输出至信号输出端OUTPUT。
上拉节点复位电路40连接第三信号端IN3、第三电压端V3、上拉节点PU，用于在第三信号端IN3的控制下，将第三电压端V3的电压输出至上拉节点PU。
本公开的实施例提供的移位寄存器单元通过增加上拉节点复位电路40，在信号输出端输出栅极扫描信号后，控制上拉节点复位电路40开启，上拉节点复位电路40向上拉节点输出低电平信号，以使输出电路30关闭。对于最后一级移位寄存器单元，无需等到下一帧开始，其输出电路30可以在上拉节点复位电路40的控制下被关闭，从而缩短了输出电路30的工作时间。
需要说明的是，信号输出端OUTPUT的电位可通过时钟信号端CLK输入的低电平来复位。
例如，如图2(b)所示，所述移位寄存器单元还包括信号输出端复位电路50。
信号输出端复位电路50连接第三信号端IN3、第三电压端V3、信号输出端OUTPUT，用于在第三信号端IN3的控制下，将第三电压端V3的电压输出至信号输出端OUTPUT。
例如，如图2(b)所示，所述移位寄存器单元还包括下拉控制电路60、下拉电路70、降噪电路80。
下拉控制电路60连接第三电压端V3、第四电压端V4、上拉节点PU、下 拉节点PD，用于对所述下拉节点PD的电平进行控制。例如，在一些示例中，下拉控制电路60被配置为在上拉节点PU的控制下，将第三电压端V3的电压输出至下拉节点PD；或者，在另一些示例中，下拉控制电路60被配置为在上拉节点PU的控制下，将第四电压端V4的电压输出至下拉节点PD。
下拉电路70连接下拉节点PD、第三电压端V3、信号输出端OUTPUT，用于在下拉节点PD的控制下，将第三电压端V3的电压输出至信号输出端OUTPUT。
降噪电路80连接下拉节点PD、第三电压端V3、上拉节点PU，用于在下拉节点PD的控制下将第三电压端V3的电压输出至上拉节点PU。
下拉控制电路60能够控制下拉节点PD的电位，以使得该下拉节点PD能够控制降噪电路80将上拉节点PU的电位下拉至第三电压端V3输出的电压的电位，从而对上拉节点PU进行降噪。
需要说明的是，本公开实施例中上述第一信号端IN1输出的信号和第二信号端IN2输出的信号反相，也就是说，若第一信号端IN1输出的信号为高电平信号，则第二信号端IN2输出的信号为低电平信号；若第一信号端IN1输出的信号为低电平信号，则第二信号端IN2输出的信号为高电平信号。此外，以下实施例均是以第一电压端V1输出的第一电源电压为高电平信号，第二电压端V2输出的第二电源电压和第三电压端V3输出的第三电源电压均为低电平信号，或者第二电压端V2和第三电压端V3接地为例进行的说明。
一方面，第一输入电路10能够在第一信号端IN1控制下，将第一电压端V1的电压输出至上拉节点PU，此外，第二输入电路20能够在第二信号端IN2的控制下，将第二电压端V2的电压输出至上拉节点PU。在此情况下，当该移位寄存器单元采用正向扫描时，第一电压端V1输出的第一电源电压为高电平信号，第二电压端V2输出的第二电源电压为低电平信号，第一电压端V1的电压用于对上拉节点PU进行充电，第二电压端V2的电压用于对上拉节点PU进行复位。而当该移位寄存器单元采用反向扫描时，第一电压端V1输出的第一电源电压为低电平信号，第二电压端V2输出的第二电源电压为高电平信号，第二电压端V2的电压用于对上拉节点PU进行充电，第一电压端V1的电压用于对上拉节点PU进行复位。
基于此，当上拉节点PU被充电后，输出电路30在该上拉节点PU的控制下，可以将时钟信号端CLK的时钟信号输出至信号输出端OUTPUT，以使得 信号输出端OUTPUT在输出阶段能够向与该信号输出端OUTPUT相连接的栅线输出栅极扫描信号。第二输入电路20在第二信号端IN2的控制下，将第二电压端V2的电压输出至上拉节点PU，以通过下拉控制电路60控制下拉节点PD的电位，以使下拉电路70在下拉节点PD的控制下，将信号输出端OUTPUT的电位下拉至第三电压端V3的电位。
另一方面，上拉节点复位电路40能够在第三信号端IN3的控制下将上拉节点PU的电位下拉至第三电压端V3的电位，以控制输出电路30关闭；信号输出端复位电路50能够在第三信号端IN3的控制下将信号输出端OUTPUT的电位也下拉至第三电压端V3的电位。
这样一来，通过增加上拉节点复位电路40，在信号输出端OUTPUT输出栅极扫描信号后，控制上拉节点复位电路40开启，上拉节点复位电路40向上拉节点PU输出低电平信号，使输出电路30关闭。对于最后一级移位寄存器单元，无需等到下一帧开始，其输出电路30即可在上拉节点复位电路40的控制下被关闭，从而缩短了最后一级移位寄存器单元的输出电路30的工作时间。此外，对于每个移位寄存器单元，在下一帧开始之前，可以通过信号输出端复位电路50向信号输出端OUTPUT输出低电位，从而可对移位寄存器单元起到降噪的作用。
以下，对上述移位寄存器单元中的各个电路的具体结构进行详细的说明。
例如，如图3和图4所示，上拉节点复位电路40包括第一晶体管M1。第一晶体管M1的栅极连接第三信号端IN3，第一极连接第三电压端V3，第二极连接上拉节点PU。
例如，如图3和图4所示，信号输出端复位电路50包括第二晶体管M2。第二晶体管M2的栅极连接第三信号端IN3，第一极连接第三电压端V3，第二极连接信号输出端OUTPUT。
例如，如图3和图4所示，第一输入电路10包括第三晶体管M3。所述第三晶体管M3的栅极连接所述第一信号端IN1，第一极连接所述第一电压端V1，第二极连接所述上拉节点PU。
例如，如图3和图4所示，第二输入电路20包括第四晶体管M4。所述第四晶体管M4的栅极连接所述第二信号端IN2，第一极连接所述第二电压端V2，第二极连接所述上拉节点PU。
例如，如图3和图4所示，输出电路30包括第五晶体管M5和电容C。所 述第五晶体管M5的栅极连接所述上拉节点PU，第一极连接所述时钟信号端CLK，第二极连接所述信号输出端OUTPUT和所述电容C的第二端。所述电容C的第一端连接所述上拉节点PU，第二端还连接所述信号输出端OUTPUT。
例如，如图3所示，在一些实施例中，下拉控制电路60包括第六晶体管M6、第七晶体管M7。所述第六晶体管M6的栅极连接所述第四电压端V4，第一极连接所述第四电压端V4，第二极连接所述下拉节点PD。所述第七晶体管M7的栅极连接所述上拉节点PU，第一极连接所述第三电压端V3，第二极连接所述下拉节点PD。
例如，如图4所示，在另一些实施例中，下拉控制电路60还包括第八晶体管M8、第九晶体管M9。所述第八晶体管M8的栅极连接所述第四电压端V4，第一极连接所述第四电压端V4，第二极连接所述第六晶体管M6的栅极。所述第九晶体管M9的栅极连接所述上拉节点PU，第一极连接所述第三电压端V3，第二极连接所述第六晶体管M6的栅极。
例如，如图3和图4所示，下拉电路70包括第十晶体管M10。第十晶体管M10的栅极连接下拉节点PD，第一极连接第三电压端V3，第二极连接信号输出端OUTPUT。
例如，如图3和图4所示，降噪电路80包括第十一晶体管M11。第十一晶体管M11的栅极连接下拉节点PD，第一极连接第三电压端V3，第二极连接上拉节点PU。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除作为控制极的栅极，直接描述了其中一极为第一极，另一极为第二极，所以本公开实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。上述晶体管的第一极可以为源极，第二极可以为漏极，或者，上述晶体管的第一极可以为漏极，第二极为源极，本公开对此不作限定。上述晶体管可以为N型晶体管，也可以为P型晶体管；可以为增强型晶体管，也可以为耗尽型晶体管；为了清楚起见，本公开的实施例以晶体管为N型晶体管为例详细阐述了本公开的技术方案，然而本公开的实施例的晶体管不限于N型晶体管，本领域技术人员还可以根据实际需要利用P型晶体管实现本公开中的实施例中的一个或多个晶体管的功能。
图3为图2(b)中各个电路的一种具体结构示意图；图4为图2(b)中各个电路的另一种具体结构示意图；图5为控制图3或4所示的移位寄存器单元的一种信号时序图。以下，结合图5所示的信号时序图对图3和图4所示的移位寄存器单元在的不同阶段的情况进行详细的举例说明。其中，本公开实施例中是以第一电压端V1输出的第一电源电压为高电平信号，第二电压端V2输出的第二电源电压和第三电压端V3输出的第三电源电压均为低电平信号为例进行的说明。此外，以下说明是以第一信号端IN1输出的信号为输入信号INPUT，第二信号端IN2输出的信号为复位信号RESET为例。需要说明的是，在以下说明中，“1”表示高电平信号，“0”表示低电平信号。
例如，如图5所示，在第U帧中，在输入阶段P1，输入信号INPUT为高电平信号，复位信号RESET为低电平信号，时钟信号端CLK输出的时钟信号CLKA为低电平信号，第三信号端IN3输出的上拉节点复位信号Ctrl为低电平信号，第四电压端V4输出的第四电源电压V d4为高电平信号，也就是说，INPUT＝1，RESET＝0，CLKA＝0，Ctrl＝0，V d4＝1。
此时，由于第一信号端IN1输出高电平信号，因此第三晶体管M3导通，从而将第一电压端V1输出的高电平的第一电源电压输出至上拉节点PU，从而上拉节点PU的电压为高电平信号。在上拉节点PU高电位的控制下，第五晶体管M5导通，从而将时钟信号端CLK的低电平的时钟信号CLKA输出至信号输出端OUTPUT。
例如，如图3所示，在上拉节点PU高电位的控制下，第七晶体管M7导通，在第四电压端V4输出的高电平的第四电源电压V d4的控制下，第六晶体管M6导通，但由于第七晶体管M7沟道的宽长比大于第六晶体管M6沟道的宽长比，使得下拉节点PD的电位仍会通过第七晶体管M7下拉至第三电压端V3输出的第三电源电压。在此情况下，下拉节点PD的电压为低电平信号，从而第十晶体管M10和第十一晶体管M11均处于截止状态。
例如，如图4所示，在上拉节点PU高电位的控制下，第七晶体管M7和第九晶体管M9导通，在第四电压端V4输出的高电平的第四电源电压V d4的控制下，第八晶体管M8导通，但由于第九晶体管M9沟道的宽长比大于第八晶体管M8沟道的宽长比，使得第六晶体管M6栅极为低电平，从而控制第六晶体管M6截止，下拉节点PD的电位通过第七晶体管M7下拉至第三电压端V3输出的第三电源电压。在此情况下，下拉节点PD的电压为低电平信号，从 而第十晶体管M10和第十一晶体管M11均处于截止状态。
此外，第三信号端IN3输出低电平信号，使得第一晶体管M1和第二晶体管M2均截止；第二信号端IN2输出低电平信号，使得第四晶体管M4截止。
综上所述，信号输出端OUTPUT在上述输入阶段P1输出低电平。
例如，如图5所示，在输出阶段P2，输入信号INPUT为低电平信号，复位信号RESET为低电平信号，时钟信号端CLK输出的时钟信号CLKA为高电平信号，第三信号端IN3输出的上拉节点复位信号Ctrl为低电平信号，第四电压端V4输出的第四电源电压V d4为高电平信号，也就是说，INPUT＝0，RESET＝0，CLKA＝1，Ctrl＝0，V d4＝1。
此时，由于第一信号端IN1输出低电平信号，因此第三晶体管M3处于截止状态。由于电容C的保持作用，电容C继续对上拉节点PU进行充电，从而使得第五晶体管M5保持开启状态。在此情况下，时钟信号端CLK的输出的高电平的时钟信号CLKA通过第五晶体管M5输出至信号输出端OUTPUT。此外，在电容C的自举(Bootstrapping)作用下，上拉节点PU的电位进一步升高(电容C与信号输出端OUTPUT连接的一端的电位由0跳变为1，在电容C对上拉节点PU进行充电时，上拉节点PU的电位在1的基础上再向高电位跳变1)，以维持第五晶体管M5处于导通的状态，从而使得时钟信号端CLK输出的时钟信号CLKA能够作为栅极扫描信号输出至与信号输出端OUTPUT相连接的栅线上。
例如，如图3所示，在上拉节点PU高电位的控制下，第七晶体管M7导通，在第四电压端V4输出的高电平第四电源电压V d4的控制下，第六晶体管M6导通，但由于第七晶体管M7沟道的宽长比大于第六晶体管M6沟道的宽长比，使得下拉节点PD的电位仍会通过第七晶体管M7下拉至第三电压端V3输出的第三电源电压。在此情况下，下拉节点PD的电压为低电平信号，从而第十晶体管M10和第十一晶体管M11均处于截止状态。
例如，如图4所示，在上拉节点PU高电位的控制下，第七晶体管M7和第九晶体管M9导通，在第四电压端V4输出的高电平的第四电源电压V d4的控制下，第八晶体管M8导通，但由于第九晶体管M9沟道的宽长比大于第八晶体管M8沟道的宽长比，使得第六晶体管M6栅极为低电平，从而第六晶体管M6截止，下拉节点PD的电位通过第七晶体管M7下拉至第三电压端V3输出的第三电源电压。在此情况下，下拉节点PD的电压为低电平信号，从而 第十晶体管M10和第十一晶体管M11均处于截止状态。
此外，第三信号端IN3输出低电平信号，使得第一晶体管M1和第二晶体管M2均截止，第二信号端IN2输出低电平信号，使得第四晶体管M4截止。
综上所述，信号输出端OUTPUT在上述输出阶段P2输出高电平，以向与信号输出端OUTPUT相连接的栅线输出栅极扫描信号。
例如，如图5所示，在下拉阶段P3，输入信号INPUT为低电平信号，复位信号RESET为高电平信号，时钟信号端CLK输出的时钟信号CLKA为低电平信号，第三信号端IN3输出的上拉节点复位信号Ctrl为低电平信号，第四电压端V4输出的第四电源电压V d4为高电平信号，也就是说，INPUT＝0，RESET＝1，CLKA＝0，Ctrl＝0，V d4＝1。
此时，由于第二信号端IN2输出高电平信号，第四晶体管M4导通，上拉节点PU的电位被下拉至第二电压端V2输出的第二电源电压，从而第五晶体管M5处于截止状态。
例如，如图3所示，在上拉节点PU低电位的控制下，第七晶体管M7截止，第六晶体管M6在第四电压端V4输出的第四电源电压V d4的控制下导通，并将第四电压端V4输出的第四电源电压V d4输出至下拉节点PD，由此，下拉节点PD的电压为高电平信号，在下拉节点PD高电位的控制下，第十晶体管M10和第十一晶体管M11均导通，通过第十一晶体管M11将上拉节点PU的电位下拉至第三电压端V3输出的第三电源电压，并通过第十晶体管M10将信号输出端OUTPUT的电位下拉至第三电压端V3输出的第三电源电压。
例如，如图4所示，在上拉节点PU低电位的控制下，第七晶体管M7和第九晶体管M9均截止，第八晶体管M8在第四电压端V4输出的第四电源电压V d4的控制下导通，并将第四电压端V4输出的第四电源电压V d4输出至第六晶体管M6的栅极，控制第六晶体管M6导通，第六晶体管M6将第四电压端V4输出的第四电源电压V d4输出至下拉节点PD，由此，下拉节点PD的电压为高电平信号，在下拉节点PD高电位的控制下，第十晶体管M10和第十一晶体管M11均导通，通过第十一晶体管M11将上拉节点PU的电位下拉至第三电压端V3输出的第三电源电压，并通过第十晶体管M10将信号输出端OUTPUT的电位下拉至第三电压端V3输出的第三电源电压。
此外，第一信号端IN1输出低电平信号，使得第三晶体管M3截止；第三信号端IN3输出低电平信号，使得第一晶体管M1和第二晶体管M2均截止。
例如，如图5所示，在复位阶段P4，输入信号INPUT为低电平信号，复位信号RESET为低电平信号，第三信号端IN3输出的上拉节点复位信号Ctrl为高电平信号，第四电压端V4输出的第四电源电压V d4为低电平信号，也就是说，INPUT＝0，RESET＝0，Ctrl＝1，V d4＝0。
此时，第三信号端IN3输出高电平信号，从而第一晶体管M1和第二晶体管M2均导通，第一晶体管M1将第三电压端V3输出的第三电源电压输出至上拉节点PU，以对上拉节点PU进行复位，此时，上拉节点PU的电压为低电平信号，第五晶体管M5截止；另外，第二晶体管M2将第三电压端V3输出的第三电源电压输出至信号输出端OUTPUT，以对信号输出端OUTPUT进行复位。
例如，第三信号端IN3可以在整个复位阶段P4一直输出高电平信号，也可以是在复位阶段P4开始和/或结束时各输出一次高电平信号。
在复位阶段P4中，除了第一晶体管M1和第二晶体管M2导通以外，其余晶体管均处于截止状态。
需要说明的是，上述实施例中晶体管的工作过程是以所有晶体管为N型晶体管为例进行说明的，当所有晶体管均为P型时，需要对图5中各个控制信号进行翻转，而移位寄存器单元中各个电路的晶体管的工作过程同上所述，此处不再赘述。
例如，上述移位寄存器单元的工作过程，是以上述多个移位寄存器单元级联构成的栅极驱动电路采用正向扫描的方式为例进行的说明。当采用反向扫描时，在图3和图4所示的移位寄存器单元中，则第一信号端IN1输出复位信号RESET，第二信号端IN2输出输入信号INPUT。此外，上述第一电压端V1输出低电平信号，第二电压端V2输出高电平信号。
本公开实施例还提供一种栅极驱动电路，图6为本公开实施例提供的一种栅极驱动电路的结构示意图。例如，如图6所示，栅极驱动电路包括多个级联的如上述任意一项所述的移位寄存器单元(RS1、RS2……RSn)。
例如，第一级移位寄存器单元RS1的第一信号端IN1连接起始信号端STV，除了第一级移位寄存器单元RS1以外，本级移位寄存器单元RS(n-1)的第一信号端IN1与上一级移位寄存器单元RS(n-2)的信号输出端OUTPUT连接。起始信号端STV用于输出起始信号，该栅极驱动电路的第一级移位寄存器单元RS1在接收到上述起始信号后开始对栅线(G1、G2……Gn)进行逐行扫描。
例如，除了最后一级移位寄存器单元RSn以外，本级移位寄存器单元RS(n-1)的第二信号端IN2与下一级移位寄存器单元RSn的信号输出端OUTPUT连接，最后一级移位寄存器单元RSn的第二信号端IN2连接上述起始信号端STV。当起始信号端STV的起始信号输入第一级移位寄存器单元RS1的第一信号端IN1时，最后一级移位寄存器单元RSn的第二信号端IN2可以将起始信号端STV的起始信号作为复位信号对最后一级移位寄存器单元RSn的信号输出端OUTPUT进行复位。
在此基础上，每一级移位寄存器单元的第一电压端V1连接高电平VDD，第二电压端V2连接低电平VSS，第三电压端V3连接低电平VGL。
例如，如图6所示，栅极驱动电路提供第一时钟信号CLKA和第二时钟信号CLKB，第一时钟信号CLKA被施加至第2N-1级移位寄存器单元的时钟信号端CLK；第二时钟信号CLKB被施加至第2N级移位寄存器单元的时钟信号端CLK；N为正整数，且N大于等于1。
此外，图6所示的栅极驱动电路是对栅线进行正向扫描时各个控制信号的连接方法。当采用该栅极驱动电路对栅线进行反向扫描时，第一级移位寄存器单元RS1的第二信号端IN2连接起始信号端STV，除了第一级移位寄存器单元RS1以外，本级移位寄存器单元RS(n-1)的第二信号端IN2与上一级移位寄存器单元RS(n-2)的信号输出端OUTPUT连接，上一级移位寄存器单元RS(n-1)的信号输出端OUTPUT与下一级移位寄存器单元RS(n)的第二信号端IN2相连接。除了最后一级移位寄存器单元RSn以外，本级移位寄存器单元RS(n-1)的第一信号端IN1与上一级移位寄存器单元RSn的信号输出端OUTPUT连接。最后一级移位寄存器单元RSn的第一信号端IN1连接上述起始信号端STV。此时，每一级移位寄存器单元的第一电压端V1连接低电平VSS，第二电压端V2连接高电平VDD，第三电压端V3连接低电平VGL。
从图6可知，栅极驱动电路中的每个移位寄存器单元连接同一根第三信号端IN3，当第三信号端IN3输出高电平信号时，栅极驱动电路中的所有移位寄存器单元实现对信号输出端OUTPUT和上拉节点PU的复位。
需要说明的是，在本公开中，可以仅在栅极驱动电路的最后一级移位寄存器单元中设置上拉节点复位电路；也可以在栅极驱动电路的所有移位寄存器单元中设置上拉节点复位电路，本公开对此不作限制。
本公开实施例还提供一种显示装置，图7为本公开一实施例提供的一种显 示装置的示意框图。例如，如图7所示，显示装置100包括如上所述的任意一种栅极驱动电路50，该显示装置100具有与前述实施例提供的栅极驱动电路相同的有益效果。由于前述实施例已经对栅极驱动电路的结构和有益效果进行了详细的描述，此处不再赘述。
本公开实施例还提供一种用于驱动上述栅极驱动电路的驱动方法，图8为本公开一实施例提供的一种栅极驱动电路的驱动方法的流程图。例如，如图8所示，所述驱动方法包括：
S20：在一帧的扫描阶段，栅极驱动电路的第一级移位寄存器单元接收起始信号端的起始信号，逐级开启栅极驱动电路中的移位寄存器单元。
除最后一级外的移位寄存器单元外，各级移位寄存器单元的上拉节点PU电位的拉低是第二输入电路20在第二信号端IN2的控制下将第三电压端V3的信号输入至上拉节点PU来完成的；最后一级位移位寄存器单元输出栅极扫描信号后，最后一级位移位寄存器单元的上拉节点PU电位的拉低是上拉节点复位电路40在第三信号端IN3的控制下将第三电压端V3的信号输入至上拉节点PU来完成的。
S21：在一帧的场消隐阶段，在第三信号端的控制下，将第三电压端的电压输出至所有级联的移位寄存器单元的上拉节点，以同时复位所有级联的移位寄存器单元的上拉节点。
本公开实施例提供的栅极驱动电路的驱动方法的有益效果与上述移位寄存器单元的有益效果相同，此处不再赘述。
本公开实施例还提供一种用于驱动上述任意一种移位寄存器单元的方法，图9为本公开一实施例提供的一种移位寄存器单元的驱动方法的流程图。例如，如图9所示，所述驱动方法包括：
S10：在输入阶段，在第一信号端的控制下，第一输入电路将第一电压端的电压输出至上拉节点；
S11：在输出阶段，在上拉节点的控制下，输出电路将时钟信号端的时钟信号输出至信号输出端，信号输出端输出栅极扫描信号。
例如，如图5所示，在步骤S10中，在输入阶段P1：
在第一信号端IN1的控制下，第一输入电路10将第一电压端V1的第一电源电压输出至上拉节点PU。在上拉节点PU的控制下，输出电路30将时钟信号端CLK的时钟信号(低电平信号)输出至信号输出端OUTPUT。
例如，当上述移位寄存器单元中各个电路的结构如图3或图4所示，且各个电路中的晶体管均为N型晶体管时，如图5所示，在该输入阶段P1中，时钟信号端CLK输出的时钟信号CLKA为低电平信号，第一信号端IN1输出高电平信号，第二信号端IN2输出低电平信号，第三信号端IN3输出低电平信号，第四电压端V4输出高电压，上拉节点PU的电压为高电平，此时，信号输出端OUTPUT输出低电平信号。
例如，第一信号端IN1输出高电平信号，从而第一输入电路10在第一信号端IN1的高电平的控制下将第一电压端V1输出的第一电源电压(高电平信号)输出至上拉节点PU。在输入阶段P1，由于第一信号端IN1输出高电平信号，因此第三晶体管M3导通，从而将第一电压端V1输出的第一电源电压输出至上拉节点PU，从而上拉节点PU的电压为高电平信号。在上拉节点PU的控制下，第五晶体管M5导通，将时钟信号端CLK的低电平的时钟信号CLKA输出至信号输出端OUTPUT。
例如，第三信号端IN3输出低电平信号，使得第一晶体管M1和第二晶体管M2均截止，第二信号端IN2输出低电平信号，使得第四晶体管M4截止。
例如，如图5所示，在步骤S20中，在输出阶段P2，在上拉节点PU的控制下，输出电路30将时钟信号端CLK的时钟信号CLKA(高电平信号)输出至信号输出端OUTPUT，信号输出端OUTPUT输出栅极扫描信号。
例如，当上述移位寄存器单元中各个电路的结构如图3或图4所示，且各个电路中的晶体管均为N型晶体管时，如图5所示，在输出阶段P2，时钟信号端CLK输出的时钟信号CLKA为高电平信号，第一信号端IN1输出低电平信号，第二信号端IN2输出低电平信号，第三信号端IN3输出低电平信号，第四电压端V4输出高电平信号；上拉节点PU的电压为高电平，此时，信号输出端OUTPUT输出高电平信号。
例如，在上拉节点PU高电平的控制下，输出电路30将时钟信号端CLK输出的时钟信号CLKA输出至信号输出端OUTPUT。在输出阶段P2，由于第一信号端IN1输出低电平信号，因此第三晶体管M3处于截止状态。电容C将继续对上拉节点PU进行充电，从而使得第五晶体管M5保持开启状态。在此情况下，时钟信号端CLK输出的高电平的时钟信号CLKA通过第五晶体管M5输出至信号输出端OUTPUT。此外，在电容C的自举(Bootstrapping)作用下，上拉节点PU的电位进一步升高，以维持第五晶体管M5处于导通的状 态，从而使得时钟信号端CLK输出的时钟信号CLKA能够作为栅极扫描信号输出至与信号输出端OUTPUT相连接的栅线上。
例如，第三信号端IN3输出低电平信号，使得第一晶体管M1和第二晶体管M2均截止，第二信号端IN2输出低电平信号，使得第四晶体管M4截止。
本公开提供的移位寄存器单元驱动方法的有益效果与上述移位寄存器单元的有益效果均相同，此处不再赘述。
例如，在一些实施例中，所述移位寄存器单元还包括信号输出端复位电路50、下拉控制电路60、下拉电路70、降噪电路80，如图5所示，在输入阶段P1，在第一信号端IN1的控制下，第一输入电路10将第一电压端V1的第一电源电压输出至上拉节点PU。在上拉节点PU的控制下，输出电路30将时钟信号端CLK的时钟信号CLKA(低电平信号)输出至信号输出端OUTPUT。
例如，下拉控制电路60在上拉节点PU高电位的控制下，将下拉节点PD的电位下拉至第三电压端V3输出的第三电源电压。此时，第二输入电路20、下拉电路70、降噪电路80、上拉节点复位电路40均未开启。
例如，当上述移位寄存器单元中各个电路的结构如图3或图4所示，且各个电路中的晶体管均为N型晶体管时，如图5所示，在输入阶段P1，时钟信号端CLK输出低电平信号(CLKA)，第一信号端IN1输出高电平信号，第二信号端IN2输出低电平信号，第三信号端IN3输出低电平信号，第四电压端V4输出高电压，上拉节点PU的电压为高电平，下拉节点PD的电压为低电平，此时，信号输出端OUTPUT输出低电平信号。
例如，第一信号端IN1输出高电平信号，第一输入电路10在第一信号端IN1的高电平的控制下将第一电压端V1的高电平输出至上拉节点PU。例如，在输入阶段P1，由于第一信号端IN1输出高电平信号，因此第三晶体管M3导通，从而将第一电压端V1输出的第一电源电压输出至上拉节点PU，从而上拉节点PU的电压为高电平信号。在上拉节点PU的控制下，第五晶体管M5导通，将时钟信号端CLK的低电平的时钟信号CLKA输出至信号输出端OUTPUT。
例如，如图3所示，在上拉节点PU高电位的控制下，第七晶体管M7导通，在第四电压端V4输出的高电平第四电源电压控制下，第六晶体管M6导通，但由于第七晶体管M7沟道的宽长比大于第六晶体管M6沟道的宽长比，使得下拉节点PD的电位仍会通过第七晶体管M7下拉至第三电压端V3输出 的第三电源电压。在此情况下，下拉节点PD的电压为低电平信号，从而第十晶体管M10和第十一晶体管M11均处于截止状态。
例如，如图4所示，在上拉节点PU高电位的控制下，第七晶体管M7和第九晶体管M9导通，在第四电压端V4输出的高电平的第四电源电压的控制下，第八晶体管M8导通，但由于第九晶体管M9沟道的宽长比大于第八晶体管M8沟道的宽长比，使得第六晶体管M6栅极为低电平，从而第六晶体管M6截止，下拉节点PD的电位通过第七晶体管M7下拉至第三电压端V3输出的第三电源电压。在此情况下，下拉节点PD的电压为低电平信号，从而第十晶体管M10和第十一晶体管M11均处于截止状态。
此外，第三信号端IN3输出低电平信号，使得第一晶体管M1和第二晶体管M2均截止，第二信号端IN2输出低电平信号，使得第四晶体管M4截止。
例如，如图5所示，在输出阶段P2，在上拉节点PU的控制下，输出电路30将时钟信号端CLK的时钟信号CLKA(高电平信号)输出至信号输出端OUTPUT，信号输出端OUTPUT输出栅极扫描信号。
例如，下拉控制电路60在上拉节点PU高电位的控制下，将下拉节点PD的电位下拉至第三电压端V3输出的第三电源电压。此时，第一输入电路10、第二输入电路20、降噪电路80、下拉电路70和上拉节点复位电路40均未开启。
例如，当上述移位寄存器单元中各个电路的结构如图3或图4所示，且各个电路中的晶体管均为N型晶体管时，如图5所示，在输出阶段P2，时钟信号端CLK输出高电平信号(CLKA)，第一信号端IN1输出低电平信号，第二信号端IN2输出低电平信号、第三信号端IN3输出低电平信号、第四电压端V4输出高电压；上拉节点PU的电压为高电平，下拉节点PD的电压为低电平，此时，信号输出端OUTPUT输出高电平信号。
例如，在上拉节点PU高电平的控制下，输出电路30将时钟信号端CLK输出的时钟信号CLKA(高电平信号)输出至信号输出端OUTPUT。例如，在输出阶段P2，由于第一信号端IN1输出低电平信号，因此第三晶体管M3处于截止状态。电容C对上拉节点PU进行充电，从而使得第五晶体管M5保持开启状态。在此情况下，时钟信号端CLK输出的时钟信号CLKA通过第五晶体管M5输出至信号输出端OUTPUT。此外，在电容C的自举(Bootstrapping)作用下，上拉节点PU的电位进一步升高，以维持第五晶体管M5处于导通的 状态，从而使得时钟信号端CLK输出的时钟信号CLKA能够作为栅极扫描信号输出至与信号输出端OUTPUT相连接的栅线上。
例如，如图3所示，在上拉节点PU高电位的控制下，第七晶体管M7导通，在第四电压端V4输出的高电平第四电源电压的控制下，第六晶体管M6导通，但由于第七晶体管M7沟道的宽长比大于第六晶体管M6沟道的宽长比，使得下拉节点PD的电位仍会通过第七晶体管M7下拉至第三电压端V3输出的第三电源电压。在此情况下，下拉节点PD的电压为低电平信号，从而第十晶体管M10和第十一晶体管M11均处于截止状态。
例如，如图4所示，在上拉节点PU高电位的控制下，第七晶体管M7和第九晶体管M9导通，在第四电压端V4输出的高电平的第四电源电压的控制下，第八晶体管M8导通，但由于第九晶体管M9沟道的宽长比大于第八晶体管M8沟道的宽长比，使得第六晶体管M6栅极为低电平，从而第六晶体管M6截止，下拉节点PD的电位通过第七晶体管M7下拉至第三电压端V3输出的第三电源电压。在此情况下，下拉节点PD的电压为低电平信号，从而第十晶体管M10和第十一晶体管M11均处于截止状态。
此外，第三信号端IN3输出低电平信号，使得第一晶体管M1和第二晶体管M2均截止，第二信号端IN2输出低电平信号，使得第四晶体管M4截止。
例如，在一些实施例中，驱动方法还包括：下拉阶段，在第二信号端的控制下，第二输入电路将第二电压端的电压输出至上拉节点，以控制输出电路关闭；在上拉节点的控制下，下拉控制电路将第四电压端的电压输出至下拉节点；在下拉节点的控制下，下拉电路将第三电压端的电压输出至信号输出端，降噪电路将所述第三电压端的电压输出至上拉节点。
例如，如图5所示，在下拉阶段P3：在第二信号端IN2的控制下，第二输入电路20将第二电压端V2的第二电源电压输出至上拉节点PU，以控制输出电路30关闭；在上拉节点PU的控制下，下拉控制电路60将第四电压端V4输出的第四电源电压(高电平信号)输出至下拉节点PD；在下拉节点PD的控制下，下拉电路70将第三电压端V3的第三电源电压输出至信号输出端OUTPUT，同时，降噪电路80将将第三电压端V3的第三电源电压输出至上拉节点PU。
例如，在下拉阶段P3，第一输入电路10、第二输入电路20、上拉节点复位电路40均未开启。
例如，当上述移位寄存器单元中各个电路的结构如图3或图4所示，且各个电路中的晶体管均为N型晶体管时，如图5所示，在下拉阶段P3，时钟信号端CLK输出的时钟信号CLKA为低电平信号，第一信号端IN1输出低电平信号，第二信号端IN2输出高电平信号；上拉节点PU的电压为低电平信号，下拉节点PD的电压为高电平，此时，信号输出端OUTPUT输出低电平信号。
例如，下拉控制电路60将第四电压端V4的第四电源电压(高电平)输出至下拉节点PD，在下拉节点PD的控制下，下拉电路70将第三电压端V3的第三电源电压(低电平)输出至信号输出端OUTPUT，降噪电路80将第三电压端V3的第三电源电压(低电平)输出至上拉节点PU。例如，在下拉阶段P3，由于第二信号端IN2输出高电平信号，第四晶体管M4导通，从而将上拉节点PU的电位下拉至第二电压端V2的第二电源电压(低电平)，从而第五晶体管M5处于截止状态。
例如，如图3所示，在上拉节点PU低电位的控制下，第七晶体管M7截止，第六晶体管M6在第四电压端V4输出的第四电源电压的控制下导通，并将第四电压端V4输出的第四电源电压输出至下拉节点PD，由此，下拉节点PD的电压为高电平信号，在下拉节点PD高电位的控制下，第十晶体管M10和第十一晶体管M11均导通，通过第十一晶体管M11将上拉节点PU的电位下拉至第三电压端V3输出的第三电源电压(低电平)，并通过第十晶体管M10将信号输出端OUTPUT的电位下拉至第三电压端V3输出的第三电源电压。
例如，如图4所示，在上拉节点PU低电位的控制下，第七晶体管M7和第九晶体管M9均截止，第八晶体管M8在第四电压端V4输出的第四电源电压(高电平)的控制下导通，并将第四电压端V4输出的第四电源电压输出至第六晶体管M6的栅极，控制第六晶体管M6导通，第六晶体管M6将第四电压端V4输出的第四电源电压输出至下拉节点PD，由此，下拉节点PD的电压为高电平信号，在下拉节点PD高电位的控制下，第十晶体管M10和第十一晶体管M11均导通，通过第十一晶体管M11将上拉节点PU的电位下拉至第三电压端V3输出的第三电源电压(低电平)，并通过第十晶体管M10将信号输出端OUTPUT的电位下拉至第三电压端V3输出的第三电源电压。
例如，第一信号端IN1输出低电平信号，使得第三晶体管M3截止；第三信号端IN3输出低电平信号，使得第一晶体管M1和第二晶体管M2均截止。
例如，在一些实施例中，驱动方法还包括：在复位阶段，在第三信号端的 控制下，上拉节点复位电路将第三电压端的电压输出至上拉节点。
例如，如图5所示，在复位阶段P4，在第三信号端IN3的控制下，上拉节点复位电路40将第三电压端V3的电压输出至上拉节点PU，以对上拉节点PU进行复位，从而控制输出电路30关闭；信号输出端复位电路50将第三电压端V3的电压输出至信号输出端OUTPUT，对信号输出端OUTPUT进行复位。
例如，在复位阶段P4，第一输入电路10、第二输入电路20、下拉控制电路60、下拉电路70和降噪电路80均未开启。
例如，当上述移位寄存器单元中各个电路的结构如图3或图4所示，且各个电路中的晶体管均为N型晶体管时，如图5所示，在复位阶段P4，第一信号端IN1输出低电平信号，第二信号端IN2输出低电平信号，第三信号端IN3输出高电平信号，第四电压端V4输出低电平信号；上拉节点PU的电压为低电平信号，下拉节点PD的电压为低电平信号，此时，信号输出端OUTPUT输出低电平信号。
例如，在第三信号端IN3的控制下，上拉节点复位电路40将上拉节点PU的电压下拉至第三电压端V3的第三电源电压，从而输出电路30断开，时钟信号端CLK的高电平信号无法输出。例如，在复位阶段P4，第三信号端IN3输出高电平信号，从而第一晶体管M1导通，第一晶体管M1将第三电压端V3的第三电源电压输入至上拉节点PU，以对上拉节点PU进行复位，此时，在上拉节点PU的控制下第五晶体管M5截止；第三信号端IN3输出高电平信号，从而第二晶体管M2导通，第二晶体管M2将第三电压端V3的第三电源电压输入至信号输出端OUTPUT，以对信号输出端OUTPUT进行复位。
例如，在复位阶段P4，除第一晶体管M1和第二晶体管M2导通外，其余晶体管均处于截止状态。
需要说明的是，第一，如图6所示，对于最后一级移位寄存器单元，第三信号端IN3输出高电平信号后，等到下一帧开始时，第二信号端IN2才能输出高电平信号，也就是说，最后一级移位寄存器单元在上述四个阶段中，在执行完输入阶段P1和输出阶段P2后，会先进行复位阶段P4，然后再进行下拉阶段P3；而对于其他级移位寄存器单元来讲，从输入阶段P1到复位阶段P4依次执行。从而，上拉节点PU点电位的波形图如图10所示，最后一级移位寄存器单元的上拉节点无需等到下一帧扫描开始时被拉低，而是在本帧扫描结束后 的复位阶段P4直接被拉低。
第二，当移位寄存器单元中没有信号输出端复位电路50时，可以将上述驱动方法中关于降噪电路80的步骤全部去除，其余步骤不改变。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (16)

  1. 一种移位寄存器单元，包括：第一输入电路、第二输入电路、输出电路和上拉节点复位电路；
    所述第一输入电路连接第一信号端、第一电压端、上拉节点，用于在所述第一信号端的控制下，将所述第一电压端的电压输出至所述上拉节点；
    所述第二输入电路连接第二信号端、第二电压端、所述上拉节点，用于在所述第二信号端的控制下，将所述第二电压端的电压输出至所述上拉节点；
    所述输出电路连接时钟信号端、所述上拉节点、信号输出端，用于在所述上拉节点的控制下，将所述时钟信号端的时钟信号输出至所述信号输出端；
    所述上拉节点复位电路连接第三信号端、第三电压端、所述上拉节点，用于在所述第三信号端的控制下，将所述第三电压端的电压输出至所述上拉节点。
  2. 根据权利要求1所述的移位寄存器单元，还包括信号输出端复位电路；
    其中，所述信号输出端复位电路连接所述第三信号端、所述第三电压端、所述信号输出端，用于在所述第三信号端的控制下，将所述第三电压端的电压输出至所述信号输出端。
  3. 根据权利要求1或2所述的移位寄存器单元，还包括下拉控制电路、下拉电路、降噪电路；
    其中，所述下拉控制电路连接所述第三电压端、第四电压端、所述上拉节点、下拉节点，用于对所述下拉节点的电平进行控制；
    所述下拉电路连接所述下拉节点、所述第三电压端、所述信号输出端，用于在所述下拉节点的控制下，将所述第三电压端的电压输出至所述信号输出端；
    所述降噪电路连接所述下拉节点、所述第三电压端、所述上拉节点，用于在所述下拉节点的控制下将所述第三电压端的电压输出至所述上拉节点。
  4. 根据权利要求1-3任一项所述的移位寄存器单元，其中，所述上拉节点复位电路包括第一晶体管；
    所述第一晶体管的栅极连接所述第三信号端，第一极连接所述第三电压端，第二极连接所述上拉节点。
  5. 根据权利要求2-4任一项所述的移位寄存器单元，其中，所述信号输 出端复位电路包括第二晶体管；
    所述第二晶体管的栅极连接所述第三信号端，第一极连接所述第三电压端，第二极连接所述信号输出端。
  6. 根据权利要求1-5任一项所述的移位寄存器单元，其中，所述第一输入电路包括第三晶体管；所述第二输入电路包括第四晶体管；
    所述第三晶体管的栅极连接所述第一信号端，第一极连接所述第一电压端，第二极连接所述上拉节点；
    所述第四晶体管的栅极连接所述第二信号端，第一极连接所述第二电压端，第二极连接所述上拉节点。
  7. 根据权利要求1-6任一项所述的移位寄存器单元，其中，所述输出电路包括第五晶体管和电容；
    所述第五晶体管的栅极连接所述上拉节点，第一极连接所述时钟信号端，第二极连接所述信号输出端和所述电容的第二端；
    所述电容的第一端连接所述上拉节点，第二端还连接所述信号输出端。
  8. 根据权利要求3-7任一项所述的移位寄存器单元，其中，所述下拉控制电路包括第六晶体管、第七晶体管；
    所述第六晶体管的栅极连接所述第四电压端，第一极连接所述第四电压端，第二极连接所述下拉节点；
    所述第七晶体管的栅极连接所述上拉节点，第一极连接所述第三电压端，第二极连接所述下拉节点。
  9. 根据权利要求8所述的移位寄存器单元，其中，所述下拉控制电路还包括第八晶体管、第九晶体管；
    所述第八晶体管的栅极连接所述第四电压端，第一极连接所述第四电压端，第二极连接所述第六晶体管的栅极；
    所述第九晶体管的栅极连接所述上拉节点，第一极连接所述第三电压端，第二极连接所述第六晶体管的栅极。
  10. 根据权利要求3-9任一项所述的移位寄存器单元，其中，所述下拉电路包括第十晶体管；所述降噪电路包括第十一晶体管；
    所述第十晶体管的栅极连接所述下拉节点，第一极连接所述第三电压端，第二极连接所述信号输出端；
    所述第十一晶体管的栅极连接所述下拉节点，第一极连接所述第三电压 端，第二极连接所述上拉节点。
  11. 一种栅极驱动电路，包括至少两级级联的如权利要求1-10任一项所述的移位寄存器单元；
    第一级移位寄存器单元的第一信号端与起始信号端相连接；
    除了所述第一级移位寄存器单元以外，本级移位寄存器单元的第一信号端与上一级移位寄存器单元的信号输出端连接；
    除了最后一级移位寄存器单元以外，所述本级移位寄存器单元的第二信号端与下一级移位寄存器单元的信号输出端连接；
    所述最后一级移位寄存器单元的第二信号端连接所述起始信号端。
  12. 一种显示装置，包括权利要求11所述的栅极驱动电路。
  13. 一种用于驱动权利要求1-10任一项所述的移位寄存器单元的驱动方法，包括：
    输入阶段：
    在所述第一信号端的控制下，所述第一输入电路将所述第一电压端的电压输出至所述上拉节点；
    输出阶段：
    在所述上拉节点的控制下，所述输出电路将所述时钟信号端的时钟信号输出至所述信号输出端，所述信号输出端输出栅极扫描信号。
  14. 根据权利要求13所述的驱动方法，其中，所述移位寄存器单元还包括下拉控制电路、下拉电路、降噪电路；
    所述驱动方法还包括：
    下拉阶段：
    在所述第二信号端的控制下，所述第二输入电路将所述第二电压端的电压输出至所述上拉节点，以控制所述输出电路关闭；
    在所述上拉节点的控制下，所述下拉控制电路将第四电压端的电压输出至下拉节点；
    在所述下拉节点的控制下，所述下拉电路将所述第三电压端的电压输出至所述信号输出端，所述降噪电路将所述第三电压端的电压输出至所述上拉节点。
  15. 根据权利要求13或14所述的驱动方法，还包括：
    复位阶段：
    在所述第三信号端的控制下，所述上拉节点复位电路将所述第三电压端的电压输出至所述上拉节点。
  16. 一种用于驱动权利要求11所述的栅极驱动电路的驱动方法，包括：
    在一帧的扫描阶段：
    所述栅极驱动电路的第一级移位寄存器单元接收所述起始信号端的起始信号，逐级开启栅极驱动电路中的移位寄存器单元；
    在一帧的场消隐阶段：
    在所述第三信号端的控制下，将所述第三电压端的电压输出至所有级联的移位寄存器单元的上拉节点，以同时复位所有级联的移位寄存器单元的上拉节点。
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