WO2020253323A1 - 移位寄存器单元、驱动方法、栅极驱动电路和显示装置 - Google Patents

移位寄存器单元、驱动方法、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2020253323A1
WO2020253323A1 PCT/CN2020/082940 CN2020082940W WO2020253323A1 WO 2020253323 A1 WO2020253323 A1 WO 2020253323A1 CN 2020082940 W CN2020082940 W CN 2020082940W WO 2020253323 A1 WO2020253323 A1 WO 2020253323A1
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WIPO (PCT)
Prior art keywords
pull
node
control
transistor
electrically connected
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PCT/CN2020/082940
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English (en)
French (fr)
Inventor
刘幸一
吴鹏
汪弋
周纪登
吕凤珍
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Publication of WO2020253323A1 publication Critical patent/WO2020253323A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of display driving technology, and in particular to a shift register unit, a driving method, a gate driving circuit and a display device.
  • the register is composed of a combination of flip-flops with storage function.
  • a flip-flop can store one bit of binary code, and the register that stores N bit of binary code needs n flip-flops to form. According to function, it can be divided into: basic register and shift register.
  • the data in the shift register can be shifted to the right or left bit by bit under the action of the shift pulse.
  • the data can be input in parallel, output in parallel, serial input, serial output, or parallel input and serial output. Serial input and parallel output are very flexible and versatile.
  • the present disclosure provides a shift register unit, including a pull-down node control circuit and a bias control circuit, wherein
  • the control terminal of the pull-down node control circuit is electrically connected with the pull-up node
  • the first terminal of the pull-down node control circuit is electrically connected with the pull-down node
  • the second terminal of the pull-down node control circuit is electrically connected with the first voltage terminal
  • the pull-down node control circuit is configured to control the connection or disconnection between the pull-down node and the first voltage terminal under the control of the potential of the pull-up node
  • the bias control circuit is electrically connected to the pull-up node, and is used to control the potential of the pull-up node when the pull-down node control circuit controls the disconnection between the pull-down node and the first voltage terminal , To control the gate-source voltage of the pull-down node control transistor included in the pull-down node control circuit to be within a predetermined voltage range.
  • the pull-down node control transistor is an n-type transistor, and the predetermined voltage range is less than zero.
  • the pull-down node control transistor is a p-type transistor, and the predetermined voltage range is greater than zero.
  • the pull-down node control circuit includes a pull-down node control transistor
  • the control electrode of the pull-down node control transistor is electrically connected to the pull-up node
  • the first electrode of the pull-down node control transistor is electrically connected to the pull-down node
  • the second electrode of the pull-down node controls the transistor and the first voltage Terminal electrical connection.
  • the bias control circuit includes a bias control transistor
  • the control electrode of the bias control transistor is electrically connected to the bias control terminal, the first electrode of the bias control transistor is electrically connected to the pull-up node, and the second electrode of the bias control transistor is electrically connected to a second voltage Terminal electrical connection;
  • the bias control terminal is used to provide a bias control signal, so that when the pull-down node control transistor is turned off, the bias control transistor is controlled to be turned on.
  • the bias control voltage terminal is a pull-down control node
  • the pull-down node control circuit further includes a pull-down control node control circuit and a pull-down control transistor;
  • the pull-down control node control circuit is configured to control the potential of the pull-down control node under the control of the potential of the pull-up node;
  • the control electrode of the pull-down control transistor is electrically connected to the pull-down control node
  • the first electrode of the pull-down control transistor is electrically connected to the power supply voltage terminal
  • the second electrode of the pull-down control transistor is electrically connected to the pull-down node.
  • the pull-down node control transistor is an n-type transistor. When the pull-down node control transistor is turned off, the second voltage input from the second voltage terminal is less than the first voltage input from the first voltage terminal.
  • the pull-down node control transistor is a p-type transistor. When the pull-down node control transistor is turned off, the second voltage input from the second voltage terminal is greater than the first voltage input from the first voltage terminal.
  • the pull-down node includes a first pull-down node and a second pull-down node
  • the pull-down node control circuit includes a first pull-down node control transistor and a second pull-down node control transistor
  • the control electrode of the first pull-down node control transistor is electrically connected to the pull-up node, the first electrode of the first pull-down node control transistor is electrically connected to the first pull-down node, and the first pull-down node
  • the second pole of the pull node control transistor is electrically connected to the first voltage terminal
  • the control electrode of the second pull-down node control transistor is electrically connected to the pull-up node
  • the first electrode of the second pull-down node control transistor is electrically connected to the second pull-down node
  • the second pull-down node controls the transistor
  • the second pole is electrically connected to the first voltage terminal.
  • the bias control circuit includes a first bias control transistor and a second bias control transistor
  • the control electrode of the first bias control transistor is electrically connected to the first bias control terminal, the first electrode of the first bias control transistor is electrically connected to the pull-up node, and the first bias control transistor
  • the second pole of is electrically connected to the second voltage terminal;
  • the control electrode of the second bias control transistor is electrically connected to the second bias control terminal, the first electrode of the second bias control transistor is electrically connected to the pull-up node, and the second bias control transistor The second pole of is electrically connected to the third voltage terminal;
  • the first bias control terminal is used to provide a first bias control signal, so that when the first pull-down node control transistor and the second pull-down node control transistor are turned off, the first bias control is controlled The transistor is turned on;
  • the second bias control terminal is used to provide a second bias control signal, so that when the first pull-down node control transistor and the second pull-down node control transistor are turned off, the second bias control is controlled The transistor is turned on.
  • the first bias control voltage terminal is a first pull-down control node
  • the second bias control voltage terminal is a second pull-down control node
  • the pull-down node control circuit further includes a first pull-down control node control circuit, a first pull-down control transistor, a second pull-down control node control circuit, and a second pull-down control transistor;
  • the first pull-down control node control circuit is configured to control the potential of the first pull-down control node under the control of the potential of the pull-up node;
  • the control electrode of the first pull-down control transistor is electrically connected to the first pull-down control node, the first electrode of the first pull-down control transistor is electrically connected to the first power supply voltage terminal, and the first pull-down control transistor The second electrode of the control transistor is electrically connected to the first pull-down node;
  • the second pull-down control node control circuit is configured to control the potential of the second pull-down control node under the control of the potential of the pull-up node;
  • the control electrode of the second pull-down control transistor is electrically connected to the second pull-down control node
  • the first electrode of the second pull-down control transistor is electrically connected to the second power supply voltage terminal
  • the first electrode of the second pull-down control transistor is electrically connected.
  • the two poles are electrically connected to the second pull-down node.
  • the first pull-down control node control circuit includes a first pull-down control node control transistor and a second pull-down control node control transistor
  • the second pull-down control node control circuit includes a third pull-down control node control transistor and a second pull-down control node control transistor.
  • the control electrode of the first pull-down control node control transistor and the first electrode of the first pull-down control node control transistor are electrically connected to the first power supply voltage terminal, and the first pull-down control node controls the second terminal of the transistor. Pole is electrically connected to the first pull-down control node;
  • the control electrode of the second pull-down control node control transistor is electrically connected to the pull-up node
  • the first electrode of the second pull-down control node control transistor is electrically connected to the first pull-down control node
  • the second pull-down control node The second pole of the control transistor is electrically connected to the first voltage terminal by the pull-down control node
  • control electrode of the third pull-down control node control transistor and the first electrode of the third pull-down control node control transistor are electrically connected to the second power supply voltage terminal, and the third pull-down control node controls the second electrode of the transistor and the The second pull-down control node is electrically connected;
  • the control electrode of the fourth pull-down control node control transistor is electrically connected to the pull-up node
  • the first electrode of the fourth pull-down control node control transistor is electrically connected to the second pull-down control node
  • the fourth pull-down control node The second pole of the control node control transistor is electrically connected to the first voltage terminal.
  • the first pull-down node control transistor and the second pull-down node control transistor are both n-type transistors, and when the first pull-down node control transistor and the second pull-down node control transistor are turned off, The second voltage input from the second voltage terminal is smaller than the first voltage input from the first voltage terminal, and the third voltage input from the third voltage terminal is smaller than the first voltage.
  • the first pull-down node control transistor and the second pull-down node control transistor are both p-type transistors, and when the first pull-down node control transistor and the second pull-down node control transistor are turned off, The second voltage input from the second voltage terminal is greater than the first voltage input from the first voltage terminal, and the third voltage input from the third voltage terminal is greater than the first voltage.
  • the present disclosure also provides a shift register unit, including a pull-up node control circuit, a pull-down node control circuit, a bias control circuit, a storage capacitor, a gate drive signal output terminal, a gate drive signal output circuit, and a carry signal output circuit And carry signal output terminal; among them,
  • the pull-up node control circuit includes a first pull-up node control transistor, a second pull-up node control transistor, a third pull-up node control transistor, a fourth pull-up node control transistor, and a fifth pull-up node control transistor;
  • the gate and drain of the first pull-up node control transistor are electrically connected to the input terminal, and the source of the first pull-up node control transistor is electrically connected to the pull-up node;
  • the gate of the second pull-up node control transistor is electrically connected to the reset terminal, the drain of the second pull-up node control transistor is electrically connected to the pull-up node, and the second pull-up node controls the source of the transistor.
  • the pole is electrically connected to the first voltage terminal;
  • the gate of the third pull-up node control transistor is electrically connected to the start signal terminal, the drain of the third pull-up node control transistor is electrically connected to the pull-up node, and the third pull-up node controls the transistor
  • the source of is electrically connected to the first voltage terminal;
  • the gate of the fourth pull-up node control transistor is electrically connected to the first pull-down node
  • the drain of the fourth pull-up node control transistor is electrically connected to the pull-up node
  • the fourth pull-up node controls The source of the transistor is electrically connected to the first voltage terminal
  • the gate of the fifth pull-up node control transistor is electrically connected to the second pull-down node, the drain of the fifth pull-up node control transistor is electrically connected to the pull-up node, and the fifth pull-up node controls the transistor
  • the source of is electrically connected to the first voltage terminal;
  • a first end of the storage capacitor is electrically connected to the pull-up node, and a second end of the storage capacitor is electrically connected to the gate drive signal output end;
  • the pull-down node control circuit includes a first pull-down control node control transistor, a second pull-down control node control transistor, a first pull-down control transistor, a third pull-down control node control transistor, a fourth pull-down control node control transistor, and a second pull-down control node Control transistor
  • the control electrode of the first pull-down control node control transistor and the first electrode of the first pull-down control node control transistor are electrically connected to the first power supply voltage terminal, and the first pull-down control node controls the second terminal of the transistor. Pole is electrically connected to the first pull-down control node;
  • the control electrode of the second pull-down control node control transistor is electrically connected to the pull-up node
  • the first electrode of the second pull-down control node control transistor is electrically connected to the first pull-down control node
  • the second pull-down control node The second pole of the control transistor is electrically connected to the first voltage terminal by the pull-down control node
  • the control electrode of the first pull-down control transistor is electrically connected to the first pull-down control node, the first electrode of the first pull-down control transistor is electrically connected to the first power supply voltage terminal, and the first pull-down control transistor The second electrode of the control transistor is electrically connected to the first pull-down node;
  • control electrode of the third pull-down control node control transistor and the first electrode of the third pull-down control node control transistor are electrically connected to the second power supply voltage terminal, and the third pull-down control node controls the second electrode of the transistor and the The second pull-down control node is electrically connected;
  • the control electrode of the fourth pull-down control node control transistor is electrically connected to the pull-up node
  • the first electrode of the fourth pull-down control node control transistor is electrically connected to the second pull-down control node
  • the fourth pull-down control node The second pole of the control node control transistor is electrically connected to the first voltage terminal
  • the control electrode of the second pull-down control transistor is electrically connected to the second pull-down control node, the first electrode of the second pull-down control transistor is electrically connected to the second power supply voltage terminal, and the first electrode of the second pull-down control transistor is electrically connected.
  • the two poles are electrically connected to the second pull-down node;
  • the bias control circuit includes a first bias control transistor and a second bias control transistor
  • the control electrode of the first bias control transistor is electrically connected to the first pull-down control node, the first electrode of the first bias control transistor is electrically connected to the pull-up node, and the first bias The second pole of the control transistor is electrically connected to the second voltage terminal;
  • the control electrode of the second bias control transistor is electrically connected to the second pull-down control node, the first electrode of the second bias control transistor is electrically connected to the pull-up node, and the second bias control The second pole of the transistor is electrically connected to the third voltage terminal;
  • the gate drive signal output circuit includes a first gate drive signal output transistor, a second gate drive signal output transistor, and a third gate drive signal output transistor,
  • the gate of the first gate drive signal output transistor is electrically connected to the pull-up node, the drain of the first gate drive signal output transistor is electrically connected to the clock signal terminal, and the first gate drive signal The source of the output transistor is electrically connected to the gate drive signal output terminal;
  • the gate of the second gate drive signal output transistor is electrically connected to the first pull-down node, and the drain of the second gate drive signal output transistor is electrically connected to the gate drive signal output terminal, so The source of the second gate drive signal output transistor is electrically connected to the first voltage terminal;
  • the gate of the third gate drive signal output transistor is electrically connected to the second pull-down node, the drain of the third gate drive signal output transistor is electrically connected to the gate drive signal output terminal, and the The source of the third gate drive signal output transistor is electrically connected to the first voltage terminal;
  • the carry signal output circuit includes a first carry signal output transistor, a second carry signal output transistor, and a third carry signal output transistor,
  • the gate of the first carry signal output transistor is electrically connected to the pull-up node, the drain of the first carry signal output transistor is electrically connected to the clock signal terminal, and the source of the first carry signal output transistor Pole is electrically connected with the carry signal output terminal;
  • the gate of the second carry signal output transistor is electrically connected to the first pull-down node, the drain of the second carry signal output transistor is electrically connected to the carry signal output terminal, and the second carry signal output The source of the transistor is electrically connected to the first voltage terminal;
  • the gate of the third carry signal output transistor is electrically connected to the second pull-down node, the drain of the third carry signal output transistor is electrically connected to the carry signal output terminal, and the third carry signal output transistor The source of is electrically connected to the first voltage terminal.
  • the present disclosure also provides a driving method, which is applied to the above-mentioned shift register unit, and the driving method includes:
  • the pull-down node control circuit controls the pull-down node to disconnect from the first voltage terminal under the control of the potential of the pull-up node; the bias control circuit controls the pull-up node Potential to control the gate-source voltage of the pull-down node control transistor included in the pull-down node control circuit to be within a predetermined voltage range.
  • the pull-down node control transistor is an n-type transistor, and the predetermined voltage range is less than zero.
  • the pull-down node control transistor is a p-type transistor, and the predetermined voltage range is greater than zero.
  • the present disclosure also provides a gate driving circuit, which includes multiple stages of the above-mentioned shift register units.
  • the present disclosure also provides a display device including the above-mentioned gate drive circuit.
  • Figure 1 is a structural diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 2 is a structural diagram of a shift register unit according to another embodiment of the present disclosure.
  • FIG. 3 is a structural diagram of a shift register unit according to another embodiment of the present disclosure.
  • FIG. 4 is a structural diagram of a shift register unit according to another embodiment of the present disclosure.
  • FIG. 5 is a structural diagram of a shift register unit according to another embodiment of the present disclosure.
  • FIG. 6 is a circuit diagram of a specific embodiment of the shift register unit according to the present disclosure.
  • FIG. 7 is a working timing diagram of the specific embodiment of the shift register unit according to the present disclosure.
  • the transistors used in all the embodiments of the present disclosure may be triodes, thin film transistors or field effect transistors or other devices with the same characteristics.
  • one of the poles is called the first pole and the other pole is called the second pole.
  • the control electrode when the transistor is a triode, can be a base, the first electrode can be a collector, and the second electrode can be an emitter; or, the control electrode can be a base.
  • the first electrode may be an emitter electrode, and the second electrode may be a collector electrode.
  • the control electrode when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate, the first electrode may be a drain, and the second electrode may be a source; or The control electrode may be a gate, the first electrode may be a source, and the second electrode may be a drain.
  • the problem of abnormal lighting display occurred one after another.
  • the threshold voltage of the pull-down node control transistor included in the pull-down node control circuit in the shift register unit will gradually shift in the positive direction, so that the on-state current Ion of the pull-down node control transistor decreases.
  • the competition relationship between the pull-up node and the pull-down node is abnormal, so that the potential of the pull-up node cannot be reset during the reset phase, and the screen display is abnormal.
  • the present disclosure provides a shift register unit, a driving method, a gate driving circuit, and a display device to solve the threshold value of the pull-down node control transistor included in the pull-down node control circuit in the shift register unit in the related art A serious problem with voltage drift.
  • the shift register unit includes a pull-down node control circuit 11 and a bias control circuit 12, wherein,
  • the control end of the pull-down node control circuit 11 is electrically connected to the pull-up node PU, the first end of the pull-down node control circuit 11 is electrically connected to the pull-down node PD, and the second end of the pull-down node control circuit 11 is electrically connected to the first
  • the voltage terminal VT1 is electrically connected, and the pull-down node control circuit 11 is configured to control the connection or disconnection between the pull-down node PD and the first voltage terminal VT1 under the control of the potential of the pull-up node PU;
  • the bias control circuit 12 is electrically connected to the pull-up node PU, and is used to control the disconnection between the pull-down node PD and the first voltage terminal VT1 by the pull-down node control circuit 11
  • the potential of the node PU is pulled up to control the gate-source voltage of the pull-down node control transistor included in the pull-down node control circuit 11 to be within a predetermined voltage range, so that the pull-down node control transistor is in a reverse bias state.
  • the first voltage terminal VT1 may be the first low voltage terminal, but is not limited to this.
  • the display period includes an input phase, an output phase, a reset phase, and an output cut-off hold phase that are sequentially set;
  • the pull-down node control circuit 11 controls the connection between the pull-down node PD and the first voltage terminal VT1 under the control of the potential of the pull-up node PU;
  • the pull-down node control circuit 11 controls the pull-down node PD to disconnect from the first voltage terminal VT1 under the control of the potential of the pull-up node PU; the bias control circuit 12 controls all The potential of the pull-up node PU is used to control the gate-source voltage of the pull-down node control transistor included in the pull-down node control circuit 11 to be within a predetermined voltage range, so that the pull-down node control transistor is in a reverse bias state.
  • the pull-down node control transistor is an n-type transistor, and the predetermined voltage range is less than 0; or,
  • the pull-down node control transistor is a p-type transistor, and the predetermined voltage range is greater than zero.
  • the pull-down node control circuit may include a pull-down node control transistor
  • the control electrode of the pull-down node control transistor is electrically connected to the pull-up node
  • the first electrode of the pull-down node control transistor is electrically connected to the pull-down node
  • the second electrode of the pull-down node controls the transistor and the first voltage Terminal electrical connection
  • the bias control circuit includes a bias control transistor
  • the control electrode of the bias control transistor is electrically connected to the bias control terminal, the first electrode of the bias control transistor is electrically connected to the pull-up node, and the second electrode of the bias control transistor is electrically connected to a second voltage Terminal electrical connection;
  • the bias control terminal is used to provide a bias control signal, so that when the pull-down node control transistor is turned off, the bias control transistor is controlled to be turned on.
  • the second voltage terminal may be a second low voltage terminal, but is not limited to this.
  • the pull-down node control circuit may only include one pull-down node control transistor, and the shift register unit described in the embodiment of the present disclosure may only use one pull-down node, but it is not limited to this.
  • the pull-down node control transistor is an n-type transistor, and when the pull-down node control transistor is turned off, the second voltage is less than the first voltage; or, the pull-down node control transistor is a p-type transistor. When the pull-down node controls the transistor to be turned off, the second voltage is greater than the first voltage;
  • the first voltage terminal is used to input the first voltage
  • the second voltage terminal is used to input the second voltage
  • the pull-down node control circuit 11 may include a pull-down node control transistor MDC1;
  • the gate of the pull-down node control transistor MDC1 is electrically connected to the pull-up node PU, the drain of the pull-down node control transistor MDC1 is electrically connected to the pull-down node PD, and the source of the pull-down node control transistor MDC1 is electrically connected to
  • the first low voltage terminal is electrically connected; the first low voltage terminal is used to input the first low voltage LVGL;
  • the bias control circuit 12 may include a bias control transistor MBC1;
  • the gate of the bias control transistor MBC1 is electrically connected to the bias control terminal BCtrl, the drain of the bias control transistor MBC1 is electrically connected to the pull-up node PU, and the source of the bias control transistor MBC1 is electrically connected to the
  • the second low voltage terminal is electrically connected; the second low voltage terminal is used to input the second low voltage VGL2;
  • the bias control terminal BCtrl is used to provide a bias control signal, so that when the pull-down node control transistor MDC1 is turned off, the bias control transistor MBC1 is controlled to be turned on.
  • both MDC1 and MBC1 are NMOS transistors (N-type metal-oxide-semiconductor field effect transistors), but not limited to this.
  • VGL2 is less than LVGL
  • the gate-source voltage of MDC1 is less than zero. Since the threshold voltage of the pull-down node control transistor in the related art gradually shifts in the positive direction, and the gate-source voltage of the MDC1 in this application is less than 0, the threshold voltage deviation of the MDC1 can be reduced.
  • the potential of PU is high, MDC1 is turned on, the gate-source voltage of MDC1 is greater than 0, and the threshold voltage of MDC1 is positively shifted; the bias control signal input by BCtrl is low and MBC1 is turned off ;
  • the potential of PU is low, the bias control signal is high, MBC1 is turned on, PU is connected to VGL2, that is, the gate of MDC1 is connected to VGL2 and the source of MDC1 If the pole is connected to LVGL, the gate-source voltage of MDC1 is less than 0, and the threshold voltage of MDC1 shifts negatively.
  • the threshold voltage of MDC1 tends to a stable state under the interaction of positive and negative gate-source voltage biases.
  • the gate-source voltage of MDC1 is less than 0 during the input and output stages, and it is necessary to control the gate-source voltage of MDC1 to be greater than 0 during the reset stage and the output cut-off hold stage. In order to make the threshold voltage of MDC1 stable.
  • the bias control voltage terminal may be a pull-down control node
  • the pull-down node control circuit further includes a pull-down control node control circuit and a pull-down control transistor;
  • the pull-down control node control circuit is configured to control the potential of the pull-down control node under the control of the potential of the pull-up node;
  • the control electrode of the pull-down control transistor is electrically connected to the pull-down control node
  • the first electrode of the pull-down control transistor is electrically connected to the power supply voltage terminal
  • the second electrode of the pull-down control transistor is electrically connected to the pull-down node.
  • the bias control voltage terminal is a pull-down control node PDCN;
  • the pull-down node control circuit 11 also includes a pull-down control node control circuit 30 and a pull-down control transistor MDC2;
  • the pull-down control node control circuit 30 is configured to control the potential of the pull-down control node PDCN under the control of the potential of the pull-up node PU;
  • the gate of the pull-down control transistor MDC2 is electrically connected to the pull-down control node PDCN, the drain of the pull-down control transistor MDC2 is electrically connected to the power supply voltage terminal, and the source of the pull-down control transistor MDC2 is electrically connected to the pull-down node PD. Electrical connection
  • the power supply voltage terminal is used to input the power supply voltage VDD.
  • MDC2 is an NMOS transistor, but it is not limited to this.
  • MDC1 and MDC2 together control the potential of PD, and the pull-down control node control circuit 30 controls the potential of PDCN.
  • the pull-down control node control circuit 30 may include a first control transistor and a second control transistor;
  • control electrode of the first control transistor and the first electrode of the first control transistor are electrically connected to the power supply voltage terminal, and the second electrode of the first control transistor is electrically connected to the pull-down control node;
  • the control electrode of the second control transistor is electrically connected to the pull-up node, the first electrode of the second control transistor is electrically connected to the pull-down control node, and the second electrode of the second control transistor is electrically connected to the first The voltage terminal is electrically connected.
  • the shift register unit described in the embodiment of the present disclosure may further include a pull-up node control circuit, a storage capacitor, and a carry signal. Output terminal, gate drive signal output terminal, gate drive signal output circuit and carry signal output circuit;
  • the pull-up node control circuit may be electrically connected to the input terminal, the start signal terminal and the reset terminal, the pull-down node and the pull-up node, and is used for the input signal provided at the input terminal, the start signal provided by the start signal terminal, and the reset Control the potential of the pull-up node under the control of the reset signal provided by the terminal and the potential of the pull-down node;
  • the first end of the storage capacitor may be electrically connected to the pull-up node, and the second end of the storage capacitor may be electrically connected to the gate drive signal output end;
  • the gate drive signal output circuit is electrically connected to the pull-up node, the pull-down node, the gate drive signal output terminal, the clock signal terminal, and the first voltage terminal, respectively, for controlling under the control of the potential of the pull-up node Communicating between the gate driving signal output terminal and the clock signal terminal, and controlling the communication between the gate driving signal output terminal and the first voltage terminal under the control of the potential of the pull-down node;
  • the carry signal output circuit is electrically connected to the pull-up node, the pull-down node, the carry signal output terminal, the clock signal terminal, and the first voltage terminal, respectively, for controlling the carry signal under the control of the potential of the pull-up node
  • the output terminal is connected to the clock signal terminal, and the connection between the carry signal output terminal and the first voltage terminal is controlled under the control of the potential of the pull-down node;
  • the gate drive signal output from the gate drive signal output terminal is used to drive the corresponding row of gate lines, and the carry signal output from the carry signal output terminal is used to provide input signals to the adjacent next-stage shift register units and to The adjacent upper stage shift register unit provides a reset signal.
  • the pull-down node may include a first pull-down node and a second pull-down node;
  • the pull-down node control circuit may include a first pull-down node control transistor and a second pull-down node control transistor;
  • the control electrode of the first pull-down node control transistor is electrically connected to the pull-up node, the first electrode of the first pull-down node control transistor is electrically connected to the first pull-down node, and the first pull-down node
  • the second pole of the pull node control transistor is electrically connected to the first voltage terminal
  • the control electrode of the second pull-down node control transistor is electrically connected to the pull-up node
  • the first electrode of the second pull-down node control transistor is electrically connected to the second pull-down node
  • the second pull-down node controls the transistor
  • the second pole of is electrically connected to the first voltage terminal
  • the bias control circuit includes a first bias control transistor and a second bias control transistor
  • the control electrode of the first bias control transistor is electrically connected to the first bias control terminal, the first electrode of the first bias control transistor is electrically connected to the pull-up node, and the first bias control transistor
  • the second pole of is electrically connected to the second voltage terminal;
  • the control electrode of the second bias control transistor is electrically connected to the second bias control terminal, the first electrode of the second bias control transistor is electrically connected to the pull-up node, and the second bias control transistor The second pole of is electrically connected to the third voltage terminal;
  • the first bias control terminal is used to provide a first bias control signal, so that when the first pull-down node control transistor and the second pull-down node control transistor are turned off, the first bias is controlled
  • the control transistor is turned on;
  • the second bias control terminal is used to provide a second bias control signal, so that when the first pull-down node control transistor and the second pull-down node control transistor are turned off, the second bias is controlled The control transistor is turned on.
  • the shift register unit described in the embodiment of the present disclosure may use two pull-down nodes, the pull-down node control circuit may include two pull-down node control transistors, and the bias control circuit may include two biases. Control transistors, but not limited to this.
  • the first voltage terminal may be a first low voltage terminal
  • the second voltage terminal and the third voltage terminal may be a second low voltage terminal, but not limited to this.
  • the first pull-down node control transistor and the second pull-down node control transistor are n-type transistors, and when the first pull-down node control transistor and the second pull-down node control transistor are turned off , The second voltage is less than the first voltage, and the third voltage is less than the first voltage; or, the first pull-down node control transistor and the second pull-down node control transistor are p-type transistors, and the first pull-down node When the control transistor and the second pull-down node control transistor are turned off, the second voltage is greater than the first voltage, and the third voltage is greater than the first voltage;
  • the first voltage terminal is used to input the first voltage
  • the second voltage terminal is used to input the second voltage
  • the third voltage terminal is used to input the third voltage
  • the pull-down node may include a first pull-down node PD1 and a second pull-down node PD2;
  • the pull-down node control circuit 11 may include a first pull-down node control transistor M6 and a second pull-down node control transistor M6';
  • the gate of the first pull-down node control transistor M6 is electrically connected to the pull-up node PU, the drain of the first pull-down node control transistor M6 is electrically connected to the first pull-down node PD1, and the The source of the first pull-down node control transistor M6 is electrically connected to the first low voltage terminal; the first low voltage terminal is used to input the first low voltage LVGL;
  • the gate of the second pull-down node control transistor M6' is electrically connected to the pull-up node PU, the drain of the second pull-down node control transistor M6' is electrically connected to the second pull-down node PD2, and the The source of the second pull-down node control transistor M6' is electrically connected to the first low voltage terminal;
  • the bias control circuit 12 includes a first bias control transistor M14 and a second bias control transistor M14;
  • the gate of the first bias control transistor M14 is electrically connected to the first bias control terminal BCtrl1, the drain of the first bias control transistor M14 is electrically connected to the pull-up node PU, and the first bias control transistor M14 is electrically connected to the pull-up node PU.
  • the source of the control transistor M14 is electrically connected to the second low voltage terminal; the second low voltage terminal is used to provide the second low voltage VGL2;
  • the gate of the second bias control transistor M14' is electrically connected to the second bias control terminal BCtrl2, the drain of the second bias control transistor M14' is electrically connected to the pull-up node PU, and the first The source of the second bias control transistor M14' is electrically connected to the second low voltage terminal;
  • the first bias control terminal BCtrl1 is used to provide a first bias control signal, so that when the first pull-down node control transistor M6 and the second pull-down node control transistor M6' are turned off, the control The first bias control transistor M14 is turned on;
  • the second bias control terminal BCtrl2 is used to provide a second bias control signal, so that when the first pull-down node control transistor M6 and the second pull-down node control transistor M6' are turned off, the control The second bias control transistor M14' is turned on.
  • M6, M6', M14, and M14' are all NMOS transistors (N-type metal-oxide-semiconductor field effect transistors), but not limited to this.
  • VGL2 is less than LVGL
  • the gate-source voltage of M6 is less than 0, so that the threshold voltage offset of M6 can be reduced
  • the threshold voltage of M6' The gate-source voltage is less than 0, so that the threshold voltage shift of M6' can be reduced.
  • M6 and M6' work alternately, and correspondingly, M14 and M14' also work alternately. That is, when M6 works, correspondingly, M14 also works. At this time, M6' and M14' do not work; when M6 does not work, M14 does not work accordingly. At this time, M6' and M14' work.
  • the potential of PU is high, M6 or M6' is turned on, the gate-source voltage of M6 or M6' is greater than 0, and the threshold voltage of M6 or M6' is negatively shifted ;
  • the first bias control signal input by BCtrl1 or the second bias control signal input by BCtrl2 is low, and M14 or M14' is off;
  • the potential of PU is low, the first bias control signal or the second bias control signal is high, M14 or M14' is turned on, and PU is connected to VGL2 , That is, the gate of M6 or M6' is connected to VGL2, the source of M6 or M6' is connected to LVGL, then the gate-source voltage of M6 or M6' is less than 0, the threshold of M6 The voltage or threshold voltage of M6' shifts in the reverse direction.
  • the threshold voltage of M6 and the threshold voltage of M6' tend to be stable under the interaction of positive and negative gate-source voltage biases of M6 and M6'.
  • the gate-source voltage of M6 and the gate-source voltage of M6' are less than 0, and it needs to be in the reset stage and the output cut-off hold stage , Controlling the gate-source voltage of M6 and the gate-source voltage of M6' to be greater than 0, so that the threshold voltage of M6 and the threshold voltage of M6' are stable.
  • the first bias control voltage terminal may be a first pull-down control node
  • the second bias control voltage terminal may be a second pull-down control node
  • the pull-down node control circuit may further include a first pull-down control node control circuit, a first pull-down control transistor, a second pull-down control node control circuit, and a second pull-down control transistor;
  • the first pull-down control node control circuit is configured to control the potential of the first pull-down control node under the control of the potential of the pull-up node;
  • the control electrode of the first pull-down control transistor is electrically connected to the first pull-down control node, the first electrode of the first pull-down control transistor is electrically connected to the first power supply voltage terminal, and the first pull-down control transistor The second electrode of the control transistor is electrically connected to the first pull-down node;
  • the second pull-down control node control circuit is configured to control the potential of the second pull-down control node under the control of the potential of the pull-up node;
  • the control electrode of the second pull-down control transistor is electrically connected to the second pull-down control node
  • the first electrode of the second pull-down control transistor is electrically connected to the second power supply voltage terminal
  • the first electrode of the second pull-down control transistor is electrically connected.
  • the two poles are electrically connected to the second pull-down node.
  • the first bias control voltage terminal is a first pull-down control node PDCN1, and the second bias control voltage terminal Is the second pull-down control node PDCN2;
  • the pull-down node control circuit 11 may also include a first pull-down control node control circuit 301, a first pull-down control transistor M5, a second pull-down control node control circuit 302, and a second pull-down control transistor M5';
  • the first pull-down control node control circuit 301 is electrically connected to the pull-up node PU and the first pull-down control node PDCN1, respectively, and is configured to control the first pull-down node under the control of the potential of the pull-up node PU. Control the potential of the node PDCN1;
  • the gate of the first pull-down control transistor M5 is electrically connected to the first pull-down control node PDCN1, the drain of the first pull-down control transistor M5 is electrically connected to the first power voltage terminal, and the first The source of the pull-down control transistor M5 is electrically connected to the first pull-down node PD1;
  • the second pull-down control node control circuit 302 is electrically connected to the pull-up node PU and the second pull-down control node PDCN2, respectively, and is configured to control the second pull-down control under the control of the potential of the pull-up node PU.
  • the gate of the second pull-down control transistor M5' is electrically connected to the second pull-down control node PDCN2, the drain of the second pull-down control transistor M5' is electrically connected to the second power supply voltage terminal, and the second pull-down control transistor M5' The source of the control transistor M5' is electrically connected to the second pull-down node PD2;
  • the first power supply voltage terminal is used for inputting a first power supply voltage VDD1
  • the second power supply voltage terminal is used for inputting a second power supply voltage VDD2.
  • M5 and M5' are NMOS transistors, but not limited to this.
  • M6 and M5 together control the potential of PD1
  • the first pull-down control node control circuit 301 controls the potential of PDCN1
  • M6' and M5' together control PD2
  • the second pull-down control node control circuit 302 controls the potential of PDCN2.
  • the first pull-down control node control circuit includes a first pull-down control node control transistor M9 and a second pull-down control node control transistor M8;
  • the second pull-down control node control circuit includes a third pull-down control node control transistor M9' and a fourth pull-down control node control transistor M8';
  • the control electrode of the first pull-down control node control transistor M9 and the first electrode of the first pull-down control node control transistor M9 are electrically connected to the first power supply voltage terminal VDD1, and the first pull-down control node control transistor
  • the second pole of M9 is electrically connected to the first pull-down control node PDCN1;
  • the control electrode of the second pull-down control node control transistor M8 is electrically connected to the pull-up node PU, and the first electrode of the second pull-down control node control transistor M8 is electrically connected to the first pull-down control node, so The second pull-down control node controls the second pole of the transistor M8 to be electrically connected to the first voltage terminal;
  • the control electrode of the third pull-down control node control transistor M9' and the first electrode of the third pull-down control node control transistor M9' are electrically connected to the second power supply voltage terminal VDD2, and the third pull-down control node control transistor M9
  • the second pole of ' is electrically connected to the second pull-down control node PDCN2;
  • the control electrode of the fourth pull-down control node control transistor M8' is electrically connected to the pull-up node PU, and the first electrode of the fourth pull-down control node control transistor M8' is electrically connected to the second pull-down control node PDCN2 , The second pole of the fourth pull-down control node control transistor M8' is electrically connected to the first voltage terminal.
  • the specific embodiment of the shift register unit described in the present disclosure further includes a pull-up node control circuit, a storage capacitor C1, a gate drive signal output terminal G_out, a gate drive signal output circuit, a carry signal output terminal Out_c, and a carry signal.
  • Signal output circuit ;
  • the pull-up node control circuit includes a first pull-up node control transistor M1, a second pull-up node control transistor M2, a third pull-up node control transistor M0, a fourth pull-up node control transistor M10', and a fifth pull-up node Control transistor M10, where
  • the gate and drain of M1 are electrically connected to the input terminal Input, and the source of M1 is electrically connected to the pull-up node PU;
  • the gate of M2 is electrically connected to the reset terminal Reset_PU, the drain of M2 is electrically connected to PU, and the source of M2 is electrically connected to the first low voltage terminal; the first low voltage terminal is used to input the first low voltage LVGL;
  • the gate of M0 is electrically connected to the start signal terminal STV, the drain of M0 is electrically connected to PU, and the source of M0 is electrically connected to the first low voltage terminal;
  • the gate of M10' is electrically connected to the first pull-down node PD1, the drain of M10' is electrically connected to PU, and the source of M10' is electrically connected to the first low voltage terminal;
  • the gate of M10 is electrically connected to the second pull-down node PD2, the drain of M10 is electrically connected to PU, and the source of M10 is electrically connected to the first low voltage terminal;
  • the first end of C1 is electrically connected to PU, and the second end of C1 is electrically connected to G_out;
  • the gate drive signal output circuit includes a first gate drive signal output transistor M3, a second gate drive signal output transistor M11, and a third gate drive signal output transistor M11', wherein,
  • the gate of M3 is electrically connected to PU, the drain of M3 is connected to the clock signal CLK, and the source of M3 is electrically connected to G_out;
  • the gate of M11 is electrically connected to PD1, the drain of M11 is electrically connected to G_out, and the source of M11 is connected to LVGL;
  • the gate of M11’ is electrically connected to PD2, the drain of M11’ is electrically connected to G_out, and the source of M11’ is connected to LVGL;
  • the carry signal output circuit includes a first carry signal output transistor M13, a second carry signal output transistor M12, and a third carry signal output transistor M12', wherein,
  • the gate of M13 is electrically connected to PU, the drain of M13 is connected to the clock signal CLK, and the source of M3 is electrically connected to Out_c;
  • the gate of M12 is electrically connected to PD1, the drain of M12 is electrically connected to Out_c, and the source of M12 is connected to LVGL;
  • the gate of M12' is electrically connected to PD2, the drain of M12' is electrically connected to Out_c, and the source of M12' is connected to LVGL.
  • all the transistors are NMOS transistors, but not limited to this.
  • the display period includes an input phase t1, an output phase t2, a reset phase t3, and an output cut-off holding phase t4 that are sequentially set;
  • Display period VDD1 is high level, VDD2 is low level; among them, M9, M5, M8 and M6 work alternately with M9', M5', M8' and M6', VDD1 is high level, VDD2 is When low level, M9, M5, M8 and M6 work, M9', M5', M8' and M6' do not work; when VDD1 is low level and VDD2 is high level, M9', M5', M8' and M6' Works, M9, M5, M8 and M6 do not work. Correspondingly, M14 and M14' also work alternately.
  • the potential of PU is about 30V
  • LVGL is -8V
  • VGL2 is -8V
  • M6 is on
  • PD1 is low
  • M8 is on
  • PDCN1 low
  • M14 is off
  • M6 is off.
  • the gate-source voltage is about 38V;
  • the potential of PU is about 45V, LVGL is -8V, VGL2 is -8V, M6 is on, PD1 is low, M8 is on, PDCN1 is low, M14 is off, and the gate source of M6 is The voltage is about 53V;
  • the potential of PU is low
  • the potential of PD1 is about 28V
  • the potential of LVGL is -8V
  • VGL2 is -15V
  • M6 is off
  • the potential of PDCN1 is high
  • M5 Turn on
  • M14 turns on, so that the gate of M6 is connected to -15V
  • the gate-source voltage of M6 is -7V.
  • the M6 is on for a short period of time in one display period, that is, M6 is in the high gate-source voltage (Vgs) state of 38V-53V for a short time in one display period; the M6 is on for a long time in one display period. That is, within one display period, M6 is in the negative Vgs state of -7V for a long time, so that under the interaction of the positive and negative gate-source voltage bias of M6, the threshold voltage of M6 tends to a stable state.
  • Vgs gate-source voltage
  • the threshold voltage of M6 shifts in the positive direction during the input phase t1 and the output phase t2, and the threshold voltage of M6 reverses during the reset phase t3 and the output cut-off holding phase t4. To drift, which can make the threshold voltage of M6 tend to a stable state.
  • VDD1 is at a low level and VDD2 is at a high level
  • the working process of the shift register unit shown in FIG. 6 can be specifically referred to the foregoing description process, which will not be repeated here.
  • the display time includes a plurality of display time periods, and each display time period includes a first display time period and a second display time period set in sequence;
  • VDD1 is at a high level, and VDD2 is at a low level;
  • VDD1 is at low level and VDD2 is at high level;
  • the first display period may include at least one display period
  • the second display period may include at least one display period
  • the potential of CLK when CLK is at a low level, the potential of CLK may be -8V, and when CLK is at a high level, the potential of CLK may be 32V, but it is not limited to this.
  • the driving method according to the embodiment of the present disclosure is applied to the above-mentioned shift register unit, and the driving method includes:
  • the pull-down node control circuit controls the pull-down node to disconnect from the first voltage terminal under the control of the potential of the pull-up node; the bias control circuit controls the pull-up node Potential to control the gate-source voltage of the pull-down node control transistor included in the pull-down node control circuit to be within a predetermined voltage range.
  • the pull-down node control transistor may be an n-type transistor, and the predetermined voltage range is less than 0; or,
  • the pull-down node control transistor may be a p-type transistor, and the predetermined voltage range is greater than zero.
  • the gate driving circuit according to the embodiment of the present disclosure includes multiple stages of the above-mentioned shift register units.
  • the display device includes the above-mentioned gate driving circuit.
  • the display device may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种移位寄存器单元、驱动方法、栅极驱动电路和显示装置。移位寄存器单元包括下拉节点控制电路（11）和偏置控制电路（12），下拉节点控制电路（11）用于在上拉节点（PU）的电位的控制下，控制下拉节点（PD）与第一电压端（VT1）之间连通或断开；偏置控制电路（12）用于在下拉节点控制电路（11）控制下拉节点（PD）与第一电压端（VT1）之间断开时，通过控制上拉节点（PU）的电位，以控制下拉节点控制电路（11）包括的下拉节点控制晶体管（MDC1）的栅源电压（Vgs）处于预定电压范围内。

Description

移位寄存器单元、驱动方法、栅极驱动电路和显示装置
相关申请的交叉引用
本申请主张在2019年6月18日在中国提交的中国专利申请号No.201910528404.0的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示驱动技术领域，尤其涉及一种移位寄存器单元、驱动方法、栅极驱动电路和显示装置。
背景技术
在数字电路中，用来存放二进制数据或代码的电路称为寄存器。寄存器是由具有存储功能的触发器组合起来构成的。一个触发器可以存储一位二进制代码，存放N位二进制代码的寄存器，需用n个触发器来构成。按功能可分为：基本寄存器和移位寄存器。移位寄存器中的数据可以在移位脉冲作用下依次逐位右移或左移，数据既可以并行输入、并行输出，也可以串行输入、串行输出，还可以并行输入、串行输出，串行输入、并行输出，十分灵活，用途也很广。
发明内容
本公开提供了一种移位寄存器单元，包括下拉节点控制电路和偏置控制电路，其中，
所述下拉节点控制电路的控制端与上拉节点电连接，所述下拉节点控制电路的第一端与下拉节点电连接，所述下拉节点控制电路的第二端与第一电压端电连接，所述下拉节点控制电路用于在上拉节点的电位的控制下，控制所述下拉节点与所述第一电压端之间连通或断开；
所述偏置控制电路与所述上拉节点电连接，用于在所述下拉节点控制电路控制所述下拉节点与所述第一电压端之间断开时，通过控制所述上拉节点的电位，以控制所述下拉节点控制电路包括的下拉节点控制晶体管的栅源电 压处于预定电压范围内。
实施时，所述下拉节点控制晶体管为n型晶体管，所述预定电压范围为小于0。
实施时，所述下拉节点控制晶体管为p型晶体管，所述预定电压范围为大于0。
实施时，所述下拉节点控制电路包括一个下拉节点控制晶体管；
所述下拉节点控制晶体管的控制极与所述上拉节点电连接，所述下拉节点控制晶体管的第一极与所述下拉节点电连接，所述下拉节点控制晶体管的第二极与第一电压端电连接。
实施时，所述偏置控制电路包括偏置控制晶体管；
所述偏置控制晶体管的控制极与偏置控制端电连接，所述偏置控制晶体管的第一极与所述上拉节点电连接，所述偏置控制晶体管的第二极与第二电压端电连接；
所述偏置控制端用于提供偏置控制信号，以使得在所述下拉节点控制晶体管关断时，控制所述偏置控制晶体管导通。
实施时，所述偏置控制电压端为下拉控制节点；
所述下拉节点控制电路还包括下拉控制节点控制电路和下拉控制晶体管；
所述下拉控制节点控制电路用于在所述上拉节点的电位的控制下，控制所述下拉控制节点的电位；
所述下拉控制晶体管的控制极与所述下拉控制节点电连接，所述下拉控制晶体管的第一极与电源电压端电连接，所述下拉控制晶体管的第二极与所述下拉节点电连接。
实施时，所述下拉节点控制晶体管为n型晶体管，在所述下拉节点控制晶体管关断时，所述第二电压端输入的第二电压小于所述第一电压端输入的第一电压。
实施时，所述下拉节点控制晶体管为p型晶体管，在所述下拉节点控制晶体管关断时，所述第二电压端输入的第二电压大于所述第一电压端输入的第一电压。
实施时，所述下拉节点包括第一下拉节点和第二下拉节点；所述下拉节 点控制电路包括第一下拉节点控制晶体管和第二下拉节点控制晶体管；
所述第一下拉节点控制晶体管的控制极与所述上拉节点电连接，所述第一下拉节点控制晶体管的第一极与所述第一下拉节点电连接，所述第一下拉节点控制晶体管的第二极与第一电压端电连接；
所述第二下拉节点控制晶体管的控制极与所述上拉节点电连接，所述第二下拉节点控制晶体管的第一极与所述第二下拉节点电连接，所述第二下拉节点控制晶体管的第二极与第一电压端电连接。
实施时，所述偏置控制电路包括第一偏置控制晶体管和第二偏置控制晶体管；
所述第一偏置控制晶体管的控制极与第一偏置控制端电连接，所述第一偏置控制晶体管的第一极与所述上拉节点电连接，所述第一偏置控制晶体管的第二极与第二电压端电连接；
所述第二偏置控制晶体管的控制极与第二偏置控制端电连接，所述第二偏置控制晶体管的第一极与所述上拉节点电连接，所述第二偏置控制晶体管的第二极与第三电压端电连接；
所述第一偏置控制端用于提供第一偏置控制信号，以使得所述第一下拉节点控制晶体管和所述第二下拉节点控制晶体管关断时，控制所述第一偏置控制晶体管导通；
所述第二偏置控制端用于提供第二偏置控制信号，以使得所述第一下拉节点控制晶体管和所述第二下拉节点控制晶体管关断时，控制所述第二偏置控制晶体管导通。
实施时，所述第一偏置控制电压端为第一下拉控制节点，所述第二偏置控制电压端为第二下拉控制节点；
所述下拉节点控制电路还包括第一下拉控制节点控制电路、第一下拉控制晶体管、第二下拉控制节点控制电路和第二下拉控制晶体管；
所述第一下拉控制节点控制电路用于在所述上拉节点的电位的控制下，控制所述第一下拉控制节点的电位；
所述第一下拉控制晶体管的控制极与所述第一下拉控制节点电连接，所述第一下拉控制晶体管的第一极与第一电源电压端电连接，所述第一下拉控 制晶体管的第二极与所述第一下拉节点电连接；
所述第二下拉控制节点控制电路用于在所述上拉节点的电位的控制下，控制所述第二下拉控制节点的电位；
所述第二下拉控制晶体管的控制极与所述第二下拉控制节点电连接，所述第二下拉控制晶体管的第一极与第二电源电压端电连接，所述第二下拉控制晶体管的第二极与所述第二下拉节点电连接。
实施时，所述第一下拉控制节点控制电路包括第一下拉控制节点控制晶体管和第二下拉控制节点控制晶体管，所述第二下拉控制节点控制电路包括第三下拉控制节点控制晶体管和第四下拉控制节点控制晶体管；
所述第一下拉控制节点控制晶体管的控制极和所述第一下拉控制节点控制晶体管的第一极与第一电源电压端电连接，所述第一下拉控制节点控制晶体管的第二极与所述第一下拉控制节点电连接；
所述第二下拉控制节点控制晶体管的控制极与所述上拉节点电连接，所述第二下拉控制节点控制晶体管的第一极与所述第一下拉控制节点电连接，所述第二下拉控制节点控制晶体管的第二极与第一电压端电连接；
所述第三下拉控制节点控制晶体管的控制极和所述第三下拉控制节点控制晶体管的第一极与第二电源电压端电连接，所述第三下拉控制节点控制晶体管的第二极与所述第二下拉控制节点电连接；
所述第四下拉控制节点控制晶体管的控制极与所述上拉节点电连接，所述第四下拉控制节点控制晶体管的第一极与所述第二下拉控制节点电连接，所述第四下拉控制节点控制晶体管的第二极与第一电压端电连接。
实施时，所述第一下拉节点控制晶体管和所述第二下拉节点控制晶体管都为n型晶体管，在所述第一下拉节点控制晶体管和所述第二下拉节点控制晶体管关断时，所述第二电压端输入的第二电压小于所述第一电压端输入的第一电压，所述第三电压端输入的第三电压小于所述第一电压。
实施时，所述第一下拉节点控制晶体管和所述第二下拉节点控制晶体管都为p型晶体管，在所述第一下拉节点控制晶体管和所述第二下拉节点控制晶体管关断时，所述第二电压端输入的第二电压大于所述第一电压端输入的第一电压，所述第三电压端输入的第三电压大于所述第一电压。
本公开还提供了一种移位寄存器单元，包括上拉节点控制电路、下拉节点控制电路、偏置控制电路、存储电容、栅极驱动信号输出端、栅极驱动信号输出电路、进位信号输出电路和进位信号输出端；其中，
所述上拉节点控制电路包括第一上拉节点控制晶体管、第二上拉节点控制晶体管、第三上拉节点控制晶体管、第四上拉节点控制晶体管和第五上拉节点控制晶体管；
所述第一上拉节点控制晶体管的栅极和漏极都与输入端电连接，所述第一上拉节点控制晶体管的源极与上拉节点电连接；
所述第二上拉节点控制晶体管的栅极与复位端电连接，所述第二上拉节点控制晶体管的漏极与所述上拉节点电连接，所述第二上拉节点控制晶体管的源极与第一电压端电连接；
所述第三上拉节点控制晶体管的栅极与起始信号端电连接，所述第三上拉节点控制晶体管的漏极与所述上拉节点电连接，所述第三上拉节点控制晶体管的源极与所述第一电压端电连接；
所述第四上拉节点控制晶体管的栅极与第一下拉节点电连接，所述第四上拉节点控制晶体管的漏极与所述上拉节点电连接，所述第四上拉节点控制晶体管的源极与所述第一电压端电连接；
所述第五上拉节点控制晶体管的栅极与第二下拉节点电连接，所述第五上拉节点控制晶体管的漏极与所述上拉节点电连接，所述第五上拉节点控制晶体管的源极与所述第一电压端电连接；
所述存储电容的第一端与所述上拉节点电连接，所述存储电容的第二端与所述栅极驱动信号输出端电连接；
所述下拉节点控制电路包括第一下拉控制节点控制晶体管、第二下拉控制节点控制晶体管、第一下拉控制晶体管、第三下拉控制节点控制晶体管、第四下拉控制节点控制晶体管和第二下拉控制晶体管；
所述第一下拉控制节点控制晶体管的控制极和所述第一下拉控制节点控制晶体管的第一极与第一电源电压端电连接，所述第一下拉控制节点控制晶体管的第二极与所述第一下拉控制节点电连接；
所述第二下拉控制节点控制晶体管的控制极与所述上拉节点电连接，所 述第二下拉控制节点控制晶体管的第一极与所述第一下拉控制节点电连接，所述第二下拉控制节点控制晶体管的第二极与第一电压端电连接；
所述第一下拉控制晶体管的控制极与所述第一下拉控制节点电连接，所述第一下拉控制晶体管的第一极与第一电源电压端电连接，所述第一下拉控制晶体管的第二极与所述第一下拉节点电连接；
所述第三下拉控制节点控制晶体管的控制极和所述第三下拉控制节点控制晶体管的第一极与第二电源电压端电连接，所述第三下拉控制节点控制晶体管的第二极与所述第二下拉控制节点电连接；
所述第四下拉控制节点控制晶体管的控制极与所述上拉节点电连接，所述第四下拉控制节点控制晶体管的第一极与所述第二下拉控制节点电连接，所述第四下拉控制节点控制晶体管的第二极与第一电压端电连接；
所述第二下拉控制晶体管的控制极与所述第二下拉控制节点电连接，所述第二下拉控制晶体管的第一极与第二电源电压端电连接，所述第二下拉控制晶体管的第二极与所述第二下拉节点电连接；
所述偏置控制电路包括第一偏置控制晶体管和第二偏置控制晶体管；
所述第一偏置控制晶体管的控制极与所述第一下拉控制节点电连接，所述第一偏置控制晶体管的第一极与所述上拉节点电连接，所述第一偏置控制晶体管的第二极与第二电压端电连接；
所述第二偏置控制晶体管的控制极与所述第二下拉控制节点电连接，所述第二偏置控制晶体管的第一极与所述上拉节点电连接，所述第二偏置控制晶体管的第二极与第三电压端电连接；
所述栅极驱动信号输出电路包括第一栅极驱动信号输出晶体管、第二栅极驱动信号输出晶体管和第三栅极驱动信号输出晶体管，
所述第一栅极驱动信号输出晶体管的栅极与所述上拉节点电连接，所述第一栅极驱动信号输出晶体管的漏极与时钟信号端电连接，所述第一栅极驱动信号输出晶体管的源极与所述栅极驱动信号输出端电连接；
所述第二栅极驱动信号输出晶体管的栅极与所述第一下拉节点电连接，所述第二栅极驱动信号输出晶体管的漏极与所述栅极驱动信号输出端电连接，所述第二栅极驱动信号输出晶体管的源极与所述第一电压端电连接；
所述第三栅极驱动信号输出晶体管的栅极与所述第二下拉节点电连接，所述第三栅极驱动信号输出晶体管的漏极与所述栅极驱动信号输出端电连接，所述第三栅极驱动信号输出晶体管的源极与所述第一电压端电连接；
所述进位信号输出电路包括第一进位信号输出晶体管、第二进位信号输出晶体管和第三进位信号输出晶体管，
所述第一进位信号输出晶体管的栅极与所述上拉节点电连接，所述第一进位信号输出晶体管的漏极与所述时钟信号端电连接，所述第一进位信号输出晶体管的源极与所述进位信号输出端电连接；
所述第二进位信号输出晶体管的栅极与所述第一下拉节点电连接，所述第二进位信号输出晶体管的漏极与所述进位信号输出端电连接，所述第二进位信号输出晶体管的源极与所述第一电压端电连接；
所述第三进位信号输出晶体管的栅极与所述第二下拉节点电连接，所述第三进位信号输出晶体管的漏极与所述进位信号输出端电连接，所述第三进位信号输出晶体管的源极与所述第一电压端电连接。
本公开还提供了一种驱动方法，应用于上述的移位寄存器单元，所述驱动方法包括：
在复位阶段和输出截止保持阶段，下拉节点控制电路在上拉节点的电位的控制下，控制所述下拉节点与所述第一电压端之间断开；偏置控制电路控制所述上拉节点的电位，以控制下拉节点控制电路包括的下拉节点控制晶体管的栅源电压处于预定电压范围内。
实施时，所述下拉节点控制晶体管为n型晶体管，所述预定电压范围为小于0。
实施时，所述下拉节点控制晶体管为p型晶体管，所述预定电压范围为大于0。
本公开还提供了一种栅极驱动电路，包括多级上述的移位寄存器单元。
本公开还提供了一种显示装置，包括上述的栅极驱动电路。
附图说明
图1是本公开实施例所述的移位寄存器单元的结构图；
图2是本公开另一实施例所述的移位寄存器单元的结构图；
图3是本公开又一实施例所述的移位寄存器单元的结构图；
图4是本公开再一实施例所述的移位寄存器单元的结构图；
图5是本公开又一实施例所述的移位寄存器单元的结构图；
图6是本公开所述的移位寄存器单元的一具体实施例的电路图；
图7是本公开所述的移位寄存器单元的该具体实施例的工作时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为三极管时，所述控制极可以为基极，所述第一极可以为集电极，所述第二极可以发射极；或者，所述控制极可以为基极，所述第一极可以为发射极，所述第二极可以集电极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述控制极可以为栅极，所述第一极可以为漏极，所述第二极可以为源极；或者，所述控制极可以为栅极，所述第一极可以为源极，所述第二极可以为漏极。
在相关技术中的显示面板的信赖性测试过程中，在点灯超过300个小时后，陆续出现点灯显示异常的问题。经解析发现，信赖性测试过程中，移位寄存器单元中的下拉节点控制电路包括的下拉节点控制晶体管的阈值电压会逐渐发生正向漂移，使得所述下拉节点控制晶体管的开态电流Ion降低，上拉节点和下拉节点之间的竞争关系出现异常，从而使得在复位阶段无法对上拉节点的电位进行复位，出现屏幕显示异常。
针对上述技术问题，本公开提供一种移位寄存器单元、驱动方法、栅极驱动电路和显示装置，以解决相关技术中的移位寄存器单元中的下拉节点控 制电路包括的下拉节点控制晶体管的阈值电压漂移现象严重的问题。
如图1所示，本公开实施例所述的移位寄存器单元包括下拉节点控制电路11和偏置控制电路12，其中，
所述下拉节点控制电路11的控制端与上拉节点PU电连接，所述下拉节点控制电路11的第一端与下拉节点PD电连接，所述下拉节点控制电路11的第二端与第一电压端VT1电连接，所述下拉节点控制电路11用于在上拉节点PU的电位的控制下，控制所述下拉节点PD与所述第一电压端VT1之间连通或断开；
所述偏置控制电路12与所述上拉节点PU电连接，用于在所述下拉节点控制电路11控制所述下拉节点PD与所述第一电压端VT1之间断开时，通过控制所述上拉节点PU的电位，以控制所述下拉节点控制电路11包括的下拉节点控制晶体管的栅源电压处于预定电压范围内，以使得所述下拉节点控制晶体管处于反向偏置状态。
在具体实施时，所述第一电压端VT1可以为第一低电压端，但不以此为为限。
本公开如图1所示的移位寄存器单元的实施例在工作时，显示周期包括依次设置的输入阶段、输出阶段、复位阶段和输出截止保持阶段；
在输入阶段和输出阶段，下拉节点控制电路11在上拉节点PU的电位的控制下，控制所述下拉节点PD与所述第一电压端VT1之间连通；
在复位阶段和输出截止保持阶段，下拉节点控制电路11在上拉节点PU的电位的控制下，控制所述下拉节点PD与所述第一电压端VT1之间断开；偏置控制电路12控制所述上拉节点PU的电位，以控制下拉节点控制电路11包括的下拉节点控制晶体管的栅源电压处于预定电压范围内，以使得所述下拉节点控制晶体管处于反向偏置状态。
在具体实施时，所述下拉节点控制晶体管为n型晶体管，所述预定电压范围为小于0；或者，
所述下拉节点控制晶体管为p型晶体管，所述预定电压范围为大于0。
具体的，所述下拉节点控制电路可以包括一个下拉节点控制晶体管；
所述下拉节点控制晶体管的控制极与所述上拉节点电连接，所述下拉节 点控制晶体管的第一极与所述下拉节点电连接，所述下拉节点控制晶体管的第二极与第一电压端电连接；
所述偏置控制电路包括偏置控制晶体管；
所述偏置控制晶体管的控制极与偏置控制端电连接，所述偏置控制晶体管的第一极与所述上拉节点电连接，所述偏置控制晶体管的第二极与第二电压端电连接；
所述偏置控制端用于提供偏置控制信号，以使得在所述下拉节点控制晶体管关断时，控制所述偏置控制晶体管导通。
在具体实施时，所述第二电压端可以为第二低电压端，但不以此为限。
在具体实施时，所述下拉节点控制电路可以仅包括一个下拉节点控制晶体管，并本公开实施例所述的移位寄存器单元可以仅采用一个下拉节点，但不以此为限。
在具体实施时，所述下拉节点控制晶体管为n型晶体管，在所述下拉节点控制晶体管关断时，第二电压小于第一电压；或者，所述下拉节点控制晶体管为p型晶体管，在所述下拉节点控制晶体管关断时，第二电压大于第一电压；
所述第一电压端用于输入所述第一电压，所述第二电压端用于输入所述第二电压。
如图2所示，在图1所示的移位寄存器单元的实施例的基础上，所述下拉节点控制电路11可以包括下拉节点控制晶体管MDC1；
所述下拉节点控制晶体管MDC1的栅极与所述上拉节点PU电连接，所述下拉节点控制晶体管MDC1的漏极与所述下拉节点PD电连接，所述下拉节点控制晶体管MDC1的源极与第一低电压端电连接；所述第一低电压端用于输入第一低电压LVGL；
所述偏置控制电路12可以包括偏置控制晶体管MBC1；
所述偏置控制晶体管MBC1的栅极与偏置控制端BCtrl电连接，所述偏置控制晶体管MBC1的漏极与所述上拉节点PU电连接，所述偏置控制晶体管MBC1的源极与第二低电压端电连接；所述第二低电压端用于输入第二低电压VGL2；
所述偏置控制端BCtrl用于提供偏置控制信号，以使得在所述下拉节点控制晶体管MDC1关断时，控制所述偏置控制晶体管MBC1导通。
在图2所示的移位寄存器单元的实施例中，MDC1和MBC1都为NMOS管(N型金属-氧化物-半导体场效应晶体管)，但不以此为限。
在图2所示的移位寄存器单元的实施例中，在复位阶段和输出截止保持阶段，VGL2小于LVGL，MDC1的栅源电压小于0。由于相关技术中的下拉节点控制晶体管的阈值电压会逐渐发生正向漂移，而本申请中的MDC1的栅源电压小于0，从而能够减小MDC1的阈值电压偏移。
本公开如图2所示的移位寄存器单元的实施例在工作时，
在输入阶段和输出阶段，PU的电位为高电平，MDC1打开，MDC1的栅源电压大于0，MDC1的阈值电压正向偏移；BCtrl输入的偏置控制信号为低电平，MBC1关断；
在复位阶段和输出截止保持阶段，PU的电位为低电平，所述偏置控制信号为高电平，MBC1导通，PU接入VGL2，也即MDC1的栅极接入VGL2，MDC1的源极接入LVGL，则MDC1的栅源电压小于0，MDC1的阈值电压负向偏移。
本公开如图2所示的移位寄存器单元的实施例在工作时，MDC1在正负栅源电压偏压交互作用下，MDC1的阈值电压趋向稳定状态。
在具体实施时，当MDC1被替换为p型晶体管时，在输入阶段和输出阶段，MDC1的栅源电压小于0，则需要在复位阶段和输出截止保持阶段，控制MDC1的栅源电压大于0，以使得MDC1的阈值电压稳定。
具体的，所述偏置控制电压端可以为下拉控制节点；
所述下拉节点控制电路还包括下拉控制节点控制电路和下拉控制晶体管；
所述下拉控制节点控制电路用于在所述上拉节点的电位的控制下，控制所述下拉控制节点的电位；
所述下拉控制晶体管的控制极与所述下拉控制节点电连接，所述下拉控制晶体管的第一极与电源电压端电连接，所述下拉控制晶体管的第二极与所述下拉节点电连接。
如图3所示，在图2所示的移位寄存器单元的实施例的基础上，所述偏 置控制电压端为下拉控制节点PDCN；
所述下拉节点控制电路11还包括下拉控制节点控制电路30和下拉控制晶体管MDC2；
所述下拉控制节点控制电路30用于在所述上拉节点PU的电位的控制下，控制所述下拉控制节点PDCN的电位；
所述下拉控制晶体管MDC2的栅极与所述下拉控制节点PDCN电连接，所述下拉控制晶体管MDC2的漏极与电源电压端电连接，所述下拉控制晶体管MDC2的源极与所述下拉节点PD电连接；
所述电源电压端用于输入电源电压VDD。
在图3所示的移位寄存器单元的实施例中，MDC2为NMOS管，但不以此为限。
本公开如图3所示的移位寄存器单元的实施例在工作时，MDC1和MDC2一起控制PD的电位，下拉控制节点控制电路30控制PDCN的电位。
在具体实施时，所述下拉控制节点控制电路30可以包括第一控制晶体管和第二控制晶体管；
所述第一控制晶体管的控制极和所述第一控制晶体管的第一极与电源电压端电连接，所述第一控制晶体管的第二极与所述下拉控制节点电连接；
所述第二控制晶体管的控制极与所述上拉节点电连接，所述第二控制晶体管的第一极与所述下拉控制节点电连接，所述第二控制晶体管的第二极与第一电压端电连接。
在具体实施时，在本公开如图3所示的移位寄存器单元的实施例的基础上，本公开实施例所述的移位寄存器单元还可以包括上拉节点控制电路、存储电容、进位信号输出端、栅极驱动信号输出端、栅极驱动信号输出电路和进位信号输出电路；
所述上拉节点控制电路可以与输入端、起始信号端和复位端、下拉节点和上拉节点电连接，用于在输入端提供的输入信号、起始信号端提供的起始信号、复位端提供的复位信号和下拉节点的电位的控制下，控制上拉节点的电位；
所述存储电容的第一端可以与所述上拉节点电连接，所述存储电容的第 二端可以与栅极驱动信号输出端电连接；
所述栅极驱动信号输出电路分别与上拉节点、下拉节点、栅极驱动信号输出端、时钟信号端和第一电压端电连接，用于在所述上拉节点的电位的控制下，控制所述栅极驱动信号输出端与所述时钟信号端之间连通，在所述下拉节点的电位的控制下，控制所述栅极驱动信号输出端与所述第一电压端之间连通；
所述进位信号输出电路分别与上拉节点、下拉节点、进位信号输出端、时钟信号端和第一电压端电连接，用于在所述上拉节点的电位的控制下，控制所述进位信号输出端与所述时钟信号端之间连通，在所述下拉节点的电位的控制下，控制所述进位信号输出端与所述第一电压端之间连通；
所述栅极驱动信号输出端输出的栅极驱动信号用于驱动相应行栅线，所述进位信号输出端输出的进位信号用于向相邻下一级移位寄存器单元提供输入信号，并向相邻上一级移位寄存器单元提供复位信号。
具体的，所述下拉节点可以包括第一下拉节点和第二下拉节点；所述下拉节点控制电路可以包括第一下拉节点控制晶体管和第二下拉节点控制晶体管；
所述第一下拉节点控制晶体管的控制极与所述上拉节点电连接，所述第一下拉节点控制晶体管的第一极与所述第一下拉节点电连接，所述第一下拉节点控制晶体管的第二极与第一电压端电连接；
所述第二下拉节点控制晶体管的控制极与所述上拉节点电连接，所述第二下拉节点控制晶体管的第一极与所述第二下拉节点电连接，所述第二下拉节点控制晶体管的第二极与第一电压端电连接；
所述偏置控制电路包括第一偏置控制晶体管和第二偏置控制晶体管；
所述第一偏置控制晶体管的控制极与第一偏置控制端电连接，所述第一偏置控制晶体管的第一极与所述上拉节点电连接，所述第一偏置控制晶体管的第二极与第二电压端电连接；
所述第二偏置控制晶体管的控制极与第二偏置控制端电连接，所述第二偏置控制晶体管的第一极与所述上拉节点电连接，所述第二偏置控制晶体管的第二极与第三电压端电连接；
所述第一偏置控制端用于提供第一偏置控制信号，以使得在所述第一下拉节点控制晶体管和所述第二下拉节点控制晶体管关断时，控制所述第一偏置控制晶体管导通；
所述第二偏置控制端用于提供第二偏置控制信号，以使得在所述第一下拉节点控制晶体管和所述第二下拉节点控制晶体管关断时，控制所述第二偏置控制晶体管导通。
在具体实施时，本公开实施例所述的移位寄存器单元可以采用两个下拉节点，所述下拉节点控制电路可以包括两个下拉节点控制晶体管，所述偏置控制电路可以包括两个偏置控制晶体管，但不以此为限。
在具体实施时，所述第一电压端可以为第一低电压端，所述第二电压端和所述第三电压端可以为第二低电压端，但不以此为限。
在具体实施时，所述第一下拉节点控制晶体管和所述第二下拉节点控制晶体管为n型晶体管，在所述第一下拉节点控制晶体管和所述第二下拉节点控制晶体管关断时，第二电压小于第一电压，第三电压小于第一电压；或者，所述第一下拉节点控制晶体管和所述第二下拉节点控制晶体管为p型晶体管，在所述第一下拉节点控制晶体管和所述第二下拉节点控制晶体管关断时，第二电压大于第一电压，第三电压大于第一电压；
所述第一电压端用于输入所述第一电压，所述第二电压端用于输入所述第二电压，所述第三电压端用于输入所述第三电压。
如图4所示，在图1所示的移位寄存器单元的实施例的基础上，所述下拉节点可以包括第一下拉节点PD1和第二下拉节点PD2；
所述下拉节点控制电路11可以包括第一下拉节点控制晶体管M6和第二下拉节点控制晶体管M6’；
所述第一下拉节点控制晶体管M6的栅极与所述上拉节点PU电连接，所述第一下拉节点控制晶体管M6的漏极与所述第一下拉节点PD1电连接，所述第一下拉节点控制晶体管M6的源极与第一低电压端电连接；所述第一低电压端用于输入第一低电压LVGL；
所述第二下拉节点控制晶体管M6’的栅极与所述上拉节点PU电连接，所述第二下拉节点控制晶体管M6’的漏极与所述第二下拉节点PD2电连接， 所述第二下拉节点控制晶体管M6’的源极与所述第一低电压端电连接；
所述偏置控制电路12包括第一偏置控制晶体管M14和第二偏置控制晶体管M14；
所述第一偏置控制晶体管M14的栅极与第一偏置控制端BCtrl1电连接，所述第一偏置控制晶体管M14的漏极与所述上拉节点PU电连接，所述第一偏置控制晶体管M14的源极与第二低电压端电连接；所述第二低电压端用于提供第二低电压VGL2；
所述第二偏置控制晶体管M14’的栅极与第二偏置控制端BCtrl2电连接，所述第二偏置控制晶体管M14’的漏极与所述上拉节点PU电连接，所述第二偏置控制晶体管M14’的源极与所述第二低电压端电连接；
所述第一偏置控制端BCtrl1用于提供第一偏置控制信号，以使得在所述第一下拉节点控制晶体管M6和所述第二下拉节点控制晶体管M6’关断时，控制所述第一偏置控制晶体管M14导通；
所述第二偏置控制端BCtrl2用于提供第二偏置控制信号，以使得在所述第一下拉节点控制晶体管M6和所述第二下拉节点控制晶体管M6’关断时，控制所述第二偏置控制晶体管M14’导通。
在图4所示的移位寄存器单元的实施例中，M6、M6’、M14和M14’都为NMOS管(N型金属-氧化物-半导体场效应晶体管)，但不以此为限。
在图4所示的移位寄存器单元的实施例中，在复位阶段和输出截止保持阶段，VGL2小于LVGL，M6的栅源电压小于0，从而能够减小M6的阈值电压偏移，M6’的栅源电压小于0，从而能够减小M6’的阈值电压偏移。
本公开如图4所示的移位寄存器单元的实施例在工作时，M6和M6’交替工作，相应的，M14和M14’也交替工作。即，M6工作时，相应的，M14也工作，此时M6’和M14’不工作；M6不工作时，M14也相应不工作，此时，M6’和M14’工作。
在输入阶段和输出阶段，PU的电位为高电平，M6或M6’打开，M6的栅源电压或M6’的栅源电压大于0，M6的阈值电压或M6’的阈值电压负向偏移；BCtrl1输入的第一偏置控制信号或BCtrl2输入的第二偏置控制信号为低电平，M14或M14’关断；
在复位阶段和输出截止保持阶段，PU的电位为低电平，所述第一偏置控制信号或所述第二偏置控制信号为高电平，M14或M14’导通，PU接入VGL2，也即M6的栅极或M6’的栅极接入VGL2，M6的源极或M6’的源极接入LVGL，则M6的栅源电压或M6’的栅源电压小于0，M6的阈值电压或M6’的阈值电压反向偏移。
本公开如图4所示的移位寄存器单元的实施例在工作时，M6和M6’在正负栅源电压偏压交互作用下，M6的阈值电压和M6’的阈值电压趋向稳定状态。
在具体实施时，当M6和M6’被替换为p型晶体管时，在输入阶段和输出阶段，M6的栅源电压和M6’的栅源电压小于0，则需要在复位阶段和输出截止保持阶段，控制M6的栅源电压和M6’的栅源电压大于0，以使得M6的阈值电压和M6’的阈值电压稳定。
在具体实施时，所述第一偏置控制电压端可以为第一下拉控制节点，所述第二偏置控制电压端可以为第二下拉控制节点；
所述下拉节点控制电路还可以包括第一下拉控制节点控制电路、第一下拉控制晶体管、第二下拉控制节点控制电路和第二下拉控制晶体管；
所述第一下拉控制节点控制电路用于在所述上拉节点的电位的控制下，控制所述第一下拉控制节点的电位；
所述第一下拉控制晶体管的控制极与所述第一下拉控制节点电连接，所述第一下拉控制晶体管的第一极与第一电源电压端电连接，所述第一下拉控制晶体管的第二极与所述第一下拉节点电连接；
所述第二下拉控制节点控制电路用于在所述上拉节点的电位的控制下，控制所述第二下拉控制节点的电位；
所述第二下拉控制晶体管的控制极与所述第二下拉控制节点电连接，所述第二下拉控制晶体管的第一极与第二电源电压端电连接，所述第二下拉控制晶体管的第二极与所述第二下拉节点电连接。
如图5所示，在图4所示的移位寄存器单元的实施例的基础上，所述第一偏置控制电压端为第一下拉控制节点PDCN1，所述第二偏置控制电压端为第二下拉控制节点PDCN2；
所述下拉节点控制电路11还可以包括第一下拉控制节点控制电路301、第一下拉控制晶体管M5、第二下拉控制节点控制电路302和第二下拉控制晶体管M5’；
所述第一下拉控制节点控制电路301分别与上拉节点PU和第一下拉控制节点PDCN1电连接，用于在所述上拉节点PU的电位的控制下，控制所述第一下拉控制节点PDCN1的电位；
所述第一下拉控制晶体管M5的栅极与所述第一下拉控制节点PDCN1电连接，所述第一下拉控制晶体管M5的漏极与第一电源电压端电连接，所述第一下拉控制晶体管M5的源极与所述第一下拉节点PD1电连接；
所述第二下拉控制节点控制电路302分别与所述上拉节点PU和第二下拉控制节点PDCN2电连接，用于在所述上拉节点PU的电位的控制下，控制所述第二下拉控制节点PDCN2的电位；
所述第二下拉控制晶体管M5’的栅极与所述第二下拉控制节点PDCN2电连接，所述第二下拉控制晶体管M5’的漏极与第二电源电压端电连接，所述第二下拉控制晶体管M5’的源极与所述第二下拉节点PD2电连接；
所述第一电源电压端用于输入第一电源电压VDD1，所述第二电源电压端用于输入第二电源电压VDD2。
在图5所示的移位寄存器单元的实施例中，M5和M5’为NMOS管，但不以此为限。
本公开如图5所示的移位寄存器单元的实施例在工作时，M6和M5一起控制PD1的电位，第一下拉控制节点控制电路301控制PDCN1的电位；M6’和M5’一起控制PD2的电位，第二下拉控制节点控制电路302控制PDCN2的电位。
如图6所示，在本公开如图5所示的移位寄存器单元的实施例的基础上，在本公开所述的移位寄存器单元的一具体实施例中，
所述第一下拉控制节点控制电路包括第一下拉控制节点控制晶体管M9和第二下拉控制节点控制晶体管M8；
所述第二下拉控制节点控制电路包括第三下拉控制节点控制晶体管M9’和第四下拉控制节点控制晶体管M8’；
所述第一下拉控制节点控制晶体管M9的控制极和所述第一下拉控制节点控制晶体管M9的第一极与第一电源电压端VDD1电连接，所述第一下拉控制节点控制晶体管M9的第二极与所述第一下拉控制节点PDCN1电连接；
所述第二下拉控制节点控制晶体管M8的控制极与所述上拉节点PU电连接，所述第二下拉控制节点控制晶体管M8的第一极与所述第一下拉控制节点电连接，所述第二下拉控制节点控制晶体管M8的第二极与第一电压端电连接；
所述第三下拉控制节点控制晶体管M9’的控制极和所述第三下拉控制节点控制晶体管M9’的第一极与第二电源电压端VDD2电连接，所述第三下拉控制节点控制晶体管M9’的第二极与所述第二下拉控制节点PDCN2电连接；
所述第四下拉控制节点控制晶体管M8’的控制极与所述上拉节点PU电连接，所述第四下拉控制节点控制晶体管M8’的第一极与所述第二下拉控制节点PDCN2电连接，所述第四下拉控制节点控制晶体管M8’的第二极与第一电压端电连接。
进一步，本公开所述的移位寄存器单元的该具体实施例还包括上拉节点控制电路、存储电容C1、栅极驱动信号输出端G_out、栅极驱动信号输出电路、进位信号输出端Out_c和进位信号输出电路；
所述上拉节点控制电路包括第一上拉节点控制晶体管M1、第二上拉节点控制晶体管M2、第三上拉节点控制晶体管M0、第四上拉节点控制晶体管M10’和第五上拉节点控制晶体管M10，其中，
M1的栅极和漏极都与输入端Input电连接，M1的源极与上拉节点PU电连接；
M2的栅极与复位端Reset_PU电连接，M2的漏极与PU电连接，M2的源极与第一低电压端电连接；所述第一低电压端用于输入第一低电压LVGL；
M0的栅极与起始信号端STV电连接，M0的漏极与PU电连接，M0的源极与所述第一低电压端电连接；
M10’的栅极与第一下拉节点PD1电连接，M10’的漏极与PU电连接，M10’的源极与所述第一低电压端电连接；
M10的栅极与第二下拉节点PD2电连接，M10的漏极与PU电连接， M10的源极与所述第一低电压端电连接；
C1的第一端与PU电连接，C1的第二端与G_out电连接；
所述栅极驱动信号输出电路包括第一栅极驱动信号输出晶体管M3、第二栅极驱动信号输出晶体管M11和第三栅极驱动信号输出晶体管M11’，其中，
M3的栅极与PU电连接，M3的漏极接入时钟信号CLK，M3的源极与G_out电连接；
M11的栅极与PD1电连接，M11的漏极与G_out电连接，M11的源极接入LVGL；
M11’的栅极与PD2电连接，M11’的漏极与G_out电连接，M11’的源极接入LVGL；
所述进位信号输出电路包括第一进位信号输出晶体管M13、第二进位信号输出晶体管M12和第三进位信号输出晶体管M12’，其中，
M13的栅极与PU电连接，M13的漏极接入时钟信号CLK，M3的源极与Out_c电连接；
M12的栅极与PD1电连接，M12的漏极与Out_c电连接，M12的源极接入LVGL；
M12’的栅极与PD2电连接，M12’的漏极与Out_c电连接，M12’的源极接入LVGL。
在图6所示的移位寄存器单元的具体实施例中，所有的晶体管都为NMOS管，但不以此为限。
如图7所示，本公开所述的移位寄存器单元的具体实施例在工作时，显示周期包括依次设置的输入阶段t1、输出阶段t2、复位阶段t3和输出截止保持阶段t4；在所述显示周期，VDD1为高电平，VDD2为低电平；其中，M9、M5、M8和M6，与M9’、M5’、M8’和M6’是交替工作的，VDD1为高电平，VDD2为低电平时，M9、M5、M8和M6工作，M9’、M5’、M8’和M6’不工作；VDD1为低电平，VDD2为高电平时，M9’、M5’、M8’和M6’工作，M9、M5、M8和M6不工作。相应的，M14和M14’也交替工作。
在输入阶段t1，PU的电位为30V左右，LVGL为-8V，VGL2为-8V，M6打开，PD1的电位为低电平，M8打开，PDCN1的电位为低电平，M14关断， M6的栅源电压为38V左右；
在输出阶段t2，PU的电位为45V左右，LVGL为-8V，VGL2为-8V，M6打开，PD1的电位为低电平，M8打开，PDCN1为低电平，M14关断，M6的栅源电压为53V左右；
在复位阶段t3和输出截止保持阶段t4，PU的电位为低电平，PD1的电位为28V左右，LVGL为-8V，VGL2为-15V，M6关断，并PDCN1的电位为高电平，M5打开，M14打开，以使得M6的栅极接入-15V，M6的栅源电压为-7V。
此外，如图7所示，一个显示周期内M6开启时间较短，即一个显示周期内M6短时间处于38V-53V的高栅源电压(Vgs)状态；一个显示周期内M6开启时间较长，即一个显示周期内M6长时间处于-7V的负Vgs状态，从而M6在正负栅源电压偏压交互作用下，M6的阈值电压趋向稳定状态。
本公开所述的移位寄存器单元的具体实施例在工作时，在输入阶段t1和输出阶段t2，M6的阈值电压正向漂移，在复位阶段t3和输出截止保持阶段t4，M6的阈值电压反向漂移，从而可以使得M6的阈值电压趋向稳定状态。
此外，VDD1为低电平，VDD2为高电平时，图6所示的移位寄存器单元的工作过程可具体参见上述描述过程，此处不再赘述。
本公开实施例所述的移位寄存器单元的具体实施例在工作时，显示时间包括多个显示时间段，每一显示时间段包括依次设置的第一显示时间段和第二显示时间段；
在所述第一显示时间段，VDD1为高电平，VDD2为低电平；
在所述第二显示时间段，VDD1为低电平，VDD2为高电平；
所述第一显示时间段可以包括至少一个显示周期，所述第二显示时间段可以包括至少一个显示周期。
在本公开实施例中，当CLK为低电平时，CLK的电位可以为-8V，当CLK为高电平时，CLK的电位可以为32V，但不以此为限。
本公开实施例所述的驱动方法，应用于上述的移位寄存器单元，所述驱动方法包括：
在复位阶段和输出截止保持阶段，下拉节点控制电路在上拉节点的电位 的控制下，控制所述下拉节点与所述第一电压端之间断开；偏置控制电路控制所述上拉节点的电位，以控制下拉节点控制电路包括的下拉节点控制晶体管的栅源电压处于预定电压范围内。
在具体实施时，所述下拉节点控制晶体管可以为n型晶体管，所述预定电压范围为小于0；或者，
所述下拉节点控制晶体管可以为p型晶体管，所述预定电压范围为大于0。
本公开实施例所述的栅极驱动电路包括多级上述的移位寄存器单元。
本公开实施例所述的显示装置包括上述的栅极驱动电路。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的可选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (20)

  1. 一种移位寄存器单元，包括下拉节点控制电路和偏置控制电路，其中，
    所述下拉节点控制电路的控制端与上拉节点电连接，所述下拉节点控制电路的第一端与下拉节点电连接，所述下拉节点控制电路的第二端与第一电压端电连接，所述下拉节点控制电路用于在上拉节点的电位的控制下，控制所述下拉节点与所述第一电压端之间连通或断开；
    所述偏置控制电路与所述上拉节点电连接，用于在所述下拉节点控制电路控制所述下拉节点与所述第一电压端之间断开时，通过控制所述上拉节点的电位，以控制所述下拉节点控制电路包括的下拉节点控制晶体管的栅源电压处于预定电压范围内。
  2. 如权利要求1所述的移位寄存器单元，其中，所述下拉节点控制晶体管为n型晶体管，所述预定电压范围为小于0。
  3. 如权利要求1所述的移位寄存器单元，其中，所述下拉节点控制晶体管为p型晶体管，所述预定电压范围为大于0。
  4. 如权利要求1所述的移位寄存器单元，其中，所述下拉节点控制电路包括下拉节点控制晶体管；
    所述下拉节点控制晶体管的控制极与所述上拉节点电连接，所述下拉节点控制晶体管的第一极与所述下拉节点电连接，所述下拉节点控制晶体管的第二极与第一电压端电连接。
  5. 如权利要求4所述的移位寄存器单元，其中，所述偏置控制电路包括偏置控制晶体管；
    所述偏置控制晶体管的控制极与偏置控制端电连接，所述偏置控制晶体管的第一极与所述上拉节点电连接，所述偏置控制晶体管的第二极与第二电压端电连接；
    所述偏置控制端用于提供偏置控制信号，以使得在所述下拉节点控制晶体管关断时，控制所述偏置控制晶体管导通。
  6. 如权利要求5所述的移位寄存器单元，其中，所述偏置控制电压端为下拉控制节点；
    所述下拉节点控制电路还包括下拉控制节点控制电路和下拉控制晶体管；
    所述下拉控制节点控制电路用于在所述上拉节点的电位的控制下，控制所述下拉控制节点的电位；
    所述下拉控制晶体管的控制极与所述下拉控制节点电连接，所述下拉控制晶体管的第一极与电源电压端电连接，所述下拉控制晶体管的第二极与所述下拉节点电连接。
  7. 如权利要求4-6任一项所述的移位寄存器单元，其中，所述下拉节点控制晶体管为n型晶体管，在所述下拉节点控制晶体管关断时，所述第二电压端输入的第二电压小于所述第一电压端输入的第一电压。
  8. 如权利要求4-6任一项所述的移位寄存器单元，其中，所述下拉节点控制晶体管为p型晶体管，在所述下拉节点控制晶体管关断时，所述第二电压端输入的第二电压大于所述第一电压端输入的第一电压。
  9. 如权利要求1所述的移位寄存器单元，其中，所述下拉节点包括第一下拉节点和第二下拉节点；所述下拉节点控制电路包括第一下拉节点控制晶体管和第二下拉节点控制晶体管；
    所述第一下拉节点控制晶体管的控制极与所述上拉节点电连接，所述第一下拉节点控制晶体管的第一极与所述第一下拉节点电连接，所述第一下拉节点控制晶体管的第二极与第一电压端电连接；
    所述第二下拉节点控制晶体管的控制极与所述上拉节点电连接，所述第二下拉节点控制晶体管的第一极与所述第二下拉节点电连接，所述第二下拉节点控制晶体管的第二极与第一电压端电连接。
  10. 如权利要求9所述的移位寄存器单元，其中，所述偏置控制电路包括第一偏置控制晶体管和第二偏置控制晶体管；
    所述第一偏置控制晶体管的控制极与第一偏置控制端电连接，所述第一偏置控制晶体管的第一极与所述上拉节点电连接，所述第一偏置控制晶体管的第二极与第二电压端电连接；
    所述第二偏置控制晶体管的控制极与第二偏置控制端电连接，所述第二偏置控制晶体管的第一极与所述上拉节点电连接，所述第二偏置控制晶体管的第二极与第三电压端电连接；
    所述第一偏置控制端用于提供第一偏置控制信号，以使得所述第一下拉节点控制晶体管和所述第二下拉节点控制晶体管关断时，控制所述第一偏置控制晶体管导通；
    所述第二偏置控制端用于提供第二偏置控制信号，以使得所述第一下拉节点控制晶体管和所述第二下拉节点控制晶体管关断时，控制所述第二偏置控制晶体管导通。
  11. 如权利要求10所述的移位寄存器单元，其中，所述第一偏置控制电压端为第一下拉控制节点，所述第二偏置控制电压端为第二下拉控制节点；
    所述下拉节点控制电路还包括第一下拉控制节点控制电路、第一下拉控制晶体管、第二下拉控制节点控制电路和第二下拉控制晶体管；
    所述第一下拉控制节点控制电路用于在所述上拉节点的电位的控制下，控制所述第一下拉控制节点的电位；
    所述第一下拉控制晶体管的控制极与所述第一下拉控制节点电连接，所述第一下拉控制晶体管的第一极与第一电源电压端电连接，所述第一下拉控制晶体管的第二极与所述第一下拉节点电连接；
    所述第二下拉控制节点控制电路用于在所述上拉节点的电位的控制下，控制所述第二下拉控制节点的电位；
    所述第二下拉控制晶体管的控制极与所述第二下拉控制节点电连接，所述第二下拉控制晶体管的第一极与第二电源电压端电连接，所述第二下拉控制晶体管的第二极与所述第二下拉节点电连接。
  12. 如权利要求11所述的移位寄存器单元，其中，所述第一下拉控制节点控制电路包括第一下拉控制节点控制晶体管和第二下拉控制节点控制晶体管，所述第二下拉控制节点控制电路包括第三下拉控制节点控制晶体管和第四下拉控制节点控制晶体管；
    所述第一下拉控制节点控制晶体管的控制极和所述第一下拉控制节点控制晶体管的第一极与第一电源电压端电连接，所述第一下拉控制节点控制晶体管的第二极与所述第一下拉控制节点电连接；
    所述第二下拉控制节点控制晶体管的控制极与所述上拉节点电连接，所述第二下拉控制节点控制晶体管的第一极与所述第一下拉控制节点电连接， 所述第二下拉控制节点控制晶体管的第二极与第一电压端电连接；
    所述第三下拉控制节点控制晶体管的控制极和所述第三下拉控制节点控制晶体管的第一极与第二电源电压端电连接，所述第三下拉控制节点控制晶体管的第二极与所述第二下拉控制节点电连接；
    所述第四下拉控制节点控制晶体管的控制极与所述上拉节点电连接，所述第四下拉控制节点控制晶体管的第一极与所述第二下拉控制节点电连接，所述第四下拉控制节点控制晶体管的第二极与第一电压端电连接。
  13. 如权利要求9-12任一项所述的移位寄存器单元，其中，所述第一下拉节点控制晶体管和所述第二下拉节点控制晶体管都为n型晶体管，在所述第一下拉节点控制晶体管和所述第二下拉节点控制晶体管关断时，所述第二电压端输入的第二电压小于所述第一电压端输入的第一电压，所述第三电压端输入的第三电压小于所述第一电压。
  14. 如权利要求9-12任一项所述的移位寄存器单元，其中，所述第一下拉节点控制晶体管和所述第二下拉节点控制晶体管都为p型晶体管，在所述第一下拉节点控制晶体管和所述第二下拉节点控制晶体管关断时，所述第二电压端输入的第二电压大于所述第一电压端输入的第一电压，所述第三电压端输入的第三电压大于所述第一电压。
  15. 一种移位寄存器单元，包括上拉节点控制电路、下拉节点控制电路、偏置控制电路、存储电容、栅极驱动信号输出端、栅极驱动信号输出电路、进位信号输出电路和进位信号输出端；其中，
    所述上拉节点控制电路包括第一上拉节点控制晶体管、第二上拉节点控制晶体管、第三上拉节点控制晶体管、第四上拉节点控制晶体管和第五上拉节点控制晶体管；
    所述第一上拉节点控制晶体管的栅极和漏极都与输入端电连接，所述第一上拉节点控制晶体管的源极与上拉节点电连接；
    所述第二上拉节点控制晶体管的栅极与复位端电连接，所述第二上拉节点控制晶体管的漏极与所述上拉节点电连接，所述第二上拉节点控制晶体管的源极与第一电压端电连接；
    所述第三上拉节点控制晶体管的栅极与起始信号端电连接，所述第三上 拉节点控制晶体管的漏极与所述上拉节点电连接，所述第三上拉节点控制晶体管的源极与所述第一电压端电连接；
    所述第四上拉节点控制晶体管的栅极与第一下拉节点电连接，所述第四上拉节点控制晶体管的漏极与所述上拉节点电连接，所述第四上拉节点控制晶体管的源极与所述第一电压端电连接；
    所述第五上拉节点控制晶体管的栅极与第二下拉节点电连接，所述第五上拉节点控制晶体管的漏极与所述上拉节点电连接，所述第五上拉节点控制晶体管的源极与所述第一电压端电连接；
    所述存储电容的第一端与所述上拉节点电连接，所述存储电容的第二端与所述栅极驱动信号输出端电连接；
    所述下拉节点控制电路包括第一下拉控制节点控制晶体管、第二下拉控制节点控制晶体管、第一下拉控制晶体管、第三下拉控制节点控制晶体管、第四下拉控制节点控制晶体管和第二下拉控制晶体管；
    所述第一下拉控制节点控制晶体管的控制极和所述第一下拉控制节点控制晶体管的第一极与第一电源电压端电连接，所述第一下拉控制节点控制晶体管的第二极与所述第一下拉控制节点电连接；
    所述第二下拉控制节点控制晶体管的控制极与所述上拉节点电连接，所述第二下拉控制节点控制晶体管的第一极与所述第一下拉控制节点电连接，所述第二下拉控制节点控制晶体管的第二极与第一电压端电连接；
    所述第一下拉控制晶体管的控制极与所述第一下拉控制节点电连接，所述第一下拉控制晶体管的第一极与第一电源电压端电连接，所述第一下拉控制晶体管的第二极与所述第一下拉节点电连接；
    所述第三下拉控制节点控制晶体管的控制极和所述第三下拉控制节点控制晶体管的第一极与第二电源电压端电连接，所述第三下拉控制节点控制晶体管的第二极与所述第二下拉控制节点电连接；
    所述第四下拉控制节点控制晶体管的控制极与所述上拉节点电连接，所述第四下拉控制节点控制晶体管的第一极与所述第二下拉控制节点电连接，所述第四下拉控制节点控制晶体管的第二极与第一电压端电连接；
    所述第二下拉控制晶体管的控制极与所述第二下拉控制节点电连接，所 述第二下拉控制晶体管的第一极与第二电源电压端电连接，所述第二下拉控制晶体管的第二极与所述第二下拉节点电连接；
    所述偏置控制电路包括第一偏置控制晶体管和第二偏置控制晶体管；
    所述第一偏置控制晶体管的控制极与所述第一下拉控制节点电连接，所述第一偏置控制晶体管的第一极与所述上拉节点电连接，所述第一偏置控制晶体管的第二极与第二电压端电连接；
    所述第二偏置控制晶体管的控制极与所述第二下拉控制节点电连接，所述第二偏置控制晶体管的第一极与所述上拉节点电连接，所述第二偏置控制晶体管的第二极与第三电压端电连接；
    所述栅极驱动信号输出电路包括第一栅极驱动信号输出晶体管、第二栅极驱动信号输出晶体管和第三栅极驱动信号输出晶体管，
    所述第一栅极驱动信号输出晶体管的栅极与所述上拉节点电连接，所述第一栅极驱动信号输出晶体管的漏极与时钟信号端电连接，所述第一栅极驱动信号输出晶体管的源极与所述栅极驱动信号输出端电连接；
    所述第二栅极驱动信号输出晶体管的栅极与所述第一下拉节点电连接，所述第二栅极驱动信号输出晶体管的漏极与所述栅极驱动信号输出端电连接，所述第二栅极驱动信号输出晶体管的源极与所述第一电压端电连接；
    所述第三栅极驱动信号输出晶体管的栅极与所述第二下拉节点电连接，所述第三栅极驱动信号输出晶体管的漏极与所述栅极驱动信号输出端电连接，所述第三栅极驱动信号输出晶体管的源极与所述第一电压端电连接；
    所述进位信号输出电路包括第一进位信号输出晶体管、第二进位信号输出晶体管和第三进位信号输出晶体管，
    所述第一进位信号输出晶体管的栅极与所述上拉节点电连接，所述第一进位信号输出晶体管的漏极与所述时钟信号端电连接，所述第一进位信号输出晶体管的源极与所述进位信号输出端电连接；
    所述第二进位信号输出晶体管的栅极与所述第一下拉节点电连接，所述第二进位信号输出晶体管的漏极与所述进位信号输出端电连接，所述第二进位信号输出晶体管的源极与所述第一电压端电连接；
    所述第三进位信号输出晶体管的栅极与所述第二下拉节点电连接，所述 第三进位信号输出晶体管的漏极与所述进位信号输出端电连接，所述第三进位信号输出晶体管的源极与所述第一电压端电连接。
  16. 一种驱动方法，应用于如权利要求1至15中任一权利要求所述的移位寄存器单元，所述驱动方法包括：
    在复位阶段和输出截止保持阶段，下拉节点控制电路在上拉节点的电位的控制下，控制所述下拉节点与所述第一电压端之间断开；偏置控制电路控制所述上拉节点的电位，以控制下拉节点控制电路包括的下拉节点控制晶体管的栅源电压处于预定电压范围内。
  17. 如权利要求16所述的驱动方法，其中，所述下拉节点控制晶体管为n型晶体管，所述预定电压范围为小于0。
  18. 如权利要求16所述的驱动方法，其中，所述下拉节点控制晶体管为p型晶体管，所述预定电压范围为大于0。
  19. 一种栅极驱动电路，包括多级如权利要求1至15中任一权利要求所述的移位寄存器单元。
  20. 一种显示装置，包括如权利要求19所述的栅极驱动电路。
PCT/CN2020/082940 2019-06-18 2020-04-02 移位寄存器单元、驱动方法、栅极驱动电路和显示装置 WO2020253323A1 (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220327975A1 (en) * 2020-02-24 2022-10-13 Beijing Boe Display Technology Co., Ltd. Shift register circuit, gate driving circuit and display apparatus

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110246447A (zh) * 2019-06-18 2019-09-17 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
CN113168802B (zh) * 2019-10-18 2023-05-09 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN116030766A (zh) * 2021-10-26 2023-04-28 武汉京东方光电科技有限公司 移位寄存器单元、栅极驱动电路及显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070045908A (ko) * 2005-10-27 2007-05-02 엘지.필립스 엘시디 주식회사 쉬프트 레지스터
CN103617775A (zh) * 2013-10-28 2014-03-05 北京大学深圳研究生院 移位寄存器单元、栅极驱动电路及显示器
CN104078021A (zh) * 2014-07-17 2014-10-01 深圳市华星光电技术有限公司 具有自我补偿功能的栅极驱动电路
CN104134416A (zh) * 2013-04-30 2014-11-05 乐金显示有限公司 栅极移位寄存器及使用其的显示装置
CN205564249U (zh) * 2016-02-03 2016-09-07 京东方科技集团股份有限公司 移位寄存器单元和显示装置
CN106409200A (zh) * 2015-07-31 2017-02-15 乐金显示有限公司 栅极驱动电路及使用该栅极驱动电路的显示装置
CN110246447A (zh) * 2019-06-18 2019-09-17 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102654984B (zh) * 2011-10-21 2014-03-26 京东方科技集团股份有限公司 移位寄存器单元以及栅极驱动电路
CN103226981B (zh) * 2013-04-10 2015-09-16 京东方科技集团股份有限公司 一种移位寄存器单元及栅极驱动电路
KR102064923B1 (ko) * 2013-08-12 2020-01-13 삼성디스플레이 주식회사 게이트 구동 회로 및 이를 구비한 표시 장치
CN104795106B (zh) * 2015-04-14 2019-04-05 上海天马有机发光显示技术有限公司 移位寄存器及驱动方法、驱动电路、阵列基板和显示装置
CN105528985B (zh) * 2016-02-03 2019-08-30 京东方科技集团股份有限公司 移位寄存器单元、驱动方法和显示装置
CN107464521B (zh) * 2017-09-29 2019-09-20 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及驱动方法、显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070045908A (ko) * 2005-10-27 2007-05-02 엘지.필립스 엘시디 주식회사 쉬프트 레지스터
CN104134416A (zh) * 2013-04-30 2014-11-05 乐金显示有限公司 栅极移位寄存器及使用其的显示装置
CN103617775A (zh) * 2013-10-28 2014-03-05 北京大学深圳研究生院 移位寄存器单元、栅极驱动电路及显示器
CN104078021A (zh) * 2014-07-17 2014-10-01 深圳市华星光电技术有限公司 具有自我补偿功能的栅极驱动电路
CN106409200A (zh) * 2015-07-31 2017-02-15 乐金显示有限公司 栅极驱动电路及使用该栅极驱动电路的显示装置
CN205564249U (zh) * 2016-02-03 2016-09-07 京东方科技集团股份有限公司 移位寄存器单元和显示装置
CN110246447A (zh) * 2019-06-18 2019-09-17 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220327975A1 (en) * 2020-02-24 2022-10-13 Beijing Boe Display Technology Co., Ltd. Shift register circuit, gate driving circuit and display apparatus
US11830398B2 (en) * 2020-02-24 2023-11-28 Beijing Boe Display Technology Co., Ltd. Shift register circuit, gate driving circuit and display apparatus

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