WO2022213579A1 - 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置 - Google Patents
移位寄存器单元及其驱动方法、栅极驱动电路、显示装置 Download PDFInfo
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- WO2022213579A1 WO2022213579A1 PCT/CN2021/126087 CN2021126087W WO2022213579A1 WO 2022213579 A1 WO2022213579 A1 WO 2022213579A1 CN 2021126087 W CN2021126087 W CN 2021126087W WO 2022213579 A1 WO2022213579 A1 WO 2022213579A1
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- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 6
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- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052733 gallium Inorganic materials 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
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- 230000005669 field effect Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
Definitions
- the present disclosure relates to the field of display technology, and in particular, to a shift register unit and a driving method thereof, a gate driving circuit, and a display device.
- the shift register usually includes a plurality of cascaded shift register units, and each shift register unit is used to drive a row of pixel units.
- Embodiments of the present disclosure provide a shift register unit and a driving method thereof, a gate driving circuit, and a display device, and the technical solutions are as follows:
- a shift register unit comprising:
- a first input circuit respectively coupled to a first clock terminal, a first node, a second node, a third node, a pull-up power supply terminal and a pull-down power supply terminal, the first input circuit is used to respond to the first clock
- the first clock signal provided by the terminal controls the on-off of the pull-up power terminal and the first node, and controls the on-off of the pull-down power terminal and the first node; and is used for responding to the first node.
- the potential of the second node controls the on-off of the pull-up power terminal and the third node, and controls the on-off of the pull-down power terminal and the third node;
- the second input circuit is respectively coupled to the first node, the second node, the third node, the pull-up power terminal, the pull-down power terminal, the input control terminal and the first clock terminal , the second input circuit is configured to control the pull-up in response to the potential of the first node, the potential of the third node, the first clock signal and the input control signal provided by the input control terminal on/off of the power terminal and the second node, and controlling the on/off of the pull-down power terminal and the second node;
- the output circuit is used for responding to the potential of the third node and the second clock signal provided by the second clock terminal to control the on-off of the pull-up power terminal and the output terminal, and control the on-off of the pull-down power terminal and the output terminal.
- the output circuit includes: a first output sub-circuit and a second output sub-circuit;
- the first output sub-circuit is respectively coupled to the second clock terminal, the third node, the pull-up power terminal, the pull-down power terminal and the fourth node, and the first output sub-circuit is used for In response to the second clock signal and the potential of the third node, the on-off of the pull-up power terminal and the fourth node is controlled, and the on-off of the pull-down power terminal and the fourth node is controlled ;
- the second output sub-circuit is respectively coupled to the fourth node, the pull-up power terminal, the pull-down power terminal and the output terminal, and the second output sub-circuit is used for responding to the fourth node
- the potential of the node controls the on-off of the pull-up power terminal and the output terminal, and controls the on-off of the pull-down power terminal and the output terminal.
- the first output sub-circuit includes: a first output transistor, a second output transistor, and a third output transistor, and the first output transistor is a complementary metal-oxide-semiconductor CMOS transistor;
- the gate of the first output transistor is coupled to the second clock terminal, and a first pole of the first output transistor and a first pole of the second output transistor are both coupled to the pull-up power supply terminal connected, the other first pole of the first output transistor is coupled to the second pole of the third output transistor, and the second pole of the first output transistor and the second pole of the second output transistor are both is coupled to the fourth node, the gate of the second output transistor and the gate of the third output transistor are both coupled to the third node, and the first pole of the third output transistor is connected to the third node.
- the pull-down power terminal is coupled.
- the second output sub-circuit includes: an odd number of fourth output transistors connected in series between the fourth node and the output end;
- Each of the fourth output transistors is a CMOS transistor, and two first electrodes of each of the fourth output transistors are respectively coupled to the pull-up power supply terminal and the pull-down power supply terminal.
- the second output sub-circuit includes: three of the fourth output transistors;
- the gate of the first fourth output transistor is coupled to the fourth node, and the second electrode of the first fourth output transistor is coupled to the gate of the second fourth output transistor connected, the second pole of the second fourth output transistor is coupled to the gate of the third fourth output transistor, and the second pole of the third fourth output transistor is coupled to the output terminal catch.
- the width to length ratio of the at least one fourth output transistor is greater than the width to length ratio of other transistors in the shift register unit except the at least one fourth output transistor.
- the second input circuit includes: a first input sub-circuit and a second input sub-circuit;
- the first input sub-circuit is respectively coupled to the first node, the first clock terminal, the input control terminal, the pull-up power terminal, the pull-down power terminal and the second node, so The first input sub-circuit is used to control the on-off of the pull-up power supply terminal and the second node in response to the potential of the first node, the input control signal and the first clock signal, and to control on-off of the pull-down power supply terminal and the second node;
- the second input sub-circuit is respectively coupled to the first clock terminal, the first node, the second node, the third node, the pull-up power terminal and the pull-down power terminal, so The second input sub-circuit is configured to control the on-off of the pull-up power supply terminal and the second node in response to the potential of the first node, the potential of the third node and the first clock signal, And control the on-off of the pull-down power terminal and the second node.
- the first input sub-circuit includes: a first input transistor, a second input transistor, a third input transistor and a fourth input transistor; the first input transistor and the third input transistor are both CMOS transistors ;
- the gate of the first input transistor is coupled to the first node, the two first poles of the first input transistor are respectively coupled to the pull-up power supply terminal and the pull-down power supply terminal, and the first The second pole of an input transistor is coupled to the gate of the second input transistor, and the gate of the second input transistor is further coupled to the first clock terminal;
- a first pole of the second input transistor is coupled to the pull-down power supply terminal, and a second pole of the second input transistor is coupled to a first pole of the third input transistor;
- the other first pole of the third input transistor is coupled to the second pole of the fourth input transistor, the gate of the third input transistor is coupled to the input control terminal, and the third input transistor The second pole of is coupled to the second node;
- the gate of the fourth input transistor is coupled to the first node, and the first electrode of the fourth input transistor is coupled to the pull-up power terminal.
- the second input sub-circuit includes: a fifth input transistor, a sixth input transistor and a seventh input transistor; the sixth input transistor is a CMOS transistor;
- the gate of the fifth input transistor is coupled to the first clock terminal, the first pole of the fifth input transistor is coupled to the pull-up power supply terminal, and the second pole of the fifth input transistor is coupled to the pull-up power supply terminal. a first pole of the sixth input transistor is coupled;
- the other first pole of the sixth input transistor is coupled to the second pole of the seventh input transistor, and the gate of the sixth input transistor is coupled to the third node;
- the first electrode of the seventh input transistor is coupled to the pull-down power supply terminal, and the gate of the seventh input transistor is coupled to the first node.
- the first input circuit includes: a third input sub-circuit and a fourth input sub-circuit;
- the third input sub-circuit is respectively coupled to the first clock terminal, the pull-up power terminal, the pull-down power terminal and the first node, and the third input sub-circuit is used for responding to the a first clock signal, which controls the on-off of the pull-up power terminal and the first node, and controls the on-off of the pull-down power terminal and the first node;
- the fourth input sub-circuit is respectively coupled to the second node, the pull-up power terminal, the pull-down power terminal and the third node, and the fourth input sub-circuit is used for responding to the first
- the potential of the second node controls the on-off of the pull-up power terminal and the third node, and controls the on-off of the pull-down power terminal and the third node.
- the third input sub-circuit includes: an eighth input transistor and a ninth input transistor;
- the fourth input sub-circuit includes: a tenth input transistor; the eighth input transistor and the ninth input transistor and the tenth input transistor are both CMOS transistors;
- the gate of the eighth input transistor and the gate of the ninth input transistor are both coupled to the first clock terminal, and the two first poles of the eighth input transistor and the ninth input transistor The two first poles are respectively coupled to the pull-up power supply terminal and the pull-down power supply terminal, and the second pole of the eighth input transistor and the second pole of the ninth input transistor are both connected to the first pole. node coupling;
- the gate of the tenth input transistor is coupled to the second node, the two first poles of the tenth input transistor are respectively coupled to the pull-up power terminal and the pull-down power terminal, and the first The second pole of the ten-input transistor is coupled to the third node.
- a method for driving a shift register unit for driving the shift register unit according to the above aspect; the method includes:
- the first input circuit controls the pull-down power supply terminal to conduct with the first node in response to the first clock signal provided by the first clock terminal;
- the second input circuit responds to the input control signal provided by the input control terminal and the first node a clock signal to control the pull-down power terminal to conduct with the second node;
- the first input circuit also controls the pull-up power terminal to conduct with the third node in response to the potential of the second node;
- the first input circuit controls the pull-up power supply terminal to conduct with the first node in response to the first clock signal
- the second input circuit responds to the potential of the first node and The potential of the third node controls the pull-down power terminal and the second node to conduct, and the first input circuit also controls the pull-up power terminal and the second node in response to the potential of the second node.
- the third node is turned on; the output circuit controls the pull-up power supply terminal to be turned on with the output terminal in response to the potential of the third node and the second clock signal provided by the second clock terminal;
- the first input circuit controls the pull-down power supply terminal to conduct with the first node in response to the first clock signal
- the second input circuit responds to the potential of the first node and all
- the input control signal controls the pull-up power terminal and the second node to conduct
- the first input circuit also controls the pull-down power terminal and the third node in response to the potential of the second node.
- the output circuit controls the pull-down power supply terminal and the output terminal to be turned on in response to the potential of the third node and the second clock signal.
- a gate drive circuit comprising: at least two cascaded shift register units according to the above aspects;
- the first clock terminal of the odd-numbered stage shift register unit is coupled to the first clock signal line, and the second clock terminal of the odd-numbered stage shift register unit is coupled to the second clock signal line;
- the first clock terminal of the even-numbered stage shift register unit is coupled to the second clock signal line, and the second clock terminal of the even-numbered stage shift register unit is coupled to the first clock signal line.
- a display device in another aspect, includes: a display panel, and the gate driving circuit according to the above aspect, the display panel includes a plurality of pixel circuits;
- the gate driving circuit is coupled to a gate signal terminal in the pixel circuit, and the gate driving circuit is used for providing a gate driving signal to the gate signal terminal.
- the pixel circuit includes: a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor, a fifth switch transistor, a sixth switch transistor, a seventh switch transistor, and a storage capacitor;
- the gate of the first switch transistor is coupled to the reset control terminal, the first pole of the first switch transistor is coupled to the reset signal terminal, and the second pole of the first switch transistor is coupled to the second switch transistor The first pole of , the second pole of the sixth switching transistor and the anode of the light-emitting element are coupled;
- the gate of the second switch transistor is coupled to the switch control terminal, and the second pole of the second switch transistor is coupled to the gate of the third switch transistor;
- the gate of the fifth switching transistor and the gate of the sixth switching transistor are both coupled to the light-emitting control terminal, the first pole of the fifth switching transistor is coupled to the driving power terminal, and the fifth switching transistor
- the gate of the fourth switch transistor and the gate of the seventh switch transistor are both coupled to the gate signal terminal; the first pole of the fourth switch transistor is coupled to the data signal terminal, and the fourth switch transistor is coupled to the data signal terminal.
- the second pole of the four-switch transistor is coupled to the second pole of the third switch transistor; the first pole of the seventh switch transistor is coupled to the first pole of the third switch transistor, and the seventh switch transistor the second pole of the transistor is coupled to the gate of the third switching transistor;
- One end of the storage capacitor is coupled to the gate of the third switching transistor, and the other end of the storage capacitor is coupled to the drive power end;
- the fourth switch transistor and the seventh switch transistor are both N-type indium gallium zinc oxide IGZO transistors, and the output end of the shift register unit in the gate driving circuit is connected to the output end of the fourth switch transistor.
- the gate is coupled to the gate of the seventh switching transistor.
- FIG. 1 is a schematic structural diagram of a shift register unit provided by an embodiment of the present disclosure
- FIG. 2 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure.
- FIG. 3 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure.
- FIG. 4 is a schematic structural diagram of still another shift register unit provided by an embodiment of the present disclosure.
- FIG. 5 is a schematic structural diagram of still another shift register unit provided by an embodiment of the present disclosure.
- FIG. 6 is a flowchart of a method for driving a shift register unit provided by an embodiment of the present disclosure
- FIG. 9 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present disclosure.
- FIG. 10 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
- FIG. 11 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure.
- FIG. 12 is a timing diagram of each signal terminal in a pixel circuit provided by an embodiment of the present disclosure.
- the transistors used in all the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics, and the transistors used in the embodiments of the present disclosure are mainly switching transistors according to their functions in the circuit. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable. In the embodiments of the present disclosure, the source electrode is referred to as the first electrode and the drain electrode is referred to as the second electrode, or the drain electrode is referred to as the first electrode and the source electrode is referred to as the second electrode. According to the form in the drawings, the middle terminal of the transistor is the gate, the signal input terminal is the source, and the signal output terminal is the drain.
- the switching transistor used in the embodiments of the present disclosure may include any one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level, and turned off when the gate is at a high level , the N-type switching transistor is turned on when the gate is high and turned off when the gate is low.
- multiple signals in each embodiment of the present disclosure correspond to a first potential and a second potential, and the first potential and the second potential only represent that the potential of the signal has two different state quantities, and do not represent the first potential in the whole text. The potential or the second potential has a specific value.
- a shift register unit generally includes: an input circuit, an output circuit and a pull-down circuit.
- the input circuit is coupled to the pull-up node, and the input circuit is used for charging the pull-up node according to the driving signal output by the cascaded upper-stage shift register unit.
- the output circuit is coupled to the output terminal, and the output circuit is used for outputting a gate driving signal to the output terminal under the control of the pull-up node.
- the pull-down circuit is respectively coupled to the pull-up node and the output terminal, and the pull-down circuit is used to reduce noise on the pull-up node and the output terminal.
- FIG. 1 is a schematic structural diagram of a shift register unit provided by an embodiment of the present disclosure.
- the shift register unit may include: a first input circuit 01, a second input circuit 02 and an output circuit 03.
- the first input circuit 01 may be coupled to a first clock terminal CKV1 , a first node N1 , a second node N2 , a third node N3 , a pull-up power terminal VGH and a pull-down power terminal VGL, respectively.
- the first input circuit 01 can be used to control the connection between the pull-up power terminal VGH and the first node N1, and control the pull-down power terminal VGL and the first node N1 in response to the first clock signal provided by the first clock terminal CKV1. on and off.
- coupling may refer to electrical connection.
- the first input sub-circuit 01 can control the pull-down power supply terminal VGL to conduct with the first node N1 when the potential of the first clock signal is the first potential, and when the potential of the first clock signal is the second potential,
- the pull-up power terminal VGH is controlled to be turned on with the first node N1.
- the pull-up power supply terminal VGH and the first node N1 are turned on, the pull-up power supply signal provided by the pull-up power supply terminal VGH can be transmitted to the first node N1 through the first input sub-circuit 01 .
- the pull-down power signal provided by the pull-down power terminal VGL can be transmitted to the first node N1 through the first input sub-circuit 01 .
- the control of the potential of the first node N1 is realized.
- the first input sub-circuit 01 can also control the on-off of the pull-down power supply terminal VGL and the third node N3 when the potential of the second node N2 is the first potential, and the potential of the second node N2 is the second potential
- the pull-up power supply terminal VGH and the third node N3 are controlled to be turned on and off.
- the pull-up power supply terminal VGH and the third node N3 are turned on, the pull-up power supply signal can be transmitted to the third node N3 through the first input sub-circuit 01 .
- the pull-down power terminal VGL and the third node N3 are turned on, the pull-down power signal can be transmitted to the third node N3 through the first input sub-circuit 01 .
- the control of the potential of the third node N3 is realized.
- the potential of the pull-up power signal may be the first potential
- the potential of the pull-down power signal may be the second potential.
- the first potential described in the embodiment of the present disclosure may be a high potential relative to the second potential, that is, the first potential relative to the second potential is larger.
- the first potential ie, high potential
- the second potential ie, low potential
- the first potential may be an inactive potential
- the first potential may be an inactive potential
- the second potential may be an effective potential.
- the second input circuit 02 may be coupled to the first node N1, the second node N2, the third node N3, the pull-up power terminal VGH, the pull-down power terminal VGL, the input control terminal CSTV and the first clock terminal CKV1, respectively. catch.
- the second input circuit 02 can be used to control the pull-up power supply terminal VGH and the second node in response to the potential of the first node N1, the potential of the third node N3, the first clock signal and the input control signal provided by the input control terminal CSTV
- the on-off of N2 is controlled, and the on-off of the pull-down power supply terminal VGL and the second node N2 is controlled.
- the second input circuit 02 can control the pull-down power supply terminal VGL to conduct with the second node N2 when the potential of the first clock signal and the potential of the input control signal are both the first potential, and/or, at the first node When the potential of N1 and the potential of the third node N3 are both the first potential, the pull-down power supply terminal VGL is controlled to conduct with the second node N2.
- the second input circuit 02 can control the pull-up power supply terminal VGH and the second node N2 to conduct when the potential of the first node N1 and the potential of the input control signal are both the second potential, and/or, at the first When the potential of the clock signal and the potential of the third node N3 are both the second potential, the pull-up power supply terminal VGH is controlled to conduct with the second node N2.
- the pull-up power signal can be transmitted to the second node N2 through the second input circuit 02 .
- the pull-down power terminal VGL and the second node N2 are turned on, the pull-down power signal can be transmitted to the second node N2 through the second input circuit 02 .
- the control of the potential of the second node N2 is realized.
- the output circuit 03 may be coupled to the pull-up power terminal VGH, the pull-down power terminal VGL, the third node N3, the second clock terminal CKV2 and the output terminal OUT, respectively.
- the output circuit 03 can be used to control the on-off of the pull-up power terminal VGH and the output terminal OUT in response to the potential of the third node N3 and the second clock signal provided by the second clock terminal CKV2, and to control the pull-down power terminal VGL and the output The on-off of the terminal OUT.
- the output circuit 03 can control the pull-up power supply terminal VGH and the output terminal OUT to conduct. And, the output circuit 03 can control the pull-down power terminal VGL and the output terminal OUT to be turned on when the potential of the third node N3 is the second potential, and/or when the potential of the second clock signal is the first potential.
- the pull-up power supply terminal VGH and the output terminal OUT when the pull-up power supply terminal VGH and the output terminal OUT are turned on, the pull-up power supply signal can be transmitted to the output terminal OUT through the output circuit 03 .
- the pull-down power supply terminal VGL and the output terminal OUT are turned on, the pull-down power supply signal can be transmitted to the output terminal OUT through the output circuit 03 .
- the output terminal OUT can be coupled to the gate signal terminal of the pixel circuit in the display panel to provide the gate signal terminal with a gate driving signal.
- the transistor coupled to the gate signal terminal in the pixel circuit can be reliably turned on or off in response to the pull-up power signal and the pull-down power signal transmitted by the output terminal OUT.
- the shift register unit described in the embodiments of the present disclosure only includes an input circuit and an output circuit.
- the first clock signal provided by the first clock terminal CKV1, the second clock signal provided by the second clock terminal CKV2, and the input control signal provided by the input control terminal CSTV it is possible to reliably transmit a high potential to the output terminal OUT.
- the shift register unit needs to set fewer signal terminals, and the control process is relatively simple.
- the embodiments of the present disclosure provide a shift register unit, in which the first input circuit can be controlled by the first clock signal provided by the first clock terminal and the potential of the second node , respectively control the potential of the first node and the potential of the third node.
- the second input circuit can control the potential of the second node under the control of the first clock signal, the input control signal provided by the input control terminal, the potential of the third node and the potential of the first node.
- the output circuit can transmit a high-level pull-up power signal or a low-level pull-down power signal to the output end under the control of the third node.
- FIG. 2 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure.
- the output circuit 03 may include: a first output sub-circuit 031 and a second output sub-circuit 032 .
- the first output sub-circuit 031 can be respectively coupled to the second clock terminal CKV2, the third node N3, the pull-up power terminal VGH, the pull-down power terminal VGL and the fourth node N4.
- the first output sub-circuit 031 can be used to control the on-off of the pull-up power terminal VGH and the fourth node N4, and control the pull-down power terminal VGL and the fourth node N4 in response to the second clock signal and the potential of the third node N3 on and off.
- the first output sub-circuit 031 can control the pull-down power supply terminal VGL to conduct with the fourth node N4 when the potential of the third node N3 and the potential of the second clock signal are both the first potential, and the third node N3
- the potential of the second clock signal is the second potential, and/or when the potential of the second clock signal is the second potential, the pull-up power supply terminal VGH is controlled to be turned on with the fourth node N4.
- the pull-down power terminal VGL and the fourth node N4 are turned on, the pull-down power signal can be transmitted to the fourth node N4 through the first output sub-circuit 031 .
- the pull-up power signal can be transmitted to the fourth node N4 through the first output sub-circuit 031 .
- the control of the potential of the fourth node N4 is realized.
- the second output sub-circuit 032 may be coupled to the fourth node N4, the pull-up power terminal VGH, the pull-down power terminal VGL and the output terminal OUT, respectively.
- the second output sub-circuit 032 can be used to control the on-off of the pull-up power terminal VGH and the output terminal OUT, and control the on-off of the pull-down power terminal VGL and the output terminal OUT in response to the potential of the fourth node N4.
- the second output sub-circuit 032 can control the pull-down power supply terminal VGL and the output terminal OUT to be turned on when the potential of the fourth node N4 is the first potential, and control the pull-down power supply terminal VGL and the output terminal OUT when the potential of the fourth node N4 is the second potential
- the pull-up power supply terminal VGH is connected to the output terminal OUT.
- the pull-down power supply terminal VGL and the output terminal OUT are turned on, the pull-down power supply signal can be transmitted to the output terminal OUT through the second output sub-circuit 032 .
- the pull-up power supply terminal VGH and the output terminal OUT are turned on, the pull-up power supply signal can be transmitted to the output terminal OUT through the second output sub-circuit 032 .
- the control of the potential of the output terminal OUT is realized.
- FIG. 3 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure.
- the second input circuit 02 may include: a first input sub-circuit 021 and a second input sub-circuit 022 .
- the first input sub-circuit 021 can be respectively coupled to the first node N1, the first clock terminal CKV1, the input control terminal CSTV, the pull-up power terminal VGH, the pull-down power terminal VGL and the second node N2.
- the first input sub-circuit 021 can be used to control the on-off of the pull-up power terminal VGH and the second node N2 in response to the potential of the first node N1, the input control signal and the first clock signal, and to control the pull-down power terminal VGL and the second node N2. On-off of the second node N2.
- the first input sub-circuit 021 may control the pull-down power supply terminal VGL to conduct with the second node N2 when the potential of the first clock signal and the potential of the input control signal are both the first potential. And, the first input sub-circuit 021 can control the pull-up power supply terminal VGH to conduct with the second node N2 when the potential of the first node N1 and the potential of the input control signal are both the second potential.
- the pull-up power terminal VGH and the second node N2 are turned on, the pull-up power signal can be transmitted to the second node N2 through the first input sub-circuit 021 .
- the pull-down power signal can be transmitted to the second node N2 through the first input sub-circuit 021 .
- the control of the potential of the second node N2 is realized.
- the second input sub-circuit 022 may be coupled to the first clock terminal CKV1, the first node N1, the second node N2, the third node N3, the pull-up power terminal VGH and the pull-down power terminal VGL, respectively.
- the second input sub-circuit 022 can be used to control the on-off of the pull-up power supply terminal VGH and the second node N2, and control the pull-down power supply in response to the potential of the first node N1, the potential of the third node N3 and the first clock signal The connection between the terminal VGL and the second node N2.
- the second input sub-circuit 022 can control the pull-down power supply terminal VGL to conduct with the second node N2 when the potential of the first node N1 and the potential of the third node N3 are both the first potential.
- the second input sub-circuit 022 can control the pull-up power terminal VGH to conduct with the second node N2 when the potential of the first clock signal and the potential of the third node N3 are both the second potential.
- the pull-up power terminal VGH and the second node N2 are turned on, the pull-up power signal can be transmitted to the second node N2 through the second input sub-circuit 022 .
- the pull-down power terminal VGL is turned on with the second node N2, the pull-down power signal can be transmitted to the second node N2 through the second input sub-circuit 022.
- the control of the potential of the second node N2 is realized.
- FIG. 4 is a schematic structural diagram of still another shift register unit provided by an embodiment of the present disclosure.
- the first input circuit 01 includes: a third input sub-circuit 011 and a fourth input sub-circuit 012 .
- the third input sub-circuit 011 can be respectively coupled to the first clock terminal CKV1, the pull-up power terminal VGH, the pull-down power terminal VGL and the first node N1, and the third input sub-circuit 011 can be used to respond to the first The clock signal controls the on-off of the pull-up power terminal VGH and the first node N1, and controls the on-off of the pull-down power terminal VGL and the first node N1.
- the third input sub-circuit 011 can control the pull-down power supply terminal VGL to conduct with the first node N1 when the potential of the first clock signal is the first potential, and when the potential of the first clock signal is the second potential,
- the pull-up power terminal VGH is controlled to be turned on with the first node N1.
- the pull-down power terminal VGL and the first node N1 are turned on, the pull-down power signal can be transmitted to the first node N1 through the third input sub-circuit 011 .
- the pull-up power terminal VGH is turned on with the first node N1 , the pull-up power signal can be transmitted to the first node N1 through the third input sub-circuit 011 .
- the control of the potential of the first node N1 is realized.
- the fourth input sub-circuit 012 may be coupled to the second node N2, the pull-up power terminal VGH, the pull-down power terminal VGL and the third node N3, respectively.
- the fourth input sub-circuit 012 can be used to control the on-off of the pull-up power terminal VGH and the third node N3, and control the on-off of the pull-down power terminal VGL and the third node N3 in response to the potential of the second node N2.
- the fourth input sub-circuit 012 can control the pull-down power supply terminal VGL to conduct with the third node N3 when the potential of the second node N2 is the first potential, and when the potential of the second node N2 is the second potential,
- the pull-up power supply terminal VGH is controlled to be turned on with the third node N3.
- the pull-down power signal can be transmitted to the third node N3 through the fourth input sub-circuit 012 .
- the pull-up power terminal VGH and the third node N3 are turned on, the pull-up power signal can be transmitted to the third node N3 through the fourth input sub-circuit 012 .
- the control of the potential of the third node N3 is realized.
- FIG. 5 is a schematic structural diagram of still another shift register unit provided by an embodiment of the present disclosure.
- the first output sub-circuit 031 may include: a first output transistor T1 , a second output transistor T2 and a third output transistor T3 .
- the first output transistor may be a complementary metal-oxide-semiconductor (CMOS) transistor.
- CMOS complementary metal-oxide-semiconductor
- CMOS transistor refers to a complementary MOS integrated circuit composed of a P-type transistor and an N-type transistor.
- the CMOS transistor may have one gate, two first poles (also referred to as source) and one drain.
- the gate of the CMOS transistor receives a high-level signal
- the N-type transistor it includes is turned on.
- the signal provided by the signal terminal coupled to the first pole of the N-type transistor can be transmitted to The second pole of the CMOS transistor.
- the gate of the CMOS transistor When the gate of the CMOS transistor receives a low-level signal, the P-type transistor it includes is turned on. At this time, among the two first poles, the signal provided by the signal terminal coupled to the first pole of the P-type transistor can be transmitted to The second pole of the CMOS transistor.
- the gate of the first output transistor T1 may be coupled to the second clock terminal CKV2 , and the two first electrodes of the first output transistor T1 may be respectively connected to
- the pull-up power terminal VGH is coupled to the fourth node N4, and the second pole of the first output transistor T1 may be coupled to the second pole of the second output transistor T2.
- the first pole of the second output transistor T2 may be coupled to the pull-up power supply terminal VGH, the gate of the second output transistor T2 and the gate of the third output transistor T3 may both be coupled to the third node N3, and the third output transistor The first pole of T3 may be coupled to the pull-down power supply terminal VGL, and the second pole of the third output transistor T3 may be coupled to the fourth node N4.
- the gate of the first output transistor T1 may be coupled to the second clock terminal CKV2, a first pole of the first output transistor T1 and the first pole of the second output transistor T2 may both be coupled to the pull-up power supply terminal VGH, and the first The other first pole of an output transistor T1 may be coupled to the second pole of the third output transistor T3, and both the second pole of the first output transistor T1 and the second pole of the second output transistor T2 may be connected to the fourth node N4 Coupling, the gate of the second output transistor T2 and the gate of the third output transistor T3 may both be coupled to the third node N3, and the first pole of the third output transistor T3 may be coupled to the pull-down power supply terminal VGL.
- the second output sub-circuit 032 may include: an odd number of fourth output transistors T4 connected in series between the fourth node N4 and the output terminal OUT.
- each fourth output transistor T4 may be a CMOS transistor, and the two first poles of each fourth output transistor T4 may be respectively coupled to the pull-up power supply terminal VGH and the pull-down power supply terminal VGL.
- the second output sub-circuit 032 shown therein includes three fourth output transistors T4 connected in series.
- the gate of the first fourth output transistor T4 is coupled to the fourth node N4, the second pole of the first fourth output transistor T4 is coupled to the gate of the second fourth output transistor T4, the second
- the second electrode of the third fourth output transistor T4 is coupled to the gate of the third fourth output transistor T4, and the second electrode of the third fourth output transistor T4 is coupled to the output terminal OUT.
- the second output sub-circuit 032 can invert the potential of the fourth node N4 and transmit it to the output terminal OUT.
- inverters can also be used to replace odd-numbered fourth output transistors T4.
- the function of the second output sub-circuit 032 is to invert the potential of the fourth node N4 and transmit it to the output terminal OUT
- the three fourth output transistors T4 included in the second output sub-circuit 032 can also be called three-stage buffer (buffer).
- the first input sub-circuit 021 may include: a first input transistor M1 , a second input transistor M2 , a third input transistor M3 and a fourth input transistor M4 .
- the first input transistor M1 and the third input transistor M3 may both be CMOS transistors.
- the gate of the first input transistor M1 may be coupled to the first node N1, the two first poles of the first input transistor M1 may be respectively coupled to the pull-up power supply terminal VGH and the pull-down power supply terminal VGL, and the first input transistor M1
- the second electrode may be coupled to the gate of the second input transistor M2, and the gate of the second input transistor M2 is further coupled to the first clock terminal CKV1. That is, the second pole of the first input transistor M1 and the first clock terminal CKV1 may be coupled together and coupled to the gate of the second input transistor M2 at the same time.
- the first electrode of the second input transistor M2 may be coupled to the pull-down power supply terminal VGL, and the second electrode of the second input transistor M2 may be coupled to a first electrode of the third input transistor M3.
- the other first pole of the third input transistor M3 may be coupled to the second pole of the fourth input transistor M4, the gate of the third input transistor M3 may be coupled to the input control terminal CSTV, and the second pole of the third input transistor M3 The pole may be coupled with the second node N2.
- the gate of the fourth input transistor M4 may be coupled to the first node N1, and the first pole of the fourth input transistor M4 may be coupled to the pull-up power supply terminal VGH.
- the second input sub-circuit 022 may include: a fifth input transistor M5 , a sixth input transistor M6 and a seventh input transistor M7 .
- the sixth input transistor M6 may be a CMOS transistor.
- the gate of the fifth input transistor M5 may be coupled to the first clock terminal CKV1, the first pole of the fifth input transistor M5 may be coupled to the pull-up power supply terminal VGH, and the second pole of the fifth input transistor M5 may be coupled to the sixth input transistor A first pole of M6 is coupled.
- the gate of the fifth input transistor M5 may be coupled to the node where the second pole of the first input transistor M1 is coupled to the first clock terminal CKV1, so as to be indirectly coupled to the first clock terminal CKV1. .
- the other first pole of the sixth input transistor M6 may be coupled with the second pole of the seventh input transistor M7, and the gate of the sixth input transistor M6 may be coupled with the third node N3.
- the first pole of the seventh input transistor M7 may be coupled to the pull-down power supply terminal VGL, and the gate of the seventh input transistor M7 may be coupled to the first node N1.
- the third input sub-circuit 011 may include: an eighth input transistor M8 and a ninth input transistor M9.
- the fourth input sub-circuit 012 may include: a tenth input transistor M10.
- the eighth input transistor M8, the ninth input transistor M9 and the tenth input transistor M10 may all be CMOS transistors.
- the gate of the eighth input transistor M8 and the gate of the ninth input transistor M9 may both be coupled to the first clock terminal CKV1, the two first poles of the eighth input transistor M8 and the two first poles of the ninth input transistor M9 The poles may both be coupled to the pull-up power terminal VGH and the pull-down power terminal VGL, respectively.
- the second pole of the eighth input transistor M8 and the second pole of the ninth input transistor M9 may both be coupled to the first node N1.
- the gate of the ninth input transistor M9 may be coupled to the node where the second pole of the first input transistor M1 is coupled to the first clock terminal CKV1, so as to be indirectly coupled to the first clock terminal CKV1.
- the gate of the seventh input transistor M7 may be coupled to the second pole of the ninth input transistor M9, so as to be indirectly coupled to the first node N1.
- the gate of the tenth input transistor M10 may be coupled to the second node N2, the two first poles of the tenth input transistor M10 may be respectively coupled to the pull-up power terminal VGH and the pull-down power terminal VGL, and the tenth input transistor M10 has a
- the second pole may be coupled with the third node N3.
- the shift register unit described in the embodiment of the present disclosure includes a total of 13 P-type transistors (PMOS for short) and 13 N-type transistors (NMOS for short), and a first clock terminal CKV1 needs to be set in total,
- the second clock terminal CKV2 and an input control terminal CSTV have a total of three control terminals.
- the embodiments of the present disclosure do not limit the number of transistors included in the shift register unit, and other structures capable of realizing the above functions may also be applicable to the solutions of the embodiments of the present disclosure.
- the width to length ratio of the at least one fourth output transistor T4 may be greater than the width to length ratio of other transistors in the shift register unit except the at least one fourth output transistor T4. That is, among the respective transistors shown in FIG. 5 , the aspect ratio of at least one fourth output transistor T4 may be set relatively large. In this way, the overall output capability of the second output sub-circuit 032 can be enhanced, so as to realize high-frequency driving of the transistor (especially the N-type transistor) coupled to the gate signal terminal in the pixel circuit, so as to satisfy the requirements for driving the coupled light-emitting element of the pixel circuit. driving demand.
- the width to length ratio of each fourth output transistor T4 may be the same.
- the width to length ratio of each fourth output transistor T4 may also be different.
- the transistor coupled to the pull-up power terminal VGH may be a P-type transistor
- the transistor directly coupled to the pull-down power terminal VGL may be an N-type transistor.
- the transistor of the third input transistor M3 coupled to the second input transistor M2 is an N-type transistor
- the transistor of the transistor M4 is a P-type transistor.
- the transistor coupled to the seventh input transistor M7 is an N-type transistor
- the transistor coupled to the fifth input transistor M5 is a P-type transistor
- the transistor coupled between the fourth node N4 and the third output transistor T3 is an N-type transistor.
- each transistor included in the first input sub-circuit 021 may be called a latch, and combined with the eighth input transistor M8 may be called a clock latch.
- the structure composed of each transistor included in the second input sub-circuit 022 and the ninth input transistor M9 may also be called a latch, and in combination with the tenth input transistor M10 may also be called a clock latch.
- the first input circuit 01 and the second input circuit 02 described in the embodiments of the present disclosure may actually include two clock latches.
- the two clock latches can write a pulse signal with a width of 2H to the third node N3 based on the first clock signal provided by the first clock terminal CKV1 and the input control signal provided by the input control terminal CSTV, that is, at A pulse with a width of 2H is formed at the third node N3, and H refers to the unit of the pulse width.
- the first output sub-circuit 031 may write a pulse signal with a width of 1H to the fourth node N4 based on the pulse signal with a width of 2H.
- the first output sub-circuit 031 can shift a pulse signal with a width of 2H to a pulse signal with a width of 1H.
- a pulse signal with a width of 1H can be formed at the output terminal OUT, and the potential of the pulse signal formed at the output terminal OUT is exactly opposite to that at the fourth node N4.
- the shift register unit described in the embodiment of the present disclosure only includes a plurality of CMOS transistors, P-type transistors and N-type transistors, but does not include any capacitors.
- a logic circuit eg, the clock latch described above
- the control manner of the shift register unit described in the embodiment of the present disclosure is relatively simple.
- the embodiments of the present disclosure provide a shift register unit, in which the first input circuit can be controlled by the first clock signal provided by the first clock terminal and the potential of the second node , respectively control the potential of the first node and the potential of the third node.
- the second input circuit can control the potential of the second node under the control of the first clock signal, the input control signal provided by the input control terminal, the potential of the third node and the potential of the first node.
- the output circuit can transmit a high-level pull-up power signal or a low-level pull-down power signal to the output end under the control of the third node.
- FIG. 6 is a flowchart of a method for driving a shift register unit provided by an embodiment of the present disclosure, which can be used to drive the shift register unit shown in any of FIGS. 1 to 5 . As shown in Figure 6, the method may include:
- Step 601 in the input stage, in response to the first clock signal provided by the first clock terminal, the first input circuit controls the pull-down power terminal to conduct with the first node.
- the second input circuit controls the pull-down power terminal to conduct with the second node in response to the input control signal and the first clock signal provided by the input control terminal.
- the first input circuit also controls the pull-up power supply terminal to conduct with the third node in response to the potential of the second node.
- Step 602 In the output stage, the first input circuit controls the pull-up power supply terminal to conduct with the first node in response to the first clock signal, and the second input circuit controls the pull-down power supply in response to the potential of the first node and the potential of the third node The first input circuit also controls the pull-up power terminal to conduct with the third node in response to the potential of the second node.
- the output circuit controls the pull-up power supply terminal to conduct with the output terminal in response to the potential of the third node and the second clock signal provided by the second clock terminal.
- Step 603 In the pull-down stage, the first input circuit controls the pull-down power terminal to conduct with the first node in response to the first clock signal, and the second input circuit controls the pull-up power terminal to connect with the first node in response to the potential of the first node and the input control signal.
- the second node is turned on, the first input circuit also controls the pull-down power supply terminal to conduct with the third node in response to the potential of the second node, and the output circuit controls the pull-down power supply terminal and the third node in response to the potential of the third node and the second clock signal. The output is turned on.
- FIG. 7 is a timing diagram of each signal terminal and each node in a shift register unit provided by an embodiment of the present disclosure.
- the potential of the first clock signal provided by the first clock terminal CKV1 is the first potential.
- the N-type transistor in the eighth input transistor M8, the N-type transistor in the ninth input transistor M9 and the second input transistor M2 are all turned on, and the fifth input transistor M5 is turned off.
- the pull-down power terminal VGL is connected to the first node N1, and the pull-down power signal of the second potential is transmitted to the first node N1 through the N-type transistor in the eighth input transistor M8 and the N-type transistor in the ninth input transistor M9.
- the fourth input transistor M4 and the P-type transistors in the first input transistor M1 are both turned on, and the seventh input transistor M7 is turned off.
- the pull-up power supply signal of the first potential is transmitted to the gate of the second input transistor M2 through the first input transistor M1.
- the second input transistor M2 remains on.
- the potential of the input control signal provided by the input control terminal CSTV is the first potential, and the N-type transistor in the third input transistor M3 is turned on.
- the pull-down power terminal VGL is turned on with the second node N2, and the pull-down power signal of the second potential can be transmitted to the second node N2 through the N-type transistors of the second input transistor M2 and the third input transistor M3 which are turned on.
- the P-type transistor in the tenth input transistor M10 is turned on, the pull-up power supply terminal VGH and the third node N3 are turned on, and the pull-up power supply signal of the first potential can be transmitted to the third node through the P-type transistor in the tenth input transistor M10 N3.
- Both the N-type transistor and the third output transistor T3 in the sixth input transistor M6 are turned on, and the second output transistor T2 is turned off.
- the potential of the second clock signal provided by the second clock terminal CKV2 is the second potential, and the P-type transistor in the first output transistor T1 is turned on.
- the pull-up power terminal VGH is turned on with the fourth node N4, and the pull-up power signal of the first potential is transmitted to the fourth node N4 through the P-type transistor in the first output transistor T1.
- the N-type transistor in the first fourth output transistor T4 is turned on, and the pull-down power supply signal of the second potential is transmitted to the gate of the second fourth output transistor T4 through the turned-on N-type transistor.
- the P-type transistor in the second fourth output transistor T4 is turned on, and the pull-up power supply signal of the first potential is transmitted to the gate of the third fourth output transistor T4 through the turned-on P-type transistor.
- the N-type transistor in the third and fourth output transistor T4 is turned on, and the pull-down power supply signal of the second potential is transmitted to the output terminal OUT through the turned-on N-type transistor.
- the potential of the first clock signal jumps to the second potential
- the P-type transistor in the eighth input transistor M8, the P-type transistor in the ninth input transistor M9 and the fifth input transistor M5 are all turned on, the second The input transistor M2 is turned off.
- the pull-up power terminal VGH is connected to the first node N1, and the pull-up power signal of the first potential is transmitted to the first node N1 through the P-type transistor in the eighth input transistor M8 and the P-type transistor in the ninth input transistor M9.
- the N-type transistor and the seventh input transistor M7 in the first input transistor M1 are both turned on, and the fourth input transistor M4 is turned off.
- the pull-down power supply signal of the second potential is transmitted to the gate of the second input transistor M2 through the N-type transistor in the first input transistor M1.
- the second input transistor M2 remains on.
- the potential of the input control signal jumps to the second potential.
- the P-type transistor in the third input transistor M3 is turned on. Since the potential of the third node N3 is the first potential, the N-type transistor, the third output transistor T3 and the second output transistor T2 in the sixth input transistor M6 are all kept on. And because the seventh input transistor M7 is turned on, the pull-down power supply terminal VGH and the second node N2 remain conductive.
- the pull-down power supply signal of the second potential may be transmitted to the second node N2 through the N-type transistor of the seventh input transistor M7 and the sixth input transistor M6, which are turned on.
- the P-type transistor in the tenth input transistor M10 is kept on, the pull-up power supply terminal VGH and the third node N3 are kept on, and the pull-up power supply signal of the first potential continues to be transmitted to the third node through the P-type transistor in the tenth input transistor M10.
- the N-type transistor and the third output transistor T3 in the sixth input transistor M6 are kept on, and the second output transistor T2 is turned off.
- the potential of the second clock signal jumps to the first potential, and the N-type transistor in the first output transistor T1 is turned on.
- the pull-down power terminal VGL is connected to the fourth node N4, and the pull-down power signal of the second potential is transmitted to the fourth node N4 through the turned-on third output transistor T3 and the N-type transistor in the first output transistor T1.
- the P-type transistor in the first fourth output transistor T4 is turned on, and the pull-up power supply signal of the first potential is transmitted to the gate of the second fourth output transistor T4 through the turned-on P-type transistor.
- the N-type transistor in the second fourth output transistor T4 is turned on, and the pull-down power signal of the second potential is transmitted to the gate of the third fourth output transistor T4 through the turned-on N-type transistor.
- the P-type transistor in the third and fourth output transistor T4 is turned on, and the pull-up power supply signal of the first potential is transmitted to the output terminal OUT through the turned-on P-type transistor.
- the potential of the first clock signal jumps to the first potential.
- the N-type transistor in the eighth input transistor M8, the N-type transistor in the ninth input transistor M9 and the second input transistor M2 are all turned on, and the fifth input transistor M5 is turned off.
- the pull-down power terminal VGL is connected to the first node N1, and the pull-down power signal of the second potential is transmitted to the first node N1 through the N-type transistor in the eighth input transistor M8 and the N-type transistor in the ninth input transistor M9.
- the fourth input transistor M4 and the P-type transistors in the first input transistor M1 are both turned on, and the seventh input transistor M7 is turned off.
- the pull-up power supply signal of the first potential is transmitted to the gate of the second input transistor M2 through the first input transistor M1.
- the second input transistor M2 remains on.
- the potential of the input control signal is maintained at the second potential, and the P-type transistor in the third input transistor M3 is turned on.
- the pull-up power terminal VGH is turned on with the second node N2, and the pull-up power signal of the first potential can be transmitted to the second node N2 through the P-type transistors in the fourth input transistor M4 and the third input transistor M3 that are turned on.
- the N-type transistor in the tenth input transistor M10 is turned on, the pull-down power terminal VGL is connected to the third node N3, and the pull-down power signal of the second potential can be transmitted to the third node N3 through the N-type transistor in the tenth input transistor M10.
- the P-type transistor and the second output transistor T2 in the sixth input transistor M6 are both turned on, and the third output transistor T3 is turned off.
- the potential of the second clock signal jumps to the second potential, and the P-type transistor in the first output transistor T1 is turned on.
- the pull-up power terminal VGH is turned on with the fourth node N4, and the pull-up power signal of the first potential is transmitted to the fourth node N4 through the P-type transistor in the first output transistor T1 and the second output transistor T2.
- the N-type transistor in the first fourth output transistor T4 is turned on, and the pull-down power supply signal of the second potential is transmitted to the gate of the second fourth output transistor T4 through the turned-on N-type transistor.
- the P-type transistor in the second fourth output transistor T4 is turned on, and the pull-up power supply signal of the first potential is transmitted to the gate of the third fourth output transistor T4 through the turned-on P-type transistor.
- the N-type transistor in the third and fourth output transistor T4 is turned on, and the pull-down power supply signal of the second potential is transmitted to the output terminal OUT through the turned-on N-type transistor.
- FIG. 8 also shows a timing diagram of signal terminals of three cascaded shift register units. Referring to FIG. 8 , it can be seen that the potentials at the output terminals OUT1 , OUT2 and OUT3 of the three shift register units may be the first potential in sequence.
- the embodiments of the present disclosure provide a method for driving a shift register unit, in which the first input circuit can be controlled by the first clock signal provided by the first clock terminal and the potential of the second node , respectively control the potential of the first node and the potential of the third node.
- the second input circuit can control the potential of the second node under the control of the first clock signal, the input control signal provided by the input control terminal, the potential of the third node and the potential of the first node.
- the output circuit can transmit a high-level pull-up power signal or a low-level pull-down power signal to the output end under the control of the third node.
- FIG. 9 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present disclosure.
- the gate driving circuit may include: at least two cascaded shift register units 00 as shown in any one of FIGS. 1 to 5 .
- the gate driving circuit can be connected to two clock signal lines: a first clock signal line ckv1 and a second clock signal line ckv2.
- the first clock terminal CKV1 of the odd-numbered stage shift register unit 00 can be coupled to the first clock signal line ckv1, and the second clock terminal CKV2 of the odd-numbered stage shift register unit 00 can be connected to the second clock terminal CKV2.
- the clock signal line ckv2 is coupled.
- the first clock terminal CKV1 of the even-numbered stage shift register unit 00 may be coupled to the second clock signal line ckv2, and the second clock terminal CKV2 of the even-numbered stage shift register unit 00 may be coupled to the first clock signal line ckv1.
- the two first clock terminals CKV1 included in every two adjacent shift register units 00 may be alternately coupled to the first clock signal line ckv1 and the second clock signal line ckv2, and every two adjacent shift register units 00 are shifted
- the two second clock terminals CKV2 included in the register unit 00 may be alternately coupled to the first clock signal line ckv1 and the second clock signal line ckv2.
- the input control terminal CSTV of each stage shift register unit 00 may be connected with the output terminal OUT of the cascaded previous stage shift register unit 00 coupled (not shown in Figure 9). In this way, the purpose of cascading is achieved.
- FIG. 10 is a display device provided by an embodiment of the present disclosure. As shown in FIG. 10 , the display device may include: a display panel 100 , and a gate driving circuit 000 as shown in FIG. 9 .
- the display panel 100 may include a plurality of pixel circuits.
- the gate driving circuit 000 can be coupled to the gate signal terminals in each pixel circuit, and the gate driving circuit 000 can be used to provide gate driving signals for the gate signal terminals.
- a plurality of pixel circuits in the display panel 100 may be arranged in an array.
- the output terminal of each shift register unit can be coupled to the gate signal terminal coupled to each pixel circuit located in the same row, and the gate signal terminal coupled to each shift register unit on different lines.
- the gate signal terminals coupled to the pixel circuits in the same row can be coupled to a gate line, and the gate line can be further coupled to the output terminal of a shift register unit.
- the gate driving circuit 000 may be disposed on the display panel 100, that is, integrated with the display panel, so that the design of the narrow frame of the display device can be facilitated.
- the transistor coupled to the gate signal terminal may be an N-type indium gallium zinc oxide (IGZO) transistor.
- IGZO indium gallium zinc oxide
- FIG. 11 shows a schematic structural diagram of a pixel circuit.
- the pixel circuit shown includes a first switch transistor K1, a second switch transistor K2, a third switch transistor K3, a fourth switch transistor K4, a fifth switch transistor K5, a sixth switch transistor K6, The seventh switch transistor K7 and the storage capacitor C1.
- the gate of the first switch transistor K1 is coupled to the reset control terminal RST(n-1), the first pole of the first switch transistor K1 is coupled to the reset signal terminal Vinit, and the second pole of the first switch transistor K1 is connected to the reset signal terminal Vinit.
- the anode of the light emitting element L1 is coupled.
- the cathode of the light-emitting element L1 may also be coupled to the power supply terminal VSS.
- the first switching transistor K1 can be used to transmit the reset signal provided by the reset signal terminal Vinit to the anode of the light-emitting element L1 in response to the reset control signal provided by the reset control terminal RST(n-1).
- the gate of the second switch transistor K2 is coupled to the switch control terminal GATE(n-1), the first pole of the second switch transistor K2 is coupled to the second pole of the first switch transistor K1, and the second pole of the second switch transistor K2
- the diode is coupled to the gate of the third switching transistor K3.
- the second switch transistor K2 may be used to control the gate of the third switch transistor K3 to conduct with the second pole of the first switch transistor K1 in response to a signal provided by the switch control terminal GATE(n-1).
- the gate of the fourth switch transistor K4 and the gate of the seventh switch transistor K7 may both be coupled to the gate signal terminal GATE(n), the first pole of the fourth switch transistor K4 is coupled to the data signal terminal DATA, the fourth The second pole of the switch transistor K4 is coupled to the second pole of the third switch transistor K3.
- the first pole of the seventh switch transistor K7 may be coupled with the first pole of the third switch transistor K3, and the second pole of the seventh switch transistor K7 may be coupled with the gate of the third switch transistor K3.
- the fourth switching transistor K4 may be used to transmit the data signal provided by the data signal terminal DATA to the second pole of the third switching transistor K3 in response to the gate driving signal provided by the gate signal terminal GATE(n).
- the seventh switch transistor K7 may be used to control the on-off of the first pole of the third switch transistor K3 and the gate of the third switch transistor K3 in response to the gate driving signal.
- the gate of the fifth switching transistor K5 and the gate of the sixth switching transistor K6 can both be coupled to the light-emitting control terminal EM, the first pole of the fifth switching transistor K5 can be coupled to the driving power terminal VDD, and the fifth switching transistor K5
- the second pole of the can be coupled to the first pole of the third switching transistor K3.
- the first pole of the sixth switching transistor K6 may be coupled with the second pole of the third switching transistor K3, and the second pole of the sixth switching transistor K6 may be coupled with the anode of the light emitting element L1.
- the fifth switch transistor K5 can be used to transmit the driving power signal provided by the driving power terminal VDD to the first electrode of the third switching transistor K3 in response to the lighting control signal provided by the lighting control terminal EM.
- the sixth switch transistor K6 may be used to control the connection between the second pole of the third switch transistor K3 and the anode of the light-emitting element L1 in response to the light-emitting control signal.
- One end of the storage capacitor C1 may be coupled to the gate of the third switching transistor K3, and the other end of the storage capacitor C1 may be coupled to the driving power terminal VDD.
- the fourth switching transistor K4 and the seventh switching transistor K7 coupled to the gate signal terminal GATE(n) may both be N-type transistors, and may both be transistors made of IGZO material.
- the fifth switch transistor K5 and the sixth switch transistor K6 coupled to the light-emitting control terminal EM may both be N-type transistors.
- the remaining transistors including the first switching transistor K1 , the second switching transistor K2 and the third switching transistor K3 ) may all be P-type transistors.
- FIG. 12 also shows a timing diagram of each signal terminal in the pixel circuit.
- the process of driving the light-emitting element L1 to emit light may include: a reset stage t01, a writing stage t02 and a light-emitting stage t03.
- the high potential represents the effective potential.
- the potential of the signal provided by GATE(n-1) and the potential of the signal provided by RST(n-1) may be effective potentials.
- the first switching transistor K1 and the second switching transistor K2 are turned on, and the reset signal terminal Vinit can transmit a reset signal to the gate of the third switching transistor K3 and the anode of the light-emitting element L1.
- the potential of the gate driving signal provided by the gate signal terminal GATE(n) may be an effective potential.
- the fourth switch transistor K4 and the seventh switch transistor K7 are turned on, and the data signal terminal DATA can transmit a data signal to the gate of the third switch transistor K3.
- the potential of the light-emitting control signal provided by the light-emitting control terminal EM is an effective potential.
- the fifth switching transistor K5 and the sixth switching transistor K6 are turned on, and the third switching transistor K3 is also kept turned on at this stage.
- the driving power terminal VDD can transmit the driving power signal to the first pole of the third switching transistor K3, and the third switching transistor K3 can transmit the driving power signal to the first pole of the sixth switching transistor K6 based on the potential of its gate and the potential of the first pole drive current.
- the sixth switching transistor K6 then transmits the driving current to the light-emitting element L1, and the light-emitting element L1 emits light.
- the timing at the output terminal OUT of the shift register unit may be consistent with the timing at the gate signal terminal GATE(n) shown in FIG. 12 .
- the gate of the N-type IGZO transistor needs to respond to a strong driving signal to work reliably.
- the drive capability of the signal output from the shift register unit of the related art to the gate signal terminal is weak, resulting in the structure shown in FIG. 11 , the drive capability of the fourth switch transistor K4 is weak, and the data signal cannot be reliably transmitted to the third switch.
- the second pole of the transistor K3 which in turn makes it impossible to reliably drive the light-emitting element L1 to emit light.
- the shift register unit due to its strong output capability, it can ensure that the fourth switch transistor K4 reliably transmits the data signal to the second pole of the third switch transistor K3, thereby ensuring that the light-emitting element L1 is The luminous effect is better.
- FIG. 11 only schematically shows an optional 7T1C (ie, 7 transistors and 1 capacitor) pixel circuit.
- the embodiments of the present disclosure do not limit the structure of the pixel circuit driven by the shift register unit, for example, it can also be used to drive the pixel circuit of the 6T1C structure.
- the transistors in the pixel circuits described in the embodiments of the present disclosure may also be low temperature polycrystalline silicon oxide (low temperature polycrystalline oxide, LTPO) transistors.
- low temperature polycrystalline silicon oxide low temperature polycrystalline oxide, LTPO
- the display devices provided by the embodiments of the present disclosure may be: an active-matrix organic light-emitting diode (AMOLED) display device, an organic light-emitting diode (OLED) display device, and a liquid crystal display device Any product or component with display function.
- AMOLED active-matrix organic light-emitting diode
- OLED organic light-emitting diode
- liquid crystal display device Any product or component with display function.
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Abstract
Description
Claims (15)
- 一种移位寄存器单元,所述移位寄存器单元包括:第一输入电路,分别与第一时钟端、第一节点、第二节点、第三节点、上拉电源端和下拉电源端耦接,所述第一输入电路用于响应于所述第一时钟端提供的第一时钟信号,控制所述上拉电源端与所述第一节点的通断,并控制所述下拉电源端与所述第一节点的通断;以及用于响应于所述第二节点的电位,控制所述上拉电源端与所述第三节点的通断,并控制所述下拉电源端与所述第三节点的通断;第二输入电路,分别与所述第一节点、所述第二节点、所述第三节点、所述上拉电源端、所述下拉电源端、输入控制端和所述第一时钟端耦接,所述第二输入电路用于响应于所述第一节点的电位、所述第三节点的电位、所述第一时钟信号和所述输入控制端提供的输入控制信号,控制所述上拉电源端与所述第二节点的通断,并控制所述下拉电源端与所述第二节点的通断;以及输出电路,分别与所述上拉电源端、所述下拉电源端、所述第三节点、第二时钟端和输出端耦接,所述输出电路用于响应于所述第三节点的电位和所述第二时钟端提供的第二时钟信号,控制所述上拉电源端与所述输出端的通断,并控制所述下拉电源端与所述输出端的通断。
- 根据权利要求1所述的移位寄存器单元,其中,所述输出电路包括:第一输出子电路和第二输出子电路;所述第一输出子电路分别与所述第二时钟端、所述第三节点、所述上拉电源端、所述下拉电源端和第四节点耦接,所述第一输出子电路用于响应于所述第二时钟信号和所述第三节点的电位,控制所述上拉电源端与所述第四节点的通断,并控制所述下拉电源端与所述第四节点的通断;所述第二输出子电路分别与所述第四节点、所述上拉电源端、所述下拉电源端和所述输出端耦接,所述第二输出子电路用于响应于所述第四节点的电位,控制所述上拉电源端与所述输出端的通断,并控制所述下拉电源端与所述输出端的通断。
- 根据权利要求2所述的移位寄存器单元,其中,所述第一输出子电路包括:第一输出晶体管、第二输出晶体管和第三输出晶体管,所述第一输出晶体管为互补型金属氧化物半导体CMOS晶体管;所述第一输出晶体管的栅极与所述第二时钟端耦接,所述第一输出晶体管的一个第一极和所述第二输出晶体管的第一极均与所述上拉电源端耦接,所述第一输出晶体管的另一个第一极与所述第三输出晶体管的第二极耦接,所述第一输出晶体管的第二极和所述第二输出晶体管的第二极均与所述第四节点耦接,所述第二输出晶体管的栅极和所述第三输出晶体管的栅极均与所述第三节点耦接,所述第三输出晶体管的第一极与所述下拉电源端耦接。
- 根据权利要求2所述的移位寄存器单元,其中,所述第二输出子电路包括:串联在所述第四节点和所述输出端之间的奇数个第四输出晶体管;每个所述第四输出晶体管均为CMOS晶体管,且每个所述第四输出晶体管的两个第一极分别与所述上拉电源端和所述下拉电源端耦接。
- 根据权利要求4所述的移位寄存器单元,其中,所述第二输出子电路包括:三个所述第四输出晶体管;其中,第一个所述第四输出晶体管的栅极与所述第四节点耦接,第一个所述第四输出晶体管的第二极与第二个所述第四输出晶体管的栅极耦接,第二个所述第四输出晶体管的第二极与第三个所述第四输出晶体管的栅极耦接,第三个所述第四输出晶体管的第二极与所述输出端耦接。
- 根据权利要求4所述的移位寄存器单元,其中,至少一个第四输出晶体管的宽长比,大于所述移位寄存器单元中除所述至少一个第四输出晶体管之外的其他晶体管的宽长比。
- 根据权利要求1至6任一所述的移位寄存器单元,其中,所述第二输入电路包括:第一输入子电路和第二输入子电路;所述第一输入子电路分别与所述第一节点、所述第一时钟端、所述输入控制端、所述上拉电源端、所述下拉电源端和所述第二节点耦接,所述第一输入 子电路用于响应于所述第一节点的电位、所述输入控制信号和所述第一时钟信号,控制所述上拉电源端与所述第二节点的通断,并控制所述下拉电源端与所述第二节点的通断;所述第二输入子电路分别与所述第一时钟端、所述第一节点、所述第二节点、所述第三节点、所述上拉电源端和所述下拉电源端耦接,所述第二输入子电路用于响应于所述第一节点的电位、所述第三节点的电位和所述第一时钟信号,控制所述上拉电源端与所述第二节点的通断,并控制所述下拉电源端与所述第二节点的通断。
- 根据权利要求7所述的移位寄存器单元,其中,所述第一输入子电路包括:第一输入晶体管、第二输入晶体管、第三输入晶体管和第四输入晶体管;所述第一输入晶体管和所述第三输入晶体管均为CMOS晶体管;所述第一输入晶体管的栅极与所述第一节点耦接,所述第一输入晶体管的两个第一极分别与所述上拉电源端和所述下拉电源端耦接,所述第一输入晶体管的第二极与所述第二输入晶体管的栅极耦接,且所述第二输入晶体管的栅极还与所述第一时钟端耦接;所述第二输入晶体管的第一极与所述下拉电源端耦接,所述第二输入晶体管的第二极与所述第三输入晶体管的一个第一极耦接;所述第三输入晶体管的另一个第一极与所述第四输入晶体管的第二极耦接,所述第三输入晶体管的栅极与所述输入控制端耦接,所述第三输入晶体管的第二极与所述第二节点耦接;所述第四输入晶体管的栅极与所述第一节点耦接,所述第四输入晶体管的第一极与所述上拉电源端耦接。
- 根据权利要求7所述的移位寄存器单元,其中,所述第二输入子电路包括:第五输入晶体管、第六输入晶体管和第七输入晶体管;所述第六输入晶体管为CMOS晶体管;所述第五输入晶体管的栅极与所述第一时钟端耦接,所述第五输入晶体管第一极与所述上拉电源端耦接,所述第五输入晶体管第二极与所述第六输入晶体管的一个第一极耦接;所述第六输入晶体管的另一个第一极与所述第七输入晶体管的第二极耦接,所述第六输入晶体管的栅极与所述第三节点耦接;所述第七输入晶体管的第一极与所述下拉电源端耦接,所述第七输入晶体管的栅极与所述第一节点耦接。
- 根据权利要求1至9任一所述的移位寄存器单元,其中,所述第一输入电路包括:第三输入子电路和第四输入子电路;所述第三输入子电路分别与所述第一时钟端、所述上拉电源端、所述下拉电源端和所述第一节点耦接,所述第三输入子电路用于响应于所述第一时钟信号,控制所述上拉电源端与所述第一节点的通断,并控制所述下拉电源端与所述第一节点的通断;所述第四输入子电路分别与所述第二节点、所述上拉电源端、所述下拉电源端和所述第三节点耦接,所述第四输入子电路用于响应于所述第二节点的电位,控制所述上拉电源端与所述第三节点的通断,并控制所述下拉电源端与所述第三节点的通断。
- 根据权利要求10所述的移位寄存器单元,其中,所述第三输入子电路包括:第八输入晶体管和第九输入晶体管;所述第四输入子电路包括:第十输入晶体管;所述第八输入晶体管、所述第九输入晶体管和所述第十输入晶体管均为CMOS晶体管;所述第八输入晶体管的栅极和所述第九输入晶体管的栅极均与所述第一时钟端耦接,所述第八输入晶体管的两个第一极和所述第九输入晶体管的两个第一极均分别与所述上拉电源端和所述下拉电源端耦接,所述第八输入晶体管的第二极和所述第九输入晶体管的第二极均与所述第一节点耦接;所述第十输入晶体管的栅极与所述第二节点耦接,所述第十输入晶体管的两个第一极分别与所述上拉电源端和所述下拉电源端耦接,所述第十输入晶体管的第二极与所述第三节点耦接。
- 一种移位寄存器单元的驱动方法,其中,用于驱动如权利要求1至11任一所述的移位寄存器单元;所述方法包括:输入阶段,第一输入电路响应于第一时钟端提供的第一时钟信号,控制下拉电源端与第一节点导通;第二输入电路响应于输入控制端提供的输入控制信号和所述第一时钟信号,控制所述下拉电源端与第二节点导通;所述第一输入电路还响应于所述第二节点的电位,控制上拉电源端与第三节点导通;输出阶段,所述第一输入电路响应于所述第一时钟信号,控制所述上拉电源端与所述第一节点导通,所述第二输入电路响应于所述第一节点的电位和所述第三节点的电位,控制所述下拉电源端与所述第二节点导通,所述第一输入电路还响应于所述第二节点的电位,控制所述上拉电源端与所述第三节点导通;输出电路响应于所述第三节点的电位和第二时钟端提供的第二时钟信号,控制所述上拉电源端与所述输出端导通;下拉阶段,所述第一输入电路响应于所述第一时钟信号,控制所述下拉电源端与所述第一节点导通,所述第二输入电路响应于所述第一节点的电位和所述输入控制信号,控制所述上拉电源端与所述第二节点导通,所述第一输入电路还响应于所述第二节点的电位,控制所述下拉电源端与所述第三节点导通,所述输出电路响应于所述第三节点的电位和所述第二时钟信号,控制所述下拉电源端与所述输出端导通。
- 一种栅极驱动电路,其中,所述栅极驱动电路包括:至少两个级联的如权利要求1至11任一所述的移位寄存器单元;奇数级移位寄存器单元的第一时钟端与第一时钟信号线耦接,奇数级移位寄存器单元的第二时钟端与第二时钟信号线耦接;偶数级移位寄存器单元的第一时钟端与第二时钟信号线耦接,偶数级移位寄存器单元的第二时钟端与第一时钟信号线耦接。
- 一种显示装置,其中,所述显示装置包括:显示面板,以及如权利要求13所述的栅极驱动电路,所述显示面板包括多个像素电路;所述栅极驱动电路与所述像素电路中的栅极信号端耦接,所述栅极驱动电路用于为所述栅极信号端提供栅极驱动信号。
- 根据权利要求14所述的显示装置,其中,所述像素电路包括:第一开关晶体管、第二开关晶体管、第三开关晶体管、第四开关晶体管、第五开关晶体管、第六开关晶体管、第七开关晶体管和存储电容;所述第一开关晶体管的栅极与复位控制端耦接,所述第一开关晶体管的第一极与复位信号端耦接,所述第一开关晶体管的第二极与所述第二开关晶体管的第一极、所述第六开关晶体管的第二极以及发光元件的阳极耦接;所述第二开关晶体管的栅极与开关控制端耦接,所述第二开关晶体管的第二极与所述第三开关晶体管的栅极耦接;所述第五开关晶体管的栅极和所述第六开关晶体管的栅极均与发光控制端耦接,所述第五开关晶体管的第一极与驱动电源端耦接,所述第五开关晶体管的第二极与所述第三开关晶体管的第一极耦接;所述第六开关晶体管的第一极与所述第三开关晶体管的第二极耦接;所述第四开关晶体管的栅极和所述第七开关晶体管的栅极均与所述栅极信号端耦接;所述第四开关晶体管的第一极与数据信号端耦接,所述第四开关晶体管的第二极与所述第三开关晶体管的第二极耦接;所述第七开关晶体管的第一极与所述第三开关晶体管的第一极耦接,所述第七开关晶体管的第二极与所述第三开关晶体管的栅极耦接;所述存储电容的一端与所述第三开关晶体管的栅极耦接,所述存储电容的另一端与所述驱动电源端耦接;其中,所述第四开关晶体管和所述第七开关晶体管均为N型铟镓锌氧化物IGZO晶体管,且所述栅极驱动电路中移位寄存器单元的输出端与所述第四开关晶体管的栅极和所述第七开关晶体管的栅极耦接。
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