WO2022213579A1 - 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置 - Google Patents

移位寄存器单元及其驱动方法、栅极驱动电路、显示装置 Download PDF

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Publication number
WO2022213579A1
WO2022213579A1 PCT/CN2021/126087 CN2021126087W WO2022213579A1 WO 2022213579 A1 WO2022213579 A1 WO 2022213579A1 CN 2021126087 W CN2021126087 W CN 2021126087W WO 2022213579 A1 WO2022213579 A1 WO 2022213579A1
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WIPO (PCT)
Prior art keywords
transistor
node
terminal
input
pull
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PCT/CN2021/126087
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English (en)
French (fr)
Inventor
王铸
闫政龙
卢辉
刘珂
石领
陈义鹏
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US17/910,539 priority Critical patent/US20240203316A1/en
Publication of WO2022213579A1 publication Critical patent/WO2022213579A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a shift register unit and a driving method thereof, a gate driving circuit, and a display device.
  • the shift register usually includes a plurality of cascaded shift register units, and each shift register unit is used to drive a row of pixel units.
  • Embodiments of the present disclosure provide a shift register unit and a driving method thereof, a gate driving circuit, and a display device, and the technical solutions are as follows:
  • a shift register unit comprising:
  • a first input circuit respectively coupled to a first clock terminal, a first node, a second node, a third node, a pull-up power supply terminal and a pull-down power supply terminal, the first input circuit is used to respond to the first clock
  • the first clock signal provided by the terminal controls the on-off of the pull-up power terminal and the first node, and controls the on-off of the pull-down power terminal and the first node; and is used for responding to the first node.
  • the potential of the second node controls the on-off of the pull-up power terminal and the third node, and controls the on-off of the pull-down power terminal and the third node;
  • the second input circuit is respectively coupled to the first node, the second node, the third node, the pull-up power terminal, the pull-down power terminal, the input control terminal and the first clock terminal , the second input circuit is configured to control the pull-up in response to the potential of the first node, the potential of the third node, the first clock signal and the input control signal provided by the input control terminal on/off of the power terminal and the second node, and controlling the on/off of the pull-down power terminal and the second node;
  • the output circuit is used for responding to the potential of the third node and the second clock signal provided by the second clock terminal to control the on-off of the pull-up power terminal and the output terminal, and control the on-off of the pull-down power terminal and the output terminal.
  • the output circuit includes: a first output sub-circuit and a second output sub-circuit;
  • the first output sub-circuit is respectively coupled to the second clock terminal, the third node, the pull-up power terminal, the pull-down power terminal and the fourth node, and the first output sub-circuit is used for In response to the second clock signal and the potential of the third node, the on-off of the pull-up power terminal and the fourth node is controlled, and the on-off of the pull-down power terminal and the fourth node is controlled ;
  • the second output sub-circuit is respectively coupled to the fourth node, the pull-up power terminal, the pull-down power terminal and the output terminal, and the second output sub-circuit is used for responding to the fourth node
  • the potential of the node controls the on-off of the pull-up power terminal and the output terminal, and controls the on-off of the pull-down power terminal and the output terminal.
  • the first output sub-circuit includes: a first output transistor, a second output transistor, and a third output transistor, and the first output transistor is a complementary metal-oxide-semiconductor CMOS transistor;
  • the gate of the first output transistor is coupled to the second clock terminal, and a first pole of the first output transistor and a first pole of the second output transistor are both coupled to the pull-up power supply terminal connected, the other first pole of the first output transistor is coupled to the second pole of the third output transistor, and the second pole of the first output transistor and the second pole of the second output transistor are both is coupled to the fourth node, the gate of the second output transistor and the gate of the third output transistor are both coupled to the third node, and the first pole of the third output transistor is connected to the third node.
  • the pull-down power terminal is coupled.
  • the second output sub-circuit includes: an odd number of fourth output transistors connected in series between the fourth node and the output end;
  • Each of the fourth output transistors is a CMOS transistor, and two first electrodes of each of the fourth output transistors are respectively coupled to the pull-up power supply terminal and the pull-down power supply terminal.
  • the second output sub-circuit includes: three of the fourth output transistors;
  • the gate of the first fourth output transistor is coupled to the fourth node, and the second electrode of the first fourth output transistor is coupled to the gate of the second fourth output transistor connected, the second pole of the second fourth output transistor is coupled to the gate of the third fourth output transistor, and the second pole of the third fourth output transistor is coupled to the output terminal catch.
  • the width to length ratio of the at least one fourth output transistor is greater than the width to length ratio of other transistors in the shift register unit except the at least one fourth output transistor.
  • the second input circuit includes: a first input sub-circuit and a second input sub-circuit;
  • the first input sub-circuit is respectively coupled to the first node, the first clock terminal, the input control terminal, the pull-up power terminal, the pull-down power terminal and the second node, so The first input sub-circuit is used to control the on-off of the pull-up power supply terminal and the second node in response to the potential of the first node, the input control signal and the first clock signal, and to control on-off of the pull-down power supply terminal and the second node;
  • the second input sub-circuit is respectively coupled to the first clock terminal, the first node, the second node, the third node, the pull-up power terminal and the pull-down power terminal, so The second input sub-circuit is configured to control the on-off of the pull-up power supply terminal and the second node in response to the potential of the first node, the potential of the third node and the first clock signal, And control the on-off of the pull-down power terminal and the second node.
  • the first input sub-circuit includes: a first input transistor, a second input transistor, a third input transistor and a fourth input transistor; the first input transistor and the third input transistor are both CMOS transistors ;
  • the gate of the first input transistor is coupled to the first node, the two first poles of the first input transistor are respectively coupled to the pull-up power supply terminal and the pull-down power supply terminal, and the first The second pole of an input transistor is coupled to the gate of the second input transistor, and the gate of the second input transistor is further coupled to the first clock terminal;
  • a first pole of the second input transistor is coupled to the pull-down power supply terminal, and a second pole of the second input transistor is coupled to a first pole of the third input transistor;
  • the other first pole of the third input transistor is coupled to the second pole of the fourth input transistor, the gate of the third input transistor is coupled to the input control terminal, and the third input transistor The second pole of is coupled to the second node;
  • the gate of the fourth input transistor is coupled to the first node, and the first electrode of the fourth input transistor is coupled to the pull-up power terminal.
  • the second input sub-circuit includes: a fifth input transistor, a sixth input transistor and a seventh input transistor; the sixth input transistor is a CMOS transistor;
  • the gate of the fifth input transistor is coupled to the first clock terminal, the first pole of the fifth input transistor is coupled to the pull-up power supply terminal, and the second pole of the fifth input transistor is coupled to the pull-up power supply terminal. a first pole of the sixth input transistor is coupled;
  • the other first pole of the sixth input transistor is coupled to the second pole of the seventh input transistor, and the gate of the sixth input transistor is coupled to the third node;
  • the first electrode of the seventh input transistor is coupled to the pull-down power supply terminal, and the gate of the seventh input transistor is coupled to the first node.
  • the first input circuit includes: a third input sub-circuit and a fourth input sub-circuit;
  • the third input sub-circuit is respectively coupled to the first clock terminal, the pull-up power terminal, the pull-down power terminal and the first node, and the third input sub-circuit is used for responding to the a first clock signal, which controls the on-off of the pull-up power terminal and the first node, and controls the on-off of the pull-down power terminal and the first node;
  • the fourth input sub-circuit is respectively coupled to the second node, the pull-up power terminal, the pull-down power terminal and the third node, and the fourth input sub-circuit is used for responding to the first
  • the potential of the second node controls the on-off of the pull-up power terminal and the third node, and controls the on-off of the pull-down power terminal and the third node.
  • the third input sub-circuit includes: an eighth input transistor and a ninth input transistor;
  • the fourth input sub-circuit includes: a tenth input transistor; the eighth input transistor and the ninth input transistor and the tenth input transistor are both CMOS transistors;
  • the gate of the eighth input transistor and the gate of the ninth input transistor are both coupled to the first clock terminal, and the two first poles of the eighth input transistor and the ninth input transistor The two first poles are respectively coupled to the pull-up power supply terminal and the pull-down power supply terminal, and the second pole of the eighth input transistor and the second pole of the ninth input transistor are both connected to the first pole. node coupling;
  • the gate of the tenth input transistor is coupled to the second node, the two first poles of the tenth input transistor are respectively coupled to the pull-up power terminal and the pull-down power terminal, and the first The second pole of the ten-input transistor is coupled to the third node.
  • a method for driving a shift register unit for driving the shift register unit according to the above aspect; the method includes:
  • the first input circuit controls the pull-down power supply terminal to conduct with the first node in response to the first clock signal provided by the first clock terminal;
  • the second input circuit responds to the input control signal provided by the input control terminal and the first node a clock signal to control the pull-down power terminal to conduct with the second node;
  • the first input circuit also controls the pull-up power terminal to conduct with the third node in response to the potential of the second node;
  • the first input circuit controls the pull-up power supply terminal to conduct with the first node in response to the first clock signal
  • the second input circuit responds to the potential of the first node and The potential of the third node controls the pull-down power terminal and the second node to conduct, and the first input circuit also controls the pull-up power terminal and the second node in response to the potential of the second node.
  • the third node is turned on; the output circuit controls the pull-up power supply terminal to be turned on with the output terminal in response to the potential of the third node and the second clock signal provided by the second clock terminal;
  • the first input circuit controls the pull-down power supply terminal to conduct with the first node in response to the first clock signal
  • the second input circuit responds to the potential of the first node and all
  • the input control signal controls the pull-up power terminal and the second node to conduct
  • the first input circuit also controls the pull-down power terminal and the third node in response to the potential of the second node.
  • the output circuit controls the pull-down power supply terminal and the output terminal to be turned on in response to the potential of the third node and the second clock signal.
  • a gate drive circuit comprising: at least two cascaded shift register units according to the above aspects;
  • the first clock terminal of the odd-numbered stage shift register unit is coupled to the first clock signal line, and the second clock terminal of the odd-numbered stage shift register unit is coupled to the second clock signal line;
  • the first clock terminal of the even-numbered stage shift register unit is coupled to the second clock signal line, and the second clock terminal of the even-numbered stage shift register unit is coupled to the first clock signal line.
  • a display device in another aspect, includes: a display panel, and the gate driving circuit according to the above aspect, the display panel includes a plurality of pixel circuits;
  • the gate driving circuit is coupled to a gate signal terminal in the pixel circuit, and the gate driving circuit is used for providing a gate driving signal to the gate signal terminal.
  • the pixel circuit includes: a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor, a fifth switch transistor, a sixth switch transistor, a seventh switch transistor, and a storage capacitor;
  • the gate of the first switch transistor is coupled to the reset control terminal, the first pole of the first switch transistor is coupled to the reset signal terminal, and the second pole of the first switch transistor is coupled to the second switch transistor The first pole of , the second pole of the sixth switching transistor and the anode of the light-emitting element are coupled;
  • the gate of the second switch transistor is coupled to the switch control terminal, and the second pole of the second switch transistor is coupled to the gate of the third switch transistor;
  • the gate of the fifth switching transistor and the gate of the sixth switching transistor are both coupled to the light-emitting control terminal, the first pole of the fifth switching transistor is coupled to the driving power terminal, and the fifth switching transistor
  • the gate of the fourth switch transistor and the gate of the seventh switch transistor are both coupled to the gate signal terminal; the first pole of the fourth switch transistor is coupled to the data signal terminal, and the fourth switch transistor is coupled to the data signal terminal.
  • the second pole of the four-switch transistor is coupled to the second pole of the third switch transistor; the first pole of the seventh switch transistor is coupled to the first pole of the third switch transistor, and the seventh switch transistor the second pole of the transistor is coupled to the gate of the third switching transistor;
  • One end of the storage capacitor is coupled to the gate of the third switching transistor, and the other end of the storage capacitor is coupled to the drive power end;
  • the fourth switch transistor and the seventh switch transistor are both N-type indium gallium zinc oxide IGZO transistors, and the output end of the shift register unit in the gate driving circuit is connected to the output end of the fourth switch transistor.
  • the gate is coupled to the gate of the seventh switching transistor.
  • FIG. 1 is a schematic structural diagram of a shift register unit provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of still another shift register unit provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of still another shift register unit provided by an embodiment of the present disclosure.
  • FIG. 6 is a flowchart of a method for driving a shift register unit provided by an embodiment of the present disclosure
  • FIG. 9 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 12 is a timing diagram of each signal terminal in a pixel circuit provided by an embodiment of the present disclosure.
  • the transistors used in all the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics, and the transistors used in the embodiments of the present disclosure are mainly switching transistors according to their functions in the circuit. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable. In the embodiments of the present disclosure, the source electrode is referred to as the first electrode and the drain electrode is referred to as the second electrode, or the drain electrode is referred to as the first electrode and the source electrode is referred to as the second electrode. According to the form in the drawings, the middle terminal of the transistor is the gate, the signal input terminal is the source, and the signal output terminal is the drain.
  • the switching transistor used in the embodiments of the present disclosure may include any one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level, and turned off when the gate is at a high level , the N-type switching transistor is turned on when the gate is high and turned off when the gate is low.
  • multiple signals in each embodiment of the present disclosure correspond to a first potential and a second potential, and the first potential and the second potential only represent that the potential of the signal has two different state quantities, and do not represent the first potential in the whole text. The potential or the second potential has a specific value.
  • a shift register unit generally includes: an input circuit, an output circuit and a pull-down circuit.
  • the input circuit is coupled to the pull-up node, and the input circuit is used for charging the pull-up node according to the driving signal output by the cascaded upper-stage shift register unit.
  • the output circuit is coupled to the output terminal, and the output circuit is used for outputting a gate driving signal to the output terminal under the control of the pull-up node.
  • the pull-down circuit is respectively coupled to the pull-up node and the output terminal, and the pull-down circuit is used to reduce noise on the pull-up node and the output terminal.
  • FIG. 1 is a schematic structural diagram of a shift register unit provided by an embodiment of the present disclosure.
  • the shift register unit may include: a first input circuit 01, a second input circuit 02 and an output circuit 03.
  • the first input circuit 01 may be coupled to a first clock terminal CKV1 , a first node N1 , a second node N2 , a third node N3 , a pull-up power terminal VGH and a pull-down power terminal VGL, respectively.
  • the first input circuit 01 can be used to control the connection between the pull-up power terminal VGH and the first node N1, and control the pull-down power terminal VGL and the first node N1 in response to the first clock signal provided by the first clock terminal CKV1. on and off.
  • coupling may refer to electrical connection.
  • the first input sub-circuit 01 can control the pull-down power supply terminal VGL to conduct with the first node N1 when the potential of the first clock signal is the first potential, and when the potential of the first clock signal is the second potential,
  • the pull-up power terminal VGH is controlled to be turned on with the first node N1.
  • the pull-up power supply terminal VGH and the first node N1 are turned on, the pull-up power supply signal provided by the pull-up power supply terminal VGH can be transmitted to the first node N1 through the first input sub-circuit 01 .
  • the pull-down power signal provided by the pull-down power terminal VGL can be transmitted to the first node N1 through the first input sub-circuit 01 .
  • the control of the potential of the first node N1 is realized.
  • the first input sub-circuit 01 can also control the on-off of the pull-down power supply terminal VGL and the third node N3 when the potential of the second node N2 is the first potential, and the potential of the second node N2 is the second potential
  • the pull-up power supply terminal VGH and the third node N3 are controlled to be turned on and off.
  • the pull-up power supply terminal VGH and the third node N3 are turned on, the pull-up power supply signal can be transmitted to the third node N3 through the first input sub-circuit 01 .
  • the pull-down power terminal VGL and the third node N3 are turned on, the pull-down power signal can be transmitted to the third node N3 through the first input sub-circuit 01 .
  • the control of the potential of the third node N3 is realized.
  • the potential of the pull-up power signal may be the first potential
  • the potential of the pull-down power signal may be the second potential.
  • the first potential described in the embodiment of the present disclosure may be a high potential relative to the second potential, that is, the first potential relative to the second potential is larger.
  • the first potential ie, high potential
  • the second potential ie, low potential
  • the first potential may be an inactive potential
  • the first potential may be an inactive potential
  • the second potential may be an effective potential.
  • the second input circuit 02 may be coupled to the first node N1, the second node N2, the third node N3, the pull-up power terminal VGH, the pull-down power terminal VGL, the input control terminal CSTV and the first clock terminal CKV1, respectively. catch.
  • the second input circuit 02 can be used to control the pull-up power supply terminal VGH and the second node in response to the potential of the first node N1, the potential of the third node N3, the first clock signal and the input control signal provided by the input control terminal CSTV
  • the on-off of N2 is controlled, and the on-off of the pull-down power supply terminal VGL and the second node N2 is controlled.
  • the second input circuit 02 can control the pull-down power supply terminal VGL to conduct with the second node N2 when the potential of the first clock signal and the potential of the input control signal are both the first potential, and/or, at the first node When the potential of N1 and the potential of the third node N3 are both the first potential, the pull-down power supply terminal VGL is controlled to conduct with the second node N2.
  • the second input circuit 02 can control the pull-up power supply terminal VGH and the second node N2 to conduct when the potential of the first node N1 and the potential of the input control signal are both the second potential, and/or, at the first When the potential of the clock signal and the potential of the third node N3 are both the second potential, the pull-up power supply terminal VGH is controlled to conduct with the second node N2.
  • the pull-up power signal can be transmitted to the second node N2 through the second input circuit 02 .
  • the pull-down power terminal VGL and the second node N2 are turned on, the pull-down power signal can be transmitted to the second node N2 through the second input circuit 02 .
  • the control of the potential of the second node N2 is realized.
  • the output circuit 03 may be coupled to the pull-up power terminal VGH, the pull-down power terminal VGL, the third node N3, the second clock terminal CKV2 and the output terminal OUT, respectively.
  • the output circuit 03 can be used to control the on-off of the pull-up power terminal VGH and the output terminal OUT in response to the potential of the third node N3 and the second clock signal provided by the second clock terminal CKV2, and to control the pull-down power terminal VGL and the output The on-off of the terminal OUT.
  • the output circuit 03 can control the pull-up power supply terminal VGH and the output terminal OUT to conduct. And, the output circuit 03 can control the pull-down power terminal VGL and the output terminal OUT to be turned on when the potential of the third node N3 is the second potential, and/or when the potential of the second clock signal is the first potential.
  • the pull-up power supply terminal VGH and the output terminal OUT when the pull-up power supply terminal VGH and the output terminal OUT are turned on, the pull-up power supply signal can be transmitted to the output terminal OUT through the output circuit 03 .
  • the pull-down power supply terminal VGL and the output terminal OUT are turned on, the pull-down power supply signal can be transmitted to the output terminal OUT through the output circuit 03 .
  • the output terminal OUT can be coupled to the gate signal terminal of the pixel circuit in the display panel to provide the gate signal terminal with a gate driving signal.
  • the transistor coupled to the gate signal terminal in the pixel circuit can be reliably turned on or off in response to the pull-up power signal and the pull-down power signal transmitted by the output terminal OUT.
  • the shift register unit described in the embodiments of the present disclosure only includes an input circuit and an output circuit.
  • the first clock signal provided by the first clock terminal CKV1, the second clock signal provided by the second clock terminal CKV2, and the input control signal provided by the input control terminal CSTV it is possible to reliably transmit a high potential to the output terminal OUT.
  • the shift register unit needs to set fewer signal terminals, and the control process is relatively simple.
  • the embodiments of the present disclosure provide a shift register unit, in which the first input circuit can be controlled by the first clock signal provided by the first clock terminal and the potential of the second node , respectively control the potential of the first node and the potential of the third node.
  • the second input circuit can control the potential of the second node under the control of the first clock signal, the input control signal provided by the input control terminal, the potential of the third node and the potential of the first node.
  • the output circuit can transmit a high-level pull-up power signal or a low-level pull-down power signal to the output end under the control of the third node.
  • FIG. 2 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure.
  • the output circuit 03 may include: a first output sub-circuit 031 and a second output sub-circuit 032 .
  • the first output sub-circuit 031 can be respectively coupled to the second clock terminal CKV2, the third node N3, the pull-up power terminal VGH, the pull-down power terminal VGL and the fourth node N4.
  • the first output sub-circuit 031 can be used to control the on-off of the pull-up power terminal VGH and the fourth node N4, and control the pull-down power terminal VGL and the fourth node N4 in response to the second clock signal and the potential of the third node N3 on and off.
  • the first output sub-circuit 031 can control the pull-down power supply terminal VGL to conduct with the fourth node N4 when the potential of the third node N3 and the potential of the second clock signal are both the first potential, and the third node N3
  • the potential of the second clock signal is the second potential, and/or when the potential of the second clock signal is the second potential, the pull-up power supply terminal VGH is controlled to be turned on with the fourth node N4.
  • the pull-down power terminal VGL and the fourth node N4 are turned on, the pull-down power signal can be transmitted to the fourth node N4 through the first output sub-circuit 031 .
  • the pull-up power signal can be transmitted to the fourth node N4 through the first output sub-circuit 031 .
  • the control of the potential of the fourth node N4 is realized.
  • the second output sub-circuit 032 may be coupled to the fourth node N4, the pull-up power terminal VGH, the pull-down power terminal VGL and the output terminal OUT, respectively.
  • the second output sub-circuit 032 can be used to control the on-off of the pull-up power terminal VGH and the output terminal OUT, and control the on-off of the pull-down power terminal VGL and the output terminal OUT in response to the potential of the fourth node N4.
  • the second output sub-circuit 032 can control the pull-down power supply terminal VGL and the output terminal OUT to be turned on when the potential of the fourth node N4 is the first potential, and control the pull-down power supply terminal VGL and the output terminal OUT when the potential of the fourth node N4 is the second potential
  • the pull-up power supply terminal VGH is connected to the output terminal OUT.
  • the pull-down power supply terminal VGL and the output terminal OUT are turned on, the pull-down power supply signal can be transmitted to the output terminal OUT through the second output sub-circuit 032 .
  • the pull-up power supply terminal VGH and the output terminal OUT are turned on, the pull-up power supply signal can be transmitted to the output terminal OUT through the second output sub-circuit 032 .
  • the control of the potential of the output terminal OUT is realized.
  • FIG. 3 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure.
  • the second input circuit 02 may include: a first input sub-circuit 021 and a second input sub-circuit 022 .
  • the first input sub-circuit 021 can be respectively coupled to the first node N1, the first clock terminal CKV1, the input control terminal CSTV, the pull-up power terminal VGH, the pull-down power terminal VGL and the second node N2.
  • the first input sub-circuit 021 can be used to control the on-off of the pull-up power terminal VGH and the second node N2 in response to the potential of the first node N1, the input control signal and the first clock signal, and to control the pull-down power terminal VGL and the second node N2. On-off of the second node N2.
  • the first input sub-circuit 021 may control the pull-down power supply terminal VGL to conduct with the second node N2 when the potential of the first clock signal and the potential of the input control signal are both the first potential. And, the first input sub-circuit 021 can control the pull-up power supply terminal VGH to conduct with the second node N2 when the potential of the first node N1 and the potential of the input control signal are both the second potential.
  • the pull-up power terminal VGH and the second node N2 are turned on, the pull-up power signal can be transmitted to the second node N2 through the first input sub-circuit 021 .
  • the pull-down power signal can be transmitted to the second node N2 through the first input sub-circuit 021 .
  • the control of the potential of the second node N2 is realized.
  • the second input sub-circuit 022 may be coupled to the first clock terminal CKV1, the first node N1, the second node N2, the third node N3, the pull-up power terminal VGH and the pull-down power terminal VGL, respectively.
  • the second input sub-circuit 022 can be used to control the on-off of the pull-up power supply terminal VGH and the second node N2, and control the pull-down power supply in response to the potential of the first node N1, the potential of the third node N3 and the first clock signal The connection between the terminal VGL and the second node N2.
  • the second input sub-circuit 022 can control the pull-down power supply terminal VGL to conduct with the second node N2 when the potential of the first node N1 and the potential of the third node N3 are both the first potential.
  • the second input sub-circuit 022 can control the pull-up power terminal VGH to conduct with the second node N2 when the potential of the first clock signal and the potential of the third node N3 are both the second potential.
  • the pull-up power terminal VGH and the second node N2 are turned on, the pull-up power signal can be transmitted to the second node N2 through the second input sub-circuit 022 .
  • the pull-down power terminal VGL is turned on with the second node N2, the pull-down power signal can be transmitted to the second node N2 through the second input sub-circuit 022.
  • the control of the potential of the second node N2 is realized.
  • FIG. 4 is a schematic structural diagram of still another shift register unit provided by an embodiment of the present disclosure.
  • the first input circuit 01 includes: a third input sub-circuit 011 and a fourth input sub-circuit 012 .
  • the third input sub-circuit 011 can be respectively coupled to the first clock terminal CKV1, the pull-up power terminal VGH, the pull-down power terminal VGL and the first node N1, and the third input sub-circuit 011 can be used to respond to the first The clock signal controls the on-off of the pull-up power terminal VGH and the first node N1, and controls the on-off of the pull-down power terminal VGL and the first node N1.
  • the third input sub-circuit 011 can control the pull-down power supply terminal VGL to conduct with the first node N1 when the potential of the first clock signal is the first potential, and when the potential of the first clock signal is the second potential,
  • the pull-up power terminal VGH is controlled to be turned on with the first node N1.
  • the pull-down power terminal VGL and the first node N1 are turned on, the pull-down power signal can be transmitted to the first node N1 through the third input sub-circuit 011 .
  • the pull-up power terminal VGH is turned on with the first node N1 , the pull-up power signal can be transmitted to the first node N1 through the third input sub-circuit 011 .
  • the control of the potential of the first node N1 is realized.
  • the fourth input sub-circuit 012 may be coupled to the second node N2, the pull-up power terminal VGH, the pull-down power terminal VGL and the third node N3, respectively.
  • the fourth input sub-circuit 012 can be used to control the on-off of the pull-up power terminal VGH and the third node N3, and control the on-off of the pull-down power terminal VGL and the third node N3 in response to the potential of the second node N2.
  • the fourth input sub-circuit 012 can control the pull-down power supply terminal VGL to conduct with the third node N3 when the potential of the second node N2 is the first potential, and when the potential of the second node N2 is the second potential,
  • the pull-up power supply terminal VGH is controlled to be turned on with the third node N3.
  • the pull-down power signal can be transmitted to the third node N3 through the fourth input sub-circuit 012 .
  • the pull-up power terminal VGH and the third node N3 are turned on, the pull-up power signal can be transmitted to the third node N3 through the fourth input sub-circuit 012 .
  • the control of the potential of the third node N3 is realized.
  • FIG. 5 is a schematic structural diagram of still another shift register unit provided by an embodiment of the present disclosure.
  • the first output sub-circuit 031 may include: a first output transistor T1 , a second output transistor T2 and a third output transistor T3 .
  • the first output transistor may be a complementary metal-oxide-semiconductor (CMOS) transistor.
  • CMOS complementary metal-oxide-semiconductor
  • CMOS transistor refers to a complementary MOS integrated circuit composed of a P-type transistor and an N-type transistor.
  • the CMOS transistor may have one gate, two first poles (also referred to as source) and one drain.
  • the gate of the CMOS transistor receives a high-level signal
  • the N-type transistor it includes is turned on.
  • the signal provided by the signal terminal coupled to the first pole of the N-type transistor can be transmitted to The second pole of the CMOS transistor.
  • the gate of the CMOS transistor When the gate of the CMOS transistor receives a low-level signal, the P-type transistor it includes is turned on. At this time, among the two first poles, the signal provided by the signal terminal coupled to the first pole of the P-type transistor can be transmitted to The second pole of the CMOS transistor.
  • the gate of the first output transistor T1 may be coupled to the second clock terminal CKV2 , and the two first electrodes of the first output transistor T1 may be respectively connected to
  • the pull-up power terminal VGH is coupled to the fourth node N4, and the second pole of the first output transistor T1 may be coupled to the second pole of the second output transistor T2.
  • the first pole of the second output transistor T2 may be coupled to the pull-up power supply terminal VGH, the gate of the second output transistor T2 and the gate of the third output transistor T3 may both be coupled to the third node N3, and the third output transistor The first pole of T3 may be coupled to the pull-down power supply terminal VGL, and the second pole of the third output transistor T3 may be coupled to the fourth node N4.
  • the gate of the first output transistor T1 may be coupled to the second clock terminal CKV2, a first pole of the first output transistor T1 and the first pole of the second output transistor T2 may both be coupled to the pull-up power supply terminal VGH, and the first The other first pole of an output transistor T1 may be coupled to the second pole of the third output transistor T3, and both the second pole of the first output transistor T1 and the second pole of the second output transistor T2 may be connected to the fourth node N4 Coupling, the gate of the second output transistor T2 and the gate of the third output transistor T3 may both be coupled to the third node N3, and the first pole of the third output transistor T3 may be coupled to the pull-down power supply terminal VGL.
  • the second output sub-circuit 032 may include: an odd number of fourth output transistors T4 connected in series between the fourth node N4 and the output terminal OUT.
  • each fourth output transistor T4 may be a CMOS transistor, and the two first poles of each fourth output transistor T4 may be respectively coupled to the pull-up power supply terminal VGH and the pull-down power supply terminal VGL.
  • the second output sub-circuit 032 shown therein includes three fourth output transistors T4 connected in series.
  • the gate of the first fourth output transistor T4 is coupled to the fourth node N4, the second pole of the first fourth output transistor T4 is coupled to the gate of the second fourth output transistor T4, the second
  • the second electrode of the third fourth output transistor T4 is coupled to the gate of the third fourth output transistor T4, and the second electrode of the third fourth output transistor T4 is coupled to the output terminal OUT.
  • the second output sub-circuit 032 can invert the potential of the fourth node N4 and transmit it to the output terminal OUT.
  • inverters can also be used to replace odd-numbered fourth output transistors T4.
  • the function of the second output sub-circuit 032 is to invert the potential of the fourth node N4 and transmit it to the output terminal OUT
  • the three fourth output transistors T4 included in the second output sub-circuit 032 can also be called three-stage buffer (buffer).
  • the first input sub-circuit 021 may include: a first input transistor M1 , a second input transistor M2 , a third input transistor M3 and a fourth input transistor M4 .
  • the first input transistor M1 and the third input transistor M3 may both be CMOS transistors.
  • the gate of the first input transistor M1 may be coupled to the first node N1, the two first poles of the first input transistor M1 may be respectively coupled to the pull-up power supply terminal VGH and the pull-down power supply terminal VGL, and the first input transistor M1
  • the second electrode may be coupled to the gate of the second input transistor M2, and the gate of the second input transistor M2 is further coupled to the first clock terminal CKV1. That is, the second pole of the first input transistor M1 and the first clock terminal CKV1 may be coupled together and coupled to the gate of the second input transistor M2 at the same time.
  • the first electrode of the second input transistor M2 may be coupled to the pull-down power supply terminal VGL, and the second electrode of the second input transistor M2 may be coupled to a first electrode of the third input transistor M3.
  • the other first pole of the third input transistor M3 may be coupled to the second pole of the fourth input transistor M4, the gate of the third input transistor M3 may be coupled to the input control terminal CSTV, and the second pole of the third input transistor M3 The pole may be coupled with the second node N2.
  • the gate of the fourth input transistor M4 may be coupled to the first node N1, and the first pole of the fourth input transistor M4 may be coupled to the pull-up power supply terminal VGH.
  • the second input sub-circuit 022 may include: a fifth input transistor M5 , a sixth input transistor M6 and a seventh input transistor M7 .
  • the sixth input transistor M6 may be a CMOS transistor.
  • the gate of the fifth input transistor M5 may be coupled to the first clock terminal CKV1, the first pole of the fifth input transistor M5 may be coupled to the pull-up power supply terminal VGH, and the second pole of the fifth input transistor M5 may be coupled to the sixth input transistor A first pole of M6 is coupled.
  • the gate of the fifth input transistor M5 may be coupled to the node where the second pole of the first input transistor M1 is coupled to the first clock terminal CKV1, so as to be indirectly coupled to the first clock terminal CKV1. .
  • the other first pole of the sixth input transistor M6 may be coupled with the second pole of the seventh input transistor M7, and the gate of the sixth input transistor M6 may be coupled with the third node N3.
  • the first pole of the seventh input transistor M7 may be coupled to the pull-down power supply terminal VGL, and the gate of the seventh input transistor M7 may be coupled to the first node N1.
  • the third input sub-circuit 011 may include: an eighth input transistor M8 and a ninth input transistor M9.
  • the fourth input sub-circuit 012 may include: a tenth input transistor M10.
  • the eighth input transistor M8, the ninth input transistor M9 and the tenth input transistor M10 may all be CMOS transistors.
  • the gate of the eighth input transistor M8 and the gate of the ninth input transistor M9 may both be coupled to the first clock terminal CKV1, the two first poles of the eighth input transistor M8 and the two first poles of the ninth input transistor M9 The poles may both be coupled to the pull-up power terminal VGH and the pull-down power terminal VGL, respectively.
  • the second pole of the eighth input transistor M8 and the second pole of the ninth input transistor M9 may both be coupled to the first node N1.
  • the gate of the ninth input transistor M9 may be coupled to the node where the second pole of the first input transistor M1 is coupled to the first clock terminal CKV1, so as to be indirectly coupled to the first clock terminal CKV1.
  • the gate of the seventh input transistor M7 may be coupled to the second pole of the ninth input transistor M9, so as to be indirectly coupled to the first node N1.
  • the gate of the tenth input transistor M10 may be coupled to the second node N2, the two first poles of the tenth input transistor M10 may be respectively coupled to the pull-up power terminal VGH and the pull-down power terminal VGL, and the tenth input transistor M10 has a
  • the second pole may be coupled with the third node N3.
  • the shift register unit described in the embodiment of the present disclosure includes a total of 13 P-type transistors (PMOS for short) and 13 N-type transistors (NMOS for short), and a first clock terminal CKV1 needs to be set in total,
  • the second clock terminal CKV2 and an input control terminal CSTV have a total of three control terminals.
  • the embodiments of the present disclosure do not limit the number of transistors included in the shift register unit, and other structures capable of realizing the above functions may also be applicable to the solutions of the embodiments of the present disclosure.
  • the width to length ratio of the at least one fourth output transistor T4 may be greater than the width to length ratio of other transistors in the shift register unit except the at least one fourth output transistor T4. That is, among the respective transistors shown in FIG. 5 , the aspect ratio of at least one fourth output transistor T4 may be set relatively large. In this way, the overall output capability of the second output sub-circuit 032 can be enhanced, so as to realize high-frequency driving of the transistor (especially the N-type transistor) coupled to the gate signal terminal in the pixel circuit, so as to satisfy the requirements for driving the coupled light-emitting element of the pixel circuit. driving demand.
  • the width to length ratio of each fourth output transistor T4 may be the same.
  • the width to length ratio of each fourth output transistor T4 may also be different.
  • the transistor coupled to the pull-up power terminal VGH may be a P-type transistor
  • the transistor directly coupled to the pull-down power terminal VGL may be an N-type transistor.
  • the transistor of the third input transistor M3 coupled to the second input transistor M2 is an N-type transistor
  • the transistor of the transistor M4 is a P-type transistor.
  • the transistor coupled to the seventh input transistor M7 is an N-type transistor
  • the transistor coupled to the fifth input transistor M5 is a P-type transistor
  • the transistor coupled between the fourth node N4 and the third output transistor T3 is an N-type transistor.
  • each transistor included in the first input sub-circuit 021 may be called a latch, and combined with the eighth input transistor M8 may be called a clock latch.
  • the structure composed of each transistor included in the second input sub-circuit 022 and the ninth input transistor M9 may also be called a latch, and in combination with the tenth input transistor M10 may also be called a clock latch.
  • the first input circuit 01 and the second input circuit 02 described in the embodiments of the present disclosure may actually include two clock latches.
  • the two clock latches can write a pulse signal with a width of 2H to the third node N3 based on the first clock signal provided by the first clock terminal CKV1 and the input control signal provided by the input control terminal CSTV, that is, at A pulse with a width of 2H is formed at the third node N3, and H refers to the unit of the pulse width.
  • the first output sub-circuit 031 may write a pulse signal with a width of 1H to the fourth node N4 based on the pulse signal with a width of 2H.
  • the first output sub-circuit 031 can shift a pulse signal with a width of 2H to a pulse signal with a width of 1H.
  • a pulse signal with a width of 1H can be formed at the output terminal OUT, and the potential of the pulse signal formed at the output terminal OUT is exactly opposite to that at the fourth node N4.
  • the shift register unit described in the embodiment of the present disclosure only includes a plurality of CMOS transistors, P-type transistors and N-type transistors, but does not include any capacitors.
  • a logic circuit eg, the clock latch described above
  • the control manner of the shift register unit described in the embodiment of the present disclosure is relatively simple.
  • the embodiments of the present disclosure provide a shift register unit, in which the first input circuit can be controlled by the first clock signal provided by the first clock terminal and the potential of the second node , respectively control the potential of the first node and the potential of the third node.
  • the second input circuit can control the potential of the second node under the control of the first clock signal, the input control signal provided by the input control terminal, the potential of the third node and the potential of the first node.
  • the output circuit can transmit a high-level pull-up power signal or a low-level pull-down power signal to the output end under the control of the third node.
  • FIG. 6 is a flowchart of a method for driving a shift register unit provided by an embodiment of the present disclosure, which can be used to drive the shift register unit shown in any of FIGS. 1 to 5 . As shown in Figure 6, the method may include:
  • Step 601 in the input stage, in response to the first clock signal provided by the first clock terminal, the first input circuit controls the pull-down power terminal to conduct with the first node.
  • the second input circuit controls the pull-down power terminal to conduct with the second node in response to the input control signal and the first clock signal provided by the input control terminal.
  • the first input circuit also controls the pull-up power supply terminal to conduct with the third node in response to the potential of the second node.
  • Step 602 In the output stage, the first input circuit controls the pull-up power supply terminal to conduct with the first node in response to the first clock signal, and the second input circuit controls the pull-down power supply in response to the potential of the first node and the potential of the third node The first input circuit also controls the pull-up power terminal to conduct with the third node in response to the potential of the second node.
  • the output circuit controls the pull-up power supply terminal to conduct with the output terminal in response to the potential of the third node and the second clock signal provided by the second clock terminal.
  • Step 603 In the pull-down stage, the first input circuit controls the pull-down power terminal to conduct with the first node in response to the first clock signal, and the second input circuit controls the pull-up power terminal to connect with the first node in response to the potential of the first node and the input control signal.
  • the second node is turned on, the first input circuit also controls the pull-down power supply terminal to conduct with the third node in response to the potential of the second node, and the output circuit controls the pull-down power supply terminal and the third node in response to the potential of the third node and the second clock signal. The output is turned on.
  • FIG. 7 is a timing diagram of each signal terminal and each node in a shift register unit provided by an embodiment of the present disclosure.
  • the potential of the first clock signal provided by the first clock terminal CKV1 is the first potential.
  • the N-type transistor in the eighth input transistor M8, the N-type transistor in the ninth input transistor M9 and the second input transistor M2 are all turned on, and the fifth input transistor M5 is turned off.
  • the pull-down power terminal VGL is connected to the first node N1, and the pull-down power signal of the second potential is transmitted to the first node N1 through the N-type transistor in the eighth input transistor M8 and the N-type transistor in the ninth input transistor M9.
  • the fourth input transistor M4 and the P-type transistors in the first input transistor M1 are both turned on, and the seventh input transistor M7 is turned off.
  • the pull-up power supply signal of the first potential is transmitted to the gate of the second input transistor M2 through the first input transistor M1.
  • the second input transistor M2 remains on.
  • the potential of the input control signal provided by the input control terminal CSTV is the first potential, and the N-type transistor in the third input transistor M3 is turned on.
  • the pull-down power terminal VGL is turned on with the second node N2, and the pull-down power signal of the second potential can be transmitted to the second node N2 through the N-type transistors of the second input transistor M2 and the third input transistor M3 which are turned on.
  • the P-type transistor in the tenth input transistor M10 is turned on, the pull-up power supply terminal VGH and the third node N3 are turned on, and the pull-up power supply signal of the first potential can be transmitted to the third node through the P-type transistor in the tenth input transistor M10 N3.
  • Both the N-type transistor and the third output transistor T3 in the sixth input transistor M6 are turned on, and the second output transistor T2 is turned off.
  • the potential of the second clock signal provided by the second clock terminal CKV2 is the second potential, and the P-type transistor in the first output transistor T1 is turned on.
  • the pull-up power terminal VGH is turned on with the fourth node N4, and the pull-up power signal of the first potential is transmitted to the fourth node N4 through the P-type transistor in the first output transistor T1.
  • the N-type transistor in the first fourth output transistor T4 is turned on, and the pull-down power supply signal of the second potential is transmitted to the gate of the second fourth output transistor T4 through the turned-on N-type transistor.
  • the P-type transistor in the second fourth output transistor T4 is turned on, and the pull-up power supply signal of the first potential is transmitted to the gate of the third fourth output transistor T4 through the turned-on P-type transistor.
  • the N-type transistor in the third and fourth output transistor T4 is turned on, and the pull-down power supply signal of the second potential is transmitted to the output terminal OUT through the turned-on N-type transistor.
  • the potential of the first clock signal jumps to the second potential
  • the P-type transistor in the eighth input transistor M8, the P-type transistor in the ninth input transistor M9 and the fifth input transistor M5 are all turned on, the second The input transistor M2 is turned off.
  • the pull-up power terminal VGH is connected to the first node N1, and the pull-up power signal of the first potential is transmitted to the first node N1 through the P-type transistor in the eighth input transistor M8 and the P-type transistor in the ninth input transistor M9.
  • the N-type transistor and the seventh input transistor M7 in the first input transistor M1 are both turned on, and the fourth input transistor M4 is turned off.
  • the pull-down power supply signal of the second potential is transmitted to the gate of the second input transistor M2 through the N-type transistor in the first input transistor M1.
  • the second input transistor M2 remains on.
  • the potential of the input control signal jumps to the second potential.
  • the P-type transistor in the third input transistor M3 is turned on. Since the potential of the third node N3 is the first potential, the N-type transistor, the third output transistor T3 and the second output transistor T2 in the sixth input transistor M6 are all kept on. And because the seventh input transistor M7 is turned on, the pull-down power supply terminal VGH and the second node N2 remain conductive.
  • the pull-down power supply signal of the second potential may be transmitted to the second node N2 through the N-type transistor of the seventh input transistor M7 and the sixth input transistor M6, which are turned on.
  • the P-type transistor in the tenth input transistor M10 is kept on, the pull-up power supply terminal VGH and the third node N3 are kept on, and the pull-up power supply signal of the first potential continues to be transmitted to the third node through the P-type transistor in the tenth input transistor M10.
  • the N-type transistor and the third output transistor T3 in the sixth input transistor M6 are kept on, and the second output transistor T2 is turned off.
  • the potential of the second clock signal jumps to the first potential, and the N-type transistor in the first output transistor T1 is turned on.
  • the pull-down power terminal VGL is connected to the fourth node N4, and the pull-down power signal of the second potential is transmitted to the fourth node N4 through the turned-on third output transistor T3 and the N-type transistor in the first output transistor T1.
  • the P-type transistor in the first fourth output transistor T4 is turned on, and the pull-up power supply signal of the first potential is transmitted to the gate of the second fourth output transistor T4 through the turned-on P-type transistor.
  • the N-type transistor in the second fourth output transistor T4 is turned on, and the pull-down power signal of the second potential is transmitted to the gate of the third fourth output transistor T4 through the turned-on N-type transistor.
  • the P-type transistor in the third and fourth output transistor T4 is turned on, and the pull-up power supply signal of the first potential is transmitted to the output terminal OUT through the turned-on P-type transistor.
  • the potential of the first clock signal jumps to the first potential.
  • the N-type transistor in the eighth input transistor M8, the N-type transistor in the ninth input transistor M9 and the second input transistor M2 are all turned on, and the fifth input transistor M5 is turned off.
  • the pull-down power terminal VGL is connected to the first node N1, and the pull-down power signal of the second potential is transmitted to the first node N1 through the N-type transistor in the eighth input transistor M8 and the N-type transistor in the ninth input transistor M9.
  • the fourth input transistor M4 and the P-type transistors in the first input transistor M1 are both turned on, and the seventh input transistor M7 is turned off.
  • the pull-up power supply signal of the first potential is transmitted to the gate of the second input transistor M2 through the first input transistor M1.
  • the second input transistor M2 remains on.
  • the potential of the input control signal is maintained at the second potential, and the P-type transistor in the third input transistor M3 is turned on.
  • the pull-up power terminal VGH is turned on with the second node N2, and the pull-up power signal of the first potential can be transmitted to the second node N2 through the P-type transistors in the fourth input transistor M4 and the third input transistor M3 that are turned on.
  • the N-type transistor in the tenth input transistor M10 is turned on, the pull-down power terminal VGL is connected to the third node N3, and the pull-down power signal of the second potential can be transmitted to the third node N3 through the N-type transistor in the tenth input transistor M10.
  • the P-type transistor and the second output transistor T2 in the sixth input transistor M6 are both turned on, and the third output transistor T3 is turned off.
  • the potential of the second clock signal jumps to the second potential, and the P-type transistor in the first output transistor T1 is turned on.
  • the pull-up power terminal VGH is turned on with the fourth node N4, and the pull-up power signal of the first potential is transmitted to the fourth node N4 through the P-type transistor in the first output transistor T1 and the second output transistor T2.
  • the N-type transistor in the first fourth output transistor T4 is turned on, and the pull-down power supply signal of the second potential is transmitted to the gate of the second fourth output transistor T4 through the turned-on N-type transistor.
  • the P-type transistor in the second fourth output transistor T4 is turned on, and the pull-up power supply signal of the first potential is transmitted to the gate of the third fourth output transistor T4 through the turned-on P-type transistor.
  • the N-type transistor in the third and fourth output transistor T4 is turned on, and the pull-down power supply signal of the second potential is transmitted to the output terminal OUT through the turned-on N-type transistor.
  • FIG. 8 also shows a timing diagram of signal terminals of three cascaded shift register units. Referring to FIG. 8 , it can be seen that the potentials at the output terminals OUT1 , OUT2 and OUT3 of the three shift register units may be the first potential in sequence.
  • the embodiments of the present disclosure provide a method for driving a shift register unit, in which the first input circuit can be controlled by the first clock signal provided by the first clock terminal and the potential of the second node , respectively control the potential of the first node and the potential of the third node.
  • the second input circuit can control the potential of the second node under the control of the first clock signal, the input control signal provided by the input control terminal, the potential of the third node and the potential of the first node.
  • the output circuit can transmit a high-level pull-up power signal or a low-level pull-down power signal to the output end under the control of the third node.
  • FIG. 9 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present disclosure.
  • the gate driving circuit may include: at least two cascaded shift register units 00 as shown in any one of FIGS. 1 to 5 .
  • the gate driving circuit can be connected to two clock signal lines: a first clock signal line ckv1 and a second clock signal line ckv2.
  • the first clock terminal CKV1 of the odd-numbered stage shift register unit 00 can be coupled to the first clock signal line ckv1, and the second clock terminal CKV2 of the odd-numbered stage shift register unit 00 can be connected to the second clock terminal CKV2.
  • the clock signal line ckv2 is coupled.
  • the first clock terminal CKV1 of the even-numbered stage shift register unit 00 may be coupled to the second clock signal line ckv2, and the second clock terminal CKV2 of the even-numbered stage shift register unit 00 may be coupled to the first clock signal line ckv1.
  • the two first clock terminals CKV1 included in every two adjacent shift register units 00 may be alternately coupled to the first clock signal line ckv1 and the second clock signal line ckv2, and every two adjacent shift register units 00 are shifted
  • the two second clock terminals CKV2 included in the register unit 00 may be alternately coupled to the first clock signal line ckv1 and the second clock signal line ckv2.
  • the input control terminal CSTV of each stage shift register unit 00 may be connected with the output terminal OUT of the cascaded previous stage shift register unit 00 coupled (not shown in Figure 9). In this way, the purpose of cascading is achieved.
  • FIG. 10 is a display device provided by an embodiment of the present disclosure. As shown in FIG. 10 , the display device may include: a display panel 100 , and a gate driving circuit 000 as shown in FIG. 9 .
  • the display panel 100 may include a plurality of pixel circuits.
  • the gate driving circuit 000 can be coupled to the gate signal terminals in each pixel circuit, and the gate driving circuit 000 can be used to provide gate driving signals for the gate signal terminals.
  • a plurality of pixel circuits in the display panel 100 may be arranged in an array.
  • the output terminal of each shift register unit can be coupled to the gate signal terminal coupled to each pixel circuit located in the same row, and the gate signal terminal coupled to each shift register unit on different lines.
  • the gate signal terminals coupled to the pixel circuits in the same row can be coupled to a gate line, and the gate line can be further coupled to the output terminal of a shift register unit.
  • the gate driving circuit 000 may be disposed on the display panel 100, that is, integrated with the display panel, so that the design of the narrow frame of the display device can be facilitated.
  • the transistor coupled to the gate signal terminal may be an N-type indium gallium zinc oxide (IGZO) transistor.
  • IGZO indium gallium zinc oxide
  • FIG. 11 shows a schematic structural diagram of a pixel circuit.
  • the pixel circuit shown includes a first switch transistor K1, a second switch transistor K2, a third switch transistor K3, a fourth switch transistor K4, a fifth switch transistor K5, a sixth switch transistor K6, The seventh switch transistor K7 and the storage capacitor C1.
  • the gate of the first switch transistor K1 is coupled to the reset control terminal RST(n-1), the first pole of the first switch transistor K1 is coupled to the reset signal terminal Vinit, and the second pole of the first switch transistor K1 is connected to the reset signal terminal Vinit.
  • the anode of the light emitting element L1 is coupled.
  • the cathode of the light-emitting element L1 may also be coupled to the power supply terminal VSS.
  • the first switching transistor K1 can be used to transmit the reset signal provided by the reset signal terminal Vinit to the anode of the light-emitting element L1 in response to the reset control signal provided by the reset control terminal RST(n-1).
  • the gate of the second switch transistor K2 is coupled to the switch control terminal GATE(n-1), the first pole of the second switch transistor K2 is coupled to the second pole of the first switch transistor K1, and the second pole of the second switch transistor K2
  • the diode is coupled to the gate of the third switching transistor K3.
  • the second switch transistor K2 may be used to control the gate of the third switch transistor K3 to conduct with the second pole of the first switch transistor K1 in response to a signal provided by the switch control terminal GATE(n-1).
  • the gate of the fourth switch transistor K4 and the gate of the seventh switch transistor K7 may both be coupled to the gate signal terminal GATE(n), the first pole of the fourth switch transistor K4 is coupled to the data signal terminal DATA, the fourth The second pole of the switch transistor K4 is coupled to the second pole of the third switch transistor K3.
  • the first pole of the seventh switch transistor K7 may be coupled with the first pole of the third switch transistor K3, and the second pole of the seventh switch transistor K7 may be coupled with the gate of the third switch transistor K3.
  • the fourth switching transistor K4 may be used to transmit the data signal provided by the data signal terminal DATA to the second pole of the third switching transistor K3 in response to the gate driving signal provided by the gate signal terminal GATE(n).
  • the seventh switch transistor K7 may be used to control the on-off of the first pole of the third switch transistor K3 and the gate of the third switch transistor K3 in response to the gate driving signal.
  • the gate of the fifth switching transistor K5 and the gate of the sixth switching transistor K6 can both be coupled to the light-emitting control terminal EM, the first pole of the fifth switching transistor K5 can be coupled to the driving power terminal VDD, and the fifth switching transistor K5
  • the second pole of the can be coupled to the first pole of the third switching transistor K3.
  • the first pole of the sixth switching transistor K6 may be coupled with the second pole of the third switching transistor K3, and the second pole of the sixth switching transistor K6 may be coupled with the anode of the light emitting element L1.
  • the fifth switch transistor K5 can be used to transmit the driving power signal provided by the driving power terminal VDD to the first electrode of the third switching transistor K3 in response to the lighting control signal provided by the lighting control terminal EM.
  • the sixth switch transistor K6 may be used to control the connection between the second pole of the third switch transistor K3 and the anode of the light-emitting element L1 in response to the light-emitting control signal.
  • One end of the storage capacitor C1 may be coupled to the gate of the third switching transistor K3, and the other end of the storage capacitor C1 may be coupled to the driving power terminal VDD.
  • the fourth switching transistor K4 and the seventh switching transistor K7 coupled to the gate signal terminal GATE(n) may both be N-type transistors, and may both be transistors made of IGZO material.
  • the fifth switch transistor K5 and the sixth switch transistor K6 coupled to the light-emitting control terminal EM may both be N-type transistors.
  • the remaining transistors including the first switching transistor K1 , the second switching transistor K2 and the third switching transistor K3 ) may all be P-type transistors.
  • FIG. 12 also shows a timing diagram of each signal terminal in the pixel circuit.
  • the process of driving the light-emitting element L1 to emit light may include: a reset stage t01, a writing stage t02 and a light-emitting stage t03.
  • the high potential represents the effective potential.
  • the potential of the signal provided by GATE(n-1) and the potential of the signal provided by RST(n-1) may be effective potentials.
  • the first switching transistor K1 and the second switching transistor K2 are turned on, and the reset signal terminal Vinit can transmit a reset signal to the gate of the third switching transistor K3 and the anode of the light-emitting element L1.
  • the potential of the gate driving signal provided by the gate signal terminal GATE(n) may be an effective potential.
  • the fourth switch transistor K4 and the seventh switch transistor K7 are turned on, and the data signal terminal DATA can transmit a data signal to the gate of the third switch transistor K3.
  • the potential of the light-emitting control signal provided by the light-emitting control terminal EM is an effective potential.
  • the fifth switching transistor K5 and the sixth switching transistor K6 are turned on, and the third switching transistor K3 is also kept turned on at this stage.
  • the driving power terminal VDD can transmit the driving power signal to the first pole of the third switching transistor K3, and the third switching transistor K3 can transmit the driving power signal to the first pole of the sixth switching transistor K6 based on the potential of its gate and the potential of the first pole drive current.
  • the sixth switching transistor K6 then transmits the driving current to the light-emitting element L1, and the light-emitting element L1 emits light.
  • the timing at the output terminal OUT of the shift register unit may be consistent with the timing at the gate signal terminal GATE(n) shown in FIG. 12 .
  • the gate of the N-type IGZO transistor needs to respond to a strong driving signal to work reliably.
  • the drive capability of the signal output from the shift register unit of the related art to the gate signal terminal is weak, resulting in the structure shown in FIG. 11 , the drive capability of the fourth switch transistor K4 is weak, and the data signal cannot be reliably transmitted to the third switch.
  • the second pole of the transistor K3 which in turn makes it impossible to reliably drive the light-emitting element L1 to emit light.
  • the shift register unit due to its strong output capability, it can ensure that the fourth switch transistor K4 reliably transmits the data signal to the second pole of the third switch transistor K3, thereby ensuring that the light-emitting element L1 is The luminous effect is better.
  • FIG. 11 only schematically shows an optional 7T1C (ie, 7 transistors and 1 capacitor) pixel circuit.
  • the embodiments of the present disclosure do not limit the structure of the pixel circuit driven by the shift register unit, for example, it can also be used to drive the pixel circuit of the 6T1C structure.
  • the transistors in the pixel circuits described in the embodiments of the present disclosure may also be low temperature polycrystalline silicon oxide (low temperature polycrystalline oxide, LTPO) transistors.
  • low temperature polycrystalline silicon oxide low temperature polycrystalline oxide, LTPO
  • the display devices provided by the embodiments of the present disclosure may be: an active-matrix organic light-emitting diode (AMOLED) display device, an organic light-emitting diode (OLED) display device, and a liquid crystal display device Any product or component with display function.
  • AMOLED active-matrix organic light-emitting diode
  • OLED organic light-emitting diode
  • liquid crystal display device Any product or component with display function.

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Abstract

本公开提供了一种移位寄存器单元及其驱动方法、栅极驱动电路、显示装置，属于显示技术领域。该移位寄存器单元中，第一输入电路可以在第一时钟端提供的第一时钟信号和第二节点的电位的控制下，分别控制第一节点的电位和第三节点的电位。第二输入电路可以在第一时钟信号，输入控制端提供的输入控制信号，第三节点的电位以及第一节点的电位的控制下，控制第二节点的电位。输出电路可以在第三节点的控制下，向输出端传输高电位的上拉电源信号或低电位的下拉电源信号。如此，仅通过灵活设置两个时钟端提供的时钟信号和一个输入控制端提供的输入控制信号，即可以实现对输出端的电位的可靠控制，该控制过程较为简单，控制灵活性较高。

Description

移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
本公开要求于2021年4月8日提交的申请号为202110378872.1、发明名称为“移位寄存器单元及其驱动方法、栅极驱动电路、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，特别涉及一种移位寄存器单元及其驱动方法、栅极驱动电路、显示装置。
背景技术
移位寄存器通常包括多个级联的移位寄存器单元，每个移位寄存器单元用于驱动一行像素单元，由该多个级联的移位寄存器单元可以实现对显示装置中各行像素单元的逐行扫描驱动，以显示图像。
发明内容
本公开实施例提供了一种移位寄存器单元及其驱动方法、栅极驱动电路、显示装置，所述技术方案如下：
一方面，提供了一种移位寄存器单元，所述移位寄存器单元包括：
第一输入电路，分别与第一时钟端、第一节点、第二节点、第三节点、上拉电源端和下拉电源端耦接，所述第一输入电路用于响应于所述第一时钟端提供的第一时钟信号，控制所述上拉电源端与所述第一节点的通断，并控制所述下拉电源端与所述第一节点的通断；以及用于响应于所述第二节点的电位，控制所述上拉电源端与所述第三节点的通断，并控制所述下拉电源端与所述第三节点的通断；
第二输入电路，分别与所述第一节点、所述第二节点、所述第三节点、所述上拉电源端、所述下拉电源端、输入控制端和所述第一时钟端耦接，所述第二输入电路用于响应于所述第一节点的电位、所述第三节点的电位、所述第一时钟信号和所述输入控制端提供的输入控制信号，控制所述上拉电源端与所述 第二节点的通断，并控制所述下拉电源端与所述第二节点的通断；
以及输出电路，分别与所述上拉电源端、所述下拉电源端、所述第三节点、第二时钟端和输出端耦接，所述输出电路用于响应于所述第三节点的电位和所述第二时钟端提供的第二时钟信号，控制所述上拉电源端与所述输出端的通断，并控制所述下拉电源端与所述输出端的通断。
可选的，所述输出电路包括：第一输出子电路和第二输出子电路；
所述第一输出子电路分别与所述第二时钟端、所述第三节点、所述上拉电源端、所述下拉电源端和第四节点耦接，所述第一输出子电路用于响应于所述第二时钟信号和所述第三节点的电位，控制所述上拉电源端与所述第四节点的通断，并控制所述下拉电源端与所述第四节点的通断；
所述第二输出子电路分别与所述第四节点、所述上拉电源端、所述下拉电源端和所述输出端耦接，所述第二输出子电路用于响应于所述第四节点的电位，控制所述上拉电源端与所述输出端的通断，并控制所述下拉电源端与所述输出端的通断。
可选的，所述第一输出子电路包括：第一输出晶体管、第二输出晶体管和第三输出晶体管，所述第一输出极晶体管为互补型金属氧化物半导体CMOS晶体管；
所述第一输出晶体管的栅极与所述第二时钟端耦接，所述第一输出晶体管的一个第一极和所述第二输出晶体管的第一极均与所述上拉电源端耦接，所述第一输出晶体管的另一个第一极与所述第三输出晶体管的第二极耦接，所述第一输出晶体管的第二极和所述第二输出晶体管的第二极均与所述第四节点耦接，所述第二输出晶体管的栅极和所述第三输出晶体管的栅极均与所述第三节点耦接，所述第三输出晶体管的第一极与所述下拉电源端耦接。
可选的，所述第二输出子电路包括：串联在所述第四节点和所述输出端之间的奇数个第四输出晶体管；
每个所述第四输出晶体管均为CMOS晶体管，且每个所述第四输出晶体管的两个第一极分别与所述上拉电源端和所述下拉电源端耦接。
可选的，所述第二输出子电路包括：三个所述第四输出晶体管；
其中，第一个所述第四输出晶体管的栅极与所述第四节点耦接，第一个所述第四输出晶体管的第二极与第二个所述第四输出晶体管的栅极耦接，第二个 所述第四输出晶体管的第二极与第三个所述第四输出晶体管的栅极耦接，第三个所述第四输出晶体管的第二极与所述输出端耦接。
可选的，至少一个第四输出晶体管的宽长比，大于所述移位寄存器单元中除所述至少一个第四输出晶体管之外的其他晶体管的宽长比。
可选的，所述第二输入电路包括：第一输入子电路和第二输入子电路；
所述第一输入子电路分别与所述第一节点、所述第一时钟端、所述输入控制端、所述上拉电源端、所述下拉电源端和所述第二节点耦接，所述第一输入子电路用于响应于所述第一节点的电位、所述输入控制信号和所述第一时钟信号，控制所述上拉电源端与所述第二节点的通断，并控制所述下拉电源端与所述第二节点的通断；
所述第二输入子电路分别与所述第一时钟端、所述第一节点、所述第二节点、所述第三节点、所述上拉电源端和所述下拉电源端耦接，所述第二输入子电路用于响应于所述第一节点的电位、所述第三节点的电位和所述第一时钟信号，控制所述上拉电源端与所述第二节点的通断，并控制所述下拉电源端与所述第二节点的通断。
可选的，所述第一输入子电路包括：第一输入晶体管、第二输入晶体管、第三输入晶体管和第四输入晶体管；所述第一输入晶体管和所述第三输入晶体管均为CMOS晶体管；
所述第一输入晶体管的栅极与所述第一节点耦接，所述第一输入晶体管的两个第一极分别与所述上拉电源端和所述下拉电源端耦接，所述第一输入晶体管的第二极与所述第二输入晶体管的栅极耦接，且所述第二输入晶体管的栅极还与所述第一时钟端耦接；
所述第二输入晶体管的第一极与所述下拉电源端耦接，所述第二输入晶体管的第二极与所述第三输入晶体管的一个第一极耦接；
所述第三输入晶体管的另一个第一极与所述第四输入晶体管的第二极耦接，所述第三输入晶体管的栅极与所述输入控制端耦接，所述第三输入晶体管的第二极与所述第二节点耦接；
所述第四输入晶体管的栅极与所述第一节点耦接，所述第四输入晶体管的第一极与所述上拉电源端耦接。
可选的，所述第二输入子电路包括：第五输入晶体管、第六输入晶体管和 第七输入晶体管；所述第六输入晶体管为CMOS晶体管；
所述第五输入晶体管的栅极与所述第一时钟端耦接，所述第五输入晶体管第一极与所述上拉电源端耦接，所述第五输入晶体管第二极与所述第六输入晶体管的一个第一极耦接；
所述第六输入晶体管的另一个第一极与所述第七输入晶体管的第二极耦接，所述第六输入晶体管的栅极与所述第三节点耦接；
所述第七输入晶体管的第一极与所述下拉电源端耦接，所述第七输入晶体管的栅极与所述第一节点耦接。
可选的，所述第一输入电路包括：第三输入子电路和第四输入子电路；
所述第三输入子电路分别与所述第一时钟端、所述上拉电源端、所述下拉电源端和所述第一节点耦接，所述第三输入子电路用于响应于所述第一时钟信号，控制所述上拉电源端与所述第一节点的通断，并控制所述下拉电源端与所述第一节点的通断；
所述第四输入子电路分别与所述第二节点、所述上拉电源端、所述下拉电源端和所述第三节点耦接，所述第四输入子电路用于响应于所述第二节点的电位，控制所述上拉电源端与所述第三节点的通断，并控制所述下拉电源端与所述第三节点的通断。
可选的，所述第三输入子电路包括：第八输入晶体管和第九输入晶体管；所述第四输入子电路包括：第十输入晶体管；所述第八输入晶体管、所述第九输入晶体管和所述第十输入晶体管均为CMOS晶体管；
所述第八输入晶体管的栅极和所述第九输入晶体管的栅极均与所述第一时钟端耦接，所述第八输入晶体管的两个第一极和所述第九输入晶体管的两个第一极均分别与所述上拉电源端和所述下拉电源端耦接，所述第八输入晶体管的第二极和所述第九输入晶体管的第二极均与所述第一节点耦接；
所述第十输入晶体管的栅极与所述第二节点耦接，所述第十输入晶体管的两个第一极分别与所述上拉电源端和所述下拉电源端耦接，所述第十输入晶体管的第二极与所述第三节点耦接。
另一方面，提供了一种移位寄存器单元的驱动方法，用于驱动如上述方面所述的移位寄存器单元；所述方法包括：
输入阶段，第一输入电路响应于第一时钟端提供的第一时钟信号，控制下 拉电源端与第一节点导通；第二输入电路响应于输入控制端提供的输入控制信号和所述第一时钟信号，控制所述下拉电源端与第二节点导通；所述第一输入电路还响应于所述第二节点的电位，控制上拉电源端与第三节点导通；
输出阶段，所述第一输入电路响应于所述第一时钟信号，控制所述上拉电源端与所述第一节点导通，所述第二输入电路响应于所述第一节点的电位和所述第三节点的电位，控制所述下拉电源端与所述第二节点导通，所述第一输入电路还响应于所述第二节点的电位，控制所述上拉电源端与所述第三节点导通；输出电路响应于所述第三节点的电位和第二时钟端提供的第二时钟信号，控制所述上拉电源端与所述输出端导通；
下拉阶段，所述第一输入电路响应于所述第一时钟信号，控制所述下拉电源端与所述第一节点导通，所述第二输入电路响应于所述第一节点的电位和所述输入控制信号，控制所述上拉电源端与所述第二节点导通，所述第一输入电路还响应于所述第二节点的电位，控制所述下拉电源端与所述第三节点导通，所述输出电路响应于所述第三节点的电位和所述第二时钟信号，控制所述下拉电源端与所述输出端导通。
又一方面，提供了一种栅极驱动电路，所述栅极驱动电路包括：至少两个级联的如上述方面所述的移位寄存器单元；
奇数级移位寄存器单元的第一时钟端与第一时钟信号线耦接，奇数级移位寄存器单元的第二时钟端与第二时钟信号线耦接；
偶数级移位寄存器单元的第一时钟端与第二时钟信号线耦接，偶数级移位寄存器单元的第二时钟端与第一时钟信号线耦接。
再一方面，提供了一种显示装置，所述显示装置包括：显示面板，以及如上述方面所述的栅极驱动电路，所述显示面板包括多个像素电路；
所述栅极驱动电路与所述像素电路中的栅极信号端耦接，所述栅极驱动电路用于为所述栅极信号端提供栅极驱动信号。
可选的，所述像素电路包括：第一开关晶体管、第二开关晶体管、第三开关晶体管、第四开关晶体管、第五开关晶体管、第六开关晶体管、第七开关晶体管和存储电容；
所述第一开关晶体管的栅极与复位控制端耦接，所述第一开关晶体管的第一极与复位信号端耦接，所述第一开关晶体管的第二极与所述第二开关晶体管 的第一极、所述第六开关晶体管的第二极以及发光元件的阳极耦接；
所述第二开关晶体管的栅极与开关控制端耦接，所述第二开关晶体管的第二极与所述第三开关晶体管的栅极耦接；
所述第五开关晶体管的栅极和所述第六开关晶体管的栅极均与发光控制端耦接，所述第五开关晶体管的第一极与驱动电源端耦接，所述第五开关晶体管的第二极与所述第三开关晶体管的第一极耦接；所述第六开关晶体管的第一极与所述第三开关晶体管的第二极耦接；
所述第四开关晶体管的栅极和所述第七开关晶体管的栅极均与所述栅极信号端耦接；所述第四开关晶体管的第一极与数据信号端耦接，所述第四开关晶体管的第二极与所述第三开关晶体管的第二极耦接；所述第七开关晶体管的第一极与所述第三开关晶体管的第一极耦接，所述第七开关晶体管的第二极与所述第三开关晶体管的栅极耦接；
所述存储电容的一端与所述第三开关晶体管的栅极耦接，所述存储电容的另一端与所述驱动电源端耦接；
其中，所述第四开关晶体管和所述第七开关晶体管均为N型铟镓锌氧化物IGZO晶体管，且所述栅极驱动电路中移位寄存器单元的输出端与所述第四开关晶体管的栅极和所述第七开关晶体管的栅极耦接。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种移位寄存器单元的结构示意图；
图2是本公开实施例提供的另一种移位寄存器单元的结构示意图；
图3是本公开实施例提供的又一种移位寄存器单元的结构示意图；
图4是本公开实施例提供的再一种移位寄存器单元的结构示意图；
图5是本公开实施例提供的再一种移位寄存器单元的结构示意图；
图6是本公开实施例提供的一种移位寄存器单元的驱动方法流程图；
图7是本公开实施例提供的一种移位寄存器单元中各信号端的时序图；
图8是本公开实施例提供的另一种移位寄存器单元中各信号端的时序图；
图9是本公开实施例提供的一种栅极驱动电路的结构示意图；
图10是本公开实施例提供的一种显示装置的结构示意图；
图11是本公开实施例提供的一种像素电路的结构示意图；
图12是本公开实施例提供的一种像素电路中各信号端的时序图。
具体实施方式
为了使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开作进一步地详细描述。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件，根据在电路中的作用本公开的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，将其中源极称为第一极，漏极称为第二极，或者将其中漏极称为第一极，源极称为第二极。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外，本公开实施例所采用的开关晶体管可以包括P型开关晶体管和N型开关晶体管中的任一种，其中，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型开关晶体管在栅极为高电平时导通，在栅极为低电平时截止。此外，本公开各个实施例中的多个信号都对应有第一电位和第二电位，第一电位和第二电位仅代表该信号的电位有2个不同的状态量，不代表全文中第一电位或第二电位具有特定的数值。
相关技术中，移位寄存器单元一般包括：输入电路、输出电路和下拉电路。输入电路与上拉节点耦接，输入电路用于根据级联的上一级移位寄存器单元输出的驱动信号，对上拉节点充电。输出电路与输出端耦接，输出电路用于在该上拉节点的控制下向输出端输出栅极驱动信号。下拉电路分别与上拉节点和输出端耦接，下拉电路用于对上拉节点和输出端进行降噪。但是，相关技术中移位寄存器单元控制输出端的电位的过程较为复杂，控制灵活性较差。
本公开实施例提供了一种移位寄存器单元，该移位寄存器单元控制输出端的电位的过程较为简单，控制灵活性较好。图1是本公开实施例提供的一种移位寄存器单元的结构示意图。如图1所示，该移位寄存器单元可以包括：第一 输入电路01、第二输入电路02以及输出电路03。
参考图1，该第一输入电路01可以分别与第一时钟端CKV1、第一节点N1、第二节点N2、第三节点N3、上拉电源端VGH和下拉电源端VGL耦接。该第一输入电路01可以用于响应于第一时钟端CKV1提供的第一时钟信号，控制上拉电源端VGH与第一节点N1的通断，并控制下拉电源端VGL与第一节点N1的通断。以及可以用于响应于第二节点N2的电位，控制上拉电源端VGH与第三节点N3的通断，并控制下拉电源端VGL与第三节点N3的通断。其中，耦接可以是指电连接。
例如，该第一输入子电路01可以在第一时钟信号的电位为第一电位时，控制下拉电源端VGL与第一节点N1导通，并在第一时钟信号的电位为第二电位时，控制上拉电源端VGH与第一节点N1导通。在上拉电源端VGH与第一节点N1导通时，上拉电源端VGH提供的上拉电源信号可以经第一输入子电路01传输至第一节点N1。在下拉电源端VGL与第一节点N1导通时，下拉电源端VGL提供的下拉电源信号可以经第一输入子电路01传输至第一节点N1。从而实现对第一节点N1的电位的控制。
例如，该第一输入子电路01还可以在第二节点N2的电位为第一电位时，控制下拉电源端VGL与第三节点N3的通断，并在第二节点N2的电位为第二电位时，控制上拉电源端VGH与第三节点N3的通断。同理，在上拉电源端VGH与第三节点N3导通时，上拉电源信号可以经第一输入子电路01传输至第三节点N3。在下拉电源端VGL与第三节点N3导通时，下拉电源信号可以经第一输入子电路01传输至第三节点N3。从而实现对第三节点N3的电位的控制。
可选的，上拉电源信号的电位可以为第一电位，下拉电源信号的电位可以为第二电位。本公开实施例记载的第一电位相对于第二电位可以为高电位，即第一电位的相对于第二电位较大。并且，对于N型晶体管而言，第一电位(即，高电位)可以为有效电位，第二电位(即，低电位)可以为无效电位。对于P型晶体管而言，第一电位可以为无效电位，第二电位可以为有效电位。
继续参考图1，第二输入电路02可以分别与第一节点N1、第二节点N2、第三节点N3、上拉电源端VGH、下拉电源端VGL、输入控制端CSTV和第一时钟端CKV1耦接。该第二输入电路02可以用于响应于第一节点N1的电位、第三节点N3的电位、第一时钟信号和输入控制端CSTV提供的输入控制信号， 控制上拉电源端VGH与第二节点N2的通断，并控制下拉电源端VGL与第二节点N2的通断。
例如，该第二输入电路02可以在第一时钟信号的电位和输入控制信号的电位均为第一电位时，控制下拉电源端VGL与第二节点N2导通，和/或，在第一节点N1的电位和第三节点N3的电位均为第一电位时，控制下拉电源端VGL与第二节点N2导通。以及，该第二输入电路02可以在第一节点N1的电位和输入控制信号的电位均为第二电位时，控制上拉电源端VGH与第二节点N2导通，和/或，在第一时钟信号的电位和第三节点N3的电位均为第二电位时，控制上拉电源端VGH与第二节点N2导通。
其中，在上拉电源端VGH与第二节点N2导通时，上拉电源信号可以经第二输入电路02传输至第二节点N2。在下拉电源端VGL与第二节点N2导通时，下拉电源信号可以经第二输入电路02传输至第二节点N2。从而实现对第二节点N2的电位的控制。
继续参考图1，该输出电路03可以分别与上拉电源端VGH、下拉电源端VGL、第三节点N3、第二时钟端CKV2和输出端OUT耦接。该输出电路03可以用于响应于第三节点N3的电位和第二时钟端CKV2提供的第二时钟信号，控制上拉电源端VGH与输出端OUT的通断，并控制下拉电源端VGL与输出端OUT的通断。
例如，该输出电路03可以在第三节点N3的电位和第二时钟信号的电位均为第一电位时，控制上拉电源端VGH与输出端OUT导通。以及，该输出电路03可以在第三节点N3的电位为第二电位，和/或，第二时钟信号的电位为第一电位时，控制下拉电源端VGL与输出端OUT导通。
其中，在上拉电源端VGH与输出端OUT导通时，上拉电源信号可以经输出电路03传输至输出端OUT。在下拉电源端VGL与输出端OUT导通时，下拉电源信号可以经输出电路03传输至输出端OUT。从而实现对输出端OUT的电位的控制。该输出端OUT可以与显示面板中像素电路的栅极信号端耦接，以为该栅极信号端提供栅极驱动信号。像素电路中耦接栅极信号端的晶体管可以响应于输出端OUT传输的上拉电源信号和下拉电源信号，可靠开启或关断。
基于以上实施例可知，本公开实施例记载的移位寄存器单元仅包括输入电路和输出电路。通过灵活设置第一时钟端CKV1提供的第一时钟信号、第二时 钟端CKV2提供的第二时钟信号和输入控制端CSTV提供的输入控制信号，即可以达到向输出端OUT可靠传输高电位的上拉电源信号和低电位的下拉电源信号的目的。移位寄存器单元所需设置的信号端较少，控制过程较为简单。
综上所述，本公开实施例提供了一种移位寄存器单元，该移位寄存器单元中，第一输入电路可以在第一时钟端提供的第一时钟信号和第二节点的电位的控制下，分别控制第一节点的电位和第三节点的电位。第二输入电路可以在第一时钟信号，输入控制端提供的输入控制信号，第三节点的电位和第一节点的电位的控制下，控制第二节点的电位。输出电路可以在第三节点的控制下，向输出端传输高电位的上拉电源信号或低电位的下拉电源信号。如此，仅通过灵活设置两个时钟端提供的时钟信号和一个输入控制端提供的输入控制信号，即可以实现对输出端的电位的可靠控制，该控制过程较为简单，控制灵活性较高。
图2是本公开实施例提供的另一种移位寄存器单元的结构示意图。如图2所示，该输出电路03可以包括：第一输出子电路031和第二输出子电路032。
其中，该第一输出子电路031可以分别与第二时钟端CKV2、第三节点N3、上拉电源端VGH、下拉电源端VGL和第四节点N4耦接。该第一输出子电路031可以用于响应于第二时钟信号和第三节点N3的电位，控制上拉电源端VGH与第四节点N4的通断，并控制下拉电源端VGL与第四节点N4的通断。
例如，该第一输出子电路031可以在第三节点N3的电位和第二时钟信号的电位均为第一电位时，控制下拉电源端VGL与第四节点N4导通，并在第三节点N3的电位为第二电位，和/或，第二时钟信号的电位为第二电位时，控制上拉电源端VGH与第四节点N4导通。在下拉电源端VGL与第四节点N4导通时，下拉电源信号可以经第一输出子电路031传输至第四节点N4。在上拉电源端VGH与第四节点N4导通时，上拉电源信号可以经第一输出子电路031传输至第四节点N4。从而实现对第四节点N4的电位的控制。
该第二输出子电路032可以分别与第四节点N4、上拉电源端VGH、下拉电源端VGL和输出端OUT耦接。该第二输出子电路032可以用于响应于第四节点N4的电位，控制上拉电源端VGH与输出端OUT的通断，并控制下拉电源端VGL与输出端OUT的通断。
例如，该第二输出子电路032可以在第四节点N4的电位为第一电位时，控 制下拉电源端VGL与输出端OUT导通，并在第四节点N4的电位为第二电位时，控制上拉电源端VGH与输出端OUT导通。在下拉电源端VGL与输出端OUT导通时，下拉电源信号可以经第二输出子电路032传输至输出端OUT。在上拉电源端VGH与输出端OUT导通时，上拉电源信号可以经第二输出子电路032传输至输出端OUT。从而实现对输出端OUT的电位的控制。
图3是本公开实施例提供的又一种移位寄存器单元的结构示意图。如图3所示，该第二输入电路02可以包括：第一输入子电路021和第二输入子电路022。
其中，该第一输入子电路021可以分别与第一节点N1、第一时钟端CKV1、输入控制端CSTV、上拉电源端VGH、下拉电源端VGL和第二节点N2耦接。该第一输入子电路021可以用于响应于第一节点N1的电位、输入控制信号和第一时钟信号，控制上拉电源端VGH与第二节点N2的通断，并控制下拉电源端VGL与第二节点N2的通断。
例如，该第一输入子电路021可以第一时钟信号的电位和输入控制信号的电位均为第一电位时，控制下拉电源端VGL与第二节点N2导通。以及，该第一输入子电路021可以在第一节点N1的电位和输入控制信号的电位均为第二电位时，控制上拉电源端VGH与第二节点N2导通。在上拉电源端VGH与第二节点N2导通时，上拉电源信号可以经第一输入子电路021传输至第二节点N2。在下拉电源端VGL与第二节点N2导通时，下拉电源信号可以经第一输入子电路021传输至第二节点N2。从而实现对第二节点N2的电位的控制。
该第二输入子电路022可以分别与第一时钟端CKV1、第一节点N1、第二节点N2、第三节点N3、上拉电源端VGH和下拉电源端VGL耦接。该第二输入子电路022可以用于响应于第一节点N1的电位、第三节点N3的电位和第一时钟信号，控制上拉电源端VGH与第二节点N2的通断，并控制下拉电源端VGL与第二节点N2的通断。
例如，该第二输入子电路022可以在第一节点N1的电位和第三节点N3的电位均为第一电位时，控制下拉电源端VGL与第二节点N2导通。以及，该第二输入子电路022可以在第一时钟信号的电位和第三节点N3的电位均为第二电位时，控制上拉电源端VGH与第二节点N2导通。在上拉电源端VGH与第二节点N2导通时，上拉电源信号可以经第二输入子电路022传输至第二节点N2。在下拉电源端VGL与第二节点N2导通时，下拉电源信号可以经第二输入子电 路022传输至第二节点N2。从而实现对第二节点N2的电位的控制。
图4是本公开实施例提供的再一种移位寄存器单元的结构示意图。如图4所示，第一输入电路01包括：第三输入子电路011和第四输入子电路012。
其中，该第三输入子电路011可以分别与第一时钟端CKV1、上拉电源端VGH、下拉电源端VGL和第一节点N1耦接，该第三输入子电路011可以用于响应于第一时钟信号，控制上拉电源端VGH与第一节点N1的通断，并控制下拉电源端VGL与第一节点N1的通断。
例如，该第三输入子电路011可以在第一时钟信号的电位为第一电位时，控制下拉电源端VGL与第一节点N1导通，并在第一时钟信号的电位为第二电位时，控制上拉电源端VGH与第一节点N1导通。其中，在下拉电源端VGL与第一节点N1导通时，下拉电源信号可以经第三输入子电路011传输至第一节点N1。在上拉电源端VGH与第一节点N1导通时，上拉电源信号可以经第三输入子电路011传输至第一节点N1。从而实现对第一节点N1的电位的控制。
该第四输入子电路012可以分别与第二节点N2、上拉电源端VGH、下拉电源端VGL和第三节点N3耦接。该第四输入子电路012可以用于响应于第二节点N2的电位，控制上拉电源端VGH与第三节点N3的通断，并控制下拉电源端VGL与第三节点N3的通断。
例如，该第四输入子电路012可以在第二节点N2的电位为第一电位时，控制下拉电源端VGL与第三节点N3导通，并在第二节点N2的电位为第二电位时，控制上拉电源端VGH与第三节点N3导通。其中，在下拉电源端VGL与第三节点N3导通时，下拉电源信号可以经第四输入子电路012传输至第三节点N3。在上拉电源端VGH与第三节点N3导通时，上拉电源信号可以经第四输入子电路012传输至第三节点N3。从而实现对第三节点N3的电位的控制。
图5是本公开实施例提供的再一种移位寄存器单元的结构示意图。如图5所示，该第一输出子电路031可以包括：第一输出晶体管T1、第二输出晶体管T2和第三输出晶体管T3。
其中，该第一输出极晶体管可以为互补型金属氧化物半导体(complementary metal-oxide-semiconductor，CMOS)晶体管。参考图5可以看出，CMOS晶体管是指由一个P型晶体管和一个N型晶体管共同构成的互补型MOS集成电路，如此，CMOS晶体管可以具有一个栅极、两个第一极(也可以称为源极)和一 个漏极。当CMOS晶体管的栅极接收到高电位的信号时，其包括的N型晶体管开启，此时，两个第一极中，N型晶体管的第一极耦接的信号端提供的信号可以传输至CMOS晶体管的第二极。当CMOS晶体管的栅极接收到低电位的信号时，其包括的P型晶体管开启，此时，两个第一极中，P型晶体管的第一极耦接的信号端提供的信号可以传输至CMOS晶体管的第二极。
基于对CMOS晶体管的介绍，参考图5，在本公开实施例中，第一输出晶体管T1的栅极可以与第二时钟端CKV2耦接，第一输出晶体管T1的两个第一极可以分别与上拉电源端VGH和第四节点N4耦接，第一输出晶体管T1的第二极可以与第二输出晶体管T2的第二极耦接。
第二输出晶体管T2的第一极可以与上拉电源端VGH耦接，第二输出晶体管T2的栅极和第三输出晶体管T3的栅极均可以与第三节点N3耦接，第三输出晶体管T3的第一极可以与下拉电源端VGL耦接，第三输出晶体管T3的第二极可以与第四节点N4耦接。
第一输出晶体管T1的栅极可以与第二时钟端CKV2耦接，第一输出晶体管T1的一个第一极和第二输出晶体管T2的第一极可以均与上拉电源端VGH耦接，第一输出晶体管T1的另一个第一极可以与第三输出晶体管T3的第二极耦接，第一输出晶体管T1的第二极和第二输出晶体管T2的第二极可以均与第四节点N4耦接，第二输出晶体管T2的栅极和第三输出晶体管T3的栅极可以均与第三节点N3耦接，第三输出晶体管T3的第一极可以与下拉电源端VGL耦接。
可选的，继续参考图5可以看出，第二输出子电路032可以包括：串联在第四节点N4和输出端OUT之间的奇数个第四输出晶体管T4。
其中，每个第四输出晶体管T4可以均为CMOS晶体管，且每个第四输出晶体管T4的两个第一极可以分别与上拉电源端VGH和下拉电源端VGL耦接。
例如，参考图5，其示出的第二输出子电路032共包括三个串联的第四输出晶体管T4。其中，第一个第四输出晶体管T4的栅极与第四节点N4耦接，第一个第四输出晶体管T4的第二极与第二个第四输出晶体管T4的栅极耦接，第二个第四输出晶体管T4的第二极与第三个第四输出晶体管T4的栅极耦接，第三个第四输出晶体管T4的第二极与输出端OUT耦接。
基于第二输出子电路032的结构可知，第二输出子电路032可以将第四节点N4的电位反相处理后，传输至输出端OUT。
如此，也可以采用反相器代替奇数个第四输出晶体管T4。且，因第二输出子电路032的作用是将第四节点N4的电位反相后传输至输出端OUT，故第二输出子电路032包括的三个第四输出晶体管T4也可以称为三级缓冲器(buffer)。
可选的，继续参考图5可以看出，第一输入子电路021可以包括：第一输入晶体管M1、第二输入晶体管M2、第三输入晶体管M3和第四输入晶体管M4。其中，第一输入晶体管M1和第三输入晶体管M3可以均为CMOS晶体管。
第一输入晶体管M1的栅极可以与第一节点N1耦接，第一输入晶体管M1的两个第一极可以分别与上拉电源端VGH和下拉电源端VGL耦接，第一输入晶体管M1的第二极可以与第二输入晶体管M2的栅极耦接，且第二输入晶体管M2的栅极还与第一时钟端CKV1耦接。即，第一输入晶体管M1的第二极和第一时钟端CKV1可以耦接在一起，并同时耦接至第二输入晶体管M2的栅极。
第二输入晶体管M2的第一极可以与下拉电源端VGL耦接，第二输入晶体管M2的第二极可以与第三输入晶体管M3的一个第一极耦接。
第三输入晶体管M3的另一个第一极可以与第四输入晶体管M4的第二极耦接，第三输入晶体管M3的栅极可以与输入控制端CSTV耦接，第三输入晶体管M3的第二极可以与第二节点N2耦接。
第四输入晶体管M4的栅极可以与第一节点N1耦接，第四输入晶体管M4的第一极可以与上拉电源端VGH耦接。
可选的，继续参考图5可以看出，第二输入子电路022可以包括：第五输入晶体管M5、第六输入晶体管M6和第七输入晶体管M7。其中，第六输入晶体管M6可以为CMOS晶体管。
第五输入晶体管M5的栅极可以与第一时钟端CKV1耦接，第五输入晶体管M5第一极可以与上拉电源端VGH耦接，第五输入晶体管M5第二极可以与第六输入晶体管M6的一个第一极耦接。可选的，参考图5，第五输入晶体管M5的栅极可以耦接至第一输入晶体管M1的第二极与第一时钟端CKV1耦接的节点，从而与第一时钟端CKV1间接耦接。
第六输入晶体管M6的另一个第一极可以与第七输入晶体管M7的第二极耦接，第六输入晶体管M6的栅极可以与第三节点N3耦接。
第七输入晶体管M7的第一极可以与下拉电源端VGL耦接，第七输入晶体管M7的栅极可以与第一节点N1耦接。
可选的，继续参考图5可以看出，第三输入子电路011可以包括：第八输入晶体管M8和第九输入晶体管M9。第四输入子电路012可以包括：第十输入晶体管M10。其中，第八输入晶体管M8、第九输入晶体管M9和第十输入晶体管M10可以均为CMOS晶体管。
第八输入晶体管M8的栅极和第九输入晶体管M9的栅极可以均与第一时钟端CKV1耦接，第八输入晶体管M8的两个第一极和第九输入晶体管M9的两个第一极可以均分别与上拉电源端VGH和下拉电源端VGL耦接，第八输入晶体管M8的第二极和第九输入晶体管M9的第二极可以均与第一节点N1耦接。
可选的，参考图5，第九输入晶体管M9的栅极可以耦接至第一输入晶体管M1的第二极与第一时钟端CKV1耦接的节点，从而与第一时钟端CKV1间接耦接。上述第七输入晶体管M7的栅极可以耦接至第九输入晶体管M9的第二极，从而与第一节点N1间接耦接。
第十输入晶体管M10的栅极可以与第二节点N2耦接，第十输入晶体管M10的两个第一极可以分别与上拉电源端VGH和下拉电源端VGL耦接，第十输入晶体管M10的第二极可以与第三节点N3耦接。
基于图5所述结构可知，本公开实施例记载的移位寄存器单元共包括13个P型晶体管(简称PMOS)，以及13个N型晶体管(简称NMOS)，共需要设置第一时钟端CKV1，第二时钟端CKV2和一个输入控制端CSTV共3个控制端。当然，本公开实施例对移位寄存器单元所包括的晶体管的数量并不作限定，能实现上述功能的其他结构也可以适用于本公开实施例的方案。
可选的，在本公开实施例中，至少一个第四输出晶体管T4的宽长比，可以大于移位寄存器单元中除至少一个第四输出晶体管T4之外的其他晶体管的宽长比。即，图5所示的各个晶体管中，至少一个第四输出晶体管T4的宽长比可以设置的相对较大。如此，可以增强第二输出子电路032的整体输出能力，从而可以实现对像素电路中耦接栅极信号端的晶体管(尤其是N型晶体管)高频驱动，满足像素电路驱动所耦接的发光元件的驱动需求。
可选的，在移位寄存器单元包括多个第四输出晶体管T4的前提下，各个第四输出晶体管T4的宽长比可以相同。当然，在一些实施例中，各个第四输出晶体管T4的宽长比也可以不同。
可选的，为使得各电路或子电路实现上述实施例记载的功能，参考图5可 以看出，本公开实施例记载的每个晶体管(包括CMOS晶体管和除CMOS之外的晶体管)中，直接耦接上拉电源端VGH的晶体管可以为P型晶体管，直接耦接下拉电源端VGL的晶体管可以为N型晶体管。除此之外，未直接与上拉电源端VGH或下拉电源端VGL耦接的各个晶体管中，第三输入晶体管M3中耦接第二输入晶体管M2的晶体管为N型晶体管，耦接第四输入晶体管M4的晶体管为P型晶体管。第六输入晶体管M6中，耦接第七输入晶体管M7的晶体管为N型晶体管，耦接第五输入晶体管M5的晶体管为P型晶体管。第一输出晶体管T1中，耦接于第四节点N4和第三输出晶体管T3之间的晶体管为N型晶体管。
其中，第一输入子电路021包括的各个晶体管组成的结构可以称为一个锁存器，再结合第八输入晶体管M8可以称为一个时钟锁存器。第二输入子电路022包括的各个晶体管和第九输入晶体管M9组成的结构也可以称为一个锁存器，再结合第十输入晶体管M10也可以称为一个时钟锁存器。换言之，结合上述电路结构和功能可知，本公开实施例记载的第一输入电路01和第二输入电路02其实可以包括两个时钟锁存器。该两个时钟锁存器可以基于第一时钟端CKV1提供的第一时钟信号和输入控制端CSTV提供的输入控制信号，向第三节点N3写入一个2H宽度的脉冲(pulse)信号，即在第三节点N3处形成一个2H宽度的脉冲，H是指脉冲宽度的单位。然后，第一输出子电路031可以再基于该2H宽度的脉冲信号，向第四节点N4写入一个1H宽度的脉冲信号。换言之，第一输出子电路031可以将2H宽度的脉冲信号移位为1H宽度的脉冲信号。最后，经第二输出子电路032处理后，输出端OUT处可形成1H宽度的脉冲信号，且输出端OUT处形成的脉冲信号的电位与第四节点N4处的电位恰好相反。
此外，结合图5结构也可以看出，本公开实施例记载的移位寄存器单元仅包括多个CMOS晶体管、P型晶体管和N型晶体管，而不包括任何电容。且本公开实施例记载的移位寄存器单元是通过逻辑电路(如，上述记载的时钟锁存器)来控制输出端OUT的电位为高电位或低电位，即进行脉冲信号的输出。如此可以进一步确定，本公开实施例记载的移位寄存器单元的控制方式较为简单。
综上所述，本公开实施例提供了一种移位寄存器单元，该移位寄存器单元中，第一输入电路可以在第一时钟端提供的第一时钟信号和第二节点的电位的控制下，分别控制第一节点的电位和第三节点的电位。第二输入电路可以在第一时钟信号，输入控制端提供的输入控制信号，第三节点的电位和第一节点的 电位的控制下，控制第二节点的电位。输出电路可以在第三节点的控制下，向输出端传输高电位的上拉电源信号或低电位的下拉电源信号。如此，仅通过灵活设置两个时钟端提供的时钟信号和一个输入控制端提供的输入控制信号，即可以实现对输出端的电位的可靠控制，该控制过程较为简单，控制灵活性较高。
图6是本公开实施例提供的一种移位寄存器单元的驱动方法流程图，可以用于驱动如图1至图5任一所示的移位寄存器单元。如图6所示，该方法可以包括：
步骤601、输入阶段，第一输入电路响应于第一时钟端提供的第一时钟信号，控制下拉电源端与第一节点导通。第二输入电路响应于输入控制端提供的输入控制信号和第一时钟信号，控制下拉电源端与第二节点导通。第一输入电路还响应于第二节点的电位，控制上拉电源端与第三节点导通。
步骤602、输出阶段，第一输入电路响应于第一时钟信号，控制上拉电源端与第一节点导通，第二输入电路响应于第一节点的电位和第三节点的电位，控制下拉电源端与第二节点导通，第一输入电路还响应于第二节点的电位，控制上拉电源端与第三节点导通。输出电路响应于第三节点的电位和第二时钟端提供的第二时钟信号，控制上拉电源端与输出端导通。
步骤603、下拉阶段，第一输入电路响应于第一时钟信号，控制下拉电源端与第一节点导通，第二输入电路响应于第一节点的电位和输入控制信号，控制上拉电源端与第二节点导通，第一输入电路还响应于第二节点的电位，控制下拉电源端与第三节点导通，输出电路响应于第三节点的电位和第二时钟信号，控制下拉电源端与输出端导通。
以图5所示结构为例，对本公开实施例提供的移位寄存器单元的工作原理介绍如下。图7是本公开实施例提供的一种移位寄存器单元中各信号端和各节点的时序图。
如图7所示，在输入阶段t1，第一时钟端CKV1提供的第一时钟信号的电位为第一电位。第八输入晶体管M8中的N型晶体管，第九输入晶体管M9中的N型晶体管和第二输入晶体管M2均开启，第五输入晶体管M5关断。下拉电源端VGL与第一节点N1导通，第二电位的下拉电源信号经第八输入晶体管M8中的N型晶体管和第九输入晶体管M9中的N型晶体管传输至第一节点N1。 第四输入晶体管M4和第一输入晶体管M1中的P型晶体管均开启，第七输入晶体管M7关断。第一电位的上拉电源信号经第一输入晶体管M1传输至第二输入晶体管M2的栅极。第二输入晶体管M2保持开启。
输入控制端CSTV提供的输入控制信号的电位为第一电位，第三输入晶体管M3中的N型晶体管开启。此时，下拉电源端VGL与第二节点N2导通，第二电位的下拉电源信号可以经开启的第二输入晶体管M2和第三输入晶体管M3中的N型晶体管传输至第二节点N2。第十输入晶体管M10中的P型晶体管开启，上拉电源端VGH与第三节点N3导通，第一电位的上拉电源信号可以经第十输入晶体管M10中的P型晶体管传输至第三节点N3。第六输入晶体管M6中的N型晶体管和第三输出晶体管T3均开启，第二输出晶体管T2关断。
第二时钟端CKV2提供的第二时钟信号的电位为第二电位，第一输出晶体管T1中的P型晶体管开启。上拉电源端VGH与第四节点N4导通，第一电位的上拉电源信号经第一输出晶体管T1中的P型晶体管传输至第四节点N4。第1个第四输出晶体管T4中的N型晶体管开启，第二电位的下拉电源信号经该开启的N型晶体管传输至第2个第四输出晶体管T4的栅极。第2个第四输出晶体管T4中的P型晶体管开启，第一电位的上拉电源信号经该开启的P型晶体管传输至第3个第四输出晶体管T4的栅极。第3个第四输出晶体管T4中的N型晶体管开启，第二电位的下拉电源信号经该开启的N型晶体管传输至输出端OUT。
在输出阶段t2，第一时钟信号的电位跳变为第二电位，第八输入晶体管M8中的P型晶体管，第九输入晶体管M9中的P型晶体管和第五输入晶体管M5均开启，第二输入晶体管M2关断。上拉电源端VGH与第一节点N1导通，第一电位的上拉电源信号经第八输入晶体管M8中的P型晶体管和第九输入晶体管M9中的P型晶体管传输至第一节点N1。第一输入晶体管M1中的N型晶体管和第七输入晶体管M7均开启，第四输入晶体管M4关断。第二电位的下拉电源信号经第一输入晶体管M1中的N型晶体管传输至第二输入晶体管M2的栅极。第二输入晶体管M2保持开启。
输入控制信号的电位跳变为第二电位。第三输入晶体管M3中的P型晶体管开启。因第三节点N3的电位为第一电位，故第六输入晶体管M6中的N型晶体管、第三输出晶体管T3和第二输出晶体管T2均保持开启。且因第七输入晶体管M7开启，故下拉电源端VGH与第二节点N2保持导通。第二电位的下拉 电源信号可以经开启的第七输入晶体管M7和第六输入晶体管M6中的N型晶体管传输至第二节点N2。第十输入晶体管M10中的P型晶体管保持开启，上拉电源端VGH与第三节点N3保持导通，第一电位的上拉电源信号继续经第十输入晶体管M10中的P型晶体管传输至第三节点N3。即第三节点N3的电位保持为第一电位。第六输入晶体管M6中的N型晶体管和第三输出晶体管T3均保持开启，第二输出晶体管T2关断。
第二时钟信号的电位跳变为第一电位，第一输出晶体管T1中的N型晶体管开启。下拉电源端VGL与第四节点N4导通，第二电位的下拉电源信号经开启的第三输出晶体管T3和第一输出晶体管T1中的N型晶体管传输至第四节点N4。第1个第四输出晶体管T4中的P型晶体管开启，第一电位的上拉电源信号经该开启的P型晶体管传输至第2个第四输出晶体管T4的栅极。第2个第四输出晶体管T4中的N型晶体管开启，第二电位的下拉电源信号经该开启的N型晶体管传输至第3个第四输出晶体管T4的栅极。第3个第四输出晶体管T4中的P型晶体管开启，第一电位的上拉电源信号经该开启的P型晶体管传输至输出端OUT。
在下拉阶段t3，第一时钟信号的电位跳变为第一电位。第八输入晶体管M8中的N型晶体管，第九输入晶体管M9中的N型晶体管和第二输入晶体管M2均开启，第五输入晶体管M5关断。下拉电源端VGL与第一节点N1导通，第二电位的下拉电源信号经第八输入晶体管M8中的N型晶体管和第九输入晶体管M9中的N型晶体管传输至第一节点N1。第四输入晶体管M4和第一输入晶体管M1中的P型晶体管均开启，第七输入晶体管M7关断。第一电位的上拉电源信号经第一输入晶体管M1传输至第二输入晶体管M2的栅极。第二输入晶体管M2保持开启。
输入控制信号的电位保持为第二电位，第三输入晶体管M3中的P型晶体管开启。此时，上拉电源端VGH与第二节点N2导通，第一电位的上拉电源信号可以经开启的第四输入晶体管M4和第三输入晶体管M3中的P型晶体管传输至第二节点N2。第十输入晶体管M10中的N型晶体管开启，下拉电源端VGL与第三节点N3导通，第二电位的下拉电源信号可以经第十输入晶体管M10中的N型晶体管传输至第三节点N3。第六输入晶体管M6中的P型晶体管和第二输出晶体管T2均开启，第三输出晶体管T3关断。
第二时钟信号的电位跳变为第二电位，第一输出晶体管T1中的P型晶体管开启。上拉电源端VGH与第四节点N4导通，第一电位的上拉电源信号经第一输出晶体管T1中的P型晶体管和第二输出晶体管T2传输至第四节点N4。第1个第四输出晶体管T4中的N型晶体管开启，第二电位的下拉电源信号经该开启的N型晶体管传输至第2个第四输出晶体管T4的栅极。第2个第四输出晶体管T4中的P型晶体管开启，第一电位的上拉电源信号经该开启的P型晶体管传输至第3个第四输出晶体管T4的栅极。第3个第四输出晶体管T4中的N型晶体管开启，第二电位的下拉电源信号经该开启的N型晶体管传输至输出端OUT。
此外，图8还示出了三个级联的移位寄存器单元的信号端时序图。参考图8可以看出，三个移位寄存器单元的输出端OUT1、OUT2和OUT3处的电位可以依次为第一电位。
综上所述，本公开实施例提供了一种移位寄存器单元的驱动方法，该方法中，第一输入电路可以在第一时钟端提供的第一时钟信号和第二节点的电位的控制下，分别控制第一节点的电位和第三节点的电位。第二输入电路可以在第一时钟信号，输入控制端提供的输入控制信号，第三节点的电位和第一节点的电位的控制下，控制第二节点的电位。输出电路可以在第三节点的控制下，向输出端传输高电位的上拉电源信号或低电位的下拉电源信号。如此，仅通过灵活设置两个时钟端提供的时钟信号和一个输入控制端提供的输入控制信号，即可以实现对输出端的电位的可靠控制，该控制过程较为简单，控制灵活性较高。
图9是本公开实施例提供的一种栅极驱动电路的结构示意图。如图9所示，该栅极驱动电路可以包括：至少两个级联的如图1至图5任一所示的移位寄存器单00。且该栅极驱动电路可以共连接两条时钟信号线：第一时钟信号线ckv1和第二时钟信号线ckv2。
其中，参考图9可以看出，奇数级移位寄存器单元00的第一时钟端CKV1可以与第一时钟信号线ckv1耦接，奇数级移位寄存器单元00的第二时钟端CKV2可以与第二时钟信号线ckv2耦接。偶数级移位寄存器单元00的第一时钟端CKV1可以与第二时钟信号线ckv2耦接，偶数级移位寄存器单元00的第二时钟端CKV2可以与第一时钟信号线ckv1耦接。即，每相邻的两个移位寄存器单元00包括的两个第一时钟端CKV1可以与第一时钟信号线ckv1和第二时钟 信号线ckv2交替耦接，且每相邻的两个移位寄存器单元00包括的两个第二时钟端CKV2可以与第一时钟信号线ckv1和第二时钟信号线ckv2交替耦接。
此外，在本公开实施例中，除第一级移位寄存器单元00外，每一级移位寄存器单元00的输入控制端CSTV可以与级联的前一级移位寄存器单元00的输出端OUT耦接(图9中未示出)。如此，即达到了级联的目的。
图10是本公开实施例提供的一种显示装置。如图10所示，该显示装置可以包括：显示面板100，以及如图9所示的栅极驱动电路000。
其中，该显示面板100可以包括多个像素电路。该栅极驱动电路000可以与各个像素电路中的栅极信号端耦接，该栅极驱动电路000可以用于为栅极信号端提供栅极驱动信号。
可选的，该显示面板100中的多个像素电路可以阵列排布。栅极驱动电路000中，每个移位寄存器单元的输出端可以与位于同一行的各个像素电路所耦接的栅极信号端耦接，且各个移位寄存器单元所耦接的栅极信号端位于不同行。如，位于同一行的各个像素电路所耦接的栅极信号端可以与一条栅线耦接，该条栅线可以再耦接至一个移位寄存器单元的输出端。
可选的，该栅极驱动电路000可以设置于显示面板100上，即与显示面板集成设置，如此，可以利于显示装置的窄边框设计。
可选的，像素电路包括的各个晶体管中，耦接栅极信号端的晶体管可以为N型铟镓锌氧化物(indium gallium zinc oxide，IGZO)晶体管。
例如，图11示出了一种像素电路的结构示意图。如图11所示，其示出的像素电路共包括第一开关晶体管K1、第二开关晶体管K2、第三开关晶体管K3、第四开关晶体管K4、第五开关晶体管K5、第六开关晶体管K6、第七开关晶体管K7以及存储电容C1。
其中，第一开关晶体管K1的栅极与复位控制端RST(n-1)耦接，第一开关晶体管K1的第一极与复位信号端Vinit耦接，第一开关晶体管K1的第二极与发光元件L1的阳极耦接。发光元件L1的阴极还可以与电源端VSS耦接。该第一开关晶体管K1可以用于响应于复位控制端RST(n-1)提供的复位控制信号，向发光元件L1的阳极传输复位信号端Vinit提供的复位信号。
第二开关晶体管K2的栅极与开关控制端GATE(n-1)耦接，第二开关晶体 管K2的第一极与第一开关晶体管K1的第二极耦接，第二开关晶体管K2的第二极与第三开关晶体管K3的栅极耦接。第二开关晶体管K2可以用于响应于开关控制端GATE(n-1)提供的信号，控制第三开关晶体管K3的栅极与第一开关晶体管K1的第二极导通。
第四开关晶体管K4的栅极和第七开关晶体管K7的栅极可以均与栅极信号端GATE(n)耦接，第四开关晶体管K4的第一极与数据信号端DATA耦接，第四开关晶体管K4的第二极与第三开关晶体管K3的第二极耦接。第七开关晶体管K7的第一极可以与第三开关晶体管K3的第一极耦接，第七开关晶体管K7的第二极可以与第三开关晶体管K3的栅极耦接。第四开关晶体管K4可以用于响应于栅极信号端GATE(n)提供的栅极驱动信号，向第三开关晶体管K3的第二极传输数据信号端DATA提供的数据信号。第七开关晶体管K7可以用于响应于栅极驱动信号，控制第三开关晶体管K3的第一极与第三开关晶体管K3的栅极的通断。
第五开关晶体管K5的栅极和第六开关晶体管K6的栅极均可以与发光控制端EM耦接，第五开关晶体管K5的第一极可以与驱动电源端VDD耦接，第五开关晶体管K5的第二极可以与第三开关晶体管K3的第一极耦接。第六开关晶体管K6的第一极可以与第三开关晶体管K3的第二极耦接，第六开关晶体管K6的第二极可以与发光元件L1的阳极耦接。第五开关晶体管K5可以用于响应于发光控制端EM提供的发光控制信号，向第三开关晶体管K3的第一极传输与驱动电源端VDD提供的驱动电源信号。第六开关晶体管K6可以用于响应于发光控制信号，控制第三开关晶体管K3的第二极与发光元件L1的阳极的通断。
存储电容C1的一端可以与第三开关晶体管K3的栅极耦接，存储电容C1的另一端可以与驱动电源端VDD耦接。
可选的，图11所示结构中，耦接栅极信号端GATE(n)的第四开关晶体管K4和第七开关晶体管K7可以均为N型晶体管，且可以均为IGZO材料制成的晶体管。耦接发光控制端EM的第五开关晶体管K5和第六开关晶体管K6可以均为N型晶体管。其余的晶体管(包括第一开关晶体管K1、第二开关晶体管K2和第三开关晶体管K3)可以均为P型晶体管。
结合图11所示像素电路的结构，图12还示出了像素电路中各信号端的时序图。参考图12可以看出，驱动发光元件L1发光的过程可以包括：重置阶段 t01、写入阶段t02和发光阶段t03。其中，图12均以高电位代表有效电位。
其中，在重置阶段t01，GATE(n-1)提供的信号的电位和RST(n-1)提供的信号的电位可以为有效电位。此时，第一开关晶体管K1和第二开关晶体管K2开启，复位信号端Vinit可以向第三开关晶体管K3的栅极和发光元件L1的阳极传输复位信号。在写入阶段t02，栅极信号端GATE(n)提供的栅极驱动信号的电位可以为有效电位。此时，第四开关晶体管K4和第七开关晶体管K7开启，数据信号端DATA可以向第三开关晶体管K3的栅极传输数据信号。在发光阶段t03，发光控制端EM提供的发光控制信号的电位为有效电位。第五开关晶体管K5和第六开关晶体管K6开启，且第三开关晶体管K3在该阶段也保持开启。驱动电源端VDD可以向第三开关晶体管K3的第一极传输驱动电源信号，第三开关晶体管K3可以基于其栅极的电位和第一极的电位，向第六开关晶体管K6的第一极传输驱动电流。第六开关晶体管K6再将该驱动电流传输至发光元件L1，发光元件L1发光。
结合图7所示时序图可以看出，移位寄存器单元的输出端OUT处的时序与图12所示栅极信号端GATE(n)的时序可以一致。
受N型IGZO晶体管的自身特性的影响，N型IGZO晶体管的栅极需要响应于较强的驱动信号才能可靠工作。相关技术的移位寄存器单元输出至栅极信号端的信号的驱动能力较弱，导致如图11所示结构中，第四开关晶体管K4的驱动能力较弱，无法将数据信号可靠传输至第三开关晶体管K3的第二极，进而导致最终无法可靠驱动发光元件L1发光。而对于本公开实施例提供的移位寄存器单元，因其输出能力较强，故可以确保第四开关晶体管K4将数据信号可靠传输至第三开关晶体管K3的第二极，进而确保发光元件L1的发光效果较好。
当然，图11仅是示意性示出一种可选的7T1C(即，7个晶体管和1个电容)的像素电路。本公开实施例对移位寄存器单元所驱动的像素电路结构不做限定，如还可以用于驱动6T1C结构的像素电路。
可选的，本公开实施例记载的像素电路中的晶体管还可以为低温多晶硅氧化物(low temperature poly crystalline oxide，LTPO)晶体管。
本公开实施例提供的显示装置可以为：有源矩阵有机发光二极管(active-matrix organic light-emitting diode，AMOLED)显示装置、有机发光二极管(organic light-emitting diode，OLED)显示装置和液晶显示装置等任何具有 显示功能的产品或部件。
应当理解的是，本公开实施例说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，例如能够根据本申请实施例图示或描述中给出那些以外的顺序实施。
应当理解的是，本公开实施例说明书中的术语“和/或”，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (15)

  1. 一种移位寄存器单元，所述移位寄存器单元包括：
    第一输入电路，分别与第一时钟端、第一节点、第二节点、第三节点、上拉电源端和下拉电源端耦接，所述第一输入电路用于响应于所述第一时钟端提供的第一时钟信号，控制所述上拉电源端与所述第一节点的通断，并控制所述下拉电源端与所述第一节点的通断；以及用于响应于所述第二节点的电位，控制所述上拉电源端与所述第三节点的通断，并控制所述下拉电源端与所述第三节点的通断；
    第二输入电路，分别与所述第一节点、所述第二节点、所述第三节点、所述上拉电源端、所述下拉电源端、输入控制端和所述第一时钟端耦接，所述第二输入电路用于响应于所述第一节点的电位、所述第三节点的电位、所述第一时钟信号和所述输入控制端提供的输入控制信号，控制所述上拉电源端与所述第二节点的通断，并控制所述下拉电源端与所述第二节点的通断；
    以及输出电路，分别与所述上拉电源端、所述下拉电源端、所述第三节点、第二时钟端和输出端耦接，所述输出电路用于响应于所述第三节点的电位和所述第二时钟端提供的第二时钟信号，控制所述上拉电源端与所述输出端的通断，并控制所述下拉电源端与所述输出端的通断。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述输出电路包括：第一输出子电路和第二输出子电路；
    所述第一输出子电路分别与所述第二时钟端、所述第三节点、所述上拉电源端、所述下拉电源端和第四节点耦接，所述第一输出子电路用于响应于所述第二时钟信号和所述第三节点的电位，控制所述上拉电源端与所述第四节点的通断，并控制所述下拉电源端与所述第四节点的通断；
    所述第二输出子电路分别与所述第四节点、所述上拉电源端、所述下拉电源端和所述输出端耦接，所述第二输出子电路用于响应于所述第四节点的电位，控制所述上拉电源端与所述输出端的通断，并控制所述下拉电源端与所述输出端的通断。
  3. 根据权利要求2所述的移位寄存器单元，其中，所述第一输出子电路包括：第一输出晶体管、第二输出晶体管和第三输出晶体管，所述第一输出晶体管为互补型金属氧化物半导体CMOS晶体管；
    所述第一输出晶体管的栅极与所述第二时钟端耦接，所述第一输出晶体管的一个第一极和所述第二输出晶体管的第一极均与所述上拉电源端耦接，所述第一输出晶体管的另一个第一极与所述第三输出晶体管的第二极耦接，所述第一输出晶体管的第二极和所述第二输出晶体管的第二极均与所述第四节点耦接，所述第二输出晶体管的栅极和所述第三输出晶体管的栅极均与所述第三节点耦接，所述第三输出晶体管的第一极与所述下拉电源端耦接。
  4. 根据权利要求2所述的移位寄存器单元，其中，所述第二输出子电路包括：串联在所述第四节点和所述输出端之间的奇数个第四输出晶体管；
    每个所述第四输出晶体管均为CMOS晶体管，且每个所述第四输出晶体管的两个第一极分别与所述上拉电源端和所述下拉电源端耦接。
  5. 根据权利要求4所述的移位寄存器单元，其中，所述第二输出子电路包括：三个所述第四输出晶体管；
    其中，第一个所述第四输出晶体管的栅极与所述第四节点耦接，第一个所述第四输出晶体管的第二极与第二个所述第四输出晶体管的栅极耦接，第二个所述第四输出晶体管的第二极与第三个所述第四输出晶体管的栅极耦接，第三个所述第四输出晶体管的第二极与所述输出端耦接。
  6. 根据权利要求4所述的移位寄存器单元，其中，至少一个第四输出晶体管的宽长比，大于所述移位寄存器单元中除所述至少一个第四输出晶体管之外的其他晶体管的宽长比。
  7. 根据权利要求1至6任一所述的移位寄存器单元，其中，所述第二输入电路包括：第一输入子电路和第二输入子电路；
    所述第一输入子电路分别与所述第一节点、所述第一时钟端、所述输入控制端、所述上拉电源端、所述下拉电源端和所述第二节点耦接，所述第一输入 子电路用于响应于所述第一节点的电位、所述输入控制信号和所述第一时钟信号，控制所述上拉电源端与所述第二节点的通断，并控制所述下拉电源端与所述第二节点的通断；
    所述第二输入子电路分别与所述第一时钟端、所述第一节点、所述第二节点、所述第三节点、所述上拉电源端和所述下拉电源端耦接，所述第二输入子电路用于响应于所述第一节点的电位、所述第三节点的电位和所述第一时钟信号，控制所述上拉电源端与所述第二节点的通断，并控制所述下拉电源端与所述第二节点的通断。
  8. 根据权利要求7所述的移位寄存器单元，其中，所述第一输入子电路包括：第一输入晶体管、第二输入晶体管、第三输入晶体管和第四输入晶体管；所述第一输入晶体管和所述第三输入晶体管均为CMOS晶体管；
    所述第一输入晶体管的栅极与所述第一节点耦接，所述第一输入晶体管的两个第一极分别与所述上拉电源端和所述下拉电源端耦接，所述第一输入晶体管的第二极与所述第二输入晶体管的栅极耦接，且所述第二输入晶体管的栅极还与所述第一时钟端耦接；
    所述第二输入晶体管的第一极与所述下拉电源端耦接，所述第二输入晶体管的第二极与所述第三输入晶体管的一个第一极耦接；
    所述第三输入晶体管的另一个第一极与所述第四输入晶体管的第二极耦接，所述第三输入晶体管的栅极与所述输入控制端耦接，所述第三输入晶体管的第二极与所述第二节点耦接；
    所述第四输入晶体管的栅极与所述第一节点耦接，所述第四输入晶体管的第一极与所述上拉电源端耦接。
  9. 根据权利要求7所述的移位寄存器单元，其中，所述第二输入子电路包括：第五输入晶体管、第六输入晶体管和第七输入晶体管；所述第六输入晶体管为CMOS晶体管；
    所述第五输入晶体管的栅极与所述第一时钟端耦接，所述第五输入晶体管第一极与所述上拉电源端耦接，所述第五输入晶体管第二极与所述第六输入晶体管的一个第一极耦接；
    所述第六输入晶体管的另一个第一极与所述第七输入晶体管的第二极耦接，所述第六输入晶体管的栅极与所述第三节点耦接；
    所述第七输入晶体管的第一极与所述下拉电源端耦接，所述第七输入晶体管的栅极与所述第一节点耦接。
  10. 根据权利要求1至9任一所述的移位寄存器单元，其中，所述第一输入电路包括：第三输入子电路和第四输入子电路；
    所述第三输入子电路分别与所述第一时钟端、所述上拉电源端、所述下拉电源端和所述第一节点耦接，所述第三输入子电路用于响应于所述第一时钟信号，控制所述上拉电源端与所述第一节点的通断，并控制所述下拉电源端与所述第一节点的通断；
    所述第四输入子电路分别与所述第二节点、所述上拉电源端、所述下拉电源端和所述第三节点耦接，所述第四输入子电路用于响应于所述第二节点的电位，控制所述上拉电源端与所述第三节点的通断，并控制所述下拉电源端与所述第三节点的通断。
  11. 根据权利要求10所述的移位寄存器单元，其中，所述第三输入子电路包括：第八输入晶体管和第九输入晶体管；所述第四输入子电路包括：第十输入晶体管；所述第八输入晶体管、所述第九输入晶体管和所述第十输入晶体管均为CMOS晶体管；
    所述第八输入晶体管的栅极和所述第九输入晶体管的栅极均与所述第一时钟端耦接，所述第八输入晶体管的两个第一极和所述第九输入晶体管的两个第一极均分别与所述上拉电源端和所述下拉电源端耦接，所述第八输入晶体管的第二极和所述第九输入晶体管的第二极均与所述第一节点耦接；
    所述第十输入晶体管的栅极与所述第二节点耦接，所述第十输入晶体管的两个第一极分别与所述上拉电源端和所述下拉电源端耦接，所述第十输入晶体管的第二极与所述第三节点耦接。
  12. 一种移位寄存器单元的驱动方法，其中，用于驱动如权利要求1至11任一所述的移位寄存器单元；所述方法包括：
    输入阶段，第一输入电路响应于第一时钟端提供的第一时钟信号，控制下拉电源端与第一节点导通；第二输入电路响应于输入控制端提供的输入控制信号和所述第一时钟信号，控制所述下拉电源端与第二节点导通；所述第一输入电路还响应于所述第二节点的电位，控制上拉电源端与第三节点导通；
    输出阶段，所述第一输入电路响应于所述第一时钟信号，控制所述上拉电源端与所述第一节点导通，所述第二输入电路响应于所述第一节点的电位和所述第三节点的电位，控制所述下拉电源端与所述第二节点导通，所述第一输入电路还响应于所述第二节点的电位，控制所述上拉电源端与所述第三节点导通；输出电路响应于所述第三节点的电位和第二时钟端提供的第二时钟信号，控制所述上拉电源端与所述输出端导通；
    下拉阶段，所述第一输入电路响应于所述第一时钟信号，控制所述下拉电源端与所述第一节点导通，所述第二输入电路响应于所述第一节点的电位和所述输入控制信号，控制所述上拉电源端与所述第二节点导通，所述第一输入电路还响应于所述第二节点的电位，控制所述下拉电源端与所述第三节点导通，所述输出电路响应于所述第三节点的电位和所述第二时钟信号，控制所述下拉电源端与所述输出端导通。
  13. 一种栅极驱动电路，其中，所述栅极驱动电路包括：至少两个级联的如权利要求1至11任一所述的移位寄存器单元；
    奇数级移位寄存器单元的第一时钟端与第一时钟信号线耦接，奇数级移位寄存器单元的第二时钟端与第二时钟信号线耦接；
    偶数级移位寄存器单元的第一时钟端与第二时钟信号线耦接，偶数级移位寄存器单元的第二时钟端与第一时钟信号线耦接。
  14. 一种显示装置，其中，所述显示装置包括：显示面板，以及如权利要求13所述的栅极驱动电路，所述显示面板包括多个像素电路；
    所述栅极驱动电路与所述像素电路中的栅极信号端耦接，所述栅极驱动电路用于为所述栅极信号端提供栅极驱动信号。
  15. 根据权利要求14所述的显示装置，其中，所述像素电路包括：第一开关晶体管、第二开关晶体管、第三开关晶体管、第四开关晶体管、第五开关晶体管、第六开关晶体管、第七开关晶体管和存储电容；
    所述第一开关晶体管的栅极与复位控制端耦接，所述第一开关晶体管的第一极与复位信号端耦接，所述第一开关晶体管的第二极与所述第二开关晶体管的第一极、所述第六开关晶体管的第二极以及发光元件的阳极耦接；
    所述第二开关晶体管的栅极与开关控制端耦接，所述第二开关晶体管的第二极与所述第三开关晶体管的栅极耦接；
    所述第五开关晶体管的栅极和所述第六开关晶体管的栅极均与发光控制端耦接，所述第五开关晶体管的第一极与驱动电源端耦接，所述第五开关晶体管的第二极与所述第三开关晶体管的第一极耦接；所述第六开关晶体管的第一极与所述第三开关晶体管的第二极耦接；
    所述第四开关晶体管的栅极和所述第七开关晶体管的栅极均与所述栅极信号端耦接；所述第四开关晶体管的第一极与数据信号端耦接，所述第四开关晶体管的第二极与所述第三开关晶体管的第二极耦接；所述第七开关晶体管的第一极与所述第三开关晶体管的第一极耦接，所述第七开关晶体管的第二极与所述第三开关晶体管的栅极耦接；
    所述存储电容的一端与所述第三开关晶体管的栅极耦接，所述存储电容的另一端与所述驱动电源端耦接；
    其中，所述第四开关晶体管和所述第七开关晶体管均为N型铟镓锌氧化物IGZO晶体管，且所述栅极驱动电路中移位寄存器单元的输出端与所述第四开关晶体管的栅极和所述第七开关晶体管的栅极耦接。
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