WO2020259319A1 - 移位寄存器单元、栅极驱动电路、显示装置和控制方法 - Google Patents

移位寄存器单元、栅极驱动电路、显示装置和控制方法 Download PDF

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Publication number
WO2020259319A1
WO2020259319A1 PCT/CN2020/095752 CN2020095752W WO2020259319A1 WO 2020259319 A1 WO2020259319 A1 WO 2020259319A1 CN 2020095752 W CN2020095752 W CN 2020095752W WO 2020259319 A1 WO2020259319 A1 WO 2020259319A1
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node
electrically connected
level
circuit
electrode
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PCT/CN2020/095752
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English (en)
French (fr)
Inventor
冯雪欢
李永谦
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京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Priority to US17/264,050 priority Critical patent/US11676541B2/en
Publication of WO2020259319A1 publication Critical patent/WO2020259319A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes

Definitions

  • the present disclosure relates to the field of display technology, in particular to a shift register unit, a gate drive circuit, a display device and a control method.
  • gate drive circuits can be used to replace gate integrated circuits, thereby reducing costs.
  • OLED Organic Light Emitting Diode
  • OLED Organic Light Emitting Diode
  • a shift register unit including: a first input sub-circuit configured to change the potential of the first node from the first node under the control of the first input signal in the first stage The first level is changed to the second level; the first output sub-circuit, electrically connected to the first node, is configured to output a gate drive signal under the control of the first clock signal in the first stage, and In the second stage after the first stage, a compensation drive signal is output under the control of the first clock signal; a first reset sub-circuit is electrically connected to the first node and used to provide the first level Is configured to reset the potential of the first node to the first level under the control of the first reset signal; the second input sub-circuit is electrically connected to the first Between the node and the first voltage terminal, it is configured to change the potential of the second node from the first level to the second level under the control of the second input signal in the first stage, and change The second level is maintained to the second stage; and a first input sub-circuit configured to change the potential of the second node
  • the first output sub-circuit is configured to change the potential of the first node from the second level to the second level under the control of the first clock signal in the first stage Third level to output the gate drive signal, and in the second stage, under the control of the first clock signal, the potential of the first node is changed from the second level to the The third level to output the compensation drive signal; wherein, the second level is between the first level and the third level; the third input sub-circuit is also configured to Under the control of the third input signal, the potential of the second node is changed from the second level to a fourth level; wherein, the second level is between the first level and the first level Between four levels.
  • the second input sub-circuit includes a first switching transistor and a first capacitor; wherein the first electrode of the first switching transistor is electrically connected to the first node, and the first switching transistor The second electrode of the first capacitor is electrically connected to the second node, the gate of the first switching transistor is configured to receive the second input signal; the first terminal of the first capacitor is electrically connected to the second node , The second terminal of the first capacitor is electrically connected to the first voltage terminal.
  • the third input sub-circuit includes a second switching transistor and a third switching transistor; wherein the first electrode of the second switching transistor is electrically connected to the gate of the third switching transistor, and The first electrode of the second switching transistor is configured to receive the third input signal, the second electrode of the second switching transistor is electrically connected to the first electrode of the third switching transistor, and the second switch The gate of the transistor is electrically connected to the second node; the second electrode of the third switching transistor is electrically connected to the first node.
  • the first reset sub-circuit includes a fourth switch transistor, wherein the first electrode of the fourth switch transistor is electrically connected to the first node, and the second electrode of the fourth switch transistor It is electrically connected to the first voltage terminal, and the gate of the fourth switch transistor is configured to receive the first reset signal.
  • the shift register unit further includes: a second reset sub-circuit configured to reset the potential of the first node and the potential of the second node under the control of a second reset signal .
  • the second reset sub-circuit includes a fifth switch transistor, wherein the first electrode of the fifth switch transistor is electrically connected to the first node, and the second electrode of the fifth switch transistor It is electrically connected to the first voltage terminal, and the gate of the fifth switch transistor is configured to receive the second reset signal.
  • the shift register unit further includes: a second output sub-circuit configured to output a carry control signal under the control of a second clock signal in the first stage.
  • the shift register unit further includes: a noise reduction sub-circuit configured to maintain the potential of the first node at the first node when the potential of the first node is reset A level; and a potential holding sub-circuit configured to maintain the potential of the output terminal of the first output sub-circuit at a fifth level when the potential of the first node is reset, and the The potential of the output terminal of the second output sub-circuit is maintained at the first level.
  • the noise reduction sub-circuit includes a sixth switch transistor, a seventh switch transistor, and an eighth switch transistor; wherein the first electrode and the gate of the sixth switch transistor are electrically connected to provide The second voltage terminal of the second level, the second electrode of the sixth switch transistor is electrically connected to the third node; the first electrode of the seventh switch transistor is electrically connected to the third node, the The second electrode of the seventh switch transistor is electrically connected to the first voltage terminal, the gate of the seventh switch transistor is electrically connected to the first node; the first electrode of the eighth switch transistor is electrically connected to the In the first node, the second electrode of the eighth switch transistor is electrically connected to the first voltage terminal, and the gate of the eighth switch transistor is electrically connected to the third node.
  • the potential holding sub-circuit includes a ninth switching transistor and a tenth switching transistor; wherein the first electrode of the ninth switching transistor is electrically connected to the output terminal of the second output sub-circuit, so The second electrode of the ninth switch transistor is electrically connected to the first voltage terminal, the gate of the ninth switch transistor is electrically connected to the third node; the first electrode of the tenth switch transistor is electrically connected to The output terminal of the first output sub-circuit, the second electrode of the tenth switch transistor is electrically connected to the third voltage terminal for providing the fifth level, and the gate of the tenth switch transistor is electrically connected To the third node.
  • the first output sub-circuit includes an eleventh switching transistor and a second capacitor; wherein the first electrode of the eleventh switching transistor is configured to receive the first clock signal, the The second electrode of the eleventh switching transistor serves as the output terminal of the first output sub-circuit, the gate of the eleventh switching transistor is electrically connected to the first node; the first terminal of the second capacitor is electrically connected Connected to the gate of the eleventh switching transistor, and the second terminal of the second capacitor is electrically connected to the second electrode of the eleventh switching transistor.
  • the second output sub-circuit includes a twelfth switching transistor; wherein the first electrode of the twelfth switching transistor is configured to receive the second clock signal, and the twelfth switch The second electrode of the transistor serves as the output terminal of the second output sub-circuit, and the gate of the twelfth switch transistor is electrically connected to the first node.
  • the first input sub-circuit includes a thirteenth switching transistor; wherein the first electrode of the thirteenth switching transistor is electrically connected to a fourth voltage terminal for providing the second level
  • the second electrode of the thirteenth switching transistor is electrically connected to the first node, and the gate of the thirteenth switching transistor is configured to receive the first input signal.
  • the shift register unit further includes a second reset sub-circuit, a second output sub-circuit, a noise reduction sub-circuit and a potential holding sub-circuit;
  • the second input sub-circuit includes a first switching transistor and A first capacitor; wherein the first electrode of the first switching transistor is electrically connected to the first node, the second electrode of the first switching transistor is electrically connected to the second node, and the first switching transistor The gate of the is configured to receive the second input signal; the first terminal of the first capacitor is electrically connected to the second node, and the second terminal of the first capacitor is electrically connected to the first voltage terminal
  • the third input sub-circuit includes a second switch transistor and a third switch transistor; wherein, the first electrode of the second switch transistor is electrically connected to the gate of the third switch transistor, and the second switch The first electrode of the transistor is configured to receive the third input signal, the second electrode of the second switching transistor is electrically connected to the first electrode of the third switching transistor, and the gate of the second switching transistor is electrically connected.
  • the first reset sub-circuit includes a fourth switch transistor; wherein, the fourth switch transistor One electrode is electrically connected to the first node, the second electrode of the fourth switch transistor is electrically connected to the first voltage terminal, and the gate of the fourth switch transistor is configured to receive the first reset signal
  • the second reset sub-circuit includes a fifth switch transistor; wherein the first electrode of the fifth switch transistor is electrically connected to the first node, and the second electrode of the fifth switch transistor is electrically connected to the At the first voltage terminal, the gate of the fifth switch transistor is configured to receive a second reset signal;
  • the noise reduction sub-circuit includes a sixth switch transistor, a seventh switch transistor, and an eighth switch transistor; wherein, the first The first electrode and the gate of the six switching transistors are electrically connected to the second voltage terminal for providing the second level, and the second electrode of the sixth switching transistor is electrically connected to the third node; the seventh The first electrode of the switching transistor is electrically
  • the first electrode of the eighth switch transistor is electrically connected to the first node, the second electrode of the eighth switch transistor is electrically connected to the first voltage terminal, and the gate of the eighth switch transistor
  • the electrode is electrically connected to the third node;
  • the potential holding sub-circuit includes a ninth switching transistor and a tenth switching transistor; wherein the first electrode of the ninth switching transistor is electrically connected to the second output sub-circuit Output terminal, the second electrode of the ninth switch transistor is electrically connected to the first voltage terminal, the gate of the ninth switch transistor is electrically connected to the third node;
  • the first electrode of the tenth switch transistor The electrode is electrically connected to the output terminal of the first output sub-circuit, the second electrode of the tenth switching transistor is electrically connected to the third voltage terminal for providing the fifth level, and the first The gate of the ten switching transistor is electrically connected to the third node;
  • the first output sub-circuit includes an eleventh switching transistor and a second capacitor; wherein the first electrode of the eleventh switching transistor is configured
  • a gate driving circuit including: a plurality of shift register units as described above.
  • the plurality of shift register units includes N shift register units, and N is a positive integer; among the N shift register units, the carry output of the i-x1th shift register unit
  • the control signal is used as the first input signal of the i-th shift register unit, and the first input signals of the first to x1th shift register units are respectively the first input signals output by the external circuit, where x1+1 ⁇ i ⁇ N and i is a positive integer, x1 is a positive integer; among the N shift register units, the carry control signal output by the j+x2th shift register unit is used as the first shift register unit of the jth shift register unit.
  • the reset signal, the first reset signal of the N-x2+1th to the Nth shift register unit is the first reset signal output by the external circuit, where 1 ⁇ j ⁇ N-x2 and j is positive Integer, x2 is a positive integer.
  • a display device including: the gate driving circuit as described above.
  • a control method for a shift register unit including: in a first stage, a first input sub-circuit under the control of a first input signal, The potential changes from the first level to the second level, and the second input sub-circuit, under the control of the second input signal, changes the potential of the second node from the first level to the second level, and changes the first level to the second level.
  • the second level of the two nodes is maintained to the second stage after the first stage; the first output sub-circuit changes the potential of the first node from the second level under the control of the first clock signal Is the third level to output the gate drive signal, wherein the second level is between the first level and the third level; the first reset sub-circuit is under the control of the first reset signal , Reset the potential of the first node to the first level; in the second stage, the third input sub-circuit under the control of the third input signal resets the potential of the first node From the first level to the second level; and the first output sub-circuit changes the potential of the first node from the second level under the control of the first clock signal Is the third level to output a compensation drive signal.
  • FIG. 1 is a structural diagram showing a shift register unit according to an embodiment of the present disclosure
  • FIG. 2 is a circuit structure diagram showing a shift register unit according to an embodiment of the present disclosure
  • 3A is a structural diagram showing a shift register unit according to another embodiment of the present disclosure.
  • 3B is a circuit structure diagram showing a shift register unit according to another embodiment of the present disclosure.
  • FIG. 4 is a timing diagram showing control signals for a shift register unit according to an embodiment of the present disclosure
  • 5A is a structural diagram showing a shift register unit according to another embodiment of the present disclosure.
  • 5B is a circuit structure diagram of a shift register unit according to another embodiment of the present disclosure.
  • FIG. 6 is a structural diagram showing a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 7 is a timing diagram showing a control signal for a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 8 is a flowchart showing a control method for a shift register unit according to an embodiment of the present disclosure
  • FIG. 9 is a structural diagram showing a display device according to an embodiment of the present disclosure.
  • a specific device when it is described that a specific device is located between the first device and the second device, there may or may not be an intermediate device between the specific device and the first device or the second device.
  • the specific device When it is described that a specific device is electrically connected to another device, the specific device may be directly electrically connected to the other device without an intervening device, or may not be directly electrically connected to the other device but having an intervening device.
  • the OLED display panel includes a pixel array, and the pixel array includes multiple rows and multiple columns of sub-pixel units.
  • Each sub-pixel unit includes a pixel circuit and a light-emitting element.
  • the pixel circuit receives various signals to drive the light-emitting element to emit light; the pixel circuit may include a driving transistor, a scanning transistor, a storage capacitor, and the like.
  • the threshold voltage of the driving transistor in each pixel circuit may be different due to the manufacturing process, and the threshold voltage of the driving transistor may drift due to, for example, the influence of temperature changes. Therefore, the difference in the threshold voltage of each driving transistor may cause poor display (for example, uneven display), so the threshold voltage needs to be compensated.
  • the pixel circuit can be, for example, the traditional 2T1C (drive transistor, scan transistor, and storage capacitor) pixel circuit and then introduce a sensing transistor, thereby obtaining 3T1C (drive transistor, scan transistor, sensing transistor). And storage capacitor) pixel circuit.
  • the driving transistor may be an N-type transistor
  • the first electrode of the sensing transistor may be connected to the source of the driving transistor
  • the second electrode of the sensing transistor may be connected to the sensing circuit via a sensing line
  • the gate of the sensing transistor It is configured to receive the compensation driving signal via the gate line (for example, the gate of the sensing transistor and the gate of the scanning transistor may be connected to the same gate line).
  • the gate drive circuit composed of shift register units needs to provide driving signals for scanning transistors and sensing transistors to the sub-pixel units in the display panel, for example, for the display stage of one frame.
  • a compensation driving signal for the sensing transistor is provided in the vertical blanking phase of one frame.
  • the two driving signals may be waveforms with different periods and different pulse widths.
  • the inventor of the present disclosure found that it is relatively difficult for the gate drive circuit to output the gate drive signal for display and the compensation drive signal for sub-pixel compensation.
  • the embodiments of the present disclosure provide a shift register unit for a gate driving circuit, so as to output a gate driving signal and a compensation driving signal respectively.
  • the shift register unit according to some embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.
  • Fig. 1 is a structural diagram showing a shift register unit according to an embodiment of the present disclosure.
  • the shift register unit may include a first input sub-circuit 110, a first output sub-circuit 130, a first reset sub-circuit 140, a second input sub-circuit 120, and a third input sub-circuit 190.
  • the first input sub-circuit 110 may be configured to change the potential of the first node Q from the first level to the second level in the first stage under the control of the first input signal V IN .
  • the first output sub-circuit 130 is electrically connected to the first node Q.
  • the first output sub-circuit 130 may be configured to output the gate driving signal under the control of the first clock signal CLKE in the first stage, and in the second stage after the first stage, in the first stage of the clock signal CLKE.
  • Output compensation drive signal under control. "OUT" in FIG. 1 represents the signal output by the first output sub-circuit.
  • the first reset sub-circuit 140 is electrically connected between the first node Q and the first voltage terminal 101.
  • the first voltage terminal 101 is used to provide a first level.
  • the first reset sub-circuit 140 may be configured to reset the potential of the first node Q under the control of the first reset signal V RE .
  • the first reset sub-circuit can reset the potential of the first node of the shift register unit of the current row, and reset the potential of the first node to the first level.
  • the second input sub-circuit 120 is electrically connected between the first node Q and the first voltage terminal 101.
  • the first voltage terminal 101 is used to provide a first level.
  • the second input sub-circuit 120 may be configured to change the potential of the second node H from the first level to the second level in the first stage under the control of the second input signal OE, and change the second level The level is maintained to the second stage.
  • the third input sub-circuit 190 is electrically connected to the second node H.
  • the third input sub-circuit 190 is configured to change the reset potential of the first node Q from the first level to the second level under the control of the third input signal CLKA in the second stage.
  • the first stage may be the display stage of one frame
  • the second stage may be the field blanking stage of one frame. It should be noted that the meaning of the first stage and the second stage in the subsequent embodiment may be the same as the meaning of the first stage and the second stage in this embodiment.
  • the shift register unit includes a first input sub-circuit, a first output sub-circuit, a first reset sub-circuit, a second input sub-circuit, and a third input sub-circuit.
  • the first input sub-circuit changes the potential of the first node from the first level to the second level under the control of the first input signal in the first stage.
  • the first output sub-circuit outputs the gate drive signal under the control of the first clock signal in the first stage, and outputs the compensation drive signal under the control of the first clock signal in the second stage.
  • the first reset sub-circuit resets the potential of the first node under the control of the first reset signal.
  • the second input sub-circuit changes the potential of the second node from the first level to the second level under the control of the second input signal in the first stage, and maintains the second level to the second stage.
  • the third input sub-circuit changes the reset potential of the first node from the first level to the second level under the control of the third input signal in the second stage.
  • the shift register unit achieves the purpose of outputting the gate driving signal in the first stage (for example, the display stage) and outputting the compensation driving signal in the second stage (for example, the vertical blanking stage).
  • the gate drive signal can be used in the display process of the display device to be output through the corresponding gate line; the compensation drive signal is also output through the corresponding gate line as the gate required in the sub-pixel compensation process.
  • Polar signal can be used in the display process of the display device to be output through the corresponding gate line; the compensation drive signal is also output through the corresponding gate line as the gate required in the sub-pixel compensation process.
  • the method or process of the sub-pixel compensation can adopt a known technology, which will not be described in detail here.
  • the first output sub-circuit 130 may be configured to change the potential of the first node Q from the second level to the third level in the first stage under the control of the first clock signal CLKE to output The gate drive signal, and in the second stage, under the control of the first clock signal CLKE, the potential of the first node Q is changed from the second level to the third level to output the compensation drive signal.
  • the second level is between the first level and the third level.
  • the first level is lower than the second level, and the second level is lower than the third level.
  • the first level is a low level
  • the second level is a high level
  • the third level is a higher level than the second level.
  • the first level is higher than the second level
  • the second level is higher than the third level.
  • the first level is a high level
  • the second level is a low level
  • the third level is a lower level than the second level.
  • the third input sub-circuit 190 may also be configured to change the potential of the second node from the second level to the fourth level under the control of the third input signal CLKA.
  • the second level is between the first level and the fourth level.
  • the first level is lower than the second level, and the second level is lower than the fourth level.
  • the first level is a low level
  • the second level is a high level
  • the fourth level is a higher level than the second level.
  • the first level is higher than the second level
  • the second level is higher than the fourth level.
  • the first level is a high level
  • the second level is a low level
  • the fourth level is a lower level than the second level.
  • the fourth level may be equal to the third level or not equal to the third level.
  • FIG. 2 is a circuit structure diagram showing a shift register unit according to an embodiment of the present disclosure.
  • the second input sub-circuit 120 may include a first switching transistor M1 and a first capacitor C1.
  • the first electrode of the first switching transistor M1 is electrically connected to the first node Q.
  • the second electrode of the first switching transistor M1 is electrically connected to the second node H.
  • the gate of the first switching transistor M1 is configured to receive the second input signal OE.
  • the first switching transistor M1 may be an N-channel Metal Oxide Semiconductor (N-channel Metal Oxide Semiconductor) transistor or a PMOS (P-channel Metal Oxide Semiconductor, P-channel Metal Oxide Semiconductor) transistor.
  • the first terminal of the first capacitor C1 is electrically connected to the second node H.
  • the second terminal of the first capacitor C1 is electrically connected to the first voltage terminal 101.
  • the first voltage terminal can be used to provide a low level VGL1 (as the first level).
  • the low level VGL1 may be a negative level.
  • the first capacitor C1 may be an external capacitor or a parasitic capacitor.
  • the third input sub-circuit 190 may include a second switching transistor M2 and a third switching transistor M3.
  • the first electrode of the second switching transistor M2 is electrically connected to the gate of the third switching transistor M3.
  • the first electrode of the second switch transistor M2 is configured to receive the third input signal CLKA.
  • the second electrode of the second switching transistor M2 is electrically connected to the first electrode of the third switching transistor M3.
  • the gate of the second switching transistor M2 is electrically connected to the second node H.
  • FIG. 2 also shows the parasitic capacitor C p of the second switching transistor M2.
  • a first end of the parasitic capacitor C p is electrically connected to the gate of the second switching transistor M2, a second end of the parasitic capacitor C p is electrically connected to the first electrode of the second switching transistor M2.
  • the second electrode of the third switching transistor M3 is electrically connected to the first node Q.
  • the second switch transistor M2 may be an NMOS transistor or a PMOS transistor
  • the third switch transistor M3 may be an NMOS transistor or a PMOS transistor.
  • the first reset sub-circuit 140 may include a fourth switch transistor M4.
  • the first electrode of the fourth switch transistor M4 is electrically connected to the first node Q.
  • the second electrode of the fourth switch transistor M4 is electrically connected to the first voltage terminal 101.
  • the gate of the fourth switch transistor M4 is configured to receive the first reset signal V RE .
  • the fourth switch transistor M4 may be an NMOS transistor or a PMOS transistor.
  • the first output sub-circuit 130 may include an eleventh switching transistor M11 and a second capacitor C2.
  • the first electrode of the eleventh switch transistor M11 is configured to receive the first clock signal CLKE.
  • the second electrode of the eleventh switch transistor M11 serves as the output terminal of the first output sub-circuit 130.
  • the gate of the eleventh switching transistor M11 is electrically connected to the first node Q.
  • the first terminal of the second capacitor C2 is electrically connected to the gate of the eleventh switching transistor M11.
  • the second terminal of the second capacitor C2 is electrically connected to the second electrode of the eleventh switch transistor M11.
  • the eleventh switch transistor M11 may be an NMOS transistor or a PMOS transistor.
  • the second capacitor C2 may be an external capacitor or a parasitic capacitor of the eleventh switching transistor M11.
  • the first input sub-circuit 110 may include a thirteenth switching transistor M13.
  • the first electrode of the thirteenth switch transistor M13 is electrically connected to the fourth voltage terminal 104 for providing the second level.
  • the second electrode of the thirteenth switching transistor M13 is electrically connected to the first node Q.
  • the gate of the thirteenth switching transistor M13 is configured to receive the first input signal V IN .
  • the thirteenth switch transistor M13 may be an NMOS transistor or a PMOS transistor.
  • FIG. 3A is a structural diagram showing a shift register unit according to another embodiment of the present disclosure.
  • FIG. 3B is a circuit structure diagram showing a shift register unit according to another embodiment of the present disclosure.
  • the shift register unit may include a first input sub-circuit 110, a first output sub-circuit 130, a first reset sub-circuit 140, a second input sub-circuit 120, and a third input sub-circuit 190.
  • the shift register unit may further include a second reset sub-circuit 150.
  • the second reset sub-circuit 150 may be configured to reset the potential of the first node Q and the potential of the second node H under the control of the second reset signal TRST.
  • the second reset sub-circuit can realize the simultaneous reset of the shift register unit of the full screen.
  • the second reset sub-circuit 150 may include a fifth switch transistor M5.
  • the first electrode of the fifth switch transistor M5 is electrically connected to the first node Q.
  • the second electrode of the fifth switch transistor M5 is electrically connected to the first voltage terminal 101.
  • the gate of the fifth switch transistor M5 is configured to receive the second reset signal TRST.
  • the fifth switch transistor M5 may be an NMOS transistor or a PMOS transistor.
  • the shift register unit may further include a second output sub-circuit 160.
  • the second output sub-circuit 160 may be configured to output the carry control signal CR under the control of the second clock signal CLKD in the first stage.
  • the carry control signal CR can be output to other shift register units.
  • the carry control signal CR can be used as the first input signal V IN of a certain row of shift register units or as the first reset signal V RE of another row of shift register units.
  • the second output sub-circuit 160 may include a twelfth switching transistor M12.
  • the first electrode of the twelfth switch transistor M12 is configured to receive the second clock signal CLKD.
  • the second electrode of the twelfth switch transistor M12 serves as the output terminal of the second output sub-circuit 160.
  • the gate of the twelfth switching transistor M12 is electrically connected to the first node Q.
  • the twelfth switch transistor M12 may be an NMOS transistor or a PMOS transistor.
  • FIG. 4 is a timing diagram showing a control signal for a shift register unit according to an embodiment of the present disclosure.
  • the working process of the shift register unit according to some embodiments of the present disclosure will be described in detail below in conjunction with FIG. 3A, FIG. 3B and FIG. 4.
  • each switch transistor in the shift register unit is an NMOS transistor
  • the first level is a low level
  • the second level is a high level.
  • the first stage is a display (Display) stage of one frame
  • the second stage is a field blanking (Blank) stage of one frame.
  • FIG. 1 display (Display) stage of one frame
  • the second stage is a field blanking (Blank) stage of one frame.
  • the first stage (for example, the display stage) may include the first period (that is, the t 1 period) to the fourth period (that is, the t 4 period), and the second stage (for example, the vertical blanking stage) may include fifth period (i.e. the period t 5) to the ninth time (i.e., time t 9).
  • the first input signal V IN and the second input signal OE are at a high level, and the first reset signal V RE , the second reset signal TRST, and the first clock
  • the signal CLKE, the second clock signal CLKD, and the third input signal CLKA are all low level.
  • the thirteenth switching transistor M13 is turned on, and the first node Q is pulled up to the second level.
  • the first switching transistor M1 is turned on, and the second node H also becomes the second level.
  • the first output sub-circuit 130 outputs a low-level gate drive signal OUT ⁇ i>
  • the second output sub-circuit 160 outputs a low-level carry control signal CR ⁇ i>.
  • OUT ⁇ i> represents the gate drive signal output by the i-th shift register unit (as the current shift register unit)
  • CR ⁇ i> represents the output of the i-th shift register unit (as the current shift register unit)
  • the carry control signal, i is a positive integer.
  • a low-level gate drive signal serves as an invalid gate drive signal
  • a low-level carry control signal serves as an invalid carry control signal.
  • the first clock signal CLKE and the second clock signal CLKD become high, and the first input signal V IN , the second input signal OE, The first reset signal V RE , the second reset signal TRST and the third input signal CLKA are all low level.
  • the first output sub-circuit 130 outputs a high-level gate drive signal OUT ⁇ i>
  • the second output sub-circuit 160 outputs a high-level carry control signal CR ⁇ i>.
  • a high-level gate drive signal is used as an effective gate drive signal
  • a high-level carry control signal is used as an effective carry control signal.
  • the first clock signal CLKE and the second clock signal CLKD both become low level, the potential of the first node Q decreases, and the first output sub
  • the circuit 130 outputs a low-level gate drive signal OUT ⁇ i>, and the second output sub-circuit 160 outputs a low-level carry control signal CR ⁇ i>.
  • the first reset signal V RE changes to a high level
  • the second input signal OE, the second reset signal TRST and the third input signal CLKA are all low level.
  • the fourth switch transistor M4 is turned on, and the potential of the first node Q becomes a low level (ie, the first level), thereby realizing the potential of the first node Q to be reset.
  • the shift register unit achieves the purpose of outputting the gate driving signal in the first stage (for example, the display stage).
  • the potential of the second node H remains at a high level (ie, the second level) and remains until the second stage (for example, the vertical blanking stage).
  • the third input signal CLKA 4 remains at a high level, the potential of the second node high level H, the first reset signal V RE, the first The clock signal CLKE, the second clock signal CLKD, the first input signal V IN , the second input signal OE and the second reset signal TRST are all low level.
  • the second switching transistor M2 and the third switching transistor M3 are turned on, and the potential of the first node Q changes from a low level (ie, a first level) to a high level (ie, a second level).
  • the second switching transistor M2 has a parasitic capacitor C p . Through the bootstrap action of the parasitic capacitor C p , the potential of the second node H continues to be pulled high. Therefore, the potential of the second node H changes from the second level to a higher fourth level.
  • the third input signal CLKA becomes low level, and the potential of the second node H decreases, changing from the fourth level to the second level. level.
  • the first clock signal CLKE becomes a high level
  • the first reset signal V RE the second reset signal TRST, the second clock signal CLKD
  • the first input signal V IN , the second input signal OE and the third input signal CLKA are all low level.
  • the potential of the first node Q is continuously pulled up to the third level.
  • the first output sub-circuit 130 outputs a high-level compensation driving signal OUT ⁇ i>.
  • a high-level compensation drive signal is used as an effective compensation drive signal.
  • a first clock signal CLKE goes low. Accordingly, the potential of the first node Q is reduced from the third level to the second level.
  • the first output sub-circuit 130 outputs a low-level compensation driving signal OUT ⁇ i>. In this embodiment, a low-level compensation drive signal is used as an invalid compensation drive signal.
  • both the second input signal OE and the second reset signal TRST become high level.
  • the first switching transistor M1 and the fifth switching transistor M5 are turned on, so that both the first node Q and the second node H are reset to a low level (ie, a first level). In this way, the process of outputting the compensation driving signal of the shift register unit is completed.
  • the shift register unit outputs a gate drive signal in the first stage (for example, the display stage), and outputs a compensation drive signal in the second stage (for example, the vertical blanking stage).
  • the gate drive signal can be used to turn on the switch transistor (for example, the scanning transistor) of the corresponding sub-pixel circuit during the display process of the display device, and the compensation drive signal can be used to make the corresponding sub-pixel circuit compensating.
  • the corresponding switching transistor for example, the sensing transistor
  • the gate driving signal and the compensation driving signal may have different periods and different pulse widths, respectively.
  • the pulse width relationship of the first clock signal CLKE, the second clock signal CLKD, the third input signal CLKA, and the second reset signal TRST can be adjusted.
  • the second input signal OE may be a random signal generated by an external circuit (for example, FPGA (Field Programmable Gate Array), etc.); since the second input signal OE is a random signal, Through the second input signal OE, random sensing of the sub-pixel unit rows in the display panel (as described later) can be realized, so that subsequent compensation operations are performed according to the sensing result.
  • FIG. 5A is a structural diagram showing a shift register unit according to another embodiment of the present disclosure.
  • FIG. 5B is a circuit structure diagram showing a shift register unit according to another embodiment of the present disclosure.
  • the shift register unit may include a first input sub-circuit 110, a first output sub-circuit 130, a first reset sub-circuit 140, a second input sub-circuit 120, a third input sub-circuit 190, a second The reset sub-circuit 150 and the second output sub-circuit 160 are reset.
  • the shift register unit may further include a noise reduction sub-circuit 170.
  • the noise reduction sub-circuit 170 may be configured to maintain the potential of the first node Q at the first level when the potential of the first node Q is reset. This can further ensure that the first node is completely reset, which plays a role in reducing noise.
  • the noise reduction sub-circuit 170 may include a sixth switch transistor M6, a seventh switch transistor M7, and an eighth switch transistor M8.
  • both the first electrode and the gate of the sixth switch transistor M6 are electrically connected to the second voltage terminal 102 for providing the second level.
  • the second electrode of the sixth switch transistor M6 is electrically connected to the third node QB.
  • the sixth switch transistor M6 may be an NMOS transistor or a PMOS transistor.
  • the second level is a high level (for example, the power supply voltage VDD).
  • the first electrode of the seventh switching transistor M7 is electrically connected to the third node QB.
  • the second electrode of the seventh switch transistor M7 is electrically connected to the first voltage terminal 101.
  • the gate of the seventh switching transistor M7 is electrically connected to the first node Q.
  • the seventh switch transistor M7 may be an NMOS transistor or a PMOS transistor.
  • the first electrode of the eighth switch transistor M8 is electrically connected to the first node Q.
  • the second electrode of the eighth switch transistor M8 is electrically connected to the first voltage terminal 101.
  • the gate of the eighth switch transistor M8 is electrically connected to the third node QB.
  • the eighth switch transistor M8 may be an NMOS transistor or a PMOS transistor.
  • the sixth switch transistor M6, the seventh switch transistor M7, and the eighth switch transistor M8 are all NMOS transistors as an example.
  • the first node Q is reset at a certain stage or stages (for example, stage t 4 or stage t 9 ).
  • the seventh switching transistor M7 is turned off.
  • the second voltage terminal 102 outputs a high-level power supply voltage VDD, which turns on the sixth switch transistor M6, which in turn causes the third node QB to be high.
  • the eighth switching transistor M8 is turned on. Therefore, the first node Q can be sufficiently pulled down to the potential of the first voltage terminal 101, that is, the potential of the first node Q is maintained at the first level. This can ensure that the first node is completely reset, which has the effect of reducing noise.
  • the shift register unit may further include a potential holding sub-circuit 180.
  • the potential holding sub-circuit 180 may be configured to maintain the potential of the output terminal of the first output sub-circuit 130 at the fifth level and the second output sub-circuit 160 when the potential of the first node Q is reset.
  • the potential of the output terminal is maintained at the first level.
  • the fifth level is of the same type as the first level. That is, when the first level is a low level, the fifth level is also a low level; when the first level is a high level, the fifth level is also a high level.
  • the fifth level may be equal to the first level.
  • the fifth level may not be equal to the first level. For example, the fifth level is higher than the first level.
  • the potential holding sub-circuit 180 may include a ninth switching transistor M9 and a tenth switching transistor M10.
  • the first electrode of the ninth switching transistor M9 is electrically connected to the output terminal of the second output sub-circuit 160 (for example, the second electrode of the twelfth switching transistor M12).
  • the second electrode of the ninth switch transistor M9 is electrically connected to the first voltage terminal 101.
  • the gate of the ninth switch transistor M9 is electrically connected to the third node QB.
  • the ninth switch transistor M9 may be an NMOS transistor or a PMOS transistor.
  • the first electrode of the tenth switching transistor M10 is electrically connected to the output terminal of the first output sub-circuit 130 (for example, the second electrode of the eleventh switching transistor M11).
  • the second electrode of the tenth switch transistor M10 is electrically connected to the third voltage terminal 103 for providing the fifth level.
  • the gate of the tenth switching transistor M10 is electrically connected to the third node QB.
  • the tenth switch transistor M10 may be an NMOS transistor or a PMOS transistor.
  • the fifth level may be a low level VGL2 (for example, a negative level).
  • the ninth switching transistor M9 and the tenth switching transistor M10 are both NMOS transistors as an example.
  • the seventh switching transistor M7 is turned on, and the third node QB is at a low level, so that the ninth switching transistor M9 and the tenth switching transistor M10 are turned off, which does not affect the first The output sub-circuit 130 and the second output sub-circuit 160 output signals.
  • the seventh switching transistor M7 is turned off. Since the sixth switch transistor M6 is turned on, the third node QB is at a high level, so that the ninth switch transistor M9 and the tenth switch transistor M10 are turned on.
  • the output terminal of the second output sub-circuit 160 can be pulled down to the low level VGL1 (ie, the first level) of the first voltage terminal 101, and the output terminal of the first output sub-circuit 130 can be pulled down to the first voltage terminal 101.
  • the low level VGL2 that is, the fifth level of the three voltage terminal 103. This helps to maintain the potentials of the output terminals of the first output sub-circuit and the output terminals of the second output sub-circuit at a low level, thereby reducing noise.
  • a gate driving circuit is also provided.
  • the gate driving circuit may include a plurality of shift register units as described above (for example, the shift register units shown in Figure 1, Figure 2, Figure 3A, Figure 3B, Figure 5A or Figure 5B).
  • the plurality of shift register units may include N shift register units, and N is a positive integer.
  • N shift register unit into the IX bit shift register unit outputs a control signal as a first input signal i-th shift register unit, the first one to the second one of the x shift register unit
  • An input signal is a first input signal output by an external circuit.
  • x 1 +1 ⁇ i ⁇ N, i is a positive integer
  • x 1 is a positive integer.
  • the carry control signal output by the j+x 2 shift register unit is used as the first reset signal of the j shift register unit, and the Nx 2 +1 shift to the Nth shift
  • the first reset signals of the register unit are respectively the first reset signals output by the external circuit. 1 ⁇ j ⁇ Nx 2 and j is a positive integer, and x 2 is a positive integer.
  • the external circuit may be a known integrated circuit or the like.
  • the external circuit can be used to output the first input signal and the first reset signal.
  • the external circuit can output different signals at different stages.
  • FIG. 6 is a structural diagram showing a gate driving circuit according to an embodiment of the present disclosure.
  • Fig. 6 shows a case where 8 shift register units (A1 to A8) are a unit group.
  • FIG. 6 shows a start signal STU, a second input signal OE, a third input signal CLKA, a second reset signal TRST, eight first clock signals CLKE_1 to CLKE_8, and eight second clock signals CLKD_1 to CLKD_8.
  • the first clock signal repeats every eight
  • the second clock signal repeats every eight.
  • the carry control signal CR ⁇ i-2> output by the i-2th shift register unit is used as the first input signal of the i-th shift register unit.
  • the carry control signal CR ⁇ 1> output by the first shift register unit A1 is used as the first input signal V IN_3 of the third shift register unit A3, and the second shift register unit A2
  • the output carry control signal CR ⁇ 2> serves as the first input signal V IN_4 of the fourth shift register unit A4, and so on.
  • the first input signals of the first shift register unit A1 and the second shift register unit A2 are the start signal STU output by an external circuit (not shown in FIG. 6).
  • the carry control signal CR ⁇ j+3> output by the j+3th shift register unit is used as the first reset signal of the jth shift register unit.
  • the carry control signal CR ⁇ 4> output by the fourth shift register unit A4 serves as the first reset signal V RE_1 of the first shift register unit A1
  • the fifth shift register unit A5 The output carry control signal CR ⁇ 5> serves as the first reset signal V RE_2 of the second shift register unit A2, and so on.
  • the first reset signals of the N-2th, N-1th, and Nth shift register units are respectively first reset signals output by an external circuit (not shown in FIG. 6).
  • the gate driving circuit By controlling the operation of each shift register unit in the gate driving circuit, the gate driving circuit can output the gate driving signal in the first stage (for example, the display stage) and in the second stage (for example, the vertical blanking stage). ) The function of outputting compensation drive signal.
  • FIG. 6 shows a case where 8 shift register units are a unit group
  • the scope of the embodiments of the present disclosure is not limited to this.
  • another number of shift register units for example, 4 or more may also be a unit group.
  • FIG. 7 is a timing diagram showing a control signal for a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 7 exemplarily shows that the fourth shift register unit A4 in the gate driving circuit outputs the gate driving signal in the first stage (for example, the display stage) and in the second stage (for example, the vertical blanking stage) ) The working process of outputting compensation driving signal.
  • the carry control signal CR ⁇ 2> output by the second shift register unit A2 serves as the first input signal V IN_4 of the fourth shift register unit A4, and the seventh shift register unit A7 outputs
  • the carry control signal CR ⁇ 7> is used as the first reset signal V RE_4 of the fourth shift register unit A4.
  • FIG. 8 is a flowchart showing a control method for a shift register unit according to an embodiment of the present disclosure. As shown in Fig. 8, the control method may include steps S802 to S810.
  • step S802 in the first stage, under the control of the first input signal, the first input sub-circuit changes the potential of the first node from the first level to the second level, and the second input sub-circuit is at the second input Under the control of the signal, the potential of the second node is changed from the first level to the second level, and the second level of the second node is maintained to the second stage after the first stage.
  • step S804 the first output sub-circuit changes the potential of the first node from the second level to the third level under the control of the first clock signal to output the gate drive signal.
  • the second level is between the first level and the third level.
  • step S806 the first reset sub-circuit resets the potential of the first node to the first level under the control of the first reset signal.
  • step S808 in the second stage, under the control of the third input signal, the third input sub-circuit changes the reset potential of the first node from the first level to the second level.
  • step S810 the first output sub-circuit changes the potential of the first node from the second level to the third level under the control of the first clock signal to output the compensation driving signal.
  • the control method for the shift register unit can output the gate driving signal in the first stage (for example, the display stage), and output the compensation driving signal in the second stage (for example, the vertical blanking stage). Therefore, the control method can enable the shift register unit to realize the function of outputting different signals at different stages without affecting the normal display of the display device.
  • control method may further include: under the control of the third input signal, the third input sub-circuit changes the potential of the second node from the second level to the fourth level.
  • the second level is between the first level and the fourth level.
  • control method may further include: after the first output sub-circuit outputs the compensation driving signal, the second reset sub-circuit under the control of the second reset signal, compare the potential of the first node with the second node The potential is reset.
  • a display device may include the gate driving circuit as described above.
  • the display device can be any product or component with a display function, such as a display panel, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and so on.
  • FIG. 9 is a structural diagram showing a display device according to an embodiment of the present disclosure.
  • the display device 1 includes a gate driving circuit 10 (for example, the gate driving circuit shown in FIG. 6).
  • the display device 1 further includes a display panel 20.
  • the display panel 20 includes a pixel array composed of a plurality of sub-pixel units P; for example, each sub-pixel unit P includes a pixel circuit and a light-emitting element.
  • the pixel circuit is, for example, a 3T1C pixel circuit, including a driver Transistors, scanning transistors, sensing transistors and storage capacitors.
  • the display device 1 may further include a data driving circuit 30.
  • the data drive circuit 30 is used to provide data signals to the sub-pixel units P in the pixel array; the gate drive circuit 10 is used to provide gate drive signals to the sub-pixel units P in the pixel array in the first stage (for example, the display stage), And in the second stage (for example, the vertical blanking stage), a compensation driving signal is provided to the sub-pixel units P of the pixel array.
  • the gate driving signal may drive the scanning transistor in the pixel circuit in the sub-pixel unit P
  • the compensation driving signal may drive the sensing transistor in the pixel circuit in the sub-driving pixel unit P.
  • the data driving circuit 30 is electrically connected to the sub-pixel unit P through the data line DL
  • the gate driving circuit 10 is electrically connected to the sub-pixel unit P through the gate line GL.

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Abstract

本公开提供了一种移位寄存器单元、栅极驱动电路、显示装置和控制方法。移位寄存器单元包括第一输入子电路、第一输出子电路、第一复位子电路、第二输入子电路和第三输入子电路。第一输入子电路用于在第一阶段将第一节点的电位由第一电平变为第二电平。第一输出子电路用于在第一阶段输出栅极驱动信号并在第二阶段输出补偿驱动信号。第一复位子电路用于将第一节点的电位复位为第一电平。第二输入子电路用于在第一阶段将第二节点的电位由第一电平变为第二电平，并将第二电平保持到第二阶段。第三输入子电路用于在第二阶段将复位后的第一节点的电位由第一电平变为第二电平。

Description

移位寄存器单元、栅极驱动电路、显示装置和控制方法
相关申请的交叉引用
本申请要求于2019年6月25日递交的中国专利申请第201910554376.X号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，特别涉及一种移位寄存器单元、栅极驱动电路、显示装置和控制方法。
背景技术
在显示技术(例如，OLED(Organic Light Emitting Diode，有机发光二极管)显示技术)中，栅极驱动电路可以用于替代栅极集成电路，从而可以减少成本。另外，在显示技术中，还可能需要对子像素发光进行补偿。
发明内容
根据本公开实施例的一个方面，提供了一种移位寄存器单元，包括：第一输入子电路，被配置为在第一阶段，在第一输入信号的控制下，将第一节点的电位由第一电平变为第二电平；第一输出子电路，与所述第一节点电连接，被配置为在第一阶段，在第一时钟信号的控制下输出栅极驱动信号，以及在所述第一阶段之后的第二阶段，在所述第一时钟信号的控制下输出补偿驱动信号；第一复位子电路，电连接在所述第一节点和用于提供所述第一电平的第一电压端之间，被配置为在第一复位信号的控制下，将所述第一节点的电位复位为所述第一电平；第二输入子电路，电连接在所述第一节点和所述第一电压端之间，被配置为在所述第一阶段，在第二输入信号的控制下，将第二节点的电位由第一电平变为第二电平，并将所述第二电平保持到所述第二阶段；以及第三输入子电路，与所述第二节点电连接，被配置为在所述第二阶段，在第三输入信号的控制下，将复位后的所述第一节点的电位由所述第一电平变为所述第二电平。
在一些实施例中，所述第一输出子电路被配置为在所述第一阶段，在所述第一时钟信号的控制下将所述第一节点的电位由所述第二电平变为第三电平以输出所述栅极驱动信号，以及在所述第二阶段，在所述第一时钟信号的控制下将所述第一节点的电位由所述第二电平变为所述第三电平以输出所述补偿驱动信号；其中，所述第二电平在所述第一电平与所述第三电平之间；所述第三输入子电路还被配置为在所述第三输入信号的控制下，将所述第二节点的电位由所述第二电平变为第四电平；其中，所述第二电平在所述第一电平与所述第四电平之间。
在一些实施例中，所述第二输入子电路包括第一开关晶体管和第一电容器；其中，所述第一开关晶体管的第一电极电连接至所述第一节点，所述第一开关晶体管的第二电极电连接至所述第二节点，所述第一开关晶体管的栅极被配置为接收所述第二输入信号；所述第一电容器的第一端电连接至所述第二节点，所述第一电容器的第二端电连接至所述第一电压端。
在一些实施例中，所述第三输入子电路包括第二开关晶体管和第三开关晶体管；其中，所述第二开关晶体管的第一电极电连接至所述第三开关晶体管的栅极，并且所述第二开关晶体管的第一电极被配置为接收所述第三输入信号，所述第二开关晶体管的第二电极电连接至所述第三开关晶体管的第一电极，所述第二开关晶体管的栅极电连接至所述第二节点；所述第三开关晶体管的第二电极电连接至所述第一节点。
在一些实施例中，所述第一复位子电路包括第四开关晶体管，其中，所述第四开关晶体管的第一电极电连接至所述第一节点，所述第四开关晶体管的第二电极电连接至所述第一电压端，所述第四开关晶体管的栅极被配置为接收所述第一复位信号。
在一些实施例中，所述移位寄存器单元还包括：第二复位子电路，被配置为在第二复位信号的控制下，将所述第一节点的电位和所述第二节点的电位复位。
在一些实施例中，所述第二复位子电路包括第五开关晶体管，其中，所述第五开关晶体管的第一电极电连接至所述第一节点，所述第五开关晶体管的第二电极电连接至所述第一电压端，所述第五开关晶体管的栅极被配置为接收所述第二复位信号。
在一些实施例中，所述移位寄存器单元还包括：第二输出子电路，被配置为在所述第一阶段，在第二时钟信号的控制下输出进位控制信号。
在一些实施例中，所述移位寄存器单元还包括：降噪子电路，被配置为在所述第一节点的电位被复位的情况下，将所述第一节点的电位保持为所述第一电平；以及电位保持子电路，被配置为在所述第一节点的电位被复位的情况下，将所述第一输出子电路的输出端的电位保持为第五电平，以及将所述第二输出子电路的输出端的电位保持为所述第一电平。
在一些实施例中，所述降噪子电路包括第六开关晶体管、第七开关晶体管和第八开关晶体管；其中，所述第六开关晶体管的第一电极和栅极均电连接至用于提供所述第二电平的第二电压端，所述第六开关晶体管的第二电极电连接至第三节点；所述第七开关晶体管的第一电极电连接至所述第三节点，所述第七开关晶体管的第二电极电连接至所述第一电压端，所述第七开关晶体管的栅极电连接至所述第一节点；所述第八开关晶体管的第一电极电连接至所述第一节点，所述第八开关晶体管的第二电极电连接至所述第一电压端，所述第八开关晶体管的栅极 电连接至所述第三节点。
在一些实施例中，所述电位保持子电路包括第九开关晶体管和第十开关晶体管；其中，所述第九开关晶体管的第一电极电连接至所述第二输出子电路的输出端，所述第九开关晶体管的第二电极电连接至所述第一电压端，所述第九开关晶体管的栅极电连接至所述第三节点；所述第十开关晶体管的第一电极电连接至所述第一输出子电路的输出端，所述第十开关晶体管的第二电极电连接至用于提供所述第五电平的第三电压端，所述第十开关晶体管的栅极电连接至所述第三节点。
在一些实施例中，所述第一输出子电路包括第十一开关晶体管和第二电容器；其中，所述第十一开关晶体管的第一电极被配置为接收所述第一时钟信号，所述第十一开关晶体管的第二电极作为所述第一输出子电路的输出端，所述第十一开关晶体管的栅极电连接至所述第一节点；所述第二电容器的第一端电连接至所述第十一开关晶体管的栅极，所述第二电容器的第二端电连接至所述第十一开关晶体管的第二电极。
在一些实施例中，所述第二输出子电路包括第十二开关晶体管；其中，所述第十二开关晶体管的第一电极被配置为接收所述第二时钟信号，所述第十二开关晶体管的第二电极作为所述第二输出子电路的输出端，所述第十二开关晶体管的栅极电连接至所述第一节点。
在一些实施例中，所述第一输入子电路包括第十三开关晶体管；其中，所述第十三开关晶体管的第一电极电连接至用于提供所述第二电平的第四电压端，所述第十三开关晶体管的第二电极电连接至所述第一节点，所述第十三开关晶体管的栅极被配置为接收所述第一输入信号。
在一些实施例中，所述的移位寄存器单元还包括第二复位子电路、第二输出子电路、降噪子电路和电位保持子电路；所述第二输入子电路包括第一开关晶体管和第一电容器；其中，所述第一开关晶体管的第一电极电连接至所述第一节点，所述第一开关晶体管的第二电极电连接至所述第二节点，所述第一开关晶体管的栅极被配置为接收所述第二输入信号；所述第一电容器的第一端电连接至所述第二节点，所述第一电容器的第二端电连接至所述第一电压端；所述第三输入子电路包括第二开关晶体管和第三开关晶体管；其中，所述第二开关晶体管的第一电极电连接至所述第三开关晶体管的栅极，并且所述第二开关晶体管的第一电极被配置为接收所述第三输入信号，所述第二开关晶体管的第二电极电连接至所述第三开关晶体管的第一电极，所述第二开关晶体管的栅极电连接至所述第二节点；所述第三开关晶体管的第二电极电连接至所述第一节点；所述第一复位子电路包括第四开关晶体管；其中，所述第四开关晶体管的第一电极电连接至所述第一节点，所述第四开关晶体管的第二电极电连接至所述第一电压端，所述第四开关晶体管的栅极被配置为接收所述第一复位信号；所述第二复位子电路包括第五开关 晶体管；其中，所述第五开关晶体管的第一电极电连接至所述第一节点，所述第五开关晶体管的第二电极电连接至所述第一电压端，所述第五开关晶体管的栅极被配置为接收第二复位信号；所述降噪子电路包括第六开关晶体管、第七开关晶体管和第八开关晶体管；其中，所述第六开关晶体管的第一电极和栅极均电连接至用于提供所述第二电平的第二电压端，所述第六开关晶体管的第二电极电连接至第三节点；所述第七开关晶体管的第一电极电连接至所述第三节点，所述第七开关晶体管的第二电极电连接至所述第一电压端，所述第七开关晶体管的栅极电连接至所述第一节点；所述第八开关晶体管的第一电极电连接至所述第一节点，所述第八开关晶体管的第二电极电连接至所述第一电压端，所述第八开关晶体管的栅极电连接至所述第三节点；所述电位保持子电路包括第九开关晶体管和第十开关晶体管；其中，所述第九开关晶体管的第一电极电连接至所述第二输出子电路的输出端，所述第九开关晶体管的第二电极电连接至所述第一电压端，所述第九开关晶体管的栅极电连接至所述第三节点；所述第十开关晶体管的第一电极电连接至所述第一输出子电路的输出端，所述第十开关晶体管的第二电极电连接至用于提供所述第五电平的第三电压端，所述第十开关晶体管的栅极电连接至所述第三节点；所述第一输出子电路包括第十一开关晶体管和第二电容器；其中，所述第十一开关晶体管的第一电极被配置为接收所述第一时钟信号，所述第十一开关晶体管的第二电极作为所述第一输出子电路的输出端，所述第十一开关晶体管的栅极电连接至所述第一节点；所述第二电容器的第一端电连接至所述第十一开关晶体管的栅极，所述第二电容器的第二端电连接至所述第十一开关晶体管的第二电极；所述第二输出子电路包括第十二开关晶体管；其中，所述第十二开关晶体管的第一电极被配置为接收第二时钟信号，所述第十二开关晶体管的第二电极作为所述第二输出子电路的输出端，所述第十二开关晶体管的栅极电连接至所述第一节点；所述第一输入子电路包括第十三开关晶体管；其中，所述第十三开关晶体管的第一电极电连接至用于提供所述第二电平的第四电压端，所述第十三开关晶体管的第二电极电连接至所述第一节点，所述第十三开关晶体管的栅极被配置为接收所述第一输入信号。
根据本公开实施例的另一个方面，提供了一种栅极驱动电路，包括：多个如前所述的移位寄存器单元。
在一些实施例中，所述多个移位寄存器单元包括N个移位寄存器单元，N为正整数；在所述N个移位寄存器单元中，第i-x1个移位寄存器单元输出的进位控制信号作为第i个移位寄存器单元的第一输入信号，第1个至第x1个移位寄存器单元的第一输入信号分别为由外部电路输出的第一输入信号，其中，x1+1≤i≤N且i为正整数，x1为正整数；在所述N个移位寄存器单元中，第j+x2个移位寄存器单元输出的进位控制信号作为第j个移位寄存器单元的第一复位信号，第N-x2+1 个至第N个移位寄存器单元的第一复位信号分别为由所述外部电路输出的第一复位信号，其中，1≤j≤N-x2且j为正整数，x2为正整数。
根据本公开实施例的另一个方面，提供了一种显示装置，包括：如前所述的栅极驱动电路。
根据本公开实施例的另一个方面，提供了一种用于移位寄存器单元的控制方法，包括：在第一阶段，第一输入子电路在第一输入信号的控制下，将第一节点的电位由第一电平变为第二电平，第二输入子电路在第二输入信号的控制下，将第二节点的电位由第一电平变为第二电平，并将所述第二节点的第二电平保持到在所述第一阶段之后的第二阶段；第一输出子电路在第一时钟信号的控制下将所述第一节点的电位由所述第二电平变为第三电平以输出栅极驱动信号，其中，所述第二电平在所述第一电平与所述第三电平之间；第一复位子电路在第一复位信号的控制下，将所述第一节点的电位复位为所述第一电平；在所述第二阶段，第三输入子电路在第三输入信号的控制下，将复位后的所述第一节点的电位由所述第一电平变为所述第二电平；以及所述第一输出子电路在所述第一时钟信号的控制下将所述第一节点的电位由所述第二电平变为所述第三电平以输出补偿驱动信号。
通过以下参照附图对本公开的示例性实施例的详细描述，本公开的其它特征及其优点将会变得清楚。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1是示出根据本公开一个实施例的移位寄存器单元的结构图；
图2是示出根据本公开一个实施例的移位寄存器单元的电路结构图；
图3A是示出根据本公开另一个实施例的移位寄存器单元的结构图；
图3B是示出根据本公开另一个实施例的移位寄存器单元的电路结构图；
图4是示出根据本公开一个实施例的用于移位寄存器单元的控制信号的时序图；
图5A是示出根据本公开另一个实施例的移位寄存器单元的结构图；
图5B是示出根据本公开另一个实施例的移位寄存器单元的电路结构图；
图6是示出根据本公开一个实施例的栅极驱动电路的结构图；
图7是示出根据本公开一个实施例的用于栅极驱动电路的控制信号的时序图；
图8是示出根据本公开一个实施例的用于移位寄存器单元的控制方法的流程图；
图9是示出根据本公开一个实施例的显示装置的结构图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本公开中，当描述到特定器件位于第一器件和第二器件之间时，在该特定器件与第一器件或第二器件之间可以存在居间器件，也可以不存在居间器件。当描述到特定器件电连接其它器件时，该特定器件可以与所述其它器件直接电连接而不具有居间器件，也可以不与所述其它器件直接电连接而具有居间器件。
本公开使用的所有术语(包括技术术语或者科学术语)与本公开所属领域的普通技术人员理解的含义相同，除非另外特别定义。还应当理解，在诸如通用字典中定义的术语应当被解释为具有与它们在相关技术的上下文中的含义相一致的含义，而不应用理想化或极度形式化的意义来解释，除非这里明确地这样定义。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为说明书的一部分。
OLED显示面板包括像素阵列，像素阵列包括多行多列的子像素单元。每个子像素单元包括像素电路和发光元件，像素电路接收各种信号以驱动发光元件发光；像素电路可以包括驱动晶体管、扫描晶体管和存储电容等。各个像素电路中 的驱动晶体管的阈值电压由于制备工艺可能存在差异，而且由于例如温度变化的影响，驱动晶体管的阈值电压可能会产生漂移现象。因此，各个驱动晶体管的阈值电压的不同可能会导致显示不良(例如，显示不均匀)，所以就需要对阈值电压进行补偿。在对OLED显示面板中的子像素单元进行补偿时，除了在子像素单元中设置像素补偿电路进行内部补偿外，还可以通过设置感测晶体管进行外部补偿。对于外部补偿的情形，像素电路例如可以为在传统的2T1C(驱动晶体管、扫描晶体管和存储电容)像素电路的基础上再引入感测晶体管，由此获得3T1C(驱动晶体管、扫描晶体管、感测晶体管和存储电容)像素电路。例如，驱动晶体管可以为N型晶体管，感测晶体管的第一极可以连接到驱动晶体管的源极，感测晶体管的第二极可以经由感测线与感测电路连接，感测晶体管的栅极被配置为经由栅线接收补偿驱动信号(例如，感测晶体管的栅极与扫描晶体管的栅极可以连接到同一栅线)。在进行外部补偿时，由移位寄存器单元构成的栅极驱动电路需要向显示面板中的子像素单元分别提供用于扫描晶体管和感测晶体管的驱动信号，例如，在一帧的显示阶段提供用于扫描晶体管的扫描驱动信号，在一帧的场消隐阶段提供用于感测晶体管的补偿驱动信号。例如，这两种驱动信号可以分别是具有不同周期和不同脉宽的波形。
本公开的发明人发现，栅极驱动电路输出用于显示的栅极驱动信号和用于子像素补偿的补偿驱动信号是比较困难的。
鉴于此，本公开的实施例提供了一种用于栅极驱动电路的移位寄存器单元，以便分别输出栅极驱动信号和补偿驱动信号。下面结合附图详细描述根据本公开一些实施例的移位寄存器单元。
图1是示出根据本公开一个实施例的移位寄存器单元的结构图。如图1所示，该移位寄存器单元可以包括第一输入子电路110、第一输出子电路130、第一复位子电路140、第二输入子电路120和第三输入子电路190。
第一输入子电路110可以被配置为在第一阶段，在第一输入信号V IN的控制下，将第一节点Q的电位由第一电平变为第二电平。
第一输出子电路130与该第一节点Q电连接。该第一输出子电路130可以被配置为在第一阶段，在第一时钟信号CLKE的控制下输出栅极驱动信号，以及在第一阶段之后的第二阶段，在该第一时钟信号CLKE的控制下输出补偿驱动信号。图1中的“OUT”表示第一输出子电路输出的信号。
第一复位子电路140电连接在第一节点Q和第一电压端101之间。该第一电压端101用于提供第一电平。该第一复位子电路140可以被配置为在第一复位信号V RE的控制下，将第一节点Q的电位复位。例如，该第一复位子电路可以实现对当前行的移位寄存器单元的第一节点的电位进行复位，将第一节点的电位复位为第一电平。
第二输入子电路120电连接在第一节点Q和第一电压端101之间。该第一电压端101用于提供第一电平。该第二输入子电路120可以被配置为在第一阶段，在第二输入信号OE的控制下，将第二节点H的电位由第一电平变为第二电平，并将该第二电平保持到第二阶段。
第三输入子电路190与第二节点H电连接。该第三输入子电路190被配置为在该第二阶段，在第三输入信号CLKA的控制下，将复位后的第一节点Q的电位由第一电平变为第二电平。
例如，在本实施例中，第一阶段可以是一帧的显示阶段，第二阶段可以是一帧的场消隐阶段。需要说明的是，后续的实施例中的第一阶段和第二阶段的含义可以与本实施例中的第一阶段和第二阶段的含义相同。
至此，提供了根据本公开一些实施例的移位寄存器单元。该移位寄存器单元包括第一输入子电路、第一输出子电路、第一复位子电路、第二输入子电路和第三输入子电路。第一输入子电路在第一阶段在第一输入信号的控制下将第一节点的电位由第一电平变为第二电平。第一输出子电路在第一阶段在第一时钟信号的控制下输出栅极驱动信号，以及在第二阶段在第一时钟信号的控制下输出补偿驱动信号。第一复位子电路在第一复位信号的控制下将第一节点的电位复位。第二输入子电路在第一阶段在第二输入信号的控制下将第二节点的电位由第一电平变为第二电平，并将该第二电平保持到第二阶段。第三输入子电路在该第二阶段在第三输入信号的控制下将复位后的第一节点的电位由第一电平变为第二电平。在该实施例中，移位寄存器单元实现了在第一阶段(例如，显示阶段)输出栅极驱动信号并在第二阶段(例如，场消隐阶段)输出补偿驱动信号的目的。
需要说明的是，栅极驱动信号可以用于在显示装置的显示过程，通过相应的栅极线输出；补偿驱动信号也通过相应的栅极线输出，作为在子像素补偿过程中所需要的栅极信号。关于该子像素补偿的方法或过程可以采用已知的技术，这里不再详细描述。
在一些实施例中，第一输出子电路130可以被配置为在第一阶段，在第一时钟信号CLKE的控制下将第一节点Q的电位由第二电平变为第三电平以输出栅极驱动信号，以及在第二阶段，在第一时钟信号CLKE的控制下将该第一节点Q的电位由第二电平变为第三电平以输出补偿驱动信号。该第二电平在第一电平与第三电平之间。
在一些实施例中，第一电平低于第二电平，第二电平低于第三电平。例如，第一电平为低电平，第二电平为高电平，第三电平为比第二电平更高的电平。在另一些实施例中，第一电平高于第二电平，第二电平高于第三电平。例如，第一电平为高电平，第二电平为低电平，第三电平为比第二电平更低的电平。
在一些实施例中，第三输入子电路190还可以被配置为在第三输入信号CLKA 的控制下，将第二节点的电位由第二电平变为第四电平。第二电平在第一电平与第四电平之间。
在一些实施例中，第一电平低于第二电平，第二电平低于第四电平。例如，第一电平为低电平，第二电平为高电平，第四电平为比第二电平更高的电平。在另一些实施例中，第一电平高于第二电平，第二电平高于第四电平。例如，第一电平为高电平，第二电平为低电平，第四电平为比第二电平更低的电平。该第四电平可以与第三电平相等，也可以与该第三电平不相等。
图2是示出根据本公开一个实施例的移位寄存器单元的电路结构图。
在一些实施例中，如图2所示，第二输入子电路120可以包括第一开关晶体管M1和第一电容器C1。
该第一开关晶体管M1的第一电极电连接至第一节点Q。该第一开关晶体管M1的第二电极电连接至第二节点H。该第一开关晶体管M1的栅极被配置为接收第二输入信号OE。例如，第一开关晶体管M1可以为NMOS(N-channel Metal Oxide Semiconductor，N型沟道金属氧化物半导体)晶体管或PMOS(P-channel Metal Oxide Semiconductor，P型沟道金属氧化物半导体)晶体管。第一电容器C1的第一端电连接至第二节点H。该第一电容器C1的第二端电连接至第一电压端101。例如，该第一电压端可以用于提供低电平VGL1(作为第一电平)。例如，该低电平VGL1可以为负电平。例如，该第一电容器C1可以是外接电容器或寄生电容器。
在一些实施例中，如图2所示，第三输入子电路190可以包括第二开关晶体管M2和第三开关晶体管M3。
该第二开关晶体管M2的第一电极电连接至第三开关晶体管M3的栅极。该第二开关晶体管M2的第一电极被配置为接收第三输入信号CLKA。该第二开关晶体管M2的第二电极电连接至第三开关晶体管M3的第一电极。该第二开关晶体管M2的栅极电连接至第二节点H。另外，图2中还示出了第二开关晶体管M2的寄生电容器C p。该寄生电容器C p的第一端电连接至第二开关晶体管M2的栅极，该寄生电容器C p的第二端电连接至第二开关晶体管M2的第一电极。第三开关晶体管M3的第二电极电连接至第一节点Q。
例如，第二开关晶体管M2可以为NMOS晶体管或PMOS晶体管，第三开关晶体管M3可以为NMOS晶体管或PMOS晶体管。
在一些实施例中，如图2所示，第一复位子电路140可以包括第四开关晶体管M4。该第四开关晶体管M4的第一电极电连接至第一节点Q。该第四开关晶体管M4的第二电极电连接至第一电压端101。该第四开关晶体管M4的栅极被配置为接收第一复位信号V RE。例如，第四开关晶体管M4可以为NMOS晶体管或PMOS晶体管。
在一些实施例中，如图2所示，第一输出子电路130可以包括第十一开关晶 体管M11和第二电容器C2。该第十一开关晶体管M11的第一电极被配置为接收第一时钟信号CLKE。该第十一开关晶体管M11的第二电极作为第一输出子电路130的输出端。该第十一开关晶体管M11的栅极电连接至第一节点Q。第二电容器C2的第一端电连接至第十一开关晶体管M11的栅极。该第二电容器C2的第二端电连接至第十一开关晶体管M11的第二电极。例如，第十一开关晶体管M11可以为NMOS晶体管或PMOS晶体管。例如，第二电容器C2可以是外接电容器或者第十一开关晶体管M11的寄生电容器。
在一些实施例中，如图2所示，第一输入子电路110可以包括第十三开关晶体管M13。该第十三开关晶体管M13的第一电极电连接至用于提供第二电平的第四电压端104。该第十三开关晶体管M13的第二电极电连接至第一节点Q。该第十三开关晶体管M13的栅极被配置为接收第一输入信号V IN。例如，第十三开关晶体管M13可以为NMOS晶体管或PMOS晶体管。
至此，描述了根据本公开一些实施例的移位寄存器单元的上述各个子电路的具体电路结构。上述各个子电路可以分别实现相应的功能，从而可以使得移位寄存器单元实现分别输出栅极驱动信号和补偿驱动信号的目的。
图3A是示出根据本公开另一个实施例的移位寄存器单元的结构图。图3B是示出根据本公开另一个实施例的移位寄存器单元的电路结构图。如图3A所示，该移位寄存器单元可以包括第一输入子电路110、第一输出子电路130、第一复位子电路140、第二输入子电路120和第三输入子电路190。
在一些实施例中，如图3A所示，该移位寄存器单元还可以包括第二复位子电路150。该第二复位子电路150可以被配置为在第二复位信号TRST的控制下，将第一节点Q的电位和第二节点H的电位复位。例如，该第二复位子电路可以实现对全屏幕的移位寄存器单元进行同时复位。
在一些实施例中，如图3B所示，该第二复位子电路150可以包括第五开关晶体管M5。该第五开关晶体管M5的第一电极电连接至第一节点Q。该第五开关晶体管M5的第二电极电连接至第一电压端101。该第五开关晶体管M5的栅极被配置为接收第二复位信号TRST。例如，第五开关晶体管M5可以为NMOS晶体管或PMOS晶体管。
在上述实施例中，通过在移位寄存器单元中设置第二复位子电路，可以实现对全屏幕的移位寄存器单元的复位控制。
在一些实施例中，如图3A所示，该移位寄存器单元还可以包括第二输出子电路160。该第二输出子电路160可以被配置为在第一阶段，在第二时钟信号CLKD的控制下输出进位控制信号CR。该进位控制信号CR可以被输出到其他移位寄存器单元。例如，该进位控制信号CR可以作为某行移位寄存器单元的第一输入信号V IN或作为另外某行移位寄存器单元的第一复位信号V RE。
在一些实施例中，如图3B所示，第二输出子电路160可以包括第十二开关晶体管M12。该第十二开关晶体管M12的第一电极被配置为接收第二时钟信号CLKD。该第十二开关晶体管M12的第二电极作为第二输出子电路160的输出端。该第十二开关晶体管M12的栅极电连接至第一节点Q。例如，第十二开关晶体管M12可以为NMOS晶体管或PMOS晶体管。
在上述实施例中，通过在移位寄存器单元中设置第二输出子电路，可以实现不同移位寄存器单元之间的进位控制。
图4是示出根据本公开一个实施例的用于移位寄存器单元的控制信号的时序图。下面结合图3A、图3B和图4详细描述根据本公开一些实施例的移位寄存器单元的工作过程。这里，以移位寄存器单元中的各个开关晶体管为NMOS晶体管、第一电平为低电平、第二电平为高电平为例进行描述。在一帧图像的显示过程中，存在第一阶段和第二阶段。例如，第一阶段为一帧的显示(Display)阶段，第二阶段为一帧的场消隐(Blank)阶段。如图4所示，第一阶段(例如，显示阶段)可以包括第一时段(即t 1时段)至第四时段(即t 4时段)，第二阶段(例如，场消隐阶段)可以包括第五时段(即t 5时段)至第九时段(即t 9时段)。
如图4所示，在第一时段(即t 1时段)，第一输入信号V IN和第二输入信号OE为高电平，第一复位信号V RE、第二复位信号TRST、第一时钟信号CLKE、第二时钟信号CLKD和第三输入信号CLKA均为低电平。在这样的情况下，第十三开关晶体管M13导通，第一节点Q被拉高到第二电平。第一开关晶体管M1导通，第二节点H也变为第二电平。第一输出子电路130输出低电平的栅极驱动信号OUT<i>，第二输出子电路160输出低电平的进位控制信号CR<i>。这里，OUT<i>表示第i个移位寄存器单元(作为当前移位寄存器单元)输出的栅极驱动信号，CR<i>表示第i个移位寄存器单元(作为当前移位寄存器单元)输出的进位控制信号，i为正整数。在该示例中，低电平的栅极驱动信号作为无效的栅极驱动信号，低电平的进位控制信号作为无效的进位控制信号。
接下来，如图4所示，在第二时段(即t 2时段)，第一时钟信号CLKE和第二时钟信号CLKD变为高电平，第一输入信号V IN、第二输入信号OE、第一复位信号V RE、第二复位信号TRST和第三输入信号CLKA均为低电平。在这样的情况下，由于第二电容器C2的自举作用，第一节点Q的电位被继续拉高到第三电平。第一输出子电路130输出高电平的栅极驱动信号OUT<i>，第二输出子电路160输出高电平的进位控制信号CR<i>。在该示例中，高电平的栅极驱动信号作为有效的栅极驱动信号，高电平的进位控制信号作为有效的进位控制信号。
接下来，如图4所示，在第三时段(即t 3时段)，第一时钟信号CLKE和第二时钟信号CLKD均变为低电平，第一节点Q的电位降低，第一输出子电路130输出低电平的栅极驱动信号OUT<i>，第二输出子电路160输出低电平的进位控制 信号CR<i>。
接下来，如图4所示，在第四时段(即t 4时段)，第一复位信号V RE变为高电平，第一时钟信号CLKE、第二时钟信号CLKD、第一输入信号V IN、第二输入信号OE、第二复位信号TRST和第三输入信号CLKA均为低电平。在这样的情况下，第四开关晶体管M4导通，第一节点Q的电位变为低电平(即第一电平)，从而实现对第一节点Q的电位复位。
在上述过程中，移位寄存器单元实现了在第一阶段(例如，显示阶段)输出栅极驱动信号的目的。在上述过程中，第二节点H的电位保持高电平(即第二电平)并一直保持到第二阶段(例如，场消隐阶段)。
接下来，如图4所示，在第五时段(即t 5时段)，第三输入信号CLKA为高电平，第二节点H的电位保持高电平，第一复位信号V RE、第一时钟信号CLKE、第二时钟信号CLKD、第一输入信号V IN、第二输入信号OE和第二复位信号TRST均为低电平。在这样的情况下，第二开关晶体管M2和第三开关晶体管M3导通，第一节点Q的电位由低电平(即第一电平)变为高电平(即第二电平)。另外，第二开关晶体管M2具有寄生电容器C p。通过寄生电容器C p的自举作用，第二节点H的电位继续被拉高。因此，第二节点H的电位由第二电平变为更高的第四电平。
接下来，如图4所示，在第六时段(即t 6时段)，第三输入信号CLKA变为低电平，则第二节点H的电位降低，由第四电平变为第二电平。
接下来，如图4所示，在第七时段(即t 7时段)，第一时钟信号CLKE变为高电平，第一复位信号V RE、第二复位信号TRST、第二时钟信号CLKD、第一输入信号V IN、第二输入信号OE和第三输入信号CLKA均为低电平。在这样的情况下，由于第二电容器C2的自举作用，第一节点Q的电位被继续拉高到第三电平。这样，第一输出子电路130输出高电平的补偿驱动信号OUT<i>。在该示例中，高电平的补偿驱动信号作为有效的补偿驱动信号。
接下来，如图4所示，在第八时段(即t 8时段)，第一时钟信号CLKE变为低电平。相应地，第一节点Q的电位由第三电平降低到第二电平。第一输出子电路130输出低电平的补偿驱动信号OUT<i>。在该实施例中，低电平的补偿驱动信号作为无效的补偿驱动信号。
接下来，如图4所示，在第九时段(即t 9时段)，第二输入信号OE和第二复位信号TRST均变为高电平。在这样的情况下，第一开关晶体管M1和第五开关晶体管M5导通，使得第一节点Q和第二节点H均被复位为低电平(即第一电平)。这样，完成了移位寄存器单元输出补偿驱动信号的过程。
至此，描述了根据本公开一些实施例的移位寄存器单元的工作过程。在该工作过程中，移位寄存器单元在第一阶段(例如，显示阶段)输出栅极驱动信号， 在第二阶段(例如，场消隐阶段)输出补偿驱动信号。栅极驱动信号可以用于在显示装置的显示过程中使相应的子像素电路的开关晶体管(例如，扫描晶体管)导通，补偿驱动信号可以用于在对相应的子像素电路进行补偿过程中使相应的开关晶体管(例如，感测晶体管)导通。因此，该移位寄存器单元可以在不影响显示装置正常显示的情况下实现在不同阶段输出不同信号的功能。该栅极驱动信号和该补偿驱动信号可以分别具有不同的周期和不同的脉宽。
在一些实施例中，第一时钟信号CLKE、第二时钟信号CLKD、第三输入信号CLKA和第二复位信号TRST的脉宽关系是可以调节的。在一些实施例中，第二输入信号OE可以是由外部电路(例如，FPGA(Field Programmable Gate Array，现场可编程门阵列)等)产生的随机信号；由于第二输入信号OE是随机信号，因此通过该第二输入信号OE可以实现对于显示面板(如后所描述的)中子像素单元行的随机感测，由此后续根据感测结果进行补偿操作。
图5A是示出根据本公开另一个实施例的移位寄存器单元的结构图。图5B是示出根据本公开另一个实施例的移位寄存器单元的电路结构图。如图5A所示，该移位寄存器单元可以包括第一输入子电路110、第一输出子电路130、第一复位子电路140、第二输入子电路120、第三输入子电路190、第二复位子电路150和第二输出子电路160。
在一些实施例中，如图5A所示，该移位寄存器单元还可以包括降噪子电路170。该降噪子电路170可以被配置为在第一节点Q的电位被复位的情况下，将该第一节点Q的电位保持为第一电平。这样可以进一步保证该第一节点被完全复位，起到降低噪声的作用。
在一些实施例中，如图5B所示，降噪子电路170可以包括第六开关晶体管M6、第七开关晶体管M7和第八开关晶体管M8。
如图5B所示，该第六开关晶体管M6的第一电极和栅极均电连接至用于提供第二电平的第二电压端102。该第六开关晶体管M6的第二电极电连接至第三节点QB。例如，该第六开关晶体管M6可以为NMOS晶体管或PMOS晶体管。例如，该第二电平为高电平(例如电源电压VDD)。第七开关晶体管M7的第一电极电连接至第三节点QB。该第七开关晶体管M7的第二电极电连接至第一电压端101。第七开关晶体管M7的栅极电连接至第一节点Q。例如，该第七开关晶体管M7可以为NMOS晶体管或PMOS晶体管。第八开关晶体管M8的第一电极电连接至该第一节点Q。该第八开关晶体管M8的第二电极电连接至第一电压端101。该第八开关晶体管M8的栅极电连接至第三节点QB。例如，该第八开关晶体管M8可以为NMOS晶体管或PMOS晶体管。
下面以第六开关晶体管M6、第七开关晶体管M7和第八开关晶体管M8均为NMOS晶体管为例进行描述。在前面描述的工作过程中，第一节点Q在某个或某 些阶段(例如t 4阶段或t 9阶段)被复位。在第一节点Q被复位为低电平(即第一电平)的情况下，第七开关晶体管M7截止。第二电压端102输出高电平的电源电压VDD，这使得第六开关晶体管M6导通，进而导致第三节点QB为高电平。在这样的情况下，第八开关晶体管M8导通。因此，第一节点Q能够被充分地拉低到第一电压端101的电位，即第一节点Q的电位保持为第一电平。这样可以保证该第一节点被完全复位，起到降低噪声的作用。
在一些实施例中，如图5A所示，该移位寄存器单元还可以包括电位保持子电路180。该电位保持子电路180可以被配置为在第一节点Q的电位被复位的情况下，将第一输出子电路130的输出端的电位保持为第五电平，以及将第二输出子电路160的输出端的电位保持为第一电平。该第五电平与第一电平属于同类型的电平。即，在第一电平为低电平的情况下，第五电平也为低电平；在第一电平为高电平的情况下，第五电平也为高电平。在一些实施例中，第五电平可以与第一电平相等。在另一些实施例中，第五电平也可以与第一电平不相等。例如，第五电平高于第一电平。
在一些实施例中，如图5B所示，电位保持子电路180可以包括第九开关晶体管M9和第十开关晶体管M10。该第九开关晶体管M9的第一电极电连接至第二输出子电路160的输出端(例如，第十二开关晶体管M12的第二电极)。该第九开关晶体管M9的第二电极电连接至第一电压端101。该第九开关晶体管M9的栅极电连接至第三节点QB。例如，该第九开关晶体管M9可以为NMOS晶体管或PMOS晶体管。第十开关晶体管M10的第一电极电连接至第一输出子电路130的输出端(例如，第十一开关晶体管M11的第二电极)。该第十开关晶体管M10的第二电极电连接至用于提供第五电平的第三电压端103。该第十开关晶体管M10的栅极电连接至第三节点QB。例如，该第十开关晶体管M10可以为NMOS晶体管或PMOS晶体管。例如，第五电平可以为低电平VGL2(例如负电平)。
下面以第九开关晶体管M9和第十开关晶体管M10均为NMOS晶体管为例进行描述。在第一节点Q为高电平的情况下，第七开关晶体管M7导通，第三节点QB为低电平，从而使得第九开关晶体管M9和第十开关晶体管M10截止，这样不影响第一输出子电路130和第二输出子电路160输出信号。在第一节点Q被复位为低电平的情况下，第七开关晶体管M7截止。由于第六开关晶体管M6导通，导致第三节点QB为高电平，从而使得第九开关晶体管M9和第十开关晶体管M10导通。这样可以使得第二输出子电路160的输出端被拉低到第一电压端101的低电平VGL1(即第一电平)，以及使得第一输出子电路130的输出端被拉低到第三电压端103的低电平VGL2(即第五电平)。这样有利于维持第一输出子电路的输出端和第二输出子电路的输出端的电位为低电平，从而起到减小噪声的作用。
在本公开的一些实施例中，还提供了一种栅极驱动电路。该栅极驱动电路可 以包括多个如前所述的移位寄存器单元(例如，如图1、图2、图3A、图3B、图5A或图5B所示的移位寄存器单元)。
在一些实施例中，该多个移位寄存器单元可以包括N个移位寄存器单元，N为正整数。在N个移位寄存器单元中，第i-x 1个移位寄存器单元输出的进位控制信号作为第i个移位寄存器单元的第一输入信号，第1个至第x 1个移位寄存器单元的第一输入信号分别为由外部电路输出的第一输入信号。x 1+1≤i≤N且i为正整数，x 1为正整数。在N个移位寄存器单元中，第j+x 2个移位寄存器单元输出的进位控制信号作为第j个移位寄存器单元的第一复位信号，第N-x 2+1个至第N个移位寄存器单元的第一复位信号分别为由外部电路输出的第一复位信号。1≤j≤N-x 2且j为正整数，x 2为正整数。
需要说明的是，该外部电路可以为已知的集成电路等。该外部电路可以用于输出第一输入信号和第一复位信号。例如，该外部电路可以在不同等阶段输出不同的信号。
图6是示出根据本公开一个实施例的栅极驱动电路的结构图。图6示出了8个移位寄存器单元(A1至A8)为一个单元组的情况。图6中示出了起始信号STU、第二输入信号OE、第三输入信号CLKA、第二复位信号TRST、8个第一时钟信号CLKE_1至CLKE_8和8个第二时钟信号CLKD_1至CLKD_8。这里，在栅极驱动电路中，每8个第一时钟信号重复出现，以及每8个第二时钟信号重复出现。
下面以x 1＝2、x 2＝3为例，结合图6详细描述本公开一些实施例的栅极驱动电路。
在一些实施例中，第i-2个移位寄存器单元输出的进位控制信号CR<i-2>作为第i个移位寄存器单元的第一输入信号。例如，如图6所示，第1个移位寄存器单元A1输出的进位控制信号CR<1>作为第3个移位寄存器单元A3的第一输入信号V IN_3，第2个移位寄存器单元A2输出的进位控制信号CR<2>作为第4个移位寄存器单元A4的第一输入信号V IN_4，等等。另外，第1个移位寄存器单元A1和第2个移位寄存器单元A2的第一输入信号分别为由外部电路(图6中未示出)输出的起始信号STU。
在一些实施例中，第j+3个移位寄存器单元输出的进位控制信号CR<j+3>作为第j个移位寄存器单元的第一复位信号。例如，如图6所示，第4个移位寄存器单元A4输出的进位控制信号CR<4>作为第1个移位寄存器单元A1的第一复位信号V RE_1，第5个移位寄存器单元A5输出的进位控制信号CR<5>作为第2个移位寄存器单元A2的第一复位信号V RE_2，等等。另外，第N-2个、第N-1个和第N个移位寄存器单元的第一复位信号分别为由外部电路(图6中未示出)输出的第一复位信号。
至此，详细描述了根据本公开一些实施例的栅极驱动电路。通过控制该栅极 驱动电路中的各个移位寄存器单元的运行，可以实现栅极驱动电路在第一阶段(例如，显示阶段)输出栅极驱动信号并在第二阶段(例如，场消隐阶段)输出补偿驱动信号的功能。
需要说明的是，虽然图6中示出了8个移位寄存器单元为一个单元组的情况，但是本公开实施例的范围并不仅限于此。例如，还可以是其他数量(例如4个或更多个)的移位寄存器单元为一个单元组。
图7是示出根据本公开一个实施例的用于栅极驱动电路的控制信号的时序图。图7示例性地示出了该栅极驱动电路中的第4个移位寄存器单元A4在第一阶段(例如，显示阶段)输出栅极驱动信号并在第二阶段(例如，场消隐阶段)输出补偿驱动信号的工作过程。
在该工作过程中，第2个移位寄存器单元A2输出的进位控制信号CR<2>作为该第4个移位寄存器单元A4的第一输入信号V IN_4，第7个移位寄存器单元A7输出的进位控制信号CR<7>作为该第4个移位寄存器单元A4的第一复位信号V RE_4。关于该第4个移位寄存器单元A4的工作过程，可以参考前面结合图4所描述的移位寄存器单元的工作过程，这里不在赘述。
图8是示出根据本公开一个实施例的用于移位寄存器单元的控制方法的流程图。如图8所示，该控制方法可以包括步骤S802至S810。
在步骤S802，在第一阶段，第一输入子电路在第一输入信号的控制下，将第一节点的电位由第一电平变为第二电平，第二输入子电路在第二输入信号的控制下，将第二节点的电位由第一电平变为第二电平，并将第二节点的第二电平保持到在第一阶段之后的第二阶段。
在步骤S804，第一输出子电路在第一时钟信号的控制下将第一节点的电位由第二电平变为第三电平以输出栅极驱动信号。第二电平在第一电平与第三电平之间。
在步骤S806，第一复位子电路在第一复位信号的控制下，将第一节点的电位复位为第一电平。
在步骤S808，在第二阶段，第三输入子电路在第三输入信号的控制下，将复位后的第一节点的电位由第一电平变为第二电平。
在步骤S810，第一输出子电路在第一时钟信号的控制下将第一节点的电位由第二电平变为第三电平以输出补偿驱动信号。
至此，提供了根据本公开一些实施例的用于移位寄存器单元的控制方法。通过该控制方法，移位寄存器单元可以在第一阶段(例如，显示阶段)输出栅极驱动信号，并在第二阶段(例如，场消隐阶段)输出补偿驱动信号。因此，该控制方法可以使得移位寄存器单元在不影响显示装置正常显示的情况下实现在不同阶段输出不同信号的功能。
在一些实施例中，所述控制方法还可以包括：第三输入子电路在第三输入信号的控制下，将第二节点的电位由第二电平变为第四电平。第二电平在第一电平与第四电平之间。
在一些实施例中，所述控制方法还可以包括：在第一输出子电路输出补偿驱动信号之后，第二复位子电路在第二复位信号的控制下，将第一节点的电位和第二节点的电位复位。
在本公开的一些实施例中，还提供了一种显示装置。该显示装置可以包括如前所述的栅极驱动电路。例如，该显示装置可以为：显示面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
图9是示出根据本公开一个实施例的显示装置的结构图。如图9所示，该显示装置1包括栅极驱动电路10(例如，如图6所示的栅极驱动电路)。该显示装置1还包括显示面板20，显示面板20包括由多个子像素单元P构成的像素阵列；例如，每个子像素单元P包括像素电路和发光元件，该像素电路例如为3T1C像素电路，包括驱动晶体管、扫描晶体管、感测晶体管和存储电容。例如，该显示装置1还可以包括数据驱动电路30。数据驱动电路30用于提供数据信号给像素阵列中的子像素单元P；栅极驱动电路10用于在第一阶段(例如，显示阶段)提供栅极驱动信号给像素阵列的子像素单元P，并在第二阶段(例如，场消隐阶段)提供补偿驱动信号给像素阵列的子像素单元P。例如，栅极驱动信号可以驱动子像素单元P中的像素电路中的扫描晶体管，补偿驱动信号可以驱动子驱动像素单元P中的像素电路中的感测晶体管。数据驱动电路30通过数据线DL与子像素单元P电连接，栅极驱动电路10通过栅线GL与子像素单元P电连接。
本公开的实施例提供的显示装置的技术效果可以参考上述实施例中关于移位寄存器单元和栅极驱动电路的相应描述，这里不再赘述。
至此，已经详细描述了本公开的各实施例。为了避免模糊本公开的构思，没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (19)

  1. 一种移位寄存器单元，包括：
    第一输入子电路，被配置为在第一阶段，在第一输入信号的控制下，将第一节点的电位由第一电平变为第二电平；
    第一输出子电路，与所述第一节点电连接，被配置为在所述第一阶段，在第一时钟信号的控制下输出栅极驱动信号，以及在所述第一阶段之后的第二阶段，在所述第一时钟信号的控制下输出补偿驱动信号；
    第一复位子电路，电连接在所述第一节点和用于提供所述第一电平的第一电压端之间，被配置为在第一复位信号的控制下，将所述第一节点的电位复位为所述第一电平；
    第二输入子电路，电连接在所述第一节点和所述第一电压端之间，被配置为在所述第一阶段，在第二输入信号的控制下，将第二节点的电位由所述第一电平变为所述第二电平，并将所述第二电平保持到所述第二阶段；以及
    第三输入子电路，与所述第二节点电连接，被配置为在所述第二阶段，在第三输入信号的控制下，将复位后的所述第一节点的电位由所述第一电平变为所述第二电平。
  2. 根据权利要求1所述的移位寄存器单元，其中，
    所述第一输出子电路被配置为在所述第一阶段，在所述第一时钟信号的控制下将所述第一节点的电位由所述第二电平变为第三电平以输出所述栅极驱动信号，以及在所述第二阶段，在所述第一时钟信号的控制下将所述第一节点的电位由所述第二电平变为所述第三电平以输出所述补偿驱动信号；其中，所述第二电平在所述第一电平与所述第三电平之间；
    所述第三输入子电路还被配置为在所述第三输入信号的控制下，将所述第二节点的电位由所述第二电平变为第四电平；其中，所述第二电平在所述第一电平与所述第四电平之间。
  3. 根据权利要求1或2所述的移位寄存器单元，其中，
    所述第二输入子电路包括第一开关晶体管和第一电容器；
    其中，所述第一开关晶体管的第一电极电连接至所述第一节点，所述第一开关晶体管的第二电极电连接至所述第二节点，所述第一开关晶体管的栅极被配置为接收所述第二输入信号；
    所述第一电容器的第一端电连接至所述第二节点，所述第一电容器的第二端电连接至所述第一电压端。
  4. 根据权利要求1-3中任一项所述的移位寄存器单元，其中，
    所述第三输入子电路包括第二开关晶体管和第三开关晶体管；
    其中，所述第二开关晶体管的第一电极电连接至所述第三开关晶体管的栅极，并且所述第二开关晶体管的第一电极被配置为接收所述第三输入信号，所述第二开关晶体管的第二电极电连接至所述第三开关晶体管的第一电极，所述第二开关晶体管的栅极电连接至所述第二节点；所述第三开关晶体管的第二电极电连接至所述第一节点。
  5. 根据权利要求1-4中任一项所述的移位寄存器单元，其中，
    所述第一复位子电路包括第四开关晶体管，
    其中，所述第四开关晶体管的第一电极电连接至所述第一节点，所述第四开关晶体管的第二电极电连接至所述第一电压端，所述第四开关晶体管的栅极被配置为接收所述第一复位信号。
  6. 根据权利要求1-5中任一项所述的移位寄存器单元，还包括：
    第二复位子电路，被配置为在第二复位信号的控制下，将所述第一节点的电位和所述第二节点的电位复位。
  7. 根据权利要求6所述的移位寄存器单元，其中，
    所述第二复位子电路包括第五开关晶体管，
    其中，所述第五开关晶体管的第一电极电连接至所述第一节点，所述第五开关晶体管的第二电极电连接至所述第一电压端，所述第五开关晶体管的栅极被配置为接收所述第二复位信号。
  8. 根据权利要求1-7中任一项所述的移位寄存器单元，还包括：
    第二输出子电路，被配置为在所述第一阶段，在第二时钟信号的控制下输出进位控制信号。
  9. 根据权利要求8所述的移位寄存器单元，还包括：
    降噪子电路，被配置为在所述第一节点的电位被复位的情况下，将所述第一节点的电位保持为所述第一电平；以及
    电位保持子电路，被配置为在所述第一节点的电位被复位的情况下，将所述第一输出子电路的输出端的电位保持为第五电平，以及将所述第二输出子电路的输出端的电位保持为所述第一电平。
  10. 根据权利要求9所述的移位寄存器单元，其中，
    所述降噪子电路包括第六开关晶体管、第七开关晶体管和第八开关晶体管；
    其中，所述第六开关晶体管的第一电极和栅极均电连接至用于提供所述第二电平的第二电压端，所述第六开关晶体管的第二电极电连接至第三节点；
    所述第七开关晶体管的第一电极电连接至所述第三节点，所述第七开关晶体管的第二电极电连接至所述第一电压端，所述第七开关晶体管的栅极电连接至所述第一节点；
    所述第八开关晶体管的第一电极电连接至所述第一节点，所述第八开关晶体管的第二电极电连接至所述第一电压端，所述第八开关晶体管的栅极电连接至所述第三节点。
  11. 根据权利要求9所述的移位寄存器单元，其中，
    所述电位保持子电路包括第九开关晶体管和第十开关晶体管；
    其中，所述第九开关晶体管的第一电极电连接至所述第二输出子电路的输出端，所述第九开关晶体管的第二电极电连接至所述第一电压端，所述第九开关晶体管的栅极电连接至所述第三节点；
    所述第十开关晶体管的第一电极电连接至所述第一输出子电路的输出端，所述第十开关晶体管的第二电极电连接至用于提供所述第五电平的第三电压端，所述第十开关晶体管的栅极电连接至所述第三节点。
  12. 根据权利要求1-11中任一项所述的移位寄存器单元，其中，
    所述第一输出子电路包括第十一开关晶体管和第二电容器；
    其中，所述第十一开关晶体管的第一电极被配置为接收所述第一时钟信号，所述第十一开关晶体管的第二电极作为所述第一输出子电路的输出端，所述第十一开关晶体管的栅极电连接至所述第一节点；
    所述第二电容器的第一端电连接至所述第十一开关晶体管的栅极，所述第二电容器的第二端电连接至所述第十一开关晶体管的第二电极。
  13. 根据权利要求8-11中任一项所述的移位寄存器单元，其中，
    所述第二输出子电路包括第十二开关晶体管；
    其中，所述第十二开关晶体管的第一电极被配置为接收所述第二时钟信号，所述第十二开关晶体管的第二电极作为所述第二输出子电路的输出端，所述第十二开关晶体管的栅极电连接至所述第一节点。
  14. 根据权利要求1-13中任一项所述的移位寄存器单元，其中，
    所述第一输入子电路包括第十三开关晶体管；
    其中，所述第十三开关晶体管的第一电极电连接至用于提供所述第二电平的第四电压端，所述第十三开关晶体管的第二电极电连接至所述第一节点，所述第十三开关晶体管的栅极被配置为接收所述第一输入信号。
  15. 根据权利要求1或2所述的移位寄存器单元，其中，
    所述的移位寄存器单元还包括第二复位子电路、第二输出子电路、降噪子电路和电位保持子电路；
    所述第二输入子电路包括第一开关晶体管和第一电容器；其中，所述第一开关晶体管的第一电极电连接至所述第一节点，所述第一开关晶体管的第二电极电连接至所述第二节点，所述第一开关晶体管的栅极被配置为接收所述第二输入信号；所述第一电容器的第一端电连接至所述第二节点，所述第一电容器的第二端电连接至所述第一电压端；
    所述第三输入子电路包括第二开关晶体管和第三开关晶体管；其中，所述第二开关晶体管的第一电极电连接至所述第三开关晶体管的栅极，并且所述第二开关晶体管的第一电极被配置为接收所述第三输入信号，所述第二开关晶体管的第二电极电连接至所述第三开关晶体管的第一电极，所述第二开关晶体管的栅极电连接至所述第二节点；所述第三开关晶体管的第二电极电连接至所述第一节点；
    所述第一复位子电路包括第四开关晶体管；其中，所述第四开关晶体管的第一电极电连接至所述第一节点，所述第四开关晶体管的第二电极电连接至所述第一电压端，所述第四开关晶体管的栅极被配置为接收所述第一复位信号；
    所述第二复位子电路包括第五开关晶体管；其中，所述第五开关晶体管的第一电极电连接至所述第一节点，所述第五开关晶体管的第二电极电连接至所述第一电压端，所述第五开关晶体管的栅极被配置为接收第二复位信号；
    所述降噪子电路包括第六开关晶体管、第七开关晶体管和第八开关晶体管；其中，所述第六开关晶体管的第一电极和栅极均电连接至用于提供所述第二电平的第二电压端，所述第六开关晶体管的第二电极电连接至第三节点；所述第七开关晶体管的第一电极电连接至所述第三节点，所述第七开关晶体管的第二电极电连接至所述第一电压端，所述第七开关晶体管的栅极电连接至所述第一节点；所述第八开关晶体管的第一电极电连接至所述第一节点，所述第八开关晶体管的第二电极电连接至所述第一电压端，所述第八开关晶体管的栅极电连接至所述第三节点；
    所述电位保持子电路包括第九开关晶体管和第十开关晶体管；其中，所述第九开关晶体管的第一电极电连接至所述第二输出子电路的输出端，所述第九开关晶体管的第二电极电连接至所述第一电压端，所述第九开关晶体管的栅极电连接至所述 第三节点；所述第十开关晶体管的第一电极电连接至所述第一输出子电路的输出端，所述第十开关晶体管的第二电极电连接至用于提供所述第五电平的第三电压端，所述第十开关晶体管的栅极电连接至所述第三节点；
    所述第一输出子电路包括第十一开关晶体管和第二电容器；其中，所述第十一开关晶体管的第一电极被配置为接收所述第一时钟信号，所述第十一开关晶体管的第二电极作为所述第一输出子电路的输出端，所述第十一开关晶体管的栅极电连接至所述第一节点；所述第二电容器的第一端电连接至所述第十一开关晶体管的栅极，所述第二电容器的第二端电连接至所述第十一开关晶体管的第二电极；
    所述第二输出子电路包括第十二开关晶体管；其中，所述第十二开关晶体管的第一电极被配置为接收第二时钟信号，所述第十二开关晶体管的第二电极作为所述第二输出子电路的输出端，所述第十二开关晶体管的栅极电连接至所述第一节点；
    所述第一输入子电路包括第十三开关晶体管；其中，所述第十三开关晶体管的第一电极电连接至用于提供所述第二电平的第四电压端，所述第十三开关晶体管的第二电极电连接至所述第一节点，所述第十三开关晶体管的栅极被配置为接收所述第一输入信号。
  16. 一种栅极驱动电路，包括：多个如权利要求8至11任意一项所述的移位寄存器单元。
  17. 根据权利要求16所述的栅极驱动电路，其中，
    所述多个移位寄存器单元包括N个移位寄存器单元，N为正整数；
    在所述N个移位寄存器单元中，第i-x 1个移位寄存器单元输出的进位控制信号作为第i个移位寄存器单元的第一输入信号，第1个至第x 1个移位寄存器单元的第一输入信号分别为由外部电路输出的第一输入信号，其中，x 1+1≤i≤N且i为正整数，x 1为正整数；
    在所述N个移位寄存器单元中，第j+x 2个移位寄存器单元输出的进位控制信号作为第j个移位寄存器单元的第一复位信号，第N-x 2+1个至第N个移位寄存器单元的第一复位信号分别为由所述外部电路输出的第一复位信号，其中，1≤j≤N-x 2且j为正整数，x 2为正整数。
  18. 一种显示装置，包括：如权利要求16或17所述的栅极驱动电路。
  19. 一种用于移位寄存器单元的控制方法，包括：
    在第一阶段，第一输入子电路在第一输入信号的控制下，将第一节点的电位由第一电平变为第二电平，第二输入子电路在第二输入信号的控制下，将第二节点的 电位由第一电平变为第二电平，并将所述第二节点的第二电平保持到在所述第一阶段之后的第二阶段；
    第一输出子电路在第一时钟信号的控制下将所述第一节点的电位由所述第二电平变为第三电平以输出栅极驱动信号，其中，所述第二电平在所述第一电平与所述第三电平之间；
    第一复位子电路在第一复位信号的控制下，将所述第一节点的电位复位为所述第一电平；
    在所述第二阶段，第三输入子电路在第三输入信号的控制下，将复位后的所述第一节点的电位由所述第一电平变为所述第二电平；以及
    所述第一输出子电路在所述第一时钟信号的控制下将所述第一节点的电位由所述第二电平变为所述第三电平以输出补偿驱动信号。
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