WO2018223834A1 - 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置 - Google Patents

移位寄存器单元及其驱动方法、栅极驱动电路及显示装置 Download PDF

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Publication number
WO2018223834A1
WO2018223834A1 PCT/CN2018/087619 CN2018087619W WO2018223834A1 WO 2018223834 A1 WO2018223834 A1 WO 2018223834A1 CN 2018087619 W CN2018087619 W CN 2018087619W WO 2018223834 A1 WO2018223834 A1 WO 2018223834A1
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Prior art keywords
transistor
pull
potential
node
signal
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PCT/CN2018/087619
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English (en)
French (fr)
Inventor
青海刚
谭文
龙跃
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US16/319,623 priority Critical patent/US11183103B2/en
Publication of WO2018223834A1 publication Critical patent/WO2018223834A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register unit and a driving method thereof, a gate driving circuit, and a display device.
  • the display device When displaying the image, the display device needs to scan the pixel array by using a gate driving circuit, and the gate driving circuit includes a plurality of cascaded shift register units, each shift register unit corresponding to a row of pixel units in the pixel array, The plurality of cascaded shift register units enable progressive scan driving of each row of pixel cells in the pixel array of the display device to display an image.
  • the gate driving circuit includes a plurality of cascaded shift register units, each shift register unit corresponding to a row of pixel units in the pixel array, The plurality of cascaded shift register units enable progressive scan driving of each row of pixel cells in the pixel array of the display device to display an image.
  • a shift register unit in the related art, which mainly includes an input sub-circuit, an output sub-circuit, and a noise reduction sub-circuit.
  • the input sub-circuit is used to input the voltage of the output end of the shift register unit of the previous row to the shift register unit, and pull up the level of the pull-up node in the shift register unit to a high level;
  • the output sub-circuit is used to Under the control of the pull-up node, the gate drive signal is output to the output end of the shift register unit;
  • the noise reduction sub-circuit is used to pull down the level of the output terminal of the shift register unit to low power under the control of the clock signal Flat, thereby achieving noise reduction at the output of the shift register unit.
  • the noise reduction sub-circuit is controlled by the clock signal, when the clock signal is at a low level, the transistor in the noise reduction sub-circuit cannot be effectively turned on, and at this time, the noise reduction sub-circuit cannot make the output terminal level effective. Pulling down to a low level, the noise reduction sub-circuit has poor noise reduction performance.
  • the present disclosure provides a shift register unit and a driving method thereof, a gate driving circuit, and a display device.
  • a shift register unit including: an input sub-circuit, a control sub-circuit, a noise reduction sub-circuit, and an output sub-circuit.
  • the input sub-circuit is respectively connected to the input signal end, the first control signal end and the pull-up node, and is configured to output to the pull-up node when the input signal outputted by the input signal end is the first potential The first control signal of the first control signal end.
  • the control sub-circuit is respectively connected to the pull-up node, the first clock signal end, the second clock signal end, the first power signal end, the second power signal end, and the pull-down node, and is configured to be at the pull-up node a first potential, a second power signal from the second power signal terminal is output to the pull-down node, and a second clock signal outputted at the second clock signal terminal is a second potential, and the first clock
  • the first clock signal outputted by the signal terminal is the first potential
  • the first power signal from the first power signal terminal is output to the pull-down node, wherein the first power signal is a first potential
  • the second power source The signal is the second potential.
  • the noise reduction sub-circuit is respectively connected to the pull-down node, the second clock signal end, the second power signal end and the output end, and is configured to be at the pull-down node or the second clock signal end At a potential, the second power signal is output to the output, wherein the first clock signal and the second clock signal have the same frequency and opposite phases.
  • the output sub-circuit is respectively connected to the first clock signal end, the pull-up node and the output end, and is configured to output the first to the output end when the pull-up node is at a first potential A clock signal.
  • the input sub-circuit is further connected to the reset signal end and the second control signal end, and is configured to output to the pull-up node when the reset signal outputted by the reset signal end is the first potential a second control signal of the second control signal end, wherein the first control signal is a first potential, and the second control signal is a second potential.
  • the noise reduction sub-circuit is further connected to the pull-up node, and is configured to output the second power signal to the pull-up node when the pull-down node is at a first potential.
  • the control sub-circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor; a gate of the first transistor is connected to the second clock signal end a first pole is connected to the first power signal terminal, a second pole is connected to the first node, a gate of the second transistor is connected to the first node, and the first pole and the first clock signal end are Connected, a second pole is connected to a gate of the third transistor; a first pole of the third transistor is connected to the first power signal terminal, and a second pole is connected to the pull-down node; the fourth transistor a gate connected to the pull-up node, a first pole connected to the second clock signal terminal, a second pole connected to the first node, and a gate of the fifth transistor connected to the pull-up node The first pole is connected to the second power signal end, and the second pole is connected to the pull-down node.
  • the noise reduction sub-circuit includes: a sixth transistor, a seventh transistor, and an eighth transistor; a gate of the sixth transistor is connected to the pull-down node, and the first pole and the second power source a signal terminal is connected, a second pole is connected to the pull-up node; a gate of the seventh transistor is connected to the pull-down node, a first pole is connected to the second power signal end, a second pole is connected to the output An end connection; a gate of the eighth transistor is connected to the second clock signal end, a first pole is connected to the second power signal end, and a second pole is connected to the output end.
  • the input sub-circuit includes: a ninth transistor and a tenth transistor; a gate of the ninth transistor is connected to the input signal end, and a first pole is connected to the first control signal end, a second pole is connected to the pull-up node; a gate of the tenth transistor is connected to the reset signal end, a first pole is connected to the second control signal end, and a second pole is connected to the pull-up node .
  • the output sub-circuit includes: an eleventh transistor and a capacitor; a gate of the eleventh transistor is connected to the pull-up node, and a first pole is connected to the first clock signal end, The second pole is connected to the output end; one end of the capacitor is connected to the pull-up node, and the other end is connected to the output end.
  • a driving method of a shift register unit comprising: an input sub-circuit, a control sub-circuit, a noise reduction sub-circuit, and an output sub-circuit; the method comprising:
  • the input signal outputted by the input signal terminal is a first potential
  • the input sub-circuit outputs a first control signal from the first control signal end, the first control signal, under the control of the input signal Charging the pull-up node for a first potential
  • the first clock signal outputted by the first clock signal terminal is a first potential
  • the pull-up node maintains a first potential
  • the output sub-circuit is output to the output terminal under the control of the pull-up node The first clock signal
  • the first clock signal and the second clock signal alternately being a first potential, and when the first clock signal is at a first potential, the control sub-circuit outputs to the pull-down node a first power signal from the first power signal terminal, the first power signal is at a first potential, and the noise reduction sub-circuit outputs the second power signal to the output terminal under the control of the pull-down node;
  • the noise reduction sub-circuit outputs the second power signal to the output terminal under the control of the second clock signal when the second clock signal is at a first potential.
  • the input sub-circuit outputs a second control signal from the second control signal end to the pull-up node under the control of the reset signal, and the noise reduction sub-circuit is controlled by the second clock signal
  • the output terminal outputs a second power signal from the second power signal terminal, and the second control signal and the second power signal are both at a second potential.
  • control sub-circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor; and the noise reduction sub-circuit includes: a sixth transistor, a seventh transistor, and Eighth transistor
  • the first clock signal and the second clock signal are alternately at a first potential, the second transistor is maintained in an on state, and the first clock signal is terminated to the third transistor
  • the gate outputs the first clock signal, when the first clock signal is at a first potential, the third transistor is turned on, and the first power signal end outputs the first power to the pull-down node a signal, the sixth transistor and the seventh transistor are turned on, the second power signal terminal respectively outputting the second power signal to the pull-up node and the output terminal; and the second clock signal
  • the eighth power transistor is turned on, and the second power signal terminal outputs the second power signal to the output terminal.
  • the transistors are all N-type transistors, and the first potential is at a high potential with respect to the second potential.
  • a gate driving circuit including: at least two cascaded shift register units as described above.
  • a display device comprising: a gate driving circuit as described above.
  • the present disclosure provides a shift register unit and a driving method thereof, a gate driving circuit and a display device, wherein the shift register unit includes a control sub-circuit and a noise reduction sub-circuit, and the control sub-circuit can be in the first clock signal At the first potential, the potential of the pull-down node is controlled to be the first potential; and the noise reduction sub-circuit can control the potential of the output terminal to be the second potential when the pull-down node or the second clock signal is at the first potential. Since the first clock signal and the second clock signal have the same phase and opposite frequency, the control sub-circuit and the noise reduction sub-circuit can control the potential of the output terminal to be the second potential after the output stage of the shift register unit, thereby ensuring Effective noise reduction at this output.
  • FIG. 1 is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 3 is a flowchart of a driving method of a shift register unit according to an embodiment of the present disclosure
  • FIG. 4 is a timing diagram of a driving process of a shift register unit according to an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of another shift register unit according to an embodiment of the present disclosure.
  • FIG. 6 is a timing diagram of a driving process of another shift register unit according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other device having the same characteristics, and the transistors employed in the embodiments of the present disclosure are mainly switching transistors according to the functions in the circuit. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable. In the embodiments of the present disclosure, the source is referred to as a first stage and the drain is referred to as a second stage. According to the form in the drawing, the middle end of the transistor is the gate, the signal input end is the source, and the signal output end is the drain.
  • the switching transistor employed in the embodiments of the present disclosure may include any one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level, and is turned off when the gate is at a high level.
  • the N-type switching transistor is turned on when the gate is at a high level and turned off when the gate is at a low level.
  • the plurality of signals in the various embodiments of the present disclosure correspond to a first potential and a second potential, and the first potential and the second potential only represent two state quantities of the potential of the signal, and do not represent the first potential in the whole or The second potential has a specific value.
  • the first potential is high with respect to the second potential as an example.
  • the shift register unit may include: an input sub-circuit 10, a control sub-circuit 20, a noise reduction sub-circuit 30, and an output. Subcircuit 40.
  • the input sub-circuit 10 is respectively connected to the input signal terminal IN, the first control signal terminal CN and the pull-up node PU, and is configured to output to the pull-up node PU when the input signal outputted by the input signal terminal IN is at the first potential.
  • the first control signal from the first control signal terminal CN is the first potential, so the pull-up node PU can be charged.
  • the input sub-circuit 10 is further connected to the reset signal terminal RST and the second control signal terminal CNB, and is configured to output to the pull-up node PU when the reset signal outputted by the reset signal terminal RST is the first potential.
  • the second control signal of the second control signal terminal CNB, the second control signal is the second potential, so the pull-up node PU can be reset.
  • the first control signal is a first potential
  • the second control signal is a second potential.
  • the control sub-circuit 20 is respectively connected to the pull-up node PU, the first clock signal terminal CK, the second clock signal terminal CKB, the first power signal terminal VGH, the second power signal terminal VGL, and the pull-down node PD, for When the pull-up node PU is at the first potential, the second power signal from the second power signal terminal VGL is output to the pull-down node PD, and the second clock signal outputted at the second clock signal terminal CKB is the second potential. And when the first clock signal outputted by the first clock signal terminal CK is the first potential, the first power signal from the first power signal terminal VGH is output to the pull-down node PD, wherein the first power signal is the first potential The second power signal is a second potential.
  • the noise reduction sub-circuit 30 is connected to the pull-down node PD, the second clock signal terminal CKB, the second power signal terminal VGL and the output terminal OUT, respectively, for the pull-down node PD or the second clock signal terminal CKB At the first potential, the second power signal is output to the output terminal OUT, thereby denoising the output terminal OUT.
  • the first clock signal and the second clock signal have the same frequency and opposite phases (ie, the phases are 180° out of phase).
  • the noise reduction sub-circuit 30 may be further connected to the pull-up node PU for outputting the second power signal to the pull-up node PU when the pull-down node PD is at a first potential.
  • the output sub-circuit 40 is respectively connected to the first clock signal terminal CK, the pull-up node PU and the output terminal OUT, and is configured to output the first to the output terminal OUT when the pull-up node PU is at the first potential
  • the clock signal, the first clock signal output by the output sub-circuit 40 is a gate driving signal for driving a row of pixel units.
  • the control sub-circuit 20 may specifically include: a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor. T4 and fifth transistor T5.
  • the gate of the first transistor T1 is connected to the second clock signal terminal CKB, the first pole is connected to the first power signal terminal VGH, and the second pole is connected to the first node P1.
  • the gate of the second transistor T2 is connected to the first node P1, the first pole is connected to the first clock signal terminal CK, the second pole is connected to the gate of the third transistor T3, and the first pole of the third transistor T3 is The first power signal terminal VGH is connected, and the second pole is connected to the pull-down node PD.
  • the gate of the fourth transistor T4 is connected to the pull-up node PU, the first pole is connected to the second clock signal terminal CKB, and the second pole is connected to the first node P1.
  • the gate of the fifth transistor T5 is connected to the pull-up node PU, the first pole is connected to the second power signal terminal VGL, and the second pole is connected to the pull-down node PD.
  • the fourth transistor T4 and the fifth transistor T5 of the control sub-circuit 20 are turned on, and the second power signal from the second power signal terminal VGL is output to the pull-down node PD;
  • the second clock signal outputted by the second clock signal terminal CKB is the second potential
  • the first clock signal outputted by the first clock signal terminal CK is the first potential
  • the first node P1 is at the first potential
  • the second transistor T2 and the third transistor T3 of the control sub-circuit 20 are turned on, and output a first power signal from the first power signal terminal VGH to the pull-down node PD, wherein the first power signal is a first potential
  • the second power signal is at a second potential.
  • the noise reduction sub-circuit 30 may include a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8.
  • the gate of the sixth transistor T6 is connected to the pull-down node PD, the first pole is connected to the second power signal terminal VGL, and the second pole is connected to the pull-up node PU.
  • the gate of the seventh transistor T7 is connected to the pull-down node PD, the first pole is connected to the second power signal terminal VGL, and the second pole is connected to the output terminal OUT.
  • the gate of the eighth transistor T8 is connected to the second clock signal terminal CKB, the first pole is connected to the second power signal terminal VGL, and the second pole is connected to the output terminal OUT.
  • the noise reduction sub-circuit 30 When the pull-down node PD is at the first potential, the noise reduction sub-circuit 30 outputs the second power signal to the pull-up node PU and the output terminal OUT, thereby performing noise reduction on the pull-up node PU and the output terminal OUT. .
  • the noise reduction sub-circuit 30 outputs the second power signal to the output terminal OUT, thereby performing noise reduction on the output terminal OUT.
  • the input sub-circuit 10 may include: a ninth transistor T9 and a tenth transistor T10; the output sub-circuit 40 may include an eleventh transistor T11 and a capacitor C1.
  • the gate of the ninth transistor T9 is connected to the input signal terminal IN, the first pole is connected to the first control signal terminal CN, and the second pole is connected to the pull-up node PU.
  • the gate of the tenth transistor T10 is connected to the reset signal terminal RST, the first pole is connected to the second control signal terminal CNB, and the second pole is connected to the pull-up node PU.
  • the input sub-circuit 10 When the input signal outputted by the input signal terminal IN is the first potential, the input sub-circuit 10 outputs the first control signal from the first control signal terminal CN to the pull-up node PU, so that the pull-up node PU can be Charge it.
  • the input sub-circuit 10 When the reset signal outputted by the reset signal terminal RST is the first potential, the input sub-circuit 10 outputs a second control signal from the second control signal terminal CNB to the pull-up node PU, so that the pull-up node PU can be Reset.
  • the gate of the eleventh transistor T11 is connected to the pull-up node PU, the first pole is connected to the first clock signal terminal CK, and the second pole is connected to the output terminal OUT.
  • One end of the capacitor C1 is connected to the pull-up node PU, and the other end is connected to the output terminal OUT.
  • the output sub-circuit 40 When the pull-up node PU is at the first potential, the output sub-circuit 40 outputs the first clock signal to the output terminal OUT as a gate driving signal for driving a row of pixel circuits.
  • the embodiment of the present disclosure provides a shift register unit, where the shift register unit includes a control sub-circuit and a noise reduction sub-circuit, and the control sub-circuit can be when the first clock signal is at the first potential.
  • the potential of the pull-down node is controlled to be a first potential; and the noise reduction sub-circuit can control the potential of the output terminal to be the second potential when the pull-down node or the second clock signal is at the first potential. Since the first clock signal and the second clock signal have the same phase and opposite frequency, the control sub-circuit and the noise reduction sub-circuit can control the potential of the output terminal to be the second potential after the output stage of the shift register unit, thereby ensuring Effective noise reduction at this output.
  • only one capacitor is applied to the shift register unit provided by the embodiment of the present disclosure, the circuit structure is relatively simple, the occupied area is small, and the narrow bezel design of the display panel is easy to implement.
  • Embodiments of the present disclosure provide a driving method of a shift register unit, which may be used to drive a shift register unit as shown in FIG. 1 or FIG. 2.
  • the shift register unit includes: an input sub-circuit 10.
  • step 101 the charging phase, the input signal outputted by the input signal terminal IN is the first potential, and the input sub-circuit 10 outputs the first control signal from the first control signal terminal CN under the control of the input signal.
  • the first control signal is at a first potential to charge the pull-up node PU.
  • the control sub-circuit 20 outputs a second power supply signal from the second power supply signal terminal VGL to the pull-down node PD under the control of the pull-up node PU.
  • Step 102 The output stage, the first clock signal outputted by the first clock signal terminal CK is a first potential, the pull-up node PU maintains a first potential, and the output sub-circuit 40 is under the control of the pull-up node PU The output terminal OUT outputs the first clock signal. Meanwhile, in the output stage, the control sub-circuit 20 outputs a second power supply signal from the second power supply signal terminal VGL to the pull-down node PD under the control of the pull-up node PU.
  • the output noise reduction phase, the first clock signal and the second clock signal are alternately at a first potential, and when the first clock signal is at the first potential, the control sub-circuit 20 is to the pull-down node
  • the PD outputs a first power signal from the first power signal terminal VGH, the first power signal is at a first potential, and the noise reduction sub-circuit 30 is respectively controlled by the pull-down node PD to the pull-up node PU and the output
  • the terminal OUT outputs the second power signal; when the second clock signal is at the first potential, the noise reduction sub-circuit 30 outputs the second power signal to the output terminal OUT under the control of the second clock signal.
  • the input sub-circuit 10 in the case where the input sub-circuit 10 is also connected to the reset signal terminal, in the step 103 of the output noise reduction phase (this phase may also be referred to as a first output noise reduction phase or In the reset phase), when the reset signal outputted by the reset signal terminal RST is the first potential and the second clock signal outputted by the second clock signal terminal CKB is the first potential, the input sub-circuit 10 is also under the control of the reset signal.
  • a second control signal from the second control signal terminal CNB is output to the pull-up node PU.
  • the noise reduction sub-circuit 30 outputs a second power signal from the second power signal terminal VGL to the output terminal OUT under the control of the second clock signal, and the second control signal and the second power signal are both Is the second potential.
  • the first clock signal and the second clock signal alternately are at a first potential, and the reset signal terminal RST The output reset signal is the second potential.
  • FIG. 4 is a timing diagram of a driving process of a shift register unit according to an embodiment of the present disclosure.
  • the shift register unit shown in FIG. 2 is taken as an example to describe a driving method of a shift register unit according to an embodiment of the present disclosure. . It should be understood that although the case where the input sub-circuit 10 is connected to the reset signal input terminal RST is specifically described in the following description, the reset signal input terminal RST and its corresponding operation may be omitted according to actual needs.
  • the input signal outputted by the input signal terminal IN, and the second clock signal outputted by the second clock signal terminal CKB are the first potential
  • the reset signal output by the reset signal terminal RST and the The first clock signal outputted by a clock signal terminal CK is a second potential.
  • the ninth transistor T9, the first transistor T1 and the eighth transistor T8 are turned on, and the first control signal terminal IN outputs a first control signal to one end of the capacitor C1 through the ninth transistor T9.
  • the potential of the first control signal is the same as the potential of the first power supply signal terminal VGH, and both are high. Therefore, the capacitor C1 can be charged to raise the potential of the pull-up node PU.
  • the eleventh transistor T11, the fourth transistor T4, and the fifth transistor T5 are turned on, the first clock signal terminal CK outputs a first clock signal to the output terminal OUT, and the potential of the output terminal OUT is pulled low; the second power source
  • the signal terminal VGL outputs a second power signal to the pull-down node PD through the fifth transistor T5, and pulls down the potential of the pull-down node PD, thereby turning off the sixth transistor T6 and the seventh transistor T7, thereby avoiding the potential of the pull-up node PU. influences.
  • the second clock signal and the first power signal drive the second transistor T2 to be turned on, and the first clock signal terminal CK is output to the gate of the third transistor T3.
  • the first clock signal of the potential, the third transistor T3 is turned off, so the first power signal terminal VGH does not affect the potential of the pull-down node PD.
  • the input signal, the reset signal and the second clock signal are both at the second potential, the first transistor T1, the eighth to the tenth transistors are all in an off state; the first clock signal outputted by the first clock signal terminal CK
  • the pull-up node PU has no discharge path maintained at the first potential, and the first clock signal terminal CK outputs the first clock signal to the output terminal OUT.
  • the pull-down node PD remains at the second potential, and the second clock signal terminal CKB outputs the second potential to the first node P1 through the fourth transistor T4.
  • the second transistor T2 is turned off, the first clock signal at the first potential outputted by the first clock signal terminal CK cannot be applied to the gate of the third transistor T3 through the second transistor T2, and the third transistor T3 remains The off state of the previous stage, so that the sixth transistor T6 and the seventh transistor T7 are also kept off state, to avoid affecting the potential of the pull-up node PU and the output terminal OUT.
  • the signal outputted by the reset signal terminal RST and the second clock signal terminal CKB is at the first potential
  • the signal outputted by the input signal terminal IN and the first clock signal terminal CK is the first
  • the two potentials, the ninth transistor T9 are turned off, and the first transistor T1, the eighth transistor T8, and the tenth transistor T10 are turned on.
  • the second control signal terminal CNB pulls up the node PU to output a second control signal.
  • the potential of the second control signal is equal to the potential of the second power signal terminal VGL, and both are low, so
  • the pull-up node PU performs resetting, at which time the fourth transistor T4 and the fifth transistor T5 are turned off.
  • the first transistor T1 is turned on, the first power signal terminal VGH drives the second transistor T2 to be turned on, but since the first clock signal outputted by the first clock signal terminal CK is at the second potential, the third transistor T3 is still turned off. status. Since the eighth transistor T8 is turned on, the second clock signal terminal CKB outputs a second clock signal at the second potential to the output terminal OUT, thereby resetting the output terminal OUT.
  • the reset signal outputted by the reset signal terminal RST maintains the second potential, the first clock signal outputted by the first clock signal terminal CK and the second clock signal output from the second clock signal terminal CKB.
  • the clock signal alternates to a first potential.
  • the gate of the second transistor T2 ie, the first node P1 maintains the state of the previous stage by using its own gate-source capacitance because it has no low-level pull-down, and thus remains in an on state, the first clock signal terminal CK
  • the first clock signal is continuously output to the gate of the third transistor T3.
  • the third transistor T3 When the first clock signal is at the first potential, the third transistor T3 is turned on, and the first power signal terminal VGH outputs the first power signal to the pull-down node PD, the sixth transistor T6 and the seventh transistor T7 Turning on, the second power signal terminal VGL respectively outputs the second power signal to the node PU and the output terminal OUT; when the second clock signal is at the first potential, the eighth transistor T8 is turned on, and the second power signal is The terminal VGL outputs the second power signal to the output terminal OUT.
  • each transistor in the noise reduction sub-circuit 30 can continuously perform noise reduction on the output terminal OUT.
  • the noise reduction performance of the shift register unit is effectively improved.
  • each transistor is an N-type transistor and the first potential is at a high potential with respect to the second potential.
  • the transistors may also adopt P-type transistors.
  • the connection relationship between the transistors may remain unchanged, but the output of the first power signal terminal VGH is The first power signal is at a high level, and the second power signal outputted by the second power signal terminal VGL is at a low level. Therefore, as can be seen by comparing FIG. 2 and FIG. 5, only the positions of the two signal terminals need to be interchanged.
  • the first potential may be low relative to the second potential
  • the timing diagram of each signal terminal may be as shown in FIG. 6.
  • the potential change of each signal terminal can be opposite to the potential change shown in Fig. 4 (i.e., the phase difference between the two is 180 degrees).
  • the present disclosure provides a driving method of a shift register unit.
  • the control sub-circuit In the output noise reduction phase, when the first clock signal is at the first potential, the control sub-circuit can control the potential of the pull-down node to be the first potential.
  • the noise reduction sub-circuit can reduce noise on the pull-up node and the output end under the control of the pull-down node; and when the second clock signal is at the first potential, the noise reduction sub-circuit can directly reduce the noise on the output end . Since the first clock signal and the second clock signal have the same phase and opposite frequency, the potential of the output of the shift register unit can be kept at the second potential after the output stage, thereby ensuring effective noise reduction for the output.
  • FIG. 7 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • the gate driving circuit may include at least two cascaded shift register units 00, wherein each shift register unit may It is a shift register unit as shown in FIG. 1, FIG. 2 or FIG. 5.
  • the input signal terminal IN input of each stage shift register unit is connected to the output terminal OUT of the shift register unit of the previous stage; the reset signal terminal RST of each stage shift register unit and the next The output terminal OUT of the stage shift register unit is connected.
  • the input signal terminal IN of the nth stage shift register unit is connected to the output terminal OUT(n-1) of the n-1th stage shift register unit, and the nth stage shift The reset signal terminal RST of the register unit is connected to the output terminal OUT(n+1) of the n+1th stage shift register unit. It can also be seen from FIG.
  • each of the shift register units in the gate driving circuit can realize forward and reverse bidirectional scanning of the display device.
  • each shift in the gate drive circuit can be caused.
  • the register units are sequentially activated starting from the first stage shift register unit, whereby forward scanning of the display device can be achieved.
  • each shift register unit in the gate drive circuit can be made Starting from the last stage shift register unit, a reverse scan of the display device can be achieved.
  • the embodiment of the present disclosure further provides a display device, which may include a gate driving circuit as shown in FIG.
  • the display device can be: liquid crystal panel, electronic paper, OLED panel, AMOLED panel, low temperature polysilicon (English: Low Temperature Poly-silicon; LTPS) display panel, mobile phone, tablet computer, television, display, notebook computer, digital Any product or component that has a display function, such as a photo frame or a navigator.

Abstract

一种移位寄存器单元及其驱动方法、栅极驱动电路及显示装置，属于显示技术领域。该移位寄存器单元中包括控制子电路（20）和降噪子电路（30），该控制子电路（20）可以在第一时钟信号（CK）为第一电位时，控制下拉节点（PD）的电位为第一电位；而该降噪子电路（30）则可以在下拉节点（PD）或者第二时钟信号（CKB）为第一电位时，控制输出端（OUT）的电位为第二电位。由于该第一时钟信号（CK）和第二时钟信号（CKB）频率相同相位相反，因此该控制子电路（20）和降噪子电路（30）可以在移位寄存器单元的输出阶段之后，控制输出端（OUT）的电位持续为第二电位，从而保证对该输出端（OUT）的有效降噪。

Description

移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
相关申请的交叉引用
本申请要求于2017年6月9日提交的中国专利申请第201710433808.2号的优先权，该中国专利申请的全文通过引用的方式结合于此以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，特别涉及一种移位寄存器单元及其驱动方法、栅极驱动电路及显示装置。
背景技术
显示装置在显示图像时，需要利用栅极驱动电路对像素阵列进行扫描，栅极驱动电路包括多个级联的移位寄存器单元，每个移位寄存器单元对应像素阵列中的一行像素单元，由该多个级联的移位寄存器单元实现对显示装置的像素阵列中各行像素单元的逐行扫描驱动，以显示图像。
相关技术中有一种移位寄存器单元，该移位寄存器单元主要包括输入子电路、输出子电路和降噪子电路。其中，输入子电路用于将上一行移位寄存器单元输出端的电压输入至该移位寄存器单元，将该移位寄存器单元中上拉节点的电平上拉至高电平；输出子电路用于在上拉节点的控制下，向该移位寄存器单元的输出端输出栅极驱动信号；降噪子电路用于在时钟信号的控制下，将该移位寄存器单元的输出端的电平下拉至低电平，从而实现对该移位寄存器单元的输出端的降噪。
但是，由于降噪子电路是由时钟信号控制的，当该时钟信号处于低电平时，该降噪子电路中的晶体管无法有效导通，此时该降噪子电路无法将输出端的电平有效下拉至低电平，该降噪子电路的降噪性能较差。
发明内容
为了解决相关技术中移位寄存器单元降噪性能较差的问题，本公开提供了一种移位寄存器单元及其驱动方法、栅极驱动电路及显示装置。
根据本公开实施例，提供了一种移位寄存器单元，所述移位寄存器单元包括：输入子电路、控制子电路、降噪子电路和输出子电路。
所述输入子电路分别与输入信号端、第一控制信号端和上拉节点连接，用于在所述输入信号端输出的输入信号为第一电位时，向所述上拉节点输出来自所述第一控制信号端的第一控制信号。
所述控制子电路分别与所述上拉节点、第一时钟信号端、第二时钟信号端、第一电源信号端、第二电源信号端和下拉节点连接，用于在所述上拉节点为第一电位时，向所述下拉节点输出来自所述第二电源信号端的第二电源信号，以及在所述第二时钟信号端输出的第二时钟信号为第二电位、且所述第一时钟信号端输出的第一时钟信号为第一电位时，向所述下拉节点输出来自所述第一电源信号端的第一电源信号，其中所述第一电源信号为第一电位，所述第二电源信号为第二电位。
所述降噪子电路分别与所述下拉节点、所述第二时钟信号端、所述第二电源信号端和输出端连接，用于在所述下拉节点或所述第二时钟信号端为第一电位时，向所述输出端输出所述第二电源信号，其中，所述第一时钟信号和所述第二时钟信号的频率相同，相位相反。
所述输出子电路分别与所述第一时钟信号端、所述上拉节点和所述输出端连接，用于在所述上拉节点为第一电位时，向所述输出端输出所述第一时钟信号。
根据本公开实施例，所述输入子电路还与复位信号端和第二控制信号端连接，用于在所述复位信号端输出的复位信号为第一电位时，向所述上拉节点输出来自所述第二控制信号端的第二控制信号，其中所述第一控制信号为第一电位，所述第二控制信号为第二电位。
根据本公开实施例，所述降噪子电路还与所述上拉节点连接，用于在所述下拉节点为第一电位时，向所述上拉节点输出所述第二电源信号。
根据本公开实施例，所述控制子电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管和第五晶体管；所述第一晶体管的栅极与所述第二时钟信号端连接，第一极与所述第一电源信号端连接，第二极与第一节点连接；所述第二晶体管的栅极与所述第一节点连接，第一极与所述第一时钟信号端连接，第二极与所述第三晶体管的栅极连接；所述第三晶体管的第一极 与所述第一电源信号端连接，第二极与所述下拉节点连接；所述第四晶体管的栅极与所述上拉节点连接，第一极与所述第二时钟信号端连接，第二极与所述第一节点连接；所述第五晶体管的栅极与所述上拉节点连接，第一极与所述第二电源信号端连接，第二极与所述下拉节点连接。
根据本公开实施例，所述降噪子电路包括：第六晶体管、第七晶体管和第八晶体管；所述第六晶体管的栅极与所述下拉节点连接，第一极与所述第二电源信号端连接，第二极与所述上拉节点连接；所述第七晶体管的栅极与所述下拉节点连接，第一极与所述第二电源信号端连接，第二极与所述输出端连接；所述第八晶体管的栅极与所述第二时钟信号端连接，第一极与所述第二电源信号端连接，第二极与所述输出端连接。
根据本公开实施例，所述输入子电路包括：第九晶体管和第十晶体管；所述第九晶体管的栅极与所述输入信号端连接，第一极与所述第一控制信号端连接，第二极与所述上拉节点连接；所述第十晶体管的栅极与所述复位信号端连接，第一极与所述第二控制信号端连接，第二极与所述上拉节点连接。
根据本公开实施例，所述输出子电路包括：第十一晶体管和电容器；所述第十一晶体管的栅极与所述上拉节点连接，第一极与所述第一时钟信号端连接，第二极与所述输出端连接；所述电容器的一端与所述上拉节点连接，另一端与所述输出端连接。
根据本公开实施例，提供了一种移位寄存器单元的驱动方法，所述移位寄存器单元包括：输入子电路、控制子电路、降噪子电路和输出子电路；所述方法包括：
充电阶段，输入信号端输出的输入信号为第一电位，所述输入子电路在所述输入信号的控制下，向上拉节点输出来自第一控制信号端的第一控制信号，所述第一控制信号为第一电位，对所述上拉节点进行充电；
输出阶段，第一时钟信号端输出的第一时钟信号为第一电位，所述上拉节点保持第一电位，所述输出子电路在所述上拉节点的控制下，向所述输出端输出所述第一时钟信号；
降噪输出降噪阶段，所述第一时钟信号和所述第二时钟信号交替为第一电位，在所述第一时钟信号为第一电位时，所述控制子电路向所述下拉节点输出来自第一电源信号端的第一电源信号，所述第一电源信号处于第一电位， 所述降噪子电路在所述下拉节点的控制下，向所述输出端输出所述第二电源信号；在所述第二时钟信号为第一电位时，所述降噪子电路在所述第二时钟信号的控制下，向所述输出端输出所述第二电源信号。
根据本公开实施例，在所述输出降噪阶段中，在所述复位信号端输出的复位信号为第一电位且所述第二时钟信号端输出的第二时钟信号为第一电位时，所述输入子电路在所述复位信号的控制下，向所述上拉节点输出来自第二控制信号端的第二控制信号，所述降噪子电路在所述第二时钟信号的控制下，向所述输出端输出来自第二电源信号端的第二电源信号，所述第二控制信号和所述第二电源信号均为第二电位。
根据本公开实施例，所述控制子电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管和第五晶体管；所述降噪子电路，包括：第六晶体管、第七晶体管和第八晶体管；
所述输出降噪阶段中，所述第一时钟信号和所述第二时钟信号交替为第一电位，所述第二晶体管保持导通状态，所述第一时钟信号端向所述第三晶体管的栅极输出所述第一时钟信号，在所述第一时钟信号为第一电位时，所述第三晶体管导通，所述第一电源信号端向所述下拉节点输出所述第一电源信号，所述第六晶体管和所述第七晶体管导通，所述第二电源信号端分别向所述上拉节点和所述输出端输出所述第二电源信号；在所述第二时钟信号为第一电位时，所述第八晶体管导通，所述第二电源信号端向所述输出端输出所述第二电源信号。
根据本公开实施例，所述晶体管均为N型晶体管，所述第一电位相对于所述第二电位为高电位。
根据本公开实施例，提供了一种栅极驱动电路，所述栅极驱动电路包括：至少两个级联的如上所述的移位寄存器单元。
根据本公开实施例，提供了一种显示装置，所述显示装置包括：如上所述的栅极驱动电路。
本公开提供了一种移位寄存器单元及其驱动方法、栅极驱动电路及显示装置，该移位寄存器单元中包括控制子电路和降噪子电路，该控制子电路可以在第一时钟信号为第一电位时，控制下拉节点的电位为第一电位；而该降噪子电路则可以在下拉节点或者第二时钟信号为第一电位时，控制输出端 的电位为第二电位。由于该第一时钟信号和第二时钟信号频率相同相位相反，因此该控制子电路和降噪子电路可以在移位寄存器单元的输出阶段之后，控制输出端的电位持续为第二电位，从而保证对该输出端的有效降噪。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制本公开，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种移位寄存器单元的结构示意图；
图2是本公开实施例提供的一种移位寄存器单元的结构示意图；
图3是本公开实施例提供的一种移位寄存器单元的驱动方法的流程图；
图4是本公开实施例提供的一种移位寄存器单元的驱动过程的时序图；
图5是本公开实施例提供的另一种移位寄存器单元的结构示意图；
图6是本公开实施例提供的另一种移位寄存器单元的驱动过程的时序图；
图7是本公开实施例提供的一种栅极驱动电路的结构示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，本公开下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件，根据在电路中的作用本公开的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以 其源极、漏极是可以互换的。在本公开实施例中，将其中源极称为第一级，漏极称为第二级。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外，本公开实施例所采用的开关晶体管可以包括P型开关晶体管和N型开关晶体管中的任一种，其中，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型开关晶体管在栅极为高电平时导通，在栅极为低电平时截止。此外，本公开各个实施例中的多个信号都对应有第一电位和第二电位，第一电位和第二电位仅代表该信号的电位有2个状态量，不代表全文中第一电位或第二电位具有特定的数值。在本公开实施例中，以第一电位相对于第二电位为高电位为例进行说明。
图1是本公开实施例提供的一种移位寄存器单元的结构示意图，如图1所示，该移位寄存器单元可以包括：输入子电路10、控制子电路20、降噪子电路30和输出子电路40。
该输入子电路10分别与输入信号端IN、第一控制信号端CN和上拉节点PU连接，用于在该输入信号端IN输出的输入信号为第一电位时，向该上拉节点PU输出来自该第一控制信号端CN的第一控制信号，该第一控制信号为第一电位，因此可以对该上拉节点PU进行充电。
此外，该输入子电路10还可以与复位信号端RST和第二控制信号端CNB连接，用于在该复位信号端RST输出的复位信号为第一电位时，向该上拉节点PU输出来自该第二控制信号端CNB的第二控制信号，该第二控制信号为第二电位，因此可以对该上拉节点PU进行复位。其中，所述第一控制信号为第一电位，所述第二控制信号为第二电位。
该控制子电路20分别与该上拉节点PU、第一时钟信号端CK、第二时钟信号端CKB、第一电源信号端VGH、第二电源信号端VGL和下拉节点PD连接，用于在该上拉节点PU为第一电位时，向该下拉节点PD输出来自该第二电源信号端VGL的第二电源信号，以及在该第二时钟信号端CKB输出的第二时钟信号为第二电位，且该第一时钟信号端CK输出的第一时钟信号为第一电位时，向该下拉节点PD输出来自该第一电源信号端VGH的第一电源信号，其中该第一电源信号为第一电位，该第二电源信号为第二电位。
该降噪子电路30分别与该下拉节点PD、该第二时钟信号端CKB、该第二电源信号端VGL和输出端OUT连接，用于在该下拉节点PD或该第二时 钟信号端CKB为第一电位时，向该输出端OUT输出该第二电源信号，从而对该输出端OUT进行降噪。其中，该第一时钟信号和该第二时钟信号的频率相同，相位相反(即，相位相差180°)。
此外，所述降噪子电路30还可以与所述上拉节点PU连接，用于在所述下拉节点PD为第一电位时，向所述上拉节点PU输出所述第二电源信号。
该输出子电路40分别与该第一时钟信号端CK、该上拉节点PU和该输出端OUT连接，用于在该上拉节点PU为第一电位时，向该输出端OUT输出该第一时钟信号，该输出子电路40输出的第一时钟信号即为用于驱动一行像素单元的栅极驱动信号。
图2是本公开实施例提供的一种移位寄存器单元的结构示意图，参考图2，该控制子电路20具体可以包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5。
其中，第一晶体管T1的栅极与第二时钟信号端CKB连接，第一极与第一电源信号端VGH连接，第二极与第一节点P1连接。
第二晶体管T2的栅极与该第一节点P1连接，第一极与第一时钟信号端CK连接，第二极与第三晶体管T3的栅极连接；该第三晶体管T3的第一极与该第一电源信号端VGH连接，第二极与下拉节点PD连接。
第四晶体管T4的栅极与该上拉节点PU连接，第一极与该第二时钟信号端CKB连接，第二极与该第一节点P1连接。
第五晶体管T5的栅极与该上拉节点PU连接，第一极与该第二电源信号端VGL连接，第二极与该下拉节点PD连接。
在该上拉节点PU为第一电位时，该控制子电路20的第四晶体管T4和第五晶体管T5导通，向该下拉节点PD输出来自该第二电源信号端VGL的第二电源信号；以及在该第二时钟信号端CKB输出的第二时钟信号为第二电位、且该第一时钟信号端CK输出的第一时钟信号为第一电位时，该第一节点P1为第一电位，该控制子电路20的第二晶体管T2和第三晶体管T3导通，向该下拉节点PD输出来自该第一电源信号端VGH的第一电源信号，其中该第一电源信号为第一电位，该第二电源信号为第二电位。
根据本公开实施例，该降噪子电路30可以包括：第六晶体管T6、第七晶体管T7和第八晶体管T8。
其中，第六晶体管T6的栅极与该下拉节点PD连接，第一极与该第二电源信号端VGL连接，第二极与该上拉节点PU连接。
第七晶体管T7的栅极与该下拉节点PD连接，第一极与该第二电源信号端VGL连接，第二极与该输出端OUT连接。
第八晶体管T8的栅极与该第二时钟信号端CKB连接，第一极与该第二电源信号端VGL连接，第二极与该输出端OUT连接。
在该下拉节点PD为第一电位时，该降噪子电路30向该上拉节点PU和该输出端OUT输出该第二电源信号，从而对该上拉节点PU和该输出端OUT进行降噪。或者，在该第二时钟信号端CKB为第一电位时，该降噪子电路30向该输出端OUT输出该第二电源信号，从而对该输出端OUT进行降噪。
进一步的，根据本公开实施例，参考图2，该输入子电路10可以包括：第九晶体管T9和第十晶体管T10；该输出子电路40可以包括：第十一晶体管T11和电容器C1。
该第九晶体管T9的栅极与该输入信号端IN连接，第一极与该第一控制信号端CN连接，第二极与该上拉节点PU连接。
该第十晶体管T10的栅极与该复位信号端RST连接，第一极与该第二控制信号端CNB连接，第二极与该上拉节点PU连接。
在该输入信号端IN输出的输入信号为第一电位时，该输入子电路10向该上拉节点PU输出来自该第一控制信号端CN的第一控制信号，因此可以对该上拉节点PU进行充电。
在该复位信号端RST输出的复位信号为第一电位时，该输入子电路10向该上拉节点PU输出来自该第二控制信号端CNB的第二控制信号，因此可以对该上拉节点PU进行复位。
该第十一晶体管T11的栅极与该上拉节点PU连接，第一极与该第一时钟信号端CK连接，第二极与该输出端OUT连接。
该电容器C1的一端与该上拉节点PU连接，另一端与该输出端OUT连接。
在该上拉节点PU为第一电位时，该输出子电路40向该输出端OUT输出该第一时钟信号作为驱动一行像素电路的栅极驱动信号。
综上所述，本公开实施例提供了一种移位寄存器单元，该移位寄存器单 元中包括控制子电路和降噪子电路，该控制子电路可以在第一时钟信号为第一电位时，控制下拉节点的电位为第一电位；而该降噪子电路则可以在下拉节点或者第二时钟信号为第一电位时，控制输出端的电位为第二电位。由于该第一时钟信号和第二时钟信号频率相同相位相反，因此该控制子电路和降噪子电路可以在移位寄存器单元的输出阶段之后，控制输出端的电位持续为第二电位，从而保证对该输出端的有效降噪。此外，本公开实施例提供的移位寄存器单元中仅应用了一个电容器，电路结构较为简单，占用面积较小，易于实现显示面板的窄边框设计。
本公开实施例提供了一种移位寄存器单元的驱动方法，该方法可以用于驱动如图1或图2所示的移位寄存器单元，参考图1，该移位寄存器单元包括：输入子电路10、控制子电路20、降噪子电路30和输出子电路40；参考图3，该方法可以包括：
步骤101、充电阶段，输入信号端IN输出的输入信号为第一电位，该输入子电路10在该输入信号的控制下，向上拉节点PU输出来自第一控制信号端CN的第一控制信号，该第一控制信号为第一电位，对该上拉节点PU进行充电。同时，在该充电阶段中，控制子电路20在上拉节点PU的控制下，向下拉节点PD输出来自第二电源信号端VGL的第二电源信号。
步骤102、输出阶段，第一时钟信号端CK输出的第一时钟信号为第一电位，该上拉节点PU保持第一电位，该输出子电路40在该上拉节点PU的控制下，向该输出端OUT输出该第一时钟信号。同时，在该输出阶段，该控制子电路20在上拉节点PU的控制下，向下拉节点PD输出来自第二电源信号端VGL的第二电源信号。
降噪步骤103和104、输出降噪阶段，该第一时钟信号和该第二时钟信号交替为第一电位，在该第一时钟信号为第一电位时，该控制子电路20向该下拉节点PD输出来自第一电源信号端VGH的第一电源信号，该第一电源信号处于第一电位，该降噪子电路30在该下拉节点PD的控制下，分别向该上拉节点PU和该输出端OUT输出该第二电源信号；在该第二时钟信号为第一电位时，该降噪子电路30在该第二时钟信号的控制下，向该输出端OUT输出该第二电源信号。
此外，根据本公开实施例，在所述输入子电路10还与复位信号端连接的 情况下，在该输出降噪阶段的步骤103中(该阶段也可以被称为第一输出降噪阶段或复位阶段)，在复位信号端RST输出的复位信号为第一电位且第二时钟信号端CKB输出的第二时钟信号为第一电位时，该输入子电路10还在该复位信号的控制下，向该上拉节点PU输出来自第二控制信号端CNB的第二控制信号。此时，该降噪子电路30在该第二时钟信号的控制下，向该输出端OUT输出来自第二电源信号端VGL的第二电源信号，该第二控制信号和该第二电源信号均为第二电位。在该输出降噪阶段的步骤104(该阶段也可以被称为第二输出降噪阶段)中，该第一时钟信号和该第二时钟信号交替为第一电位，且所述复位信号端RST输出的复位信号为第二电位。
图4是本公开实施例提供的一种移位寄存器单元的驱动过程的时序图，以图2所示的移位寄存器单元为例，详细介绍本公开实施例提供的移位寄存器单元的驱动方法。应了解，尽管在下面的描述中具体描述了输入子电路10与复位信号输入端RST连接的情况，然而根据实际需要，可以省略该复位信号输入端RST及其相应的操作。
结合图2和图4，在充电阶段t1中，输入信号端IN输出的输入信号，以及第二时钟信号端CKB输出的第二时钟信号为第一电位，复位信号端RST输出的复位信号以及第一时钟信号端CK输出的第一时钟信号为第二电位。此时，第九晶体管T9、第一晶体管T1和第八晶体管T8导通，第一控制信号端IN通过第九晶体管T9向电容器C1的一端输出第一控制信号，从图4可以看出，该第一控制信号的电位与第一电源信号端VGH的电位相同，均为高电位，因此可以对该电容器C1充电，将上拉节点PU的电位拉高。此时，第十一晶体管T11、第四晶体管T4和第五晶体管T5导通，第一时钟信号端CK向输出端OUT输出第一时钟信号，将该输出端OUT的电位拉低；第二电源信号端VGL通过第五晶体管T5向下拉节点PD输出第二电源信号，将该下拉节点PD的电位拉低，从而使得第六晶体管T6和第七晶体管T7截止，避免对上拉节点PU的电位造成影响。
此外，由于第一晶体管T1和第四晶体管T4导通，第二时钟信号和第一电源信号驱动第二晶体管T2导通，第一时钟信号端CK向第三晶体管T3的栅极输出处于第二电位的第一时钟信号，该第三晶体管T3截止，因此第一电源信号端VGH不会对下拉节点PD的电位产生影响。
在输出阶段t2中，输入信号、复位信号和第二时钟信号均处于第二电位，第一晶体管T1、第八至第十晶体管均处于截止状态；第一时钟信号端CK输出的第一时钟信号为第一电位，该上拉节点PU没有放电路径保持为第一电位，第一时钟信号端CK向该输出端OUT输出该第一时钟信号。此外，由于第四晶体管T4和第五晶体管T5保持导通状态，下拉节点PD仍然保持为第二电位，第二时钟信号端CKB通过第四晶体管T4向第一节点P1输出处于第二电位的第二时钟信号，该第二晶体管T2截止，第一时钟信号端CK输出的处于第一电位的第一时钟信号无法通过第二晶体管T2作用到第三晶体管T3的栅极，第三晶体管T3仍然保持上一阶段的截止状态，从而使得第六晶体管T6和第七晶体管T7也依旧保持截止状态，避免对上拉节点PU和输出端OUT的电位造成影响。
在第一输出降噪阶段t3(复位阶段t3)中，复位信号端RST和第二时钟信号端CKB输出的信号处于第一电位，输入信号端IN和第一时钟信号端CK输出的信号为第二电位，第九晶体管T9截止，第一晶体管T1、第八晶体管T8和第十晶体管T10导通。第二控制信号端CNB向上拉节点PU输出第二控制信号，从图4可以看出，该第二控制信号的电位与第二电源信号端VGL的电位相等，均为低电位，因此可以对该上拉节点PU进行复位，此时第四晶体管T4和第五晶体管T5截止。虽然第一晶体管T1导通，第一电源信号端VGH驱动第二晶体管T2导通，但由于此时第一时钟信号端CK输出的第一时钟信号为第二电位，第三晶体管T3仍然处于截止状态。由于第八晶体管T8导通，第二时钟信号端CKB向输出端OUT输出处于第二电位的第二时钟信号，从而对该输出端OUT进行复位。
在之后的第二输出降噪阶段t4中，复位信号端RST输出的复位信号保持第二电位，该第一时钟信号端CK输出的第一时钟信号和该第二时钟信号端CKB输出的第二时钟信号交替为第一电位。第二晶体管T2的栅极(即第一节点P1)由于没有低电平下拉且利用本身的栅源电容保持了上一阶段的状态，因此会一直保持导通状态，该第一时钟信号端CK向该第三晶体管T3的栅极持续输出第一时钟信号。在该第一时钟信号为第一电位时，该第三晶体管T3导通，该第一电源信号端VGH向该下拉节点PD输出该第一电源信号，该第六晶体管T6和该第七晶体管T7导通，第二电源信号端VGL分别向上拉节 点PU和输出端OUT输出该第二电源信号；在该第二时钟信号为第一电位时，该第八晶体管T8导通，该第二电源信号端VGL向该输出端OUT输出该第二电源信号。
由于在该第二输出降噪阶段中，两个时钟信号端CK和CKB输出的时钟信号频率相同且相位相反，因此该降噪子电路30中的各个晶体管可以持续对输出端OUT进行降噪，有效改善了该移位寄存器单元的降噪性能。
需要说明的是，在上述实施例中，均是以各个晶体管为N型晶体管，且第一电位相对于该第二电位为高电位为例进行的说明。当然，如图5所示，该各个晶体管还可以采用P型晶体管，当该各个晶体管采用P型晶体管时，各晶体管之间的连接关系可以保持不变，但由于第一电源信号端VGH输出的第一电源信号为高电平，第二电源信号端VGL输出的第二电源信号为低电平，因此对比图2和图5可以看出，仅该两个信号端的位置需要互换。此外，当该各个晶体管采用P型晶体管时，该第一电位相对于该第二电位可以为低电位，各个信号端的时序图可以如图6所示。从图6中可以看出，各个信号端的电位变化可以与图4所示的电位变化相反(即二者的相位差为180度)。
综上所述，本公开提供了一种移位寄存器单元的驱动方法，在输出降噪阶段，当第一时钟信号为第一电位时，该控制子电路可控制下拉节点的电位为第一电位，该降噪子电路可以在下拉节点的控制下，对上拉节点和输出端进行降噪；而当第二时钟信号为第一电位时，该降噪子电路可以直接对输出端进行降噪。由于该第一时钟信号和第二时钟信号频率相同相位相反，因此可以使得移位寄存器单元输出端的电位在输出阶段之后持续为第二电位，从而保证对该输出端的有效降噪。
图7是本公开实施例提供的一种栅极驱动电路的结构示意图，参考图7，该栅极驱动电路可以包括至少两个级联的移位寄存器单元00，其中每个移位寄存器单元可以为如图1、图2或者图5所示的移位寄存器单元。
从图7中可以看出，每一级移位寄存器单元的输入信号端IN输入与上一级移位寄存器单元的输出端OUT相连；每一级移位寄存器单元的复位信号端RST与下一级移位寄存器单元的输出端OUT相连，例如第n级移位寄存器单元的输入信号端IN与第n-1级移位寄存器单元的输出端OUT(n-1)相连，第n级移位寄存器单元的复位信号端RST与第n+1级移位寄存器单元的输出 端OUT(n+1)相连。从图7中还可以看出，该栅极驱动电路中，第一极移位寄存器单元的输入信号端IN，以及最后一级移位寄存器单元的复位信号端RST可以与帧同步信号端STV端相连。此外，通过对该第一控制信号端CN和第二控制信号端CNB的控制，可以使得该栅极驱动电路中的各个移位寄存器单元实现对显示装置的正反双向扫描。
例如，当第一控制信号端CN输出处于第一电位的第一控制信号，第二控制信号端CNB输出处于第二电位的第二控制信号时，可以使得该栅极驱动电路中的各个移位寄存器单元从第一级移位寄存器单元开始依次启动，由此可以实现对显示装置的正向扫描。当第一控制信号端CN输出处于第二电位的第一控制信号，第二控制信号端CNB输出处于第一电位的第二控制信号时，可以使得该栅极驱动电路中的各个移位寄存器单元从最后一级移位寄存器单元开始依次启动，由此可以实现对显示装置的反向扫描。
本公开实施例还提供一种显示装置，该显示装置可以包括如图7所示的栅极驱动电路。该显示装置可以为：液晶面板、电子纸、OLED面板、AMOLED面板、低温多晶硅(英文：Low Temperature Poly-silicon；简称：LTPS)显示面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，前述描述的移位寄存器单元和各子电路的具体工作过程，可以参考上述方法实施例中的对应过程，在此不再赘述。
以上所述仅为本公开的较佳实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (13)

  1. 一种移位寄存器单元，包括：
    输入子电路，其分别与输入信号端、第一控制信号端、和上拉节点连接，用于在所述输入信号端输出的输入信号为第一电位时，向所述上拉节点输出来自所述第一控制信号端的第一控制信号；
    控制子电路，其分别与所述上拉节点、第一时钟信号端、第二时钟信号端、第一电源信号端、第二电源信号端和下拉节点连接，用于在所述上拉节点为第一电位时，向所述下拉节点输出来自所述第二电源信号端的第二电源信号，以及在所述第一时钟信号端输出的第一时钟信号为第一电位时，向所述下拉节点输出来自所述第一电源信号端的第一电源信号；
    降噪子电路，其分别与所述下拉节点、所述第二时钟信号端、所述第二电源信号端和输出端连接，用于在所述下拉节点或所述第二时钟信号端输出的第二时钟信号为第一电位时，向所述输出端输出所述第二电源信号；
    输出子电路，其分别与所述第一时钟信号端、所述上拉节点和所述输出端连接，用于在所述上拉节点为第一电位时，向所述输出端输出所述第一时钟信号，
    其中所述第一电源信号为第一电位，所述第二电源信号为第二电位，所述第一时钟信号和所述第二时钟信号的频率相同且相位相反。
  2. 根据权利要求1所述的移位寄存器单元，其中，
    所述输入子电路还与复位信号端和第二控制信号端连接，用于在所述复位信号端输出的复位信号为第一电位时，向所述上拉节点输出来自所述第二控制信号端的第二控制信号，
    其中所述第一控制信号为第一电位，所述第二控制信号为第二电位。
  3. 根据权利要求1所述的移位寄存器单元，其中，
    所述降噪子电路还与所述上拉节点连接，用于在所述下拉节点为第一电位时，向所述上拉节点输出所述第二电源信号。
  4. 根据权利要求1所述的移位寄存器单元，其中，所述控制子电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管和第五晶体管；
    所述第一晶体管的栅极与所述第二时钟信号端连接，第一极与所述第一电源信号端连接，第二极与第一节点连接；
    所述第二晶体管的栅极与所述第一节点连接，第一极与所述第一时钟信号端连接，第二极与所述第三晶体管的栅极连接；
    所述第三晶体管的第一极与所述第一电源信号端连接，第二极与所述下拉节点连接；
    所述第四晶体管的栅极与所述上拉节点连接，第一极与所述第二时钟信号端连接，第二极与所述第一节点连接；
    所述第五晶体管的栅极与所述上拉节点连接，第一极与所述第二电源信号端连接，第二极与所述下拉节点连接。
  5. 根据权利要求3所述的移位寄存器单元，其中，所述降噪子电路包括：第六晶体管、第七晶体管和第八晶体管；
    所述第六晶体管的栅极与所述下拉节点连接，第一极与所述第二电源信号端连接，第二极与所述上拉节点连接；
    所述第七晶体管的栅极与所述下拉节点连接，第一极与所述第二电源信号端连接，第二极与所述输出端连接；
    所述第八晶体管的栅极与所述第二时钟信号端连接，第一极与所述第二电源信号端连接，第二极与所述输出端连接。
  6. 根据权利要求2所述的移位寄存器单元，其中，所述输入子电路包括：第九晶体管和第十晶体管；
    所述第九晶体管的栅极与所述输入信号端连接，第一极与所述第一控制信号端连接，第二极与所述上拉节点连接；
    所述第十晶体管的栅极与所述复位信号端连接，第一极与所述第二控制信号端连接，第二极与所述上拉节点连接。
  7. 根据权利要求1至3任一所述的移位寄存器单元，其特征在于，所 述输出子电路包括：第十一晶体管和电容器；
    所述第十一晶体管的栅极与所述上拉节点连接，第一极与所述第一时钟信号端连接，第二极与所述输出端连接；
    所述电容器的一端与所述上拉节点连接，另一端与所述输出端连接。
  8. 一种移位寄存器单元的驱动方法，其特征在于，所述移位寄存器单元包括：输入子电路、控制子电路、降噪子电路和输出子电路；所述方法包括：
    充电阶段，输入信号端输出的输入信号为第一电位，所述输入子电路在所述输入信号的控制下，向上拉节点输出来自第一控制信号端的第一控制信号，所述第一控制信号为第一电位，对所述上拉节点进行充电；
    输出阶段，第一时钟信号端输出的第一时钟信号为第一电位，所述上拉节点保持第一电位，所述输出子电路在所述上拉节点的控制下，向输出端输出所述第一时钟信号；
    输出降噪阶段，所述第一时钟信号和所述第二时钟信号交替为第一电位，在所述第一时钟信号为第一电位时，所述控制子电路向所述下拉节点输出来自第一电源信号端的第一电源信号，所述第一电源信号处于第一电位，所述降噪子电路在所述下拉节点的控制下，向所述输出端输出所述第二电源信号；在所述第二时钟信号为第一电位时，所述降噪子电路在所述第二时钟信号的控制下，向所述输出端输出所述第二电源信号。
  9. 根据权利要求8所述的方法，其中，在所述输出降噪阶段中，在所述复位信号端输出的复位信号为第一电位且所述第二时钟信号端输出的第二时钟信号为第一电位时，所述输入子电路在所述复位信号的控制下，向所述上拉节点输出来自第二控制信号端的第二控制信号，所述降噪子电路在所述第二时钟信号的控制下，向所述输出端输出来自第二电源信号端的第二电源信号，所述第二控制信号和所述第二电源信号均为第二电位。
  10. 根据权利要求8所述的方法，其中，所述控制子电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管和第五晶体管；所述降噪子电 路，包括：第六晶体管、第七晶体管和第八晶体管；
    所述输出降噪阶段中，所述第一时钟信号和所述第二时钟信号交替为第一电位，所述第二晶体管保持导通状态，所述第一时钟信号端向所述第三晶体管的栅极输出所述第一时钟信号，在所述第一时钟信号为第一电位时，所述第三晶体管导通，所述第一电源信号端向所述下拉节点输出所述第一电源信号，所述第六晶体管和所述第七晶体管导通，所述第二电源信号端分别向所述上拉节点和所述输出端输出所述第二电源信号；在所述第二时钟信号为第一电位时，所述第八晶体管导通，所述第二电源信号端向所述输出端输出所述第二电源信号。
  11. 根据权利要求10所述的方法，其中，
    所述晶体管均为N型晶体管，所述第一电位相对于所述第二电位为高电位。
  12. 一种栅极驱动电路，包括：
    至少两个级联的如权利要求1至7任一所述的移位寄存器单元。
  13. 一种显示装置，包括：如权利要求12所述的栅极驱动电路。
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