WO2018059159A1 - 移位寄存器单元、驱动方法、栅极驱动电路及显示装置 - Google Patents

移位寄存器单元、驱动方法、栅极驱动电路及显示装置 Download PDF

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Publication number
WO2018059159A1
WO2018059159A1 PCT/CN2017/098304 CN2017098304W WO2018059159A1 WO 2018059159 A1 WO2018059159 A1 WO 2018059159A1 CN 2017098304 W CN2017098304 W CN 2017098304W WO 2018059159 A1 WO2018059159 A1 WO 2018059159A1
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Prior art keywords
output
circuit
control
clock signal
transistor
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PCT/CN2017/098304
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English (en)
French (fr)
Inventor
李艳
时凌云
孙伟
谢晓波
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京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US15/879,724 priority Critical patent/US10453369B2/en
Publication of WO2018059159A1 publication Critical patent/WO2018059159A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • Embodiments of the present disclosure relate to a shift register unit, a driving method, a gate driving circuit, and a display device.
  • the gate driving circuit (also referred to as a shift register) includes a plurality of cascaded shift register units, wherein each shift register unit is used to drive a row of pixel units, and the pixel unit of the display device is implemented by the plurality of shift register units
  • the progressive scan drive to display the image.
  • the gate driving circuit can scan the pixels of each row in the display device once in one frame time, wherein the charging time for each row of pixel cells is determined by the frequency of the clock signal.
  • the gate driving circuit drives the pixel unit, the charging time for each row of pixel units is also fixed.
  • the driving method is relatively simple.
  • an embodiment of the present disclosure provides a shift register unit, where the shift register unit includes:
  • the clock control circuit is respectively connected to a control signal end, a first clock signal end, a second clock signal end, a third clock signal end, the output control circuit and the output circuit, and the clock control circuit is configured to be Controlling a signal from the control signal terminal and a third clock signal from the third clock signal terminal, alternately outputting a first clock signal from the first clock signal terminal and from the second to the output circuit a second clock signal of the clock signal end, and alternately outputting the inverted signal of the first clock signal and the second clock signal to the output control circuit An inverted signal, wherein the first clock signal, the second clock signal, and the third clock signal have the same frequency and different phases;
  • the output control circuit is respectively connected to the clock control circuit, the pull-up node and the output end, and is configured to control a potential of the pull-up node and the output end;
  • the output circuit is respectively connected to the clock control circuit, the pull-up node and the output end, and configured to output, from the output of the pull-off node, the output from the clock control circuit signal.
  • an embodiment of the present disclosure provides a driving method of a shift register unit, where the shift register unit includes: a clock control circuit, an output control circuit, and an output circuit, and the method includes:
  • the control signal outputted by the control signal terminal is a first potential, and the first clock signal from the first clock signal terminal is output to the output circuit through the clock control circuit, and is output to the output control circuit.
  • the control signal outputted by the control signal terminal is a second potential
  • the third clock signal terminal outputs a third clock signal
  • the first clock signal is alternately outputted to the output circuit by the clock control circuit.
  • a second clock signal from the second clock signal terminal, and alternately outputting the inverted signal of the first clock signal and the inverted signal of the second clock signal to the output control circuit;
  • the first clock signal, the second clock signal, and the third clock signal have the same frequency and different phases.
  • an embodiment of the present disclosure provides a gate driving circuit, where the gate driving circuit includes:
  • each shift register unit is a shift register unit as described in the first aspect.
  • an embodiment of the present disclosure provides a display device, comprising: the gate driving circuit according to the third aspect.
  • FIG. 1 is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 2 is a second schematic structural diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a circuit structure of a shift register unit according to an embodiment of the present disclosure
  • FIG. 4 is a second schematic structural diagram of a circuit of a shift register unit according to an embodiment of the present disclosure
  • FIG. 5 is a flowchart of a driving method of a shift register unit according to an embodiment of the present disclosure
  • FIG. 6 is a timing diagram of signals in a shift register unit according to an embodiment of the present disclosure.
  • FIG. 7 is a second timing diagram of signals in a shift register unit according to an embodiment of the present disclosure.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other device having the same characteristics, and the transistors employed in the embodiments of the present disclosure are mainly switching transistors according to the functions in the circuit. Since the source and drain of the switching transistor used here are symmetrical, the source and the drain are interchangeable. In the disclosed embodiment, the source is referred to as a first pole, the drain is referred to as a second pole, and the gate is referred to as a third pole. According to the form in the drawing, the middle end of the transistor is the gate, the signal input end is the source, and the output end is the drain.
  • the switching transistor used in the embodiments of the present disclosure may include a P-type switching transistor and an N-type switching transistor.
  • the P-type switching transistor is turned on when the gate is at a low level, and is turned off when the gate is at a high level.
  • the switching transistor is turned on when the gate is at a high level and turned off when the gate is at a low level.
  • the plurality of signals in various embodiments of the present disclosure correspond to a first potential and a second potential.
  • the first potential and the second potential represent only the electrical energy of the signal
  • the bit has two state quantities, and does not mean that the first potential or the second potential in the full text has a specific value, that is, the potential values of the first potential (or the second potential) of each signal may be the same or different.
  • first clock signal, the second clock signal, and the third clock signal in the embodiment of the present disclosure have the same frequency and different phases.
  • the duty ratios of the first clock signal, the second clock signal, and the third clock signal may both be one-half; and the phase difference between the first clock signal and the second clock signal is 180 degrees, the first clock The phase difference between the signal and the third clock signal is 90 degrees.
  • Embodiments of the present disclosure provide a shift register unit, a driving method, a gate driving circuit, and a display device.
  • the shift register unit includes an output control circuit and an output circuit, and further includes a clock control circuit.
  • clock control circuit Through the clock control circuit, clock signals of different frequencies or different duty ratios can be respectively output to the output control circuit and the output circuit, so that the output circuit can output driving signals of different frequencies or different duty ratios to the pixel unit through the output end.
  • the charging time of each row of pixel units can be adjusted, thereby enriching the driving mode of the gate driving circuit to the display device, and improving the flexibility of driving.
  • FIG. 1 is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure. As shown in FIG. 1 , the shift register unit includes a clock control circuit 10, an output control circuit 20, and an output circuit 30.
  • the clock control circuit 10 is configured to output to the output circuit 30 from the first clock signal terminal under control of a control signal from the control signal terminal EN and a third clock signal from the third clock signal terminal CK3.
  • a first clock signal of CK1 and outputting an inverted signal of the first clock signal to the output control circuit 20; or alternatively outputting the first clock signal and the second clock signal terminal CK2 to the output circuit 30
  • a clock signal, and the output control circuit 20 alternately outputs an inverted signal of the first clock signal and an inverted signal of the second clock signal.
  • the first clock signal, the second clock signal, and the third clock signal have the same frequency and different phases.
  • the output control circuit 20 and the clock control circuit 10 the input signal terminal STV, the reset signal terminal RST, the second power signal terminal VGL, the third power signal terminal CN, the fourth power signal terminal CNB, the pull-up node PU, and the output The terminal OUT is connected.
  • the output control circuit 20 is configured to control the potential of the pull-up node PU and the output terminal OUT.
  • the output circuit 30 and the clock control respectively The circuit 10, the pull-up node PU and the output terminal OUT are connected, and are configured to output a signal from the clock control circuit 10 to the output terminal OUT under the control of the pull-up node PU.
  • the embodiments of the present disclosure provide a shift register unit that includes an output control circuit and an output circuit, and further includes a clock control circuit.
  • the clock control circuit can output a first clock signal to the output circuit or alternately output the first clock signal and the second clock signal to the output circuit, so that the output circuit can be under the control of the signal output by the clock control circuit.
  • the driving signals of different frequencies or different duty ratios are output to the pixel unit, thereby adjusting the charging time of each row of pixel units, thereby enriching the driving mode of the gate driving circuit to the display device, and improving the driving flexibility.
  • FIG. 2 is another schematic structural diagram of a shift register unit according to an embodiment of the present disclosure.
  • the clock control circuit 10 may include a first control sub-circuit 101, a second control sub-circuit 102, and an inverting sub-circuit 103.
  • the first control sub-circuit 101 is connected to the control signal terminal EN, the first power signal terminal VGH, the third clock signal terminal CK3 and the second control sub-circuit 102, respectively.
  • the first control sub-circuit 101 is configured to output a first power signal from the first power signal terminal VGH to the second control sub-circuit 102 under the control of the control signal, or from the third clock signal terminal CK3 The third clock signal.
  • the second control sub-circuit 102 is connected to the first control sub-circuit 101, the first clock signal terminal CK1, the second clock signal terminal CK2, the inverting sub-circuit 103, and the output circuit 30, respectively.
  • the second control sub-circuit 102 is configured to output the first clock signal to the inverting sub-circuit 103 and the output circuit 30 respectively under the control of the first power signal; or, in the third clock signal Under control, the first clock signal and the second clock signal are alternately output to the inverter sub-circuit 103, and the first clock signal and the second clock signal are alternately output to the output circuit 30.
  • the inverter sub-circuit 103 is connected to the second control sub-circuit 102 and the output control circuit 20, and is configured to invert the signal output from the second control sub-circuit 102 and output the signal to the output control circuit 20.
  • FIG. 3 is a schematic diagram of a circuit structure of a shift register unit according to an embodiment of the present disclosure.
  • the first control sub-circuit 101 may include a first transistor M1 and a second transistor M2.
  • the first transistor M1 and the second transistor M2 have opposite polarities.
  • the first transistor M1 may be a P-type transistor
  • the second transistor M2 may be an N-type transistor
  • the first transistor M1 may be an N-type transistor
  • the second transistor M2 may be a P-type transistor.
  • a gate of the first transistor M1 is connected to the control signal terminal EN, a first pole of the first transistor M1 is connected to the first power signal terminal VGH, and a second pole of the first transistor M1 and the second controller Circuitry 102 is connected.
  • a gate of the second transistor M2 is connected to the control signal terminal EN, a first pole of the second transistor M2 is connected to the third clock signal terminal CK3, and a second pole of the second transistor M2 is opposite to the second controller.
  • Circuitry 102 is connected.
  • the inverter sub-circuit 103 includes a first inverter F1, and an input end of the first inverter F1 is connected to the second control sub-circuit 102, and a signal output end of the first inverter F1. It is connected to the output control circuit 20.
  • the second control sub-circuit 102 may include a third transistor M3 and a fourth transistor M4.
  • the third transistor M3 and the fourth transistor M4 have opposite polarities.
  • the third transistor M3 may be an N-type transistor
  • the fourth transistor M4 may be a P-type transistor.
  • the third transistor M3 may be a P-type transistor
  • the fourth transistor M4 may be an N-type transistor.
  • the gate of the third transistor M3 is connected to the first control sub-circuit 101. As shown in FIG. 3, the gate of the third transistor M3 is respectively connected to the second pole of the first transistor M1 and the second pole of the second transistor M2, and the first pole of the third transistor M3 and the first clock
  • the signal terminal CK1 is connected, and the second electrode of the third transistor M3 is connected to the inverter sub-circuit 103 and the output circuit 30, respectively.
  • the gate of the fourth transistor M4 is connected to the first control sub-circuit 101. As shown in FIG. 3, the gate of the fourth transistor M4 is respectively connected to the second pole of the first transistor M1 and the second pole of the second transistor M2, and the first pole of the fourth transistor M4 and the second clock
  • the signal terminal CK2 is connected, and the second electrode of the fourth transistor M4 is connected to the inverter sub-circuit 103 and the output circuit 30, respectively.
  • the second control sub-circuit 102 may further include: a second inverter F2, a first transmission gate TG1, a third inverter F3, and a Two transmission gates TG2.
  • An input end of the second inverter F2 is connected to the first control sub-circuit 101, for example, the first An input terminal of the second inverter F2 is connected to an output terminal of the first control sub-circuit 101.
  • the signal output end of the second inverter F2 is connected to the first control end of the first transmission gate TG1; the second control end of the first transmission gate TG1 is connected to the first control sub-circuit 101, the first transmission
  • the input end of the gate TG1 is connected to the first clock signal terminal CK1, and the signal output terminal of the first transmission gate TG1 is connected to the inverter sub-circuit 103 and the output circuit 30, respectively.
  • An input end of the third inverter F3 is connected to the first control sub-circuit 101.
  • an input end of the third inverter F3 is connected to an output end of the first control sub-circuit 101.
  • the signal output end of the third inverter F3 is connected to the second control end of the second transmission gate TG2; the first control end of the second transmission gate TG2 is connected to the first control sub-circuit 101, the second transmission
  • the input terminal of the gate TG2 is connected to the second clock signal terminal CK2, and the signal output terminal of the second transmission gate TG2 is connected to the inverter sub-circuit 103 and the output circuit 30, respectively.
  • the duty ratios of the first clock signal, the second clock signal, and the third clock signal may both be one-half, and the first clock signal and the second clock signal are The phase difference may be 180 degrees, and the phase difference between the first clock signal and the third clock signal may be 90 degrees.
  • the output control circuit 20 in the shift register unit may include: a first output control transistor M5, a second output control transistor M6, a third output control transistor M7, The fourth output control transistor M8, the fifth output control transistor M9, the sixth output control transistor M10, and the seventh output control transistor M11.
  • the output circuit 30 can include an output transistor M12 and a capacitor C.
  • the gate of the first output control transistor M5 is connected to the input signal terminal STV, and the first electrode of the first output control transistor M5 is connected to the third power signal terminal CN, and the first output control transistor M5 is The two poles are connected to the pull-up node PU.
  • the gate of the second output control transistor M6 is connected to the reset signal terminal RST, the first pole of the second output control transistor M6 is connected to the fourth power signal terminal CNB, and the second output controls the second pole of the transistor M6. Connected to the pull-up node PU.
  • the gate of the third output control transistor M7 is connected to the pull-up node PU, the first pole of the third output control transistor M7 is connected to the second power signal terminal VGL, and the third output controls the second pole of the transistor M7. Connected to the drop-down node PD.
  • the gate of the fourth output control transistor M8 is connected to the output terminal OUT, and the fourth output control
  • the first pole of the transistor M8 is connected to the second power signal terminal VGL, and the second pole of the fourth output control transistor M8 is connected to the pull-down node PD.
  • the gate and the first pole of the fifth output control transistor M9 are connected to the clock control circuit 10 (for example, the first output terminal CKB_N of the clock control circuit 10), and the fifth output controls the second pole of the transistor M9 and the Pull down the node PD connection.
  • the gate of the sixth output control transistor M10 is connected to the pull-down node PD, the first pole of the sixth output control transistor M10 is connected to the second power signal terminal VGL, and the second output of the sixth output control transistor M10 is The pull-up node PU is connected.
  • the gate of the seventh output control transistor M11 is connected to the pull-down node PD, the first pole of the seventh output control transistor M11 is connected to the second power signal terminal VGL, and the second output of the seventh output control transistor M11 is The output terminal OUT is connected.
  • the gate of the output transistor M12 is connected to the pull-up node PU.
  • the first pole of the output transistor M12 is connected to the clock control circuit 10 (for example, the second output terminal CK_N of the clock control circuit 10).
  • the output transistor M12 is connected.
  • the second pole is connected to the output terminal OUT.
  • One end of the capacitor C is connected to the pull-up node PU, and the other end is connected to the output terminal OUT.
  • the embodiments of the present disclosure provide a shift register unit that includes an output control circuit and an output circuit, and further includes a clock control circuit.
  • the clock control circuit can output a first clock signal to the output circuit or alternately output the first clock signal and the second clock signal to the output circuit, so that the output circuit can be under the control of the signal output by the clock control circuit.
  • the driving signals of different frequencies or different duty ratios are output to the pixel unit, thereby adjusting the charging time of the shift register unit for each row of pixel units.
  • the frequency of the driving signal outputted by the output circuit When the frequency of the driving signal outputted by the output circuit is high, the charging time of each row of pixel units is short, and the display resolution of the display device is high at this time, and the high-definition display of the display device can be realized; when the driving signal output by the output circuit is output When the frequency is low, the charging time of each row of pixel units is long. At this time, the resolution of the display device is low, and the low power consumption display of the display device can be realized, thereby enriching the driving mode of the gate driving circuit to the display device. Increases the flexibility of the drive.
  • the first transistor M1 and the fourth transistor M4 are P-type transistors, and the remaining transistors (M2, M3, and M5-M12) are N-type transistors, and the second The description is made by taking an example in which the potential is high with respect to the first potential.
  • the first transistor M1 and the fourth transistor M4 may also be N-type transistors, and the rest The transistors (M2, M3, and M5-M12) may also be P-type transistors.
  • the second potential may be low relative to the first potential, and the potential change of the respective signal terminals may be as shown in FIG. 6 below. The potential changes are reversed (ie, the phase difference between the two is 180 degrees).
  • FIG. 5 is a flowchart of a method for driving a shift register unit according to an embodiment of the present disclosure.
  • the method may be applied to the shift register unit shown in any one of FIG. 1 to FIG. 4, as shown in FIG.
  • the shift register unit may include a clock control circuit 10, an output control circuit 20, and an output circuit 30.
  • the method can include:
  • Step 201 In the first driving mode, the control signal outputted by the control signal terminal EN is a first potential, and the first clock signal from the first clock signal terminal CK1 is output to the output circuit 30 through the clock control circuit 10, and The output control circuit 20 outputs an inverted signal of the first clock signal.
  • Step 202 In the second driving mode, the control signal outputted by the control signal terminal EN is the second potential, and the third clock signal terminal CK3 outputs the third clock signal, and the clock control circuit 10 alternately outputs the third signal to the output circuit 30.
  • a clock signal and a second clock signal from the second clock signal terminal CK2, and an output signal of the first clock signal and an inverted signal of the second clock signal are alternately output to the output control circuit 20.
  • the first clock signal, the second clock signal, and the third clock signal have the same frequency and different phases.
  • the second potential can be high relative to the first potential.
  • the embodiments of the present disclosure provide a driving method of a shift register unit including two driving modes (for example, the first driving mode and the second driving mode as described above).
  • the frequency of the signals output by the clock control circuit to the output circuit is different, so that the output circuit can output driving signals of different frequencies or different duty ratios to the pixel unit, thereby adjusting the shift register unit pair.
  • the charging time of the row pixel unit enriches the driving mode of the gate driving circuit to the display device, and the driving flexibility is improved.
  • the clock control circuit 10 may include a first control sub-circuit 101, a second control sub-circuit 102, and an inverting sub-circuit 103.
  • 6 is a timing diagram of a driving method according to an embodiment of the present disclosure.
  • the signal CK_N in FIG. 6 is a signal output by the second control sub-circuit 102 to the output circuit 30, and the signal CKB_N is the output of the inverting sub-circuit 103.
  • the signal output by the control circuit 20 is a timing diagram of a driving method according to an embodiment of the present disclosure.
  • the signal CK_N in FIG. 6 is a signal output by the second control sub-circuit 102 to the output circuit 30, and the signal CKB_N is the output of the inverting sub-circuit 103.
  • the signal output by the control circuit 20 is a timing diagram of a driving method according to an embodiment of the present disclosure.
  • the signal CK_N in FIG. 6 is a signal output by the second control sub-circuit
  • the control signal output by the control signal terminal EN The first control sub-circuit 101 outputs a first power signal from the first power signal terminal VGH to the second control sub-circuit 102, the first power signal is a second potential, and the second potential is opposite.
  • the first potential can be high.
  • the second control sub-circuit 102 outputs the first clock signal to the output circuit 30 and the inverting sub-circuit 103 respectively under the control of the first power signal, and the inverting sub-circuit 103 performs the first clock signal. After the inversion, it is output to the output control circuit 20. For example, it can be seen from FIG.
  • the signal CK_N output by the second control sub-circuit 102 to the output circuit 30 is the first clock signal output by the first clock signal terminal CK1.
  • the signal CKB_N output from the inverter sub-circuit 103 to the output control circuit 20 is opposite in phase to the signal CK_N.
  • the control signal outputted by the control signal terminal EN is the second potential
  • the first control sub-circuit 101 outputs the third clock signal from the third clock signal terminal CK3 to the second control sub-circuit 102.
  • the second control sub-circuit 102 outputs the first clock signal to the output circuit 30 and the inverting sub-circuit 103, respectively; when the third clock signal is at the first potential
  • the second control sub-circuit 102 outputs the second clock signal to the output circuit 30 and the inverting sub-circuit 103, respectively.
  • the inverter sub-circuit 103 inverts the signal output from the second control sub-circuit 102, and outputs the signal to the output control circuit 20.
  • the second control sub-circuit is output to the output circuit.
  • the signal CK_N is the first clock signal.
  • the signal CK_N output by the second control sub-circuit to the output circuit is the second clock signal, and the inverse sub-circuit is output to the output control circuit.
  • the signal CKB_N is opposite in phase to the signal CK_N.
  • the first control sub-circuit 101 includes: a first transistor M1 and a second transistor M2, the first transistor M1 and the second transistor M2 having opposite polarities;
  • the second control sub-circuit 102 includes a third transistor M3 and a fourth transistor M4, and the third transistor M3 and the fourth transistor M4 have opposite polarities.
  • the first transistor M1 and the fourth transistor M4 are P-type transistors
  • the second transistor M2 and the third transistor M3 are N-type transistors.
  • the control signal is the first potential
  • the first transistor M1 is turned on
  • the second transistor M2 is turned off
  • the first power signal terminal VGH is output to the second control sub-circuit 102.
  • the first power signal from the first power terminal VGH. Due to the first power source
  • the signal is at the second potential.
  • the third transistor M3 is turned on
  • the fourth transistor M4 is turned off
  • the first clock signal terminal CK1 outputs the first clock signal to the output circuit 30 and the inverting sub-circuit 103, respectively.
  • the inverter sub-circuit 103 inverts the first clock signal and outputs it to the output control circuit 20. Referring to FIG.
  • the waveform of the signal CK_N output by the second control sub-circuit is the same as the waveform of the first clock signal (ie, the signal output by the first clock signal terminal CK1).
  • the signal CKB_N output by the circuit is opposite to the phase of the first clock signal.
  • the control signal is the second potential
  • the first transistor M1 is turned off
  • the second transistor M2 is turned on
  • the third clock signal terminal CK3 is output to the second control sub-circuit 102.
  • Three clock signals When the third clock signal is at the second potential, the third transistor M3 is turned on, the fourth transistor M4 is turned off, and the first clock signal terminal CK1 outputs the first to the output circuit 30 and the inverting sub-circuit 103, respectively.
  • a clock signal For example, in FIG.
  • the third clock signal outputted by the third clock signal terminal CK3 is at the second potential
  • the waveform of the signal CK_N output by the second control sub-circuit is The waveform of the first clock signal is the same.
  • the third clock signal is at the first potential
  • the third transistor M3 is turned off
  • the fourth transistor M4 is turned on
  • the second clock signal terminal CK2 outputs the first to the output circuit 30 and the inverting sub-circuit 103, respectively.
  • Two clock signals For example, in FIG.
  • the third clock signal is at the first potential, and the waveform of the signal CK_N output by the second control sub-circuit is the same as the waveform of the second clock signal. Further, in the second driving mode T2, the signal CKB_N output by the inverting sub-circuit is opposite to the phase of the signal CK_N.
  • the first control sub-circuit 101 includes a first transistor M1 and a second transistor M2, and the first transistor M1 and the second transistor M2 have opposite polarities.
  • the second control sub-circuit 102 includes a second inverter F2, a first transmission gate TG1, a third inverter F3, and a second transmission gate TG2.
  • the control signal is the first potential
  • the first transistor M1 is turned on
  • the second transistor M2 is turned off
  • the first power signal terminal VGH is output to the second control sub-circuit 102.
  • the first power signal Since the first power supply signal is at the second potential, the second inverter F2 inverts the first power supply signal, and outputs the first control terminal to the first control terminal of the first transmission gate TG1.
  • TG1 is turned on;
  • the third inverter F3 inverts the first power signal, and outputs the second control terminal to the second control terminal of the second transmission gate TG2, the second transmission gate TG2 shut down.
  • the first transmission gate TG1 Since the first transmission gate TG1 is turned on, the first clock signal terminal CK1 outputs the first clock signal to the output circuit 30 and the inverter sub-circuit 103, respectively, and the inverter sub-circuit 103 reverses the first clock signal.
  • the phase is output to the output control circuit 20.
  • the waveform of the signal CK_N output by the second control sub-circuit is the same as the waveform of the first clock signal, and the signal CKB_N output by the inverter sub-circuit and the first clock signal The opposite is true.
  • the control signal is the second potential
  • the first transistor M1 is turned off
  • the second transistor M2 is turned on
  • the third clock signal terminal CK3 outputs the third to the second control sub-circuit 102.
  • Clock signal When the third clock signal is at the second potential, the second inverter F2 inverts the third clock signal, and outputs the third clock signal to the first control terminal of the first transmission gate TG1, the third inverter After the third clock signal is inverted, the third clock signal is output to the second control terminal of the second transmission gate TG2.
  • the first transmission gate TG1 is turned on, and the second transmission gate TG2 is turned off.
  • the first transmission gate TG1 Since the first transmission gate TG1 is turned on, the first clock signal terminal CK1 outputs the first clock signal to the output circuit 30 and the inverter sub-circuit 103, respectively.
  • the waveform of the signal CK_N output by the second control sub-circuit is the same as the waveform of the first clock signal.
  • the third clock signal is at the first potential, the first transmission gate TG1 is turned off, the second transmission gate TG2 is turned on, and the second clock signal terminal CK2 outputs the output to the output circuit 30 and the inverting sub-circuit 103, respectively.
  • the second clock signal For example, in FIG.
  • the waveform of the signal CK_N output by the second control sub-circuit is the same as the waveform of the second clock signal.
  • the signal CKB_N output by the inverting sub-circuit is opposite to the phase of the signal CK_N.
  • the frequency of the signal CK_N outputted by the second control sub-circuit to the output circuit can be adjusted by adjusting the potential of the control signal output by the control signal terminal EN.
  • the shift register unit when the control signal is at the first potential, the shift register unit is in the first driving mode T1, and in the first driving mode, the frequency of the signal CK_N is equal to the frequency of the first clock signal, from FIG. It can be seen that the frequency of the signal CK_N in the first driving mode is half of the second driving mode. At this time, the charging time of the shift register unit for each row of pixel units is long, and the gate driving circuit pairs each row in the display device.
  • the time required for the pixel unit to scan once is twice that of the second driving mode. At this time, the display resolution of the display device is low, and the low power consumption display of the display device can be realized.
  • the control signal outputted by the control signal terminal EN is the second potential
  • the shift register unit is in the second driving mode T2
  • the frequency of the signal CK_N is twice that of the first driving mode T1. Since the driving signal outputted when the shift register unit drives the pixel unit is the signal CK_N, in the second driving mode T2, the charging time of the shift register unit for each row of pixel units is short.
  • the time required for the gate driving circuit to scan each row of pixel units in the display device is half of the first driving mode.
  • the gate driving circuit can scan the pixel units of each row in the display device twice in the second driving mode. Therefore, high definition display of the display device can be achieved.
  • the duty ratios of the first clock signal, the second clock signal, and the third clock signal may both be one-half, and the first The phase difference between the clock signal and the second clock signal is 180 degrees, that is, the first clock signal is inverted from the second clock signal, and the phase difference between the first clock signal and the third clock signal is 90 degrees.
  • the duty ratios of the first to third clock signals and the phase difference between the clock signals may be adjusted according to actual conditions, which is not limited in the embodiment of the present disclosure.
  • the timing charts of the first to third clock signals, the signal CK_N, and the signal CKB_N may also be as shown in FIG. 7 (only the timing of each signal in the second driving mode T2 is plotted in FIG. 7).
  • the duty ratio of the first clock signal outputted by the first clock signal terminal CK1 may be one quarter
  • the duty ratio of the second clock signal outputted by the second clock signal terminal CK2 is also one quarter.
  • the duty ratio of the third clock signal output by the third clock signal terminal CK3 is one-half.
  • the frequency of the signal CK_N does not change in the first driving mode and the second driving mode, but the duty ratio of the signal CK_N is in the first driving mode. It is one quarter and one half in the second drive mode.
  • the higher the duty ratio of the signal CK_N the longer the charging time for each row of pixel units, so it is also possible to realize the pixel for each row by changing the duty ratio of the driving signal of the shift register unit. Adjustment of the charging time of the unit.
  • the operation principle of the shift register unit in any driving mode will be described by taking the shift register unit shown in FIGS. 3 and 4 and the timing shown in FIG. 6 as an example.
  • the specific driving process of the shift register unit may include an input phase, an output phase, and a reset phase.
  • the input signal outputted by the input signal terminal STV is the second potential
  • the first output control transistor M5 is turned on
  • the third power signal signal terminal CN pulls up the node PU to output the third power signal.
  • the third power signal is at a second potential (for example, a high potential), so that the pull-up section The potential of the point PU is pulled high, at which time the third output control transistor M7 and the output transistor M12 are turned on, the second power supply signal terminal VGL outputs a second power supply signal to the pull-down node PD, and the sixth output control transistor M10 is turned off.
  • the output circuit outputs a signal CK_N from the clock control circuit to the output terminal OUT, which may be at a first potential (eg, a low potential) during the input phase.
  • the pull-up node maintains the second potential, and when the clock control circuit hops the signal CK_N outputted to the output circuit to the second potential, the pull-up node PU is further pulled up due to the bootstrap effect.
  • the output transistor M12 is fully turned on, and the output circuit outputs the signal CK_N from the clock control circuit to the output terminal OUT, thereby implementing the opening of one row of pixel units (ie, driving the row of pixel units), so that the source in the display device
  • the pole drive circuit is capable of charging the row of pixel units through the data line, that is, the duration of the signal CK_N being at the second potential.
  • the signal CK_N has a longer duration at the second potential in each cycle in the first driving mode T1, and a shorter duration in the second potential in the second driving mode, so the shift register unit is In different driving modes, the charging time of each row of pixel units is different, thereby realizing high definition display or low power consumption display of the display device.
  • the reset signal outputted by the reset signal terminal RST is the second potential, so that the second output control transistor M6 is turned on, and the fourth power signal terminal CNB pulls up the node PU to output the fourth power signal. Since the fourth power signal is at the first potential, the potential of the pull-up node PU is pulled down to the first potential, and the signal CK_N outputted by the clock control circuit to the output circuit jumps to the first potential again, and the clock control When the signal CKB_N outputted by the circuit to the output control circuit is at the second potential, the fifth output control transistor M9 is turned on, the potential of the pull-down node PD is pulled high, and the sixth output control transistor M10 and the seventh output control transistor M11 are turned on, and the second power source is turned on.
  • the signal terminal VGL pulls up the node PU and the output terminal OUT respectively to output a second power signal, and the second power signal is a first potential. At this time, the shift register unit is turned off to prevent the abnormal output of the shift register unit from affecting the shift register unit of other rows.
  • the shift register unit can be applied to Low Temperature Poly-silicon (LTPS) display.
  • LTPS Low Temperature Poly-silicon
  • the LTPS display device has good signal transmission performance, filtering capability and good signal stability.
  • the embodiments of the present disclosure provide a driving method of a shift register unit, where the driving method includes two driving modes.
  • the shift register unit can be directed to the image
  • the prime unit outputs drive signals of different frequencies or different duty ratios, thereby adjusting the charging time of the shift register unit for each row of pixel units.
  • the first driving mode when the frequency of the driving signal outputted by the shift register unit is low, the charging time for each row of pixel units is long, and the resolution of the display device is low, and the display device can be low. Power consumption display.
  • the embodiment of the present disclosure enriches the driving mode of the gate driving circuit to the display device, and improves the flexibility of driving.
  • An embodiment of the present disclosure provides a gate driving circuit, which may include at least two cascaded shift register units, wherein each shift register unit may be as shown in any of FIGS. 1 to 4 .
  • An embodiment of the present disclosure provides a display device, which may include a gate driving circuit, which may include at least two cascaded shift register units as shown in any of FIGS. 1 to 4.
  • the display device may be: a liquid crystal panel, an electronic paper, an OLED panel, an AMOLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like, or any product or component having a display function.

Abstract

一种移位寄存器单元、驱动方法、栅极驱动电路及显示装置。所述移位寄存器单元包括：时钟控制电路(10)、输出控制电路(20)和输出电路(30)；该移位寄存器单元可以通过该时钟控制电路(10)，分别向输出控制电路(20)和输出电路(30)输出不同频率或者不同占空比的时钟信号，从而使得该输出电路(30)可以通过输出端(OUT)向像素单元输出不同频率或者不同占空比的驱动信号，以调整该移位寄存器单元对每行像素单元的充电时间，因此丰富了栅极驱动电路对显示装置的驱动方式，提高了驱动的灵活性。

Description

移位寄存器单元、驱动方法、栅极驱动电路及显示装置 技术领域
本公开实施例涉及一种移位寄存器单元、驱动方法、栅极驱动电路及显示装置。
背景技术
显示装置在显示图像时，需要利用栅极驱动电路(英文：Gate Driver on Array；简称：GOA)对像素单元进行驱动。栅极驱动电路(也称移位寄存器)包括多个级联的移位寄存器单元，其中每个移位寄存器单元用于驱动一行像素单元，由多个移位寄存器单元实现对显示装置的像素单元的逐行扫描驱动，以显示图像。
在相关技术中，栅极驱动电路能够在一帧的时间内对显示装置中各行像素单元扫描一遍，其中，对每行像素单元的充电时间是由时钟信号的频率决定的。
由于移位寄存器单元中所连接的时钟信号端输出的时钟信号的频率和占空比是固定的，因此该栅极驱动电路对像素单元进行驱动时，对每行像素单元的充电时间也是固定的，驱动方式较为单一。
发明内容
第一方面，本公开实施例提供了一种移位寄存器单元，所述移位寄存器单元包括：
时钟控制电路、输出控制电路和输出电路。
所述时钟控制电路分别与控制信号端、第一时钟信号端、第二时钟信号端、第三时钟信号端、所述输出控制电路和所述输出电路连接，所述时钟控制电路被配置为在来自所述控制信号端的控制信号和来自所述第三时钟信号端的第三时钟信号的控制下，向所述输出电路交替输出来自所述第一时钟信号端的第一时钟信号和来自所述第二时钟信号端的第二时钟信号，并向所述输出控制电路交替输出所述第一时钟信号的反相信号和所述第二时钟信号的 反相信号，其中，所述第一时钟信号、所述第二时钟信号和所述第三时钟信号的频率相同，相位互不相同；
所述输出控制电路分别与所述时钟控制电路、上拉节点和输出端连接，被配置为控制所述上拉节点和所述输出端的电位；
所述输出电路分别与所述时钟控制电路、所述上拉节点和所述输出端连接，被配置为在所述上拉节点的控制下，向所述输出端输出来自所述时钟控制电路的信号。
第二方面，本公开实施例提供了一种移位寄存器单元的驱动方法，所述移位寄存器单元包括：时钟控制电路、输出控制电路和输出电路，所述方法包括：
在第一驱动模式下，控制信号端输出的控制信号为第一电位，通过所述时钟控制电路向所述输出电路输出来自第一时钟信号端的第一时钟信号，并向所述输出控制电路输出所述第一时钟信号的反相信号；
在第二驱动模式下，控制信号端输出的控制信号为第二电位，第三时钟信号端输出第三时钟信号，通过所述时钟控制电路向所述输出电路交替输出所述第一时钟信号和来自第二时钟信号端的第二时钟信号，并向所述输出控制电路交替输出所述第一时钟信号的反相信号和所述第二时钟信号的反相信号；
其中，所述第一时钟信号、所述第二时钟信号和所述第三时钟信号的频率相同，相位互不相同。
第三方面，本公开实施例提供了一种栅极驱动电路，所述栅极驱动电路包括：
至少两个级联的移位寄存器单元，其中，每个移位寄存器单元为如第一方面所述的移位寄存器单元。
第四方面，本公开实施例提供了一种显示装置，所述显示装置包括：如第三方面所述的栅极驱动电路。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本 公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种移位寄存器单元的结构示意图之一；
图2是本公开实施例提供的一种移位寄存器单元的结构示意图之二；
图3是本公开实施例提供的一种移位寄存器单元的电路结构示意图之一；
图4是本公开实施例提供的一种移位寄存器单元的电路结构示意图之二；
图5是本公开实施例提供的一种移位寄存器单元的驱动方法的流程图；
图6是本公开实施例提供的一种移位寄存器单元中各信号的时序图之一；以及
图7是本公开实施例提供的一种移位寄存器单元中各信号的时序图之二。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件，根据在电路中的作用本公开的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，将源极称为第一极，漏极称为第二极，栅极称为第三极。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、输出端为漏极。此外，本公开实施例所采用的开关晶体管可以包括P型开关晶体管和N型开关晶体管两种，其中，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型开关晶体管在栅极为高电平时导通，在栅极为低电平时截止。此外，本公开各个实施例中的多个信号都对应有第一电位和第二电位。第一电位和第二电位仅代表该信号的电 位有2个状态量，不代表全文中第一电位或第二电位具有特定的数值，即各个信号的第一电位(或第二电位)的电位值可以相同也可以不同。进一步的，本公开实施例中的第一时钟信号、第二时钟信号和第三时钟信号的频率相同，相位互不相同。例如，该第一时钟信号、第二时钟信号和第三时钟信号的占空比可以均为二分之一；且该第一时钟信号与第二时钟信号的相位差为180度，第一时钟信号与第三时钟信号的相位差为90度。
本公开实施例提供了一种移位寄存器单元、驱动方法、栅极驱动电路及显示装置。该移位寄存器单元包括输出控制电路和输出电路，还包括时钟控制电路。通过该时钟控制电路，可以分别向输出控制电路和输出电路输出不同频率或者不同占空比的时钟信号，从而使得该输出电路可以通过输出端向像素单元输出不同频率或者不同占空比的驱动信号，进而可以调整对每行像素单元的充电时间，因此丰富了栅极驱动电路对显示装置的驱动方式，提高了驱动的灵活性。
图1是本公开实施例提供的一种移位寄存器单元的结构示意图，如图1所示，该移位寄存器单元包括：时钟控制电路10、输出控制电路20和输出电路30。
该时钟控制电路10分别与控制信号端EN、第一电源信号端VGH、第一时钟信号端CK1、第二时钟信号端CK2、第三时钟信号端CK3、该输出控制电路20和该输出电路30连接。该时钟控制电路10被配置为：在来自该控制信号端EN的控制信号和来自该第三时钟信号端CK3的第三时钟信号的控制下，向该输出电路30输出来自该第一时钟信号端CK1的第一时钟信号，并向该输出控制电路20输出该第一时钟信号的反相信号；或者，向该输出电路30交替输出该第一时钟信号和来自该第二时钟信号端CK2的第二时钟信号，并向该输出控制电路20交替输出该第一时钟信号的反相信号和该第二时钟信号的反相信号。该第一时钟信号、该第二时钟信号和该第三时钟信号的频率相同，相位互不相同。
该输出控制电路20分别与该时钟控制电路10、输入信号端STV、复位信号端RST、第二电源信号端VGL、第三电源信号端CN、第四电源信号端CNB、上拉节点PU和输出端OUT连接。该输出控制电路20被配置为控制该上拉节点PU和该输出端OUT的电位。该输出电路30分别与该时钟控制 电路10、该上拉节点PU和该输出端OUT连接，被配置为在该上拉节点PU的控制下，向该输出端OUT输出来自该时钟控制电路10的信号。
综上所述，本公开实施例提供了一种移位寄存器单元，该移位寄存器单元包括输出控制电路和输出电路，还包括时钟控制电路。通过该时钟控制电路，可以向输出电路输出第一时钟信号，或者向输出电路交替输出第一时钟信号和第二时钟信号，从而使得该输出电路可以在该时钟控制电路输出的信号的控制下，向像素单元输出不同频率或者不同占空比的驱动信号，进而可以调整对每行像素单元的充电时间，因此丰富了栅极驱动电路对显示装置的驱动方式，提高了驱动的灵活性。
图2是本公开实施例提供的一种移位寄存器单元的另一结构示意图。参考图2，该时钟控制电路10可以包括：第一控制子电路101、第二控制子电路102和反相子电路103。
该第一控制子电路101分别与该控制信号端EN、该第一电源信号端VGH、该第三时钟信号端CK3和该第二控制子电路102连接。该第一控制子电路101被配置为在该控制信号的控制下，向该第二控制子电路102输出来自该第一电源信号端VGH的第一电源信号，或者来自该第三时钟信号端CK3的第三时钟信号。
该第二控制子电路102分别与该第一控制子电路101、该第一时钟信号端CK1、该第二时钟信号端CK2、该反相子电路103和该输出电路30连接。该第二控制子电路102被配置为：在该第一电源信号的控制下，分别向该反相子电路103和该输出电路30输出该第一时钟信号；或者，在该第三时钟信号的控制下，向该反相子电路103交替输出该第一时钟信号和该第二时钟信号，并向该输出电路30交替输出该第一时钟信号和该第二时钟信号。
该反相子电路103分别与该第二控制子电路102和该输出控制电路20连接，被配置为对该第二控制子电路102输出的信号进行反相后，输出至该输出控制电路20。
图3是本公开实施例提供的一种移位寄存器单元的电路结构示意图。参考图3，该第一控制子电路101可以包括：第一晶体管M1和第二晶体管M2。该第一晶体管M1和该第二晶体管M2的极性相反，例如，如图3所示，该第一晶体管M1可以为P型晶体管，该第二晶体管M2可以为N型晶体管。 或者，该第一晶体管M1可以为N型晶体管，该第二晶体管M2可以为P型晶体管。
该第一晶体管M1的栅极与该控制信号端EN连接，该第一晶体管M1的第一极与该第一电源信号端VGH连接，该第一晶体管M1的第二极与该第二控制子电路102连接。
该第二晶体管M2的栅极与该控制信号端EN连接，该第二晶体管M2的第一极与该第三时钟信号端CK3连接，该第二晶体管M2的第二极与该第二控制子电路102连接。
参考图3，该反相子电路103包括：第一反相器F1，该第一反相器F1的输入端与该第二控制子电路102连接，该第一反相器F1的信号输出端与该输出控制电路20连接。
在本公开一种示例的实施例中，如图3所示，该第二控制子电路102可以包括：第三晶体管M3和第四晶体管M4。该第三晶体管M3和该第四晶体管M4的极性相反，例如，如图3所示，该第三晶体管M3可以为N型晶体管，该第四晶体管M4可以为P型晶体管。或者，该第三晶体管M3可以为P型晶体管，该第四晶体管M4可以为N型晶体管。
该第三晶体管M3的栅极与该第一控制子电路101连接。如图3所示，第三晶体管M3的栅极分别与该第一晶体管M1的第二极以及该第二晶体管M2的第二极连接，该第三晶体管M3的第一极与该第一时钟信号端CK1连接，该第三晶体管M3的第二极分别与该反相子电路103和该输出电路30连接。
该第四晶体管M4的栅极与该第一控制子电路101连接。如图3所示，第四晶体管M4的栅极分别与该第一晶体管M1的第二极以及该第二晶体管M2的第二极连接，该第四晶体管M4的第一极与该第二时钟信号端CK2连接，该第四晶体管M4的第二极分别与该反相子电路103和该输出电路30连接。
在本公开另一种示例的实施例中，如图4所示，该第二控制子电路102还可以包括：第二反相器F2、第一传输门TG1、第三反相器F3和第二传输门TG2。
该第二反相器F2的输入端与该第一控制子电路101连接，例如，该第 二反相器F2的输入端与该第一控制子电路101的输出端连接。该第二反相器F2的信号输出端与该第一传输门TG1的第一控制端连接；该第一传输门TG1的第二控制端与该第一控制子电路101连接，该第一传输门TG1的输入端与该第一时钟信号端CK1连接，该第一传输门TG1的信号输出端分别与该反相子电路103和该输出电路30连接。
该第三反相器F3的输入端与该第一控制子电路101连接，例如，该第三反相器F3的输入端与该第一控制子电路101的输出端连接。该第三反相器F3的信号输出端与该第二传输门TG2的第二控制端连接；该第二传输门TG2的第一控制端与该第一控制子电路101连接，该第二传输门TG2的输入端与该第二时钟信号端CK2连接，该第二传输门TG2的信号输出端分别与该反相子电路103和该输出电路30连接。
在本公开实施例一种示例的实现方式中，该第一时钟信号、第二时钟信号和第三时钟信号的占空比可以均为二分之一，且第一时钟信号与第二时钟信号的相位差可以为180度，第一时钟信号与第三时钟信号的相位差可以为90度。
作为一种示例的实现方式，参考图3和图4，该移位寄存器单元中的输出控制电路20可以包括：第一输出控制晶体管M5、第二输出控制晶体管M6、第三输出控制晶体管M7、第四输出控制晶体管M8、第五输出控制晶体管M9、第六输出控制晶体管M10和第七输出控制晶体管M11。该输出电路30可以包括：输出晶体管M12和电容器C。
例如，该第一输出控制晶体管M5的栅极与该输入信号端STV连接，该第一输出控制晶体管M5的第一极与该第三电源信号端CN连接，该第一输出控制晶体管M5的第二极与该上拉节点PU连接。
该第二输出控制晶体管M6的栅极与该复位信号端RST连接，该第二输出控制晶体管M6的第一极与该第四电源信号端CNB连接，该第二输出控制晶体管M6的第二极与该上拉节点PU连接。
该第三输出控制晶体管M7的栅极与该上拉节点PU连接，该第三输出控制晶体管M7的第一极与该第二电源信号端VGL连接，该第三输出控制晶体管M7的第二极与下拉节点PD连接。
该第四输出控制晶体管M8的栅极与该输出端OUT连接，该第四输出控 制晶体管M8的第一极与该第二电源信号端VGL连接，该第四输出控制晶体管M8的第二极与该下拉节点PD连接。
该第五输出控制晶体管M9的栅极和第一极与该时钟控制电路10(例如，该时钟控制电路10的第一输出端CKB_N)连接，该第五输出控制晶体管M9的第二极与该下拉节点PD连接。
该第六输出控制晶体管M10的栅极与该下拉节点PD连接，该第六输出控制晶体管M10的第一极与该第二电源信号端VGL连接，该第六输出控制晶体管M10的第二极与该上拉节点PU连接。
该第七输出控制晶体管M11的栅极与该下拉节点PD连接，该第七输出控制晶体管M11的第一极与该第二电源信号端VGL连接，该第七输出控制晶体管M11的第二极与该输出端OUT连接。
该输出晶体管M12的栅极与该上拉节点PU连接，该输出晶体管M12的第一极与该时钟控制电路10(例如，该时钟控制电路10的第二输出端CK_N)连接，该输出晶体管M12的第二极与该输出端OUT连接。该电容器C的一端与该上拉节点PU连接，另一端与该输出端OUT连接。
综上所述，本公开实施例提供了一种移位寄存器单元，该移位寄存器单元包括输出控制电路和输出电路，还包括时钟控制电路。通过该时钟控制电路，可以向输出电路输出第一时钟信号，或者向输出电路交替输出第一时钟信号和第二时钟信号，从而使得该输出电路可以在该时钟控制电路输出的信号的控制下，向像素单元输出不同频率或者不同占空比的驱动信号，进而可以调整移位寄存器单元对每行像素单元的充电时间。当输出电路输出的驱动信号的频率较高时，对每行像素单元的充电时间较短，此时显示装置的显示分辨率较高，可以实现显示装置的高清显示；当输出电路输出的驱动信号的频率较低时，对每行像素单元的充电时间较长，此时显示装置的分辨率较低，可以实现显示装置的低功耗显示，因此丰富了栅极驱动电路对显示装置的驱动方式，提高了驱动的灵活性。
需要说明的是，在本公开各实施例中，均是以第一晶体管M1和第四晶体管M4为P型晶体管，其余的晶体管(M2、M3和M5-M12)为N型晶体管，且第二电位相对于第一电位为高电位为例进行的说明。
当然，该第一晶体管M1和第四晶体管M4也可以为N型晶体管，其余 的晶体管(M2、M3和M5-M12)也可以为P型晶体管，此时该第二电位相对于该第一电位可以为低电位，且该各个信号端的电位变化可以与下述附图6所示的电位变化相反(即二者的相位差为180度)。
图5是本公开实施例提供的一种移位寄存器单元的驱动方法的流程图，该方法可以应用于图1至图4任一所示的移位寄存器单元中，如图1所示，该移位寄存器单元可以包括：时钟控制电路10、输出控制电路20和输出电路30。参考图5，该方法可以包括：
步骤201、在第一驱动模式中，控制信号端EN输出的控制信号为第一电位，通过该时钟控制电路10向该输出电路30输出来自第一时钟信号端CK1的第一时钟信号，并向该输出控制电路20输出该第一时钟信号的反相信号。
步骤202、在第二驱动模式中，控制信号端EN输出的控制信号为第二电位，第三时钟信号端CK3输出第三时钟信号，通过该时钟控制电路10向该输出电路30交替输出该第一时钟信号和来自第二时钟信号端CK2的第二时钟信号，并向该输出控制电路20交替输出该第一时钟信号的反相信号和该第二时钟信号的反相信号。
例如，该第一时钟信号、该第二时钟信号和该第三时钟信号的频率相同，相位互不相同。此外，该第二电位相对于该第一电位可以为高电位。
综上所述，本公开实施例提供了一种移位寄存器单元的驱动方法，该驱动方法包括两种驱动模式(例如，如上所述的第一驱动模式和第二驱动模式)。在不同的驱动模式下，时钟控制电路向输出电路输出的信号的频率不同，从而使得该输出电路可以向像素单元输出不同频率或者不同占空比的驱动信号，进而可以调整移位寄存器单元对每行像素单元的充电时间，因此丰富了栅极驱动电路对显示装置的驱动方式，提高了驱动的灵活性。
例如，参考图2，该时钟控制电路10可以包括：第一控制子电路101、第二控制子电路102和反相子电路103。图6是本公开实施例提供的一种驱动方法的时序图，图6中信号CK_N为第二控制子电路102向该输出电路30输出的信号，信号CKB_N为该反相子电路103向该输出控制电路20输出的信号。
如图6所示，在该第一驱动模式T1中，该控制信号端EN输出的控制信 号为第一电位，该第一控制子电路101向该第二控制子电路102输出来自第一电源信号端VGH的第一电源信号，该第一电源信号为第二电位，该第二电位相对于该第一电位可以为高电位。该第二控制子电路102在该第一电源信号的控制下，分别向该输出电路30和该反相子电路103输出该第一时钟信号，该反相子电路103对该第一时钟信号进行反相后，输出至该输出控制电路20。示例的，从图6中可以看出，在该第一驱动模式T1中，第二控制子电路102向输出电路30输出的信号CK_N即为该第一时钟信号端CK1输出的第一时钟信号，反相子电路103向输出控制电路20输出的信号CKB_N与信号CK_N的相位相反。
该第二驱动模式T2中，该控制信号端EN输出的控制信号为第二电位，该第一控制子电路101向该第二控制子电路102输出来自第三时钟信号端CK3的第三时钟信号。当该第三时钟信号处于第二电位时，该第二控制子电路102分别向该输出电路30和该反相子电路103输出该第一时钟信号；当该第三时钟信号处于第一电位时，该第二控制子电路102分别向该输出电路30和该反相子电路103输出该第二时钟信号。该反相子电路103对该第二控制子电路102输出的信号进行反相后，输出至该输出控制电路20。示例的，从图6中可以看出，在该第二驱动模式T2中，当该第三时钟信号端CK3输出的第三时钟信号为第二电位时，该第二控制子电路向输出电路输出的信号CK_N为该第一时钟信号，当该第三时钟信号为第一电位时，该第二控制子电路向输出电路输出的信号CK_N为第二时钟信号，反相子电路向输出控制电路输出的信号CKB_N与信号CK_N的相位相反。
在本公开一种示例的实施例中，参考图3，该第一控制子电路101包括：第一晶体管M1和第二晶体管M2，该第一晶体管M1和该第二晶体管M2的极性相反；该第二控制子电路102包括：第三晶体管M3和第四晶体管M4，该第三晶体管M3和该第四晶体管M4的极性相反。示例的，如图3所示，该第一晶体管M1和第四晶体管M4为P型晶体管，该第二晶体管M2和第三晶体管M3为N型晶体管。
在该第一驱动模式T1中，该控制信号为第一电位，该第一晶体管M1开启，该第二晶体管M2关断，此时该第一电源信号端VGH向该第二控制子电路102输出来自第一电源端VGH的该第一电源信号。由于该第一电源 信号处于第二电位，此时该第三晶体管M3开启，该第四晶体管M4关断，该第一时钟信号端CK1分别向该输出电路30和该反相子电路103输出该第一时钟信号，该反相子电路103对该第一时钟信号进行反相后输出至该输出控制电路20。参考图6，在第一驱动模式T1中，该第二控制子电路输出的信号CK_N的波形与该第一时钟信号(即第一时钟信号端CK1输出的信号)的波形相同，该反相子电路输出的信号CKB_N与该第一时钟信号的相位相反。
在该第二驱动模式T2中，该控制信号为第二电位，该第一晶体管M1关断，该第二晶体管M2开启，该第三时钟信号端CK3向该第二控制子电路102输出该第三时钟信号。当该第三时钟信号处于第二电位时，该第三晶体管M3开启，该第四晶体管M4关断，该第一时钟信号端CK1分别向该输出电路30和该反相子电路103输出该第一时钟信号。例如图6中，第二驱动模式T2中的t1和t3阶段，该第三时钟信号端CK3输出的第三时钟信号处于第二电位，此时该第二控制子电路输出的信号CK_N的波形与该第一时钟信号的波形相同。当该第三时钟信号处于第一电位时，该第三晶体管M3关断，该第四晶体管M4开启，该第二时钟信号端CK2分别向该输出电路30和该反相子电路103输出该第二时钟信号。例如图6中，在第二驱动模式T2中的t2阶段，该第三时钟信号处于第一电位，此时第二控制子电路输出的信号CK_N的波形与该第二时钟信号的波形相同。并且，在该第二驱动模式T2中，该反相子电路输出的信号CKB_N与信号CK_N的相位相反。
在本公开另一种示例的实施例中，参考图4，该第一控制子电路101包括：第一晶体管M1和第二晶体管M2，该第一晶体管M1和该第二晶体管M2的极性相反；该第二控制子电路102包括：第二反相器F2、第一传输门TG1、第三反相器F3和第二传输门TG2。
在该第一驱动模式T1中，该控制信号为第一电位，该第一晶体管M1开启，该第二晶体管M2关断，此时该第一电源信号端VGH向该第二控制子电路102输出该第一电源信号。由于该第一电源信号处于第二电位，该第二反相器F2对该第一电源信号进行反相后，输出至该第一传输门TG1的第一控制端，此时该第一传输门TG1开启；该第三反相器F3对该第一电源信号进行反相后，输出至该第二传输门TG2的第二控制端，该第二传输门TG2 关闭。由于该第一传输门TG1开启，该第一时钟信号端CK1分别向该输出电路30和该反相子电路103输出该第一时钟信号，该反相子电路103对该第一时钟信号进行反相后输出至该输出控制电路20。参考图6，在第一驱动模式T1中，该第二控制子电路输出的信号CK_N的波形与该第一时钟信号的波形相同，该反相子电路输出的信号CKB_N与该第一时钟信号的相位相反。
该第二驱动模式T2中，该控制信号为第二电位，该第一晶体管M1关断，该第二晶体管M2开启，该第三时钟信号端CK3向该第二控制子电路102输出该第三时钟信号。当该第三时钟信号处于第二电位时，该第二反相器F2对该第三时钟信号进行反相后，输出至该第一传输门TG1的第一控制端，该第三反相器F3对该第三时钟信号进行反相后，输出至该第二传输门TG2的第二控制端，该第一传输门TG1开启，该第二传输门TG2关闭。由于该第一传输门TG1开启，该第一时钟信号端CK1分别向该输出电路30和该反相子电路103输出该第一时钟信号。例如图6中，在第二驱动模式T2中的t1和t3阶段，该第二控制子电路输出的信号CK_N的波形与该第一时钟信号的波形相同。当该第三时钟信号处于第一电位时，该第一传输门TG1关闭，该第二传输门TG2开启，该第二时钟信号端CK2分别向该输出电路30和该反相子电路103输出该第二时钟信号。例如图6中，在第二驱动模式T2中的t2阶段，第二控制子电路输出的信号CK_N的波形与该第二时钟信号的波形相同。在整个第二驱动模式T2中，该反相子电路输出的信号CKB_N与信号CK_N的相位相反。
综上可知，在本公开实施例中，可以通过调整该控制信号端EN输出的控制信号的电位，实现对第二控制子电路向输出电路输出的信号CK_N的频率的调整。参考图6，当控制信号为第一电位时，该移位寄存器单元处于第一驱动模式T1，在该第一驱动模式下，信号CK_N的频率与该第一时钟信号的频率相等，从图6中可以看出，第一驱动模式中信号CK_N的频率为第二驱动模式中的一半，此时移位寄存器单元对每行像素单元的充电时间较长，该栅极驱动电路对显示装置中各行像素单元扫描一遍所需的时间为第二驱动模式的两倍，此时显示装置的显示分辨率较低，可以实现显示装置的低功耗显示。当控制信号端EN输出的控制信号为第二电位时，该移位寄存器单元处于第二驱动模式T2中，信号CK_N的频率为第一驱动模式T1中的两倍， 由于移位寄存器单元对像素单元进行驱动时输出的驱动信号即为该信号CK_N，因此，在该第二驱动模式T2中，移位寄存器单元对每行像素单元的充电时间较短，此时该栅极驱动电路对显示装置中各行像素单元扫描一遍所需的时间为第一驱动模式的一半。也即是，在栅极驱动电路以第一驱动模式扫描一遍显示装置中各像素单元所需的时间内，栅极驱动电路在第二驱动模式下能够对显示装置中各行像素单元扫描两遍，因此可以实现显示装置的高清显示。
在本公开实施例一种示例的实现方式中，参考图6，该第一时钟信号、该第二时钟信号和该第三时钟信号的占空比可以均为二分之一，且该第一时钟信号与该第二时钟信号的相位差为180度，即该第一时钟信号与该第二时钟信号等幅反相，该第一时钟信号与该第三时钟信号的相位差为90度。
需要说明的是，该第一至第三时钟信号的占空比，以及各个时钟信号之间的相位差还可以根据实际情况进行调整，本公开实施例对此不做限定。示例的，该第一至第三时钟信号、信号CK_N以及信号CKB_N的时序图还可以如图7所示(图7中仅绘制了第二驱动模式T2中各信号的时序)。例如，该第一时钟信号端CK1输出的第一时钟信号的占空比可以为四分之一，该第二时钟信号端CK2输出的第二时钟信号的占空比也为四分之一，该第三时钟信号端CK3输出的第三时钟信号的占空比为二分之一。对于图7所示的各个时钟信号的频率和占空比，在第一驱动模式和第二驱动模式下，信号CK_N的频率未发生改变，但该信号CK_N的占空比在第一驱动模式下为四分之一，在第二驱动模式下为二分之一。在频率相等的情况下，信号CK_N的占空比越高，对每行像素单元的充电时间越长，因此也可以通过改变该移位寄存器单元的驱动信号的占空比来实现对每行像素单元的充电时间的调整。
进一步的，以图3和图4所示的移位寄存器单元以及图6所示的时序为例，对该移位寄存器单元在任一驱动模式下的工作原理进行介绍。在任一驱动模式下(例如，在上述第一驱动模式或上述第二驱动模式下)，该移位寄存器单元的具体驱动过程均可以包括输入阶段、输出阶段和复位阶段。
在输入阶段中，输入信号端STV输出的输入信号为第二电位，第一输出控制晶体管M5开启，第三电源信号端CN向上拉节点PU输出第三电源信号。参考图6，该第三电源信号为第二电位(例如，高电位)，使该上拉节 点PU的电位被拉高，此时第三输出控制晶体管M7和输出晶体管M12开启，第二电源信号端VGL向下拉节点PD输出第二电源信号，第六输出控制晶体管M10关断。此时输出电路向输出端OUT输出来自时钟控制电路的信号CK_N，该信号CK_N在该输入阶段可以为第一电位(例如，低电位)。
在输出阶段中，该上拉节点保持第二电位，当时钟控制电路向所述输出电路输出的信号CK_N跳变至第二电位时，上拉节点PU由于自举效应，其电位被进一步拉高，此时输出晶体管M12完全开启，输出电路向输出端OUT输出来自该时钟控制电路的信号CK_N，从而实现对一行像素单元的开启(即对该行像素单元进行驱动)，使得显示装置中的源极驱动电路能够通过数据线对该行像素单元进行充电，该充电时间即为信号CK_N处于第二电位的时长。参考图6可知，信号CK_N在第一驱动模式T1中每个周期处于第二电位的时长较长，在第二驱动模式中每个周期处于第二电位的时长较短，因此移位寄存器单元在不同的驱动模式下，对每行像素单元的充电时间不同，由此可以实现显示装置的高清显示或者低功耗显示。
在复位阶段中，复位信号端RST输出的复位信号为第二电位，使得第二输出控制晶体管M6开启，第四电源信号端CNB向上拉节点PU输出第四电源信号。由于该第四电源信号为第一电位，从而将该上拉节点PU的电位下拉为第一电位，并且当时钟控制电路向输出电路输出的信号CK_N再次跳变至第一电位，且该时钟控制电路向输出控制电路输出的信号CKB_N处于第二电位时，第五输出控制晶体管M9开启，下拉节点PD的电位被拉高，第六输出控制晶体管M10和第七输出控制晶体管M11开启，第二电源信号端VGL向上拉节点PU和输出端OUT分别输出第二电源信号，该第二电源信号为第一电位。此时该移位寄存器单元处于关闭状态，以避免移位寄存器单元的非正常输出对其他行的移位寄存器单元造成影响。
此外，由于本公开实施例提供的移位寄存器单元中同时采用了N型晶体管和P型晶体管，因此该移位寄存器单元可以应用于低温多晶硅(英文：Low Temperature Poly-silicon；简称：LTPS)显示装置中。LTPS显示装置信号传输性能好，有滤波能力，信号稳定性好。
综上所述，本公开实施例提供了一种移位寄存器单元的驱动方法，该驱动方法包括两种驱动模式。在不同的驱动模式下，移位寄存器单元能够向像 素单元输出不同频率或者不同占空比的驱动信号，进而可以调整移位寄存器单元对每行像素单元的充电时间。例如，在第一驱动模式下，移位寄存器单元输出的驱动信号的频率较低时，对每行像素单元的充电时间较长，此时显示装置的分辨率较低，可以实现显示装置的低功耗显示。在第二驱动模式下，移位寄存器单元输出的驱动信号的频率较高时，对每行像素单元的充电时间较短，此时显示装置的显示分辨率较高，可以实现显示装置的高清显示。因此，本公开实施例丰富了栅极驱动电路对显示装置的驱动方式，提高了驱动的灵活性。
本公开实施例提供了一种栅极驱动电路，该栅极驱动电路可以包括至少两个级联的移位寄存器单元，其中，每个移位寄存器单元可以为如图1至图4任一所示的移位寄存器单元。
本公开实施例提供一种显示装置，该显示装置可以包括栅极驱动电路，该栅极驱动电路可以包括至少两个级联的如图1至图4任一所示的移位寄存器单元。该显示装置可以为：液晶面板、电子纸、OLED面板、AMOLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述仅为本公开的示例实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。
在本文中，诸如“第一”和“第二”等关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护 范围应以所述权利要求的保护范围为准。
本公开要求于2016年9月30日递交的中国专利申请第201610873900.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (15)

  1. 一种移位寄存器单元，包括：
    时钟控制电路、输出控制电路和输出电路；其中，
    所述时钟控制电路分别与控制信号端、第一时钟信号端、第二时钟信号端、第三时钟信号端、所述输出控制电路和所述输出电路连接，所述时钟控制电路被配置为在来自所述控制信号端的控制信号和来自所述第三时钟信号端的第三时钟信号的控制下，向所述输出电路交替输出来自所述第一时钟信号端的第一时钟信号和来自所述第二时钟信号端的第二时钟信号，并向所述输出控制电路交替输出所述第一时钟信号的反相信号和所述第二时钟信号的反相信号，其中，所述第一时钟信号、所述第二时钟信号和所述第三时钟信号的频率相同，相位互不相同；
    所述输出控制电路分别与所述时钟控制电路、上拉节点和输出端连接，被配置为控制所述上拉节点和所述输出端的电位；
    所述输出电路分别与所述时钟控制电路、所述上拉节点和所述输出端连接，被配置为在所述上拉节点的控制下，向所述输出端输出来自所述时钟控制电路的信号。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述时钟控制电路还被配置为在来自所述控制信号端的控制信号和来自所述第三时钟信号端的第三时钟信号的控制下，向所述输出电路输出所述第一时钟信号，并向所述输出控制电路输出所述第一时钟信号的反相信号。
  3. 根据权利要求1或2所述的移位寄存器单元，其中，所述时钟控制电路包括：第一控制子电路、第二控制子电路和反相子电路；
    所述第一控制子电路分别与所述控制信号端、第一电源信号端、所述第三时钟信号端和所述第二控制子电路连接，被配置为在所述控制信号的控制下，向所述第二控制子电路输出来自所述第一电源信号端的第一电源信号，或者来自所述第三时钟信号端的第三时钟信号；
    所述第二控制子电路分别与所述第一控制子电路、所述第一时钟信号端、 所述第二时钟信号端、所述反相子电路和所述输出电路连接，所述第二控制子电路被配置为：在所述第一电源信号的控制下，分别向所述反相子电路和所述输出电路输出所述第一时钟信号；或者，在所述第三时钟信号的控制下，向所述反相子电路交替输出所述第一时钟信号和所述第二时钟信号，并向所述输出电路交替输出所述第一时钟信号和所述第二时钟信号；
    所述反相子电路分别与所述第二控制子电路和所述输出控制电路连接，被配置为对所述第二控制子电路输出的信号进行反相后，输出至所述输出控制电路。
  4. 根据权利要求3所述的移位寄存器单元，其中，所述第一控制子电路包括：第一晶体管和第二晶体管，所述第一晶体管和所述第二晶体管的极性相反；
    所述第一晶体管的栅极与所述控制信号端连接，所述第一晶体管的第一极与所述第一电源信号端连接，所述第一晶体管的第二极与所述第二控制子电路连接；
    所述第二晶体管的栅极与所述控制信号端连接，所述第二晶体管的第一极与所述第三时钟信号端连接，所述第二晶体管的第二极与所述第二控制子电路连接。
  5. 根据权利要求3或4所述的移位寄存器单元，其中，所述反相子电路包括：第一反相器；
    所述第一反相器的输入端与所述第二控制子电路连接，所述第一反相器的信号输出端与所述输出控制电路连接。
  6. 根据权利要求3至5任一所述的移位寄存器单元，其中，所述第二控制子电路包括：第三晶体管和第四晶体管，所述第三晶体管和所述第四晶体管的极性相反；
    所述第三晶体管的栅极与所述第一控制子电路连接，所述第三晶体管的第一极与所述第一时钟信号端连接，所述第三晶体管的第二极分别与所述反相子电路和所述输出电路连接；
    所述第四晶体管的栅极与所述第一控制子电路连接，所述第四晶体管的第一极与所述第二时钟信号端连接，所述第四晶体管的第二极分别与所述反相子电路和所述输出电路连接。
  7. 根据权利要求3至5任一所述的移位寄存器单元，其中，所述第二控制子电路包括：第二反相器、第一传输门、第三反相器和第二传输门；
    所述第二反相器的输入端与所述第一控制子电路连接，所述第二反相器的信号输出端与所述第一传输门的第一控制端连接；
    所述第一传输门的第二控制端与所述第一控制子电路连接，所述第一传输门的输入端与所述第一时钟信号端连接，所述第一传输门的信号输出端分别与所述反相子电路和所述输出电路连接；
    所述第三反相器的输入端与所述第一控制子电路连接，所述第三反相器的信号输出端与所述第二传输门的第二控制端连接；
    所述第二传输门的第一控制端与所述第一控制子电路连接，所述第二传输门的输入端与所述第二时钟信号端连接，所述第二传输门的信号输出端分别与所述反相子电路和所述输出电路连接。
  8. 根据权利要求1至7任一所述的移位寄存器单元，其中，所述输出控制电路包括：第一输出控制晶体管、第二输出控制晶体管、第三输出控制晶体管、第四输出控制晶体管、第五输出控制晶体管、第六输出控制晶体管和第七输出控制晶体管；
    所述第一输出控制晶体管的栅极与输入信号端连接，所述第一输出控制晶体管的第一极与第三电源信号端连接，所述第一输出控制晶体管的第二极与所述上拉节点连接；
    所述第二输出控制晶体管的栅极与复位信号端连接，所述第二输出控制晶体管的第一极与第四电源信号端连接，所述第二输出控制晶体管的第二极与所述上拉节点连接；
    所述第三输出控制晶体管的栅极与所述上拉节点连接，所述第三输出控制晶体管的第一极与第二电源信号端连接，所述第三输出控制晶体管的第二极与下拉节点连接；
    所述第四输出控制晶体管的栅极与所述输出端连接，所述第四输出控制晶体管的第一极与所述第二电源信号端连接，所述第四输出控制晶体管的第二极与所述下拉节点连接；
    所述第五输出控制晶体管的栅极和第一极与所述时钟控制电路连接，所述第五输出控制晶体管的第二极与所述下拉节点连接；
    所述第六输出控制晶体管的栅极与所述下拉节点连接，所述第六输出控制晶体管的第一极与所述第二电源信号端连接，所述第六输出控制晶体管的第二极与所述上拉节点连接；
    所述第七输出控制晶体管的栅极与所述下拉节点连接，所述第七输出控制晶体管的第一极与所述第二电源信号端连接，所述第七输出控制晶体管的第二极与所述输出端连接。
  9. 根据权利要求1至8任一所述的移位寄存器单元，其中，所述输出电路包括：输出晶体管和电容器；
    所述输出晶体管的栅极与所述上拉节点连接，所述输出晶体管的第一极与所述时钟控制电路连接，所述输出晶体管的第二极与所述输出端连接；
    所述电容器的一端与所述上拉节点连接，另一端与所述输出端连接。
  10. 根据权利要求1至9任一所述的移位寄存器单元，其中，
    所述第一时钟信号、所述第二时钟信号和所述第三时钟信号的占空比均为二分之一；
    所述第一时钟信号与所述第二时钟信号的相位差为180度，所述第一时钟信号与所述第三时钟信号的相位差为90度。
  11. 一种移位寄存器单元的驱动方法，其中，所述移位寄存器单元包括：时钟控制电路、输出控制电路和输出电路，所述方法包括：
    在第一驱动模式下，控制信号端输出的控制信号为第一电位，通过所述时钟控制电路向所述输出电路输出来自第一时钟信号端的第一时钟信号，并向所述输出控制电路输出所述第一时钟信号的反相信号；
    在第二驱动模式下，控制信号端输出的控制信号为第二电位，第三时钟 信号端输出第三时钟信号，通过所述时钟控制电路向所述输出电路交替输出所述第一时钟信号和来自第二时钟信号端的第二时钟信号，并向所述输出控制电路交替输出所述第一时钟信号的反相信号和所述第二时钟信号的反相信号；
    其中，所述第一时钟信号、所述第二时钟信号和所述第三时钟信号的频率相同，相位互不相同。
  12. 根据权利要求11所述的方法，其中，所述第一驱动模式和所述第二驱动模式中的任一驱动模式包括：
    输入阶段，其中，输入信号端输出的输入信号为第二电位，所述输出控制电路将上拉节点的电位上拉为第二电位；
    输出阶段，其中，所述上拉节点保持第二电位，所述输出电路接收并输出来自所述时钟控制电路的信号；
    复位阶段，其中，复位信号端输出的复位信号为第二电位，所述输出控制电路控制所述上拉节点的电位为第一电位。
  13. 根据权利要求11或12所述的方法，其中，
    所述第一时钟信号、所述第二时钟信号和所述第三时钟信号的占空比均为二分之一；
    所述第一时钟信号与所述第二时钟信号的相位差为180度，所述第一时钟信号与所述第三时钟信号的相位差为90度。
  14. 一种栅极驱动电路，包括：
    至少两个级联的移位寄存器单元，其中，每个移位寄存器单元为如权利要求1至10任一所述的移位寄存器单元。
  15. 一种显示装置，包括：如权利要求14所述的栅极驱动电路。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10923022B2 (en) 2019-02-05 2021-02-16 Apple Inc. Display gate drivers with dynamic and reduced voltage swing

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106251804B (zh) * 2016-09-30 2018-12-21 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN106548747A (zh) * 2017-02-06 2017-03-29 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN106710561B (zh) * 2017-03-08 2019-09-17 京东方科技集团股份有限公司 一种移位寄存器、栅线集成驱动电路及显示装置
CN106960652B (zh) 2017-04-21 2018-10-30 京东方科技集团股份有限公司 栅极驱动单元、驱动方法、栅极驱动电路和显示装置
CN109410881B (zh) * 2018-12-20 2020-06-02 深圳市华星光电技术有限公司 信号传输系统及信号传输方法
CN111326126B (zh) * 2020-04-16 2022-03-25 福州京东方光电科技有限公司 信号提供电路、信号提供方法及显示装置
CN111583851A (zh) * 2020-05-28 2020-08-25 南京中电熊猫液晶显示科技有限公司 一种栅极驱动电路及其驱动方法
US11658689B2 (en) * 2020-06-29 2023-05-23 Qualcomm Incorporated T-switch with shunt for improved receiver sensitivity
CN114793461B (zh) * 2020-11-24 2024-04-09 京东方科技集团股份有限公司 移位寄存器电路、栅极驱动电路及其驱动方法、显示装置
CN112700745B (zh) * 2021-01-19 2023-05-05 Tcl华星光电技术有限公司 显示面板的驱动方法及显示面板
CN113570995B (zh) * 2021-07-30 2023-11-24 北京京东方显示技术有限公司 信号时序控制方法、栅极驱动电路以及显示面板
CN113570996B (zh) 2021-07-30 2022-05-10 惠科股份有限公司 显示面板的驱动电路和显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110148853A1 (en) * 2009-12-18 2011-06-23 Gwang-Bum Ko Display panel
US20130002306A1 (en) * 2011-06-30 2013-01-03 Chung Kyung-Hoon Stage circuit and scan driver using the same
CN103035218A (zh) * 2012-12-14 2013-04-10 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路及显示器件
CN104835466A (zh) * 2015-05-20 2015-08-12 京东方科技集团股份有限公司 扫描驱动电路、阵列基板、显示装置及驱动方法
CN106251804A (zh) * 2016-09-30 2016-12-21 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI511116B (zh) * 2006-10-17 2015-12-01 Semiconductor Energy Lab 脈衝輸出電路、移位暫存器及顯示裝置
KR20080041894A (ko) * 2006-11-08 2008-05-14 삼성전자주식회사 액정 표시 장치
TWI384756B (zh) * 2009-12-22 2013-02-01 Au Optronics Corp 移位暫存器
KR101373979B1 (ko) * 2010-05-07 2014-03-14 엘지디스플레이 주식회사 게이트 쉬프트 레지스터와 이를 이용한 표시장치
US9336740B2 (en) * 2011-06-30 2016-05-10 Sharp Kabushiki Kaisha Shift register, display drive circuit, display panel, and display device
CN102654986A (zh) * 2011-11-25 2012-09-05 京东方科技集团股份有限公司 移位寄存器的级、栅极驱动器、阵列基板以及显示装置
CN102982777B (zh) * 2012-12-07 2015-10-07 京东方科技集团股份有限公司 显示装置的栅极驱动电路
KR102100915B1 (ko) * 2013-12-13 2020-04-16 엘지디스플레이 주식회사 표시장치를 위한 타이밍 제어장치 및 방법
CN103778896B (zh) * 2014-01-20 2016-05-04 深圳市华星光电技术有限公司 集成栅极驱动电路及具有集成栅极驱动电路的显示面板
CN104134430B (zh) * 2014-07-04 2016-08-17 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路及显示装置
CN104269145B (zh) * 2014-09-05 2016-07-06 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路及显示装置
CN104485086A (zh) * 2015-01-04 2015-04-01 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、栅极驱动电路及显示器件
CN104715710B (zh) * 2015-04-10 2016-10-19 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、扫描驱动电路、显示装置
CN104882168B (zh) * 2015-06-19 2018-09-04 京东方科技集团股份有限公司 移位寄存单元、移位寄存器、栅极驱动电路和显示装置
CN104867438B (zh) * 2015-06-24 2018-02-13 合肥鑫晟光电科技有限公司 移位寄存器单元及其驱动方法、移位寄存器和显示装置
CN106205461B (zh) * 2016-09-30 2019-04-02 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN106710561B (zh) * 2017-03-08 2019-09-17 京东方科技集团股份有限公司 一种移位寄存器、栅线集成驱动电路及显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110148853A1 (en) * 2009-12-18 2011-06-23 Gwang-Bum Ko Display panel
US20130002306A1 (en) * 2011-06-30 2013-01-03 Chung Kyung-Hoon Stage circuit and scan driver using the same
CN103035218A (zh) * 2012-12-14 2013-04-10 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路及显示器件
CN104835466A (zh) * 2015-05-20 2015-08-12 京东方科技集团股份有限公司 扫描驱动电路、阵列基板、显示装置及驱动方法
CN106251804A (zh) * 2016-09-30 2016-12-21 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10923022B2 (en) 2019-02-05 2021-02-16 Apple Inc. Display gate drivers with dynamic and reduced voltage swing

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