WO2018040711A1 - 移位寄存器及其中的驱动方法、栅极驱动电路和显示装置 - Google Patents

移位寄存器及其中的驱动方法、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2018040711A1
WO2018040711A1 PCT/CN2017/090775 CN2017090775W WO2018040711A1 WO 2018040711 A1 WO2018040711 A1 WO 2018040711A1 CN 2017090775 W CN2017090775 W CN 2017090775W WO 2018040711 A1 WO2018040711 A1 WO 2018040711A1
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Prior art keywords
node
pull
terminal
unit
clock signal
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PCT/CN2017/090775
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English (en)
French (fr)
Inventor
郑灿
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京东方科技集团股份有限公司
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Priority to JP2018500805A priority Critical patent/JP6893909B2/ja
Priority to US17/191,101 priority patent/USRE49782E1/en
Priority to US15/736,543 priority patent/US10223993B2/en
Publication of WO2018040711A1 publication Critical patent/WO2018040711A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms

Definitions

  • the present disclosure relates to a shift register and a driving method therefor, a gate driving circuit including the shift register, and a display device.
  • TFT-LCDs Thin film transistor liquid crystal displays
  • the driving circuit of the TFT-LCD mainly includes a gate driving circuit and a data driving circuit.
  • the data driving circuit is configured to sequentially latch the input data according to the clock signal timing and convert the latched data into an analog signal and input the data to the data line of the display panel.
  • the gate driving circuit is usually implemented by a shift register that converts a clock signal into an on/off voltage, which are respectively output to respective gate lines of the display panel.
  • a gate line on the display panel is typically docked with a shift register (ie, the stage of the shift register). Progressive scanning of pixels in the display panel is achieved by causing the respective shift registers to sequentially output the turn-on voltage.
  • At least one embodiment of the present disclosure provides a shift register and a driving method therefor. It can reduce the noise at the output of the shift register and improve the drive capability of the shift register.
  • a shift register comprising:
  • An input unit the first end of which is connected to the input end of the shift register for receiving an input signal from the input end, the second end is connected to the first clock signal end, and the third end is connected to the first node, configured to be The input signal is supplied to the first section under the control of the first clock signal of the first clock signal end point;
  • a pull-up unit the first end of which is connected to the first power voltage terminal, the second end is connected to the second node, and the third end is connected to the output end of the shift register, and is configured to be under the control of the voltage of the second node
  • the voltage of the first power voltage terminal is provided to the output terminal;
  • the pull-up control unit has a first end connected to the second clock signal end, a second end connected to the first power voltage end, a third end connected to the second node, a fourth end connected to the input end, and a fifth end and a third end
  • the two power supply voltage terminals are connected, configured to provide the voltage of the first power supply voltage terminal to the second node under the control of the input signal or to control the voltage under the control of the second clock signal from the second clock signal end a voltage of the two power supply voltage terminals is provided to the second node;
  • a pull-down unit the first end of which is connected to the first node, the second end is connected to the third clock signal end, and the third end is connected to the output end, and is configured to be from the third clock signal end under the control of the voltage of the first node a third clock signal is provided to the output terminal;
  • a pull-down control unit configured to be the first one under the control of the voltage of the second node a voltage at a voltage terminal of the power supply is supplied to the first node;
  • the first noise reduction unit has a first end connected to the third clock signal end, a second end connected to the output end, and a third end connected to the third node, configured to reduce the voltage of the third node by Leakage of the first node by the input unit;
  • a second noise reduction unit wherein the first end is connected to the fourth node, the second end is connected to the first node, and the third end is connected to the second power voltage end, and is configured to reduce the voltage of the fourth node by Small leakage of the first node by the pull-down control unit;
  • the third node is a connection point of the first noise reduction unit and the input unit
  • the fourth node is a connection point of the second noise reduction unit and the pull-down control unit.
  • the input unit includes: a first transistor having a gate connected to the first clock signal terminal, a first pole connected to the input terminal, a second pole connected to the third node, and a second transistor having a gate and a first clock The signal end is connected, the first pole is connected to the third node, and the second pole is connected to the first node.
  • the pull-up unit includes: a third transistor having a gate connected to the second node, a first pole connected to the first power voltage terminal, a second pole connected to the output terminal, and a first capacitor having a first end and a first end The two nodes are connected, and the second end is connected to the first power voltage terminal.
  • the pull-up control unit includes: a fourth transistor having a gate connected to the input terminal, a first pole connected to the first power supply voltage terminal, a second pole connected to the second node, and a fifth transistor having a gate Connected to the second clock signal terminal, the first pole is connected to the second node, and the second pole is connected to the second power voltage terminal.
  • the pull-down unit includes: a sixth transistor having a gate connected to the first node, a first pole connected to the output terminal, a second pole connected to the third clock signal end, and a second capacitor having a first end and a first end The nodes are connected, and the second end is connected to the output.
  • the pull-down control unit includes: a seventh transistor having a gate connected to the second node, a first pole connected to the first power voltage terminal, a second pole connected to the fourth node, and an eighth transistor having a gate and a The two nodes are connected, the first end is connected to the fourth node, and the second end is connected to the first node.
  • the first noise reduction unit includes: a ninth transistor having a gate connected to the output end, a first pole connected to the third clock signal end, and a second pole connected to the third node.
  • the second noise reduction unit includes: a tenth transistor having a gate connected to the first node, a first pole connected to the fourth node, and a second pole connected to the second power voltage terminal.
  • the above transistors are all P-type transistors.
  • the duty ratios of the first, second, and third clock signals of the first, second, and third clock signal terminals are both 33%.
  • the first supply voltage terminal is a high supply voltage terminal and the second supply voltage terminal is a low supply voltage terminal.
  • a driving method applied to a shift register including an input unit, a pull-up unit, a pull-up control unit, a pull-down unit, a pull-down control unit, and a first noise reduction unit is disclosed. And a second noise reduction unit, the driving method comprising:
  • the first node is an input unit, a pull-down unit, a pull-down control unit, and a second noise reduction unit Connection point
  • the second node is a connection point of the pull-up unit
  • the third node is the connection point of the first noise reduction unit and the input unit
  • the fourth node is the second noise reduction unit and Pull down the connection point of the control unit.
  • the first supply voltage terminal is a high supply voltage terminal and the second supply voltage terminal is a low supply voltage terminal.
  • the duty ratio of the third clock signal of the third clock signal terminal is 33%.
  • Another aspect of the present disclosure also provides a gate driving circuit including the above shift register.
  • Another aspect of the present disclosure also provides a display device including the above-described gate driving circuit.
  • the driving method thereof the gate driving circuit including the shift register, and the display device, a series transistor structure is employed, and the timing is controlled to access the connection point of the series transistor
  • the level of the drive transistor reduces the leakage current of the gate level of the drive transistor during the output stage, thereby reducing the noise at the output of the shift register and improving the drive capability of the shift register.
  • FIG. 1 shows a block diagram of a shift register in accordance with an embodiment of the present disclosure
  • FIG. 2 illustrates an example circuit configuration diagram of a shift register in accordance with an embodiment of the present disclosure
  • FIG. 3 is a timing chart when the shift register of FIG. 2 is scanned
  • Figure 4 is a circuit diagram showing a known shift register
  • FIG. 5 is a view showing a comparison of gate levels of respective driving transistors of the shift register of FIG. 2 and the shift register of FIG. 4 under the same circuit parameter conditions;
  • Figure 6 is a graph showing the comparison of the output levels of the respective drive transistors of the shift register of Figure 2 and the shift register of Figure 4 under the same circuit parameters.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other device having the same characteristics.
  • the connection modes of the drain and the source of each transistor are interchangeable. Therefore, the drain and source of each transistor in the embodiment of the present disclosure are practically indistinguishable.
  • the drain and source of each transistor in the embodiment of the present disclosure are practically indistinguishable.
  • the gate one of which is called the drain and the other is called the source.
  • the present disclosure proposes a shift register, which can effectively reduce noise at the output end and improve the driving capability of the shift register.
  • FIG. 1 shows a block diagram of a shift register in accordance with an embodiment of the present disclosure.
  • the shift register includes an input unit 11, a pull-up unit 12, a pull-up control unit 13, a pull-down unit 14, a pull-down control unit 15, a first noise reduction unit 16, and a second Noise reduction unit 17.
  • the first end of the input unit 11 is connected to the input terminal INPUT of the shift register for receiving an input signal from the input terminal INPUT, the second end is connected to the first clock signal terminal CK1, and the third end is connected to the first node N1.
  • the input unit 11 is configured to deliver the received input signal to the first node N1 under the control of the first clock signal at the first clock signal terminal CK1.
  • the first end of the pull-up unit 12 is connected to the first power supply voltage terminal VGH, the second end is connected to the second node N2, and the third end is connected to the output terminal OUTPUT of the shift register.
  • the pull-up unit 12 is configured to supply the voltage VGH of the first power supply voltage terminal to the output terminal OUTPUT under the control of the voltage of the second node N2.
  • the first end of the pull-up control unit 13 is connected to the second clock signal terminal CK2, the second end is connected to the first power voltage terminal VGH, the third terminal is connected to the second node N2, and the fourth terminal is connected to the input terminal INPUT.
  • the five terminals are connected to the second power supply voltage terminal VGL.
  • the pull-up control unit 13 is configured to provide the voltage of the first power supply voltage terminal VGH to the second node N2 or under the control of a second clock signal from the second clock signal terminal under the control of the input signal The voltage of the second power supply voltage terminal VGL is supplied to the second node N2.
  • the first end of the pull-down unit 14 is connected to the first node N1, the second end is connected to the third clock signal terminal CK3, and the third end is connected to the output terminal OUTPUT.
  • the pull-down unit 14 is configured to supply a third clock signal from the third clock signal terminal CK3 to the output terminal OUTPUT under the control of the voltage of the first node N1.
  • the first end of the pull-down control unit 15 is connected to the first power voltage terminal VGH, the second end is connected to the first node N1, and the third end is connected to the second node N2.
  • the pull-down control unit 15 is configured to provide the voltage of the first power voltage terminal VGH to the voltage under the control of the voltage of the second node N2 The first node N1.
  • the first end of the first noise reduction unit 16 is connected to the third clock signal terminal CK3, the second end is connected to the output terminal OUTPUT, and the third end is connected to the third node N3.
  • the first noise reduction unit 16 is configured to reduce leakage of the first node N1 by the input unit 11 by adjusting a voltage of the third node N3.
  • the first end of the second noise reduction unit 17 is connected to the fourth node N4, the second end is connected to the first node N1, and the third end is connected to the second power voltage terminal VGL.
  • the second noise reduction unit 17 is configured to reduce leakage of the first node N1 by the pull-down control unit 15 by adjusting the voltage of the fourth node N4.
  • the third node N3 is a connection point of the first noise reduction unit 16 and the input unit 11, and the fourth node N4 is a connection point of the second noise reduction unit 17 and the pull-down control unit 15.
  • the first noise reduction unit 16 and the second noise reduction unit 17 reduce the level of the first node N1 by reducing the leakage of the first node N1 by the input unit 11 and the pull-down control unit 15, thereby reducing the output of the shift register. noise.
  • the duty ratios of the first, second, and third clock signals of the first, second, and third clock signal terminals are all 33%.
  • the first power supply voltage terminal VGH is a high power supply voltage terminal
  • the second power supply voltage terminal VGL is a low power supply voltage terminal.
  • FIG. 2 shows an example circuit configuration diagram of a shift register according to an embodiment of the present disclosure.
  • the transistors in FIG. 2 are P-type transistors that are turned on when the gate is input with a low level.
  • the input unit 11 includes a first transistor M1 and a second transistor M2.
  • the gate of the first transistor M1 is connected to the first clock signal terminal CK1, the first pole is connected to the input terminal INPUT, and the second pole is connected to the third node N3.
  • the gate of the second transistor M2 is connected to the first clock signal terminal CK1, the first pole is connected to the third node N3, and the second pole is connected to the first node N1.
  • the first clock signal of the first clock signal terminal CK1 is at a low level
  • the first transistor M1 and the second transistor M2 are respectively turned on, and the input signal of the input terminal INPUT is transmitted to the first node N1.
  • the pull up unit 12 includes a third transistor M3 and a first capacitor C1.
  • the gate of the third transistor M3 is connected to the second node N2, the first pole is connected to the first power voltage terminal VGH, and the second pole is connected to the output terminal OUTPUT.
  • First end and second section of the first capacitor C1 The point N2 is connected, and the second end is connected to the first power voltage terminal VGH.
  • the third transistor M3 is turned on, and the voltage VGH of the first power supply voltage terminal is supplied to the output terminal OUTPUT.
  • the pull-up control unit 13 includes a fourth transistor M4 and a fifth transistor M5.
  • the gate of the fourth transistor M4 is connected to the input terminal INPUT, the first pole is connected to the first power supply voltage terminal VGH, and the second pole is connected to the second node N2.
  • the gate of the fifth transistor M5 is connected to the second clock signal terminal CK2, the first pole is connected to the second node N2, and the second pole is connected to the second power supply voltage terminal VGL.
  • the fifth transistor M5 when the second clock signal at the second clock signal terminal CK2 is at a low level, the fifth transistor M5 is turned on, and the voltage of the second power source voltage terminal VGL is supplied to the second node N2; at the input end When the input signal at the INPUT is at a low level, the fourth transistor M4 is turned on, and the voltage of the first power supply voltage terminal VGH is supplied to the second node N2.
  • the pull down unit 14 includes a sixth transistor M6 and a second capacitor C2.
  • the gate of the sixth transistor M6 is connected to the first node N1, the first pole is connected to the output terminal OUTPUT, and the second pole is connected to the third clock signal terminal CK3.
  • the first end of the second capacitor C2 is connected to the first node N1, and the second end is connected to the output terminal OUTPUT.
  • the pull-down control unit 15 includes a seventh transistor M7 and an eighth transistor M8.
  • the gate of the seventh transistor M7 is connected to the second node N2, the first pole is connected to the first power supply voltage terminal VGH, and the second pole is connected to the fourth node N4.
  • the gate of the eighth transistor M8 is connected to the second node N2, the first end is connected to the fourth node N4, and the second end is connected to the first node N1.
  • the seventh transistor M7 and the eighth transistor M8 are respectively turned on, and the voltage of the first power supply voltage terminal VGH is supplied to the first node N1.
  • the first noise reduction unit 16 includes a ninth transistor M9 whose gate is connected to the output terminal OUTPUT, the first pole is connected to the third clock signal terminal CK3, and the second pole is connected to the third node N3. .
  • the output signal at the output terminal OUTPUT is at a low level and when the third clock signal from the third clock signal terminal CK3 is at a low level, the ninth transistor M9 is turned on, so that the voltage of the third node N3 is pulled low, thereby reducing
  • the leakage of the second transistor M2 to the first node N1 is reduced, and the influence on the level of the first node N1 is reduced, that is, the influence on the gate level of the driving transistor, that is, the sixth transistor M6 is reduced.
  • the noise at the output of the shift register is reduced, and the driving capability of the driving transistor is improved.
  • the second noise reduction unit 17 includes a tenth transistor M10 having a gate connected to the first node N1, a first pole connected to the fourth node N4, and a second pole and a second power voltage terminal VGL. connection.
  • the tenth transistor M10 When the voltage of the first node N1 is at a low level, the tenth transistor M10 is turned on, so that the voltage of the fourth node N4 is pulled down, thereby reducing the leakage of the eighth transistor M8 to the first node N1, reducing the pair
  • the influence of the level of the first node N1 is such that the level of the first node N1 can be kept at a low level all the time, that is, the influence on the gate level of the driving transistor, that is, the sixth transistor M6 is reduced, The output noise is reduced and the driving capability of the driving transistor is improved.
  • FIG. 3 is a timing chart when the shift register of FIG. 2 is scanned. A specific operation of the shift register according to an embodiment of the present disclosure at the time of scanning will be described below with reference to FIGS. 2 and 3.
  • the first power voltage terminal VGH is a high power voltage terminal
  • the second power voltage terminal VGL is a low power voltage terminal
  • the signal input to the input terminal INPUT and the first clock signal of the first clock signal terminal CK1 are at a low level VL (which also represents the level of the second power supply voltage terminal VGL in this embodiment).
  • the third clock signal of the third clock signal terminal CK3 is at the high level VH (which also represents the level of the first power source voltage terminal VGH in this embodiment).
  • the first transistor M1 and the second transistor M2 are turned on, and the low-level signal of the input terminal INPUT is transmitted to the first node N1, and the first node N1 is at a low level.
  • the first node N1 level is VL+
  • the fourth transistor M4 is turned on, pulling the level of the second node N2 to the high level of the first power supply voltage terminal VGH, and the third transistor M3 is turned off.
  • the signal input to the input terminal INPUT and the first clock signal of the first clock signal terminal CK1 are at a high level VH, and the third clock signal at the third clock signal terminal CK3 is at a low level VL. . Since the sixth transistor M6 is turned on in the t1 phase, the third clock signal of the third clock signal terminal CK3 is at a low level, so the output terminal OUTPUT outputs an output signal of a low level. Since the first clock signal of the first clock signal terminal CK1 is at a high level, the first transistor M1 and the second transistor M2 are turned off.
  • the level of the second node N2 is pulled to a high level in the t1 phase, so the seventh transistor M7 and the eighth transistor M8 are turned off, and the gate of the sixth transistor M6 is in a floating state. Since the capacitor has the characteristic of keeping the voltage difference between the two ends constant, the voltage difference between the second capacitor C2 (VL+
  • the sixth transistor M6 operates in the linear region, and the third clock signal of the third clock signal terminal CK3 is transmitted to the output terminal OUTPUT without a threshold loss, and the output terminal OUTPUT output signal has a level of VL.
  • the low-level output terminal OUTPUT output signal turns on the ninth transistor M9, and the level of the third node N3 is pulled low, reducing the leakage current of the second transistor M2, thereby reducing the first
  • the influence of the level of the node N1 that is, the influence on the gate level of the driving transistor (the sixth transistor M6), reduces the noise at the output of the shift register.
  • the level of the first node N1 is at a low level, and the tenth transistor M10 is turned on, pulling the level of the fourth node N4 low, thereby reducing the leakage current of the eighth transistor M8, thereby reducing the first
  • the influence of the level of the node N1 is such that the level of the first node N1 can be kept at a low level all the time, that is, the influence on the gate level of the driving transistor (the sixth transistor M6) is reduced, and the output is lowered.
  • the terminal noise increases the driving capability of the driving transistor.
  • this phase is divided into two sub-phases.
  • the third clock signal of the third clock signal terminal CK3 jumps at a high level VH
  • the second capacitor C2 has a characteristic of maintaining the voltage difference between the two ends thereof, so that the level of the first node N1 is also Jump to VL+
  • the sixth transistor M6 is still in an on state, and pulls up the level of the output terminal OUTPUT output signal to the high level VH of the third clock signal of the third clock signal terminal CK3.
  • the second clock signal of the second clock signal terminal CK2 jumps to a low level
  • the fifth transistor M5 is turned on
  • the level of the second node N2 is pulled low
  • the third transistor M3 is turned on
  • the level of the output OUTPUT output signal is maintained at a high level VH.
  • the seventh transistor M7 and the eighth transistor M8 are turned on, the level of the first node N1 is pulled to the high level VH, and the sixth transistor M6 is turned off.
  • the second clock signal of the second clock signal terminal CK2 periodically jumps to a low level, and the level of the second node N2 is kept at a low level, so the third transistor M3 remains Turn on, and stabilize the level of the output OUTPUT output signal at a high level VH.
  • the low level of the second node N2 turns on the seventh transistor M7 and the eighth transistor M8, and stabilizes the level of the first node N1 at the high level VH.
  • the first clock signal of the first clock signal terminal CK1 periodically jumps to a low level, and also turns on the first transistor M1 and the second transistor M2 to stabilize the level of the first node N1. At high level VH. Thereby ensuring a stable output of the output terminal OUTPUT, reducing noise.
  • the shift register receives the low level signal of the input terminal INPUT and re-executes the above stages.
  • the duty ratios of the first, second, and third clock signals of the first, second, and third clock signal terminals are all 33%.
  • the shift register according to an embodiment of the present disclosure adopts a series transistor structure (for example, M1 and M2 are connected in series, and M7 and M8 are connected in series), and the corresponding power is connected at a connection point (for example, N3, N4) of the series transistor by timing control.
  • a series transistor structure for example, M1 and M2 are connected in series, and M7 and M8 are connected in series
  • the corresponding power is connected at a connection point (for example, N3, N4) of the series transistor by timing control.
  • Flattening to reduce its leakage current for example, reducing the leakage current of the second transistor M2 and the leakage current of the eighth transistor M8
  • reducing the pull-down phase ie, the output phase
  • the influence of the level of the first node N1 thereby eliminating the noise at the output, improves the driving capability of the shift register.
  • the present disclosure also provides a driving method of the above shift register.
  • the method will be described below with reference to Figs. 1 and 3.
  • the shift register includes an input unit 11, a pull-up unit 12, a pull-up control unit 13, a pull-down unit 14, a pull-down control unit 15, a first noise reduction unit 16, and a
  • the second noise reduction unit 17 the driving method of the shift register comprises:
  • the input signal is provided by the input unit 11 to the first node N1;
  • the voltage of the first power voltage terminal VGH is supplied to the output terminal OUTPUT of the shift register by the pull-up unit 12;
  • the voltage of the first power voltage terminal VGH or the voltage of the second power voltage terminal VGL is supplied to the second node N2 by the pull-up control unit 13;
  • the third clock signal from the third clock signal terminal CK3 is supplied to the output terminal OUTPUT by the pull-down unit 14;
  • the first power supply voltage terminal VGH is supplied to the first node N1 by the pull-down control unit 15;
  • the leakage of the first node N1 by the input unit 11 is reduced by the first noise reduction unit 16 by adjusting the voltage of the third node N3;
  • the leakage of the first node N1 by the pull-down control unit 15 is reduced by the second noise reduction unit 17 by adjusting the voltage of the fourth node N4;
  • the first node N1 is a connection point of the input unit 11, the pull-down unit 14, the pull-down control unit 15, and the second noise reduction unit 17, and the second node is the pull-up unit 12, the pull-up control unit 13, and the pull-down control unit 15.
  • Connection point, the third node N3 is the connection of the first noise reduction unit 16 and the input unit 11
  • the fourth node N4 is a connection point of the second noise reduction unit 17 and the pull-down control unit 15.
  • the first power voltage terminal VGH is a high power voltage terminal
  • the second power voltage terminal VGL is a low power voltage terminal
  • the duty ratio of the third clock signal of the third clock signal terminal CK3 is 33%.
  • FIGS. 5-6 respectively show the shift register of FIG. 2 and the shift register of FIG. 4 respectively driving the transistors under the same circuit parameter conditions. Comparison of gate level and output level.
  • the shift register of the embodiment of the present disclosure is compared with the driving capability of a known shift register shown in FIG. 4, in terms of device size, device model, driving pulse width, and Under the same conditions of load (10k ⁇ , 60pF), it can be seen that in the output stage, the gate level of the driving transistor in the shift register of the embodiment of the present disclosure is higher than the gate of the driving transistor of the known shift register. The low level holding effect is better, and therefore the output level of the driving transistor in the shift register of the embodiment of the present disclosure is correspondingly smaller than the output level of the driving transistor of the known shift register.
  • the shift register according to an embodiment of the present disclosure adopts a series transistor structure, and by timing control, a corresponding level is connected at a connection point of the series transistor to reduce its leakage current, and a pull-down phase (ie, an output stage) is applied to the driving transistor.
  • a pull-down phase ie, an output stage
  • the effect of the gate level which eliminates the noise at the output, improves the drive capability of the shift register.
  • Embodiments of the present disclosure also provide a gate driving circuit including the shift register in the above embodiment.
  • the shift register in the gate driving circuit has the same advantages as the shift register in the above embodiment, and details are not described herein again.
  • the embodiment of the present disclosure further provides a display device including the gate driving circuit in the above embodiment.
  • the display device may be any product or component having an display function such as an organic light emitting diode display panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a gate driving circuit including the shift register, and a display device In a shift register and a driving method thereof, a gate driving circuit including the shift register, and a display device according to an embodiment of the present disclosure, a series transistor structure is employed, and a timing is controlled to access a corresponding point at a connection point of the series transistor The level reduces the leakage current of the gate level of the driving transistor in the output stage, thereby reducing the noise at the output of the shift register, and improving the driving capability of the shift register.

Abstract

一种移位寄存器及其驱动方法、栅极驱动电路和显示装置。该移位寄存器包含输入单元(11)，配置为将输入信号提供至第一节点(N1)；上拉单元(12)，配置为将第一电源电压端(VGH)的电压提供给输出端(OUTPUT)；上拉控制单元(13)，配置为将第一电源电压端(VGH)或第二电源电压端(VGL)的电压提供给第二节点(N2)；下拉单元(14)，配置为将第三时钟信号(CK3)提供给输出端(OUTPUT)；下拉控制单元(15)，配置为将第一电源电压端(VGH)的电压提供给第一节点(N1)；第一降噪单元(16)，配置为通过调节第三节点(N3)的电压，来减小输入单元(11)对第一节点(N1)的漏电；以及第二降噪单元(17)，配置为通过调节第四节点(N4)的电压，来减小下拉控制单元(15)对第一节点(N1)的漏电。可以降低输出端(OUTPUT)的噪声，提高驱动能力。

Description

移位寄存器及其中的驱动方法、栅极驱动电路和显示装置
本申请要求于2016年8月29日递交的中国专利申请第201610754883.4号的优先权，在此全文引用该中国专利申请公开的内容作为本申请的一部分。
技术领域
本公开涉及一种移位寄存器及其中的驱动方法、包括该移位寄存器的栅极驱动电路和显示装置。
背景技术
薄膜晶体管液晶显示器(TFT-LCD)广泛应用于生产生活的各个领域，其采用M*N点排列的逐行扫描矩阵显示。在进行显示时，TFT-LCD通过驱动电路来驱动显示面板中的各个像素进行显示。TFT-LCD的驱动电路主要包含栅极驱动电路和数据驱动电路。其中，数据驱动电路用于依据时钟信号定时将输入的数据顺序锁存并将锁存的数据转换成模拟信号后输入到显示面板的数据线。栅极驱动电路通常用移位寄存器来实现，所述移位寄存器将时钟信号转换成开启/断开电压，分别输出到显示面板的各条栅线上。显示面板上的一条栅线通常与一个移位寄存器(即移位寄存器的一级)对接。通过使得各个移位寄存器依序轮流输出开启电压，实现对显示面板中像素的逐行扫描。
在显示领域，为了不断改善显示画面，提高用户体验，高清、高像素数目(Pixels Per Inch，简称PPI)显示成了研究的热门。但随着像素数目的提高，每一行栅线驱动的像素数目也增大，移位寄存器的负载增大，因此提高移位寄存器的驱动能力十分必要。
发明内容
本公开的至少一个实施例提供了一种移位寄存器及其中的驱动方法。可以降低移位寄存器输出端的噪声，提高移位寄存器的驱动能力。
根据本公开的一方面，公开了一种移位寄存器，包含：
输入单元，其第一端与该移位寄存器的输入端连接用于从该输入端接收输入信号，第二端与第一时钟信号端连接，第三端与第一节点连接，配置为在来自第一时钟信号端的第一时钟信号的控制下将输入信号提供至第一节 点；
上拉单元，其第一端与第一电源电压端连接，第二端与第二节点连接，第三端与该移位寄存器的输出端连接，配置为在第二节点的电压的控制下将所述第一电源电压端的电压提供给所述输出端；
上拉控制单元，其第一端与第二时钟信号端连接，第二端与第一电源电压端连接，第三端与第二节点连接，第四端与输入端连接，第五端与第二电源电压端连接，配置为在输入信号的控制下将所述第一电源电压端的电压提供给所述第二节点或是在来自第二时钟信号端的第二时钟信号的控制下将所述第二电源电压端的电压提供给所述第二节点；
下拉单元，其第一端与第一节点连接，第二端与第三时钟信号端连接，第三端与输出端连接，配置为在第一节点的电压的控制下将来自第三钟信号端的第三时钟信号提供给所述输出端；
下拉控制单元，其第一端与第一电源电压端连接，第二端与第一节点连接，第三端与第二节点连接，配置为在第二节点的电压的控制下将所述第一电源电压端的电压提供给所述第一节点；
第一降噪单元，其第一端与第三时钟信号端连接，第二端与输出端连接，第三端与第三节点连接，配置为通过调节所述第三节点的电压，来减小所述输入单元对第一节点的漏电；以及
第二降噪单元，其第一端与第四节点连接，第二端与第一节点连接，第三端与第二电源电压端连接，配置为通过调节所述第四节点的电压，来减小所述下拉控制单元对第一节点的漏电；
其中，第三节点是第一降噪单元和输入单元的连接点，第四节点是第二降噪单元和下拉控制单元的连接点。
例如，输入单元包括：第一晶体管，其栅极与第一时钟信号端连接，第一极与输入端连接，第二极与第三节点连接；以及第二晶体管，其栅极与第一时钟信号端连接，第一极与第三节点连接，第二极与第一节点连接。
例如，上拉单元包括：第三晶体管，其栅极与第二节点连接，第一极与第一电源电压端连接，第二极与输出端连接；以及第一电容，其第一端与第二节点连接，第二端与第一电源电压端连接。
例如，上拉控制单元包括：第四晶体管，其栅极与输入端连接，第一极与第一电源电压端连接，第二极与第二节点连接；以及第五晶体管，其栅极 与第二时钟信号端连接，第一极与第二节点连接，第二极与第二电源电压端连接。
例如，下拉单元包括：第六晶体管，其栅极与第一节点连接，第一极与输出端连接，第二极与第三时钟信号端连接；以及第二电容，其第一端与第一节点连接，第二端与输出端连接。
例如，下拉控制单元包括：第七晶体管，其栅极与第二节点连接，第一极与第一电源电压端连接，第二极与第四节点连接；以及第八晶体管，其栅极与第二节点连接，第一端与第四节点连接，第二端与第一节点连接。
例如，第一降噪单元包括：第九晶体管，其栅极与输出端连接，第一极与第三时钟信号端连接，第二极与第三节点连接。
例如，第二降噪单元包括：第十晶体管，其栅极与第一节点连接，第一极与第四节点连接，第二极与第二电源电压端连接。
例如，上述晶体管均为P型晶体管。
例如，上述第一、第二和第三时钟信号端的第一、第二和第三时钟信号的占空比均为33％。
例如，第一电源电压端是高电源电压端，第二电源电压端是低电源电压端。
根据本公开的又一方面，公开了一种应用于移位寄存器的驱动方法，该移位寄存器包含输入单元、上拉单元、上拉控制单元、下拉单元、下拉控制单元、第一降噪单元和第二降噪单元，该驱动方法包含：
由输入单元将输入信号提供至第一节点；
由上拉单元将第一电源电压端的电压提供给该移位寄存器的输出端；
由上拉控制单元将第一电源电压端的电压或第二电源电压端的电压提供给第二节点；
由下拉单元将来自第三钟信号端的第三时钟信号提供给所述输出端；
由下拉控制单元将所述第一电源电压端的电压提供给所述第一节点；
由第一降噪单元通过调节第三节点的电压，来减小所述输入单元对第一节点的漏电；
由第二降噪单元通过调节第四节点的电压，来减小所述下拉控制单元对第一节点的漏电；
其中，第一节点是输入单元、下拉单元、下拉控制单元和第二降噪单元 的连接点，第二节点是上拉单元、上拉控制单元和下拉控制单元的连接点，第三节点是第一降噪单元和输入单元的连接点，第四节点是第二降噪单元和下拉控制单元的连接点。
例如，第一电源电压端是高电源电压端，第二电源电压端是低电源电压端。
例如，上述第三时钟信号端的第三时钟信号的占空比为33％。
本公开的另一方面还提供一种栅极驱动电路，所述栅极驱动电路包括上述移位寄存器。
本公开的另一方面还提供一种显示装置，所述显示装置包括上述栅极驱动电路。
在根据本公开实施例的移位寄存器及其中的驱动方法、包括该移位寄存器的栅极驱动电路和显示装置中，采用串联晶体管结构，通过时序控制，在串联晶体管的连接点处接入相应的电平来降低驱动晶体管的栅极电平在输出阶段的漏电流，进而降低移位寄存器输出端的噪声，提高了移位寄存器的驱动能力。
附图说明
图1示出了根据本公开实施例的移位寄存器的框图；
图2示出了根据本公开实施例的移位寄存器的一种示例电路结构图；
图3示出了图2中的移位寄存器进行扫描时的时序图；
图4示出了一种已知移位寄存器的电路结构图；
图5示出了图2中的移位寄存器与图4中的移位寄存器在相同电路参数条件下各自驱动晶体管的栅极电平的比较图；
图6示出了图2中的移位寄存器与图4中的移位寄存器在相同电路参数条件下各自驱动晶体管的输出电平的比较图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本实施例中，每个晶体管的漏极和源极的连接方式可以互换，因此，本公开实施例中各晶体管的漏极、源极实际是没有区别的。这里，仅仅是为了区分晶体管除栅极之外的两极，而将其中一极称为漏极，另一极称为源极。
本公开提出一种移位寄存器，可以有效降低输出端噪声，提高移位寄存器的驱动能力。
图1示出了根据本公开实施例的移位寄存器的框图。如图1所示，在一个实施例中，该移位寄存器包括输入单元11、上拉单元12、上拉控制单元13、下拉单元14、下拉控制单元15、第一降噪单元16和第二降噪单元17。
输入单元11的第一端与该移位寄存器的输入端INPUT连接用于从该输入端INPUT接收输入信号，第二端与第一时钟信号端CK1连接，第三端与第一节点N1连接。该输入单元11被配置为在第一时钟信号端CK1处的第一时钟信号的控制下将所接收的输入信号传递到第一节点N1。
上拉单元12的第一端与第一电源电压端VGH连接，第二端与第二节点N2连接，第三端与该移位寄存器的输出端OUTPUT连接。该上拉单元12被配置为在第二节点N2的电压的控制下将所述第一电源电压端的电压VGH提供给所述输出端OUTPUT。
上拉控制单元13的第一端与第二时钟信号端CK2连接，第二端与第一电源电压端VGH连接，第三端与第二节点N2连接，第四端与输入端INPUT连接，第五端与第二电源电压端VGL连接。该上拉控制单元13被配置为在输入信号的控制下将所述第一电源电压端VGH的电压提供给所述第二节点N2或是在来自第二时钟信号端的第二时钟信号的控制下将所述第二电源电压端VGL的电压提供给所述第二节点N2。
下拉单元14的第一端与第一节点N1连接，第二端与第三时钟信号端CK3连接，第三端与输出端OUTPUT连接。该下拉单元14被配置为在第一节点N1的电压的控制下将来自第三时钟信号端CK3的第三时钟信号提供给所述输出端OUTPUT。
下拉控制单元15的第一端与第一电源电压端VGH连接，第二端与第一节点N1连接，第三端与第二节点N2连接。该下拉控制单元15被配置为在第二节点N2的电压的控制下将所述第一电源电压端VGH的电压提供给所述 第一节点N1。
第一降噪单元16的第一端与第三时钟信号端CK3连接，第二端与输出端OUTPUT连接，第三端与第三节点N3连接。该第一降噪单元16被配置为通过调节所述第三节点N3的电压，来减小所述输入单元11对第一节点N1的漏电。
第二降噪单元17的第一端与第四节点N4连接，第二端与第一节点N1连接，第三端与第二电源电压端VGL连接。该第二降噪单元17被配置为通过调节所述第四节点N4的电压，来减小所述下拉控制单元15对第一节点N1的漏电。
第三节点N3是第一降噪单元16和输入单元11的连接点，第四节点N4是第二降噪单元17和下拉控制单元15的连接点。
第一降噪单元16和第二降噪单元17通过减小输入单元11和下拉控制单元15对第一节点N1的漏电，维持第一节点N1的电平，来降低该移位寄存器的输出端的噪声。
上述第一、第二和第三时钟信号端的第一、第二和第三时钟信号的占空比均为33％。
第一电源电压端VGH是高电源电压端，第二电源电压端VGL是低电源电压端。
图2示出了根据本公开实施例的移位寄存器的一种示例电路结构图。下面以图2中的晶体管均为在栅极输入低电平时导通的P型晶体管为例进行说明。
如图2所示，在一个实施例中，例如，输入单元11包括第一晶体管M1以及第二晶体管M2。第一晶体管M1的栅极与第一时钟信号端CK1连接，第一极与输入端INPUT连接，第二极与第三节点N3连接。第二晶体管M2的栅极与第一时钟信号端CK1连接，第一极与第三节点N3连接，第二极与第一节点N1连接。在第一时钟信号端CK1的第一时钟信号处于低电平时，第一晶体管M1和第二晶体管M2分别导通，将输入端INPUT的输入信号传递到第一节点N1。
在一个实施例中，例如，上拉单元12包括第三晶体管M3和第一电容C1。第三晶体管M3的栅极与第二节点N2连接，第一极与第一电源电压端VGH连接，第二极与输出端OUTPUT连接。第一电容C1的第一端与第二节 点N2连接，第二端与第一电源电压端VGH连接。在第二节点N2的电压处于低电平时，第三晶体管M3导通，将所述第一电源电压端的电压VGH提供给所述输出端OUTPUT。
在一个实施例中，例如，上拉控制单元13包括第四晶体管M4和第五晶体管M5。第四晶体管M4的栅极与输入端INPUT连接，第一极与第一电源电压端VGH连接，第二极与第二节点N2连接。第五晶体管M5的栅极与第二时钟信号端CK2连接，第一极与第二节点N2连接，第二极与第二电源电压端VGL连接。例如，在第二时钟信号端CK2处的第二时钟信号处于低电平时，第五晶体管M5导通，将所述第二电源电压端VGL的电压提供给所述第二节点N2；在输入端INPUT处的输入信号处于低电平时，第四晶体管M4导通，将所述第一电源电压端VGH的电压提供给所述第二节点N2。
在一个实施例中，例如，下拉单元14包括第六晶体管M6和第二电容C2。第六晶体管M6的栅极与第一节点N1连接，第一极与输出端OUTPUT连接，第二极与第三时钟信号端CK3连接。第二电容C2的第一端与第一节点N1连接，第二端与输出端OUTPUT连接。在第一节点N1的电压处于低电平时，第六晶体管M6导通，将来自第三时钟信号端CK3的第三时钟信号提供给所述输出端OUTPUT。
在一个实施例中，例如，下拉控制单元15包括第七晶体管M7和第八晶体管M8。第七晶体管M7的栅极与第二节点N2连接，第一极与第一电源电压端VGH连接，第二极与第四节点N4连接。第八晶体管M8的栅极与第二节点N2连接，第一端与第四节点N4连接，第二端与第一节点N1连接。在第二节点N2的电压处于低电平时，第七晶体管M7和第八晶体管M8分别导通，将所述第一电源电压端VGH的电压提供给所述第一节点N1。
在一个实施例中，例如，第一降噪单元16包括第九晶体管M9，其栅极与输出端OUTPUT连接，第一极与第三时钟信号端CK3连接，第二极与第三节点N3连接。在输出端OUTPUT的输出信号处于低电平并且当来自第三时钟信号端CK3的第三时钟信号处于低电平时，第九晶体管M9导通，使得第三节点N3的电压被拉低，从而减小上述第二晶体管M2对第一节点N1的漏电，减小了对第一节点N1的电平的影响，即，减小了对驱动晶体管，即，第六晶体管M6的栅极电平的影响，降低了该移位寄存器的输出端的噪声，提高驱动晶体管的驱动能力。
在一个实施例中，例如，第二降噪单元17包括第十晶体管M10，其栅极与第一节点N1连接，第一极与第四节点N4连接，第二极与第二电源电压端VGL连接。在第一节点N1的电压处于低电平时，第十晶体管M10导通，使得第四节点N4的电压被拉低，从而减小上述第八晶体管M8对第一节点N1的漏电，减小了对第一节点N1的电平的影响，使得第一节点N1的电平可以一直保持较低的电平，即，减小了对驱动晶体管，即，第六晶体管M6的栅极电平的影响，降低了输出端噪声，提高驱动晶体管的驱动能力。
能够理解，图2中所示出的输入单元11、上拉单元12、上拉控制单元13、下拉单元14、下拉控制单元15、第一降噪单元16和第二降噪单元17的具体电路结构仅仅是一种示例，各个单元也可以采用其他适当的电路结构，只要能分别实现各自的功能即可，本发明对此不做限制。
图3示出了图2中的移位寄存器进行扫描时的时序图。下面结合图2和图3对根据本公开实施例的移位寄存器在扫描时的具体工作过程进行描述。
在本实施例中，第一电源电压端VGH是高电源电压端，第二电源电压端VGL是低电源电压端。
在第一阶段t1(输入阶段)，输入端INPUT输入的信号和第一时钟信号端CK1的第一时钟信号处于低电平VL(在本实施例中也代表第二电源电压端VGL的电平)，第三时钟信号端CK3的第三时钟信号处于高电平VH(在本实施例中也代表第一电源电压端VGH的电平)。第一晶体管M1和第二晶体管M2导通，将输入端INPUT的低电平信号传递到第一节点N1，此时第一节点N1处于低电平。由于P型晶体管传递低电平有阈值损失，所以第一节点N1电平为VL+|vthp|，其中vthp代表晶体管的阈值电压(在本实施例中假定所有晶体管的阈值电压相等)。由于第一节点N1处于低电平，驱动晶体管，即，第六晶体管M6导通。因为第三时钟信号端CK3的第三时钟信号处于高电平VH，输出端OUTPUT输出高电平的输出信号。同时，由于输入端INPUT输入的信号处于低电平，第四晶体管M4导通，将第二节点N2的电平拉至第一电源电压端VGH的高电平，第三晶体管M3截止。
在第二阶段t2(下拉阶段)，输入端INPUT输入的信号和第一时钟信号端CK1的第一时钟信号处于高电平VH，第三时钟信号端CK3的第三时钟信号处于低电平VL。由于在t1阶段第六晶体管M6导通，第三时钟信号端CK3的第三时钟信号处于低电平，因此输出端OUTPUT输出低电平的输出信号。 由于第一时钟信号端CK1的第一时钟信号处于高电平，第一晶体管M1和第二晶体管M2截止。第二节点N2的电平在t1阶段被拉至高电平，所以第七晶体管M7和第八晶体管M8截止，第六晶体管M6的栅极处于悬空状态。由于电容具有保持其两端电压差不变的特性，因此第二电容C2两端电压差(VL+|Vthp|-VH)保持不变，所以第一节点N1的电平会随着输出端OUTPUT的电平的降低而降低，最后稳定在2VL+|Vthp|-VH。第六晶体管M6工作在线性区，第三时钟信号端CK3的第三时钟信号无阈值损失地传递到输出端OUTPUT，输出端OUTPUT输出信号的电平为VL。在此过程中，低电平的输出端OUTPUT输出信号将第九晶体管M9开启，第三节点N3的电平被拉低，减小了第二晶体管M2的漏电流，从而减小了对第一节点N1的电平的影响，即，减小了对驱动晶体管(第六晶体管M6)的栅极电平的影响，降低了该移位寄存器的输出端的噪声。同时，第一节点N1的电平处于低电平，第十晶体管M10导通，将第四节点N4的电平拉低，从而减小第八晶体管M8的漏电流，从而减小了对第一节点N1的电平的影响，使得第一节点N1的电平可以一直保持较低的电平，即，减小了对驱动晶体管(第六晶体管M6)的栅极电平的影响，降低了输出端噪声，提高驱动晶体管的驱动能力。
在第三阶段t3(上拉阶段)，此阶段分为两个子阶段。在第一子阶段，第三时钟信号端CK3的第三时钟信号跳变处于高电平VH，第二电容C2具有保持其两端电压差不变的特性，因此第一节点N1的电平也跳变至VL+|Vthp|。第六晶体管M6仍处于开启状态，将输出端OUTPUT输出信号的电平上拉至第三时钟信号端CK3的第三时钟信号的高电平VH。在第二子阶段，第二时钟信号端CK2的第二时钟信号跳变处于低电平，第五晶体管M5导通，第二节点N2的电平被拉低，第三晶体管M3导通，将输出端OUTPUT输出信号的电平保持在高电平VH。同时第七晶体管M7和第八晶体管M8导通，将第一节点N1的电平拉至高电平VH，第六晶体管M6截止。
在第四阶段t4(保持阶段)，第二时钟信号端CK2的第二时钟信号周期性跳变为低电平，将第二节点N2的电平保持在低电平，所以第三晶体管M3保持导通，将输出端OUTPUT输出信号的电平稳定在高电平VH。第二节点N2的低电平使第七晶体管M7和第八晶体管M8导通，将第一节点N1的电平稳定在高电平VH。第一时钟信号端CK1的第一时钟信号周期性跳变为低电平也将第一晶体管M1和第二晶体管M2导通，将第一节点N1的电平稳定 在高电平VH。从而保证输出端OUTPUT的稳定输出，降低噪声。
此后，直至下一帧到来，所述移位寄存器接收到输入端INPUT的低电平信号后，重新执行上述各阶段。
上述第一、第二和第三时钟信号端的第一、第二和第三时钟信号的占空比均为33％。
根据本公开实施例的移位寄存器采用串联晶体管结构(例如，M1和M2串联，M7和M8串联)，通过时序控制，在串联晶体管的连接点(例如，N3、N4)处接入相应的电平来减小其漏电流(例如，减小了第二晶体管M2的漏电流和第八晶体管M8的漏电流)，降低下拉阶段(即，输出阶段)对驱动晶体管的栅极电平(即，第一节点N1的电平)的影响，进而消除了输出端噪声，提高了移位寄存器的驱动能力。
本公开还提供了一种上述移位寄存器的驱动方法。下面结合图1和图3对该方法进行说明。在一个实施例中，例如，如图1所示，移位寄存器包含输入单元11、上拉单元12、上拉控制单元13、下拉单元14、下拉控制单元15、第一降噪单元16和第二降噪单元17，该移位寄存器的驱动方法包含：
由输入单元11将输入信号提供至第一节点N1；
由上拉单元12将第一电源电压端VGH的电压提供给该移位寄存器的输出端OUTPUT；
由上拉控制单元13将第一电源电压端VGH的电压或第二电源电压端VGL的电压提供给第二节点N2；
由下拉单元14将来自第三钟信号端CK3的第三时钟信号提供给所述输出端OUTPUT；
由下拉控制单元15将所述第一电源电压端VGH的电压提供给所述第一节点N1；
由第一降噪单元16通过调节第三节点N3的电压，来减小所述输入单元11对第一节点N1的漏电；
由第二降噪单元17通过调节第四节点N4的电压，来减小所述下拉控制单元15对第一节点N1的漏电；
其中，第一节点N1是输入单元11、下拉单元14、下拉控制单元15和第二降噪单元17的连接点，第二节点是上拉单元12、上拉控制单元13和下拉控制单元15的连接点，第三节点N3是第一降噪单元16和输入单元11的连 接点，第四节点N4是第二降噪单元17和下拉控制单元15的连接点。
在本实施例中，第一电源电压端VGH是高电源电压端，第二电源电压端VGL是低电源电压端，所述第三时钟信号端CK3的第三时钟信号的占空比为33％。
图4示出了一种已知移位寄存器的电路结构图，图5-6分别示出了图2中的移位寄存器与图4中的移位寄存器在相同电路参数条件下各自驱动晶体管的栅极电平和输出电平的比较图。如图5-6所示，将本公开实施例的移位寄存器与图4所示的已知的一种移位寄存器的驱动能力进行比较，在器件尺寸、器件模型、驱动脉宽、所带负载(10kΩ、60pF)相同的条件下，可以看出，在输出阶段，本公开实施例的移位寄存器中的驱动晶体管的栅极电平比该已知移位寄存器的驱动晶体管的栅极电平在低电位保持效果要好，因此本公开实施例的移位寄存器中的驱动晶体管的输出电平与该已知移位寄存器的驱动晶体管的输出电平相比，其延迟也相应较小。
根据本公开实施例的移位寄存器采用串联晶体管结构，通过时序控制，在串联晶体管的连接点处接入相应的电平来减小其漏电流，降低下拉阶段(即，输出阶段)对驱动晶体管的栅极电平的影响，进而消除了输出端噪声，提高了移位寄存器的驱动能力。
本公开实施例还提供一种栅极驱动电路，包括上述实施例中的移位寄存器。所述栅极驱动电路中的移位寄存器与上述实施例中的移位寄存器具有的优势相同，此处不再赘述。
本公开实施例还提供一种显示装置，所述显示装置包括上述实施例中的栅极驱动电路。示例性地，显示装置可以为有机发光二极管显示面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
在根据本公开实施例的移位寄存器及其驱动方法、包括该移位寄存器的栅极驱动电路和显示装置中，采用串联晶体管结构，通过时序控制，在串联晶体管的连接点处接入相应的电平来降低驱动晶体管的栅极电平在输出阶段的漏电流，进而降低移位寄存器输出端的噪声，提高了移位寄存器的驱动能力。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易 想到的变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种移位寄存器，包含：
    输入单元，其第一端与该移位寄存器的输入端连接用于从该输入端接收输入信号，第二端与第一时钟信号端连接，第三端与第一节点连接，配置为在来自第一时钟信号端的第一时钟信号的控制下将输入信号提供至第一节点；
    上拉单元，其第一端与第一电源电压端连接，第二端与第二节点连接，第三端与该移位寄存器的输出端连接，配置为在第二节点的电压的控制下将所述第一电源电压端的电压提供给所述输出端；
    上拉控制单元，其第一端与第二时钟信号端连接，第二端与第一电源电压端连接，第三端与第二节点连接，第四端与输入端连接，第五端与第二电源电压端连接，配置为在输入信号的控制下将所述第一电源电压端的电压提供给所述第二节点或是在来自第二时钟信号端的第二时钟信号的控制下将所述第二电源电压端的电压提供给所述第二节点；
    下拉单元，其第一端与第一节点连接，第二端与第三时钟信号端连接，第三端与输出端连接，配置为在第一节点的电压的控制下将来自第三钟信号端的第三时钟信号提供给所述输出端；
    下拉控制单元，其第一端与第一电源电压端连接，第二端与第一节点连接，第三端与第二节点连接，配置为在第二节点的电压的控制下将所述第一电源电压端的电压提供给所述第一节点；
    第一降噪单元，其第一端与第三时钟信号端连接，第二端与输出端连接，第三端与第三节点连接，配置为通过调节所述第三节点的电压，来减小所述输入单元对第一节点的漏电；以及
    第二降噪单元，其第一端与第四节点连接，第二端与第一节点连接，第三端与第二电源电压端连接，配置为通过调节所述第四节点的电压，来减小所述下拉控制单元对第一节点的漏电；
    其中，第三节点是第一降噪单元和输入单元的连接点，第四节点是第二降噪单元和下拉控制单元的连接点。
  2. 根据权利要求1所述的移位寄存器，其中，输入单元包括：
    第一晶体管，其栅极与第一时钟信号端连接，第一极与输入端连接，第二 极与第三节点连接；以及
    第二晶体管，其栅极与第一时钟信号端连接，第一极与第三节点连接，第二极与第一节点连接。
  3. 根据权利要求2所述的移位寄存器，其中，上拉单元包括：
    第三晶体管，其栅极与第二节点连接，第一极与第一电源电压端连接，第二极与输出端连接；以及
    第一电容，其第一端与第二节点连接，第二端与第一电源电压端连接。
  4. 根据权利要求3所述的移位寄存器，其中，上拉控制单元包括：
    第四晶体管，其栅极与输入端连接，第一极与第一电源电压端连接，第二极与第二节点连接；以及
    第五晶体管，其栅极与第二时钟信号端连接，第一极与第二节点连接，第二极与第二电源电压端连接。
  5. 根据权利要求4所述的移位寄存器，其中，下拉单元包括：
    第六晶体管，其栅极与第一节点连接，第一极与输出端连接，第二极与第三时钟信号端连接；以及
    第二电容，其第一端与第一节点连接，第二端与输出端连接。
  6. 根据权利要求5所述的移位寄存器，其中，下拉控制单元包括：
    第七晶体管，其栅极与第二节点连接，第一极与第一电源电压端连接，第二极与第四节点连接；以及
    第八晶体管，其栅极与第二节点连接，第一端与第四节点连接，第二端与第一节点连接。
  7. 根据权利要求6所述的移位寄存器，其中，第一降噪单元包括：
    第九晶体管，其栅极与输出端连接，第一极与第三时钟信号端连接，第二极与第三节点连接。
  8. 根据权利要求7所述的移位寄存器，其中，第二降噪单元包括：
    第十晶体管，其栅极与第一节点连接，第一极与第四节点连接，第二极与第二电源电压端连接。
  9. 根据权利要求2-8中任一项所述的移位寄存器，其中，所述晶体管均为P型晶体管。
  10. 根据权利要求1所述的移位寄存器，其中，所述第一、第二和第三时 钟信号端的第一、第二和第三时钟信号的占空比均为33％。
  11. 根据权利要求1所述的移位寄存器，其中，第一电源电压端是高电源电压端，第二电源电压端是低电源电压端。
  12. 一种应用于移位寄存器的驱动方法，该移位寄存器包含输入单元、上拉单元、上拉控制单元、下拉单元、下拉控制单元、第一降噪单元和第二降噪单元，该驱动方法包含：
    由输入单元将输入信号提供至第一节点；
    由上拉单元将第一电源电压端的电压提供给该移位寄存器的输出端；
    由上拉控制单元将第一电源电压端的电压或第二电源电压端的电压提供给第二节点；
    由下拉单元将来自第三钟信号端的第三时钟信号提供给所述输出端；
    由下拉控制单元将所述第一电源电压端的电压提供给所述第一节点；
    由第一降噪单元通过调节第三节点的电压，来减小所述输入单元对第一节点的漏电；
    由第二降噪单元通过调节第四节点的电压，来减小所述下拉控制单元对第一节点的漏电；
    其中，第一节点是输入单元、下拉单元、下拉控制单元和第二降噪单元的连接点，第二节点是上拉单元、上拉控制单元和下拉控制单元的连接点，第三节点是第一降噪单元和输入单元的连接点，第四节点是第二降噪单元和下拉控制单元的连接点；
    第一电源电压端是高电源电压端，第二电源电压端是低电源电压端；
    所述第三时钟信号端的第三时钟信号的占空比为33％。
  13. 一种栅极驱动电路，包括如权利要求1-11之一所述的移位寄存器。
  14. 一种显示装置，包括如权利要求13所述的栅极驱动电路。
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