WO2016070519A1 - 基于低温多晶硅半导体薄膜晶体管的goa电路 - Google Patents

基于低温多晶硅半导体薄膜晶体管的goa电路 Download PDF

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WO2016070519A1
WO2016070519A1 PCT/CN2015/072376 CN2015072376W WO2016070519A1 WO 2016070519 A1 WO2016070519 A1 WO 2016070519A1 CN 2015072376 W CN2015072376 W CN 2015072376W WO 2016070519 A1 WO2016070519 A1 WO 2016070519A1
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transistor
electrically connected
node
constant voltage
potential
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PCT/CN2015/072376
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English (en)
French (fr)
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肖军城
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深圳市华星光电技术有限公司
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Priority to KR1020177007070A priority Critical patent/KR101937064B1/ko
Priority to US14/422,694 priority patent/US9553577B2/en
Priority to JP2017522826A priority patent/JP6415713B2/ja
Priority to GB1703584.1A priority patent/GB2545127B/en
Publication of WO2016070519A1 publication Critical patent/WO2016070519A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a GOA circuit based on a low temperature polysilicon semiconductor thin film transistor.
  • GOA Gate Drive On Array
  • TFT thin film transistor
  • Array liquid crystal display array
  • the GOA circuit is mainly composed of a pull-up part, a pull-up control part, a transfer part, a pull-down part, and a pull-down sustain circuit part (
  • the pull-down holding part and the boost part responsible for the potential rise are generally composed of a bootstrap capacitor.
  • the pull-up portion is mainly responsible for outputting an input clock signal (Clock) to the gate of the thin film transistor as a driving signal of the liquid crystal display.
  • the pull-up control part is mainly responsible for controlling the opening of the pull-up part, which is generally a signal transmitted by the upper-level GOA circuit.
  • the pull-down portion is mainly responsible for quickly pulling the scan signal (that is, the potential of the gate of the thin film transistor) to a low level after outputting the scan signal.
  • the pull-down sustain circuit portion is mainly responsible for keeping the scan signal and the signal of the pull-up portion in a closed state (ie, a set negative potential).
  • the rising portion is mainly responsible for the secondary rise of the potential of the pull-up portion to ensure the normal output of the pull-up portion.
  • LTPS-TFT liquid crystal displays have attracted more and more attention.
  • LTPS-TFT liquid crystal displays have high resolution, fast response, high brightness and high opening. Rate and other advantages. Since the low-temperature polysilicon has an order of arrangement of amorphous silicon (a-Si), the low-temperature polysilicon semiconductor itself has an ultra-high electron mobility, which is 100 times higher than that of the amorphous silicon semiconductor, and the gate driver can be fabricated by using GOA technology. On the thin film transistor array substrate, the goal of system integration, space saving and cost of driving the IC are achieved.
  • a-Si amorphous silicon
  • the threshold voltage of a conventional amorphous silicon semiconductor thin film transistor is generally greater than 0 V, and the voltage of the subthreshold region is relatively large with respect to the current, but the threshold voltage of the low temperature polysilicon semiconductor thin film transistor is low (generally about It is about 0V), and the swing of the subthreshold region is small, while the GOA circuit is in the off state, many components operate with threshold voltage.
  • the voltage is close to or even higher than the threshold voltage.
  • the object of the present invention is to provide a GOA circuit based on a low-temperature polysilicon semiconductor thin film transistor, which solves the influence of the low-temperature polysilicon semiconductor thin film transistor's own characteristics on the GOA driving circuit, especially the GOA functionality caused by the leakage problem;
  • the problem that the second node potential cannot be at a higher potential during the non-active period of the pull-down sustain circuit portion.
  • the present invention provides a GOA circuit based on a low temperature polysilicon semiconductor thin film transistor, comprising a plurality of cascaded GOA units, wherein N is a positive integer, and the Nth stage GOA unit includes a pull-up control portion and a pull-up A portion, a first pull-down portion, and a pull-down sustain circuit portion.
  • the pull-up control portion includes a first transistor, and a gate electrode and a source are electrically connected to an output end of the N-1th GOA unit of the upper stage of the Nth stage GOA unit, and the drain is electrically connected. At the first node;
  • the pull-up portion includes a second transistor having a gate electrically connected to the first node, a source electrically connected to the first clock driving signal, and a drain electrically connected to the output terminal;
  • the pull-down maintaining circuit is electrically connected to the first node, the output end, the constant current constant high potential, and the first, second, and third DC constant voltage low potentials;
  • the pull-down sustain circuit portion adopts a high-low potential reverse push design, including:
  • the gate and the source of the third transistor are electrically connected to a DC constant voltage high potential, and the drain is electrically connected to the source of the fifth transistor;
  • the gate of the fourth transistor is electrically connected to the drain of the third transistor, the source is electrically connected to the DC constant voltage high potential, and the drain is electrically connected to the second node;
  • the gate of the fifth transistor is electrically connected to the first node, the source is electrically connected to the drain of the third transistor, and the drain is electrically connected to the first DC constant voltage low potential;
  • the gate of the sixth transistor is electrically connected to the first node, the source is electrically connected to the second node, and the drain is electrically connected to the source of the eighth transistor;
  • An eighth transistor the gate of the eighth transistor is electrically connected to the first node, and the source is electrically Connected to the drain of the sixth transistor, the drain is electrically connected to the third DC constant voltage low potential;
  • the gate of the tenth transistor is electrically connected to the second node, the source is electrically connected to the DC constant voltage high potential, and the drain is electrically connected to the drain of the sixth transistor;
  • the gate of the twelfth transistor is electrically connected to the second node, the source is electrically connected to the first node, and the drain is electrically connected to the second DC constant voltage low potential;
  • the gate of the thirteenth transistor is electrically connected to the second node, the source is electrically connected to the output end, and the drain is electrically connected to the first DC constant voltage low potential;
  • the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor provide a positive high potential for controlling opening of the twelfth transistor and the thirteenth transistor;
  • the eighth transistor constitutes a negative potential during operation Reverse bootstrap for providing a lower potential to the second node during operation; using a DC constant voltage high potential to provide a suitable high potential to the second node during the inactive period such that the first node and the output maintain a low potential;
  • the first pull-down portion is electrically connected to the first node, the second clock driving signal, and the second DC constant voltage low potential, and the first pull-down portion pulls down the first node according to the second clock driving signal a potential to the second DC constant voltage low potential;
  • the first pull-down portion includes a fourteenth transistor, the gate of the fourteenth transistor is electrically connected to the second clock driving signal, the source is electrically connected to the first node, and the drain is electrically connected to the first Two DC constant voltage low potential;
  • the pull-down maintaining portion further includes a ninth transistor, the gate of the ninth transistor is electrically connected to the first node, the source is electrically connected to the gate of the tenth transistor, and the drain is electrically connected to the third DC constant Depressing the potential; the eleventh transistor, the gate and the source of the eleventh transistor are electrically connected to the DC constant voltage high potential, the drain is electrically connected to the gate of the tenth transistor; the gate of the tenth transistor The pole is disconnected from the second node.
  • the fourth transistor, the sixth transistor, and the eighth transistor are connected in series.
  • the GOA circuit based on the low temperature polysilicon semiconductor thin film transistor further includes a rising portion electrically connected between the first node and the output terminal for raising the potential of the first node.
  • the rising portion includes a capacitor, one end of the capacitor is electrically connected to the first node, and the other end is electrically connected to the output end.
  • the waveform duty ratio of the first clock driving signal and the second clock driving signal is less than 50/50; during the high potential of the second clock driving signal, the fourteenth transistor pulls down the potential of the first node to the first Two DC constant voltage low potential.
  • the signal output waveform of the first node changes according to a change in a waveform duty ratio of the first clock driving signal and the second clock driving signal.
  • the signal output waveform of the first node is in a "convex" shape.
  • the gate and the source of the first transistor are electrically connected to the start signal end of the circuit.
  • the GOA circuit uses the output signal of the output end as a signal for transmitting the upper and lower stages.
  • the invention has the beneficial effects that the GOA circuit based on the low temperature polysilicon semiconductor thin film transistor provided by the invention adopts the high and low potential reverse push design in the pull-down sustaining circuit portion, and sets the first, second and third DC constant voltage low potentials which are sequentially lowered.
  • the constant current and high potential of the constant current can solve the influence of the low-temperature polysilicon semiconductor thin film transistor's own characteristics on the GOA driving circuit, especially the GOA functionality caused by the leakage problem; and solve the current GOA based on the low temperature polysilicon semiconductor thin film transistor.
  • the problem that the second node potential cannot be at a higher potential during the non-active period of the pull-down sustain circuit portion in the circuit effectively maintains the low potential of the first node and the output terminal.
  • FIG. 1 is a circuit diagram of a first embodiment of a low temperature polysilicon semiconductor thin film transistor based GOA circuit of the present invention
  • FIG. 2 is a circuit diagram showing a first-stage connection relationship of a first embodiment of a low-temperature polysilicon semiconductor thin film transistor-based GOA circuit according to the present invention
  • FIG. 3 is a circuit diagram of a second embodiment of a low temperature polysilicon semiconductor thin film transistor based GOA circuit of the present invention.
  • FIG. 4 is a first waveform setup and an output waveform diagram of a key node of a GOA circuit based on a low temperature polysilicon semiconductor thin film transistor of the present invention
  • FIG. 5 is a second waveform setting of a GOA circuit based on a low temperature polysilicon semiconductor thin film transistor of the present invention and an output waveform diagram of a key node.
  • the present invention provides a GOA circuit based on a low temperature polysilicon semiconductor thin film transistor.
  • the GOA electricity based on low temperature polysilicon semiconductor thin film transistor The path includes: a plurality of cascaded GOA units, wherein N is a positive integer, and the Nth stage GOA unit includes a pull-up control portion 100, a pull-up portion 200, a first pull-down portion 400, and a pull-down sustain circuit portion 500.
  • a rising portion 300 may also be included.
  • the pull-up control portion 100 includes a first transistor T1 whose gate and source are electrically connected to the output terminal G(N-1) of the upper N-1th GOA unit of the Nth stage GOA unit.
  • the drain is electrically connected to the first node Q(N).
  • the pull-up portion 200 includes a second transistor T2 whose gate is electrically connected to the first node Q(N), the source is electrically connected to the first clock driving signal CKN, and the drain is electrically connected to the output terminal G ( N).
  • the rising portion 300 includes a capacitor Cb. One end of the capacitor Cb is electrically connected to the first node Q(N), and the other end is electrically connected to the output terminal G(N).
  • the pull-down maintaining circuit portion 500 is electrically connected to the first node Q(N), the output terminal G(N), the constant current constant voltage high potential H, and the first, second, and third DC constant voltages are low. Potentials VSS1, VSS2, VSS3.
  • the pull-down maintaining circuit portion 500 includes: a third transistor T3, the gate and the source of the third transistor T3 are electrically connected to the DC constant voltage high potential H, and the drain is electrically connected to the fifth transistor a fourth transistor T4, the gate of the fourth transistor T4 is electrically connected to the drain of the third transistor T3, the source is electrically connected to the DC constant voltage high potential H, and the drain is electrically connected to the drain a second node P(N); a fifth transistor T5, the gate of the fifth transistor T5 is electrically connected to the first node Q(N), and the source is electrically connected to the drain of the third transistor T3, and the drain Electrically connected to the first DC constant voltage low potential VSS1; the sixth transistor T6, the gate of the sixth transistor T6 is electrically
  • the first pull-down portion 400 includes a fourteenth transistor T14.
  • the gate of the fourteenth transistor T14 is electrically connected to the second clock driving signal XCKN, and the source is electrically connected to the first node Q(N).
  • the drain is electrically connected to the second constant voltage low potential VSS2.
  • the first transistor T1 As shown in FIG. 2, in the first-level connection relationship of the GOA circuit, the first transistor T1 The gate and the source are electrically connected to the start signal terminal STV of the circuit.
  • the GOA circuit based on the low temperature polysilicon semiconductor thin film transistor is provided with a DC constant voltage high potential H and three DC constant voltage low potentials VSS1, VSS2, VSS3, and three DC constant voltage low potentials in turn.
  • the third DC constant voltage low potential VSS3 ⁇ the second DC constant voltage low potential VSS2 ⁇ the first DC constant voltage low potential VSS1, the three DC constant voltage low potentials VSS1, VSS2, VSS3 are generally independently controlled, Easy to adjust different potentials.
  • the pull-down maintaining circuit portion 500 adopts a high-low potential reverse thrust design: the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 provide a positive high potential for controlling the twelfth transistor T12 and Opening of the thirteenth transistor T13; the eighth transistor T8 constitutes a reverse bootstrap of a negative potential during operation for pulling the second node P(N) down to a third DC constant voltage low potential during operation
  • the VSS3 potential provides a suitable high potential to the second node P(N) by the DC constant voltage high potential H during the non-active period, so that the first node Q(N) and the output terminal G(N) are maintained at a low potential, eliminating both of them. Ripple voltage.
  • the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 are connected in series to prevent leakage.
  • the number of TFTs can be reduced, the layout space can be saved, and the gate of the tenth transistor T10 is electrically connected to the second node P(N), thereby preventing the potential from being too high. Harm to the tenth transistor T10.
  • the third transistor T3 and the fourth transistor T4 are controlled to be in a conducting state by the DC constant voltage high potential H, and during the inactive period, the fifth transistor T5 and the sixth transistor T6 are turned off.
  • the fourth transistor T4 supplies the constant current high potential H to the second node P(N), and the second node P(N) is at a high potential, the twelfth transistor T12 and the thirteenth transistor T13 are both turned on and passed.
  • the twelfth transistor pulls down the potential of the first node Q(N) to the second DC constant voltage low potential VSS2, and pulls the potential of the output terminal G(N) through the thirteenth transistor to the first DC constant voltage low potential VSS1;
  • the gates of the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are at a high potential from the first node Q(N), and the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are both guided.
  • the gate potential of the fourth transistor T4 is pulled down to the first DC constant voltage low potential VSS1, and the fourth transistor T4 is turned off, and the DC constant voltage high potential H is no longer supplied to the second node P(N).
  • the sixth transistor T6 and the eighth transistor T8 are both turned on, pass the sixth An eighth transistor T6 and transistor T8 pull-down node P (N) to a lower potential to the third DC constant potential down VSS3.
  • the pull-down maintaining circuit portion 500 is matched with a DC constant voltage high potential H and three DC constant voltage low potentials VSS1, VSS2, and VSS3, which can solve the low threshold voltage of the low temperature polysilicon semiconductor thin film transistor and the swing of the subthreshold region.
  • the problem that the potential of the second node cannot be at a higher potential during the non-active period of the pull-down sustain circuit portion effectively maintains the low potential of the first node Q(N) and the output terminal G(N).
  • the rising portion 300 is used to raise the potential of the first node Q(N) during the action.
  • the first pull-down portion 400 is configured to pull down the potential of the first node Q(N) to the second DC constant voltage low potential VSS2 according to the second clock driving signal XCKN during the inactive period.
  • the GOA circuit adopts an output signal of the output terminal G(N) as a signal for transmitting the upper and lower stages, and adopts an output terminal G(N-1) and an Nth stage of the upper N-1th GOA unit of the Nth stage GOA unit.
  • the output terminal G(N) of the GOA unit performs upper and lower level transmission, which can reduce the number of TFTs, thereby achieving the purpose of effectively saving layout and power consumption.
  • FIG. 3 is a circuit diagram of a second embodiment of a low temperature polysilicon semiconductor thin film transistor based GOA circuit of the present invention.
  • the second embodiment is different from the first example in that the pull-down maintaining portion 500 further includes a ninth transistor T9, and the gate of the ninth transistor T9 is electrically connected to the first node Q ( N), the source is electrically connected to the gate of the tenth transistor T10, the drain is electrically connected to the third DC constant voltage low potential VSS3; the eleventh transistor T11, the gate and the source of the eleventh transistor T11 The pole is electrically connected to the DC constant voltage high potential H, and the drain is electrically connected to the gate of the tenth transistor; the gate of the tenth transistor T10 is disconnected from the second node P(N). Except for this, the rest is the same as the first embodiment, and details are not described herein again.
  • FIG. 4 and FIG. 5 are waveform diagrams of output waveforms of the GOA circuits of the low temperature polysilicon semiconductor thin film transistors of the present invention and output waveforms of key nodes, respectively.
  • the signal output waveform of the first node Q(N) changes according to a change in the duty ratio of the waveform of the first clock driving signal CKN and the second clock driving signal XCKN.
  • the waveform duty ratios of the first clock drive signal CKN and the second clock drive signal XCKN shown in FIG. 4 are different from the waveform duty ratios of the first clock drive signal CKN and the second clock drive signal XCKN shown in FIG. 5. .
  • CK1N and CK2N respectively represent the first and second first clock driving signals CKN
  • XCK1N and XCK2N respectively represent the first and second second clock driving signals XCKN, and the first clock driving signal.
  • the waveform duty ratio of CKN and the second clock drive signal XCKN are both less than 50/50; in conjunction with FIG. 1, during the high potential of the second clock drive signal XCKN, the fourteenth transistor T14 pulls down the first node Q ( The potential of N) is to the second constant voltage low potential VSS2.
  • the signal output waveform of the first node Q(N) is in a "convex" shape, and the output terminal G(N) is normally output.
  • the GOA circuit based on the low temperature polysilicon semiconductor thin film transistor of the present invention adopts a high and low potential reverse push design in the pull-down sustaining circuit portion, and sets the first, second, and third DC constant voltage low potentials which are sequentially lowered, and A DC constant voltage high potential can solve the influence of the low-temperature polysilicon semiconductor thin film transistor's own characteristics on the GOA driving circuit, especially the leakage problem
  • the GOA functionality is poor; at the same time, the problem that the second node potential cannot be at a higher potential during the non-active period of the pull-down sustain circuit portion of the GOA circuit based on the low-temperature polysilicon semiconductor thin film transistor is effectively solved, and the first node and the output terminal are effectively maintained. Potential.

Abstract

一种基于低温多晶硅半导体薄膜晶体管的GOA电路，包括级联的多个GOA单元；第N级GOA单元包括一上拉控制部分(100)、一上拉部分(200)、一第一下拉部分(400)、及一下拉维持电路部分(500)；所述下拉维持电路部分(500)采用高低电位反推设计，并设置依次降低的第一、第二、第三直流恒压低电位(VSS1、VSS2、VSS3)、及一直流恒压高电位(H)，能够解决低温多晶硅半导体薄膜晶体管的自身特性对GOA驱动电路的影响，尤其是漏电问题带来的GOA功能性不良；同时解决了目前基于低温多晶硅半导体薄膜晶体管的GOA电路中下拉维持电路部分在非作用期间第二节点电位不能处于较高的电位的问题，有效维持第一节点(Q(N))和输出端(G(N))的低电位。

Description

基于低温多晶硅半导体薄膜晶体管的GOA电路 技术领域
本发明涉及显示技术领域，尤其涉及一种基于低温多晶硅半导体薄膜晶体管的GOA电路。
背景技术
GOA(Gate Drive On Array)，是利用薄膜晶体管(thin film transistor，TFT)液晶显示器阵列(Array)制程将栅极驱动器制作在薄膜晶体管阵列基板上，以实现逐行扫描的驱动方式。
通常，GOA电路主要由上拉部分(Pull-up part)、上拉控制部分(Pull-up control part)、下传部分(Transfer part)、下拉部分(Pull-down part)、下拉维持电路部分(Pull-down Holding part)、以及负责电位抬升的上升部分(Boost part)组成，上升部分一般由一自举电容构成。
上拉部分主要负责将输入的时钟信号(Clock)输出至薄膜晶体管的栅极，作为液晶显示器的驱动信号。上拉控制部分主要负责控制上拉部分的打开，一般是由上级GOA电路传递来的信号作用。下拉部分主要负责在输出扫描信号后，快速地将扫描信号(亦即薄膜晶体管的栅极的电位)拉低为低电平。下拉维持电路部分则主要负责将扫描信号和上拉部分的信号保持在关闭状态(即设定的负电位)。上升部分则主要负责对上拉部分的电位进行二次抬升，确保上拉部分的正常输出。
随着低温多晶硅(Low Temperature Poly-silicon，LTPS)半导体薄膜晶体管的发展，LTPS-TFT液晶显示器也越来越受关注，LTPS-TFT液晶显示器具有高分辨率、反应速度快、高亮度、高开口率等优点。由于低温多晶硅较非晶硅(a-Si)的排列有次序，低温多晶硅半导体本身具有超高的电子迁移率，比非晶硅半导体相对高100倍以上，可以采用GOA技术将栅极驱动器制作在薄膜晶体管阵列基板上，达到系统整合的目标、节省空间及驱动IC的成本。然而，现有技术中针对低温多晶硅半导体薄膜晶体管的GOA电路的开发较少，尤其需要克服很多由于低温多晶硅半导体薄膜晶体管电性本身带来的问题。例如：传统的非晶硅半导体薄膜晶体管的电学特性中阈值电压一般大于0V，而且亚阈值区域的电压相对于电流的摆幅较大，但是低温多晶硅半导体薄膜晶体管的阈值电压值较低(一般约为0V左右)，而且亚阈值区域的摆幅较小，而GOA电路在关态时很多元件操作与阈值电 压接近，甚至高于阈值电压，这样就会由于电路中TFT的漏电和工作电流的漂移，增加LTPS GOA电路设计的难度，很多适用于非晶硅半导体的扫描驱动电路，不能轻易的应用到低温多晶硅半导体的行扫描驱动电路中，会存在一些功能性问题，这样将会直接导致LTPS GOA电路无法工作，所以在设计电路时必须要考虑到低温多晶硅半导体薄膜晶体管的自身特性对GOA电路的影响。
发明内容
本发明的目的在于提供一种基于低温多晶硅半导体薄膜晶体管的GOA电路，解决低温多晶硅半导体薄膜晶体管的自身特性对GOA驱动电路的影响，尤其是漏电问题带来的GOA功能性不良；解决目前基于低温多晶硅半导体薄膜晶体管的GOA电路中下拉维持电路部分在非作用期间第二节点电位不能处于较高的电位的问题。
为实现上述目的，本发明提供一种基于低温多晶硅半导体薄膜晶体管的GOA电路，包括级联的多个GOA单元，设N为正整数，第N级GOA单元包括一上拉控制部分、一上拉部分、一第一下拉部分和一下拉维持电路部分。
所述上拉控制部分包括第一晶体管，其栅极电性与源极均电性连接于该第N级GOA单元的上一级第N-1级GOA单元的输出端，漏极电性连接于第一节点；
所述上拉部分包括第二晶体管，其栅极电性连接于第一节点，源极电性连接于第一时钟驱动信号，漏极电性连接于输出端；
所述下拉维持电路部分电性连接于所述第一节点、输出端、一直流恒压高电位、及第一、第二、与第三直流恒压低电位；
所述下拉维持电路部分采用高低电位反推设计，包括：
第三晶体管，所述第三晶体管的栅极和源极均电性连接于直流恒压高电位，漏极电性连接于第五晶体管的源极；
第四晶体管，所述第四晶体管的栅极电性连接于第三晶体管的漏极，源极电性连接于直流恒压高电位，漏极电性连接于第二节点；
第五晶体管，所述第五晶体管的栅极电性连接于第一节点，源极电性连接于第三晶体管的漏极，漏极电性连接于第一直流恒压低电位；
第六晶体管，所述第六晶体管的栅极电性连接于第一节点，源极电性连接于第二节点，漏极电性连接于第八晶体管的源极；
第八晶体管，所述第八晶体管的栅极电性连接于第一节点，源极电性 连接于第六晶体管的漏极，漏极电性连接于第三直流恒压低电位；
第十晶体管，所述第十晶体管的栅极电性连接于第二节点，源极电性连接于直流恒压高电位，漏极电性连接于第六晶体管的漏极；
第十二晶体管，所述第十二晶体管的栅极电性连接于第二节点，源极电性连接于第一节点，漏极电性连接于第二直流恒压低电位；
第十三晶体管，所述第十三晶体管的栅极电性连接于第二节点，源极电性连接于输出端，漏极电性连接于第一直流恒压低电位；
所述第三晶体管、第四晶体管、第五晶体管、第六晶体管提供正向高电位，用于控制第十二晶体管和第十三晶体管的打开；所述第八晶体管构成作用期间的负电位的反向自举，用于在作用期间向第二节点提供更低电位；利用直流恒压高电位在非作用期间向第二节点提供适当的高电位，使得第一节点与输出端维持低电位；
所述第一下拉部分电性连接于所述第一节点、第二时钟驱动信号及第二直流恒压低电位，所述第一下拉部分依据第二时钟驱动信号下拉所述第一节点的电位至所述第二直流恒压低电位；
所述第一下拉部分包括一第十四晶体管，所述第十四晶体管的栅极电性连接于第二时钟驱动信号，源极电性连接于第一节点，漏极电性连接于第二直流恒压低电位；
所述第三直流恒压低电位＜第二直流恒压低电位＜第一直流恒压低电位。
所述下拉维持部分还包括第九晶体管，所述第九晶体管的栅极电性连接于第一节点，源极电性连接于第十晶体管的栅极，漏极电性连接于第三直流恒压低电位；第十一晶体管，所述第十一晶体管的栅极与源极均电性连接于直流恒压高电位，漏极电性连接于第十晶体管的栅极；第十晶体管的栅极与第二节点断开。
所述第四晶体管、第六晶体管、与第八晶体管串联。
所述基于低温多晶硅半导体薄膜晶体管的GOA电路，还包括一上升部分，所述上升部分电性连接于所述第一节点与输出端之间，用来抬升所述第一节点的电位。
所述上升部分包括一电容，所述电容的一端电性连接于第一节点，另一端电性连接于输出端。
第一时钟驱动信号与第二时钟驱动信号的波形占空比小于50/50；在第二时钟驱动信号的高电位期间，所述第十四晶体管下拉所述第一节点的电位至所述第二直流恒压低电位。
所述第一节点的信号输出波形依据第一时钟驱动信号与第二时钟驱动信号的波形占空比的变化而变化。
所述第一节点的信号输出波形呈“凸”字形。
所述GOA电路的第一级连接关系中，第一晶体管的栅极与源极均电性连接于电路的启动信号端。
所述GOA电路采用输出端的输出信号作为上下级传信号。
本发明的有益效果：本发明提供的基于低温多晶硅半导体薄膜晶体管的GOA电路，在下拉维持电路部分采用高低电位反推设计，并设置依次降低的第一、第二、第三直流恒压低电位、及一直流恒压高电位，能够解决低温多晶硅半导体薄膜晶体管的自身特性对GOA驱动电路的影响，尤其是漏电问题带来的GOA功能性不良；同时解决了目前基于低温多晶硅半导体薄膜晶体管的GOA电路中下拉维持电路部分在非作用期间第二节点电位不能处于较高的电位的问题，有效维持第一节点和输出端的低电位。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为本发明的基于低温多晶硅半导体薄膜晶体管的GOA电路的第一实施例的电路图；
图2为本发明的基于低温多晶硅半导体薄膜晶体管的GOA电路的第一实施例的第一级连接关系的电路图；
图3为本发明的基于低温多晶硅半导体薄膜晶体管的GOA电路的第二实施例的电路图；
图4为本发明的基于低温多晶硅半导体薄膜晶体管的GOA电路的第一种波形设置和关键节点的输出波形图；
图5为本发明的基于低温多晶硅半导体薄膜晶体管的GOA电路的第二种波形设置和关键节点的输出波形图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1-2，本发明提供一种基于低温多晶硅半导体薄膜晶体管的GOA电路。如图1所示，该基于低温多晶硅半导体薄膜晶体管的GOA电 路包括：级联的多个GOA单元，设N为正整数，第N级GOA单元包括一上拉控制部分100、一上拉部分200、一第一下拉部分400和一下拉维持电路部分500；还可包括一上升部分300。
所述上拉控制部分100包括第一晶体管T1，其栅极与源极均电性连接于该第N级GOA单元的上一级第N-1级GOA单元的输出端G(N-1)，漏极电性连接于第一节点Q(N)。
所述上拉部分200包括第二晶体管T2，其栅极电性连接于第一节点Q(N)，源极电性连接于第一时钟驱动信号CKN，漏极电性连接于输出端G(N)。
所述上升部分300包括一电容Cb，所述电容Cb的一端电性连接于第一节点Q(N)，另一端电性连接于输出端G(N)。
所述下拉维持电路部分500电性连接于所述第一节点Q(N)、输出端G(N)、一直流恒压高电位H、及第一、第二、与第三直流恒压低电位VSS1、VSS2、VSS3。具体的，所述下拉维持电路部分500包括：第三晶体管T3，所述第三晶体管T3的栅极和源极均电性连接于直流恒压高电位H，漏极电性连接于第五晶体管T5的源极；第四晶体管T4，所述第四晶体管T4的栅极电性连接于第三晶体管T3的漏极，源极电性连接于直流恒压高电位H，漏极电性连接于第二节点P(N)；第五晶体管T5，所述第五晶体管T5的栅极电性连接于第一节点Q(N)，源极电性连接于第三晶体管T3的漏极，漏极电性连接于第一直流恒压低电位VSS1；第六晶体管T6，所述第六晶体管T6的栅极电性连接于第一节点Q(N)，源极电性连接于第二节点P(N)，漏极电性连接于第八晶体管T8的源极；第八晶体管T8，所述第八晶体管T8的栅极电性连接于第一节点Q(N)，源极电性连接于第六晶体管T6的漏极，漏极电性连接于第三直流恒压低电位VSS3；第十晶体管T10，所述第十晶体管T10的栅极电性连接于第二节点P(N)，源极电性连接于直流恒压高电位H，漏极电性连接于第六晶体管T6的漏极；第十二晶体管T12，所述第十二晶体管T12的栅极电性连接于第二节点P(N)，源极电性连接于第一节点Q(N)，漏极电性连接于第二直流恒压低电位VSS2；第十三晶体管T13，所述第十三晶体管T13的栅极电性连接于第二节点P(N)，源极电性连接于输出端G(N)，漏极电性连接于第一直流恒压低电位VSS1。
所述第一下拉部分400包括一第十四晶体管T14，所述第十四晶体管T14的栅极电性连接于第二时钟驱动信号XCKN，源极电性连接于第一节点Q(N)，漏极电性连接于第二恒压低电位VSS2。
如图2所示，所述GOA电路的第一级连接关系中，第一晶体管T1的 栅极与源极均电性连接于电路的启动信号端STV。
需要特别说明的是，本发明基于低温多晶硅半导体薄膜晶体管的GOA电路设置了一个直流恒压高电位H、及三个直流恒压低电位VSS1、VSS2、VSS3，且三个直流恒压低电位依次降低，即，第三直流恒压低电位VSS3＜第二直流恒压低电位VSS2＜第一直流恒压低电位VSS1，该三个直流恒压低电位VSS1、VSS2、VSS3一般分开独立控制，便于进行不同电位的调节。
所述下拉维持电路部分500采用高低电位反推设计：所述第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6提供正向高电位，用于控制第十二晶体管T12和第十三晶体管T13的打开；所述第八晶体管T8构成作用期间的负电位的反向自举，用于在作用期间将第二节点P(N)拉低至至第三直流恒压低电位VSS3电位在非作用期间利用直流恒压高电位H向第二节点P(N)提供适当的高电位，使得第一节点Q(N)与输出端G(N)维持低电位，消除二者的波纹(Ripple)电压。所述第四晶体管T4、第六晶体管T6、与第八晶体管T8串联，能够防止漏电。采用上述方式设置下拉维持电路部分500，可减少TFT颗数，节省布局(Layout)空间，且所述第十晶体管T10的栅极电性连接于第二节点P(N)，可以防止电位过高对所述第十晶体管T10的危害。
具体的，所述下拉维持电路部分500中第三晶体管T3、第四晶体管T4受直流恒压高电位H的控制处于导通状态，在非作用期间，第五晶体管T5、第六晶体管T6截止，由第四晶体管T4向第二节点P(N)提供一直流恒压高电位H，第二节点P(N)为高电位时，第十二晶体管T12、第十三晶体管T13均导通，通过第十二晶体管下拉第一节点Q(N)的电位到第二直流恒压低电位VSS2，通过第十三晶体管下拉输出端G(N)的电位到第一直流恒压低电位VSS1；在作用期间，第五晶体管T5、第六晶体管T6、第八晶体管T8的栅极为从第一节点Q(N)传来的高电位，第五晶体管T5、第六晶体管T6、第八晶体管T8均导通，通过第五晶体管T5下拉第四晶体管T4的栅极电位至第一直流恒压低电位VSS1，第四晶体管T4截止，不再向第二节点P(N)提供直流恒压高电位H，且由于第六晶体管T6和第八晶体管T8均导通，通过第六晶体管T6和第八晶体管T8下拉第二节点P(N)的电位到一更低的第三直流恒压低电位VSS3。
所述下拉维持电路部分500搭配直流恒压高电位H、及三个直流恒压低电位VSS1、VSS2、VSS3，能够解决低温多晶硅半导体薄膜晶体管的自身的阈值电压较低、亚阈值区域的摆幅较小等特性对GOA驱动电路的影响，尤其是漏电问题带来的GOA功能性不良；同时解决了目前基于低温多 晶硅半导体薄膜晶体管的GOA电路中下拉维持电路部分在非作用期间第二节点电位不能处于较高的电位的问题，有效维持第一节点Q(N)和输出端G(N)的低电位。
所述上升部分300用来在作用期间抬升所述第一节点Q(N)的电位。
所述第一下拉部分400用来在非作用期间依据第二时钟驱动信号XCKN下拉所述第一节点Q(N)的电位至所述第二直流恒压低电位VSS2。
所述GOA电路采用输出端G(N)的输出信号作为上下级传信号，采用第N级GOA单元的上一级第N-1级GOA单元的输出端G(N-1)与第N级GOA单元的输出端G(N)进行上、下级传，能够减少TFT的颗数，达到有效节省布局和功耗的目的。
请参阅图3，图3为本发明的基于低温多晶硅半导体薄膜晶体管的GOA电路的第二实施例的电路图。如图3所示，该第二实施例与第一实例例区别在于，所述下拉维持部分500还包括第九晶体管T9，所述第九晶体管T9的栅极电性连接于第一节点Q(N)，源极电性连接于第十晶体管T10的栅极，漏极电性连接于第三直流恒压低电位VSS3；第十一晶体管T11，所述第十一晶体管T11的栅极与源极均电性连接于直流恒压高电位H，漏极电性连接于第十晶体管的栅极；第十晶体管T10的栅极与第二节点P(N)断开。除此之外，其余部分与第一实施例相同，此处不再赘述。
图4、图5分别为两种本发明的基于低温多晶硅半导体薄膜晶体管的GOA电路的波形设置和关键节点的输出波形图。所述第一节点Q(N)的信号输出波形依据第一时钟驱动信号CKN与第二时钟驱动信号XCKN波形占空比的变化而变化。图4中所示的第一时钟驱动信号CKN和第二时钟驱动信号XCKN的波形占空比不同于图5中所示的第一时钟驱动信号CKN和第二时钟驱动信号XCKN的波形占空比。图4和图5中，CK1N、CK2N分别表示第一条、第二条第一时钟驱动信号CKN，XCK1N、XCK2N分别表示第一条、第二条第二时钟驱动信号XCKN，第一时钟驱动信号CKN与第二时钟驱动信号XCKN的波形占空比均小于50/50；结合图1，在第二时钟驱动信号XCKN的高电位期间，所述第十四晶体管T14下拉所述第一节点Q(N)的电位至所述第二恒压低电位VSS2。所述第一节点Q(N)的信号输出波形呈“凸”字形，所述输出端G(N)正常输出。
综上所述，本发明的基于低温多晶硅半导体薄膜晶体管的GOA电路，在下拉维持电路部分采用高低电位反推设计，并设置依次降低的第一、第二、第三直流恒压低电位、及一直流恒压高电位，能够解决低温多晶硅半导体薄膜晶体管的自身特性对GOA驱动电路的影响，尤其是漏电问题带来 的GOA功能性不良；同时解决了目前基于低温多晶硅半导体薄膜晶体管的GOA电路中下拉维持电路部分在非作用期间第二节点电位不能处于较高的电位的问题，有效维持第一节点和输出端的低电位。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (11)

  1. 一种基于低温多晶硅半导体薄膜晶体管的GOA电路，包括级联的多个GOA单元，设N为正整数，第N级GOA单元包括一上拉控制部分、一上拉部分、一第一下拉部分和一下拉维持电路部分；
    所述上拉控制部分包括第一晶体管，其栅极与源极均电性连接于该第N级GOA单元的上一级第N-1级GOA单元的输出端，漏极电性连接于第一节点；
    所述上拉部分包括第二晶体管，其栅极电性连接于第一节点，源极电性连接于第一时钟驱动信号，漏极电性连接于输出端；
    所述下拉维持电路部分电性连接于所述第一节点、输出端、一直流恒压高电位、及第一、第二、与第三直流恒压低电位；
    所述下拉维持电路部分采用高低电位反推设计，包括：
    第三晶体管，所述第三晶体管的栅极和源极均电性连接于直流恒压高电位，漏极电性连接于第五晶体管的源极；
    第四晶体管，所述第四晶体管的栅极电性连接于第三晶体管的漏极，源极电性连接于直流恒压高电位，漏极电性连接于第二节点；
    第五晶体管，所述第五晶体管的栅极电性连接于第一节点，源极电性连接于第三晶体管的漏极，漏极电性连接于第一直流恒压低电位；
    第六晶体管，所述第六晶体管的栅极电性连接于第一节点，源极电性连接于第二节点，漏极电性连接于第八晶体管的源极；
    第八晶体管，所述第八晶体管的栅极电性连接于第一节点，源极电性连接于第六晶体管的漏极，漏极电性连接于第三直流恒压低电位；
    第十晶体管，所述第十晶体管的栅极电性连接于第二节点，源极电性连接于直流恒压高电位，漏极电性连接于第六晶体管的漏极；
    第十二晶体管，所述第十二晶体管的栅极电性连接于第二节点，源极电性连接于第一节点，漏极电性连接于第二直流恒压低电位；
    第十三晶体管，所述第十三晶体管的栅极电性连接于第二节点，源极电性连接于输出端，漏极电性连接于第一直流恒压低电位；
    所述第三晶体管、第四晶体管、第五晶体管、第六晶体管提供正向高电位，用于控制第十二晶体管和第十三晶体管的打开；所述第八晶体管构成作用期间的负电位的反向自举，用于在作用期间向第二节点提供更低电位；利用直流恒压高电位在非作用期间向第二节点提供适当的高电位，使 得第一节点与输出端维持低电位；
    所述第一下拉部分电性连接于所述第一节点、第二时钟驱动信号及第二直流恒压低电位，所述第一下拉部分依据第二时钟驱动信号下拉所述第一节点的电位至所述第二直流恒压低电位；
    所述第一下拉部分包括一第十四晶体管，所述第十四晶体管的栅极电性连接于第二时钟驱动信号，源极电性连接于第一节点，漏极电性连接于第二直流恒压低电位；
    所述第三直流恒压低电位<第二直流恒压低电位<第一直流恒压低电位。
  2. 如权利要求1所述的基于低温多晶硅半导体薄膜晶体管的GOA电路，其中，所述下拉维持电路部分还包括第九晶体管，所述第九晶体管的栅极电性第一节点，源极电性连接于第十晶体管的栅极，漏极电性连接于第三直流恒压低电位；第十一晶体管，所述第十一晶体管的栅极与源极均电性连接于直流恒压高电位，漏极电性连接于第十晶体管的栅极；第十晶体管的栅极与第二节点断开。
  3. 如权利要求1所述的基于低温多晶硅半导体薄膜晶体管的GOA电路，其中，所述第四晶体管、第六晶体管与第八晶体管串联。
  4. 如权利要求1所述的基于低温多晶硅半导体薄膜晶体管的GOA电路，还包括一上升部分，所述上升部分电性连接于所述第一节点与输出端之间，用来抬升所述第一节点的电位。
  5. 如权利要求4所述的基于低温多晶硅半导体薄膜晶体管的GOA电路，其中，所述上升部分包括一电容，所述电容的一端电性连接于第一节点，另一端电性连接于输出端。
  6. 如权利要求1所述的基于低温多晶硅半导体薄膜晶体管的GOA电路，其中，第一时钟驱动信号与第二时钟驱动信号的波形占空比小于50/50；在第二时钟驱动信号的高电位期间，所述第十四晶体管下拉所述第一节点的电位至所述第二直流恒压低电位。
  7. 如权利要求4所述的基于低温多晶硅半导体薄膜晶体管的GOA电路，其中，所述第一节点的信号输出波形依据第一时钟驱动信号与第二时钟驱动信号的波形占空比的变化而变化。
  8. 如权利要求7所述的基于低温多晶硅半导体薄膜晶体管的GOA电路，其中，所述第一节点的信号输出波形呈“凸”字形。
  9. 如权利要求1所述的基于低温多晶硅半导体薄膜晶体管的GOA电路，其中，所述GOA电路的第一级连接关系中，第一晶体管的栅极与源极 均电性连接于电路的启动信号端。
  10. 如权利要求1所述的基于低温多晶硅半导体薄膜晶体管的GOA电路，其中，所述GOA电路采用输出端的输出信号作为上下级传信号。
  11. 一种基于低温多晶硅半导体薄膜晶体管的GOA电路，包括级联的多个GOA单元，设N为正整数，第N级GOA单元包括一上拉控制部分、一上拉部分、一第一下拉部分和一下拉维持电路部分；
    所述上拉控制部分包括第一晶体管，其栅极与源极均电性连接于该第N级GOA单元的上一级第N-1级GOA单元的输出端，漏极电性连接于第一节点；
    所述上拉部分包括第二晶体管，其栅极电性连接于第一节点，源极电性连接于第一时钟驱动信号，漏极电性连接于输出端；
    所述下拉维持电路部分电性连接于所述第一节点、输出端、一直流恒压高电位、及第一、第二、与第三直流恒压低电位；
    所述下拉维持电路部分采用高低电位反推设计，包括：
    第三晶体管，所述第三晶体管的栅极和源极均电性连接于直流恒压高电位，漏极电性连接于第五晶体管的源极；
    第四晶体管，所述第四晶体管的栅极电性连接于第三晶体管的漏极，源极电性连接于直流恒压高电位，漏极电性连接于第二节点；
    第五晶体管，所述第五晶体管的栅极电性连接于第一节点，源极电性连接于第三晶体管的漏极，漏极电性连接于第一直流恒压低电位；
    第六晶体管，所述第六晶体管的栅极电性连接于第一节点，源极电性连接于第二节点，漏极电性连接于第八晶体管的源极；
    第八晶体管，所述第八晶体管的栅极电性连接于第一节点，源极电性连接于第六晶体管的漏极，漏极电性连接于第三直流恒压低电位；
    第十晶体管，所述第十晶体管的栅极电性连接于第二节点，源极电性连接于直流恒压高电位，漏极电性连接于第六晶体管的漏极；
    第十二晶体管，所述第十二晶体管的栅极电性连接于第二节点，源极电性连接于第一节点，漏极电性连接于第二直流恒压低电位；
    第十三晶体管，所述第十三晶体管的栅极电性连接于第二节点，源极电性连接于输出端，漏极电性连接于第一直流恒压低电位；
    所述第三晶体管、第四晶体管、第五晶体管、第六晶体管提供正向高电位，用于控制第十二晶体管和第十三晶体管的打开；所述第八晶体管构成作用期间的负电位的反向自举，用于在作用期间向第二节点提供更低电位；利用直流恒压高电位在非作用期间向第二节点提供适当的高电位，使 得第一节点与输出端维持低电位；
    所述第一下拉部分电性连接于所述第一节点、第二时钟驱动信号及第二直流恒压低电位，所述第一下拉部分依据第二时钟驱动信号下拉所述第一节点的电位至所述第二直流恒压低电位；
    所述第一下拉部分包括一第十四晶体管，所述第十四晶体管的栅极电性连接于第二时钟驱动信号，源极电性连接于第一节点，漏极电性连接于第二直流恒压低电位；
    所述第三直流恒压低电位<第二直流恒压低电位<第一直流恒压低电位；
    还包括一上升部分，所述上升部分电性连接于所述第一节点与输出端之间，用来抬升所述第一节点的电位；
    其中，所述上升部分包括一电容，所述电容的一端电性连接于第一节点，另一端电性连接于输出端；
    其中，第一时钟驱动信号与第二时钟驱动信号的波形占空比小于50/50；在第二时钟驱动信号的高电位期间，所述第十四晶体管下拉所述第一节点的电位至所述第二直流恒压低电位；
    其中，所述第一节点的信号输出波形呈“凸”字形。
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