WO2017101200A1 - 基于ltps半导体薄膜晶体管的goa电路 - Google Patents

基于ltps半导体薄膜晶体管的goa电路 Download PDF

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WO2017101200A1
WO2017101200A1 PCT/CN2016/072428 CN2016072428W WO2017101200A1 WO 2017101200 A1 WO2017101200 A1 WO 2017101200A1 CN 2016072428 W CN2016072428 W CN 2016072428W WO 2017101200 A1 WO2017101200 A1 WO 2017101200A1
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electrically connected
thin film
film transistor
node
drain
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PCT/CN2016/072428
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English (en)
French (fr)
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李亚锋
邬金芳
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武汉华星光电技术有限公司
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Priority to US14/913,991 priority Critical patent/US9916805B2/en
Publication of WO2017101200A1 publication Critical patent/WO2017101200A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a GOA circuit based on an LTPS semiconductor thin film transistor.
  • LCD Liquid crystal display
  • PDAs personal digital assistants
  • digital cameras computer screens or laptop screens, etc.
  • GOA technology (Gate Driver on Array) is an array substrate row driving technology.
  • the original array process of the liquid crystal display panel is used to fabricate a horizontal scanning line driving circuit on a substrate around the display area, so that it can replace the external integrated circuit board ( (Integrated Circuit, IC) to complete the horizontal scanning line drive.
  • IC integrated circuit board
  • GOA technology can reduce the bonding process of external ICs, have the opportunity to increase productivity and reduce product cost, and can make LCD panels more suitable for making narrow borders or no borders. Display product.
  • LTPS-TFT liquid crystal displays have attracted more and more attention.
  • LTPS-TFT liquid crystal displays have high resolution, fast response, high brightness and high opening. Rate and other advantages. Since the low-temperature polysilicon has an order of arrangement of amorphous silicon (a-Si), the low-temperature polysilicon semiconductor itself has an ultra-high electron mobility, which is 100 times higher than that of the amorphous silicon semiconductor, and the gate driver can be fabricated by using GOA technology. On the thin film transistor array substrate, the goal of system integration, space saving and cost of driving the IC are achieved.
  • a-Si amorphous silicon
  • a GOA circuit of a conventional LTPS semiconductor thin film transistor includes a cascaded multi-level GOA unit, wherein n is a positive integer, and the nth-level GOA unit includes: a first thin film transistor T1, the first thin film.
  • the gate of the transistor T1 is electrically connected to the output terminal G(n-1) of the upper n-1th stage GOA unit, and the drain is electrically connected to the forward scanning DC control signal U2D, and the source is electrically connected to the first a third node H(n); a second thin film transistor T2, a gate of the second thin film transistor T2 is electrically connected to the first node Q(n), and a source is electrically connected to the Mth clock signal CK(M)
  • the drain is electrically connected to the output terminal G(n); the third thin film transistor T3, the gate of the third thin film transistor T3 is electrically connected to the output terminal G of the n+1th GOA unit of the next stage.
  • the source is electrically connected to the third node H(n), and the drain is electrically connected to the reverse scan DC control signal D2U; fourth thin film transistor T4, the gate of the fourth thin film transistor T4 is electrically connected to the M+1th clock signal CK(M+1), and the source is electrically connected to the output terminal G(n), and the drain
  • the gate is electrically connected to the constant voltage high potential VGH, and the source is electrically connected to the third node H(n).
  • the gate of the fifth thin film transistor T5 is electrically connected to the constant voltage high potential VGH.
  • the drain is electrically connected to the first node Q(n); the sixth thin film transistor T6, the gate of the sixth thin film transistor T6 is electrically connected to the M+1th clock signal CK(M+1), the source
  • the gate is electrically connected to the third node H(n)
  • the drain is electrically connected to the constant voltage low potential VGL
  • the seventh thin film transistor T7 is electrically connected to the second node P (the gate of the seventh thin film transistor T7) n)
  • the source is electrically connected to the third node H(n)
  • the drain is electrically connected to the constant voltage low potential VGL
  • the eighth thin film transistor T8 is electrically connected to the gate of the eighth thin film transistor T8.
  • the M+1th clock signal CK(M+1) the source is electrically connected to the second node P(n)
  • the drain is electrically connected to the constant voltage low potential VGL
  • the tenth thin film transistor T10 the first
  • the gate of the ten-th thin film transistor T10 is electrically connected to the Mth clock signal CK(M)
  • the source is electrically connected to the constant voltage high potential VGH
  • the drain is electrically connected to the second node P(n);
  • a thin film transistor T11, the gate of the eleventh thin film transistor T11 is electrically connected to the third node H(n), the source is electrically connected to the second node P(n), and the drain is electrically connected to the constant voltage a first capacitor C1, one end of the first capacitor C1 is
  • the existing GOA circuit has a forward/reverse scan function.
  • forward scanning please refer to Figure 2.
  • the forward-scanning DC control signal U2D is high, and the reverse-scan DC control signal D2U is low. In reverse scanning, the forward-scanning DC control signal U2D is low.
  • the scanning DC control signal D2U is at a high potential.
  • the first thin film transistor T1 and the third thin film transistor T3 form a forward-reverse scanning control unit, and in combination with FIG. 2, the GOA circuit is forward-scanned to the output terminal G(n) and
  • the GOA circuit is forward-scanned to the output terminal G(n) and
  • the first node Q(n) is in the low potential sustain phase
  • the output terminal G(n+1) of the n+1th GOA unit, the output terminal G(n-1) of the n-1th GOA unit, and the first The node Q(n) is low
  • the forward-scanning DC control signal U2D is high
  • the voltage between the drain and the source Vds VGH-VGL
  • the IV curve corresponding to the thin film transistor under the voltage between the poles shows that when the voltage Vgs between the gate and the source is VV, the voltage Vds between the drain and the source is larger, and the current of the thin film transistor is also higher.
  • the first, and third thin In the film transistors T1 and T3 that is, the current of the first thin film transistor T1 is greater than the current of the third thin film transistor T3, and at this time, the first and third thin film transistors T1 and T3 should be in a closed state, and the off-state current of the thin film transistor is Too high will cause leakage, that is, the first thin film transistor T1 is in a leakage state.
  • the GOA circuit reverse scans into the output terminal G(n) and the first node Q(n) is in the low potential sustain phase, the current of the third thin film transistor T3 is greater than the current of the first thin film transistor T1, and the third film Transistor T3 is in a leakage state. Leakage can result in poor stability of the existing GOA circuits described above.
  • the present invention provides a GOA circuit based on an LTPS semiconductor thin film transistor, comprising: a plurality of cascaded GOA units, each of the GOA units including: a forward and reverse scanning control unit, an output unit, and a node control unit;
  • n be a positive integer, in addition to the first level, and the last level of the GOA unit, in the nth level GOA unit:
  • the forward-reverse scan control unit includes: a first thin film transistor, a gate of the first thin film transistor is electrically connected to a forward-scanning DC control signal, and a drain is electrically connected to a first-level n-1th GOA An output of the unit, the source is electrically connected to the fourth node; the twelfth thin film transistor, the gate of the twelfth thin film transistor is electrically connected to the output end of the upper n-1th GOA unit, and the drain
  • the gate is electrically connected to the third node, and the source is electrically connected to the third node;
  • the third thin film transistor has a gate electrically connected to the reverse scan DC control signal, and the source is electrically connected a fifth node, the drain is electrically connected to the output end of the n+1th GOA unit of the next stage; and the thirteenth thin film transistor, the gate of the thirteenth thin film transistor is electrically connected to the next stage An output end of the +1 level GOA unit, the drain is electrically connected to
  • the output unit includes: a second thin film transistor, a gate of the second thin film transistor is electrically connected to the first node, a source is electrically connected to the Mth clock signal, and a drain is electrically connected to the output end; a first capacitor, one end of the first capacitor is electrically connected to the first node, and the other end is electrically connected to the output end;
  • the node control unit includes: a fourth thin film transistor, a gate of the fourth thin film transistor is electrically connected to the M+1th clock signal, a source is electrically connected to the output end, and a drain is electrically connected to the constant voltage a fifth thin film transistor, the gate of the fifth thin film transistor is electrically connected to a constant voltage high potential, the source is electrically connected to the third node, and the drain is electrically connected to the first node; a thin film transistor, the gate of the sixth thin film transistor is electrically connected to the M+1th clock signal, the source is electrically connected to the third node, and the drain is electrically connected to the constant voltage low potential; the seventh thin film transistor, The gate of the seventh thin film transistor is electrically connected to the second node, the source is electrically connected to the third node, and the drain is electrically connected to the constant voltage low potential; the eighth thin film transistor, the eighth thin film transistor The gate is electrically connected to the second node, the source is electrically connected to the output end, and the drain is electrically connected
  • the forward scan DC control signal is opposite to the potential of the reverse scan DC control signal.
  • the GOA circuit based on the LTPS semiconductor thin film transistor has a forward and reverse scan function
  • the voltage between the gate and the source of the twelfth thin film transistor is 0V, and the voltage between the drain and the source is 0V, and the third The thin film transistor and the thirteenth thin film transistor are both turned off;
  • the drain of the first thin film transistor is electrically connected to the circuit start signal.
  • the drain of the third thin film transistor is electrically connected to the circuit start signal.
  • the forward scan DC control signal is at a high potential, and when the reverse scan DC control signal is at a low potential, a forward scan is performed.
  • the forward-scanning DC control signal is at a low potential, and when the reverse-scanning DC control signal is at a high potential, a reverse scan is performed.
  • the clock signal includes two clock signals: a first clock signal and a second clock signal.
  • the Mth clock signal is the second clock signal
  • the M+1th clock signal is the first Clock signal.
  • the thin film transistors are all N-type low temperature polysilicon semiconductor thin film transistors.
  • the invention also provides a GOA circuit based on an LTPS semiconductor thin film transistor, comprising: a plurality of cascaded GOA units, each of the GOA units comprising: a forward and reverse scanning control unit, and a transmission Out unit and node control unit;
  • n be a positive integer, in addition to the first level, and the last level of the GOA unit, in the nth level GOA unit:
  • the forward-reverse scan control unit includes: a first thin film transistor, a gate of the first thin film transistor is electrically connected to a forward-scanning DC control signal, and a drain is electrically connected to a first-level n-1th GOA An output of the unit, the source is electrically connected to the fourth node; the twelfth thin film transistor, the gate of the twelfth thin film transistor is electrically connected to the output end of the upper n-1th GOA unit, and the drain
  • the gate is electrically connected to the third node, and the source is electrically connected to the third node;
  • the third thin film transistor has a gate electrically connected to the reverse scan DC control signal, and the source is electrically connected a fifth node, the drain is electrically connected to the output end of the n+1th GOA unit of the next stage; and the thirteenth thin film transistor, the gate of the thirteenth thin film transistor is electrically connected to the next stage An output end of the +1 level GOA unit, the drain is electrically connected to
  • the output unit includes: a second thin film transistor, a gate of the second thin film transistor is electrically connected to the first node, a source is electrically connected to the Mth clock signal, and a drain is electrically connected to the output end; a first capacitor, one end of the first capacitor is electrically connected to the first node, and the other end is electrically connected to the output end;
  • the node control unit includes: a fourth thin film transistor, a gate of the fourth thin film transistor is electrically connected to the M+1th clock signal, a source is electrically connected to the output end, and a drain is electrically connected to the constant voltage a fifth thin film transistor, the gate of the fifth thin film transistor is electrically connected to a constant voltage high potential, the source is electrically connected to the third node, and the drain is electrically connected to the first node; the sixth thin film transistor The gate of the sixth thin film transistor is electrically connected to the M+1th clock signal, the source is electrically connected to the third node, the drain is electrically connected to the constant voltage low potential, and the seventh thin film transistor is The gate of the seventh thin film transistor is electrically connected to the second node, the source is electrically connected to the third node, the drain is electrically connected to the constant voltage low potential; and the eighth thin film transistor is the gate of the eighth thin film transistor Electrically connected to the second node, the source is electrically connected to the output end, and the drain is electrically connected to
  • the forward scanning DC control signal is opposite to the potential of the reverse scanning DC control signal
  • the voltage between the gate and the source of the twelfth thin film transistor is 0V, and the voltage between the drain and the source is 0V, and the third The thin film transistor and the thirteenth thin film transistor are both turned off;
  • the voltage between the gate and the source of the thirteenth thin film transistor is 0V, and the voltage between the drain and the source is 0V, first The thin film transistor and the twelfth thin film transistor are both turned off;
  • the drain of the first thin film transistor is electrically connected to the circuit start signal in the first stage GOA unit;
  • the drain of the third thin film transistor is electrically connected to the circuit start signal.
  • a GOA circuit based on an LTPS semiconductor thin film transistor is provided with an output controlled by an output terminal of an n-1th stage GOA unit and an output end of an n+1th GOA unit, respectively.
  • the first and third thin film transistors are respectively controlled by a forward scan DC control signal and a reverse scan DC control signal, and are in a forward scan to an output terminal and a first node low level maintenance phase, fourth The node is low, which can reduce the leakage current of the twelfth thin film transistor.
  • the fifth node is low, and the thirteenth thin film transistor can be lowered.
  • the leakage current reduces the leakage current of the critical thin film transistor and improves the stability of the GOA circuit.
  • FIG. 1 is a circuit diagram of a conventional GOA circuit based on an LTPS semiconductor thin film transistor
  • FIG. 2 is a timing chart of a forward scan corresponding to the GOA circuit shown in FIG. 1;
  • FIG. 3 is a graph of I-V corresponding to a thin film transistor under different drain and source voltages
  • FIG. 4 is a circuit diagram of a GOA circuit based on an LTPS semiconductor thin film transistor of the present invention
  • FIG. 5 is a forward scan timing diagram of a GOA circuit based on an LTPS semiconductor thin film transistor of the present invention
  • FIG. 6 is a reverse scan timing diagram of a GOA circuit based on an LTPS semiconductor thin film transistor of the present invention
  • FIG. 7 is a circuit diagram of a first stage GOA unit of a GOA circuit based on an LTPS semiconductor thin film transistor of the present invention.
  • Figure 8 is a circuit diagram of the final stage GOA unit of the LTPS semiconductor thin film transistor based GOA circuit of the present invention.
  • the present invention provides a GOA circuit based on an LTPS semiconductor thin film transistor, comprising: a plurality of cascaded GOA units, each of the GOA units including: a forward and reverse scan control unit 100, an output unit 200, and a node Control unit 300.
  • n be a positive integer, in addition to the first level, and the last level of the GOA unit, in the nth level GOA unit:
  • the forward-reverse scan control unit 100 includes a first thin film transistor T1, a gate of the first thin film transistor T1 is electrically connected to the forward-scanning DC control signal U2D, and a drain is electrically connected to the first-level nth.
  • the output terminal G(n-1) of the -1 stage GOA unit, the source is electrically connected to the fourth node W1(n); the twelfth thin film transistor T12, the gate of the twelfth thin film transistor T12 is electrically connected
  • the output terminal G(n-1) of the upper n-1th GOA unit is electrically connected to the fourth node W1(n), and the source is electrically connected to the third node H(n); a third thin film transistor T3, the gate of the third thin film transistor T3 is electrically connected to the reverse scan DC control signal D2U, the source is electrically connected to the fifth node W2(n), and the drain is electrically connected to the next stage.
  • the output unit 200 includes a second thin film transistor T2.
  • the gate of the second thin film transistor T2 is electrically connected to the first node Q(n), and the source is electrically connected to the Mth clock signal CK(M).
  • the drain is electrically connected to the output terminal G(n); and the first capacitor C1, one end of the first capacitor C1 is electrically connected to the first node Q(n), and the other end is electrically connected to the output terminal G ( n);
  • the node control unit 300 includes: a fourth thin film transistor T4, the fourth thin film crystal
  • the gate of the tube T4 is electrically connected to the M+1th clock signal CK(M+1), the source is electrically connected to the output terminal G(n), and the drain is electrically connected to the constant voltage low potential VGL;
  • the gate of the fifth thin film transistor T5 is electrically connected to the constant voltage high potential VGH, the source is electrically connected to the third node H(n), and the drain is electrically connected to the first node Q(n).
  • a sixth thin film transistor T6 the gate of the sixth thin film transistor T6 is electrically connected to the M+1th clock signal CK(M+1), and the source is electrically connected to the third node H(n).
  • the drain is electrically connected to the constant voltage low potential VGL; the seventh thin film transistor T7, the gate of the seventh thin film transistor T7 is electrically connected to the second node P(n), and the source is electrically connected to the third node H (n), the drain is electrically connected to the constant voltage low potential VGL; the eighth thin film transistor T8, the gate of the eighth thin film transistor T8 is electrically connected to the second node P(n), and the source is electrically connected The output terminal G(n), the drain is electrically connected to the constant voltage low potential VGL; the ninth thin film transistor T9, the gate of the ninth thin film transistor T9 is electrically connected to the M+1th clock signal CK (M+ 1), the source is electrically connected to The second node P(n), the drain is electrically connected to the constant voltage low potential VGL; the tenth thin film transistor T10, the gate of the tenth thin film transistor T10 is electrically connected to the Mth clock signal CK(M), the source The gate is electrically connected to the constant voltage high potential V
  • each of the thin film transistors is an N-type low temperature polysilicon semiconductor thin film transistor.
  • the drain of the first thin film transistor T1 is electrically connected to the circuit start signal STV; in the last stage GOA unit, the first The drain of the three thin film transistor T3 is electrically connected to the circuit start signal STV.
  • the GOA circuit based on the LTPS semiconductor thin film transistor of the present invention has a forward-backward scanning function.
  • the forward scan DC control signal U2D is opposite to the potential of the reverse scan DC control signal D2U.
  • the GOA circuit performs Forward scanning; when the forward scanning DC control signal U2D is low and the reverse scanning DC control signal D2U is high, the GOA circuit performs reverse scanning.
  • the LTPS semiconductor thin film transistor-based GOA circuit includes two clock signals: a first clock signal CK(1), and a second clock signal CK(2), when the Mth When the strip clock signal CK(M) is the second clock signal CK(2), the M+1th clock signal CK(M+1) is the first clock signal CK(1).
  • the output terminal G(n) of each level of the GOA unit corresponds to a clock signal.
  • the output end of the first stage GOA unit corresponds to the first clock signal CK(1)
  • the output end of the second stage GOA unit corresponds to the second line.
  • Clock signal CK(2), third stage GOA unit The output end corresponds to the first clock signal CK(1)
  • the output signal of the fourth stage GOA unit corresponds to the second clock signal CK(2), and so on.
  • the forward-scanning DC control signal U2D is at a high potential
  • the reverse-scan DC control signal D2U is at a low potential
  • the GOA circuit is forward-scanning.
  • Phase 1 pre-charging phase: the output terminal G(n-1) of the n-1th GOA unit and the forward-scanning DC control signal U2D are both high, and the first and twelfth thin film transistors T1 and T12 are both turned on.
  • the potential of the fourth node W1(n) and the third node H(n) is pulled high, and the fifth thin film transistor T5 is always turned on by the constant voltage high potential VGH, and the first node Q(n) is precharged;
  • the eleventh thin film transistor T11 controlled by the three nodes H(n) is turned on, and the second node P(n) is pulled down to the constant voltage low potential VGL.
  • Phase 2, high-potential output stage the output terminal G(n-1) of the n-1th stage GOA unit transitions to a low potential, the twelfth thin film transistor T12 is turned off, and the Mth clock signal CK(M) provides a high potential.
  • the first node Q(n) continues to maintain a high potential under the storage of the first capacitor C1, and the second thin film transistor T2 controlled by the first node Q(n) is turned on, and the high potential provided by the Mth clock signal passes through The second thin film transistor T2 is output to the output terminal G(n).
  • Phase 3 low potential output stage the M+1th clock signal CK(M+1) provides a high potential, the sixth and fourth thin film transistors T6, T4 are turned on, the third node H(n), the first node Q Both (n) and output G(n) are pulled down to a constant voltage low potential VGL.
  • Phase 4 output terminal G(n) and first node Q(n) low potential sustaining phase: the eleventh thin film transistor controlled by the third node H(n) after the third node H(n) transitions to a low potential T11 is turned off; the Mth clock signal CK(M) and the M+1th clock signal CK(M+1) alternately provide a high potential: when the Mth clock signal CK(M) provides a high potential, the tenth thin film transistor T10 is turned on, the second node P(n) is raised to the constant voltage high potential VGH, and the seventh and eighth thin film transistors T7 and T8 controlled by the second node P(n) are both turned on to maintain the third node H(n).
  • the first node Q(n), and the output terminal G(n) are low; when the M+1th clock signal CK(M+1) is high, the sixth and fourth thin film transistors T6, T4 All are turned on, maintaining the third node H(n), the first node Q(n), and the output terminal G(n) at a low potential, and the ninth thin film transistor T9 is also turned on, and the second node P(n) is also Pulled down to a low potential, turning off the seventh and eighth thin film transistors T7, T8, preventing the second node P(n) from being at a high potential, causing the seventh and eighth thin film transistors T7, T8 to be subjected to electrical stress for a long time.
  • the circuit is unstable.
  • the output terminal G(n-1) of the n-1th stage GOA unit is provided low.
  • the forward-scanning DC control signal U2D is at a high potential
  • the first thin film transistor T1 is turned on
  • the fourth node W1(n) that is, the drain of the twelfth thin film transistor T12 is low
  • the third node H(n) That is, the source of the twelfth thin film transistor T12 is extremely low
  • the gate of the twelfth thin film transistor T12 is connected to the n-1th stage.
  • the leakage current of the twelfth thin film transistor T12 is significantly reduced compared to the prior art.
  • the third thin film transistor T3 and the thirteenth thin film transistor T13 are turned off in series, compared with the conventional GOA circuit. It also reduces the occurrence of leakage current.
  • the reverse scanning DC control signal D2U is at a high potential
  • the forward scanning DC control signal U2D is at a low potential
  • the GOA circuit is reversely scanned.
  • the specific working process is:
  • Phase 1 pre-charging phase: the output terminal G(n+1) of the n+1th GOA unit and the reverse scanning DC control signal D2U are both high, and the third and thirteenth thin film transistors T3 and T13 are both turned on.
  • the potential of the fifth node W2(n) and the third node H(n) is pulled high, and the fifth thin film transistor T5 is always turned on by the constant voltage high potential VGH, and the first node Q(n) is precharged;
  • the eleventh thin film transistor T11 controlled by the three nodes H(n) is turned on, and the second node P(n) is pulled down to the constant voltage low potential VGL.
  • Phase 2, high-potential output stage the output terminal G(n+1) of the n+1th GOA unit transitions to a low potential, the thirteenth thin film transistor T13 is turned off, and the Mth clock signal CK(M) provides a high potential.
  • the first node Q(n) continues to maintain a high potential under the storage of the first capacitor C1, and the second thin film transistor T2 controlled by the first node Q(n) is turned on, and the high potential provided by the Mth clock signal passes through The second thin film transistor T2 is output to the output terminal G(n).
  • Phase 3 low potential output stage the M+1th clock signal CK(M+1) provides a high potential, the sixth and fourth thin film transistors T6, T4 are turned on, the third node H(n), the first node Q Both (n) and output G(n) are pulled down to a constant voltage low potential VGL.
  • Phase 4 output terminal G(n) and first node Q(n) low potential sustaining phase: the eleventh thin film transistor controlled by the third node H(n) after the third node H(n) transitions to a low potential T11 is turned off; the Mth clock signal CK(M) and the M+1th clock signal CK(M+1) alternately provide a high potential: when the Mth clock signal CK(M) provides a high potential, the tenth thin film transistor T10 is turned on, the second node P(n) is raised to the constant voltage high potential VGH, and the seventh and eighth thin film transistors T7 and T8 controlled by the second node P(n) are both turned on to maintain the third node H(n).
  • the first node Q(n), and the output terminal G(n) are low; when the M+1th clock signal CK(M+1) is high, the sixth and fourth thin film transistors T6, T4 All are turned on, maintaining the third node H(n), the first node Q(n), and the output terminal G(n) at a low potential, and the ninth thin film transistor T9 is also turned on, and the second node P(n) is also Pulled down to a low potential, turning off the seventh and eighth thin film transistors T7, T8, preventing the second node P(n) from being at a high potential, causing the seventh and eighth thin film transistors T7, T8 to be subjected to electrical stress for a long time.
  • the circuit is unstable.
  • the output terminal G(n+1) of the n+1th-order GOA unit is provided low.
  • said The reverse scan DC control signal D2U is at a high potential
  • the third thin film transistor T3 is turned on
  • the fifth node W2(n) that is, the drain of the thirteenth thin film transistor T13 is low
  • the third node H(n) is the thirteenth
  • the source of the thin film transistor T13 is extremely low
  • the gate of the thirteenth thin film transistor T13 is connected to the output terminal G(n+1) of the n+1th GOA unit, which is also low, so that the gate of the thirteenth thin film transistor T13
  • the leakage current of the thirteenth thin film transistor T13 is significantly reduced compared to the prior art.
  • the first thin film transistor T1 and the twelfth thin film transistor T12 are turned off in series, compared with the conventional GOA circuit. It also reduces the occurrence of leakage current.
  • the GOA circuit based on the LTPS semiconductor thin film transistor of the present invention adds a twelfth thin film transistor controlled by the output end of the n-1th stage GOA unit and the output end of the n+1th stage GOA unit, respectively.
  • the thirteenth thin film transistor, the drain of the twelfth thin film transistor is electrically connected to the source of the first thin film transistor through the fourth node, the drain of the first thin film transistor and the output end of the n-1th stage GOA unit Electrically connected, the drain of the thirteenth thin film transistor is electrically connected to the source of the third thin film transistor through the fifth node, and the drain of the third thin film transistor is electrically connected to the output end of the n+1th GOA unit.
  • the first and third thin film transistors are respectively controlled by a forward scan DC control signal and a reverse scan DC control signal, and the fourth node is low when the forward scan to the output terminal and the first node low level sustain phase
  • the leakage current of the twelfth thin film transistor can be reduced.
  • the fifth node is low, which can reduce the leakage current of the thirteenth thin film transistor, thereby lowering The leakage current of the key thin film transistor is lowered, which improves the stability of the GOA circuit.

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Abstract

一种基于LTPS半导体薄膜晶体管的GOA电路，增设了分别受第n-1级GOA单元的输出端(G(n-1))和第n+1级GOA单元的输出端(G(n+1))控制的第十二和第十三薄膜晶体管(T12、T13)，第十二薄膜晶体管(T12)的漏极通过第四节点(W1(n))与第一薄膜晶体管(T1)的源极电性连接，第十三薄膜晶体管(T13)的漏极通过第五节点(W2(n))与第三薄膜晶体管(T3)的源极电性连接，第一和第三薄膜晶体管(T1、T3)分别受正向扫描直流控制信号(U2D)与反向扫描直流控制信号(D2U)控制，在正向扫描时能够降低第十二薄膜晶体管(T12)的漏电流，在反向扫描时能够降低第十三薄膜晶体管(T13)的漏电流，从而降低了关键薄膜晶体管的漏电流，提升了GOA电路的稳定性。

Description

基于LTPS半导体薄膜晶体管的GOA电路 技术领域
本发明涉及显示技术领域，尤其涉及一种基于LTPS半导体薄膜晶体管的GOA电路。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
GOA技术(Gate Driver on Array)即阵列基板行驱动技术，是运用液晶显示面板的原有阵列制程将水平扫描线的驱动电路制作在显示区周围的基板上，使之能替代外接集成电路板((Integrated Circuit，IC)来完成水平扫描线的驱动。GOA技术能减少外接IC的焊接(bonding)工序，有机会提升产能并降低产品成本，而且可以使液晶显示面板更适合制作窄边框或无边框的显示产品。
随着低温多晶硅(Low Temperature Poly-silicon，LTPS)半导体薄膜晶体管的发展，LTPS-TFT液晶显示器也越来越受关注，LTPS-TFT液晶显示器具有高分辨率、反应速度快、高亮度、高开口率等优点。由于低温多晶硅较非晶硅(a-Si)的排列有次序，低温多晶硅半导体本身具有超高的电子迁移率，比非晶硅半导体相对高100倍以上，可以采用GOA技术将栅极驱动器制作在薄膜晶体管阵列基板上，达到系统整合的目标、节省空间及驱动IC的成本。
请参阅图1，现有的一种LTPS半导体薄膜晶体管的GOA电路包括级联的多级GOA单元，设n为正整数，第n级GOA单元包括：第一薄膜晶体管T1，所述第一薄膜晶体管T1的栅极电性连接于上一级第n-1级GOA单元的输出端G(n-1)，漏极电性连接于正向扫描直流控制信号U2D，源极电性连接于第三节点H(n)；第二薄膜晶体管T2，所述第二薄膜晶体管T2的栅极电性连接于第一节点Q(n)，源极电性连接于第M条时钟信号CK(M)，漏极电性连接于输出端G(n)；第三薄膜晶体管T3，所述第三薄膜晶体管T3的栅极电性连接于下一级第n+1级GOA单元的输出端G(n+1)，源极电性连接于第三节点H(n)，漏极电性连接于反向扫描直流控制信号 D2U；第四薄膜晶体管T4，所述第四薄膜晶体管T4的栅极电性连接于第M+1条时钟信号CK(M+1)，源极电性连接于输出端G(n)，漏极电性连接于恒压低电位VGL；第五薄膜晶体管T5，所述第五薄膜晶体管T5的栅极电性连接于恒压高电位VGH，源极电性连接于第三节点H(n)，漏极电性连接于第一节点Q(n)；第六薄膜晶体管T6，所述第六薄膜晶体管T6的栅极电性连接于第M+1条时钟信号CK(M+1)，源极电性连接于第三节点H(n)，漏极电性连接于恒压低电位VGL；第七薄膜晶体管T7，所述第七薄膜晶体管T7的栅极电性连接于第二节点P(n)，源极电性连接于第三节点H(n)，漏极电性连接于恒压低电位VGL；第八薄膜晶体管T8，所述第八薄膜晶体管T8的栅极电性连接于第二节点P(n)，源极电性连接于输出端G(n)，漏极电性连接于恒压低电位VGL；第九薄膜晶体管T9，所述第九薄膜晶体管T9的栅极电性连接于第M+1条时钟信号CK(M+1)，源极电性连接于第二节点P(n)，漏极电性连接于恒压低电位VGL；第十薄膜晶体管T10，所述第十薄膜晶体管T10的栅极电性连接于第M条时钟信号CK(M)，源极电性连接于恒压高电位VGH，漏极电性连接于第二节点P(n)；第十一薄膜晶体管T11，所述第十一薄膜晶体管T11的栅极电性连接于第三节点H(n)，源极电性连接于第二节点P(n)，漏极电性连接于恒压低电位VGL；第一电容C1，所述第一电容C1的一端电性连接于第一节点Q(n)，另一端电性连接于输出端G(n)；以及第二电容C2，所述第二电容C2的一端电性连接于第二节点P(n)，另一端电性连接于恒压低电位VGL。
该现有的GOA电路具备正反向扫描功能。正向扫描时，请参阅图2，正向扫描直流控制信号U2D为高电位，反向扫描直流控制信号D2U为低电位；反向扫描时相反，正向扫描直流控制信号U2D为低电位，反向扫描直流控制信号D2U为高电位。
图1所示的现有的GOA电路中，第一薄膜晶体管T1和第三薄膜晶体管T3形成正反向扫描控制单元，结合图2，在GOA电路正向扫描进入到输出端G(n)及第一节点Q(n)低电位维持阶段时，第n+1级GOA单元的输出端G(n+1)、第n-1级GOA单元的输出端G(n-1)、和第一节点Q(n)均为低电位，正向扫描直流控制信号U2D为高电位，则第一薄膜晶体管T1的栅极与源极之间的电压Vgs＝0V，漏极与源极之间的电压Vds＝VGH-VGL，第三薄膜晶体管T3的栅极与源极之间的电压Vgs＝0V，漏极与源极之间的电压Vds＝0V，结合图3所示的在不同漏极与源极之间的电压下薄膜晶体管对应的I-V曲线图可知，当栅极与源极之间的电压Vgs＝0V时，漏极与源极之间的电压Vds越大，该薄膜晶体管的电流也越大，对应到第一、和第三薄 膜晶体管T1、T3中，即第一薄膜晶体管T1的电流大于第三薄膜晶体管T3的电流，而此时第一、和第三薄膜晶体管T1、T3均应处于关闭状态，薄膜晶体管的关态电流过高会引起漏电，也就是说第一薄膜晶体管T1处于漏电状态。相反的，在GOA电路反向扫描进入到输出端G(n)及第一节点Q(n)低电位维持阶段时，第三薄膜晶体管T3的电流大于第一薄膜晶体管T1的电流，第三薄膜晶体管T3处于漏电状态。漏电会导致上述现有的GOA电路的稳定性不佳。
发明内容
本发明的目的在于提供一种基于LTPS半导体薄膜晶体管的GOA电路，能够降低关键薄膜晶体管的漏电流，提升GOA电路的稳定性。
为实现上述目的，本发明提供了一种基于LTPS半导体薄膜晶体管的GOA电路，包括：级联的多个GOA单元，每个GOA单元均包括：正反向扫描控制单元、输出单元、及节点控制单元；
设n为正整数，除第一级、与最后一级GOA单元外，在第n级GOA单元中：
所述正反向扫描控制单元包括：第一薄膜晶体管，所述第一薄膜晶体管的栅极电性连接于正向扫描直流控制信号，漏极电性连接于上一级第n-1级GOA单元的输出端，源极电性连接于第四节点；第十二薄膜晶体管，所述第十二薄膜晶体管的栅极电性连接于上一级第n-1级GOA单元的输出端，漏极电性连接于第四节点，源极电性连接于第三节点；第三薄膜晶体管，所述第三薄膜晶体管的栅极电性连接于反向扫描直流控制信号，源极电性连接于第五节点，漏极电性连接于下一级第n+1级GOA单元的输出端；以及第十三薄膜晶体管，所述第十三薄膜晶体管的栅极电性连接于下一级第n+1级GOA单元的输出端，漏极电性连接于第五节点，源极电性连接于第三节点；
所述输出单元包括：第二薄膜晶体管，所述第二薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极电性连接于输出端；以及第一电容，所述第一电容的一端电性连接于第一节点，另一端电性连接于输出端；
所述节点控制单元包括：第四薄膜晶体管，所述第四薄膜晶体管的栅极电性连接于第M+1条时钟信号，源极电性连接于输出端，漏极电性连接于恒压低电位；第五薄膜晶体管，所述第五薄膜晶体管的栅极电性连接于恒压高电位，源极电性连接于第三节点，漏极电性连接于第一节点；第六 薄膜晶体管，所述第六薄膜晶体管的栅极电性连接于第M+1条时钟信号，源极电性连接于第三节点，漏极电性连接于恒压低电位；第七薄膜晶体管，所述第七薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第三节点，漏极电性连接于恒压低电位；第八薄膜晶体管，所述第八薄膜晶体管的栅极电性连接于第二节点，源极电性连接于输出端，漏极电性连接于恒压低电位；第九薄膜晶体管，所述第九薄膜晶体管的栅极电性连接于第M+1条时钟信号，源极电性连接于第二节点，漏极电性连接于恒压低电位；第十薄膜晶体管，所述第十薄膜晶体管的栅极电性连接于第M条时钟信号，源极电性连接于恒压高电位，漏极电性连接于第二节点；第十一薄膜晶体管，所述第十一薄膜晶体管的栅极电性连接于第三节点，源极电性连接于第二节点，漏极电性连接于恒压低电位；以及第二电容，所述第二电容的一端电性连接于第二节点，另一端电性连接于恒压低电位；
正向扫描直流控制信号与反向扫描直流控制信号的电位相反。
所述基于LTPS半导体薄膜晶体管的GOA电路具备正反向扫描功能；
在正向扫描进入到输出端及第一节点低电位维持阶段时，第十二薄膜晶体管的栅极与源极之间的电压为0V，漏极与源极之间的电压为0V，第三薄膜晶体管与第十三薄膜晶体管均关闭；
在反向扫描进入到输出端及第一节点低电位维持阶段时，第十三薄膜晶体管的栅极与源极之间的电压为0V，漏极与源极之间的电压为0V，第一薄膜晶体管与第十二薄膜晶体管均关闭。
在第一级GOA单元中，所述第一薄膜晶体管的漏极电性连接于电路起始信号。
在最后一级GOA单元中，所述第三薄膜晶体管的漏极电性连接于电路起始信号。
所述正向扫描直流控制信号为高电位，反向扫描直流控制信号为低电位时，进行正向扫描。
所述正向扫描直流控制信号为低电位，反向扫描直流控制信号为高电位时，进行反向扫描。
所述时钟信号包括两条时钟信号：第一条时钟信号、和第二条时钟信号，当所述第M条时钟信号为第二条时钟信号时，第M+1条时钟信号为第一条时钟信号。
所述薄膜晶体管均为N型低温多晶硅半导体薄膜晶体管。
本发明还提供一种基于LTPS半导体薄膜晶体管的GOA电路，包括：级联的多个GOA单元，每个GOA单元均包括：正反向扫描控制单元、输 出单元、及节点控制单元；
设n为正整数，除第一级、与最后一级GOA单元外，在第n级GOA单元中：
所述正反向扫描控制单元包括：第一薄膜晶体管，所述第一薄膜晶体管的栅极电性连接于正向扫描直流控制信号，漏极电性连接于上一级第n-1级GOA单元的输出端，源极电性连接于第四节点；第十二薄膜晶体管，所述第十二薄膜晶体管的栅极电性连接于上一级第n-1级GOA单元的输出端，漏极电性连接于第四节点，源极电性连接于第三节点；第三薄膜晶体管，所述第三薄膜晶体管的栅极电性连接于反向扫描直流控制信号，源极电性连接于第五节点，漏极电性连接于下一级第n+1级GOA单元的输出端；以及第十三薄膜晶体管，所述第十三薄膜晶体管的栅极电性连接于下一级第n+1级GOA单元的输出端，漏极电性连接于第五节点，源极电性连接于第三节点；
所述输出单元包括：第二薄膜晶体管，所述第二薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极电性连接于输出端；以及第一电容，所述第一电容的一端电性连接于第一节点，另一端电性连接于输出端；
所述节点控制单元包括：第四薄膜晶体管，所述第四薄膜晶体管的栅极电性连接于第M+1条时钟信号，源极电性连接于输出端，漏极电性连接于恒压低电位；第五薄膜晶体管，所述第五薄膜晶体管的栅极电性连接于恒压高电位，源极电性连接于第三节点，漏极电性连接于第一节点；第六薄膜晶体管，所述第六薄膜晶体管的栅极电性连接于第M+1条时钟信号，源极电性连接于第三节点，漏极电性连接于恒压低电位；第七薄膜晶体管，所述第七薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第三节点，漏极电性连接于恒压低电位；第八薄膜晶体管，所述第八薄膜晶体管的栅极电性连接于第二节点，源极电性连接于输出端，漏极电性连接于恒压低电位；第九薄膜晶体管，所述第九薄膜晶体管的栅极电性连接于第M+1条时钟信号，源极电性连接于第二节点，漏极电性连接于恒压低电位；第十薄膜晶体管，所述第十薄膜晶体管的栅极电性连接于第M条时钟信号，源极电性连接于恒压高电位，漏极电性连接于第二节点；第十一薄膜晶体管，所述第十一薄膜晶体管的栅极电性连接于第三节点，源极电性连接于第二节点，漏极电性连接于恒压低电位；以及第二电容，所述第二电容的一端电性连接于第二节点，另一端电性连接于恒压低电位；
正向扫描直流控制信号与反向扫描直流控制信号的电位相反；
其中，具备正反向扫描功能；
在正向扫描进入到输出端及第一节点低电位维持阶段时，第十二薄膜晶体管的栅极与源极之间的电压为0V，漏极与源极之间的电压为0V，第三薄膜晶体管与第十三薄膜晶体管均关闭；
在反向扫描进入到输出端及第一节点低电位维持阶段时，第十三薄膜晶体管的栅极与源极之间的电压为0V，漏极与源极之间的电压为0V，第一薄膜晶体管与第十二薄膜晶体管均关闭；
其中，在第一级GOA单元中，所述第一薄膜晶体管的漏极电性连接于电路起始信号；
其中，在最后一级GOA单元中，所述第三薄膜晶体管的漏极电性连接于电路起始信号。
本发明的有益效果：本发明提供的一种基于LTPS半导体薄膜晶体管的GOA电路，增设了分别受第n-1级GOA单元的输出端、和第n+1级GOA单元的输出端控制的第十二薄膜晶体管、和第十三薄膜晶体管，第十二薄膜晶体管的漏极通过第四节点与第一薄膜晶体管的源极电性连接，第一薄膜晶体管的漏极与第n-1级GOA单元的输出端电性连接，第十三薄膜晶体管的漏极通过第五节点与第三薄膜晶体管的源极电性连接，第三薄膜晶体管的漏极与第n+1级GOA单元的输出端电性连接，第一、和第三薄膜晶体管分别受正向扫描直流控制信号、与反向扫描直流控制信号控制，在正向扫描至输出端及第一节点低电平维持阶段时，第四节点为低电位，能够降低第十二薄膜晶体管的漏电流，在反向扫描至输出端及第一节点低电平维持阶段时，第五节点为低电位，能够降低第十三薄膜晶体管的漏电流，从而降低了关键薄膜晶体管的漏电流，提升了GOA电路的稳定性。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为现有的一种基于LTPS半导体薄膜晶体管的GOA电路的电路图；
图2为对应于图1所示GOA电路的正向扫描时序图；
图3为在不同漏极与源极之间的电压下薄膜晶体管对应的I-V曲线图；
图4为本发明的基于LTPS半导体薄膜晶体管的GOA电路的电路图；
图5为本发明的基于LTPS半导体薄膜晶体管的GOA电路的正向扫描时序图；
图6为本发明的基于LTPS半导体薄膜晶体管的GOA电路的反向扫描时序图；
图7为本发明的基于LTPS半导体薄膜晶体管的GOA电路的第一级GOA单元的电路图；
图8为本发明的基于LTPS半导体薄膜晶体管的GOA电路的最后一级GOA单元的电路图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图4，本发明提供一种基于LTPS半导体薄膜晶体管的GOA电路，包括：级联的多个GOA单元，每个GOA单元均包括：正反向扫描控制单元100、输出单元200、及节点控制单元300。
设n为正整数，除第一级、与最后一级GOA单元外，在第n级GOA单元中：
所述正反向扫描控制单元100包括：第一薄膜晶体管T1，所述第一薄膜晶体管T1的栅极电性连接于正向扫描直流控制信号U2D，漏极电性连接于上一级第n-1级GOA单元的输出端G(n-1)，源极电性连接于第四节点W1(n)；第十二薄膜晶体管T12，所述第十二薄膜晶体管T12的栅极电性连接于上一级第n-1级GOA单元的输出端G(n-1)，漏极电性连接于第四节点W1(n)，源极电性连接于第三节点H(n)；第三薄膜晶体管T3，所述第三薄膜晶体管T3的栅极电性连接于反向扫描直流控制信号D2U，源极电性连接于第五节点W2(n)，漏极电性连接于下一级第n+1级GOA单元的输出端G(n+1)；以及第十三薄膜晶体管T13，所述第十三薄膜晶体管T13的栅极电性连接于下一级第n+1级GOA单元的输出端G(n+1)，漏极电性连接于第五节点W2(n)，源极电性连接于第三节点H(n)；
所述输出单元200包括：第二薄膜晶体管T2，所述第二薄膜晶体管T2的栅极电性连接于第一节点Q(n)，源极电性连接于第M条时钟信号CK(M)，漏极电性连接于输出端G(n)；以及第一电容C1，所述第一电容C1的一端电性连接于第一节点Q(n)，另一端电性连接于输出端G(n)；
所述节点控制单元300包括：第四薄膜晶体管T4，所述第四薄膜晶体 管T4的栅极电性连接于第M+1条时钟信号CK(M+1)，源极电性连接于输出端G(n)，漏极电性连接于恒压低电位VGL；第五薄膜晶体管T5，所述第五薄膜晶体管T5的栅极电性连接于恒压高电位VGH，源极电性连接于第三节点H(n)，漏极电性连接于第一节点Q(n)；第六薄膜晶体管T6，所述第六薄膜晶体管T6的栅极电性连接于第M+1条时钟信号CK(M+1)，源极电性连接于第三节点H(n)，漏极电性连接于恒压低电位VGL；第七薄膜晶体管T7，所述第七薄膜晶体管T7的栅极电性连接于第二节点P(n)，源极电性连接于第三节点H(n)，漏极电性连接于恒压低电位VGL；第八薄膜晶体管T8，所述第八薄膜晶体管T8的栅极电性连接于第二节点P(n)，源极电性连接于输出端G(n)，漏极电性连接于恒压低电位VGL；第九薄膜晶体管T9，所述第九薄膜晶体管T9的栅极电性连接于第M+1条时钟信号CK(M+1)，源极电性连接于第二节点P(n)，漏极电性连接于恒压低电位VGL；第十薄膜晶体管T10，所述第十薄膜晶体管T10的栅极电性连接于第M条时钟信号CK(M)，源极电性连接于恒压高电位VGH，漏极电性连接于第二节点P(n)；第十一薄膜晶体管T11，所述第十一薄膜晶体管T11的栅极电性连接于第三节点H(n)，源极电性连接于第二节点P(n)，漏极电性连接于恒压低电位VGL；以及第二电容C2，所述第二电容C2的一端电性连接于第二节点P(n)，另一端电性连接于恒压低电位VGL。
具体地，各个薄膜晶体管均为N型低温多晶硅半导体薄膜晶体管。
特别地，请参阅图7与图8，在第一级GOA单元中，所述第一薄膜晶体管T1的漏极电性连接于电路起始信号STV；在最后一级GOA单元中，所述第三薄膜晶体管T3的漏极电性连接于电路起始信号STV。
本发明的基于LTPS半导体薄膜晶体管的GOA电路具备正反向扫描功能。所述正向扫描直流控制信号U2D与反向扫描直流控制信号D2U的电位相反，当所述正向扫描直流控制信号U2D为高电位，反向扫描直流控制信号D2U为低电位时，GOA电路进行正向扫描；当所述正向扫描直流控制信号U2D为低电位，反向扫描直流控制信号D2U为高电位时，GOA电路进行反向扫描。
请参阅图5或图6，所述基于LTPS半导体薄膜晶体管的GOA电路包括两条时钟信号：第一条时钟信号CK(1)、和第二条时钟信号CK(2)，当所述第M条时钟信号CK(M)为第二条时钟信号CK(2)时，第M+1条时钟信号CK(M+1)为第一条时钟信号CK(1)。每一级GOA单元的输出端G(n)对应一条时钟信号，例如：第一级GOA单元的输出端对应第一条时钟信号CK(1)，第二级GOA单元的输出端对应第二条时钟信号CK(2)，第三级GOA单元 的输出端对应第一条时钟信号CK(1)，第四级GOA单元的输出信号对应第二条时钟信号CK(2)，依次类推。
请结合图4与图5，所述正向扫描直流控制信号U2D为高电位，反向扫描直流控制信号D2U为低电位，GOA电路正向扫描，具体工作过程为：
阶段1、预充电阶段：第n-1级GOA单元的输出端G(n-1)与正向扫描直流控制信号U2D均为高电位，第一和第十二薄膜晶体管T1、T12均导通，第四节点W1(n)与第三节点H(n)的电位被拉高，第五薄膜晶体管T5受恒压高电位VGH控制始终打开，第一节点Q(n)被预充电；受第三节点H(n)控制的第十一薄膜晶体管T11导通，第二节点P(n)被拉低至恒压低电位VGL。
阶段2、高电位输出阶段：第n-1级GOA单元的输出端G(n-1)转变为低电位，第十二薄膜晶体管T12关闭，第M条时钟信号CK(M)提供高电位，第一节点Q(n)在第一电容C1的存储作用下继续保持高电位，受第一节点Q(n)控制的第二薄膜晶体管T2导通，第M条时钟信号提供的高电位经由第二薄膜晶体管T2输出至输出端G(n)。
阶段3、低电位输出阶段：第M+1条时钟信号CK(M+1)提供高电位，第六和第四薄膜晶体管T6、T4导通，第三节点H(n)、第一节点Q(n)、和输出端G(n)均被拉低至恒压低电位VGL。
阶段4、输出端G(n)及第一节点Q(n)低电位维持阶段：第三节点H(n)转变为低电位后，受第三节点H(n)控制的第十一薄膜晶体管T11关闭；第M条时钟信号CK(M)、第M+1条时钟信号CK(M+1)交替提供高电位：当第M条时钟信号CK(M)提供高电位时，第十薄膜晶体管T10导通，第二节点P(n)抬升至恒压高电位VGH，受第二节点P(n)控制的第七和第八薄膜晶体管T7、T8均导通，维持第三节点H(n)、第一节点Q(n)、和输出端G(n)为低电位；当第M+1条时钟信号CK(M+1)为高电位时，第六和第四薄膜晶体管T6、T4均导通，维持第三节点H(n)、第一节点Q(n)、和输出端G(n)为低电位，同时第九薄膜晶体管T9也导通，第二节点P(n)也被拉低至低电位，关闭第七和第八薄膜晶体管T7、T8，防止第二节点P(n)一直处于高电位导致第七和第八薄膜晶体管T7、T8长时间受电应力所引起的电路不稳定。
特别需要说明的是，在该正向扫描的输出端G(n)及第一节点Q(n)低电位维持阶段，由于第n-1级GOA单元的输出端G(n-1)提供低电位，所述正向扫描直流控制信号U2D为高电位，第一薄膜晶体管T1导通，第四节点W1(n)即第十二薄膜晶体管T12的漏极为低电位，第三节点H(n)即第十二薄膜晶体管T12的源极为低电位，第十二薄膜晶体管T12的栅极接第n-1级 GOA单元的输出端G(n-1)，同样为低电位，从而第十二薄膜晶体管T12的栅极与源极之间的电压Vgs＝0V，漏极与源极之间的电压Vds＝0V，结合图3可知，该第十二薄膜晶体管T12的漏电流相比于现有技术明显减小。此外，在正向扫描的输出端G(n)及第一节点Q(n)低电位维持阶段，串联的第三薄膜晶体管T3与第十三薄膜晶体管T13均关闭，和传统的GOA电路相比，也会降低漏电流的发生。
请结合图4与图6，所述反向扫描直流控制信号D2U为高电位，正向扫描直流控制信号U2D为低电位，GOA电路反向扫描，具体工作过程为：
阶段1、预充电阶段：第n+1级GOA单元的输出端G(n+1)与反向扫描直流控制信号D2U均为高电位，第三和第十三薄膜晶体管T3、T13均导通，第五节点W2(n)与第三节点H(n)的电位被拉高，第五薄膜晶体管T5受恒压高电位VGH控制始终打开，第一节点Q(n)被预充电；受第三节点H(n)控制的第十一薄膜晶体管T11导通，第二节点P(n)被拉低至恒压低电位VGL。
阶段2、高电位输出阶段：第n+1级GOA单元的输出端G(n+1)转变为低电位，第十三薄膜晶体管T13关闭，第M条时钟信号CK(M)提供高电位，第一节点Q(n)在第一电容C1的存储作用下继续保持高电位，受第一节点Q(n)控制的第二薄膜晶体管T2导通，第M条时钟信号提供的高电位经由第二薄膜晶体管T2输出至输出端G(n)。
阶段3、低电位输出阶段：第M+1条时钟信号CK(M+1)提供高电位，第六和第四薄膜晶体管T6、T4导通，第三节点H(n)、第一节点Q(n)、和输出端G(n)均被拉低至恒压低电位VGL。
阶段4、输出端G(n)及第一节点Q(n)低电位维持阶段：第三节点H(n)转变为低电位后，受第三节点H(n)控制的第十一薄膜晶体管T11关闭；第M条时钟信号CK(M)、第M+1条时钟信号CK(M+1)交替提供高电位：当第M条时钟信号CK(M)提供高电位时，第十薄膜晶体管T10导通，第二节点P(n)抬升至恒压高电位VGH，受第二节点P(n)控制的第七和第八薄膜晶体管T7、T8均导通，维持第三节点H(n)、第一节点Q(n)、和输出端G(n)为低电位；当第M+1条时钟信号CK(M+1)为高电位时，第六和第四薄膜晶体管T6、T4均导通，维持第三节点H(n)、第一节点Q(n)、和输出端G(n)为低电位，同时第九薄膜晶体管T9也导通，第二节点P(n)也被拉低至低电位，关闭第七和第八薄膜晶体管T7、T8，防止第二节点P(n)一直处于高电位导致第七和第八薄膜晶体管T7、T8长时间受电应力所引起的电路不稳定。
特别需要说明的是，在该反向扫描的输出端G(n)及第一节点Q(n)低电位维持阶段，由于第n+1级GOA单元的输出端G(n+1)提供低电位，所述 反向扫描直流控制信号D2U为高电位，第三薄膜晶体管T3导通，第五节点W2(n)即第十三薄膜晶体管T13的漏极为低电位，第三节点H(n)即第十三薄膜晶体管T13的源极为低电位，第十三薄膜晶体管T13的栅极接第n+1级GOA单元的输出端G(n+1)，同样为低电位，从而第十三薄膜晶体管T13的栅极与源极之间的电压Vgs＝0V，漏极与源极之间的电压Vds＝0V，结合图3可知，该第十三薄膜晶体管T13的漏电流相比于现有技术明显减小。此外，在反向扫描的输出端G(n)及第一节点Q(n)低电位维持阶段，串联的第一薄膜晶体管T1与第十二薄膜晶体管T12均关闭，和传统的GOA电路相比，也会降低漏电流的发生。
综上所述，本发明的基于LTPS半导体薄膜晶体管的GOA电路，增设了分别受第n-1级GOA单元的输出端、和第n+1级GOA单元的输出端控制的第十二薄膜晶体管、和第十三薄膜晶体管，第十二薄膜晶体管的漏极通过第四节点与第一薄膜晶体管的源极电性连接，第一薄膜晶体管的漏极与第n-1级GOA单元的输出端电性连接，第十三薄膜晶体管的漏极通过第五节点与第三薄膜晶体管的源极电性连接，第三薄膜晶体管的漏极与第n+1级GOA单元的输出端电性连接，第一、和第三薄膜晶体管分别受正向扫描直流控制信号、与反向扫描直流控制信号控制，在正向扫描至输出端及第一节点低电平维持阶段时，第四节点为低电位，能够降低第十二薄膜晶体管的漏电流，在反向扫描至输出端及第一节点低电平维持阶段时，第五节点为低电位，能够降低第十三薄膜晶体管的漏电流，从而降低了关键薄膜晶体管的漏电流，提升了GOA电路的稳定性。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (13)

  1. 一种基于LTPS半导体薄膜晶体管的GOA电路，包括：级联的多个GOA单元，每个GOA单元均包括：正反向扫描控制单元、输出单元、及节点控制单元；
    设n为正整数，除第一级、与最后一级GOA单元外，在第n级GOA单元中：
    所述正反向扫描控制单元包括：第一薄膜晶体管，所述第一薄膜晶体管的栅极电性连接于正向扫描直流控制信号，漏极电性连接于上一级第n-1级GOA单元的输出端，源极电性连接于第四节点；第十二薄膜晶体管，所述第十二薄膜晶体管的栅极电性连接于上一级第n-1级GOA单元的输出端，漏极电性连接于第四节点，源极电性连接于第三节点；第三薄膜晶体管，所述第三薄膜晶体管的栅极电性连接于反向扫描直流控制信号，源极电性连接于第五节点，漏极电性连接于下一级第n+1级GOA单元的输出端；以及第十三薄膜晶体管，所述第十三薄膜晶体管的栅极电性连接于下一级第n+1级GOA单元的输出端，漏极电性连接于第五节点，源极电性连接于第三节点；
    所述输出单元包括：第二薄膜晶体管，所述第二薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极电性连接于输出端；以及第一电容，所述第一电容的一端电性连接于第一节点，另一端电性连接于输出端；
    所述节点控制单元包括：第四薄膜晶体管，所述第四薄膜晶体管的栅极电性连接于第M+1条时钟信号，源极电性连接于输出端，漏极电性连接于恒压低电位；第五薄膜晶体管，所述第五薄膜晶体管的栅极电性连接于恒压高电位，源极电性连接于第三节点，漏极电性连接于第一节点；第六薄膜晶体管，所述第六薄膜晶体管的栅极电性连接于第M+1条时钟信号，源极电性连接于第三节点，漏极电性连接于恒压低电位；第七薄膜晶体管，所述第七薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第三节点，漏极电性连接于恒压低电位；第八薄膜晶体管，所述第八薄膜晶体管的栅极电性连接于第二节点，源极电性连接于输出端，漏极电性连接于恒压低电位；第九薄膜晶体管，所述第九薄膜晶体管的栅极电性连接于第M+1条时钟信号，源极电性连接于第二节点，漏极电性连接于恒压低电位；第十薄膜晶体管，所述第十薄膜晶体管的栅极电性连接于第M条时钟信号， 源极电性连接于恒压高电位，漏极电性连接于第二节点；第十一薄膜晶体管，所述第十一薄膜晶体管的栅极电性连接于第三节点，源极电性连接于第二节点，漏极电性连接于恒压低电位；以及第二电容，所述第二电容的一端电性连接于第二节点，另一端电性连接于恒压低电位；
    正向扫描直流控制信号与反向扫描直流控制信号的电位相反。
  2. 如权利要求1所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，具备正反向扫描功能；
    在正向扫描进入到输出端及第一节点低电位维持阶段时，第十二薄膜晶体管的栅极与源极之间的电压为0V，漏极与源极之间的电压为0V，第三薄膜晶体管与第十三薄膜晶体管均关闭；
    在反向扫描进入到输出端及第一节点低电位维持阶段时，第十三薄膜晶体管的栅极与源极之间的电压为0V，漏极与源极之间的电压为0V，第一薄膜晶体管与第十二薄膜晶体管均关闭。
  3. 如权利要求1所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，在第一级GOA单元中，所述第一薄膜晶体管的漏极电性连接于电路起始信号。
  4. 如权利要求1所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，在最后一级GOA单元中，所述第三薄膜晶体管的漏极电性连接于电路起始信号。
  5. 如权利要求2所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，所述正向扫描直流控制信号为高电位，反向扫描直流控制信号为低电位时，进行正向扫描。
  6. 如权利要求2所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，所述正向扫描直流控制信号为低电位，反向扫描直流控制信号为高电位时，进行反向扫描。
  7. 如权利要求1所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，所述时钟信号包括两条时钟信号：第一条时钟信号、和第二条时钟信号，当所述第M条时钟信号为第二条时钟信号时，第M+1条时钟信号为第一条时钟信号。
  8. 如权利要求1所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，所述薄膜晶体管均为N型低温多晶硅半导体薄膜晶体管。
  9. 一种基于LTPS半导体薄膜晶体管的GOA电路，包括：级联的多个GOA单元，每个GOA单元均包括：正反向扫描控制单元、输出单元、及节点控制单元；
    设n为正整数，除第一级、与最后一级GOA单元外，在第n级GOA单元中：
    所述正反向扫描控制单元包括：第一薄膜晶体管，所述第一薄膜晶体管的栅极电性连接于正向扫描直流控制信号，漏极电性连接于上一级第n-1级GOA单元的输出端，源极电性连接于第四节点；第十二薄膜晶体管，所述第十二薄膜晶体管的栅极电性连接于上一级第n-1级GOA单元的输出端，漏极电性连接于第四节点，源极电性连接于第三节点；第三薄膜晶体管，所述第三薄膜晶体管的栅极电性连接于反向扫描直流控制信号，源极电性连接于第五节点，漏极电性连接于下一级第n+1级GOA单元的输出端；以及第十三薄膜晶体管，所述第十三薄膜晶体管的栅极电性连接于下一级第n+1级GOA单元的输出端，漏极电性连接于第五节点，源极电性连接于第三节点；
    所述输出单元包括：第二薄膜晶体管，所述第二薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M条时钟信号，漏极电性连接于输出端；以及第一电容，所述第一电容的一端电性连接于第一节点，另一端电性连接于输出端；
    所述节点控制单元包括：第四薄膜晶体管，所述第四薄膜晶体管的栅极电性连接于第M+1条时钟信号，源极电性连接于输出端，漏极电性连接于恒压低电位；第五薄膜晶体管，所述第五薄膜晶体管的栅极电性连接于恒压高电位，源极电性连接于第三节点，漏极电性连接于第一节点；第六薄膜晶体管，所述第六薄膜晶体管的栅极电性连接于第M+1条时钟信号，源极电性连接于第三节点，漏极电性连接于恒压低电位；第七薄膜晶体管，所述第七薄膜晶体管的栅极电性连接于第二节点，源极电性连接于第三节点，漏极电性连接于恒压低电位；第八薄膜晶体管，所述第八薄膜晶体管的栅极电性连接于第二节点，源极电性连接于输出端，漏极电性连接于恒压低电位；第九薄膜晶体管，所述第九薄膜晶体管的栅极电性连接于第M+1条时钟信号，源极电性连接于第二节点，漏极电性连接于恒压低电位；第十薄膜晶体管，所述第十薄膜晶体管的栅极电性连接于第M条时钟信号，源极电性连接于恒压高电位，漏极电性连接于第二节点；第十一薄膜晶体管，所述第十一薄膜晶体管的栅极电性连接于第三节点，源极电性连接于第二节点，漏极电性连接于恒压低电位；以及第二电容，所述第二电容的一端电性连接于第二节点，另一端电性连接于恒压低电位；
    正向扫描直流控制信号与反向扫描直流控制信号的电位相反；
    其中，具备正反向扫描功能；
    在正向扫描进入到输出端及第一节点低电位维持阶段时，第十二薄膜晶体管的栅极与源极之间的电压为0V，漏极与源极之间的电压为0V，第三薄膜晶体管与第十三薄膜晶体管均关闭；
    在反向扫描进入到输出端及第一节点低电位维持阶段时，第十三薄膜晶体管的栅极与源极之间的电压为0V，漏极与源极之间的电压为0V，第一薄膜晶体管与第十二薄膜晶体管均关闭；
    其中，在第一级GOA单元中，所述第一薄膜晶体管的漏极电性连接于电路起始信号；
    其中，在最后一级GOA单元中，所述第三薄膜晶体管的漏极电性连接于电路起始信号。
  10. 如权利要求9所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，所述正向扫描直流控制信号为高电位，反向扫描直流控制信号为低电位时，进行正向扫描。
  11. 如权利要求9所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，所述正向扫描直流控制信号为低电位，反向扫描直流控制信号为高电位时，进行反向扫描。
  12. 如权利要求9所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，所述时钟信号包括两条时钟信号：第一条时钟信号、和第二条时钟信号，当所述第M条时钟信号为第二条时钟信号时，第M+1条时钟信号为第一条时钟信号。
  13. 如权利要求9所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，所述薄膜晶体管均为N型低温多晶硅半导体薄膜晶体管。
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Families Citing this family (20)

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Publication number Priority date Publication date Assignee Title
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CN106486075B (zh) * 2016-12-27 2019-01-22 武汉华星光电技术有限公司 Goa电路
CN107068074B (zh) * 2016-12-27 2019-04-30 武汉华星光电技术有限公司 Goa电路
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CN109300428A (zh) * 2018-11-28 2019-02-01 武汉华星光电技术有限公司 Goa电路及显示面板
CN109509443A (zh) * 2018-12-04 2019-03-22 昆山龙腾光电有限公司 栅极驱动电路及显示装置
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CN111179871B (zh) * 2020-02-12 2021-01-15 武汉华星光电技术有限公司 一种goa电路及其显示面板
CN111326096A (zh) * 2020-04-07 2020-06-23 武汉华星光电技术有限公司 Goa电路及显示面板
CN112037721B (zh) * 2020-08-06 2022-02-22 武汉华星光电技术有限公司 Goa电路及其显示面板、显示装置
CN113643640B (zh) * 2021-08-03 2023-06-02 武汉华星光电技术有限公司 栅极驱动电路及显示面板
CN113643641A (zh) * 2021-08-03 2021-11-12 武汉华星光电技术有限公司 栅极驱动电路及显示面板
CN114596828B (zh) * 2022-04-25 2022-12-09 福建华佳彩有限公司 一种降低负载的12t1c gip电路及其驱动方法
CN115394232A (zh) * 2022-09-28 2022-11-25 信利(仁寿)高端显示科技有限公司 一种栅极扫描电路及方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102945651A (zh) * 2012-10-31 2013-02-27 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路和显示装置
CN103021309A (zh) * 2011-09-23 2013-04-03 海蒂斯技术有限公司 移位寄存器及利用该移位寄存器的栅极驱动电路
KR20140014746A (ko) * 2012-07-26 2014-02-06 엘지디스플레이 주식회사 쉬프트 레지스터
CN104318909A (zh) * 2014-11-12 2015-01-28 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及其驱动方法、显示面板
CN104537992A (zh) * 2014-12-30 2015-04-22 深圳市华星光电技术有限公司 用于液晶显示装置的goa电路

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007317288A (ja) * 2006-05-25 2007-12-06 Mitsubishi Electric Corp シフトレジスタ回路およびそれを備える画像表示装置
JP5618821B2 (ja) * 2010-12-28 2014-11-05 株式会社ジャパンディスプレイ 双方向シフトレジスタ及びこれを用いた画像表示装置
CN103594118B (zh) * 2012-08-17 2016-09-07 瀚宇彩晶股份有限公司 液晶显示器及其双向移位寄存装置
KR102072214B1 (ko) * 2013-07-09 2020-02-03 삼성디스플레이 주식회사 주사 구동 장치 및 이를 포함하는 표시 장치
CN103927960B (zh) * 2013-12-30 2016-04-20 上海中航光电子有限公司 一种栅极驱动装置和显示装置
CN104091573B (zh) * 2014-06-18 2016-08-17 京东方科技集团股份有限公司 一种移位寄存单元、栅极驱动装置、显示面板和显示装置
TWI541779B (zh) * 2014-07-18 2016-07-11 友達光電股份有限公司 移位暫存器及移位暫存器的驅動方法
TWI537912B (zh) * 2014-07-21 2016-06-11 友達光電股份有限公司 移位暫存器及使用其之平面顯示器
CN104318908A (zh) * 2014-10-22 2015-01-28 友达光电股份有限公司 一种可增强电路驱动能力的栅极驱动电路
CN104409054B (zh) * 2014-11-03 2017-02-15 深圳市华星光电技术有限公司 低温多晶硅薄膜晶体管goa电路
CN104505044B (zh) * 2014-12-29 2017-07-28 上海天马微电子有限公司 一种栅极驱动电路、阵列基板、显示面板和显示装置
CN104464605B (zh) * 2014-12-30 2017-12-08 上海中航光电子有限公司 一种移位寄存器及其驱动方法、栅极驱动电路及显示屏
CN104485079B (zh) * 2014-12-31 2017-01-18 深圳市华星光电技术有限公司 用于液晶显示装置的goa电路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103021309A (zh) * 2011-09-23 2013-04-03 海蒂斯技术有限公司 移位寄存器及利用该移位寄存器的栅极驱动电路
KR20140014746A (ko) * 2012-07-26 2014-02-06 엘지디스플레이 주식회사 쉬프트 레지스터
CN102945651A (zh) * 2012-10-31 2013-02-27 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路和显示装置
CN104318909A (zh) * 2014-11-12 2015-01-28 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及其驱动方法、显示面板
CN104537992A (zh) * 2014-12-30 2015-04-22 深圳市华星光电技术有限公司 用于液晶显示装置的goa电路

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