WO2016090849A1 - 移位寄存器及其驱动方法、移位扫描电路和显示装置 - Google Patents

移位寄存器及其驱动方法、移位扫描电路和显示装置 Download PDF

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WO2016090849A1
WO2016090849A1 PCT/CN2015/079127 CN2015079127W WO2016090849A1 WO 2016090849 A1 WO2016090849 A1 WO 2016090849A1 CN 2015079127 W CN2015079127 W CN 2015079127W WO 2016090849 A1 WO2016090849 A1 WO 2016090849A1
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Prior art keywords
node
unit
inverting
switch unit
shift register
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PCT/CN2015/079127
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English (en)
French (fr)
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孙拓
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京东方科技集团股份有限公司
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Priority to EP15785036.3A priority Critical patent/EP3232430B1/en
Priority to US14/888,776 priority patent/US9530355B2/en
Publication of WO2016090849A1 publication Critical patent/WO2016090849A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0417—Special arrangements specific to the use of low carrier mobility technology
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0871—Several active elements per pixel in active matrix panels with level shifting
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to a shift register and a method of driving the same, a shift scan circuit, and a display device.
  • OLED Organic Light Emitting Diode
  • PMOLED Passive Matrix Driving OLED
  • AMOLED Active Matrix Driving OLED
  • AMOLED displays are expected to become the next generation of new flat panel displays that replace LCD (liquid crystal displays) due to their low manufacturing cost, high response speed, power saving, DC drive for portable devices, and large operating temperature range. Therefore, AMOLED display panels with in-cell touch functions have been favored by more and more people.
  • LTPS AMOLED Low Temperature Poly-silicon AMOLED, low temperature polysilicon active matrix organic light emitting diode
  • the shift register generally shifts and outputs the input signal directly, and PMOS (positive channel metal oxide semiconductor) is generally used for outputting negative logic (negative pulse signal). Therefore, the shift register in the technique known to the inventors cannot output a positive logic (positive pulse signal) if a PMOS structure is employed, and cannot be applied to the LTPS AMOLED.
  • An embodiment of the present disclosure provides a shift register including: an input switch unit, an inverting unit, an output switch unit, and a first node voltage maintaining unit;
  • the output end of the input switch unit is connected to the first node, and is turned on according to a control signal applied by the control terminal thereof;
  • the voltage stabilizing end of the first node voltage maintaining unit is connected to the first node, and is adapted to be in the Recording the level of the first node when the input switch unit is turned on, and maintaining the input end of the inverting unit to the recorded level when the input switch unit is turned off;
  • the output end of the inverting unit is connected to the second node, and is adapted to invert the level of the first node and output to the second node in response to a control signal accessed by the control terminal thereof;
  • the control end of the output switch unit is connected to the second node, and is turned on according to the level state of the second node.
  • a leakage protection switch unit is further included, an input end of the leakage protection switch unit is connected to an output end of the output switch unit, and a control end is connected to the first node, according to a level state of the first node Turn on.
  • first lock switch unit and a second lock switch unit wherein the first lock switch unit and the second lock switch unit are turned on according to a level state of the control end thereof;
  • the output end of the first lock switch unit is connected to the input end of the second lock switch unit, and the control end is connected to the second node; the output end of the second lock switch unit is connected to the first node.
  • a second node voltage maintaining unit wherein the voltage stabilizing end of the second node voltage maintaining unit is connected to the second node, and is adapted to record the level of the first node when the inverting unit operates, and The second node is maintained at the recorded level when the inverting unit stops operating.
  • the inverting unit includes: a first inverting switching unit, a second inverting switching unit, a third inverting switching unit, and a third node voltage maintaining unit; wherein each of the inverting switching units is according to a control end thereof The level state is turned on, and the control end of the inverting unit is a control end of the first inverting switch unit;
  • the output end of the first inverting switch unit and the control end of the second inverting switch unit are connected to the third node, the output end of the second inverting switch unit and the input end of the third inverting switch unit and Two nodes are connected; an output end of the third inverting switch unit is connected to the first node;
  • the voltage stabilizing end of the third node voltage maintaining unit is connected to the third node, and is adapted to record the level of the third node when the first inverting switching unit is turned on, and at the first The third node is maintained at the recorded level when the inverting switch unit is turned off.
  • the inverting unit includes: a first inverting switching unit, a second inverting switching unit, a third inverting switching unit, and a fourth inverting switching unit; wherein each of the inverting switching units is based on a level state of the control terminal, the control end of the inverting unit is a control end of the first inverting switch unit;
  • the output end of the first inverting switch unit and the control end of the second inverting switch unit and the input end of the fourth inverting switch unit are connected to the third node, and the output end of the second inverting switch unit is opposite to the first
  • the input end of the three-phase inverting switch unit is connected to the second node; the output end of the third inverting switch unit is connected to the first node.
  • each of the switching units is a P-channel transistor, and the voltage stabilizing unit is a capacitor.
  • the present invention also provides a shift scan circuit comprising: a plurality of cascaded shift registers as described in any of the above.
  • the method further includes: at least one clock signal line; wherein, the control end of the input switch unit in each shift register is connected to the same clock signal line, and the input end of the output switch unit is connected to the same clock signal line; and the shift register of the stage The input of the middle input switch unit is connected to the output of the shift register of the previous stage.
  • the inverting unit includes a first inverting switching unit, a second inverting switching unit, a third inverting switching unit, and a third node voltage maintaining unit
  • the first inverting switch in each shift register The control terminal of the unit is connected to the same clock signal line, and the clock signal line is different from the clock signal line to which the control terminal of the input switch unit is connected.
  • the inverting unit includes a first inverting switching unit, a second inverting switching unit, a third inverting switching unit, and a fourth inverting switching unit
  • the first inversion in the shift register of the current stage The control end of the switch unit is connected to the output end of the shift register of the previous stage, and the input end is connected to the second node of the shift register of the previous stage.
  • each of the shift registers includes the first lock switch unit and the second lock switch unit
  • the control terminals of the second lock switch units in the respective shift registers are connected to the same clock signal line, and the clock signal lines are different from the input The clock signal line to which the control terminal of the switch unit is connected.
  • clock signal line connected to the input end of the output switch unit and the clock signal line connected to the control end of the input switch unit are the same clock signal line.
  • An embodiment of the present disclosure further provides a method for driving a shift register for driving the shift register of any of the above, the method comprising:
  • a high level signal is applied to the input terminal of the output switching unit, and a low level signal is applied for another clock cycle.
  • An embodiment of the present disclosure also provides a display device comprising the shift scan circuit of any of the above.
  • the shift register provided by the embodiment of the present disclosure may implement a PMOS structure to shift a positive logic scan signal and output a positive logic scan signal, so that the PMOS structure can be used for scan driving the LTPS AMOLED.
  • FIG. 1 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of an alternative structure of the shift register of FIG. 1;
  • FIG. 3 is a diagram showing potential signals and potentials of nodes in a method for driving the shift register of FIG. 2;
  • FIG. 4 is a block diagram of a key signal and a node in a method for driving the shift register of FIG. 2;
  • FIG. 5 is a schematic structural diagram of still another alternative structure of the shift register of FIG. 1;
  • FIG. 6 is a diagram of a key signal and a potential map of a node in a method for driving the shift register of FIG. 5;
  • FIG. 7 is a block diagram showing the structure of a shift scan circuit including the shift register of FIG.
  • Embodiments of the present disclosure provide a shift register, as shown in FIG. 1, the shift register includes:
  • Input switch unit inverting unit, output switch unit, first node voltage maintaining unit; for convenience of description, the input end of each unit is represented as I in the figure, and the output end is represented as O, the control end Expressed as CON;
  • the output end of the input switch unit is connected to the first node N1, and is turned on according to a control signal applied by the control terminal thereof;
  • the voltage stabilizing end of the first node voltage maintaining unit is connected to the first node N1, and is adapted to record the level of the first node when the input switching unit is turned on, and maintain the input end of the inverting unit when the input switching unit is turned off For the recorded level;
  • the output end of the inverting unit is connected to the second node, and is adapted to invert the level of the first node N1 and output to the second node N2 in response to a control signal accessed by the control terminal thereof;
  • the control terminal of the output switching unit is connected to the second node N1, and is turned on according to the level state of the second node N1.
  • Embodiments of the present disclosure also provide a method that can be used to drive the shift register described above, the method comprising:
  • a high level is applied to the input terminal of the output switching unit, and a low level is applied for another clock cycle.
  • the shift register and the driving method thereof provided by the embodiments of the present disclosure can enable a shift register of a PMOS structure to shift a positive logic scan signal and output a positive logic scan signal, and combine some implementation structures and driving methods.
  • the operation of the shift register provided by the disclosed embodiments is described.
  • FIG. 2 is a schematic structural diagram of an alternative structure of the shift register of FIG. 1, including 9 PMOS transistors and two capacitors C1 and C2, wherein the drain of the first transistor T1 and the source of the second transistor T2
  • the gate of the fourth transistor T4 is connected to the third node N3, the gate of the second transistor T2 is connected to the drain, the drain of the third transistor T3, the gate of the fifth transistor T5, and the drain of the seventh transistor T7.
  • a gate of the ninth transistor T9 one end of the capacitor C1 is connected to the first node N1; a source of the fourth transistor T4, a drain of the fifth transistor T5, and a gate of the eighth transistor T8 And one end of the capacitor C2 is connected to the second node N2; the drain of the eighth transistor T8, the source of the ninth transistor T9 and the end of the capacitor C1 not connected to the node N1 are connected.
  • the gate of the first transistor T1 and the source of the third transistor T3 can be connected to the scan signal STV to make the source and the fifth transistor of the first transistor T1.
  • the source of T5 and the end of the capacitor C2 not connected to the node N2 are connected to the high level VGH, so that the drain of the fourth transistor T4 and the drain of the second transistor T2 are connected to a low level VGL, and the first transistor T3
  • a gate of the first clock signal CK1 is connected, and a gate of the seventh transistor T7 is connected to a second clock signal CK2.
  • the source of the eighth transistor T8 can be connected to one of CK1 and CK2.
  • the drain of the eighth transistor T8 constitutes the output Eout of the shift register.
  • the key signal in the method of driving the shift register in FIG. 2 and the potential map of the node can be as shown in FIG.
  • CK1 is low and CK2 is high opposite CK1.
  • the third transistor T3 is turned on, and the level of the node N1 is at a high level, causing the fifth transistor T5 and the ninth transistor T9 to be turned off.
  • the first transistor T1 is also turned off.
  • the node N3 is pulled low, and is low, thereby causing the fourth transistor T4 to be turned on, so that the level of the node N2 is low.
  • the eighth transistor T8 is turned on, and Eout (the drain of the eighth transistor T8) outputs a high-level signal (positive pulse signal). Since CK2 is high, the seventh transistor T7 is turned off.
  • the sixth transistor T6 and the seventh transistor T7 are turned on. At this time, even if the capacitor C1 fails, the level of the node N1 cannot be maintained at a high level, the node N1 will still be pulled high by VGH, ensuring that the ninth transistor T9 is turned off.
  • the sixth transistor T6 and the seventh transistor T7 function to lock the ninth transistor T9.
  • the shift register in FIG. 2 completes the shift of the positive logic signal and outputs a positive logic signal.
  • the third phase after the second phase, STV is low, CK1 is low, and CK2 is high.
  • the third transistor T3 is turned on, and since the STV is at a low level, the voltage of the node N1 is Pulling low, the fifth transistor T5 and the ninth transistor T9 are turned on, and the voltage of the node N2 is pulled high.
  • the states of the first transistor T1 and the fourth transistor T4 remain unchanged. Since CK2 is at a high level, the node N2 is also at a high level, and the sixth transistor T6 and the seventh transistor T7 are both turned off.
  • the third phase is equivalent to completing the reset of the voltage of each node.
  • the application of the high level on the fifth transistor T5 can be stopped, and the node N2 can be maintained at the high level due to the presence of the capacitor C2.
  • the turn-off of the eighth transistor T8 is ensured so that the output terminal Eout does not output a high level again.
  • Setting capacitor C2 can avoid continuing to apply a high voltage to the source of the fifth transistor after completing the output of the positive logic signal, reducing the power consumption of the shift register.
  • the above shift register can complete the shift of the positive logic signal and output the positive logic signal, and the embodiments of the present disclosure are not to be construed as limiting the scope of the disclosure.
  • the advantage of setting the ninth transistor T9 is that even if there is leakage current at the Eout terminal, it will flow into the low voltage terminal through the ninth transistor T9, and will not output a high level signal here, so that the second stage can be well guaranteed. After that, no high level signal is output.
  • the ninth transistor T9 is not provided, since the node N2 is maintained at a high level after the second phase, the Eout terminal generally does not have a high level signal output without leakage.
  • the ninth transistor T9 is not provided, and the shift register of the embodiment of the present disclosure does not affect the shift of the positive logic signal and outputs a positive logic signal, and the corresponding technical solution should also fall within the protection scope of the present disclosure.
  • the sixth transistor T6 and the seventh transistor T7 in FIG. 2 are not necessarily structures that must be provided.
  • the ninth transistor T9 is not turned on in the second stage of outputting the positive logic signal, and accordingly does not affect the shift of the embodiment of the present disclosure.
  • the bit register implements the function of shifting the output.
  • the end of the capacitor C2 that is not connected to the node N2 may not be connected to the VGH. Accordingly, the end of the capacitor C1 not connected to the node N1 does not necessarily need to be connected to Eout, and the corresponding solution does not affect the present disclosure. Implementation.
  • the key signal in the method of driving the shift register in the shift register of FIG. 2 and the potential map of the node can be as shown in FIG.
  • CK1 is low and CK2 is low.
  • the third transistor T3 is turned on, and the level of the node N1 is at a high level, causing the fifth transistor T5 and the ninth transistor T9 to be turned off.
  • the first transistor T1 is also turned off, and at this time, the node N3 is pulled low, and is low. This in turn causes the fourth transistor T4 to turn on, causing the level of the node N2 to be low.
  • the eighth transistor T8 is turned on because the CK2 is at a low level and the Eout terminal is output at a low level.
  • CK1 is at a high level
  • CK2 is also at a high level.
  • the voltages of the node N1 and the node N2 remain unchanged, and the eighth transistor T8 is in an on state.
  • the Eout terminal still outputs a high level. This completes the shift output of the positive logic signal.
  • the third transistor T3 implements input control of the positive logic signal and functions as an input switch unit.
  • the eighth transistor T8 realizes output control of the positive logic signal and functions as an output switching unit.
  • the first transistor T1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 collectively invert and output the level of the node N1 to constitute an inverting unit.
  • the ninth transistor T9 functions as a leakage protection switch and functions as a leakage protection switch unit.
  • the sixth transistor T6 and the seventh transistor T7 function to lock the ninth transistor T9 and function as a lock switch unit.
  • the capacitor C1 and the capacitor C2 function to maintain the level of the node N1 or N2, and constitute a voltage maintaining unit.
  • Embodiments of the present disclosure also provide a shift scan circuit formed by cascaded shift registers of FIG. 2 in multiple stages.
  • the shift register also includes a plurality of clock signal lines.
  • the gate of the third transistor T3 of each shift register is connected to the same clock signal line CK1, and the sixth transistor T6 is connected to a clock signal line CK2 different from CK1, and the eighth transistor T8
  • the source can be connected to CK1 or CK2.
  • the drain of the eighth transistor T8 in the shift register of the stage is connected to the source of the third transistor T3 and the gate of the first transistor T1 in the shift register of the next stage, to the source of the third transistor T3 and the first transistor
  • the gate of T1 provides an input positive logic signal. It is not difficult to see that if the sixth transistor T6 and the seventh transistor T7 are not provided, the shift scanning circuit may include only one clock signal line.
  • FIG. 5 is a schematic structural diagram of still another alternative structure of the shift register of FIG. 1. Unlike the shift register of FIG. 2, a capacitor C3 is used instead of the second transistor T2 in FIG. . Other structures and connection relationships are unchanged.
  • CK2 can be applied to the gate of the first transistor T1, and its source can be connected to the node N2' of the shift register of the previous stage.
  • the key signal on the shift register in FIG. 5 and the potential map of the key node can be as shown in FIG. 6, wherein the potential timings of CK1, CK2, node N1, node N2, Eout, and STV are the same as those in FIG.
  • the difference from Fig. 3 is that since the node N2' of the shift register of the previous stage is low only in the first stage, it remains high after the first stage.
  • the voltage of the N2' node can be introduced to charge one end of the capacitor C3 connected to the node N3.
  • the voltage of the node N3 is maintained at a high level (when turned on, the potential is equal to the N2' point, and is the same as the high level, and is maintained when not conducting. Is high).
  • the power consumption can be further reduced compared to the manner in which it is necessary to continuously output the high voltage to maintain the node N3 at the source of the first transistor T1 after the first stage in FIG.
  • Embodiments of the present disclosure also provide a shift scan circuit formed by cascading shift registers of FIG. 5 in multiple stages, the shift scan circuit further including at least one clock signal line.
  • 7 is a schematic structural diagram of a cascade of shift registers of the mth stage and the m+1th stage, wherein the first transistor T1 of each shift register is connected to the same clock signal line CK2, and the gate of the third transistor T3 is connected.
  • the same clock signal line CK1, the sixth transistor T6 is connected to a clock signal line CK2 different from CK1, and the source of the eighth transistor T8 can be connected to CK1 or CK2.
  • the drain of the eighth transistor T8 in the mth stage shift register is connected to the source of the third transistor T3 in the m+1th stage shift register, and a positive logic signal is input to the source of the third transistor T3.
  • the node N2 in the mth stage shift register is connected to the source of the first transistor T1 in the m+1th stage shift register.
  • An embodiment of the present disclosure further provides a display device including the shift scan circuit according to any one of the above, which may be a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc. Any product or part that has a display function.

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  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Shift Register Type Memory (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种移位寄存器及其驱动方法、移位扫描电路和显示装置，该移位寄存器包括：输入开关单元、反相单元、输出开关单元、第一节点电压维持单元；输入开关单元的输出端（O）与第一节点（N1）相连；第一节点电压维持单元的稳压端与第一节点（N1）相连，适于在输入开关单元导通时记录第一节点（N1）的电平，并在输入开关单元关断时将反相单元的输入端（I）维持为所记录的电平；反相单元的输出端（O）与第二节点（N2）相连；输出开关单元的控制端（CON）与第二节点（N2）相连。本方案提供的移位寄存器可以采用PMOS结构实现对正逻辑的扫描信号进行移位并输出正逻辑的扫描信号，使得PMOS结构能够用于对LTPS AMOLED进行扫描驱动。

Description

移位寄存器及其驱动方法、移位扫描电路和显示装置 技术领域
本公开涉及一种移位寄存器及其驱动方法、移位扫描电路、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)作为一种电流型发光器件，因其所具有的自发光、快速响应、宽视角和可制作在柔性衬底上等特点而越来越多地被应用于高性能显示领域当中。OLED显示装置按照驱动方式的不同可分为PMOLED(Passive Matrix Driving OLED，无源矩阵驱动有机发光二极管)和AMOLED(Active Matrix Driving OLED，有源矩阵驱动有机发光二极管)两种。AMOLED显示器由于具有低制造成本、高应答速度、省电、可用于便携式设备的直流驱动、工作温度范围大等优点而可望成为取代LCD(liquid crystal display，液晶显示器)的下一代新型平面显示器。因此，具有内嵌式触控功能的AMOLED显示面板已得到越来越多人们的青睐。
LTPS AMOLED(Low Temperature Poly-silicon AMOLED，低温多晶硅有源矩阵有机发光二极体)一般采用正脉冲用于像素的驱动。据发明人已知的技术中的移位寄存器一般对输入信号直接进行移位并输出，而由于PMOS(positive channel Metal Oxide Semiconductor，P型金属氧化物半导体)一般用于输出负逻辑(负脉冲信号)，因此，据发明人已知的技术中的移位寄存器如果采用PMOS结构则无法输出正逻辑(正脉冲信号)，不能应用于LTPS AMOLED中。
发明内容
本公开的实施例提供了一种移位寄存器，其包括：输入开关单元、反相单元、输出开关单元、第一节点电压维持单元；其中，
所述输入开关单元的输出端与第一节点相连，根据自身控制端施加的控制信号导通；
所述第一节点电压维持单元的稳压端与所述第一节点相连，适于在所述 输入开关单元导通时记录所述第一节点的电平，并在所述输入开关单元关断时将所述反相单元的输入端维持为所记录的电平；
所述反相单元的输出端与第二节点相连，适于响应于自身控制端所接入的控制信号将所述第一节点的电平反相并输出到第二节点；
所述输出开关单元的控制端与所述第二节点相连，根据所述第二节点的电平状态导通。
进一步地，还包括漏电保护开关单元，所述漏电保护开关单元的输入端与所述输出开关单元的输出端相连，控制端与所述第一节点相连，根据所述第一节点的电平状态导通。
进一步地，还包括：
第一锁定开关单元和第二锁定开关单元，所述第一锁定开关单元和第二锁定开关单元根据其控制端的电平状态导通；其中，
所述第一锁定开关单元的输出端连接第二锁定开关单元的输入端，控制端连接第二节点；所述第二锁定开关单元的输出端连接第一节点。
进一步地，还包括：
第二节点电压维持单元，所述第二节点电压维持单元的稳压端与所述第二节点相连，适于在所述反相单元工作时记录所述第一节点的电平，并在所述反相单元停止工作时将所述第二节点维持为所记录的电平。
进一步地，所述反相单元包括：第一反相开关单元、第二反相开关单元、第三反相开关单元、第三节点电压维持单元；其中，各个反相开关单元均根据自身控制端的电平状态导通，所述反相单元的控制端为所述第一反相开关单元的控制端；
所述第一反相开关单元的输出端以及第二反相开关单元的控制端与第三节点相连，第二反相开关单元的输出端与所述第三反相开关单元的输入端以及第二节点相连；所述第三反相开关单元的输出端与第一节点相连；
所述第三节点电压维持单元的稳压端与所述第三节点相连，适于在所述第一反相开关单元导通时记录所述第三节点的电平，并在所述第一反相开关单元关断时将所述第三节点维持为所记录的电平。
进一步地，所述反相单元包括：第一反相开关单元、第二反相开关单元、第三反相开关单元、第四反相开关单元；其中，各个反相开关单元均根据自 身控制端的电平状态，所述反相单元的控制端为所述第一反相开关单元的控制端；
所述第一反相开关单元的输出端以及第二反相开关单元的控制端、第四反相开关单元的输入端与第三节点相连，第二反相开关单元的输出端与所述第三反相开关单元的输入端以及第二节点相连；所述第三反相开关单元的输出端与第一节点相连。
进一步地，各个开关单元均为P沟道型晶体管，稳压单元为电容。
本发明还提供了一种移位扫描电路，包括：多个级联的如上述任一项所述的移位寄存器。
进一步地，还包括：至少一条时钟信号线；其中，各个移位寄存中的输入开关单元的控制端连接同一时钟信号线，输出开关单元的输入端连接同一时钟信号线；且本级移位寄存器中输入开关单元的输入端与上一级移位寄存器中的输出端相连。
进一步地，当所述反相单元包括第一反相开关单元、第二反相开关单元、第三反相开关单元、第三节点电压维持单元时，各个移位寄存器中的第一反相开关单元的控制端连接同一时钟信号线，且该时钟信号线不同于输入开关单元的控制端所连接的时钟信号线。
进一步地，当所述反相单元包括第一反相开关单元、第二反相开关单元、第三反相开关单元、第四反相开关单元时，本级移位寄存器中的第一反相开关单元的控制端与上一级移位寄存器中的输出端相连，输入端连接上一级移位寄存器的第二节点。
进一步地，当各个移位寄存器包括第一锁定开关单元和第二锁定开关单元时，各个移位寄存器中的第二锁定开关单元的控制端连接同一时钟信号线，且该时钟信号线不同于输入开关单元的控制端所连接的时钟信号线。
进一步地，所述输出开关单元的输入端所连接的时钟信号线与输入开关单元的控制端所连接的时钟信号线为同一时钟信号线。
本公开的实施例还提供了一种移位寄存器的驱动方法，用于驱动上述任一项所述的移位寄存器，该方法包括：
在输入开关单元的控制端施加控制信号使输入开关单元在第一时钟周期导通，并在第二时钟周期关断；其中，第一时钟周期为向输入开关单元的输 入端输入高电平信号的时钟周期；
在反相单元的控制端施加控制信号使反相单元在第一时钟周期和第二时钟周期内对第一节点的电压进行反相并输出到第二节点；
在第一时钟周期和第二时钟周期之中的一个时钟周期内，在输出开关单元的输入端施加高电平信号，在另一个时钟周期内施加低电平信号。
本公开的实施例还提供了一种显示装置，包括上述任一项所述的移位扫描电路。
本公开的实施例提供的移位寄存器可以采用PMOS结构实现对正逻辑的扫描信号进行移位并输出正逻辑的扫描信号，使得PMOS结构能够用于对LTPS AMOLED进行扫描驱动。
附图说明
图1是本公开的实施例提供的一种移位寄存器的结构示意图；
图2为图1中的移位寄存器的一种可选结构的结构示意图；
图3是一种用于对图2中的移位寄存器进行驱动的方法中的关键信号以及节点的电位图；
图4是再一种用于对图2中的移位寄存器进行驱动的方法中的关键信号以及节点的电位图；
图5为图1中的移位寄存器的再一种可选结构的结构示意图；
图6是一种用于对图5中的移位寄存器进行驱动的方法中的关键信号以及节点的电位图；以及
图7为一种包含图5中的移位寄存器的移位扫描电路的结构示意图。
具体实施方式
下面结合附图和实施例，对本公开的实施方式作进一步详细描述。以下实施例用于说明本公开，但不用来限制本公开的范围。
本公开的实施例提供了一种移位寄存器，如图1所示，该移位寄存器包括：
输入开关单元、反相单元、输出开关单元、第一节点电压维持单元；为了方便说明，各个单元的输入端在图中表示为I，输出端表示为O，控制端 表示为CON；
输入开关单元的输出端与第一节点N1相连，根据自身控制端施加的控制信号导通；
第一节点电压维持单元的稳压端与第一节点N1相连，适于在输入开关单元导通时记录第一节点的电平，并在输入开关单元关断时将反相单元的输入端维持为所记录的电平；
反相单元的输出端与第二节点相连，适于响应于自身控制端所接入的控制信号将第一节点N1的电平反相并输出到第二节点N2；
输出开关单元的控制端与第二节点N1相连，根据第二节点N1的电平状态导通。
本公开的实施例还提供了一种可用于驱动上述移位寄存器的方法，该方法包括：
在输入开关单元的控制端施加控制信号使输入开关单元在第一时钟周期和第三时钟周期导通，并在第二时钟周期关断；其中，第一时钟周期为向输入开关单元的输入端输入高电平信号的时钟周期；
在反相单元的控制端施加控制信号使反相单元在第一时钟周期和第二时钟周期内对第一节点的电压进行反相并输出到第二节点，在第三时钟周期停止工作；
在第一时钟周期和第二时钟周期之中的一个时钟周期内，在输出开关单元的输入端施加高电平，在另一个时钟周期内施加低电平。
本公开的实施例提供的移位寄存器及其驱动方法，能够使得采用PMOS结构的移位寄存器对正逻辑的扫描信号进行移位并输出正逻辑的扫描信号，下面结合一些实施结构和驱动方法对本公开的实施例提供的移位寄存器的工作原理进行说明。
图2为图1中的移位寄存器的一种可选结构的结构示意图，其中包括9个PMOS晶体管和两个电容C1和C2，其中，第一晶体管T1的漏极、第二晶体管T2的源极、第四晶体管T4的栅极均连接第三节点N3，第二晶体管T2的栅极和漏极相连，第三晶体管T3的漏极、第五晶体管T5的栅极、第七晶体管T7的漏极、第九晶体管T9的栅极、电容C1的一端连接第一节点N1；第四晶体管T4的源极、第五晶体管T5的漏极、第八晶体管T8的栅极 以及电容C2的一端连接第二节点N2；第八晶体管T8的漏极、第九晶体管T9的源极与电容C1不与节点N1相连的一端相连。
同样参考图2，在上述的移位寄存器进行驱动时，可以使第一晶体管T1的栅极、第三晶体管T3的源极接入扫描信号STV，使第一晶体管T1的源极、第五晶体管T5的源极、以及电容C2不与节点N2相连的一端连接接入高电平VGH，使第四晶体管T4的漏极、第二晶体管T2的漏极连接一个低电平VGL，第一晶体管T3的栅极连接的一个第一时钟信号CK1，第七晶体管T7的栅极连接一个第二时钟信号CK2。第八晶体管T8的源极可接入CK1和CK2之中的一个。第八晶体管T8的漏极构成该移位寄存器的输出端Eout。
当第八晶体管T8的源极接入CK1时，对图2中的移位寄存器中进行驱动的方法中的关键信号以及节点的电位图可以如图3所示。
在STV为高电平的第一阶段，CK1为低电平，CK2为与CK1相反的高电平。此时第三晶体管T3导通，节点N1的电平为高电平，导致第五晶体管T5、第九晶体管T9关断。第一晶体管T1也被关断，此时节点N3被拉低，为低电平，进而导致第四晶体管T4开启，使得节点N2的电平为低电平。此时，第八晶体管T8导通，Eout(第八晶体管T8的漏极)输出的高电平信号(正脉冲信号)。由于CK2为高电平，第七晶体管T7关断。
在第一阶段之后的第二阶段，STV变为低电平，CK1为高电平，CK2为低电平。此时第三晶体管T3被关断，电容C1将节点N1的电压维持为高电平，第五晶体管T5仍然关断。另一方面，第一晶体管T1导通，使节点N3的电平拉高，此时第四晶体管T4关断。节点N2的电压维持不变，仍为低电平。第八晶体管T8仍然导通，但是由于此时CK2为低电平，Eout拉低为低电平。另外，由于节点N2为低电平，CK2也为低电平，第六晶体管T6和第七晶体管T7导通，此时即使电容C1发生故障不能将节点N1的电平维持为高电平，节点N1仍会被VGH拉高，保证第九晶体管T9关断。第六晶体管T6和第七晶体管T7起到了锁定第九晶体管T9的作用。
至此，图2中的移位寄存器完成了对正逻辑信号的移位并输出正逻辑信号。
在第二阶段之后的第三阶段，STV为低电平，CK1为低电平，CK2为高电平。此时，第三晶体管T3导通，由于STV为低电平，节点N1的电压被 拉低，将第五晶体管T5、第九晶体管T9打开，节点N2的电压被拉高。第一晶体管T1、第四晶体管T4的状态维持不变。由于CK2为高电平，节点N2也为高电平，第六晶体管T6和第七晶体管T7均关断。第三阶段相当于完成了对各个节点的电压的复位。
另外，在第三阶段之后，可以停止在第五晶体管T5上施加高电平，由于电容C2的存在，节点N2仍可以被维持为高电平。保证第八晶体管T8的关断，使输出端Eout不会再次输出高电平。设置电容C2可以避免在完成正逻辑信号的输出后继续在第五晶体管的源极施加高电压，降低移位寄存器的功耗。当然在实际应用中，即使不设置电容C2，上述的移位寄存器仍可以完成对正逻辑信号的移位并输出正逻辑信号，本公开的实施方案不能理解为对本公开保护范围的限定。
设置第九晶体管T9的好处是：即使Eout端有漏电流存在，也会经第九晶体管T9流入低电压端，而不会在此输出高电平信号，这样就能很好的保证第二阶段之后不会输出高电平信号。但是在实际应用中，即使不设置这里的第九晶体管T9，由于节点N2在第二阶段之后维持为高电平，在不漏电的情况下，Eout端一般也不会有高电平信号输出。不设置第九晶体管T9，并不影响本公开的实施例的移位寄存器对正逻辑信号的移位并输出正逻辑信号，相应的技术方案也应该落入本公开的保护范围。
同时，需要指出的是，图2中的第六晶体管T6和第七晶体管T7也不是必须设置的结构。在电容C1能够正常将节点N1维持为高电平的情况下，在输出正逻辑信号的第二阶段，第九晶体管T9不会被导通，相应的也不会影响本公开的实施例的移位寄存器实现移位输出的功能。
需要指出的是，实际应用中，电容C2不与节点N2连接的一端也可以不连接VGH，相应地，电容C1不连接节点N1的一端也未必需要连接Eout，相应的方案也不会影响本公开的实施。
当第八晶体管T8的源极接入CK2时，对图2中的移位寄存器中的移位寄存器进行驱动的方法中的关键信号以及节点的电位图可以如图4所示。
在STV为高电平的第一阶段，CK1为低电平，CK2也为低电平。此时第三晶体管T3导通，节点N1的电平为高电平，导致第五晶体管T5、第九晶体管T9关断。第一晶体管T1也被关断，此时节点N3被拉低，为低电平， 进而导致第四晶体管T4开启，使得节点N2的电平为低电平。此时，第八晶体管T8导通，是由于CK2为低电平，Eout端输出低电平。
在第二阶段，CK1为高电平，CK2仍为低电平，此时节点N1和节点N2的电压维持不变，第八晶体管T8仍处于导通状态，由于CK2为低电平，Eout端仍输出低电平。
在第三阶段，CK1为高电平，CK2也为高电平，此时节点N1和节点N2的电压维持不变，第八晶体管T8处于导通状态。但是由于CK2为高电平，Eout端仍输出高电平。至此完成了正逻辑信号的移位输出。
在上述的移位寄存器工作的工作过程中，第三晶体管T3实现对正逻辑信号的输入控制，充当了输入开关单元。第八晶体管T8实现对正逻辑信号的输出控制，充当了输出开关单元。第一晶体管T1、第二晶体管T2、第四晶体管T4、第五晶体管T5共同对节点N1的电平进行反相并输出，构成反相单元。第九晶体管T9起到漏电保护开关的功能，充当了漏电保护开关单元。第六晶体管T6、第七晶体管T7则起到了锁定第九晶体管T9在的作用，充当了锁定开关单元。电容C1和电容C2起到了维持节点N1或N2电平的作用，构成电压维持单元。
本公开的实施例还提供了一种由多级的图2中的移位寄存器级联形成的移位扫描电路。该移位寄存器还包括多条的时钟信号线。参考图2，在该移位扫描电路中，各个移位寄存器的第三晶体管T3的栅极连接同一时钟信号线CK1，第六晶体管T6连接与CK1不同的时钟信号线CK2，第八晶体管T8的源极可连接CK1或CK2。本级移位寄存器中第八晶体管T8的漏极与下一级移位寄存器中第三晶体管T3的源极以及第一晶体管T1的栅极相连，向第三晶体管T3的源极和第一晶体管T1的栅极提供输入正逻辑信号。不难看出，如果不设置第六晶体管T6和第七晶体管T7，则该移位扫描电路可以仅包含一条时钟信号线。
图5为图1中的移位寄存器的再一种可选结构的结构示意图，与图2中的移位寄存器不同的是，在图5中使用一个电容C3代替第二晶体管T2连接在节点N3。其他结构和连接关系不变。
此时，在对图5中的移位寄存器进行驱动时，可以在第一晶体管T1的栅极施加CK2，并使其源极连接上一级移位寄存器的节点N2’。此时，施加 在图5中的移位寄存器上的关键信号以及关键节点的电位图可以如图6所示，其中CK1、CK2、节点N1、节点N2、Eout、STV的电位时序与图3一致。与图3中不同的是，由于上一级移位寄存器的节点N2’仅在第一阶段为低电平，第一阶段之后维持为高电平。则在第二阶段CK2为低电平时，可以引入N2’节点的电压对电容C3与节点N3相连的一端进行充电。这样后续过程中，无论在第一晶体管T1时是否导通，节点N3的电压都会维持为高电平(导通时，与N2’点等电位，同为高电平，不导通时，维持为高电平)。相比与图2中在第一阶段之后需要对第一晶体管T1的源极持续输出高电压维持节点N3为高电平的方式，能够进一步降低功耗。
本公开的实施例还提供了一种由多级的图5中的移位寄存器级联形成的移位扫描电路，该移位扫描电路还包括至少一条的时钟信号线。图7为第m级和第m+1级两级的移位寄存器级联的结构示意图，其中，各个移位寄存器的第一晶体管T1连接同一时钟信号线CK2，第三晶体管T3的栅极连接同一时钟信号线CK1，第六晶体管T6连接与CK1不同的时钟信号线CK2，第八晶体管T8的源极可连接CK1或CK2。第m级移位寄存器中第八晶体管T8的漏极与第m+1级移位寄存器中第三晶体管T3的源极相连，向该第三晶体管T3的源极输入正逻辑信号。第m级移位寄存器中的节点N2与第m+1级移位寄存器中的第一晶体管T1的源极相连。
本公开的实施例还提供了一种包括上述任一项所述的移位扫描电路的显示装置，该显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上实施方式仅用于说明本公开，而并非对本公开的限制，有关技术领域的普通技术人员，在不脱离本公开的精神和范围的情况下，还可以做出各种变化和变型，因此所有等同的技术方案也属于本公开的范畴，本公开的专利保护范围应由权利要求限定。
本申请要求于2014年12月10日递交的中国专利申请第201410759198.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (15)

  1. 一种移位寄存器，包括：输入开关单元、反相单元、输出开关单元、第一节点电压维持单元；其中，
    所述输入开关单元的输出端与第一节点相连，根据自身控制端施加的控制信号导通；
    所述第一节点电压维持单元的稳压端与所述第一节点相连，适于在所述输入开关单元导通时记录所述第一节点的电平，并在所述输入开关单元关断时将所述反相单元的输入端维持为所记录的电平；
    所述反相单元的输出端与第二节点相连，适于响应于自身控制端所接入的控制信号将所述第一节点的电平反相并输出到第二节点；
    所述输出开关单元的控制端与所述第二节点相连，根据所述第二节点的电平状态导通。
  2. 如权利要求1所述的移位寄存器，还包括：漏电保护开关单元，所述漏电保护开关单元的输入端与所述输出开关单元的输出端相连，控制端与所述第一节点相连，根据所述第一节点的电平状态导通。
  3. 如权利要求2所述的移位寄存器，还包括：
    第一锁定开关单元和第二锁定开关单元，所述第一锁定开关单元和第二锁定开关单元根据其控制端的电平状态导通；其中，
    所述第一锁定开关单元的输出端连接第二锁定开关单元的输入端，控制端连接第二节点；所述第二锁定开关单元的输出端连接第一节点。
  4. 如权利要求1所述的移位寄存器，还包括：
    第二节点电压维持单元，所述第二节点电压维持单元的稳压端与所述第二节点相连，适于在所述反相单元工作时记录所述第一节点的电平，并在所述反相单元停止工作时将所述第二节点维持为所记录的电平。
  5. 如权利要求1所述的移位寄存器，其中，所述反相单元包括：第一反相开关单元、第二反相开关单元、第三反相开关单元、第三节点电压维持单元；其中，各个反相开关单元均根据自身控制端的电平状态导通，所述反相单元的控制端为所述第一反相开关单元的控制端；
    所述第一反相开关单元的输出端以及第二反相开关单元的控制端与第三 节点相连，第二反相开关单元的输出端与所述第三反相开关单元的输入端以及第二节点相连；所述第三反相开关单元的输出端与第一节点相连；
    所述第三节点电压维持单元的稳压端与所述第三节点相连，适于在所述第一反相开关单元导通时记录所述第三节点的电平，并在所述第一反相开关单元关断时将所述第三节点维持为所记录的电平。
  6. 如权利要求1所述的移位寄存器，其中，所述反相单元包括：第一反相开关单元、第二反相开关单元、第三反相开关单元、第四反相开关单元；其中，各个反相开关单元均根据自身控制端的电平状态，所述反相单元的控制端为所述第一反相开关单元的控制端；
    所述第一反相开关单元的输出端以及第二反相开关单元的控制端、第四反相开关单元的输入端与第三节点相连，第二反相开关单元的输出端与所述第三反相开关单元的输入端以及第二节点相连；所述第三反相开关单元的输出端与第一节点相连。
  7. 如权利要求1-6任一项所述的移位寄存器，其中，各个开关单元均为P沟道型晶体管，稳压单元为电容。
  8. 一种移位扫描电路，包括：多个级联的如权利要求1-7任一项所述的移位寄存器。
  9. 如权利要求8所述的移位扫描电路，还包括：至少一条时钟信号线；其中，各个移位寄存中的输入开关单元的控制端连接同一时钟信号线，输出开关单元的输入端连接同一时钟信号线；且本级移位寄存器中输入开关单元的输入端与上一级移位寄存器中的输出端相连。
  10. 如权利要求9所述的移位扫描电路，其中，当各个移位寄存器为如权利要求5所述的移位寄存器时，各个移位寄存器中的第一反相开关单元的控制端连接同一时钟信号线，且该时钟信号线不同于输入开关单元的控制端所连接的时钟信号线。
  11. 如权利要求9所述的移位扫描电路，其中，当各个移位寄存器为如权利要求6所述的移位寄存器时，本级移位寄存器中的第一反相开关单元的控制端与上一级移位寄存器中的输出端相连，输入端连接上一级移位寄存器的第二节点。
  12. 如权利要求9所述的移位扫描电路，其中，当各个移位寄存器为如权 利要求3所述的移位寄存器时，各个移位寄存器中的第二锁定开关单元的控制端连接同一时钟信号线，且该时钟信号线不同于输入开关单元的控制端所连接的时钟信号线。
  13. 如权利要求9所述的移位扫描电路，其中，所述输出开关单元的输入端所连接的时钟信号线与输入开关单元的控制端所连接的时钟信号线为同一时钟信号线。
  14. 一种移位寄存器的驱动方法，用于驱动如权利要求1-7任一项所述的移位寄存器，该方法包括：
    在输入开关单元的控制端施加控制信号使输入开关单元在第一时钟周期导通，并在第二时钟周期关断；其中，第一时钟周期为向输入开关单元的输入端输入高电平信号的时钟周期；
    在反相单元的控制端施加控制信号使反相单元在第一时钟周期和第二时钟周期内对第一节点的电压进行反相并输出到第二节点；以及
    在第一时钟周期和第二时钟周期之中的一个时钟周期内，在输出开关单元的输入端施加高电平信号，在另一个时钟周期内施加低电平信号。
  15. 一种显示装置，包括如权利要求8-13任一项所述的移位扫描电路。
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