WO2021232871A1 - 栅极驱动电路、显示基板、显示装置和栅极驱动方法 - Google Patents

栅极驱动电路、显示基板、显示装置和栅极驱动方法 Download PDF

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Publication number
WO2021232871A1
WO2021232871A1 PCT/CN2021/077653 CN2021077653W WO2021232871A1 WO 2021232871 A1 WO2021232871 A1 WO 2021232871A1 CN 2021077653 W CN2021077653 W CN 2021077653W WO 2021232871 A1 WO2021232871 A1 WO 2021232871A1
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Prior art keywords
coupled
circuit
signal
transistor
control
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PCT/CN2021/077653
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English (en)
French (fr)
Inventor
商广良
董甜
殷新社
李梅
刘利宾
史世明
Original Assignee
京东方科技集团股份有限公司
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Priority to JP2021565081A priority Critical patent/JP2023526700A/ja
Priority to EP21772659.5A priority patent/EP3992960A4/en
Priority to CN202180000301.2A priority patent/CN114207704B/zh
Priority to US17/433,668 priority patent/US11875748B2/en
Publication of WO2021232871A1 publication Critical patent/WO2021232871A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • the present disclosure relates to the display field, and in particular to a gate driving circuit, a display substrate, a display device, and a gate driving method.
  • PWM dimming is generally used Specifically, a light-emitting control transistor is provided in the pixel circuit included in the pixel unit to control the driving current to flow through the organic light-emitting diode (Organic Light-Emitting Diode, referred to as OLED) time, so as to carry out the equivalent brightness of the pixel unit Precise control.
  • OLED Organic Light-Emitting Diode
  • the existing gate driving circuit can output a limited frequency of the PWM signal, and a lower frequency PWM signal will cause the organic light-emitting diode to appear flicker that can be recognized by the naked eye, resulting in poor display effect.
  • the present disclosure aims to solve at least one of the technical problems existing in the prior art, and proposes a gate driving circuit, a display substrate, a display device, and a gate driving method.
  • an embodiment of the present disclosure provides a gate drive circuit, including: a frequency multiplication control circuit and an effective output circuit, the effective output circuit includes: a plurality of cascaded first shift registers, the effective output
  • the first shift register in the first stage of the circuit is configured with a first signal input terminal and a second signal input terminal.
  • the first signal input terminal is coupled to the output control signal line, and the second signal input terminal is connected to the output control signal line.
  • the frequency multiplication control circuit is coupled, and the other first shift registers except the first shift register in the first stage in the effective output circuit are all equipped with a first cascade signal input terminal, and the other first shift registers
  • the first cascade signal input end of the register is coupled to the signal output end of the first shift register corresponding to the previous stage;
  • the frequency multiplier control circuit is coupled to the output control signal line, and is configured to respond to the control of the output control signal provided by the output control signal line, and after a preset period of time has elapsed since receiving the output control signal Providing a frequency multiplication control signal to the second signal input terminal;
  • the first shift register located in the first stage is configured to output a scan signal in response to the control of the output control signal, and to output a scan signal in response to the control of the frequency multiplication control signal.
  • the frequency multiplication control circuit includes: a plurality of cascaded second shift registers
  • the first shift register in the first stage of the frequency multiplication control circuit is equipped with a third signal input terminal, and the third signal input terminal is coupled to the output control signal line;
  • all the second shift registers except the second shift register in the first stage are equipped with a second cascade signal input terminal, and the second cascade signal of the other second shift registers The input terminal is coupled to the signal output terminal of the second shift register corresponding to the previous stage;
  • the signal output terminal of the second shift register at the last stage in the frequency multiplication control circuit is coupled to the second signal input terminal.
  • the second shift register includes: a signal writing circuit, a first control circuit, a second control circuit, and a signal output circuit;
  • the signal writing circuit, the first control circuit, the second control circuit, and the signal output circuit are coupled to a first node, and the first control circuit and the second control circuit are both Coupled to a second node, and both the second control circuit and the signal output circuit are coupled to a third node;
  • the signal writing circuit is coupled to the corresponding signal input terminal and the first clock signal terminal, and is configured to respond to the control of the first clock signal provided by the first clock signal terminal to provide the corresponding signal input terminal Write the signal of to the first node;
  • the first control circuit is coupled to the first power terminal and the first clock signal terminal, and is configured to write the first operating voltage provided by the first power terminal in response to the control of the first clock signal Input to the second node, and in response to the control of the voltage at the first node, writing the first clock signal to the second node;
  • the second control circuit is coupled to the second power terminal and the second clock signal terminal, and is configured to respond to the voltage at the second node and the second clock signal provided by the second clock signal terminal. Control, write the second clock signal to the third node, and in response to the control of the voltage at the first node, write the second operating voltage provided by the second power terminal to the first node
  • the signal output circuit is coupled to the first power terminal and the second power terminal, and is configured to write the first operating voltage to the signal output in response to the control of the voltage at the first node And write the second operating voltage to the signal output terminal in response to the control of the voltage at the third node.
  • the signal writing circuit includes: a first transistor, the first control circuit includes: a second transistor and a third transistor, and the second control circuit includes: a fourth transistor, a fifth transistor, A sixth transistor and a first capacitor, the signal output circuit includes: a seventh transistor, an eighth transistor, and a second capacitor;
  • the control electrode of the first transistor is coupled to the first clock signal terminal, the first electrode of the first transistor is coupled to the signal input terminal, and the second electrode of the first transistor is coupled to the first clock signal terminal.
  • the control electrode of the second transistor is coupled to the first node, the first electrode of the second transistor is coupled to the first clock signal terminal, and the second electrode of the second transistor is coupled to the first node.
  • the control electrode of the third transistor is coupled to the first clock signal terminal, the first electrode of the third transistor is coupled to the first power terminal, and the second electrode of the third transistor is coupled to the The second node is coupled;
  • the control electrode of the fourth transistor is coupled to the second node, the first electrode of the fourth transistor is coupled to the second clock signal terminal, and the second electrode of the fourth transistor is coupled to the second node.
  • the first pole of the five transistor is coupled;
  • the control electrode of the fifth transistor is coupled to the second clock signal terminal, and the second electrode of the fifth transistor is coupled to the third node;
  • the control electrode of the sixth transistor is coupled to the first node, the first electrode of the sixth transistor is coupled to the second power terminal, and the second electrode of the sixth transistor is coupled to the third node. Node coupling
  • a first end of the first capacitor is coupled to the second node, and a second end of the first capacitor is coupled to the second electrode of the fourth transistor;
  • the control electrode of the seventh transistor is coupled to the third node, the first electrode of the seventh transistor is coupled to the second power supply terminal, and the second electrode of the seventh transistor is coupled to the signal output terminal. End coupling
  • the control electrode of the eighth transistor is coupled to the first node, the first electrode of the eighth transistor is coupled to the first power supply terminal, and the second electrode of the eighth transistor is coupled to the signal output End coupling
  • the first terminal of the second capacitor is coupled to the third node, and the second terminal of the third capacitor is coupled to the second power terminal.
  • the second shift register further includes: a noise reduction circuit
  • the noise reduction circuit is coupled to the first node, the second node, the second power terminal, and the second clock signal terminal, and is configured to respond to the second clock signal and the second clock signal
  • the voltage at the second node is controlled, and noise reduction is performed on the voltage at the first node.
  • the noise reduction circuit includes: a ninth transistor, a tenth transistor, and a third capacitor;
  • the control electrode of the ninth transistor is coupled to the second node, the first electrode of the ninth transistor is coupled to the second power supply terminal, and the second electrode of the ninth transistor is coupled to the tenth node.
  • the first pole of the transistor is coupled;
  • the control electrode of the tenth transistor is coupled to the signal terminal of the second transistor, and the second electrode of the tenth transistor is coupled to the first node;
  • the first terminal of the third capacitor is coupled to the first node, and the second terminal of the third capacitor is coupled to the second clock signal terminal.
  • the first shift register in the effective output circuit has the same circuit structure as the second shift register in the frequency multiplication control circuit.
  • the first signal input terminal and the second signal input terminal of the first shift register in the first stage are the same signal input terminal.
  • the first signal input terminal and the second signal input terminal of the first shift register in the first stage are different signal input terminals
  • the first shift register in the first stage is configured with a second switch circuit and a third switch circuit
  • the second switch circuit is arranged between the signal writing circuit and the first signal input terminal, and is coupled to the second signal input terminal, and is configured to respond to the signal input from the second signal input terminal. Control of the provided signal to control the on-off between the signal writing circuit and the first signal input terminal;
  • the third switch circuit is arranged between the signal writing circuit and the second signal input terminal, is coupled to the first signal input terminal, and is configured to respond to the signal input terminal of the first signal input terminal.
  • the provided signal control is used to control the on-off between the signal writing circuit and the second signal input terminal.
  • the second switch circuit includes a twelfth transistor, and the third switch circuit includes a thirteenth transistor;
  • the control electrode of the twelfth transistor is coupled to the second signal input end, the first electrode of the twelfth transistor is coupled to the first signal input end, and the second electrode of the twelfth transistor is coupled to the first signal input end.
  • the pole is coupled to the signal writing circuit;
  • the control electrode of the thirteenth transistor is coupled to the first signal input end, the first electrode of the thirteenth transistor is coupled to the second signal input end, and the second electrode of the thirteenth transistor is coupled to the second signal input end.
  • the pole is coupled with the signal writing circuit.
  • the second shift register in the first stage is equipped with a first switch circuit, and the first switch circuit is arranged between the signal output circuit and the second shift register. Between the power supply terminals and coupled to the first switch control terminal, configured to control the signal output circuit and the second power terminal in response to the control of the first switch control signal provided by the first switch control terminal On and off between.
  • the first switch circuit includes: an eleventh transistor
  • the control electrode of the eleventh transistor is coupled to the first switch control terminal, the first electrode of the eleventh transistor is coupled to the second power terminal, and the second electrode of the eleventh transistor is coupled to the The signal output circuit is coupled.
  • the second shift register in the first stage is equipped with a first switch circuit, and the first switch circuit is arranged between the second control circuit and the first switch circuit. Between the two clock signal terminals, it is configured to control the on-off between the second control circuit and the second clock signal terminal in response to the control of the first switch control signal provided by the first switch control terminal.
  • the first switch circuit includes: an eleventh transistor
  • the control electrode of the eleventh transistor is coupled to the first switch control terminal, the first electrode of the eleventh transistor is coupled to the second clock signal terminal, and the second electrode of the eleventh transistor is coupled to the The second control circuit is coupled.
  • the second shift register located in the first stage is equipped with a first switch circuit, and the first switch circuit is provided between the signal writing circuit and the signal Between the input terminals and coupled to the first switch control terminal, configured to control the signal writing circuit and the signal input terminal in response to the control of the first switch control signal provided by the first switch control terminal On and off between.
  • the first switch circuit includes: an eleventh transistor
  • the control electrode of the eleventh transistor is coupled to the first switch control terminal, the first electrode of the eleventh transistor is coupled to the signal input terminal, and the second electrode of the eleventh transistor is coupled to the The signal writing circuit is coupled.
  • the second shift register located in the first stage is configured with a first power supply circuit
  • the first power supply circuit is coupled to the signal writing circuit, the first switch circuit, the first power supply terminal, and the second switch control terminal, and is configured to respond to all the signals provided by the second switch control terminal.
  • the control of the second switch control signal writes the first operating voltage to the signal writing circuit.
  • the first power supply circuit includes: a fourteenth transistor
  • the control electrode of the fourteenth transistor is coupled to the second switch control terminal, the first electrode of the fourteenth transistor is coupled to the first power terminal, and the second electrode of the fourteenth transistor is It is coupled to the signal writing circuit and the first switch circuit.
  • the second shift register located in the first stage is configured with a second power supply circuit
  • the second power supply circuit is coupled to the first power terminal, the signal output terminal of the second shift register located in the first stage, and the second switch control terminal, and is configured to respond to the second switch control terminal.
  • the provided control of the second switch control signal writes the first operating voltage to the signal output terminal of the second shift register.
  • the second power supply circuit includes: a fifteenth transistor
  • the control electrode of the fifteenth transistor is coupled to the second switch control terminal, the first electrode of the fifteenth transistor is coupled to the first power terminal, and the second electrode of the fifteenth transistor is It is coupled to the signal output terminal of the second shift register located in the first stage.
  • it further includes: an inverter circuit, the input terminal of the inverter circuit is coupled to the first switch control terminal, and the output terminal of the inverter circuit is coupled to the second switch control terminal .
  • embodiments of the present disclosure also provide a display substrate, including: the gate driving circuit provided in the first aspect and a plurality of gate lines located in the display area;
  • the gate line is coupled to a signal output terminal of a corresponding first shift register in the gate driving circuit.
  • an embodiment of the present disclosure also provides a display device, including: the display substrate provided in the first aspect and a counter substrate disposed opposite to the display substrate.
  • embodiments of the present disclosure also provide a gate driving method, based on the gate driving circuit provided in the first aspect, the gate driving method includes:
  • the shift registers of each stage in the effective output circuit sequentially output scanning signals.
  • the second signal input terminal of the shift register provides a frequency multiplication control signal
  • the shift registers of each stage in the effective output circuit sequentially output scanning signals.
  • FIG. 1 is a schematic diagram of a circuit structure of a gate driving circuit provided by an embodiment of the disclosure
  • FIG. 2a is a schematic diagram of the circuit structure of another gate driving circuit provided by an embodiment of the disclosure.
  • FIG. 2b is a working timing diagram of the gate driving circuit shown in FIG. 2a;
  • FIG. 3 is a schematic diagram of a circuit structure of a second shift register provided by an embodiment of the disclosure.
  • FIG. 4 is a schematic diagram of a circuit structure of the second shift register shown in FIG. 3;
  • FIG. 5 is a working timing diagram of the second shift register shown in FIG. 4;
  • FIG. 6a is a schematic diagram of a circuit structure of a second shift register located in the first stage in an embodiment of the disclosure
  • FIG. 6b is a schematic diagram of an optional circuit structure based on the second shift register in the first stage shown in FIG. 6a;
  • FIG. 7a is a schematic diagram of another circuit structure of the second shift register in the first stage in the embodiment of the disclosure.
  • FIG. 7b is a schematic diagram of an optional circuit structure based on the second shift register in the first stage shown in FIG. 7a;
  • FIG. 8 is a schematic diagram of another circuit structure of the second shift register located in the first stage in the embodiments of the disclosure.
  • FIG. 9 is a schematic diagram of still another circuit structure of the second shift register at the first stage in the embodiments of the present disclosure.
  • FIG. 10 is a schematic diagram of still another circuit structure of the second shift register at the first stage in the embodiments of the present disclosure.
  • FIG. 11 is a schematic diagram of still another circuit structure of the second shift register in the first stage in the embodiments of the disclosure.
  • FIG. 12a is a schematic diagram of a circuit structure of a first shift register at the first stage in an embodiment of the disclosure
  • FIG. 12b is a schematic diagram of an optional circuit structure based on the first shift register in the first stage shown in FIG. 12a;
  • FIG. 13 is a method flowchart of a gate driving method provided by an embodiment of the disclosure.
  • the gate drive circuit is equipped with an output control signal line (usually a frame start signal line, used to provide a frame start signal), and the output control signal line is connected to the first stage shifter in the gate drive circuit.
  • the bit register is coupled to control the shift register at the first stage to output scan signals, and the shift registers at other stages in the gate drive circuit output scan signals in turn.
  • the frequency of the scanning signal output by the shift registers of each stage in the gate driving circuit is equal to the frequency of the output control signal provided in the output control signal line.
  • the frequency of the output control signal provided by the output control signal is k
  • the frequency of the scan signal output by each level of shift register in the gate drive circuit involved in the related art is also k.
  • the frequency of the output control signal loaded in the output control signal line is limited, which results in the limited frequency of the scanning signal output by the shift registers of each level in the gate drive circuit.
  • the gate drive circuit involved in the related technology cannot Meet high frequency output requirements.
  • the technical solution of the present disclosure provides a gate driving circuit, a display substrate, a display device, and a gate driving method.
  • FIG. 1 is a schematic diagram of the circuit structure of a gate driving circuit provided by an embodiment of the disclosure.
  • the gate driving circuit includes: a frequency multiplication control circuit 1 and an effective output circuit 2;
  • Circuit 2 includes: a number of cascaded first shift registers A_1, A_2...A_n, where n is an integer;
  • the first shift register configuration A_1 in the first stage of the effective output circuit 2 has a first signal input terminal INPUT and The second signal input terminal INPUT', the first signal input terminal INPUT is coupled to the output control signal line, the second signal input terminal INPUT' is coupled to the frequency multiplication control circuit 1, and the effective output circuit 2 except for the first in the first stage
  • the other first shift registers A_2...A_n except one shift register are all equipped with a first cascade signal input terminal INPUT, and the first cascade signal input terminal INPUT of the other first shift registers corresponds to the previous stage.
  • the signal output terminal OUT of the first shift register is coupled.
  • the signal output terminal OUT of each first shift register A_1, A_2...A_n is coupled to a corresponding gate line GATE_1, GATE_2...GATE_n in the display area, and is used to provide scanning signals to the corresponding gate lines GATE_1, GATE_2...GATE_n .
  • the first signal input terminal INPUT and the first cascade signal input terminal INPUT are equivalent, and both are a signal input terminal of the first shift register.
  • the frequency multiplying control circuit 1 is coupled to the output control signal line, and is configured to respond to the control of the output control signal provided by the output control signal line STV, and to the second signal input terminal INPUT after a preset period of time after receiving the output control signal. 'Provide frequency multiplication control signal.
  • the first shift register A_1 located in the first stage is configured to output a scan signal in response to the control of the output control signal, and to output the scan signal in response to the control of the frequency multiplication control signal.
  • the first shift register of the other stage in response to the control of the shift register at the previous stage to output the scan signal, the first shift register itself outputs the scan signal.
  • the first shift register For the entire effective output circuit 2, after the first signal input terminal INPUT or the second signal input terminal INPUT' of the first shift register A_1 of the first stage receives a pulse, the first shift of each stage in the effective output circuit 2 Bit registers A_1, A_2...A_n will output scan signals in sequence.
  • the output control signal line STV may be a frame start signal line, or may be other signal lines set according to actual needs. In the embodiments of the present disclosure, the output control signal line STV is taken as an example of the frame start signal line for exemplary description.
  • two clock signal lines CLK and CLKB are configured to provide clock signals for the shift register in the gate drive circuit.
  • the working process of the gate determination circuit is as follows: In response to the output control signal, the shift registers of each stage in the output circuit 2 are effectively output The scanning signals are sequentially output, and each scanning signal contains 1 pulse; at the same time, the frequency multiplier control circuit 1 sends a preset time to the second shift register A_1 of the first shift register A_1 in the first stage of the effective output circuit 2
  • the signal input terminal INPUT' provides a frequency multiplication control signal, and the output control signal contains 1 pulse; in response to the frequency multiplication control signal, the first shift registers A_1, A_2...A_n of each level in the effective output circuit 2 sequentially output scanning signals, and Each scan signal contains 1 pulse.
  • the size of the "preset duration" can be designed according to actual needs. Taking a certain first shift register in the effective output circuit 2 as an example, the delay between two consecutive pulses output by the first shift register is a “preset duration”.
  • the gate drive circuit provided by the embodiments of the present disclosure can achieve frequency multiplication output, that is, the upper limit of the frequency of scanning output by the gate drive circuit is increased, and it can effectively prevent the OLED from appearing identifiable by the naked eye due to the low frequency of the PWM signal. Flashing.
  • the frequency multiplication control circuit 1 has a delay output function, and the specific circuit structure of the frequency multiplication control circuit 1 is not limited by the technical solution of the present disclosure.
  • the effective output circuit 2 in the embodiment of the present disclosure can be equivalent to the gate driving circuit in the related art, which can provide scanning signals to the gate lines in the display panel.
  • the circuit structure is not limited by the technical solution of the present disclosure.
  • Fig. 2a is a schematic diagram of the circuit structure of another gate driving circuit provided by an embodiment of the present disclosure.
  • Fig. 2b is a working timing diagram of the gate driving circuit shown in Fig. 2a; as shown in Fig. 2a and Fig. 2b, Fig. 2a
  • the gate driving circuit shown is a more specific alternative implementation based on the gate driving circuit shown in FIG.
  • the second shift register in the first stage of the frequency multiplication control circuit 1 is equipped with a third signal input terminal INPUT, and the third signal input terminal INPUT is coupled to the output control signal line STV;
  • the frequency multiplication control circuit 1 except for the second shift register B_1 in the first stage, the other second shift registers B_2...B_m are all equipped with the second cascade signal input terminal INPUT, and the other second shift registers B_2...B_m are second
  • the cascade signal input terminal INPUT is coupled to the signal output terminal OUT of the second shift register of the previous stage corresponding to each; the signal output terminal OUT of the second shift register B_m at the last stage in the frequency multiplication control circuit 1
  • the second signal input terminal INPUT' is coupled.
  • the frequency multiplying control circuit 1 is used as a dummy gate drive circuit.
  • Each of the second shift registers B_1, B_2...B_m in the gate drive circuit has a cascade relationship, but does not add to the display area.
  • the gate line provides the scan signal.
  • the frequency multiplication control circuit 1 is based on the signal transmission process of the second shift registers B_1, B_2...B_m cascaded in the gate drive circuit to achieve delayed output of the received output control signal (output as a frequency multiplication control signal) .
  • the number m of second shift registers included in the frequency multiplication control circuit 1 can be designed according to the “preset duration” and the time difference between the output pulse signals of the second shift registers of two adjacent stages.
  • the preset long time is T
  • the time when the second shift registers of two adjacent stages output pulse signals is t
  • the number of second shift registers included in the frequency multiplication control circuit 1 is T/t.
  • OUT(B_m) represents the signal output terminal of the second shift register B_m of the mth stage
  • OUT(A_n) represents the signal output terminal of the first shift register A_n of the nth stage.
  • the embodiment of the present disclosure does not limit the circuit structure of the second shift register, and the second shift register may adopt any existing shift register of any structure, and an exemplary description will be given below with reference to the accompanying drawings.
  • FIG. 3 is a schematic diagram of the circuit structure of a second shift register provided by an embodiment of the disclosure.
  • the second shift register includes: a signal writing circuit 101, a first control circuit 102, and a second control circuit.
  • the circuit 103 and the signal output circuit 104; the signal writing circuit 101, the first control circuit 102, the second control circuit 103 and the signal output circuit 104 are coupled to the first node N1, the first control circuit 102 and the second control circuit Both 103 are coupled to the second node N2, and both the second control circuit 103 and the signal output circuit 104 are coupled to the third node N3.
  • the signal writing circuit 101 is coupled to the corresponding signal input terminal INPUT and the first clock signal terminal CK, and is configured to respond to the control of the first clock signal provided by the first clock signal terminal CK to place the corresponding signal input terminal The provided signal is written to the first node N1.
  • the first control circuit 102 is coupled to the first power terminal and the first clock signal terminal CK, and is configured to write the first operating voltage provided by the first power terminal to the second node N2 in response to the control of the first clock signal, And in response to the control of the voltage at the first node N1, the first clock signal is written to the second node N2.
  • the second control circuit 103 is coupled to the second power terminal and the second clock signal terminal CKB, and is configured to respond to the control of the voltage at the second node N2 and the second clock signal provided by the second clock signal terminal CKB to control the second
  • the clock signal is written to the third node N3, and in response to the control of the voltage at the first node N1, the second operating voltage provided by the second power terminal is written to the third node N3.
  • the signal output circuit 104 is coupled to the first power terminal and the second power terminal, and is configured to write the first operating voltage to the signal output terminal OUT in response to the control of the voltage at the first node N1, and in response to the third node N3 The voltage control writes the second operating voltage to the signal output terminal OUT.
  • the second shift register further includes: a noise reduction circuit; the noise reduction circuit is coupled to the first node N1, the second node N2, the second power terminal, and the second clock signal terminal CKB, and is configured to respond to The second clock signal and the control of the voltage at the second node N2 perform noise reduction processing on the voltage at the first node N1.
  • Fig. 4 is a schematic diagram of a circuit structure of the second shift register shown in Fig. 3, as shown in Fig. 4, the second shift register shown in Fig. 4 is an optional based on the second shift register shown in Fig. 3 implementation plan.
  • the signal writing circuit 101 includes: a first transistor M1, the first control circuit 102 includes: a second transistor M2 and a third transistor M3, and the second control circuit 103 includes: a fourth transistor M4, a fifth transistor M5, a sixth transistor M6 and a first capacitor C1, the signal output circuit 104 includes: a seventh transistor M7, an eighth transistor M8, and a second capacitor C2.
  • the control electrode of the first transistor M1 is coupled to the first clock signal terminal CK, the first electrode of the first transistor M1 is coupled to the signal input terminal INPUT, and the second electrode of the first transistor M1 is coupled to the first node N1.
  • the control electrode of the second transistor M2 is coupled to the first node N1, the first electrode of the second transistor M2 is coupled to the first clock signal terminal CK, and the second electrode of the second transistor M2 is coupled to the second node N2.
  • the control electrode of the third transistor M3 is coupled to the first clock signal terminal CK, the first electrode of the third transistor M3 is coupled to the first power terminal, and the second electrode of the third transistor M3 is coupled to the second node N2.
  • the control electrode of the fourth transistor M4 is coupled to the second node N2, the first electrode of the fourth transistor M4 is coupled to the second clock signal terminal CKB, and the second electrode of the fourth transistor M4 is coupled to the first electrode of the fifth transistor M5. Coupling.
  • the control electrode of the fifth transistor M5 is coupled to the second clock signal terminal CKB, and the second electrode of the fifth transistor M5 is coupled to the third node N3.
  • the control electrode of the sixth transistor M6 is coupled to the first node N1, the first electrode of the sixth transistor M6 is coupled to the second power supply terminal, and the second electrode of the sixth transistor M6 is coupled to the third node N3.
  • the first terminal of the first capacitor C1 is coupled to the second node N2, and the second terminal of the first capacitor C1 is coupled to the second electrode of the fourth transistor M4.
  • the control electrode of the seventh transistor M7 is coupled to the third node N3, the first electrode of the seventh transistor M7 is coupled to the second power terminal, and the second electrode of the seventh transistor M7 is coupled to the signal output terminal OUT.
  • the control electrode of the eighth transistor M8 is coupled to the first node N1, the first electrode of the eighth transistor M8 is coupled to the first power terminal, and the second electrode of the eighth transistor M8 is coupled to the signal output terminal OUT.
  • the first terminal of the second capacitor C2 is coupled to the third node, and the second terminal of the second capacitor C2 is coupled to the first power terminal.
  • the noise reduction circuit includes: a ninth transistor M9, a tenth transistor M10, and a third capacitor C3.
  • the control electrode of the ninth transistor M9 is coupled to the second node N2, the first electrode of the ninth transistor M9 is coupled to the second power terminal, and the second electrode of the ninth transistor M9 is coupled to the first electrode of the tenth transistor M10 .
  • the control electrode of the tenth transistor M10 is coupled to the signal terminal of the second transistor M2, and the second electrode of the tenth transistor M10 is coupled to the first node N1.
  • the first terminal of the third capacitor C3 is coupled to the first node N1, and the second terminal of the third capacitor C3 is coupled to the second clock signal terminal CKB.
  • the involved transistors can be independently selected from one of polysilicon thin film transistors, amorphous silicon thin film transistors, oxide thin film transistors, and organic thin film transistors.
  • the “control electrode” involved in the embodiments of the present disclosure specifically refers to the gate of the transistor, the “first pole” specifically refers to the source of the transistor, and the corresponding “second pole” specifically refers to the drain of the transistor.
  • first pole specifically refers to the source of the transistor
  • second pole specifically refers to the drain of the transistor.
  • transistors can be divided into N-type transistors and P-type transistors. Each transistor in the present disclosure can be independently selected from N-type transistors or P-type transistors. In the following embodiments, all transistors in the pixel unit are P-type transistors. The transistors are taken as an example to illustrate. At this time, the transistors in the second shift register can be manufactured at the same time using the same manufacturing process. Correspondingly, the first working voltage provided by the first power terminal is a low-level voltage VGL, and the second working voltage provided by the second power terminal is a high-level voltage VGH. The working process of the second shift register shown in FIG. 4 will be described in detail below with reference to the accompanying drawings.
  • FIG. 5 is a working timing diagram of the second shift register shown in FIG. 4. As shown in FIG. 5, the working process of the second shift register includes the following stages:
  • the first clock signal provided by the first clock signal terminal CK is in a low level state
  • the second clock signal provided by the second clock signal terminal CKB is in a high level state
  • the signal provided by the third signal input terminal INPUT In a high state.
  • the first transistor M1, the third transistor M3, the fourth transistor M4, and the ninth transistor M9 are in a conducting state
  • the second transistor M2, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor are in a conducting state.
  • M8 and the tenth transistor M10 are in an off state.
  • the first transistor M1 and the third transistor M3 are both turned on, and the third signal input terminal INPUT provides a signal in a high-level state to be written to through the first transistor M1.
  • the first operating voltage VGL is written to the second node N2 through the third transistor M3, the first node N1 is in a high level state, and the second node N2 is in a low level state.
  • the sixth transistor M6 and the eighth transistor M8 are turned off. Since the second node N2 is in a low-level state, the fourth transistor M4 and the ninth transistor M9 are in a conductive state, and the second clock signal in a high-level state is written to the fourth node N4 through the fourth transistor M4. The second working voltage VGH is written to the fifth node N5 through the ninth transistor M9. At this time, the first terminal of the first capacitor C1 is in a low level state, and the second terminal of the first capacitor C1 is in a high level state.
  • the fifth transistor M5 and the tenth transistor M10 are turned off. Since the fifth transistor M5 and the sixth transistor M6 are both turned off, the third node N3 is in a floating state, the voltage at the third node N3 maintains the previous high level state, and the seventh transistor M7 is turned off.
  • the signal output terminal OUT is in a floating state, and the voltage at the signal output terminal OUT maintains the previous low level state.
  • the first clock signal provided by the first clock signal terminal CK is in a high level state
  • the second clock signal provided by the second clock signal terminal CKB is in a low level state
  • the signal provided by the third signal input terminal INPUT In a low state.
  • the fourth transistor M4, the fifth transistor M5, the seventh transistor M7, the ninth transistor M9, and the tenth transistor M10 are in a conducting state
  • the first transistor M1, the second transistor M2, the third transistor M3, and the sixth transistor M6 and the eighth transistor M8 are in an off state.
  • the first clock signal is in a high-level state
  • both the first transistor M1 and the third transistor M3 are turned off.
  • the second clock signal is in a low level state
  • the fifth transistor M5 and the tenth transistor M10 are turned on.
  • the second operating voltage VGH is written to the first node N1 through the ninth transistor M9 and the tenth transistor M10 to Maintaining the first node N1 in a high level state implements noise reduction processing on the first node N1, and the second transistor M2 and the eighth transistor M8 are maintained in an off state.
  • the first terminal of the third capacitor C3 is in a high level state
  • the second terminal of the third capacitor C3 is in a low level state.
  • the voltage at the fourth node N4 changes from the high level state to the low level state, due to the first capacitor
  • the first terminal of C1 is in a floating state, and under the bootstrap action of the first capacitor C1, the voltage at the second node N2 is pulled down to a lower state level.
  • the fifth transistor M5 Since the fifth transistor M5 is turned on, the second clock signal in the low state is written to the third node N3 through the fourth transistor M4 and the fifth transistor M5, the third node N3 is in the low state, and the seventh transistor M7 is turned on, the second working voltage VGH is written to the signal output terminal OUT through the seventh transistor M7, and the signal output terminal OUT outputs a high-level signal.
  • the first clock signal provided by the first clock signal terminal CK is in a low level state
  • the second clock signal provided by the second clock signal terminal CKB is in a high level state
  • the signal provided by the third signal input terminal INPUT In a low state.
  • the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the sixth transistor M6, the eighth transistor M8, and the ninth transistor M9 are in the conducting state
  • the fifth transistor M5 and the seventh transistor M7 and the tenth transistor M10 are in an off state.
  • the first transistor M1 and the third transistor M3 are both turned on, and the third signal input terminal INPUT provides a low-level signal to be written to through the first transistor M1.
  • the first operating voltage VGL is written to the second node N2 through the third transistor M3, the first node N1 is in a low level state, and the second node N2 is in a low level state.
  • the first terminal of the third capacitor C3 is in a low level state, and the second terminal of the third capacitor C3 is in a high level state.
  • the sixth transistor M6 and the eighth transistor M8 are turned on. Since the second node N2 is in a low-level state, the fourth transistor M4 and the ninth transistor M9 are in a conductive state, and the second clock signal in a high-level state is written to the fourth node N4 through the fourth transistor M4. The second working voltage VGH is written to the fifth node N5 through the ninth transistor M9. At this time, the first terminal of the first capacitor C1 is in a low level state, and the second terminal of the first capacitor C1 is in a high level state.
  • the fifth transistor M5 and the tenth transistor M10 are turned off. Since the fifth transistor M5 and the sixth transistor M6 are both turned off; the second operating voltage VGH is written to the third node N3 through the sixth transistor M6, and the third node N3 is in a high level state.
  • the seventh transistor M7 is turned off, the eighth transistor M8 is turned on, and the first operating voltage VGL is written to the signal output through the eighth transistor M8
  • the signal output terminal OUT outputs a low-level signal.
  • the first clock signal provided by the first clock signal terminal CK is in a high level state
  • the second clock signal provided by the second clock signal terminal CKB is in a low level state
  • the signal provided by the third signal input terminal INPUT In a low state.
  • the second transistor M2, the fifth transistor M5, the sixth transistor M6, the eighth transistor M8, and the tenth transistor M10 are in a conducting state
  • the first transistor M1, the third transistor M3, the fourth transistor M4, and the seventh transistor M7 and the ninth transistor M9 are in an off state.
  • both the first transistor M1 and the third transistor M3 are turned off. Since the first transistor M1 is turned off, the first node N1 is in a floating state; and because the second clock signal is switched from a high level state to a low level state, under the bootstrap action of the third capacitor C3, the first node N1 The voltage is pulled down to a lower state to perform noise reduction processing on the first node N1. At this time, the second transistor M2, the sixth transistor M6, and the eighth transistor M8 are all turned on. The second operating voltage VGH is written to the third node N3 through the sixth transistor M6.
  • the first clock signal in the high-level state is written to the second node N2 through the second transistor M2, the second node N2 is in the high-level state, and the fourth transistor M4 is turned off.
  • the fifth transistor M5 and the tenth transistor M10 are in a conductive state.
  • the voltage at the fourth node N4 is equal to the voltage at the third node N3
  • the voltage at the fifth node N5 is The voltage is equal to the voltage at the first node N1, that is, the voltage at the fourth node N4 is in a high-level state, and the voltage at the fifth node N5 is in a low-level state.
  • the seventh transistor M7 is turned off, the eighth transistor M8 is turned on, and the first operating voltage VGL is written to the signal output through the eighth transistor M8
  • the signal output terminal OUT outputs a low-level signal.
  • the first clock signal provided by the first clock signal terminal CK is in a low level state
  • the second clock signal provided by the second clock signal terminal CKB is in a high level state
  • the signal provided by the third signal input terminal INPUT In a low state.
  • the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the sixth transistor M6, the eighth transistor M8, and the ninth transistor M9 are in a conducting state
  • the fifth transistor M5 and the seventh transistor M7 and the tenth transistor M10 are in an off state.
  • the first transistor M1 and the third transistor M3 are both turned on, and the third signal input terminal INPUT provides a low-level signal to be written to through the first transistor M1.
  • the first operating voltage VGL is written to the second node N2 through the third transistor M3, the first node N1 is in a low level state, and the second node N2 is in a low level state.
  • the first terminal of the third capacitor C3 is in a low level state, and the second terminal of the third capacitor C3 is in a high level state.
  • the sixth transistor M6 and the eighth transistor M8 are turned on. Since the second node N2 is in a low-level state, the fourth transistor M4 and the ninth transistor M9 are in a conductive state, and the second clock signal in a high-level state is written to the fourth node N4 through the fourth transistor M4. The second working voltage VGH is written to the fifth node N5 through the ninth transistor M9. At this time, the first terminal of the first capacitor C1 is in a low level state, and the second terminal of the first capacitor C1 is in a high level state.
  • the fifth transistor M5 and the tenth transistor M10 are turned off. Since the fifth transistor M5 and the sixth transistor M6 are both turned off; the second operating voltage VGH is written to the third node N3 through the sixth transistor M6, and the third node N3 is in a high level state.
  • the seventh transistor M7 is turned off, the eighth transistor M8 is turned on, and the first operating voltage VGL is written to the signal output through the eighth transistor M8
  • the signal output terminal OUT outputs a low-level signal.
  • the fourth stage t4 and the fifth stage t5 are alternately executed, and the signal output terminal OUT maintains a low level signal until the signal provided by the third signal input terminal INPUT is in a high level state, and the second shift register works in the next cycle The first stage t1.
  • circuit structure of the second shift register shown in FIG. 4 only serves as an example, and it does not limit the technical solutions of the present disclosure.
  • the second shift register in the present disclosure may also have other Circuit structure, no more examples here.
  • the first shift register in the effective output circuit 2 has the same circuit structure as the second shift register in the frequency multiplying control circuit 1.
  • the circuit structure design of the entire gate drive circuit can be simplified. .
  • the first clock signal terminal CK of the first/second shift register located in the odd-numbered stage is coupled to the clock signal line CLK
  • the second clock signal terminal CKB of the first/second shift register located in the even-numbered stage It is coupled to the clock signal line CLKB.
  • FIG. 6a is a schematic diagram of a circuit structure of the second shift register in the first stage in the embodiment of the present disclosure. As shown in FIG. 6a, the second shift register shown in FIG. 6a is based on the second shift register shown in FIG. 3 An improvement of the register.
  • the second shift register B_1 located in the first stage is equipped with a first switch circuit 106 ;
  • the first switch circuit 106 is located between the signal output circuit 104 and the second power terminal in the second shift register of the first stage, and the first switch circuit 106 is used to control the signal output circuit 104 and the second power terminal between The on-off.
  • the signal output circuit 104 in the second shift register of the first stage is connected to the second power supply terminal, and the second shift register of the first stage is The register can work normally, the "frequency multiplication function" of the gate drive circuit is turned on; when the first switch circuit 106 is in the off state, the signal output circuit 104 and the second power supply located in the second shift register B_1 of the first stage There is a circuit break between the terminals, the second shift register B_1 in the first stage may not work normally, and the "frequency multiplication function" of the gate drive circuit is turned off.
  • Fig. 6b is a schematic diagram of an optional circuit structure based on the second shift register in the first stage shown in Fig. 6a, as shown in Fig. 6b, the signal writing circuit 101, the first control circuit 102, and the second
  • the specific circuits of the control circuit 103 and the signal output circuit 104 may be those shown in FIG. 4.
  • the signal writing circuit 101, the first control circuit 102, the second control circuit 103, and the signal output circuit 104 can also use other Circuit structure, not one by one here.
  • FIG. 7a is a schematic diagram of another circuit structure of the second shift register in the first stage in the embodiment of the disclosure. As shown in FIG. 7a, the difference from the situation shown in FIG. 6a is that the first switch circuit in FIG. 7a 106 is arranged between the second control circuit 103 and the second clock signal terminal CKB in the second shift register B_1 of the first stage, and the first switch circuit 106 is used to control the second control circuit 103 and the second clock signal terminal CKB Between on and off.
  • the second control circuit 103 located in the second shift register B_1 of the first stage conducts with the second clock signal terminal, and the second control circuit 103 located in the first stage is connected to the second clock signal terminal.
  • the second shift register B_1 can work normally, the "frequency multiplication function" of the gate drive circuit is turned on; when the first switch circuit 106 is in the off state, the second control circuit located in the second shift register B_1 of the first stage There is an open circuit between 103 and the second clock signal terminal, the second shift register B_1 in the first stage may not work normally, and the "frequency multiplication function" of the gate drive circuit is turned off.
  • Figure 7b is a schematic diagram of an alternative circuit structure based on the second shift register in the first stage shown in Figure 7a. As shown in Figure 7b, the signal writing circuit 101, the first control circuit 102, and the second The specific circuits of the control circuit 103 and the signal output circuit 104 may be those shown in FIG. 4.
  • the signal writing circuit 101, the first control circuit 102, the second control circuit 103, and the signal output circuit 104 may also use other Circuit structure, not one by one here.
  • the first switch circuit 106 includes: an eleventh transistor M11. Wherein, when the first switch circuit 106 is arranged between the signal output circuit 104 and the second power terminal, the control electrode of the eleventh transistor M11 is coupled to the switch control terminal SC, and the first electrode of the eleventh transistor M11 is coupled to the second power terminal SC.
  • the two power terminals are coupled, and the second pole of the eleventh transistor M11 is coupled to the signal output circuit 104; when the first switch circuit 106 is disposed between the second control circuit 103 and the second clock signal terminal CKB, the eleventh The control electrode of the transistor M11 is coupled to the switch control terminal SC, the first electrode of the eleventh transistor M11 is coupled to the second clock signal terminal CKB, and the second electrode of the eleventh transistor M11 is coupled to the second control circuit 103.
  • FIG. 7b only illustrates the case where the first switch circuit 106 (the eleventh transistor M11) is arranged between the second clock signal terminal and the first pole of the fourth transistor M4.
  • the first switch The circuit 106 (the eleventh transistor M11) may also be arranged between the second clock signal terminal and the control electrode of the fifth transistor M5.
  • FIG. 8 is a schematic diagram of another circuit structure of the second shift register in the first stage in the embodiment of the disclosure. As shown in FIG. 8, it is different from the situation shown in FIG. 6a to FIG. 7b.
  • the first switch circuit 106 is arranged between the signal writing circuit 101 and the signal input terminal INPUT.
  • the first switch circuit 106 is configured to control the signal writing in response to the control of the first switch control signal provided by the first switch control terminal SC.
  • the signal writing circuit 101 located in the second shift register B_1 of the first stage is connected to the signal input terminal INPUT, and the signal input terminal INPUT is located in the second stage of the first stage.
  • the shift register B_1 can work normally, the "frequency multiplication function" of the gate drive circuit is turned on; when the first switch circuit 106 is in the off state, the signal writing circuit 101 in the second shift register B_1 of the first stage It is disconnected from the signal input terminal INPUT, the second shift register B_1 in the first stage may not work normally, and the "frequency multiplication function" of the gate drive circuit is turned off.
  • the first switch circuit 106 includes: an eleventh transistor M11, a control electrode of the eleventh transistor M11 is coupled to the first switch control terminal SC, and a first electrode of the eleventh transistor M11 is coupled to the signal input terminal. INPUT is coupled, and the second electrode of the eleventh transistor M11 is coupled to the signal writing circuit 101.
  • the end N6 of the signal writing circuit 101 for coupling with the signal input terminal INPUT When a circuit breaks between the signal writing circuit 101 and the signal input terminal INPUT, the end N6 of the signal writing circuit 101 for coupling with the signal input terminal INPUT will be in a floating state (floating) and will be susceptible to external interference. The voltage is shifted. When the voltage at the end N6 of the signal writing circuit 101 for coupling with the signal input terminal INPUT shifts to a high level state, it will cause the second shift register in the first stage to produce a false output , The second shift register of the following stages will also produce false output, which will cause the "frequency multiplication function" of the gate drive circuit to be turned on abnormally.
  • FIG. 9 is a schematic diagram of another circuit structure of the second shift register located in the first stage in the embodiment of the disclosure. It is different from the situation shown in FIG. 8. In the situation shown in FIG. 9, it is located in the first stage in the frequency multiplication control circuit.
  • the second shift register is configured with a first power supply circuit 107, the first power supply circuit 107 is coupled to the signal writing circuit 101, the first switch circuit 106, the first power supply terminal and the second switch control terminal SCB, the first power supply circuit 107 is configured to write the first operating voltage to the signal writing circuit 101 in response to the control of the second switch control signal provided by the second switch control terminal SCB.
  • the second switch control signal can be used to control the first power supply circuit 107 to operate. Specifically, the first power supply circuit 107 writes the first operating voltage to the terminal N6 of the signal writing circuit 101 for coupling with the signal input terminal INPUT to maintain a stable voltage at this terminal, thereby preventing the gate drive circuit from malfunctioning. "Frequency multiplier function" is turned on abnormally.
  • the first power supply circuit 107 includes: a fourteenth transistor M14, a control electrode of the fourteenth transistor M14 is coupled to the second switch control terminal SCB, and a fourth transistor M14 of the fourteenth transistor M14 One pole is coupled to the first power terminal, and the second pole of the fourteenth transistor M14 is coupled to the signal writing circuit 101 and the first switch circuit 106.
  • the specific circuits of the signal writing circuit 101, the first control circuit 102, the second control circuit 103, and the signal output circuit 104 in FIGS. 8 and 9 can be those shown in FIG. 4.
  • FIG. 10 is a schematic diagram of the circuit structure of another second shift register provided by an embodiment of the disclosure.
  • the bit register is configured with a first switch circuit 106 and a second power supply circuit 109.
  • first switch circuit please refer to the content in the previous embodiment (in FIG. 10, only the first switch circuit 106 adopts the situation shown in FIG. 9 is shown by way of example), which will not be repeated here;
  • the second power supply circuit is described in detail.
  • the second power supply circuit 109 is coupled to the first power supply terminal, the signal output terminal OUT of the second shift register B_1 in the first stage, and the second switch control terminal SCB, and the second power supply circuit 109 is configured to respond to the second The control of the second switch control signal provided by the switch control terminal SCB writes the first operating voltage to the signal output terminal OUT of the second shift register B_1 located in the first stage.
  • the first switch circuit 106 makes a circuit break between the signal output circuit and the second power terminal (the first switch circuit 106 shown in FIG. 6a is provided between the signal output circuit and the second power terminal), or makes the second control circuit 103 and the second clock signal terminal are disconnected (the first switch circuit 106 shown in FIG. 7a is provided between the second control circuit 103 and the second clock signal terminal CKB), or the signal writing circuit 101 is connected to the signal input terminal INPUT When the circuit is disconnected (the first switch circuit 106 shown in FIG.
  • the second switch control signal can be used to control the second power supply circuit 109 to shift to the connected second
  • the signal output terminal OUT of the register is written with the first working voltage to perform noise reduction processing on the signal output terminal OUT of the second shift register B_1 located in the first stage, so as to avoid the abnormal "frequency multiplication function" of the gate drive circuit Turn on.
  • the second power supply circuit 109 includes: a fifteenth transistor M15; a control electrode of the fifteenth transistor M15 is coupled to the second switch control terminal SCB, and a first electrode of the fifteenth transistor M15 is connected to the first power supply The second electrode of the fifteenth transistor M15 is coupled to the signal output terminal OUT of the second shift register B_1 in the first stage.
  • FIG. 11 is a schematic diagram of another circuit structure of the second shift register located in the first stage in the embodiment of the disclosure. As shown in FIG. 11, it is different from the situation shown in FIG. 9 and FIG.
  • the second shift register B_1 of the first stage is configured with a first power supply circuit 107 (including a fourteenth transistor M14) and a second power supply circuit 109 (including a fifteenth transistor M15) at the same time.
  • the gate driving circuit further includes: an inverter circuit 108.
  • the input terminal of the inverter circuit 108 is coupled to the first switch control terminal SC, and the output terminal of the inverter circuit 108 is coupled to the second switch control terminal SCB.
  • the inverter circuit 108 is configured to perform inversion processing on the signal at the input terminal.
  • the inverter circuit 108 can perform inversion processing on the first switch control signal provided by the first switch control terminal SC, so as to obtain the second switch control signal. At this time, for the two different switch control terminals SC and SCB, only one switch control signal needs to be provided by the external chip.
  • the first signal input terminal INPUT and the second signal input terminal INPUT' of the first shift register A_1 located in the first stage are the same signal input terminal, that is, located in the first stage
  • the first shift register A_1 of A_1 is configured with a signal input terminal, which is simultaneously coupled to the output control signal terminal and the signal output terminal OUT of the frequency multiplication control circuit 1 for outputting the frequency multiplication control signal.
  • FIG. 12a is a schematic diagram of a circuit structure of the first shift register located in the first stage in the embodiments of the disclosure.
  • the first shift register A_1 located in the first stage A signal input terminal INPUT and a second signal input terminal INPUT′ are different signal input terminals;
  • the first shift register A_1 in the first stage further includes: a second switch circuit 110 and a third switch circuit 111.
  • the second switch circuit 110 is arranged between the signal writing circuit 101 in the first shift register of the first stage and the first signal input terminal INPUT, and is coupled to the second signal input terminal INPUT', and the second switch The circuit 110 is configured to control the on/off between the signal writing circuit 101 and the first signal input terminal INPUT in response to the control of the signal provided by the second signal input terminal INPUT′.
  • the third switch circuit 111 is arranged between the signal writing circuit 101 and the second signal input terminal INPUT' in the first shift register A_1 in the first stage, and is coupled to the first signal input terminal INPUT.
  • the third switch circuit 111 is configured to control the on/off between the signal writing circuit 101 and the second signal input terminal INPUT′ in response to the control of the signal provided by the first signal input terminal INPUT.
  • the second switch circuit 110 includes a twelfth transistor M12
  • the third switch circuit 111 includes a thirteenth transistor M14.
  • the control electrode of the twelfth transistor M12 is coupled to the second signal input terminal INPUT'
  • the first electrode of the twelfth transistor M12 is coupled to the first signal input terminal INPUT
  • the second electrode of the twelfth transistor M12 is coupled to The signal writing circuit 101 is coupled
  • the control electrode of the thirteenth transistor M14 is coupled to the first signal input terminal INPUT
  • the first electrode of the thirteenth transistor M14 is coupled to the second signal input terminal INPUT'
  • the thirteenth transistor The second pole of M14 is coupled to the signal writing circuit 101.
  • Fig. 12b is a schematic diagram of an optional circuit structure based on the first shift register in the first stage shown in Fig. 12a, as shown in Fig. 12b, the signal writing circuit 101, the first control circuit 102, and the second control circuit 102 of Fig. 12b
  • the specific circuits of the control circuit 103 and the signal output circuit 104 may be those shown in FIG. 4.
  • the signal writing circuit 101, the first control circuit 102, the second control circuit 103, and the signal output circuit 104 may also use other Circuit structure, not one by one here.
  • the embodiments of the present disclosure also provide a display substrate, which includes the gate drive circuit provided in the above embodiment and a plurality of gate lines located in the display area; the gate line corresponds to a first shift in the gate drive circuit.
  • the signal output terminal of the bit register is coupled.
  • the embodiments of the present disclosure also provide a display device, including the display substrate provided by the above-mentioned embodiments and a counter substrate disposed opposite to the display substrate.
  • a display substrate provided by the above-mentioned embodiments and a counter substrate disposed opposite to the display substrate.
  • the display substrate For a specific description of the display substrate, please refer to the content in the previous embodiments. Go into details again.
  • the display device can be any product or component with display function, such as electronic paper, liquid crystal display panel, LED panel, OLED panel, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, etc.
  • display function such as electronic paper, liquid crystal display panel, LED panel, OLED panel, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, etc.
  • FIG. 13 is a method flowchart of a gate driving method provided by an embodiment of the present disclosure. As shown in FIG. 13, the gate driving method is based on the gate driving circuit provided in the foregoing embodiment, and the gate driving method includes:
  • Step S1 In response to the output control signal, the shift registers of each stage in the effective output circuit sequentially output scanning signals.
  • the second signal input terminal provides a frequency multiplication control signal.
  • Step S2 In response to the frequency multiplication control signal, the shift registers of each stage in the effective output circuit sequentially output scanning signals.
  • step S1 and step S2 please refer to the corresponding content in the previous embodiment, which will not be repeated here.
  • a frequency multiplication control circuit is provided on the basis of the effective output circuit.
  • the frequency multiplication control circuit can provide a frequency multiplication control signal to the second signal input terminal after a preset period of time after receiving the output control signal, so as to make the effective
  • the output circuit can realize the frequency multiplication output, that is, the upper limit of the frequency of the scan output by the gate drive circuit is increased, and it can effectively prevent the OLED from flickering that can be recognized by the naked eye due to the low frequency of the PWM signal.

Abstract

一种栅极驱动电路，包括：倍频控制电路（1）和有效输出电路（2），有效输出电路（2）包括：若干个级联的第一移位寄存器，有效输出电路（2）中位于第一级的第一移位寄存器（A_1）配置有第一信号输入端（INPUT）和第二信号输入端（INPUT'），第一信号输入端（INPUT）与输出控制信号线（STV）耦接，第二信号输入端（INPUT'）与倍频控制电路（1）耦接；倍频控制电路（1）与输出控制信号线（STV）耦接，配置为响应于输出控制信号线（STV）所提供的输出控制信号的控制，从接收到输出控制信号开始经过预设时长后向第二信号输入端（INPUT'）提供倍频控制信号；位于第一级的第一移位寄存器（A_1）配置为响应于输出控制信号的控制输出扫描信号，以及响应于倍频控制信号的控制输出扫描信号。

Description

栅极驱动电路、显示基板、显示装置和栅极驱动方法 技术领域
本公开涉及显示领域，特别涉及一种栅极驱动电路、显示基板、显示装置和栅极驱动方法。
背景技术
目前，在有源矩阵有机发光二极管(Active-Matrix Organic Light-Emitting Diode，简称AMOLED)面板内，为实现对像素单元亮度的进一步控制，一般采用脉冲宽度调制(Pulse Width Modulation，简称PWM)调光；具体地，在像素单元所包含像素电路内设置一个发光控制晶体管，用于控制驱动电流流过有机发光二极管(Organic Light-Emitting Diode，简称OLED)的时间，从而对像素单元的等效亮度进行精确控制。
然而，现有栅极驱动电路可输出PWM信号的频率有限，较低频率的PWM信号会使得有机发光二极管出现肉眼可识别的闪烁现象，导致显示效果不佳。
发明内容
本公开旨在至少解决现有技术中存在的技术问题之一，提出了一种栅极驱动电路、显示基板、显示装置和栅极驱动方法。
第一方面，本公开实施例提供了一种栅极驱动电路，包括：倍频控制电路和有效输出电路，所述有效输出电路包括：若干个级联的第一移位寄存器，所述有效输出电路中位于第一级的第一移位寄存器配置有第一信号输入端和第二信号输入端，所述第一信号输入端与输出控制信号线耦接，所述第二信号输入端与所述倍频控制电路耦接，所述有效输出 电路中除位于第一级的第一移位寄存器之外的其他第一移位寄存器均配置有第一级联信号输入端，其他第一移位寄存器的第一级联信号输入端与各自所对应前一级的第一移位寄存器的信号输出端耦接；
所述倍频控制电路，与所述输出控制信号线耦接，配置为响应于所述输出控制信号线所提供的输出控制信号的控制，从接收到所述输出控制信号开始经过预设时长后向所述第二信号输入端提供倍频控制信号；
位于第一级的第一移位寄存器，配置为响应于所述输出控制信号的控制输出扫描信号，以及响应于所述倍频控制信号的控制输出扫描信号。
在一些实施例中，所述倍频控制电路包括：若干个级联的第二移位寄存器；
所述倍频控制电路中位于第一级的第一移位寄存器配置有第三信号输入端，所述第三信号输入端与所述输出控制信号线耦接；
所述倍频控制电路中除位于第一级的第二移位寄存器之外的其他第二移位寄存器均配置有第二级联信号输入端，其他第二移位寄存器的第二级联信号输入端与各自所对应前一级的第二移位寄存器的信号输出端耦接；
所述倍频控制电路中位于最后一级的第二移位寄存器的信号输出端与所述第二信号输入端耦接。
在一些实施例中，在所述倍频控制电路中，所述第二移位寄存器包括：信号写入电路、第一控制电路、第二控制电路和信号输出电路；
所述信号写入电路、所述第一控制电路、所述第二控制电路和所述信号输出电路四者耦接于第一节点，所述第一控制电路和所述第二控制电路两者耦接于第二节点，所述第二控制电路和所述信号输出电路两者耦接于第三节点；
所述信号写入电路，与对应的信号输入端和第一时钟信号端耦接，配置为响应于所述第一时钟信号端提供的第一时钟信号的控制，将对应 的信号输入端所提供的信号写入至所述第一节点；
所述第一控制电路，与第一电源端、所述第一时钟信号端耦接，配置为响应于所述第一时钟信号的控制，将所述第一电源端提供的第一工作电压写入至所述第二节点，以及响应于所述第一节点处电压的控制，将所述第一时钟信号写入至所述第二节点；
所述第二控制电路，与所述第二电源端、第二时钟信号端耦接，配置为响应于所述第二节点处电压、所述第二时钟信号端所提供的第二时钟信号的控制，将所述第二时钟信号写入至所述第三节点，以及响应于所述第一节点处电压的控制，将所述第二电源端提供的第二工作电压写入至所述第三节点；
所述信号输出电路，与所述第一电源端、所述第二电源端耦接，配置为响应于所述第一节点处电压的控制将所述第一工作电压写入至所述信号输出端，以及响应于所述第三节点处电压的控制将所述第二工作电压写入至所述信号输出端。
在一些实施例中，所述信号写入电路包括：第一晶体管，所述第一控制电路包括：第二晶体管和第三晶体管，所述第二控制电路包括：第四晶体管、第五晶体管、第六晶体管和第一电容，所述信号输出电路包括：第七晶体管、第八晶体管和第二电容；
所述第一晶体管的控制极与所述第一时钟信号端耦接，所述第一晶体管的第一极与所述信号输入端耦接，所述第一晶体管的第二极与所述第一节点耦接；
所述第二晶体管的控制极与所述第一节点耦接，所述第二晶体管的第一极与所述第一时钟信号端耦接，所述第二晶体管的第二极与所述第二节点耦接；
所述第三晶体管的控制极与所述第一时钟信号端耦接，所述第三晶体管的第一极与所述第一电源端耦接，所述第三晶体管的第二极与所述 第二节点耦接；
所述第四晶体管的控制极与所述第二节点耦接，所述第四晶体管的第一极与所述第二时钟信号端耦接，所述第四晶体管的第二极与所述第五晶体管的第一极耦接；
所述第五晶体管的控制极与所述第二时钟信号端耦接，所述第五晶体管的第二极与所述第三节点耦接；
所述第六晶体管的控制极与所述第一节点耦接，所述第六晶体管的第一极与所述第二电源端耦接，所述第六晶体管的第二极与所述第三节点耦接；
所述第一电容的第一端与所述第二节点耦接，所述第一电容的第二端与所述第四晶体管的第二极耦接；
所述第七晶体管的控制极与所述第三节点耦接，所述第七晶体管的第一极与所述第二电源端耦接，所述第七晶体管的第二极与所述信号输出端耦接；
所述第八晶体管的控制极与所述第一节点耦接，所述第八晶体管的第一极与所述第一电源端耦接，所述第八晶体管的第二极与所述信号输出端耦接；
所述第二电容的第一端与所述第三节点耦接，所述第三电容的第二端与所述第二电源端耦接。
在一些实施例中，所述第二移位寄存器还包括：降噪电路；
所述降噪电路，与所述第一节点、所述第二节点、所述第二电源端、所述第二时钟信号端耦接，配置为响应于所述第二时钟信号和所述第二节点处电压的控制，对所述第一节点处的电压进行降噪处理。
在一些实施例中，所述降噪电路包括：第九晶体管、第十晶体管和第三电容；
所述第九晶体管的控制极与所述第二节点耦接，所述第九晶体管的 第一极与所述第二电源端耦接，所述第九晶体管的第二极与所述第十晶体管的第一极耦接；
所述第十晶体管的控制极与所述第二晶体管信号端耦接，所述第十晶体管的第二极与所述第一节点耦接；
所述第三电容的第一端与所述第一节点耦接，所述第三电容的第二端与所述第二时钟信号端耦接。
在一些实施例中，在所述有效输出电路中的所述第一移位寄存器具有与所述倍频控制电路中的第二移位寄存器相同的电路结构。
在一些实施例中，在所述有效输出电路中，位于第一级的第一移位寄存器的第一信号输入端和第二信号输入端为同一信号输入端。
在一些实施例中，在所述有效输出电路中，位于第一级的第一移位寄存器的第一信号输入端和第二信号输入端为不同信号输入端；
位于第一级的第一移位寄存器配置有第二开关电路和第三开关电路；
所述第二开关电路，设置在所述信号写入电路与所述第一信号输入端之间，且与所述第二信号输入端耦接，配置为响应于所述第二信号输入端所提供的信号的控制，来控制所述信号写入电路与所述第一信号输入端之间的通断；
所述第三开关电路，设置在所述信号写入电路与所述第二信号输入端之间，且与所述第一信号输入端耦接，配置为响应于所述第一信号输入端所提供的信号的控制，来控制所述信号写入电路与所述第二信号输入端之间的通断。
在一些实施例中，所述第二开关电路包括：第十二晶体管，所述第三开关电路包括：第十三晶体管；
所述第十二晶体管的控制极与所述第二信号输入端耦接，所述第十二晶体管的第一极与所述第一信号输入端耦接，所述第十二晶体管的第 二极与所述信号写入电路耦接；
所述第十三晶体管的控制极与所述第一信号输入端耦接，所述第十三晶体管的第一极与所述第二信号输入端耦接，所述第十三晶体管的第二极与所述信号写入电路耦接。
在一些实施例中，在所述倍频控制电路中，位于第一级的第二移位寄存器配置有第一开关电路，所述第一开关电路设置在所述信号输出电路与所述第二电源端之间且与第一开关控制端耦接，配置为响应于所述第一开关控制端所提供第一开关控制信号的控制，来控制所述信号输出电路与所述第二电源端之间的通断。
在一些实施例中，所述第一开关电路包括：第十一晶体管；
所述第十一晶体管的控制极与第一开关控制端耦接，所述第十一晶体管的第一极与所述第二电源端耦接，所述第十一晶体管的第二极与所述信号输出电路耦接。
在一些实施例中，在所述倍频控制电路中，位于第一级的第二移位寄存器配置有第一开关电路，所述第一开关电路设置在所述第二控制电路与所述第二时钟信号端之间，配置为响应于所述第一开关控制端所提供第一开关控制信号的控制，来控制所述第二控制电路与所述第二时钟信号端之间的通断。
在一些实施例中，所述第一开关电路包括：第十一晶体管；
所述第十一晶体管的控制极与第一开关控制端耦接，所述第十一晶体管的第一极与所述第二时钟信号端耦接，所述第十一晶体管的第二极与所述第二控制电路耦接。
在一些实施例中，在所述倍频控制电路中，位于第一级的第二移位寄存器配置有第一开关电路，所述第一开关电路设置在所述信号写入电路与所述信号输入端之间且与第一开关控制端耦接，配置为响应于所述第一开关控制端所提供第一开关控制信号的控制，来控制所述信号写入 电路与所述信号输入端之间的通断。
在一些实施例中，所述第一开关电路包括：第十一晶体管；
所述第十一晶体管的控制极与第一开关控制端耦接，所述第十一晶体管的第一极与所述信号输入端耦接，所述第十一晶体管的第二极与所述信号写入电路耦接。
在一些实施例中，在所述倍频控制电路中，位于第一级的第二移位寄存器配置有第一供电电路；
所述第一供电电路与所述信号写入电路、所述第一开关电路、所述第一电源端和第二开关控制端耦接，配置响应于所述第二开关控制端所提供的所述第二开关控制信号的控制，向所述信号写入电路写入所述第一工作电压。
在一些实施例中，所述第一供电电路包括：第十四晶体管；
所述第十四晶体管的控制极与所述第二开关控制端耦接，所述第十四晶体管的第一极与所述第一电源端耦接，所述第十四晶体管的第二极与所述信号写入电路和所述第一开关电路耦接。
在一些实施例中，在所述倍频控制电路中，位于第一级的第二移位寄存器配置有第二供电电路；
所述第二供电电路与所述第一电源端、位于第一级的第二移位寄存器配的信号输出端和第二开关控制端耦接，配置为响应于所述第二开关控制端所提供的所述第二开关控制信号的控制，向所述第二移位寄存器的信号输出端写入所述第一工作电压。
在一些实施例中，所述第二供电电路包括：第十五晶体管；
所述第十五晶体管的控制极与所述第二开关控制端耦接，所述第十五晶体管的第一极与所述第一电源端耦接，所述第十五晶体管的第二极与位于第一级的第二移位寄存器配的信号输出端耦接。
在一些实施例中，还包括：反相电路，所述反相电路的输入端与所 述第一开关控制端耦接，所述反相电路的输出端与所述第二开关控制端耦接。
第二方面，本公开实施例还提供了一种显示基板，包括：第一方面提供的栅极驱动电路和位于显示区域内的多条栅线；
所述栅线与所述栅极驱动电路内对应的一个第一移位寄存器的信号输出端耦接。
第三方面，本公开实施例还提供了一种显示装置，包括：第一方面提供的显示基板和与所述显示基板相对设置的对置基板。
第四方面，本公开实施例还提供了一种栅极驱动方法，基于第一方面提供的栅极驱动电路，所述栅极驱动方法包括：
响应于所述输出控制信号，所述有效输出电路中的各级移位寄存器依次输出扫描信号，所述倍频控制电路经过预设时长后向所述有效输出电路中位于第一级的第一移位寄存器的所述第二信号输入端提供倍频控制信号；
响应于所述倍频控制信号，所述有效输出电路中的各级移位寄存器依次输出扫描信号。
附图说明
图1为本公开实施例提供的一种栅极驱动电路的电路结构示意图；
图2a为本公开实施例提供的另一种栅极驱动电路的电路结构示意图；
图2b为图2a所示栅极驱动电路的一种工作时序图；
图3为本公开实施例提供的一种第二移位寄存器的电路结构示意图；
图4为图3所示第二移位寄存器的一种电路结构示意图；
图5为图4所示第二移位寄存器的一种工作时序图；
图6a为本公开实施例中位于第一级的第二移位寄存器的一种电路结构示意图；
图6b为基于图6a所示位于第一级的第二移位寄存器的一种可选电路结构示意图；
图7a为本公开实施例中位于第一级的第二移位寄存器的另一种电路结构示意图；
图7b为基于图7a所示位于第一级的第二移位寄存器的一种可选电路结构示意图；
图8为本公开实施例中位于第一级的第二移位寄存器的又一种电路结构示意图；
图9为本公开实施例中位于第一级的第二移位寄存器的再一种电路结构示意图；
图10为本公开实施例中位于第一级的第二移位寄存器的再一种电路结构示意图；
图11为本公开实施例中位于第一级的第二移位寄存器的再一种电路结构示意图；
图12a为本公开实施例中位于第一级的第一移位寄存器的一种电路结构示意图；
图12b为基于图12a所示位于第一级的第一移位寄存器的一种可选电路结构示意图；
图13为本公开实施例提供的一种栅极驱动方法的方法流程图。
具体实施方式
为使本领域的技术人员更好地理解本公开的技术方案，下面结合附图对本公开提供的一种栅极驱动电路、显示基板、显示装置和栅极驱动方法进行详细描述。
在相关技术中，栅极驱动电路配置一条输出控制信号线(一般为帧起始信号线，用于提供帧起始信号)，该输出控制信号线与栅极驱动电路中位于第一级的移位寄存器耦接，用于控制位于第一级的移位寄存器输出扫描信号，位于栅极驱动电路中的其他级的移位寄存器会依次输出扫描信号。其中，栅极驱动电路中各级移位寄存器所输出扫描信号的频率等于输出控制信号线中所提供的输出控制信号的频率。示例性地，输出控制信号所提供的输出控制信号的频率为k，在相关技术中所涉及栅极驱动电路中各级移位寄存器所输出扫描信号的频率也为k。
由于为输出控制信号线提供信号的外部芯片的能力有限，使得输出控制信号线中加载的输出控制信号的频率有限，从而导致栅极驱动电路中各级移位寄存器所输出扫描信号的频率有限，对于一些需要高频率PWM信号的应用场景(例如，显示静态二维码，若PWM信号过低，则会导致明显闪烁，二维码难以被精准识别)，相关技术中涉及的栅极驱动电路无法满足高频输出需求。
为解决相关技术中存在的至少之一的技术问题，本公开技术方案提供了一种栅极驱动电路、显示基板、显示装置和栅极驱动方法。
图1为本公开实施例提供的一种栅极驱动电路的电路结构示意图，如图1所示，该一种栅极驱动电路包括：倍频控制电路1和有效输出电路2；其中，有效输出电路2包括：若干个级联的第一移位寄存器A_1、A_2…A_n，其中n为整数；有效输出电路2中位于第一级的第一移位寄存器配置A_1有第一信号输入端INPUT和第二信号输入端INPUT’，第一信号输入端INPUT与输出控制信号线耦接，第二信号输入端INPUT’与倍频控制电路1耦接，有效输出电路2中除位于第一级的第一移位寄存器之外的其他第一移位寄存器A_2…A_n均配置有第一级联信号输入端INPUT，其他第一移位寄存器的第一级联信号输入端INPUT与各自所对应前一级的第一移位寄存器的信号输出端OUT耦接。另外，每一个第 一移位寄存器A_1、A_2…A_n的信号输出端OUT耦接显示区域内的对应一条栅线GATE_1、GATE_2…GATE_n，用于向对应的栅线GATE_1、GATE_2…GATE_n提供扫描信号。需要说明的是，在本公开实施例中，第一信号输入端INPUT和第一级联信号输入端INPUT等同，均为第一移位寄存器的一个信号输入端。
倍频控制电路1与输出控制信号线耦接，配置为响应于输出控制信号线STV所提供的输出控制信号的控制，从接收到输出控制信号开始经过预设时长后向第二信号输入端INPUT’提供倍频控制信号。
位于第一级的第一移位寄存器A_1，配置为响应于输出控制信号的控制输出扫描信号，以及响应于倍频控制信号的控制输出扫描信号。对于其他级的第一移位寄存器，响应于位于自身的上一级的移位寄存器输出扫描信号的控制，自身输出扫描信号。对于整个有效输出电路2而言，在第一级的第一移位寄存器A_1的第一信号输入端INPUT或第二信号输入端INPUT’接收到脉冲后，有效输出电路2中各级第一移位寄存器A_1、A_2…A_n会依次输出扫描信号。
在本公开实施例中，输出控制信号线STV可以为帧起始信号线，也可以为根据实际需要所设置的其他信号线。本公开实施例中以输出控制信号线STV为帧起始信号线为例，进行示例性描述。针对该栅极驱动电路，配置有2条时钟信号线CLK和CLKB，用于为栅极驱动电路中的移位寄存器提供时钟信号。
以输出控制信号线STV提供的输出控制信号包含1个脉冲为例，本公开实施例提供的栅极确定电路的工作过程如下：响应于输出控制信号，有效输出电路2中的各级移位寄存器依次输出扫描信号，且每个扫描信号均包含1个脉冲；与此同时，倍频控制电路1经过预设时长后向有效输出电路2中位于第一级的第一移位寄存器A_1的第二信号输入端INPUT’提供倍频控制信号，输出控制信号包含1个脉冲；响应于倍频控 制信号，有效输出电路2中的各级第一移位寄存器A_1、A_2…A_n依次输出扫描信号，且每个扫描信号均包含1个脉冲。
其中，“预设时长”的大小可根据实际需要来进行设计。以有效输出电路2中的某一个第一移位寄存器为例，该第一移位寄存器连续所输出2个脉冲之间的延时为“预设时长”。
由上述内容可见，虽然输出控制信号仅提供了1个脉冲，但是有效输出电路2中的各级移位寄存器均会输出2个脉冲。基于相同原理，当输出控制信号提供了K个脉冲时，则栅极驱动电路中的各级第一移位寄存器可输出2K个脉冲。由此可见，本公开实施例提供的栅极驱动电路可以实现倍频输出，即提升了栅极驱动电路所输出扫描的频率上限，能有效避免因PWM信号频率过低而导致OLED出现肉眼可识别的闪烁。
本公开实施例中，倍频控制电路1具有延时输出功能，对于倍频控制电路1的具体电路结构，本公开的技术方案不作限定。本公开实施例中的有效输出电路2可等同于相关技术中的栅极驱动电路，其能够向显示面板中的栅线提供扫描信号，对于有效输出电路2(以及第一移位寄存器)的具体电路结构，本公开的技术方案也不作限定。
图2a为本公开实施例提供的另一种栅极驱动电路的电路结构示意图，图2b为图2a所示栅极驱动电路的一种工作时序图；如图2a和图2b所示，图2a所示栅极驱动电路为基于图1所示栅极驱动电路的一种更为具体的可选实施方案，其中倍频控制电路1包括：若干个级联的第二移位寄存器B_1、B_2…B_m，m为整数；倍频控制电路1中位于第一级的第二移位寄存器配置有第三信号输入端INPUT，第三信号输入端INPUT与输出控制信号线STV耦接；倍频控制电路1中除位于第一级的第二移位寄存器B_1之外的其他第二移位寄存器B_2…B_m均配置有第二级联信号输入端INPUT，其他第二移位寄存器B_2…B_m的第二级联信号输入端INPUT与各自所对应前一级的第二移位寄存器的信号输出端OUT耦接； 倍频控制电路1中位于最后一级的第二移位寄存器B_m的信号输出端OUT与第二信号输入端INPUT’耦接。
此时，倍频控制电路1作为一个仿制(Dummy)的栅极驱动电路，该栅极驱动电路中的各第二移位寄存器B_1、B_2…B_m具有级联关系，但是不会向显示区域中的栅线提供扫描信号。倍频控制电路1基于栅极驱动电路中级联的第二移位寄存器B_1、B_2…B_m的信号传递工作过程，实现对接收到的输出控制信号进行延迟输出(作为倍频控制信号进行输出)。
在实际应用中，可根据“预设时长”以及相邻两级第二移位寄存器输出脉冲信号的时间差来设计倍频控制电路1内所包含的第二移位寄存器的数量m。示例性地，预设时长时间为T,相邻两级第二移位寄存器输出脉冲信号的时间为t，则倍频控制电路1内所包含的第二移位寄存器的数量为T/t。
在图2b所示工作时序中，OUT(B_m)表示第m级的第二移位寄存器B_m的信号输出端，OUT(A_n)表示第n级的第一移位寄存器A_n的信号输出端。
需要说明的是，本公开实施例对第二移位寄存器的电路结构不作限定，第二移位寄存器可采用现有任意结构的移位寄存器，下面将结合附图进行示例性描述。
图3为本公开实施例提供的一种第二移位寄存器的电路结构示意图，如图3所示，该第二移位寄存器包括：信号写入电路101、第一控制电路102、第二控制电路103和信号输出电路104；信号写入电路101、第一控制电路102、第二控制电路103和信号输出电路104四者耦接于第一节点N1，第一控制电路102和第二控制电路103两者耦接于第二节点N2，第二控制电路103和信号输出电路104两者耦接于第三节点N3。
其中，信号写入电路101与对应的信号输入端INPUT和第一时钟信 号端CK耦接，配置为响应于第一时钟信号端CK提供的第一时钟信号的控制，将对应的信号输入端所提供的信号写入至第一节点N1。
第一控制电路102与第一电源端、第一时钟信号端CK耦接，配置为响应于第一时钟信号的控制，将第一电源端提供的第一工作电压写入至第二节点N2，以及响应于第一节点N1处电压的控制，将第一时钟信号写入至第二节点N2。
第二控制电路103与第二电源端、第二时钟信号端CKB耦接，配置为响应于第二节点N2处电压、第二时钟信号端CKB所提供的第二时钟信号的控制，将第二时钟信号写入至第三节点N3，以及响应于第一节点N1处电压的控制，将第二电源端提供的第二工作电压写入至第三节点N3。
信号输出电路104与第一电源端、第二电源端耦接，配置为响应于第一节点N1处电压的控制将第一工作电压写入至信号输出端OUT，以及响应于第三节点N3处电压的控制将第二工作电压写入至信号输出端OUT。
在一些实施例中，第二移位寄存器还包括：降噪电路；降噪电路与第一节点N1、第二节点N2、第二电源端、第二时钟信号端CKB耦接，配置为响应于第二时钟信号和第二节点N2处电压的控制，对第一节点N1处的电压进行降噪处理。
图4为图3所示第二移位寄存器的一种电路结构示意图，如图4所示，图4所示第二移位寄存器为基于图3所示第二移位寄存器的一种可选实施方案。
在一些实施例中，信号写入电路101包括：第一晶体管M1，第一控制电路102包括：第二晶体管M2和第三晶体管M3，第二控制电路103包括：第四晶体管M4、第五晶体管M5、第六晶体管M6和第一电容C1，信号输出电路104包括：第七晶体管M7、第八晶体管M8和第二电容C2。
第一晶体管M1的控制极与第一时钟信号端CK耦接，第一晶体管M1 的第一极与信号输入端INPUT耦接，第一晶体管M1的第二极与第一节点N1耦接。
第二晶体管M2的控制极与第一节点N1耦接，第二晶体管M2的第一极与第一时钟信号端CK耦接，第二晶体管M2的第二极与第二节点N2耦接。
第三晶体管M3的控制极与第一时钟信号端CK耦接，第三晶体管M3的第一极与第一电源端耦接，第三晶体管M3的第二极与第二节点N2耦接。
第四晶体管M4的控制极与第二节点N2耦接，第四晶体管M4的第一极与第二时钟信号端CKB耦接，第四晶体管M4的第二极与第五晶体管M5的第一极耦接。
第五晶体管M5的控制极与第二时钟信号端CKB耦接，第五晶体管M5的第二极与第三节点N3耦接。
第六晶体管M6的控制极与第一节点N1耦接，第六晶体管M6的第一极与第二电源端耦接，第六晶体管M6的第二极与第三节点N3耦接。
第一电容C1的第一端与第二节点N2耦接，第一电容C1的第二端与第四晶体管M4的第二极耦接。
第七晶体管M7的控制极与第三节点N3耦接，第七晶体管M7的第一极与第二电源端耦接，第七晶体管M7的第二极与信号输出端OUT耦接。
第八晶体管M8的控制极与第一节点N1耦接，第八晶体管M8的第一极与第一电源端耦接，第八晶体管M8的第二极与信号输出端OUT耦接。
第二电容C2的第一端与第三节点耦接，第二电容C2的第二端与第一电源端耦接。
在一些实施例中，降噪电路包括：第九晶体管M9、第十晶体管M10和第三电容C3。
第九晶体管M9的控制极与第二节点N2耦接，第九晶体管M9的第一 极与第二电源端耦接，第九晶体管M9的第二极与第十晶体管M10的第一极耦接。
第十晶体管M10的控制极与第二晶体管M2信号端耦接，第十晶体管M10的第二极与第一节点N1耦接。
第三电容C3的第一端与第一节点N1耦接，第三电容C3的第二端与第二时钟信号端CKB耦接。
在本公开实施例中，所涉及的各个晶体管可分别独立选自多晶硅薄膜晶体管、非晶硅薄膜晶体管、氧化物薄膜晶体管以及有机薄膜晶体管中的一种。在本公开实施例中涉及到的“控制极”具体是指晶体管的栅极，“第一极”具体是指晶体管的源极，相应的“第二极”具体是指晶体管的漏极。当然，本领域的技术人员应该知晓的是，该“第一极”与“第二极”可进行互换。
另外，晶体管可以划分为N型晶体管和P型晶体管，本公开中的各晶体管可分别独立选自N型晶体管或P型晶体管；在下述实施例中将以像素单元中的全部晶体管均为P型晶体管为例进行示例性描述，此时第二移位寄存器中的晶体管可采用相同的制备工艺得以同时制备。相应地，第一电源端提供的第一工作电压为低电平电压VGL，第二电源端提供的第二工作电压为高电平电压VGH。下面将结合附图来对图4所示第二移位寄存器的工作过程进行详细描述。
图5为图4所示第二移位寄存器的工作时序图，如图5所示，该第二移位寄存器工作过程包括如下阶段：
第一阶段t1，第一时钟信号端CK提供的第一时钟信号处于低电平状态，第二时钟信号端CKB提供的第二时钟信号处于高电平状态，第三信号输入端INPUT提供的信号处于高电平状态。此时，第一晶体管M1、第三晶体管M3、第四晶体管M4和第九晶体管M9处于导通状态，第二晶体管M2、第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管 M8和第十晶体管M10处于截止状态。
具体地，由于第一时钟信号处于低电平状态，因此第一晶体管M1和第三晶体管M3均导通，第三信号输入端INPUT提供处于高电平状态的信号通过第一晶体管M1写入至第一节点N1，第一工作电压VGL通过第三晶体管M3写入至第二节点N2，第一节点N1处于高电平状态，第二节点N2处于低电平状态。
由于第一节点N1处于高电平状态，因此第六晶体管M6和第八晶体管M8截止。由于第二节点N2处于低电平状态，因此第四晶体管M4和第九晶体管M9处于导通状态，处于高电平状态的第二时钟信号通过第四晶体管M4写入至第四节点N4，第二工作电压VGH通过第九晶体管M9写入至第五节点N5。此时，第一电容C1的第一端处于低电平状态，第一电容C1的第二端处于高电平状态。
由于第二时钟信号处于高电平状态，因此第五晶体管M5和第十晶体管M10截止。又由于第五晶体管M5和第六晶体管M6均截止，因此第三节点N3处于浮接(floating)状态，第三节点N3处电压维持之前的高电平状态，第七晶体管M7截止。
由于第七晶体管M7和第八晶体管M8均截止，信号输出端OUT处于floating状态，信号输出端OUT处电压维持之前的低电平状态。
第二阶段t2，第一时钟信号端CK提供的第一时钟信号处于高电平状态，第二时钟信号端CKB提供的第二时钟信号处于低电平状态，第三信号输入端INPUT提供的信号处于低电平状态。此时，第四晶体管M4、第五晶体管M5、第七晶体管M7和第九晶体管M9和第十晶体管M10处于导通状态，第一晶体管M1、第二晶体管M2、第三晶体管M3、第六晶体管M6、第八晶体管M8处于截止状态。
具体地，由于第一时钟信号处于高电平状态，因此第一晶体管M1和第三晶体管M3均截止。由于第二时钟信号处于低电平状态，因此第五 晶体管M5和第十晶体管M10导通，此时第二工作电压VGH通过第九晶体管M9、第十晶体管M10写入至第一节点N1，以维持第一节点N1处于高电平状态，实现对第一节点N1的降噪处理，第二晶体管M2和第八晶体管M8维持截止状态。此时第三电容C3的第一端处于高电平状态，第三电容C3的第二端处于低电平状态。
与此同时，由于处于低电平状态的第二时钟信号通过第四晶体管M4写入至第四节点N4，第四节点N4处电压由高电平状态变为低电平状态，由于第一电容C1的第一端处于floating状态，在第一电容C1的自举作用下，第二节点N2处的电压被下拉至更低状态水平。
由于第五晶体管M5导通，因此处于低电平状态的第二时钟信号通过第四晶体管M4、第五晶体管M5写入至第三节点N3，第三节点N3处于低电平状态，第七晶体管M7导通，第二工作电压VGH通过第七晶体管M7写入至信号输出端OUT，信号输出端OUT输出高电平信号。
第三阶段t3，第一时钟信号端CK提供的第一时钟信号处于低电平状态，第二时钟信号端CKB提供的第二时钟信号处于高电平状态，第三信号输入端INPUT提供的信号处于低电平状态。此时，第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第六晶体管M6、第八晶体管M8和第九晶体管M9处于导通状态，第五晶体管M5、第七晶体管M7和第十晶体管M10处于截止状态。
具体地，由于第一时钟信号处于低电平状态，因此第一晶体管M1和第三晶体管M3均导通，第三信号输入端INPUT提供处于低电平状态的信号通过第一晶体管M1写入至第一节点N1，第一工作电压VGL通过第三晶体管M3写入至第二节点N2，第一节点N1处于低电平状态，第二节点N2处于低电平状态。第三电容C3的第一端处于低电平状态，第三电容C3的第二端处于高电平状态。
由于第一节点N1处于低电平状态，因此第六晶体管M6和第八晶体 管M8导通。由于第二节点N2处于低电平状态，因此第四晶体管M4和第九晶体管M9处于导通状态，处于高电平状态的第二时钟信号通过第四晶体管M4写入至第四节点N4，第二工作电压VGH通过第九晶体管M9写入至第五节点N5。此时，第一电容C1的第一端处于低电平状态，第一电容C1的第二端处于高电平状态。
由于第二时钟信号处于高电平状态，因此第五晶体管M5和第十晶体管M10截止。又由于第五晶体管M5和第六晶体管M6均截止；第二工作电压VGH通过第六晶体管M6写入至第三节点N3，第三节点N3处于高电平状态。
由于第一节点N1处于低电平状态，第三节点N3处于高电平状态，因此第七晶体管M7截止，第八晶体管M8导通，第一工作电压VGL通过第八晶体管M8写入至信号输出端OUT，信号输出端OUT输出低电平信号。
第四阶段t4，第一时钟信号端CK提供的第一时钟信号处于高电平状态，第二时钟信号端CKB提供的第二时钟信号处于低电平状态，第三信号输入端INPUT提供的信号处于低电平状态。此时，第二晶体管M2、第五晶体管M5、第六晶体管M6、第八晶体管M8和第十晶体管M10处于导通状态，第一晶体管M1、第三晶体管M3、第四晶体管M4、第七晶体管M7和第九晶体管M9处于截止状态。
具体地，由于第一时钟信号处于高电平状态，因此第一晶体管M1和第三晶体管M3均截止。由于第一晶体管M1截止，因此第一节点N1处于浮接状态；又由于第二时钟信号由高电平状态切换至低电平状态，在第三电容C3的自举作用下，第一节点N1处电压被下拉至更低状态，以对第一节点N1进行降噪处理。此时第二晶体管M2、第六晶体管M6和第八晶体管M8均导通。第二工作电压VGH通过第六晶体管M6写入至第三节点N3。
由于第二晶体管M2处于导通状态，因此处于高电平状态的第一时钟 信号通过第二晶体管M2写入至第二节点N2，第二节点N2处于高电平状态，第四晶体管M4截止。
由于第二时钟信号处于低电平状态，因此第五晶体管M5、第十晶体管M10处于导通状态，此时第四节点N4处的电压等于第三节点N3处的电压，第五节点N5处的电压等于第一节点N1处的电压，即第四节点N4处电压处于高电平状态，第五节点N5处电压处于低电平状态。
由于第一节点N1处于低电平状态，第三节点N3处于高电平状态，因此第七晶体管M7截止，第八晶体管M8导通，第一工作电压VGL通过第八晶体管M8写入至信号输出端OUT，信号输出端OUT输出低电平信号。
第五阶段t5，第一时钟信号端CK提供的第一时钟信号处于低电平状态，第二时钟信号端CKB提供的第二时钟信号处于高电平状态，第三信号输入端INPUT提供的信号处于低电平状态。此时，第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第六晶体管M6、第八晶体管M8和第九晶体管M9处于导通状态，第五晶体管M5、第七晶体管M7和第十晶体管M10处于截止状态。
具体地，由于第一时钟信号处于低电平状态，因此第一晶体管M1和第三晶体管M3均导通，第三信号输入端INPUT提供处于低电平状态的信号通过第一晶体管M1写入至第一节点N1，第一工作电压VGL通过第三晶体管M3写入至第二节点N2，第一节点N1处于低电平状态，第二节点N2处于低电平状态。第三电容C3的第一端处于低电平状态，第三电容C3的第二端处于高电平状态。
由于第一节点N1处于低电平状态，因此第六晶体管M6和第八晶体管M8导通。由于第二节点N2处于低电平状态，因此第四晶体管M4和第九晶体管M9处于导通状态，处于高电平状态的第二时钟信号通过第四晶体管M4写入至第四节点N4，第二工作电压VGH通过第九晶体管M9写入至第五节点N5。此时，第一电容C1的第一端处于低电平状态，第一电 容C1的第二端处于高电平状态。
由于第二时钟信号处于高电平状态，因此第五晶体管M5和第十晶体管M10截止。又由于第五晶体管M5和第六晶体管M6均截止；第二工作电压VGH通过第六晶体管M6写入至第三节点N3，第三节点N3处于高电平状态。
由于第一节点N1处于低电平状态，第三节点N3处于高电平状态，因此第七晶体管M7截止，第八晶体管M8导通，第一工作电压VGL通过第八晶体管M8写入至信号输出端OUT，信号输出端OUT输出低电平信号。
此后交替执行第四阶段t4和第五阶段t5，信号输出端OUT维持输出低电平信号，直至第三信号输入端INPUT提供的信号处于高电平状态，第二移位寄存器工作于下一周期的第一阶段t1。
需要说明的是，图4所示的第二移位寄存器的电路结构仅起到示例性作用，其不会对本公开的技术方案产生限制，本公开中的第二移位寄存器还可以还有其他电路结构，此处不再一一举例。
在一些实施例中，在有效输出电路2中的第一移位寄存器具有与倍频控制电路1中的第二移位寄存器相同的电路结构，此时可以简化整个栅极驱动电路的电路结构设计。
示例性地，位于奇数级的第一/第二移位寄存器的第一时钟信号端CK与时钟信号线CLK耦接，位于偶数级的第一/第二移位寄存器的第二时钟信号端CKB与时钟信号线CLKB耦接。
图6a为本公开实施例中位于第一级的第二移位寄存器的一种电路结构示意图，如图6a所示，图6a所示第二移位寄存器为基于图3所示第二移位寄存器的一种改进。
在一些实施例中，为控制栅极驱动电路的“倍频功能”的开启和关闭，在在倍频控制电路1中，位于第一级的第二移位寄存器B_1配置有第一开关电路106；第一开关电路106设置在位于第一级的第二移位寄 存器内信号输出电路104与第二电源端之间，第一开关电路106用于控制信号输出电路104与第二电源端之间的通断。
具体地，当第一开关电路106处于导通状态时，位于第一级的第二移位寄存器内的信号输出电路104与第二电源端之间导通，位于第一级的第二移位寄存器可正常工作，栅极驱动电路的“倍频功能”的开启；当第一开关电路106处于截止状态时，位于第一级的第二移位寄存器B_1内的信号输出电路104与第二电源端之间断路，位于第一级的第二移位寄存器B_1可无法正常工作，栅极驱动电路的“倍频功能”的关闭。
图6b为基于图6a所示位于第一级的第二移位寄存器的一种可选电路结构示意图，如图6b所示，图6b的信号写入电路101、第一控制电路102、第二控制电路103和信号输出电路104的具体电路可采用图4中所示。
需要说明的是，图6b所示情况仅起到示例性作用，在本公开实施例中，信号写入电路101、第一控制电路102、第二控制电路103和信号输出电路104也可以采用其他电路结构，此处不在一一举例。
图7a为本公开实施例中位于第一级的第二移位寄存器的另一种电路结构示意图，如图7a所示，与图6a所示情况不同的是，图7a中的第一开关电路106设置于位于第一级的第二移位寄存器B_1内第二控制电路103与第二时钟信号端CKB之间，第一开关电路106用于控制第二控制电路103与第二时钟信号端CKB之间的通断。
具体地，当第一开关电路106处于导通状态时，位于第一级的第二移位寄存器B_1内的第二控制电路103与第二时钟信号端之间导通，位于第一级的第二移位寄存器B_1可正常工作，栅极驱动电路的“倍频功能”的开启；当第一开关电路106处于截止状态时，位于第一级的第二移位寄存器B_1内的第二控制电路103与第二时钟信号端之间断路，位于第一级的第二移位寄存器B_1可无法正常工作，栅极驱动电路的“倍 频功能”的关闭。
图7b为基于图7a所示位于第一级的第二移位寄存器的一种可选电路结构示意图，如图7b所示，图7b的信号写入电路101、第一控制电路102、第二控制电路103和信号输出电路104的具体电路可采用图4中所示。
需要说明的是，图7b所示情况仅起到示例性作用，在本公开实施例中，信号写入电路101、第一控制电路102、第二控制电路103和信号输出电路104也可以采用其他电路结构，此处不在一一举例。
继续参见图6b和图7b所示，在一些实施例中，第一开关电路106包括：第十一晶体管M11。其中，当第一开关电路106设置在信号输出电路104与第二电源端之间时，第十一晶体管M11的控制极与开关控制端SC耦接，第十一晶体管M11的第一极与第二电源端耦接，第十一晶体管M11的第二极与信号输出电路104耦接；当第一开关电路106设置在第二控制电路103与第二时钟信号端CKB之间时，第十一晶体管M11的控制极与开关控制端SC耦接，第十一晶体管M11的第一极与第二时钟信号端CKB耦接，第十一晶体管M11的第二极与第二控制电路103耦接。
需要说明的是，图7b中仅示例给出了第一开关电路106(第十一晶体管M11)设置于第二时钟信号端与第四晶体管M4的第一极之间的情况，当然第一开关电路106(第十一晶体管M11)也可以设置于第二时钟信号端与第五晶体管M5的控制极之间。
图8为本公开实施例中位于第一级的第二移位寄存器的又一种电路结构示意图，如图8所示，与图6a～图7b所示情况不同，图8所示情况中，第一开关电路106设置在信号写入电路101与信号输入端INPUT之间，第一开关电路106配置为响应于第一开关控制端SC所提供第一开关控制信号的控制，来控制信号写入电路101与信号输入端INPUT之间的通断。
具体地，当第一开关电路106处于导通状态时，位于第一级的第二移位寄存器B_1内的信号写入电路101与信号输入端INPUT之间导通，位于第一级的第二移位寄存器B_1可正常工作，栅极驱动电路的“倍频功能”的开启；当第一开关电路106处于截止状态时，位于第一级的第二移位寄存器B_1内的信号写入电路101与信号输入端INPUT之间断路，位于第一级的第二移位寄存器B_1可无法正常工作，栅极驱动电路的“倍频功能”的关闭。
在一些实施例中，第一开关电路106包括：第十一晶体管M11，第十一晶体管M11的控制极与第一开关控制端SC耦接，第十一晶体管M11的第一极与信号输入端INPUT耦接，第十一晶体管M11的第二极与信号写入电路101耦接。
在信号写入电路101与信号输入端INPUT之间断路时，信号写入电路101上用于与信号输入端INPUT进行耦接的一端N6会处于浮接状态(floating)并容易受到外界干扰而使得电压产生偏移，当信号写入电路101上用于与信号输入端INPUT进行耦接的一端N6电压偏移至高电平状态时，就会导致位于第一级的第二移位寄存器产生误输出，后面各级第二移位寄存器也会产生误输出，从而导致栅极驱动电路的“倍频功能”异常开启。
为解决栅极驱动电路的“倍频功能”异常开启的技术问题，本公开实施例提供了相应的解决方案。图9为本公开实施例中位于第一级的第二移位寄存器的再一种电路结构示意图，与图8所示情况不同，图9所示情况中在倍频控制电路内位于第一级的第二移位寄存器配置有第一供电电路107，第一供电电路107与信号写入电路101、第一开关电路106、第一电源端和第二开关控制端SCB耦接，第一供电电路107配置为响应于第二开关控制端SCB所提供的第二开关控制信号的控制向信号写入电路101写入第一工作电压。
在本公开实施例中，在第一开关电路106控制信号写入电路101与信号输入端INPUT之间断路时，可通过第二开关控制信号来控制第一供电电路107进行工作。具体地，第一供电电路107将第一工作电压写入至信号写入电路101上用于与信号输入端INPUT进行耦接的一端N6以维持该端的电压稳定，从而能避免栅极驱动电路的“倍频功能”异常开启。
参见图9所示，在一些实施例中，第一供电电路107包括：第十四晶体管M14，第十四晶体管M14的控制极与第二开关控制端SCB耦接，第十四晶体管M14的第一极与第一电源端耦接，第十四晶体管M14的第二极与信号写入电路101和第一开关电路106耦接。
图8和图9内的信号写入电路101、第一控制电路102、第二控制电路103和信号输出电路104的具体电路可采用图4中所示。
图10为本公开实施例提供的另一种第二移位寄存器的电路结构示意图，如图10所示，在一些实施例中，在倍频控制电路1中，位于第一级的第二移位寄存器配置有第一开关电路106和第二供电电路109。对于第一开关电路的具体实施方案可参见前面实施例中的内容(图10中仅示例性画出了第一开关电路106采用图9中所示情况)，此处不再赘述；下面仅对第二供电电路进行详细描述。
其中，第二供电电路109与第一电源端、位于第一级的第二移位寄存器B_1的信号输出端OUT和第二开关控制端SCB耦接，第二供电电路109配置为响应于第二开关控制端SCB所提供的第二开关控制信号的控制向位于第一级的第二移位寄存器B_1的信号输出端OUT写入第一工作电压。
在通过第一开关电路106使得信号输出电路与第二电源端之间的断路(图6a所示第一开关电路106设于信号输出电路与第二电源端之间)、或者使得第二控制电路103与第二时钟信号端之间断路(图7a所示第一开关电路106设于第二控制电路103与第二时钟信号端CKB之间)、或 者使得信号写入电路101与信号输入端INPUT之间断路(图8所示第一开关电路106设于信号写入电路101与信号输入端INPUT之间)时，可通过第二开关控制信号控制第二供电电路109向相连的第二移位寄存器的信号输出端OUT写入第一工作电压，以对位于第一级的第二移位寄存器B_1的信号输出端OUT进行降噪处理，从而能避免栅极驱动电路的“倍频功能”异常开启。
在一些实施例中，第二供电电路109包括：第十五晶体管M15；第十五晶体管M15的控制极与第二开关控制端SCB耦接，第十五晶体管M15的第一极与第一电源端耦接，第十五晶体管M15的第二极与位于第一级的第二移位寄存器B_1的信号输出端OUT耦接。
图11为本公开实施例中位于第一级的第二移位寄存器的再一种电路结构示意图，如图11所示，与图9和图10中所示情况不同，图11所示位于第一级的第二移位寄存器B_1同时配置有第一供电电路107(包括第十四晶体管M14)和第二供电电路109(包括第十五晶体管M15)。
在一些实施例中，栅极驱动电路还包括：反相电路108，反相电路108的输入端与第一开关控制端SC耦接，反相电路108的输出端与第二开关控制端SCB耦接，反相电路108配置为对输入端的信号进行反相处理。具体地，反相电路108能够对第一开关控制端SC所提供的第一开关控制信号进行反相处理，从而得到第二开关控制信号。此时，对于两个不同的开关控制端SC、SCB，仅需外部芯片提供一个开关控制信号即可。
在一些实施例中，在有效输出电路2中，位于第一级的第一移位寄存器A_1的第一信号输入端INPUT和第二信号输入端INPUT’为同一信号输入端，即位于第一级的第一移位寄存器A_1配置有一个信号输入端，该信号输入端同时与输出控制信号端和倍频控制电路1用于输出倍频控制信号的信号输出端OUT耦接。
图12a为本公开实施例中位于第一级的第一移位寄存器的一种电路 结构示意图，如图12a所示，在一些实施例中，位于第一级的第一移位寄存器A_1的第一信号输入端INPUT和第二信号输入端INPUT’为不同信号输入端；位于第一级的第一移位寄存器A_1还包括：第二开关电路110和第三开关电路111。
其中，第二开关电路110设置在位于第一级的第一移位寄存器内信号写入电路101与第一信号输入端INPUT之间，且与第二信号输入端INPUT’耦接，第二开关电路110配置为响应于第二信号输入端INPUT’所提供的信号的控制，来控制信号写入电路101与第一信号输入端INPUT之间的通断。
第三开关电路111设置在位于第一级的第一移位寄存器A_1内信号写入电路101与第二信号输入端INPUT’之间，且与第一信号输入端INPUT耦接，第三开关电路111配置为响应于第一信号输入端INPUT所提供的信号的控制，来控制信号写入电路101与第二信号输入端INPUT’之间的通断。
在一些实施例中，第二开关电路110包括：第十二晶体管M12，第三开关电路111包括：第十三晶体管M14。其中，第十二晶体管M12的控制极与第二信号输入端INPUT’耦接，第十二晶体管M12的第一极与第一信号输入端INPUT耦接，第十二晶体管M12的第二极与信号写入电路101耦接；第十三晶体管M14的控制极与第一信号输入端INPUT耦接，第十三晶体管M14的第一极与第二信号输入端INPUT’耦接，第十三晶体管M14的第二极与信号写入电路101耦接。
图12b为基于图12a所示位于第一级的第一移位寄存器的一种可选电路结构示意图，如图12b所示，图12b的信号写入电路101、第一控制电路102、第二控制电路103和信号输出电路104的具体电路可采用图4中所示。
需要说明的是，图12b所示情况仅起到示例性作用，在本公开实施 例中，信号写入电路101、第一控制电路102、第二控制电路103和信号输出电路104也可以采用其他电路结构，此处不在一一举例。
本公开实施例还提供了一种显示基板，该显示基板包括上述实施例提供的栅极驱动电路和位于显示区域内的多条栅线；栅线与栅极驱动电路内对应的一个第一移位寄存器的信号输出端耦接，对于该栅极驱动电路的具体描述，可参见前面实施例中内容，此处不再赘述。
本公开实施例还提供了一种显示装置，包括上述实施例提供的显示基板和与显示基板相对设置的对置基板，对于该显示基板的具体描述，可参见前面实施例中内容，此处不再赘述。
其中，显示装置可以为电子纸、液晶显示面板、LED面板、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
图13为本公开实施例提供的一种栅极驱动方法的方法流程图，如图13所示，该栅极驱动方法基于上述实施例所提供的栅极驱动电路，该栅极驱动方法包括：
步骤S1、响应于输出控制信号，有效输出电路中的各级移位寄存器依次输出扫描信号，倍频控制电路经过预设时长后向有效输出电路中位于第一级的第一移位寄存器的第二信号输入端提供倍频控制信号。
步骤S2、响应于倍频控制信号，有效输出电路中的各级移位寄存器依次输出扫描信号。
对于步骤S1和步骤S2的具体描述，可参见前面实施例中相应内容，此处不再赘述。
本公开的技术方案通过在有效输出电路的基础上设置倍频控制电路，倍频控制电路可从接收到输出控制信号开始经过预设时长后向第二信号输入端提供倍频控制信号，使得有效输出电路可实现倍频输出，即提升了栅极驱动电路所输出扫描的频率上限，能有效避免因PWM信号频 率过低而导致OLED出现肉眼可识别的闪烁。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (24)

  1. 一种栅极驱动电路，其中，包括：倍频控制电路和有效输出电路，所述有效输出电路包括：若干个级联的第一移位寄存器，所述有效输出电路中位于第一级的第一移位寄存器配置有第一信号输入端和第二信号输入端，所述第一信号输入端与输出控制信号线耦接，所述第二信号输入端与所述倍频控制电路耦接，所述有效输出电路中除位于第一级的第一移位寄存器之外的其他第一移位寄存器均配置有第一级联信号输入端，其他第一移位寄存器的第一级联信号输入端与各自所对应前一级的第一移位寄存器的信号输出端耦接；
    所述倍频控制电路，与所述输出控制信号线耦接，配置为响应于所述输出控制信号线所提供的输出控制信号的控制，从接收到所述输出控制信号开始经过预设时长后向所述第二信号输入端提供倍频控制信号；
    位于第一级的第一移位寄存器，配置为响应于所述输出控制信号的控制输出扫描信号，以及响应于所述倍频控制信号的控制输出扫描信号。
  2. 根据权利要求1所述的栅极驱动电路，其中，所述倍频控制电路包括：若干个级联的第二移位寄存器；
    所述倍频控制电路中位于第一级的第二移位寄存器配置有第三信号输入端，所述第三信号输入端与所述输出控制信号线耦接；
    所述倍频控制电路中除位于第一级的第二移位寄存器之外的其他第二移位寄存器均配置有第二级联信号输入端，其他第二移位寄存器的第二级联信号输入端与各自所对应前一级的第二移位寄存器的信号输出端耦接；
    所述倍频控制电路中位于最后一级的第二移位寄存器的信号输出端与所述第二信号输入端耦接。
  3. 根据权利要求1所述的栅极驱动电路，其中，在所述倍频控制电路中，所述第二移位寄存器包括：信号写入电路、第一控制电路、第二控制电路和信号输出电路；
    所述信号写入电路、所述第一控制电路、所述第二控制电路和所述信号输出电路四者耦接于第一节点，所述第一控制电路和所述第二控制电路两者耦接于第二节点，所述第二控制电路和所述信号输出电路两者耦接于第三节点；
    所述信号写入电路，与对应的信号输入端和第一时钟信号端耦接，配置为响应于所述第一时钟信号端提供的第一时钟信号的控制，将对应的信号输入端所提供的信号写入至所述第一节点；
    所述第一控制电路，与第一电源端、所述第一时钟信号端耦接，配置为响应于所述第一时钟信号的控制，将所述第一电源端提供的第一工作电压写入至所述第二节点，以及响应于所述第一节点处电压的控制，将所述第一时钟信号写入至所述第二节点；
    所述第二控制电路，与所述第二电源端、第二时钟信号端耦接，配置为响应于所述第二节点处电压、所述第二时钟信号端所提供的第二时钟信号的控制，将所述第二时钟信号写入至所述第三节点，以及响应于所述第一节点处电压的控制，将所述第二电源端提供的第二工作电压写入至所述第三节点；
    所述信号输出电路，与所述第一电源端、所述第二电源端耦接，配置为响应于所述第一节点处电压的控制将所述第一工作电压写入至所述信号输出端，以及响应于所述第三节点处电压的控制将所述第二工作电压写入至所述信号输出端。
  4. 根据权利要求3所述的栅极驱动电路，其中，所述信号写入电路 包括：第一晶体管，所述第一控制电路包括：第二晶体管和第三晶体管，所述第二控制电路包括：第四晶体管、第五晶体管、第六晶体管和第一电容，所述信号输出电路包括：第七晶体管、第八晶体管和第二电容；
    所述第一晶体管的控制极与所述第一时钟信号端耦接，所述第一晶体管的第一极与所述信号输入端耦接，所述第一晶体管的第二极与所述第一节点耦接；
    所述第二晶体管的控制极与所述第一节点耦接，所述第二晶体管的第一极与所述第一时钟信号端耦接，所述第二晶体管的第二极与所述第二节点耦接；
    所述第三晶体管的控制极与所述第一时钟信号端耦接，所述第三晶体管的第一极与所述第一电源端耦接，所述第三晶体管的第二极与所述第二节点耦接；
    所述第四晶体管的控制极与所述第二节点耦接，所述第四晶体管的第一极与所述第二时钟信号端耦接，所述第四晶体管的第二极与所述第五晶体管的第一极耦接；
    所述第五晶体管的控制极与所述第二时钟信号端耦接，所述第五晶体管的第二极与所述第三节点耦接；
    所述第六晶体管的控制极与所述第一节点耦接，所述第六晶体管的第一极与所述第二电源端耦接，所述第六晶体管的第二极与所述第三节点耦接；
    所述第一电容的第一端与所述第二节点耦接，所述第一电容的第二端与所述第四晶体管的第二极耦接；
    所述第七晶体管的控制极与所述第三节点耦接，所述第七晶体管的第一极与所述第二电源端耦接，所述第七晶体管的第二极与所述信号输出端耦接；
    所述第八晶体管的控制极与所述第一节点耦接，所述第八晶体管的 第一极与所述第一电源端耦接，所述第八晶体管的第二极与所述信号输出端耦接；
    所述第二电容的第一端与所述第三节点耦接，所述第三电容的第二端与所述第二电源端耦接。
  5. 根据权利要求3所述的栅极驱动电路，其中，所述第二移位寄存器还包括：降噪电路；
    所述降噪电路，与所述第一节点、所述第二节点、所述第二电源端、所述第二时钟信号端耦接，配置为响应于所述第二时钟信号和所述第二节点处电压的控制，对所述第一节点处的电压进行降噪处理。
  6. 根据权利要求5所述的栅极驱动电路，其中，所述降噪电路包括：第九晶体管、第十晶体管和第三电容；
    所述第九晶体管的控制极与所述第二节点耦接，所述第九晶体管的第一极与所述第二电源端耦接，所述第九晶体管的第二极与所述第十晶体管的第一极耦接；
    所述第十晶体管的控制极与所述第二晶体管信号端耦接，所述第十晶体管的第二极与所述第一节点耦接；
    所述第三电容的第一端与所述第一节点耦接，所述第三电容的第二端与所述第二时钟信号端耦接。
  7. 根据权利要求3至6中任一所述的栅极驱动电路，其中，在所述有效输出电路中的所述第一移位寄存器具有与所述倍频控制电路中的第二移位寄存器相同的电路结构。
  8. 根据权利要求7所述的栅极驱动电路，其中，在所述有效输出电 路中，位于第一级的第一移位寄存器的第一信号输入端和第二信号输入端为同一信号输入端。
  9. 根据权利要求7所述的栅极驱动电路，其中，在所述有效输出电路中，位于第一级的第一移位寄存器的第一信号输入端和第二信号输入端为不同信号输入端；
    位于第一级的第一移位寄存器配置有第二开关电路和第三开关电路；
    所述第二开关电路，设置在所述信号写入电路与所述第一信号输入端之间，且与所述第二信号输入端耦接，配置为响应于所述第二信号输入端所提供的信号的控制，来控制所述信号写入电路与所述第一信号输入端之间的通断；
    所述第三开关电路，设置在所述信号写入电路与所述第二信号输入端之间，且与所述第一信号输入端耦接，配置为响应于所述第一信号输入端所提供的信号的控制，来控制所述信号写入电路与所述第二信号输入端之间的通断。
  10. 根据权利要求9所述的栅极驱动电路，其中，所述第二开关电路包括：第十二晶体管，所述第三开关电路包括：第十三晶体管；
    所述第十二晶体管的控制极与所述第二信号输入端耦接，所述第十二晶体管的第一极与所述第一信号输入端耦接，所述第十二晶体管的第二极与所述信号写入电路耦接；
    所述第十三晶体管的控制极与所述第一信号输入端耦接，所述第十三晶体管的第一极与所述第二信号输入端耦接，所述第十三晶体管的第二极与所述信号写入电路耦接。
  11. 根据权利要求3至10中任一所述的栅极驱动电路，其中，在所述倍频控制电路中，位于第一级的第二移位寄存器配置有第一开关电路，所述第一开关电路设置在所述信号输出电路与所述第二电源端之间且与第一开关控制端耦接，配置为响应于所述第一开关控制端所提供第一开关控制信号的控制，来控制所述信号输出电路与所述第二电源端之间的通断。
  12. 根据权利要求11所述的栅极驱动电路，其中，所述第一开关电路包括：第十一晶体管；
    所述第十一晶体管的控制极与第一开关控制端耦接，所述第十一晶体管的第一极与所述第二电源端耦接，所述第十一晶体管的第二极与所述信号输出电路耦接。
  13. 根据权利要求3至10中任一所述的栅极驱动电路，其中，在所述倍频控制电路中，位于第一级的第二移位寄存器配置有第一开关电路，所述第一开关电路设置在所述第二控制电路与所述第二时钟信号端之间，配置为响应于所述第一开关控制端所提供第一开关控制信号的控制，来控制所述第二控制电路与所述第二时钟信号端之间的通断。
  14. 根据权利要求13所述的栅极驱动电路，其中，所述第一开关电路包括：第十一晶体管；
    所述第十一晶体管的控制极与第一开关控制端耦接，所述第十一晶体管的第一极与所述第二时钟信号端耦接，所述第十一晶体管的第二极与所述第二控制电路耦接。
  15. 根据权利要求3至10中任一所述的栅极驱动电路，其中，在所 述倍频控制电路中，位于第一级的第二移位寄存器配置有第一开关电路，所述第一开关电路设置在所述信号写入电路与所述信号输入端之间且与第一开关控制端耦接，配置为响应于所述第一开关控制端所提供第一开关控制信号的控制，来控制所述信号写入电路与所述信号输入端之间的通断。
  16. 根据权利要求15所述的栅极驱动电路，其中，所述第一开关电路包括：第十一晶体管；
    所述第十一晶体管的控制极与第一开关控制端耦接，所述第十一晶体管的第一极与所述信号输入端耦接，所述第十一晶体管的第二极与所述信号写入电路耦接。
  17. 根据权利要求15或16所述的栅极驱动电路，其中，在所述倍频控制电路中，位于第一级的第二移位寄存器配置有第一供电电路；
    所述第一供电电路与所述信号写入电路、所述第一开关电路、所述第一电源端和第二开关控制端耦接，配置为响应于所述第二开关控制端所提供的所述第二开关控制信号的控制，向所述信号写入电路写入所述第一工作电压。
  18. 根据权利要求17所述的栅极驱动电路，其中，所述第一供电电路包括：第十四晶体管；
    所述第十四晶体管的控制极与所述第二开关控制端耦接，所述第十四晶体管的第一极与所述第一电源端耦接，所述第十四晶体管的第二极与所述信号写入电路和所述第一开关电路耦接。
  19. 根据权利要求11至18中任一所述的栅极驱动电路，其中，在 所述倍频控制电路中，位于第一级的第二移位寄存器配置有第二供电电路；
    所述第二供电电路与所述第一电源端、位于第一级的第二移位寄存器配的信号输出端和第二开关控制端耦接，配置为响应于所述第二开关控制端所提供的所述第二开关控制信号的控制，向所述第二移位寄存器的信号输出端写入所述第一工作电压。
  20. 根据权利要求19所述的栅极驱动电路，其中，所述第二供电电路包括：第十五晶体管；
    所述第十五晶体管的控制极与所述第二开关控制端耦接，所述第十五晶体管的第一极与所述第一电源端耦接，所述第十五晶体管的第二极与位于第一级的第二移位寄存器配的信号输出端耦接。
  21. 根据权利要求17至20中任一所述的栅极驱动电路，其中，还包括：反相电路，所述反相电路的输入端与所述第一开关控制端耦接，所述反相电路的输出端与所述第二开关控制端耦接。
  22. 一种显示基板，其中，包括：如上述权利要求1-21中任一所述的栅极驱动电路和位于显示区域内的多条栅线；
    所述栅线与所述栅极驱动电路内对应的一个第一移位寄存器的信号输出端耦接。
  23. 一种显示装置，其中，包括：如上述权利要求22所述的显示基板和与所述显示基板相对设置的对置基板。
  24. 一种栅极驱动方法，其中，基于上述权利要求1-21中任一所述 的栅极驱动电路，所述栅极驱动方法包括：
    响应于所述输出控制信号，所述有效输出电路中的各级移位寄存器依次输出扫描信号，所述倍频控制电路经过预设时长后向所述有效输出电路中位于第一级的第一移位寄存器的所述第二信号输入端提供倍频控制信号；
    响应于所述倍频控制信号，所述有效输出电路中的各级移位寄存器依次输出扫描信号。
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