WO2018228042A1 - 移位寄存器单元、驱动方法、栅极驱动电路和显示装置 - Google Patents

移位寄存器单元、驱动方法、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2018228042A1
WO2018228042A1 PCT/CN2018/082997 CN2018082997W WO2018228042A1 WO 2018228042 A1 WO2018228042 A1 WO 2018228042A1 CN 2018082997 W CN2018082997 W CN 2018082997W WO 2018228042 A1 WO2018228042 A1 WO 2018228042A1
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Prior art keywords
output
pull
node
shift register
transistor
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PCT/CN2018/082997
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English (en)
French (fr)
Inventor
胡胜华
聂春扬
闫冰冰
朱立新
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US16/320,753 priority Critical patent/US10930189B2/en
Publication of WO2018228042A1 publication Critical patent/WO2018228042A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register unit, a driving method, a gate driving circuit, and a display device.
  • the structure of the shift register unit in the related art is a 4T1C structure, and its basic structure is simple, including a start signal input transistor, an output transistor and two reset transistors, plus a bootstrap capacitor, and a shift register unit in the related art. It is possible to realize that the gate driving signal outputs an effective level only for a certain time, and outputs an inactive level for the rest of the time, but due to the coupling effect of the gate of the TFT (Thin Film Transistor) device and its source and drain (in the related art) In the middle, the gate of the output transistor is connected to a clock signal input terminal. Therefore, since the clock signal input terminal is constantly outputting high and low levels, all gate drive signal outputs will generate jitter. 4T1C shift register in the related art The gate drive signal outputted by the unit will jitter with the change of the clock signal during the invalid period, so the stability of the gate drive signal is very poor.
  • the present disclosure provides a shift register unit including a driving module, a storage capacitor module, an output module, and a reset module, wherein
  • the driving module is respectively connected to the start end, the pull-up node, the pull-down node, the first level input end, and the set signal input end, and is configured to control whether the pull-up node and the pull-up node are under the control of the start end Determining a set signal input terminal to connect and controlling whether the pulldown node is connected to the first level input terminal;
  • the output module is respectively connected to the pull-up node, the pull-down node, the first level input end, the output signal providing end, and the local-level gate driving signal output end, respectively, for the pull-up node Controlling whether the output of the gate drive signal of the current stage is connected to the output signal supply end, and controlling whether the output of the gate drive signal of the current stage is different from the first level under the control of the pull-down node Input connection
  • the storage capacitor module is connected between the pull-up node and the output of the gate drive signal of the current stage;
  • the reset module is respectively connected to the reset end, the second level input end, the pull-up node, the pull-down node, and the first level input end, and is configured to control the pull-up under the control of the reset end Whether the node is connected to the first level input and controls whether the pull-down node is connected to the second level input.
  • the driving module includes a first driving transistor and a second driving transistor
  • a gate of the first driving transistor is connected to the start end, a first pole of the first driving transistor is connected to the pull-up node, and a second pole of the first driving transistor and the set signal Input connection
  • a gate of the second driving transistor is connected to the start end, a first pole of the second driving transistor is connected to the first level input terminal, a second pole of the second driving transistor is Pull down the node connection.
  • the reset module includes a first reset transistor and a second reset transistor
  • a gate of the first reset transistor is connected to the reset terminal, a first pole of the first reset transistor is connected to the pull-down node, and a second pole of the first reset transistor is opposite to the second level Input connection
  • a gate of the second reset transistor is connected to the reset terminal, a first pole of the second reset transistor is connected to the pull-up node, and a second pole of the second reset transistor is connected to the first Flat input connection.
  • the output module includes a first output transistor and a second output transistor
  • a gate of the first output transistor is connected to the pull-down node, a first pole of the first output transistor is connected to the first level input terminal, a second pole of the first output transistor is The gate drive signal output end of the current stage is connected;
  • a gate of the second output transistor is connected to the pull-up node, a first pole of the second output transistor is connected to the output terminal of the gate driving signal, and a second pole of the second output transistor Connected to the output signal supply terminal.
  • the first driving transistor, the second driving transistor, the first output transistor, the second output transistor, the first reset transistor, and the second reset transistor are all n-type transistors;
  • the first driving transistor, the second driving transistor, the first output transistor, the second output transistor, the first reset transistor, and the second reset transistor are all p-type transistors.
  • the storage capacitor module includes a storage capacitor; a first end of the storage capacitor is coupled to the pull-up node, and a second end of the storage capacitor is coupled to the gate drive signal output terminal of the current stage.
  • the present disclosure also provides a driving method of a shift register unit, which is applied to the above shift register unit, and the driving method includes: in each display period,
  • the set signal input end and the start end both input a second level, and the output signal supply end inputs a first level.
  • the driving module controls the pull-up node and the set
  • the signal input terminal is connected and controls the pull-down node to be connected to the first level input terminal such that the potential of the pull-up node is at a second level and the potential of the pull-down node is at a first level, and the pull-up node is
  • the output module controls the output signal output end of the current stage to be connected with the output signal supply end, so that the output signal output end of the current stage outputs the first level;
  • the set signal input end and the start end both input a first level, and the output signal supply end inputs a second level.
  • the drive module controls to disconnect the pull-up node and the set a connection between the bit signal input terminals and controlling a connection between the pull-down node and the first level input terminal, and the storage capacitor module bootstraps the potential of the pull-up node under the control of the pull-up node
  • the output module continues to control the output of the driving signal of the current stage to be connected with the output signal providing end, so that the output of the gate driving signal of the current stage outputs the second level;
  • the reset terminal inputs a second level
  • the reset module controls the pull-up node to connect with the first level input terminal and controls the pull-down node to connect with the second level input terminal. So that the potential of the pull-up node is at a first level and the potential of the pull-down node is a second level; under the control of the pull-up node, the output module controls to turn off the gate drive signal output of the current stage a connection between the end and the output signal providing end; under the control of the pull-down node, the output module controls the output of the gate driving signal of the current stage to be connected with the first level input end, to The output of the gate drive signal of the current stage is reset.
  • the present disclosure also provides a gate driving circuit comprising a plurality of stages of the above shift register unit;
  • stage gate signal output of each stage of the shift register unit is coupled to the start of an adjacent next stage shift register.
  • the set signal input end of the 4th-3th stage shift register unit is connected to the first clock signal input end, and the output signal supply end of the 4th-3th stage shift register unit is connected to the second clock signal input end.
  • a reset end of the 4th-3th stage shift register unit is connected to the third clock signal input end;
  • the set signal input end of the 4n-2 stage shift register unit is connected to the second clock signal input end, and the output signal supply end of the 4th-2nd stage shift register unit is connected to the third clock signal input end, 4th- The reset end of the 2-stage shift register unit is connected to the fourth clock signal input end;
  • the set signal input end of the 4n-1th shift register unit is connected to the third clock signal input end, and the output signal supply end of the 4n-1th stage shift register unit is connected to the fourth clock signal input end, 4n-
  • the reset end of the 1-stage shift register unit is connected to the first clock signal input end;
  • the set signal input end of the 4nth stage shift register unit is connected to the fourth clock signal input end, and the output signal supply end of the 4nth stage shift register unit is connected to the first clock signal input end, and the 4nth stage shift register unit is connected.
  • the reset end is connected to the second clock signal input end;
  • n is a positive integer, and 4n is less than or equal to the number of stages of the shift register unit included in the gate driving circuit;
  • the duty ratios of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are both 1/4, the period of the first clock signal, the period of the second clock signal, the number The period of the three clock signals and the period of the fourth clock signal are both T;
  • the second clock signal is delayed by T/4 from the first clock signal; the third clock signal is delayed by T/4 from the second clock signal; the fourth clock signal is delayed by T/4 from the third clock signal.
  • the present disclosure also provides a display device including the above-described gate drive circuit.
  • FIG. 1 is a structural diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 2 is a circuit diagram of a specific embodiment of a shift register unit of the present disclosure
  • FIG. 3 is a timing chart showing the operation of a specific embodiment of the shift register unit shown in FIG. 2 of the present disclosure
  • Figure 4 is a timing diagram of four clock signals
  • FIG. 5 is a structural diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other device having the same characteristics.
  • one of the poles is referred to as a first pole, and the other pole is referred to as a second pole.
  • the first pole may be a drain
  • the second pole may be a source
  • the first pole may be a source
  • the second pole may be a drain.
  • the shift register unit of the embodiment of the present disclosure includes a driving module 11 , an output module 12 , a reset module 13 , and a storage capacitor module 14 .
  • the driving module 11 is respectively connected to the starting end STV, the pull-up node PU, the pull-down node PD, the first level input terminal V1 and the set signal input terminal SET.
  • the driving module 11 is configured to control, according to the start end STV, whether the pull-up node PU is connected to the set signal input terminal SET and control whether the pull-down node PD is related to the first level The input terminal V1 is connected.
  • the output module 12 is respectively connected to the pull-up node PU, the pull-down node PD, the first level input terminal V1, the output signal providing terminal OP, and the local-level gate driving signal output terminal GOUT.
  • the output module 12 is configured to control whether the local gate drive signal output terminal GOUT is connected to the output signal supply terminal OP under the control of the pull-up node PU, and is controlled under the control of the pull-down node PD. Whether the current gate drive signal output terminal GOUT is connected to the first level input terminal V1.
  • the storage capacitor module 14 is connected between the pull-up node PU and the local gate drive signal output terminal GOUT.
  • the reset module 13 is connected to the reset terminal RESET, the second level input terminal V2, the pull-up node PU, the pull-down node PD, and the first level input terminal V1, respectively.
  • the reset module 13 is configured to control whether the pull-up node PU is connected to the first level input terminal V1 under the control of the reset terminal RESET, and control whether the pull-down node PD is related to the second level Input V2 is connected.
  • the shift register unit of the embodiment of the present disclosure includes an output module that controls whether the gate drive signal output terminal of the current stage is connected to the output signal supply end under the control of the pull-up node, so that the gate drive signal output jitter does not occur.
  • the shift register unit according to the embodiment of the present disclosure can realize a stable high-quality gate driving signal in a case where a TFT (Thin Film Transistor) device is used, and a narrow bezel can be realized.
  • TFT Thin Film Transistor
  • the first level input by the first level input terminal V1 may be a low level
  • the second level input by the second level input terminal V2 may be a high level.
  • the specific level values of the above two levels may be changed according to actual conditions, and are not limited to the level values exemplified above.
  • the shift register unit of the embodiment of the present disclosure includes: a driving module, an output module, and a reset module.
  • the driving module is configured to input a set signal to the output module, and the output module is configured to output a final gate driving signal to implement channel opening of an AA (Active Area) TFT device.
  • the reset module is configured to reset the gate driving signal to implement channel closing of the AA region TFT device.
  • the driving module may include a first driving transistor and a second driving transistor.
  • a gate of the first driving transistor is connected to the start end, a first pole of the first driving transistor is connected to the pull-up node, and a second pole of the first driving transistor and the set signal The input is connected.
  • a gate of the second driving transistor is connected to the start end, a first pole of the second driving transistor is connected to the first level input terminal, a second pole of the second driving transistor is Pull down the node connection.
  • the reset module may include a first reset transistor and a second reset transistor.
  • a gate of the first reset transistor is connected to the reset terminal, a first pole of the first reset transistor is connected to the pull-down node, and a second pole of the first reset transistor is opposite to the second level The input is connected.
  • a gate of the second reset transistor is connected to the reset terminal, a first pole of the second reset transistor is connected to the pull-up node, and a second pole of the second reset transistor is connected to the first Flat input connection.
  • the output module includes a first output transistor and a second output transistor.
  • a gate of the first output transistor is connected to the pull-down node, a first pole of the first output transistor is connected to the first level input terminal, a second pole of the first output transistor is The gate drive signal output of this stage is connected.
  • a gate of the second output transistor is connected to the pull-up node, a first pole of the second output transistor is connected to the output terminal of the gate driving signal, and a second pole of the second output transistor Connected to the output signal supply terminal.
  • the first driving transistor, the second driving transistor, the first output transistor, the second output transistor, the first reset transistor, and the second reset transistor may all be n-type a transistor; or, the first driving transistor, the second driving transistor, the first output transistor, the second output transistor, the first reset transistor, and the second reset transistor may both be p-type Transistor.
  • all of the transistors included in the shift register unit of the embodiment of the present disclosure are n-type or both p-type, which can reduce the number of masks used in the process, and the cost is more easily reduced.
  • the storage capacitor module may include a storage capacitor.
  • the first end of the storage capacitor is connected to the pull-up node, and the second end of the storage capacitor is connected to the output gate output signal of the local stage.
  • a specific embodiment of the shift register unit of the present disclosure includes a driving module 11, an output module 12, a reset module 13, and a storage capacitor module 14.
  • the driving module 11 includes a first driving transistor T3 and a second driving transistor T4.
  • a gate of the first driving transistor T3 is connected to the start terminal STV, a drain of the first driving transistor T3 is connected to the pull-up node PU, a source of the first driving transistor T3 is The set signal input terminal SET is connected. ;
  • the gate of the second driving transistor T4 is connected to the start terminal STV, the drain of the second driving transistor T4 is connected to the low level input terminal of the input low level VGL, and the second driving transistor T4 The source is connected to the pulldown node PD.
  • the reset module 13 includes a first reset transistor T5 and a second reset transistor T6.
  • a gate of the first reset transistor T5 is connected to the reset terminal RESET, a drain of the first reset transistor T5 is connected to the pull-down node PD, and a drain of the first reset transistor T5 is high with an input.
  • the high level input of the flat VGH is connected.
  • a gate of the second reset transistor T6 is connected to the reset terminal RESET, a drain of the second reset transistor T6 is connected to the pull-up node PU, and a source and an input of the second reset transistor T6 are low.
  • the low level input of level VGL is connected.
  • the output module 12 includes a first output transistor T1 and a second output transistor T2.
  • the gate of the first output transistor T1 is connected to the pull-down node PD, and the drain of the first output transistor T1 is connected to a low-level input terminal of the input low level VGL, the first output transistor T1
  • the source is connected to the gate drive signal output terminal GOUT of the current stage.
  • a gate of the second output transistor T2 is connected to the pull-up node PU, a drain of the second output transistor T2 is connected to the gate driving signal output terminal GOUT of the current stage, and the second output transistor T2 The source is connected to the output signal supply terminal OP.
  • the storage capacitor module 14 includes a storage capacitor Cs.
  • the first end of the storage capacitor Cs is connected to the pull-up node PU, and the second end of the storage capacitor Cs and the gate drive signal output terminal GOUT of the local gate connection.
  • T1, T2, T3, T4, T5 and T6 are all n-type transistors.
  • the above transistor can also be replaced with a p-type transistor, and only the timing of controlling the control signal of the transistor can be changed accordingly.
  • the set signal input terminal SET is connected to the first clock signal input terminal CKV1 (CKV1 is not shown in FIG. 2), and the output signal is provided.
  • the terminal OP is connected to the second clock signal input terminal CKV2 (CKV2 is not shown in FIG. 2), and the reset terminal RESET is connected to the third clock signal input terminal CKV3 (CKV3 is not shown in FIG. 2);
  • the first clock signal input by the first clock signal input terminal CKV1, the second clock signal input by the second clock signal input terminal CKV2, and the third clock signal input by the third clock signal input terminal CKV3 The duty ratio is 1/4, and the period of the first clock signal, the period of the second clock signal, and the period of the third clock signal are both T.
  • the second clock signal is delayed by T/4 from the first clock signal;
  • the third clock signal is delayed by T/4 from the second clock signal;
  • the fourth clock signal is delayed by T/4 from the third clock signal.
  • the specific embodiment of the shift register unit shown in FIG. 2 of the present disclosure is in operation, during each display period,
  • the first clock signal input terminal CKV1 and the start terminal STV both input a high level
  • the second clock signal input terminal CKV2 and the third clock signal input terminal CKV3 both input a low level
  • both T3 and T4 are turned on, so that the pull-up node PU is connected with the first clock signal input terminal CKV1 and the pull-down node PD is connected with the low-level input terminal of the input low level VGL, so that the pull-up is performed
  • the potential of the node PU is at a high level and the potential of the pull-down node PD is a low level; under the control of the pull-down node PD, T1 is turned off, and under the control of the pull-up node PU, T2 is turned on to control the level
  • the driving signal output terminal GOUT is connected to the second clock signal input terminal CKV2, so that the current driving signal output terminal GOUT outputs a low level; under the control of the third clock signal input
  • the first clock signal input terminal CKV1, the start terminal STV and the third clock signal input terminal CKV3 are both input with a low level, and the second clock signal input terminal CKV2 is input with a high level; at the start end of the STV control
  • both T3 and T4 are turned off to control the connection between the pull-up node PU and the first clock signal input terminal CKV1 and control the disconnection of the pull-down node PD and the low-level input terminal of the input low level VGL
  • the storage capacitor Cs bootstraps the potential of the pull-up node PU, and under the control of the pull-up node PU, T2 continues to open to control the driving signal output terminal GOUT and the second clock signal input of the current stage.
  • the terminal CKV2 is connected such that the driving signal output terminal GOUT of the present stage outputs a high level; under the control of the third clock signal input terminal CKV3, both T5 and T6 are turned off.
  • the third clock signal input terminal CKV3 inputs a high level, and under the control of the third clock signal input terminal CKV3, both T5 and T6 are turned on to control the pull-up node PU and the input low level VGL.
  • the low-level input terminal is connected, and the pull-down node PD is controlled to be connected to the high-level input terminal of the input high-level VGH, so that the potential of the pull-up node PU is low level and the potential of the pull-down node PD is high level
  • T1 is turned off to control disconnection between the gate drive signal output terminal GOUT of the current stage and the second clock signal input terminal CKV;
  • T1 is turned on to control the gate drive signal output terminal GOUT of the current stage to be connected with the low level input terminal of the input low level VGL to reset the gate drive signal output terminal GOUT of the current stage. Therefore, the gate drive signal output terminal GOUT of the current stage outputs a low level.
  • the specific embodiment of the shift register unit shown in FIG. 2 only needs to add two TFT devices, which can well solve the problem of gate drive signal output jitter, and at the same time, GOA (Gate On Array, the gate drive circuit disposed on the array substrate)
  • GOA Gate On Array, the gate drive circuit disposed on the array substrate
  • the voltage of the internal node of the architecture (the internal node refers to the pull-up node) is more stable, which solves the possibility of circuit misoperation of the shift register unit to some extent.
  • the specific embodiment of the shift register unit shown in FIG. 2 of the present disclosure is a 6T1C architecture, and the number of TFTs used is small, and a narrow bezel can be well realized.
  • the driving method of the shift register unit according to the embodiment of the present disclosure is applied to the above shift register unit, and the driving method includes: in each display period,
  • the set signal input end and the start end both input a second level, and the output signal supply end inputs a first level.
  • the driving module controls the pull-up node and the set
  • the signal input terminal is connected and controls the pull-down node to be connected to the first level input terminal such that the potential of the pull-up node is at a second level and the potential of the pull-down node is at a first level, and the pull-up node is
  • the output module controls the output signal output end of the current stage to be connected with the output signal supply end, so that the output signal output end of the current stage outputs the first level;
  • the set signal input end and the start end both input a first level, and the output signal supply end inputs a second level.
  • the drive module controls to disconnect the pull-up node and the set a connection between the bit signal input terminals and controlling a connection between the pull-down node and the first level input terminal, and the storage capacitor module bootstraps the potential of the pull-up node under the control of the pull-up node
  • the output module continues to control the output of the driving signal of the current stage to be connected with the output signal providing end, so that the output of the gate driving signal of the current stage outputs the second level;
  • the reset terminal inputs a second level
  • the reset module controls the pull-up node to connect with the first level input terminal and controls the pull-down node to connect with the second level input terminal. So that the potential of the pull-up node is at a first level and the potential of the pull-down node is a second level; under the control of the pull-up node, the output module controls to turn off the gate drive signal output of the current stage a connection between the end and the output signal providing end; under the control of the pull-down node, the output module controls the output of the gate driving signal of the current stage to be connected with the first level input end, to The output of the gate drive signal of the current stage is reset.
  • the driving method of the shift register unit according to the embodiment of the present disclosure is applied to the shift register unit described above, in each display period, in the initial stage, the driving module inputs a set signal to the output module; in the output stage, The output module outputs the final gate driving signal to realize channel opening of the TFT device in the AA (Active Area) area; in the reset phase, the reset module resets the gate driving signal to realize the channel closing of the TFT device in the AA area.
  • the gate driving circuit of the embodiment of the present disclosure includes a plurality of stages of the above shift register unit;
  • stage gate signal output of each stage of the shift register unit is coupled to the start of an adjacent next stage shift register.
  • the set signal input end of the 4th-3th stage shift register unit is connected to the first clock signal input end, and the 4th-3th stage shift is performed.
  • the output signal supply end of the register unit is connected to the second clock signal input end, and the reset end of the 4th-3th stage shift register unit is connected to the third clock signal input end;
  • the set signal input end of the 4n-2 stage shift register unit is connected to the second clock signal input end, and the output signal supply end of the 4th-2nd stage shift register unit is connected to the third clock signal input end, 4th- The reset end of the 2-stage shift register unit is connected to the fourth clock signal input end;
  • the set signal input end of the 4n-1th shift register unit is connected to the third clock signal input end, and the output signal supply end of the 4n-1th stage shift register unit is connected to the fourth clock signal input end, 4n-
  • the reset end of the 1-stage shift register unit is connected to the first clock signal input end;
  • the set signal input end of the 4nth stage shift register unit is connected to the fourth clock signal input end, and the output signal supply end of the 4nth stage shift register unit is connected to the first clock signal input end, and the 4nth stage shift register unit is connected.
  • the reset end is connected to the second clock signal input end;
  • n is a positive integer, and 4n is less than or equal to the number of stages of the shift register unit included in the gate driving circuit.
  • the duty ratios of the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 are both 1/4, and the period of the first clock signal CK1 is The period of the second clock signal CK2, the period of the third clock signal CK3, and the period of the fourth clock signal CK4 are both T.
  • the second clock signal CK2 is delayed by T/4 from the first clock signal CK1; the third clock signal CK3 is delayed by T/4 from the second clock signal CK2; the fourth clock signal CK4 is delayed by T/4 from the third clock signal CK3.
  • the gate drive circuit of the present disclosure will be described below by way of a specific embodiment.
  • a specific embodiment of the gate driving circuit of the present disclosure includes a first stage shift register unit GTIC1, a second stage shift register unit GTIC2, a third stage shift register unit GTIC3, and a fourth Stage shift register unit GTIC4.
  • This particular embodiment of the gate drive circuit of the present disclosure may include a plurality of stages of shift register units, and only the connection relationship of the four-stage shift register unit is shown in FIG. 5 for an example.
  • the start end of the first stage shift register unit GTIC1 is connected to the external start signal input terminal STV_IN, and the set signal input end of the first stage shift register unit GTIC1 is connected to the first clock signal input terminal CKV1.
  • the output signal providing end of the first stage shift register unit GTIC1 is connected to the second clock signal input end CKV2, and the reset end RESET of the first stage shift register unit GTIC1 is connected to the third clock signal input end CKV3;
  • the start end of the second stage shift register unit GTIC2 is connected to the first gate drive signal output terminal GOUT1 of the first stage shift register unit GTIC1, and the set signal input terminal and the second clock of the second stage shift register unit GTIC2
  • the signal input terminal CKV2 is connected, the output signal supply terminal of the second stage shift register unit GTIC2 is connected to the third clock signal input terminal CKV3, and the reset terminal of the second stage shift register unit GTIC2 is connected to the fourth clock signal input terminal CKV4;
  • the start end of the third stage shift register unit GTIC3 is connected to the second gate drive signal output terminal GOUT2 of the second stage shift register unit GTIC2, and the set signal input terminal and the third clock of the third stage shift register unit GTIC3
  • the signal input terminal CKV3 is connected, the output signal supply terminal of the third-stage shift register unit GTIC3 is connected to the fourth clock signal input terminal CKV4, and the reset terminal of the third-stage shift register unit GTIC3 is connected to the first clock signal input terminal CKV1;
  • the start end of the fourth stage shift register unit GTIC4 is connected to the third gate drive signal output terminal GOUT3 of the third stage shift register unit GTIC3, and the set signal input terminal and the fourth clock of the fourth stage shift register unit GTIC4
  • the signal input terminal CKV4 is connected
  • the output signal supply terminal of the fourth stage shift register unit GTIC4 is connected to the first clock signal input terminal CKV1
  • the reset terminal of the fourth stage shift register unit GTIC4 is connected to the second clock signal input terminal CKV2.
  • the STV is the start end of each stage of the shift register unit
  • the label SET is the set signal input end of each shift register unit
  • the label is OP.
  • the output signal supply end of the stage shift register unit, labeled as RESET is the reset end of each shift register unit
  • the label GOUT is the gate drive signal output end of each stage of the shift register unit of each stage;
  • the gate driving signal output end of the first stage shift register unit GTIC1 is connected to the first gate driving signal output terminal GOUT1;
  • the gate driving signal output end of the second stage shift register unit GTIC2 is connected to the second gate driving signal output terminal GOUT2;
  • the gate driving signal output end of the third stage shift register unit GTIC3 is connected to the third gate driving signal output terminal GOUT3;
  • the gate drive signal output terminal of the fourth stage shift register unit GTIC4 is connected to the fourth gate drive signal output terminal GOUT4.
  • the display device of the present disclosure includes a gate drive circuit thereon.
  • the display device provided in this embodiment may be any product or component having a display function, such as a display, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种移位寄存器单元、驱动方法、栅极驱动电路和显示装置。所述移位寄存器单元包括驱动模块(11)、存储电容模块(14)、输出模块(12)和复位模块(13)；所述驱动模块(11)在起始端的控制下，控制上拉节点是否与置位信号输入端连接并控制下拉节点是否与第一电平输入端连接；所述复位模块(13)在复位端的控制下，控制所述上拉节点是否与所述第一电平输入端连接，并控制所述下拉节点是否与第二电平输入端连接。

Description

移位寄存器单元、驱动方法、栅极驱动电路和显示装置
相关申请的交叉引用
本申请主张在2017年6月13日在中国提交的中国专利申请号No.201710441791.5的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器单元、驱动方法、栅极驱动电路和显示装置。
背景技术
相关技术中的移位寄存器单元的架构为4T1C结构，其基本结构简单，包括一个起始信号输入晶体管，一个输出晶体管以及两个复位晶体管，外加一个自举电容，相关技术中的移位寄存器单元可以实现栅极驱动信号只在特定时间内输出有效电平，其余时间一直输出无效电平，但由于TFT(Thin FilmTransistor，薄膜晶体管)器件的栅极和其源漏极的耦合效应(在相关技术中中，输出晶体管的栅极与一时钟信号输入端连接，因此由于该时钟信号输入端是不断间隔输出高低电平，所有栅极驱动信号输出会产生抖动)，相关技术中的4T1C移位寄存器单元输出的栅极驱动信号在无效期内会随着时钟信号的变化出现抖动，所以栅极驱动信号的稳定性很差。
发明内容
本公开提供了一种移位寄存器单元，包括驱动模块、存储电容模块、输出模块和复位模块，其中，
所述驱动模块分别与起始端、上拉节点、下拉节点、第一电平输入端和置位信号输入端连接，用于在所述起始端的控制下，控制所述上拉节点是否与所述置位信号输入端连接并控制所述下拉节点是否与所述第一电平输入端连接；
所述输出模块分别与所述上拉节点、所述下拉节点、所述第一电平输入 端、输出信号提供端和本级栅极驱动信号输出端连接，用于在所述上拉节点的控制下控制所述本级栅极驱动信号输出端是否与所述输出信号提供端连接，在所述下拉节点的控制下控制所述本级栅极驱动信号输出端是否与所述第一电平输入端连接；
所述存储电容模块连接于所述上拉节点和所述本级栅极驱动信号输出端之间；
所述复位模块分别与复位端、第二电平输入端、所述上拉节点、所述下拉节点和所述第一电平输入端连接，用于在复位端的控制下，控制所述上拉节点是否与所述第一电平输入端连接，并控制所述下拉节点是否与所述第二电平输入端连接。
实施时，所述驱动模块包括第一驱动晶体管和第二驱动晶体管；
所述第一驱动晶体管的栅极与所述起始端连接，所述第一驱动晶体管的第一极与所述上拉节点连接，所述第一驱动晶体管的第二极与所述置位信号输入端连接；
所述第二驱动晶体管的栅极与所述起始端连接，所述第二驱动晶体管的第一极与所述第一电平输入端连接，所述第二驱动晶体管的第二极与所述下拉节点连接。
实施时，所述复位模块包括第一复位晶体管和第二复位晶体管；
所述第一复位晶体管的栅极与所述复位端连接，所述第一复位晶体管的第一极与所述下拉节点连接，所述第一复位晶体管的第二极与所述第二电平输入端连接；
所述第二复位晶体管的栅极与所述复位端连接，所述第二复位晶体管的第一极与所述上拉节点连接，所述第二复位晶体管的第二极与所述第一电平输入端连接。
实施时，所述输出模块包括第一输出晶体管和第二输出晶体管；
所述第一输出晶体管的栅极与所述下拉节点连接，所述第一输出晶体管的第一极与所述第一电平输入端连接，所述第一输出晶体管的第二极与所述本级栅极驱动信号输出端连接；
所述第二输出晶体管的栅极与所述上拉节点连接，所述第二输出晶体管 的第一极与所述本级栅极驱动信号输出端连接，所述第二输出晶体管的第二极与输出信号提供端连接。
实施时，所述第一驱动晶体管、所述第二驱动晶体管、所述第一输出晶体管、所述第二输出晶体管、所述第一复位晶体管和所述第二复位晶体管都为n型晶体管；或者，所述第一驱动晶体管、所述第二驱动晶体管、所述第一输出晶体管、所述第二输出晶体管、所述第一复位晶体管和所述第二复位晶体管都为p型晶体管。
实施时，所述存储电容模块包括存储电容；所述存储电容的第一端与所述上拉节点连接，所述存储电容的第二端与所述本级栅极驱动信号输出端连接。
本公开还提供了一种移位寄存器单元的驱动方法，应用于上述的移位寄存器单元，所述驱动方法包括：在每一显示周期内，
在起始阶段，置位信号输入端和起始端都输入第二电平，输出信号提供端输入第一电平，在所述起始端的控制下，驱动模块控制上拉节点与所述置位信号输入端连接并控制下拉节点与第一电平输入端连接，以使得所述上拉节点的电位为第二电平并所述下拉节点的电位为第一电平，在所述上拉节点的控制下，输出模块控制本级驱动信号输出端与输出信号提供端连接，以使得所述本级驱动信号输出端输出第一电平；
在输出阶段，置位信号输入端和起始端都输入第一电平，输出信号提供端输入第二电平，在所述起始端的控制下，驱动模块控制断开上拉节点与所述置位信号输入端之间的连接并控制断开下拉节点与第一电平输入端之间的连接，存储电容模块自举拉升所述上拉节点的电位，在所述上拉节点的控制下，输出模块继续控制本级驱动信号输出端与输出信号提供端连接，以使得本级栅极驱动信号输出端输出第二电平；
在复位阶段，复位端输入第二电平，在复位端的控制下，复位模块控制所述上拉节点与第一电平输入端连接并控制所述下拉节点与所述第二电平输入端连接，以使得上拉节点的电位为第一电平而所述下拉节点的电位为第二电平；在所述上拉节点的控制下，输出模块控制断开所述本级栅极驱动信号输出端与所述输出信号提供端之间的连接；在所述下拉节点的控制下，所述 输出模块控制所述本级栅极驱动信号输出端与所述第一电平输入端连接，以对所述本级栅极驱动信号输出端进行复位。
本公开还提供了一种栅极驱动电路，包括多级上述的移位寄存器单元；
除了最后一级移位寄存器单元之外，每一级所述移位寄存器单元的本级栅极信号输出端与相邻下一级移位寄存器的起始端连接。
实施时，第4n-3级移位寄存器单元的置位信号输入端与第一时钟信号输入端连接，第4n-3级移位寄存器单元的输出信号提供端与第二时钟信号输入端连接，第4n-3级移位寄存器单元的复位端与第三时钟信号输入端连接；
第4n-2级移位寄存器单元的置位信号输入端与第二时钟信号输入端连接，第4n-2级移位寄存器单元的输出信号提供端与第三时钟信号输入端连接，第4n-2级移位寄存器单元的复位端与第四时钟信号输入端连接；
第4n-1级移位寄存器单元的置位信号输入端与第三时钟信号输入端连接，第4n-1级移位寄存器单元的输出信号提供端与第四时钟信号输入端连接，第4n-1级移位寄存器单元的复位端与第一时钟信号输入端连接；
第4n级移位寄存器单元的置位信号输入端与第四时钟信号输入端连接，第4n级移位寄存器单元的输出信号提供端与第一时钟信号输入端连接，第4n级移位寄存器单元的复位端与第二时钟信号输入端连接；
n为正整数，4n小于或等于所述栅极驱动电路包括的移位寄存器单元的级数；
第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号的占空比都为1/4，所述第一时钟信号的周期、所述第二时钟信号的周期、所述第三时钟信号的周期和所述第四时钟信号的周期都为T；
第二时钟信号比第一时钟信号延迟T/4；第三时钟信号比第二时钟信号延迟T/4；第四时钟信号比第三时钟信号延迟T/4。
本公开还提供了一种显示装置，包括上述的栅极驱动电路。
附图说明
图1是本公开实施例所述的移位寄存器单元的结构图；
图2是本公开所述的移位寄存器单元的一具体实施例的电路图；
图3是本公开如图2所示的移位寄存器单元的具体实施例的工作时序图；
图4是四个时钟信号的时序图；
图5是本公开实施例所述的栅极驱动电路的结构图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。在实际操作时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
如图1所示，本公开实施例所述的移位寄存器单元，包括驱动模块11、输出模块12、复位模块13和存储电容模块14。
其中，所述驱动模块11分别与起始端STV、上拉节点PU、下拉节点PD、第一电平输入端V1和置位信号输入端SET连接。所述驱动模块11用于在所述起始端STV的控制下，控制所述上拉节点PU是否与所述置位信号输入端SET连接并控制所述下拉节点PD是否与所述第一电平输入端V1连接。
所述输出模块12分别与所述上拉节点PU、所述下拉节点PD、所述第一电平输入端V1、输出信号提供端OP和本级栅极驱动信号输出端GOUT连接。所述输出模块12用于在所述上拉节点PU的控制下控制所述本级栅极驱动信号输出端GOUT是否与所述输出信号提供端OP连接，在所述下拉节点PD的控制下控制所述本级栅极驱动信号输出端GOUT是否与所述第一电平输入端V1连接。
所述存储电容模块14连接于所述上拉节点PU和所述本级栅极驱动信号输出端GOUT之间。
所述复位模块13分别与复位端RESET、第二电平输入端V2、所述上拉 节点PU、所述下拉节点PD和所述第一电平输入端V1连接。所述复位模块13用于在复位端RESET的控制下，控制所述上拉节点PU是否与所述第一电平输入端V1连接，并控制所述下拉节点PD是否与所述第二电平输入端V2连接。
本公开实施例所述的移位寄存器单元包括的输出模块是在上拉节点的控制下控制本级栅极驱动信号输出端是否与输出信号提供端连接，从而不会发生栅极驱动信号输出抖动的问题。本公开实施例所述的移位寄存器单元能够实现采用较少的TFT(Thin Film Transistor，薄膜晶体管)器件的情况下获得稳定高质的栅极驱动信号，能够实现窄边框。
具体的，所述第一电平输入端V1输入的第一电平可以为低电平，所述第二电平输入端V2输入的第二电平可以为高电平。在实际操作时，以上两个电平的具体电平值可以根据实际情况改变，并不限定于以上所例举的电平值。
本公开实施例所述的移位寄存器单元包括：驱动模块、输出模块和复位模块。其中，所述驱动模块用于将置位信号输入到所述输出模块；所述输出模块用于输出最终的栅极驱动信号，实现AA(Active Area，有效显示)区TFT器件沟道开启。所述复位模块用于复位栅极驱动信号，实现AA区TFT器件沟道关闭。
具体的，所述驱动模块可以包括第一驱动晶体管和第二驱动晶体管。
所述第一驱动晶体管的栅极与所述起始端连接，所述第一驱动晶体管的第一极与所述上拉节点连接，所述第一驱动晶体管的第二极与所述置位信号输入端连接。
所述第二驱动晶体管的栅极与所述起始端连接，所述第二驱动晶体管的第一极与所述第一电平输入端连接，所述第二驱动晶体管的第二极与所述下拉节点连接。
具体的，所述复位模块可以包括第一复位晶体管和第二复位晶体管。
所述第一复位晶体管的栅极与所述复位端连接，所述第一复位晶体管的第一极与所述下拉节点连接，所述第一复位晶体管的第二极与所述第二电平输入端连接。
所述第二复位晶体管的栅极与所述复位端连接，所述第二复位晶体管的 第一极与所述上拉节点连接，所述第二复位晶体管的第二极与所述第一电平输入端连接。
具体的，所述输出模块包括第一输出晶体管和第二输出晶体管。
所述第一输出晶体管的栅极与所述下拉节点连接，所述第一输出晶体管的第一极与所述第一电平输入端连接，所述第一输出晶体管的第二极与所述本级栅极驱动信号输出端连接。
所述第二输出晶体管的栅极与所述上拉节点连接，所述第二输出晶体管的第一极与所述本级栅极驱动信号输出端连接，所述第二输出晶体管的第二极与输出信号提供端连接。
可选的，所述第一驱动晶体管、所述第二驱动晶体管、所述第一输出晶体管、所述第二输出晶体管、所述第一复位晶体管和所述第二复位晶体管可以都为n型晶体管；或者，所述第一驱动晶体管、所述第二驱动晶体管、所述第一输出晶体管、所述第二输出晶体管、所述第一复位晶体管和所述第二复位晶体管可以都为p型晶体管。
可选地，本公开实施例所述的移位寄存器单元包括的所有的晶体管都为n型或都为p型，可以减少制程中用到的mask(掩膜)数目，更容易降低成本。
具体的，所述存储电容模块可以包括存储电容。；所述存储电容的第一端与所述上拉节点连接，所述存储电容的第二端与所述本级栅极驱动信号输出端连接。
下面通过一具体实施例来说明本公开所述的移位寄存器单元。
如图2所示，本公开所述的移位寄存器单元的一具体实施例包括驱动模块11、输出模块12、复位模块13和存储电容模块14。
所述驱动模块11包括第一驱动晶体管T3和第二驱动晶体管T4。
所述第一驱动晶体管T3的栅极与所述起始端STV连接，所述第一驱动晶体管T3的漏极与所述上拉节点PU连接，所述第一驱动晶体管T3的源极与所述置位信号输入端SET连接。；
所述第二驱动晶体管T4的栅极与所述起始端STV连接，所述第二驱动晶体管T4的漏极与输入低电平VGL的低电平输入端连接，所述第二驱动晶 体管T4的源极与所述下拉节点PD连接。
所述复位模块13包括第一复位晶体管T5和第二复位晶体管T6。
所述第一复位晶体管T5的栅极与所述复位端RESET连接，所述第一复位晶体管T5的漏极与所述下拉节点PD连接，所述第一复位晶体管T5的漏极与输入高电平VGH的高电平输入端连接。
所述第二复位晶体管T6的栅极与所述复位端RESET连接，所述第二复位晶体管T6的漏极与所述上拉节点PU连接，所述第二复位晶体管T6的源极与输入低电平VGL的低电平输入端连接。
所述输出模块12包括第一输出晶体管T1和第二输出晶体管T2。
所述第一输出晶体管T1的栅极与所述下拉节点PD连接，所述第一输出晶体管T1的漏极与输入低电平VGL的低电平输入端连接，所述第一输出晶体管T1的源极与所述本级栅极驱动信号输出端GOUT连接。；
所述第二输出晶体管T2的栅极与所述上拉节点PU连接，所述第二输出晶体管T2的漏极与所述本级栅极驱动信号输出端GOUT连接，所述第二输出晶体管T2的源极与输出信号提供端OP连接。
所述存储电容模块14包括存储电容Cs，所述存储电容Cs的第一端与所述上拉节点PU连接，所述存储电容Cs的第二端与所述本级栅极驱动信号输出端GOUT连接。
在如图2所示的移位寄存器单元的具体实施例中，T1、T2、T3、T4、T5和T6都为n型晶体管。但是在实际操作时，如上晶体管也可以被替换为p型晶体管，只需相应改变控制该晶体管的控制信号的时序即可。
在具体实施时，在如图2所示的移位寄存器单元的具体实施例中，置位信号输入端SET与第一时钟信号输入端CKV1(图2中未示出CKV1)连接，输出信号提供端OP与第二时钟信号输入端CKV2(图2中未示出CKV2)连接，复位端RESET与第三时钟信号输入端CKV3(图2中未示出CKV3)连接；
如图3所示，由第一时钟信号输入端CKV1输入的第一时钟信号、由第二时钟信号输入端CKV2输入的第二时钟信号和由第三时钟信号输入端CKV3输入的第三时钟信号的占空比都为1/4，所述第一时钟信号的周期、所 述第二时钟信号的周期和所述第三时钟信号的周期都为T。第二时钟信号比第一时钟信号延迟T/4；第三时钟信号比第二时钟信号延迟T/4；第四时钟信号比第三时钟信号延迟T/4。
如图3所示，本公开如图2所示的移位寄存器单元的具体实施例在工作时，在每一显示周期，
在起始阶段S1，第一时钟信号输入端CKV1和起始端STV都输入高电平，第二时钟信号输入端CKV2和第三时钟信号输入端CKV3都输入低电平；在所述起始端STV的控制下，T3和T4都打开，以使得上拉节点PU与第一时钟信号输入端CKV1连接并使得下拉节点PD与输入低电平VGL的低电平输入端连接，以使得所述上拉节点PU的电位为高电平并所述下拉节点PD的电位为低电平；在下拉节点PD的控制下，T1关闭，在所述上拉节点PU的控制下，T2打开，以控制本级驱动信号输出端GOUT与第二时钟信号输入端CKV2连接，以使得所述本级驱动信号输出端GOUT输出低电平；在所述第三时钟信号输入端CKV3的控制下，T5和T6都关闭。
在输出阶段S2，第一时钟信号输入端CKV1、起始端STV和第三时钟信号输入端CKV3都输入低电平，第二时钟信号输入端CKV2输入高电平；在所述起始端STV的控制下，T3和T4都关闭，以控制断开上拉节点PU与所述第一时钟信号输入端CKV1之间的连接并控制断开下拉节点PD与输入低电平VGL的低电平输入端之间的连接，存储电容Cs自举拉升所述上拉节点PU的电位，在所述上拉节点PU的控制下，T2继续打开，以控制本级驱动信号输出端GOUT与第二时钟信号输入端CKV2连接，以使得所述本级驱动信号输出端GOUT输出高电平；在所述第三时钟信号输入端CKV3的控制下，T5和T6都关闭。
在复位阶段S3，第三时钟信号输入端CKV3输入高电平，在第三时钟信号输入端CKV3的控制下，T5和T6都打开，以控制所述上拉节点PU与输入低电平VGL的低电平输入端连接，并控制所述下拉节点PD与输入高电平VGH的高电平输入端连接，以使得上拉节点PU的电位为低电平而下拉节点PD的电位为高电平；在所述上拉节点PU的控制下，T1关闭，以控制断开所述本级栅极驱动信号输出端GOUT与所述第二时钟信号输入端CKV之间的 连接；在所述下拉节点PD的控制下，T1打开，以控制所述本级栅极驱动信号输出端GOUT与输入低电平VGL的低电平输入端连接，以对所述本级栅极驱动信号输出端GOUT进行复位，使得本级栅极驱动信号输出端GOUT输出低电平。
本公开如图2所示的移位寄存器单元的具体实施例与相关技术相比只需增加两个TFT器件，既可以很好的解决栅极驱动信号输出抖动的问题，同时，GOA(Gate On Array，设置于阵列基板上的栅极驱动电路)架构内部节点的电压(内部节点指的是上拉节点)更加稳定，在一定程度上解决了移位寄存器单元的电路误操作的可能性。
本公开如图2所示的移位寄存器单元的具体实施例为6T1C架构，采用的TFT的数量较少，可以很好的实现窄边框。
本公开实施例所述的移位寄存器单元的驱动方法，应用于上述的移位寄存器单元，所述驱动方法包括：在每一显示周期内，
在起始阶段，置位信号输入端和起始端都输入第二电平，输出信号提供端输入第一电平，在所述起始端的控制下，驱动模块控制上拉节点与所述置位信号输入端连接并控制下拉节点与第一电平输入端连接，以使得所述上拉节点的电位为第二电平并所述下拉节点的电位为第一电平，在所述上拉节点的控制下，输出模块控制本级驱动信号输出端与输出信号提供端连接，以使得所述本级驱动信号输出端输出第一电平；
在输出阶段，置位信号输入端和起始端都输入第一电平，输出信号提供端输入第二电平，在所述起始端的控制下，驱动模块控制断开上拉节点与所述置位信号输入端之间的连接并控制断开下拉节点与第一电平输入端之间的连接，存储电容模块自举拉升所述上拉节点的电位，在所述上拉节点的控制下，输出模块继续控制本级驱动信号输出端与输出信号提供端连接，以使得本级栅极驱动信号输出端输出第二电平；
在复位阶段，复位端输入第二电平，在复位端的控制下，复位模块控制所述上拉节点与第一电平输入端连接并控制所述下拉节点与所述第二电平输入端连接，以使得上拉节点的电位为第一电平而所述下拉节点的电位为第二电平；在所述上拉节点的控制下，输出模块控制断开所述本级栅极驱动信号 输出端与所述输出信号提供端之间的连接；在所述下拉节点的控制下，所述输出模块控制所述本级栅极驱动信号输出端与所述第一电平输入端连接，以对所述本级栅极驱动信号输出端进行复位。
本公开实施例所述的移位寄存器单元的驱动方法应用于上述的移位寄存单元，在每一显示周期内，在起始阶段，驱动模块将置位信号输入到输出模块；在输出阶段，输出模块输出最终的栅极驱动信号，实现AA(Active Area，有效显示)区TFT器件沟道开启；在复位阶段，复位模块复位栅极驱动信号，实现AA区TFT器件沟道关闭。
本公开实施例所述的栅极驱动电路包括多级上述的移位寄存器单元；
除了最后一级移位寄存器单元之外，每一级所述移位寄存器单元的本级栅极信号输出端与相邻下一级移位寄存器的起始端连接。
在实际操作时，在本公开实施例所述的栅极驱动电路中，第4n-3级移位寄存器单元的置位信号输入端与第一时钟信号输入端连接，第4n-3级移位寄存器单元的输出信号提供端与第二时钟信号输入端连接，第4n-3级移位寄存器单元的复位端与第三时钟信号输入端连接；
第4n-2级移位寄存器单元的置位信号输入端与第二时钟信号输入端连接，第4n-2级移位寄存器单元的输出信号提供端与第三时钟信号输入端连接，第4n-2级移位寄存器单元的复位端与第四时钟信号输入端连接；
第4n-1级移位寄存器单元的置位信号输入端与第三时钟信号输入端连接，第4n-1级移位寄存器单元的输出信号提供端与第四时钟信号输入端连接，第4n-1级移位寄存器单元的复位端与第一时钟信号输入端连接；
第4n级移位寄存器单元的置位信号输入端与第四时钟信号输入端连接，第4n级移位寄存器单元的输出信号提供端与第一时钟信号输入端连接，第4n级移位寄存器单元的复位端与第二时钟信号输入端连接；
n为正整数，4n小于或等于所述栅极驱动电路包括的移位寄存器单元的级数。
如图4所示，第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3和第四时钟信号CK4的占空比都为1/4，所述第一时钟信号CK1的周期、所述第二时钟信号CK2的周期、所述第三时钟信号CK3的周期和所述第四时 钟信号CK4的周期都为T。
第二时钟信号CK2比第一时钟信号CK1延迟T/4；第三时钟信号CK3比第二时钟信号CK2延迟T/4；第四时钟信号CK4比第三时钟信号CK3延迟T/4。
下面通过一具体实施例来说明本公开所述的栅极驱动电路。
如图5所示，本公开所述的栅极驱动电路的一具体实施例包括第一级移位寄存器单元GTIC1、第二级移位寄存器单元GTIC2、第三级移位寄存器单元GTIC3和第四级移位寄存器单元GTIC4。本公开所述的栅极驱动电路的该具体实施例包括的移位寄存器单元的级数可以为多个，在图5中仅示出了四级移位寄存器单元的连接关系用于示例。
如图5所示，第一级移位寄存器单元GTIC1的起始端与外部起始信号输入端STV_IN连接，第一级移位寄存器单元GTIC1的置位信号输入端与第一时钟信号输入端CKV1连接，第一级移位寄存器单元GTIC1的输出信号提供端与第二时钟信号输入端CKV2连接，第一级移位寄存器单元GTIC1的复位端RESET与第三时钟信号输入端CKV3连接；
第二级移位寄存器单元GTIC2的起始端与第一级移位寄存器单元GTIC1的第一栅极驱动信号输出端GOUT1连接，第二级移位寄存器单元GTIC2的置位信号输入端与第二时钟信号输入端CKV2连接，第二级移位寄存器单元GTIC2的输出信号提供端与第三时钟信号输入端CKV3连接，第二级移位寄存器单元GTIC2的复位端与第四时钟信号输入端CKV4连接；
第三级移位寄存器单元GTIC3的起始端与第二级移位寄存器单元GTIC2的第二栅极驱动信号输出端GOUT2连接，第三级移位寄存器单元GTIC3的置位信号输入端与第三时钟信号输入端CKV3连接，第三级移位寄存器单元GTIC3的输出信号提供端与第四时钟信号输入端CKV4连接，第三级移位寄存器单元GTIC3的复位端与第一时钟信号输入端CKV1连接；
第四级移位寄存器单元GTIC4的起始端与第三级移位寄存器单元GTIC3的第三栅极驱动信号输出端GOUT3连接，第四级移位寄存器单元GTIC4的置位信号输入端与第四时钟信号输入端CKV4连接，第四级移位寄存器单元GTIC4的输出信号提供端与第一时钟信号输入端CKV1连接，第四级移位寄 存器单元GTIC4的复位端与第二时钟信号输入端CKV2连接。
在图5所示的具体实施例中，标号为STV的为各级移位寄存器单元的起始端，标号为SET的为各级移位寄存器单元的置位信号输入端，标号为OP的为各级移位寄存器单元的输出信号提供端，标号为RESET的为各级移位寄存器单元的复位端，标号为GOUT的为各级移位寄存器单元的本级栅极驱动信号输出端；
第一级移位寄存器单元GTIC1的本级栅极驱动信号输出端与第一栅极驱动信号输出端GOUT1连接；
第二级移位寄存器单元GTIC2的本级栅极驱动信号输出端与第二栅极驱动信号输出端GOUT2连接；
第三级移位寄存器单元GTIC3的本级栅极驱动信号输出端与第三栅极驱动信号输出端GOUT3连接；
第四级移位寄存器单元GTIC4的本级栅极驱动信号输出端与第四栅极驱动信号输出端GOUT4连接。
根据如图5中所示的级联方式，做24级仿真，栅极驱动信号输出正常。
本公开所述的显示装置包括上的栅极驱动电路。
本实施例所提供的显示装置可以显示器、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的可选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (11)

  1. 一种移位寄存器单元，包括驱动模块、存储电容模块、输出模块和复位模块，其中，
    所述驱动模块分别与起始端、上拉节点、下拉节点、第一电平输入端和置位信号输入端连接，用于在所述起始端的控制下，控制所述上拉节点是否与所述置位信号输入端连接并控制所述下拉节点是否与所述第一电平输入端连接；
    所述输出模块分别与所述上拉节点、所述下拉节点、所述第一电平输入端、输出信号提供端和本级栅极驱动信号输出端连接，用于在所述上拉节点的控制下控制所述本级栅极驱动信号输出端是否与所述输出信号提供端连接，在所述下拉节点的控制下控制所述本级栅极驱动信号输出端是否与所述第一电平输入端连接；
    所述存储电容模块连接于所述上拉节点和所述本级栅极驱动信号输出端之间；
    所述复位模块分别与复位端、第二电平输入端、所述上拉节点、所述下拉节点和所述第一电平输入端连接，用于在复位端的控制下，控制所述上拉节点是否与所述第一电平输入端连接，并控制所述下拉节点是否与所述第二电平输入端连接。
  2. 如权利要求1所述的移位寄存器单元，其中，所述驱动模块包括第一驱动晶体管和第二驱动晶体管；
    所述第一驱动晶体管的栅极与所述起始端连接，所述第一驱动晶体管的第一极与所述上拉节点连接，所述第一驱动晶体管的第二极与所述置位信号输入端连接；
    所述第二驱动晶体管的栅极与所述起始端连接，所述第二驱动晶体管的第一极与所述第一电平输入端连接，所述第二驱动晶体管的第二极与所述下拉节点连接。
  3. 如权利要求2所述的移位寄存器单元，其中，所述复位模块包括第一复位晶体管和第二复位晶体管；
    所述第一复位晶体管的栅极与所述复位端连接，所述第一复位晶体管的第一极与所述下拉节点连接，所述第一复位晶体管的第二极与所述第二电平输入端连接；
    所述第二复位晶体管的栅极与所述复位端连接，所述第二复位晶体管的第一极与所述上拉节点连接，所述第二复位晶体管的第二极与所述第一电平输入端连接。
  4. 如权利要求3所述的移位寄存器单元，其中，所述输出模块包括第一输出晶体管和第二输出晶体管；
    所述第一输出晶体管的栅极与所述下拉节点连接，所述第一输出晶体管的第一极与所述第一电平输入端连接，所述第一输出晶体管的第二极与所述本级栅极驱动信号输出端连接；
    所述第二输出晶体管的栅极与所述上拉节点连接，所述第二输出晶体管的第一极与所述本级栅极驱动信号输出端连接，所述第二输出晶体管的第二极与输出信号提供端连接。
  5. 如权利要求4所述的移位寄存器单元，其中，所述第一驱动晶体管、所述第二驱动晶体管、所述第一输出晶体管、所述第二输出晶体管、所述第一复位晶体管和所述第二复位晶体管都为n型晶体管。
  6. 如权利要求4所述的移位寄存器单元，其中，所述第一驱动晶体管、所述第二驱动晶体管、所述第一输出晶体管、所述第二输出晶体管、所述第一复位晶体管和所述第二复位晶体管都为p型晶体管。
  7. 如权利要求1所述的移位寄存器单元，其中，所述存储电容模块包括存储电容；所述存储电容的第一端与所述上拉节点连接，所述存储电容的第二端与所述本级栅极驱动信号输出端连接。
  8. 一种移位寄存器单元的驱动方法，应用于如权利要求1至7中任一权利要求所述的移位寄存器单元，所述驱动方法包括：在每一显示周期内，
    在起始阶段，置位信号输入端和起始端都输入第二电平，输出信号提供端输入第一电平，在所述起始端的控制下，驱动模块控制上拉节点与所述置位信号输入端连接并控制下拉节点与第一电平输入端连接，以使得所述上拉节点的电位为第二电平并所述下拉节点的电位为第一电平，在所述上拉节点 的控制下，输出模块控制本级驱动信号输出端与输出信号提供端连接，以使得所述本级驱动信号输出端输出第一电平；
    在输出阶段，置位信号输入端和起始端都输入第一电平，输出信号提供端输入第二电平，在所述起始端的控制下，驱动模块控制断开上拉节点与所述置位信号输入端之间的连接并控制断开下拉节点与第一电平输入端之间的连接，存储电容模块自举拉升所述上拉节点的电位，在所述上拉节点的控制下，输出模块继续控制本级驱动信号输出端与输出信号提供端连接，以使得本级栅极驱动信号输出端输出第二电平；
    在复位阶段，复位端输入第二电平，在复位端的控制下，复位模块控制所述上拉节点与第一电平输入端连接并控制所述下拉节点与所述第二电平输入端连接，以使得上拉节点的电位为第一电平而所述下拉节点的电位为第二电平；在所述上拉节点的控制下，输出模块控制断开所述本级栅极驱动信号输出端与所述输出信号提供端之间的连接；在所述下拉节点的控制下，所述输出模块控制所述本级栅极驱动信号输出端与所述第一电平输入端连接，以对所述本级栅极驱动信号输出端进行复位。
  9. 一种栅极驱动电路，包括多级如权利要求1至7中任一权利要求所述的移位寄存器单元；
    除了最后一级移位寄存器单元之外，每一级所述移位寄存器单元的本级栅极信号输出端与相邻下一级移位寄存器的起始端连接。
  10. 如权利要求9所述的栅极驱动电路，其中，第4n-3级移位寄存器单元的置位信号输入端与第一时钟信号输入端连接，第4n-3级移位寄存器单元的输出信号提供端与第二时钟信号输入端连接，第4n-3级移位寄存器单元的复位端与第三时钟信号输入端连接；
    第4n-2级移位寄存器单元的置位信号输入端与第二时钟信号输入端连接，第4n-2级移位寄存器单元的输出信号提供端与第三时钟信号输入端连接，第4n-2级移位寄存器单元的复位端与第四时钟信号输入端连接；
    第4n-1级移位寄存器单元的置位信号输入端与第三时钟信号输入端连接，第4n-1级移位寄存器单元的输出信号提供端与第四时钟信号输入端连接，第4n-1级移位寄存器单元的复位端与第一时钟信号输入端连接；
    第4n级移位寄存器单元的置位信号输入端与第四时钟信号输入端连接，第4n级移位寄存器单元的输出信号提供端与第一时钟信号输入端连接，第4n级移位寄存器单元的复位端与第二时钟信号输入端连接；
    n为正整数，4n小于或等于所述栅极驱动电路包括的移位寄存器单元的级数；
    第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号的占空比都为1/4，所述第一时钟信号的周期、所述第二时钟信号的周期、所述第三时钟信号的周期和所述第四时钟信号的周期都为T；
    第二时钟信号比第一时钟信号延迟T/4；第三时钟信号比第二时钟信号延迟T/4；第四时钟信号比第三时钟信号延迟T/4。
  11. 一种显示装置，包括如权利要求9或10所述的栅极驱动电路。
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