WO2019015630A1 - 移位寄存器单元、移位寄存器单元的驱动方法、栅极驱动电路、栅极驱动电路的驱动方法和显示装置 - Google Patents

移位寄存器单元、移位寄存器单元的驱动方法、栅极驱动电路、栅极驱动电路的驱动方法和显示装置 Download PDF

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Publication number
WO2019015630A1
WO2019015630A1 PCT/CN2018/096221 CN2018096221W WO2019015630A1 WO 2019015630 A1 WO2019015630 A1 WO 2019015630A1 CN 2018096221 W CN2018096221 W CN 2018096221W WO 2019015630 A1 WO2019015630 A1 WO 2019015630A1
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WIPO (PCT)
Prior art keywords
node
clock signal
signal input
control
shift register
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PCT/CN2018/096221
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English (en)
French (fr)
Inventor
郑灿
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京东方科技集团股份有限公司
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Priority to US16/619,308 priority Critical patent/US11011093B2/en
Publication of WO2019015630A1 publication Critical patent/WO2019015630A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of display driving technologies, and in particular, to a shift register unit, a driving method of a shift register unit, a gate driving circuit, a driving method of a gate driving circuit, and a display device.
  • the present disclosure provides a shift register unit comprising:
  • a start module respectively connected to the first clock signal input end, the first node and the initial voltage input end, for controlling the first node and the initial voltage input under the control of the first clock signal input end Connected or disconnected;
  • first capacitor module the first end is connected to the second clock signal input end, and the second end is connected to the first node;
  • a first node control module configured to be connected to the third node, the first level input end, and the first node, respectively, for controlling the first node and the first level under the control of the third node
  • the input is connected or disconnected;
  • a potential control module respectively connected to the first node, the second level input end and the second node, configured to control the second node and the second level input terminal under the control of the first node Connect or disconnect;
  • a second capacitor module the first end is connected to the second node, and the second end is connected to the gate driving signal output end;
  • a second node control module which is respectively connected to the third node, the first level input end, and the second node;
  • An output module which is respectively connected to the second node, the third node, the gate driving signal output end, the third clock signal input end, and the first level input end;
  • the third node control module is respectively connected to the fourth clock signal input end, the second level input end, the second node and the third node.
  • the shift register unit of the present disclosure further includes a third capacitor module; the first end of the third capacitor module is connected to the third node, and the second end of the third capacitor module is The first level input is connected;
  • the second node control module is configured to control, by the third node, to connect or disconnect the second node from the first level input end;
  • the third node control module is configured to control, by the second node, to connect or disconnect the third node and the fourth clock signal input end;
  • the output module is configured to control the gate driving signal output end to be connected to or disconnected from the third clock signal input end under the control of the second node, and control the A gate drive signal output is coupled to or disconnected from the first level input.
  • the start module includes: a start transistor, a gate connected to the first clock signal input end, a first pole connected to the first node, and a second pole connected to the start voltage input end ;
  • the first capacitor module includes a first capacitor; the first end of the first capacitor is connected to the second clock signal input end, and the second end of the first capacitor is connected to the first node;
  • the first node control module includes: a first node control transistor, a gate connected to the third node, a first pole connected to the first level input terminal, and a second pole connected to the first node;
  • the potential control module includes a potential control transistor, a gate connected to the first node, a first pole connected to the second node, and a second pole connected to the second level input terminal.
  • the second capacitor module includes a second capacitor; the first end of the second capacitor is connected to the second node, and the second end of the second capacitor is connected to the gate driving signal output end;
  • the second node control module includes: a second node control transistor, the gate is connected to the third node, the first pole is connected to the first level input end, and the second pole is connected to the second node;
  • the third node control module includes: a first control transistor, a gate connected to the fourth clock signal input end, a first pole connected to the third node, a second pole and the second level input end Connect; and,
  • a second control transistor the gate is connected to the second node, the first pole is connected to the third node, and the second pole is connected to the fourth clock signal input end;
  • the output module includes: a first output transistor, a gate connected to the second node, a first pole connected to the gate driving signal output end, and a second pole connected to the third clock signal input end; ,
  • a second output transistor having a gate connected to the third node, a first pole connected to the first level input terminal, and a second pole connected to the gate drive signal output end.
  • the transistor and the second output transistor are both p-type transistors, the second level input terminal is a low level input terminal, and the first level input terminal is a high level input terminal;
  • the start transistor, the first node control transistor, the potential control transistor, the second node control transistor, the first control transistor, the second control transistor, the first output transistor, and The second output transistors are all n-type transistors, the second level input terminal is a high level input terminal, and the first level input terminal is a low level input terminal.
  • the present disclosure also provides a driving method of a shift register unit for driving the above-described shift register unit, and the driving method of the shift register unit includes: in each display period,
  • the first signal V2 is input to both the start signal input end and the first clock signal input end, and the second clock signal input end, the third clock signal input end and the fourth clock signal input end are all input with the first electric power.
  • Level V1 the start unit controls the start signal input end to be connected to the first node until the potential of the first node becomes V2-Vth1, and Vth1 is a threshold voltage of the start transistor included in the start unit;
  • the potential control module controls the second node to be connected to the second level input terminal under the control of the first node until the potential of the second node becomes V2-Vth1-Vth2, and Vth2 is a potential control included in the potential control module a threshold voltage of the transistor;
  • the output module controls the gate driving signal output end to be connected to the third clock signal input end under the control of the second node, so that the gate driving signal output end outputs the first level V1 ;
  • the second clock signal input terminal inputs the second level V2, and the first signal input end, the first clock signal input end, the third clock signal input end, and the fourth clock signal input end are all input to the first level.
  • V1 since the potential of the first end of the first capacitor module is changed from V1 to V2, so that the potential of the first node becomes 2V2-Vth1-V1, and the potential control module is controlled under the control of the first node.
  • the second node is connected to the second level input terminal such that the potential of the second node is the second level V2; and the output module controls the gate driving signal output terminal under the control of the second node Connecting to the third clock signal input terminal, so that the gate drive signal output terminal outputs a first level V1;
  • the third clock signal input terminal inputs a second level V2, and the first signal input end, the first clock signal input end, the second clock signal input end, and the fourth clock signal input end are all input to the first level.
  • V1 since the potential of the first end of the first capacitor module is changed from V2 to V1, so that the potential of the first node becomes V2-Vth1, and the potential control module controls the control under the control of the first node.
  • the output module controls the gate driving signal output end to be connected to the third clock signal input end under the control of the second node, so that the gate
  • the pole drive signal output terminal outputs a second level V2, since the potential of the second terminal of the second capacitor module is changed from V1 to V2, the potential of the second node jumps to 2V2-V1;
  • the fourth clock signal input terminal inputs a second level V2, and the first signal input end, the first clock signal input end, the second clock signal input end, and the third clock signal input end are all input to the first level.
  • V1 the third node control module controls the third node to be connected to the second level input terminal under the control of the fourth clock signal input end, and the second node control unit controls under the control of the third node
  • the second node is connected to the first level input terminal, and the output module controls the gate driving signal output end to output the first level V1 under the control of the third node.
  • the driving method of the shift register unit of the present disclosure further includes:
  • the third node control module controls the third node to connect with the fourth clock signal input end,
  • the potential of the third node is caused to be a first level V1
  • the output module controls disconnection between the gate driving signal output end and the first level input terminal under the control of the third node.
  • a duty ratio of a first clock signal input by the first clock signal input terminal, a duty ratio of a second clock signal input by the second clock signal input terminal, and a third clock signal The duty ratio of the third clock signal input by the input terminal and the duty ratio of the fourth clock signal input by the fourth clock signal input terminal are both 1/4;
  • the period of the first clock signal, the period of the second clock signal, the period of the third clock signal, and the period of the fourth clock signal are both T;
  • the second clock signal is delayed by T/4 from the first clock signal
  • the third clock signal is delayed by T/4 from the second clock signal
  • the fourth clock signal is delayed from the third clock signal T/4.
  • the present disclosure also provides a gate driving circuit including M cascaded shift register units described above; M is an integer greater than one.
  • the present disclosure also provides a driving method of a gate driving circuit, the gate driving circuit includes M cascaded shift register units, and M is an integer greater than one;
  • the driving method of the gate driving circuit includes:
  • N is an integer greater than or equal to zero, and 4N+4 is less than or equal to the M
  • the first clock signal input end of the 4N+1th stage shift register unit is connected to the first clock signal
  • the second clock signal input end of the 4N+1th stage shift register unit is connected to the second clock signal
  • 4N+1 The third clock signal input end of the stage shift register unit is connected to the third clock signal
  • the fourth clock signal input end of the 4N+1th stage shift register unit is connected to the fourth clock signal
  • the first clock signal input end of the 4N+2 stage shift register unit is connected to the second clock signal, and the second clock signal input end of the 4N+2 stage shift register unit is connected to the third clock signal, 4N+2
  • the third clock signal input end of the stage shift register unit is connected to the fourth clock signal, and the fourth clock signal input end of the 4th N+2 stage shift register unit is connected to the first clock signal;
  • the first clock signal input end of the 4N+3 stage shift register unit is connected to the third clock signal, and the second clock signal input end of the 4N+3 stage shift register unit is connected to the fourth clock signal, 4N+3
  • the third clock signal input end of the stage shift register unit is connected to the first clock signal, and the fourth clock signal input end of the 4th N+3 stage shift register unit is connected to the second clock signal;
  • the first clock signal input end of the 4N+4 stage shift register unit is connected to the fourth clock signal
  • the second clock signal input end of the 4N+4th stage shift register unit is connected to the first clock signal
  • the third clock signal input end of the stage shift register unit is connected to the second clock signal
  • the fourth clock signal input end of the 4th N+4 stage shift register unit is connected to the third clock signal.
  • the present disclosure also provides a display device including the above-described gate drive circuit.
  • FIG. 1 is a structural diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 2 is a structural diagram of a shift register unit according to another embodiment of the present disclosure.
  • FIG. 3 is a circuit diagram of a specific embodiment of a shift register unit of the present disclosure.
  • FIG. 4 is a timing diagram showing the operation of a specific embodiment of the shift register unit shown in FIG. 3 of the present disclosure.
  • the transistors used in the embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other devices having the same characteristics.
  • one of the poles is referred to as a first pole, and the other pole is referred to as a second pole.
  • the first pole may be a drain
  • the second pole may be a source
  • the first pole may be a source
  • the second pole may be a drain.
  • the shift register unit includes: a start module 11 , a first capacitor module 12 , a first node control module 13 , a potential control module 14 , a second capacitor module 15 , and a second The node control module 16, the output module 17, and the third node control module 18.
  • the start module 11 is respectively connected to the first clock signal input terminal CKA, the first node N1 and the start voltage input terminal STV.
  • the starting module 11 is configured to control the first node N1 to be connected or disconnected from the starting voltage input terminal STV under the control of the first clock signal input terminal CKA.
  • the first end of the first capacitor module 12 is coupled to the second clock signal input terminal CKB.
  • the second end of the first capacitor module 12 is connected to the first node N1.
  • the first node control module 13 is connected to the third node N3, the first level input terminal inputting the first level V1, and the first node N1, respectively.
  • the first node control module 13 is configured to control the first node N1 to be connected or disconnected from the first level input terminal of the input first level V1 under the control of the third node N3.
  • the potential control module 14 is connected to the first node N1, the second level input terminal inputting the second level V2, and the second node N2, respectively.
  • the potential control module 14 is configured to control the second node N2 to be connected or disconnected from the second level input terminal of the input second level V2 under the control of the first node N1.
  • the first end of the second capacitor module 15 is connected to the second node N2.
  • the second end of the second capacitor module 15 is connected to the gate drive signal output terminal GOUT.
  • the second node control module 16 is connected to the third node N3, the first level input terminal inputting the first level V1, and the second node N2, respectively.
  • the output module 17 and the second node N2, the third node N3, the gate driving signal output terminal GOUT, the third clock signal input terminal CKC, and the first level of the input first level V1, respectively The input is connected.
  • the third node control module 18 is connected to the fourth clock signal input terminal CKD, the second level input terminal inputting the second level V2, the second node N2, and the third node N3, respectively.
  • the shift register unit provides the first capacitor module 12, the first node control module 13 and the potential control module 14 and bootstrapped through the first capacitor module 12 in the second stage of each display cycle.
  • the function is to control the potential of the first node N1 such that the potential control module 14 can better control the connection of the second node N2 to the second level input under the control of the first node N1.
  • the shift register unit according to the embodiment of the present disclosure further performs a bootstrap action of the second capacitor module 15 in the third stage of each display period, so that the potential of the second node N2 can control the output module in the third stage.
  • the output transistor will open better, enhance the drive capability of the output transistor, and achieve normal transmission of signals at narrow pulse widths.
  • the shift register unit in the embodiment of the present disclosure may further include a third capacitor module 19.
  • the first end of the third capacitor module 19 is connected to the third node N3.
  • the second end of the third capacitor module 19 is connected to the first level input terminal.
  • the second node control module 16 is configured to control the second node N2 to be connected or disconnected from the first level input end of the input first level V1 under the control of the third node N3.
  • the third node control module 18 is configured to control the third node N3 to be connected or disconnected from the fourth clock signal input terminal CKD under the control of the second node N2.
  • the output module 17 is configured to control the gate driving signal output terminal GOUT to be connected to or disconnected from the third clock signal input terminal CKC under the control of the second node N2.
  • the output module 17 is further configured to control the gate driving signal output terminal GOUT to be connected to or disconnected from the first level input terminal of the input first level V1 under the control of the third node N3.
  • the third capacitor module 19 in the shift register unit of the present disclosure can better maintain the potential of the third node.
  • the starting module may include: a starting transistor.
  • a gate of the start transistor is coupled to the first clock signal input, a first pole is coupled to the first node, and a second pole is coupled to the start voltage input.
  • the first capacitor module may include a first capacitor.
  • the first end of the first capacitor is coupled to the second clock signal input.
  • the second end of the first capacitor is connected to the first node.
  • the first node control module may include: a first node control transistor. A gate of the first node control transistor is coupled to the third node, a first pole is coupled to the first level input terminal, and a second pole is coupled to the first node.
  • the potential control module can include a potential control transistor.
  • a gate of the potential control transistor is coupled to the first node, a first pole is coupled to the second node, and a second pole is coupled to the second level input.
  • the second capacitor module may include a second capacitor.
  • the first end of the second capacitor is coupled to the second node.
  • the second end of the second capacitor is coupled to the gate drive signal output.
  • the second node control module may include: a second node control transistor.
  • the gate of the second node control transistor is connected to the third node, the first pole is connected to the first level input terminal, and the second pole is connected to the second node.
  • the third node control module may include: a first control transistor and a second control transistor.
  • a gate of the first control transistor is coupled to the fourth clock signal input terminal, a first pole is coupled to the third node, and a second pole is coupled to the second level input terminal.
  • a gate of the second control transistor is connected to the second node, a first pole is connected to the third node, and a second pole is connected to the fourth clock signal input end.
  • the output module may include a first output transistor and a second output transistor.
  • the gate of the first output transistor is connected to the second node, the first pole is connected to the gate drive signal output end, and the second pole is connected to the third clock signal input end.
  • a gate of the second output transistor is coupled to the third node, a first pole is coupled to the first level input terminal, and a second pole is coupled to the gate drive signal output terminal.
  • the start transistor, the first node control transistor, the potential control transistor, the second node control transistor, the first control transistor, the second control transistor, the The first output transistor and the second output transistor may both be p-type transistors.
  • the first level input terminal is a high level input terminal
  • the second level input terminal is a high level input terminal.
  • the first output transistor and the second output transistor may both be n-type transistors.
  • the first level input terminal is a low level input terminal
  • the second level input terminal is a high level input terminal.
  • a specific embodiment of the shift register unit of the present disclosure includes a start module 11, a first capacitor module 12, a first node control module 13, a potential control module 14, and a second capacitor module 15, The second node control module 16, the output module 17, the third node control module 18, and the third capacitor module 19.
  • the start module 11 includes a start transistor M1.
  • the gate of the start transistor M1 is connected to the first clock signal input terminal CKA, the source is connected to the first node N1, and the drain is connected to the start voltage input terminal STV.
  • the first capacitor module 12 includes a first capacitor C1.
  • the first end of the first capacitor C1 is connected to the second clock signal input terminal CKB.
  • the second end of the first capacitor C1 is connected to the first node N1.
  • the first node control module 13 includes: a first node control transistor M2.
  • the gate of the first node control transistor M2 is connected to the third node N3, the drain is connected to a high level input terminal of the input high level VGH, and the source is connected to the first node N1.
  • the potential control module 14 includes a potential control transistor M3.
  • the gate of the potential control transistor M3 is connected to the first node N1, the source is connected to the second node N2, and the drain is connected to the low-level input terminal of the input low level VGL.
  • the second capacitor module 15 includes a second capacitor C2.
  • the first end of the second capacitor C2 is connected to the second node N2.
  • the second end of the second capacitor C2 is connected to the gate driving signal output terminal GOUT.
  • the second node control module 16 includes a second node control transistor M6.
  • the gate of the second node control transistor M6 is connected to the third node N3, the drain is connected to the high level input terminal of the input high level VGH, and the source is connected to the second node N2.
  • the third node control module 18 includes a first control transistor M4 and a second control transistor M5.
  • the gate of the first control transistor M4 is connected to the fourth clock signal input terminal CKD, the source is connected to the third node N3, and the drain is connected to the low-level input terminal of the input low level VGL.
  • the gate of the second control transistor M5 is connected to the second node N2, the source is connected to the third node N3, and the drain is connected to the fourth clock signal input terminal CKD.
  • the output module 17 includes a first output transistor M7 and a second output transistor M8.
  • the gate of the first output transistor M7 is connected to the second node N2, the source is connected to the gate drive signal output terminal GOUT, and the drain is connected to the third clock signal input terminal CKC.
  • the gate of the second output transistor M8 is connected to the third node N3, the drain is connected to the high level input terminal of the input high level VGH, and the source is connected to the gate driving signal output terminal GOUT.
  • the third capacitor module 19 includes a third capacitor C3.
  • the first end of the third capacitor C3 is connected to the third node N3.
  • the second end of the third capacitor C3 is connected to the high level input terminal of the input high level VGH.
  • all of the transistors are p-type transistors.
  • the above transistors may also be replaced with n-type transistors, and the types of transistors are not limited herein.
  • GOUT is grounded through load resistors and load capacitors in series.
  • the specific embodiment of the shift register unit shown in FIG. 3 of the present disclosure includes the following stages in each display cycle during operation.
  • the potential of N1 becomes VGL-Vth1
  • Vth1 is the threshold voltage of the starting transistor included in the starting unit (Vth1 is a negative value because M1 is a p-type transistor); M3 is turned on until N2
  • the potential becomes VGL-Vth1-Vth2
  • Vth2 is the threshold voltage of the potential control transistor included in the potential control module (Vth2 is a negative value because M2 is a p-type transistor); under the control of N2, M7 is turned on, and GOUT is connected to CKC.
  • M5 is turned on to control the connection between N3 and CKD, so that the potential of N3 is high level VGH, under the control of N3, M8 is turned off to control GOUT Disconnected from the high level input of the input high level VGH.
  • CKB inputs a low level VGL
  • STV, CKA, CKC, and CKD both input a high level VGH. Since the potential of the first end of C1 is changed from VGH to VGL, the potential of N1 becomes 2VGL accordingly.
  • M3 is turned on to control N2 to connect with the low level input of the input low level VGL, so that the potential of N2 is low level VGL; under the control of N2, M7 is turned on.
  • N2 To control the connection between GOUT and CKC, so that GOUT outputs a high level VGH; under the control of N2, M5 is turned on to control the connection between N3 and CKD, so that the potential of N3 is high level VGH, under the control of N3 M8 is turned off to control the disconnection between GOUT and the high level input of the input high level VGH.
  • CKC inputs a low level VGL
  • STV, CKA, CKB, and CKD both input a high level VGH. Since the potential of the first end of C1 is changed from VGL to VGH, the potential of N1 changes to VGL accordingly.
  • -Vth1 under the control of N1, M3 is disconnected to control the disconnection between N2 and the low level input of the input low level VGL; under the control of N2, M7 is turned on to control the connection of GOUT and CKC, so that GOUT outputs a low level VGL.
  • N2 Since the potential of the second end of C2 is changed from VGH to VGL, the potential of N2 jumps to 2VGL-VGH; under the control of the second node N2, M5 is turned on to control N3 and The CKD is connected such that the potential of N3 is at a high level VGH. Under the control of N3, M8 is turned off to control the disconnection between GOUT and the high level input of the input high level VGH.
  • CKD inputs a low level VGL
  • STV, CKA, CKB, and CKC both input a high level VGH.
  • M4 is turned on to control the low level input of N3 and the input low level VGL.
  • M6 is turned on to control N2 to connect with the high level input terminal of input high level VGH.
  • N2 is disconnected; under the control of N3, M8 is turned on to control GOUT outputs a high level VGH.
  • CKA inputs a low level VGL, STV, CKB, CKC and CKD all input a high level VGH, M1 is turned on, the high level of the STV input is passed to N1, so that M3 is turned off, and the potential of N2 is still When it is high, the potential of N3 is still low, M7 is off, M8 is on, and GOUT still outputs high level VGH.
  • a particular embodiment of the shift register unit of the present disclosure utilizes the bootstrap effect of two capacitors by setting C1, M2, and M3: the bootstrap effect of the first capacitor C1 in the second phase t2, such that the potential of N1 It is able to control the M3 to open very well, so that N2 is connected to the VGL; in the third stage t3, the bootstrap effect of the second capacitor C2, so that the potential of the N2 can control the output module to include the first output transistor M7 to be better opened.
  • the driving capability of the first output transistor M7 is enhanced to achieve normal transmission of signals at a narrow pulse width.
  • the duty ratio of the first clock signal input by the CKA, the duty ratio of the second clock signal input by the CKB, the duty ratio of the third clock signal input by the CKC, and the fourth clock signal of the CKD input can be both 1/4.
  • the period of the first clock signal, the period of the second clock signal, the period of the third clock signal, and the period of the fourth clock signal may both be T.
  • the second clock signal is delayed by T/4 from the first clock signal
  • the third clock signal is delayed by T/4 from the second clock signal
  • the fourth clock signal is delayed from the third clock signal T/4.
  • the driving method of the shift register unit according to the embodiment of the present disclosure is for driving the shift register unit, and the driving method of the shift register unit includes: in each display period, the following stages are included.
  • the first signal V2 is input to both the start signal input end and the first clock signal input end, and the second clock signal input end, the third clock signal input end and the fourth clock signal input end are all input with the first electric power.
  • Level V1 the start unit controls the start signal input end to be connected to the first node until the potential of the first node becomes V2-Vth1, and Vth1 is a threshold voltage of the start transistor included in the start unit;
  • the potential control module controls the second node to be connected to the second level input terminal under the control of the first node until the potential of the second node becomes V2-Vth1-Vth2, and Vth2 is a potential control included in the potential control module a threshold voltage of the transistor;
  • the output module controls the gate driving signal output end to be connected to the third clock signal input end under the control of the second node, so that the gate driving signal output end outputs the first level V1 .
  • the second clock signal input terminal inputs the second level V2, and the first signal input end, the first clock signal input end, the third clock signal input end, and the fourth clock signal input end are all input to the first level.
  • V1 since the potential of the first end of the first capacitor module is changed from V1 to V2, so that the potential of the first node becomes 2V2-Vth1-V1, and the potential control module is controlled under the control of the first node.
  • the second node is connected to the second level input terminal such that the potential of the second node is the second level V2; and the output module controls the gate driving signal output terminal under the control of the second node Connected to the third clock signal input terminal such that the gate drive signal output terminal outputs a first level V1.
  • the third clock signal input terminal inputs a second level V2, and the first signal input end, the first clock signal input end, the second clock signal input end, and the fourth clock signal input end are all input to the first level.
  • V1 since the potential of the first end of the first capacitor module is changed from V2 to V1, so that the potential of the first node becomes V2-Vth1, and the potential control module controls the control under the control of the first node.
  • the output module Disconnecting between the second node and the second level input terminal; the output module controls the gate driving signal output end to be connected to the third clock signal input end under the control of the second node, so that the gate The pole drive signal output terminal outputs the second level V2. Since the potential of the second terminal of the second capacitor module is changed from V1 to V2, the potential of the second node jumps to 2V2-V1.
  • the fourth clock signal input terminal inputs a second level V2, and the first signal input end, the first clock signal input end, the second clock signal input end, and the third clock signal input end are all input to the first level.
  • V1 the third node control module controls the third node to be connected to the second level input terminal under the control of the fourth clock signal input end, and the second node control unit controls under the control of the third node
  • the second node is connected to the first level input terminal, and the output module controls the gate driving signal output end to output the first level V1 under the control of the third node.
  • the potential of the first node is controlled by the bootstrap action of the first capacitor module at the second stage of each display period, so that the first The potential control module under the control of the node can better control the connection between the second node and the second level input than the related art.
  • the shift register unit according to the embodiment of the present disclosure further performs a bootstrap action of the second capacitor module 15 in the third stage of each display period, so that the potential of the second node N2 can control the output module in the third stage.
  • the output transistor will open better, enhance the drive capability of the output transistor, and achieve normal transmission of signals at narrow pulse widths.
  • the driving method of the shift register unit in the embodiment of the present disclosure further includes:
  • the third node control module controls the third node to connect with the fourth clock signal input end,
  • the potential of the third node is caused to be a first level V1
  • the output module controls disconnection between the gate driving signal output end and the first level input terminal under the control of the third node.
  • a duty ratio of the first clock signal input by the first clock signal input terminal, a duty ratio of the second clock signal input by the second clock signal input terminal, and the third clock signal may both be 1/4.
  • the period of the first clock signal, the period of the second clock signal, the period of the third clock signal, and the period of the fourth clock signal may both be T.
  • the second clock signal is delayed by T/4 from the first clock signal
  • the third clock signal is delayed by T/4 from the second clock signal
  • the fourth clock signal is delayed from the third clock signal T/4.
  • the gate driving circuit of the embodiment of the present disclosure includes M cascaded shift register units; M is an integer greater than 1.
  • the 4th N+1th shift register unit, the 4th N+2 shift register unit, the 4th N+3 shift register unit, and the 4th N+4 shift in the M cascaded shift register units The operation of the register unit is as follows, where N is an integer greater than or equal to zero, and 4N+4 is less than or equal to the M.
  • the first clock signal input end of the 4N+1th stage shift register unit is connected to the first clock signal
  • the second clock signal input end of the 4N+1th stage shift register unit is connected to the second clock signal
  • 4N+1 The third clock signal input end of the stage shift register unit is connected to the third clock signal
  • the fourth clock signal input end of the 4N+1th stage shift register unit is connected to the fourth clock signal.
  • the first clock signal input end of the 4th N+2 stage shift register unit is connected to the second clock signal, and the second clock signal input end of the 4th N+2 stage shift register unit is connected to the third clock signal,
  • the third clock signal input end of the 4N+2 stage shift register unit is connected to the fourth clock signal, and the fourth clock signal input end of the 4N+2 stage shift register unit is connected to the first clock signal.
  • the first clock signal input end of the 4N+3 stage shift register unit is connected to the third clock signal
  • the second clock signal input end of the 4N+3 stage shift register unit is connected to the fourth clock signal
  • 4N The third clock signal input end of the +3 stage shift register unit is connected to the first clock signal
  • the fourth clock signal input end of the 4N+3 stage shift register unit is connected to the second clock signal.
  • the first clock signal input end of the 4th N+4 stage shift register unit is connected to the fourth clock signal
  • the second clock signal input end of the 4N+4th stage shift register unit is connected to the first clock signal
  • the third clock signal input end of the 4N+4 stage shift register unit is connected to the second clock signal
  • the fourth clock signal input end of the 4N+4th stage shift register unit is connected to the third clock signal.
  • the display device includes the above-described gate driving circuit.
  • the display device may include a liquid crystal display device such as a liquid crystal panel, a liquid crystal television, a mobile phone, or a liquid crystal display.
  • a liquid crystal display device such as a liquid crystal panel, a liquid crystal television, a mobile phone, or a liquid crystal display.
  • the embodiments of the present disclosure may also include an organic light emitting display or other type of display device such as an electronic reader or the like.

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Abstract

一种移位寄存器单元、驱动方法、栅极驱动电路和显示装置。移位寄存器单元包括：起始模块，用于在第一时钟信号输入端的控制下控制第一节点与起始电压输入端连接或断开；第一电容模块，第一端与第二时钟信号输入端连接，第二端与所述第一节点连接；第一节点控制模块，用于在第三节点的控制下控制第一节点与第一电平输入端连接或断开；电位控制模块，用于在第一节点的控制下控制第二节点与第二电平输入端连接或断开；第二电容模块；第二节点控制模块；输出模块；以及，第三节点控制模块。

Description

移位寄存器单元、移位寄存器单元的驱动方法、栅极驱动电路、栅极驱动电路的驱动方法和显示装置
相关申请的交叉引用
本申请主张在2017年7月20日在中国提交的中国专利申请号No.201710597800.X的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示驱动技术领域，尤其涉及一种移位寄存器单元、移位寄存器单元的驱动方法、栅极驱动电路、栅极驱动电路的驱动方法和显示装置。
背景技术
在显示领域，为了不断改善显示画面，提高用户体验，高清、高ppi(pixel per inch，每英寸像素个数)显示成了研究的热门。但随着像素数目的增加，包括多级移位寄存器单元的栅极驱动电路在一帧显示时间内所需扫描的行数增加，平均每一行栅极驱动信号的脉宽不断变窄，对移位寄存器的驱动能力的要求不断提高。
发明内容
本公开提供了一种移位寄存器单元，包括：
起始模块，分别与第一时钟信号输入端、第一节点和起始电压输入端连接，用于在所述第一时钟信号输入端的控制下控制所述第一节点与所述起始电压输入端连接或断开；
第一电容模块，第一端与第二时钟信号输入端连接，第二端与所述第一节点连接；
第一节点控制模块，分别与第三节点、第一电平输入端和所述第一节点连接，用于在所述第三节点的控制下控制所述第一节点与所述第一电平输入端连接或断开；
电位控制模块，分别与所述第一节点、第二电平输入端和第二节点连接， 用于在所述第一节点的控制下控制所述第二节点与所述第二电平输入端连接或断开；
第二电容模块，第一端与所述第二节点连接，第二端与栅极驱动信号输出端连接；
第二节点控制模块，分别与第三节点、第一电平输入端和所述第二节点连接；
输出模块，分别与所述第二节点、第三节点、所述栅极驱动信号输出端、第三时钟信号输入端和所述第一电平输入端连接；以及，
第三节点控制模块，分别与第四时钟信号输入端、第二电平输入端、所述第二节点和所述第三节点连接。
实施时，本公开所述的移位寄存器单元还包括第三电容模块；所述第三电容模块的第一端与所述第三节点连接，所述第三电容模块的第二端与所述第一电平输入端连接；
所述第二节点控制模块用于在所述第三节点的控制下，控制所述第二节点与所述第一电平输入端连接或断开；
所述第三节点控制模块用于在所述第二节点的控制下控制所述第三节点与所述第四时钟信号输入端连接或断开；
所述输出模块用于在所述第二节点的控制下控制所述栅极驱动信号输出端与所述第三时钟信号输入端连接或断开，在所述第三节点的控制下控制所述栅极驱动信号输出端与所述第一电平输入端连接或断开。
实施时，所述起始模块包括：起始晶体管，栅极与所述第一时钟信号输入端连接，第一极与所述第一节点连接，第二极与所述起始电压输入端连接；
所述第一电容模块包括第一电容；所述第一电容的第一端与第二时钟信号输入端连接，所述第一电容的第二端与所述第一节点连接；
所述第一节点控制模块包括：第一节点控制晶体管，栅极与所述第三节点连接，第一极与所述第一电平输入端连接，第二极与所述第一节点连接；
所述电位控制模块包括：电位控制晶体管，栅极与所述第一节点连接，第一极与所述第二节点连接，第二极与所述第二电平输入端连接。
实施时，第二电容模块包括第二电容；所述第二电容的第一端与所述第 二节点连接，所述第二电容的第二端与所述栅极驱动信号输出端连接；
所述第二节点控制模块包括：第二节点控制晶体管，栅极与第三节点连接，第一极与所述第一电平输入端连接，第二极与所述第二节点连接；
所述第三节点控制模块包括：第一控制晶体管，栅极与所述第四时钟信号输入端连接，第一极与所述第三节点连接，第二极与所述第二电平输入端连接；以及，
第二控制晶体管，栅极与所述第二节点连接，第一极与所述第三节点连接，第二极与所述第四时钟信号输入端连接；
所述输出模块包括：第一输出晶体管，栅极与所述第二节点连接，第一极与所述栅极驱动信号输出端连接，第二极与所述第三时钟信号输入端连接；以及，
第二输出晶体管，栅极与所述第三节点连接，第一极与所述第一电平输入端连接，第二极与所述栅极驱动信号输出端连接。
实施时，所述起始晶体管、所述第一节点控制晶体管、所述电位控制晶体管、所述第二节点控制晶体管、所述第一控制晶体管、所述第二控制晶体管、所述第一输出晶体管和所述第二输出晶体管都为p型晶体管，所述第二电平输入端为低电平输入端，所述第一电平输入端为高电平输入端；或者，
所述起始晶体管、所述第一节点控制晶体管、所述电位控制晶体管、所述第二节点控制晶体管、所述第一控制晶体管、所述第二控制晶体管、所述第一输出晶体管和所述第二输出晶体管都为n型晶体管，所述第二电平输入端为高电平输入端，所述第一电平输入端为低电平输入端。
本公开还提供了一种移位寄存器单元的驱动方法，用于驱动上述的移位寄存器单元，所述移位寄存器单元的驱动方法包括：在每一显示周期，
在第一阶段，起始信号输入端和第一时钟信号输入端都输入第二电平V2，第二时钟信号输入端、第三时钟信号输入端和第四时钟信号输入端都输入第一电平V1，起始单元控制所述起始信号输入端与第一节点连接，直至所述第一节点的电位变为V2-Vth1，Vth1为所述起始单元包括的起始晶体管的阈值电压；电位控制模块在所述第一节点的控制下控制第二节点与第二电平输入端连接，直至所述第二节点的电位变为V2-Vth1-Vth2，Vth2为电位控制模块 包括的电位控制晶体管的阈值电压；输出模块在所述第二节点的控制下控制栅极驱动信号输出端与所述第三时钟信号输入端连接，以使得所述栅极驱动信号输出端输出第一电平V1；
在第二阶段，第二时钟信号输入端输入第二电平V2，起始信号输入端、第一时钟信号输入端、第三时钟信号输入端和第四时钟信号输入端都输入第一电平V1，由于第一电容模块的第一端的电位由V1跳变为V2，使得所述第一节点的电位相应变为2V2-Vth1-V1，电位控制模块在所述第一节点的控制下控制所述第二节点与所述第二电平输入端连接，以使得所述第二节点的电位为第二电平V2；输出模块在所述第二节点的控制下控制栅极驱动信号输出端与所述第三时钟信号输入端连接，以使得所述栅极驱动信号输出端输出第一电平V1；
在第三阶段，第三时钟信号输入端输入第二电平V2，起始信号输入端、第一时钟信号输入端、第二时钟信号输入端和第四时钟信号输入端都输入第一电平V1，由于第一电容模块的第一端的电位由V2跳变为V1，使得所述第一节点的电位相应变为V2-Vth1，电位控制模块在所述第一节点的控制下控制所述第二节点与所述第二电平输入端之间断开；输出模块在所述第二节点的控制下控制栅极驱动信号输出端与所述第三时钟信号输入端连接，以使得所述栅极驱动信号输出端输出第二电平V2，由于第二电容模块的第二端的电位由V1跳变为V2，则所述第二节点的电位跳变为2V2-V1；
在第四阶段，第四时钟信号输入端输入第二电平V2，起始信号输入端、第一时钟信号输入端、第二时钟信号输入端和第三时钟信号输入端都输入第一电平V1，第三节点控制模块在所述第四时钟信号输入端的控制下控制所述第三节点与所述第二电平输入端连接，第二节点控制单元在所述第三节点的控制下控制所述第二节点与第一电平输入端连接，输出模块在第三节点的控制下控制所述栅极驱动信号输出端输出第一电平V1。
实施时，本公开所述的移位寄存器单元的驱动方法还包括：
在所述第一阶段、所述第二阶段和所述第三阶段，在所述第二节点的控制下，第三节点控制模块控制第三节点与所述第四时钟信号输入端连接，以使得所述第三节点的电位为第一电平V1，所述输出模块在所述第三节点的控 制下控制所述栅极驱动信号输出端与所述第一电平输入端之间断开。
实施时，由所述第一时钟信号输入端输入的第一时钟信号的占空比、由所述第二时钟信号输入端输入的第二时钟信号的占空比、由所述第三时钟信号输入端输入的第三时钟信号的占空比和由所述第四时钟信号输入端输入的第四时钟信号的占空比都为1/4；
所述第一时钟信号的周期、所述第二时钟信号的周期、所述第三时钟信号的周期和所述第四时钟信号的周期都为T；
所述第二时钟信号比所述第一时钟信号推迟T/4，所述第三时钟信号比所述第二时钟信号推迟T/4，所述第四时钟信号比所述第三时钟信号推迟T/4。
本公开还提供了一种栅极驱动电路，包括M个级联的上述的移位寄存器单元；M为大于1的整数。
本公开还提供了一种栅极驱动电路的驱动方法，所述栅极驱动电路包括M个级联的上述的移位寄存器单元，M为大于1的整数；
其中，所述栅极驱动电路的驱动方法包括：
对于M个级联的移位寄存器单元中的第4N+1级移位寄存器单元、第4N+2级移位寄存器单元、第4N+3级移位寄存器单元、第4N+4级移位寄存器单元，N为大于等于零的整数，且4N+4小于或等于所述M，
第4N+1级移位寄存器单元的第一时钟信号输入端接入第一时钟信号，第4N+1级移位寄存器单元的第二时钟信号输入端接入第二时钟信号，第4N+1级移位寄存器单元的第三时钟信号输入端接入第三时钟信号，第4N+1级移位寄存器单元的第四时钟信号输入端接入第四时钟信号；
第4N+2级移位寄存器单元的第一时钟信号输入端接入第二时钟信号，第4N+2级移位寄存器单元的第二时钟信号输入端接入第三时钟信号，第4N+2级移位寄存器单元的第三时钟信号输入端接入第四时钟信号，第4N+2级移位寄存器单元的第四时钟信号输入端接入第一时钟信号；
第4N+3级移位寄存器单元的第一时钟信号输入端接入第三时钟信号，第4N+3级移位寄存器单元的第二时钟信号输入端接入第四时钟信号，第4N+3级移位寄存器单元的第三时钟信号输入端接入第一时钟信号，第4N+3级移位寄存器单元的第四时钟信号输入端接入第二时钟信号；
第4N+4级移位寄存器单元的第一时钟信号输入端接入第四时钟信号，第4N+4级移位寄存器单元的第二时钟信号输入端接入第一时钟信号，第4N+4级移位寄存器单元的第三时钟信号输入端接入第二时钟信号，第4N+4级移位寄存器单元的第四时钟信号输入端接入第三时钟信号。
本公开还提供了一种显示装置，包括上述的栅极驱动电路。
附图说明
图1是本公开实施例所述的移位寄存器单元的结构图；
图2是本公开另一实施例所述的移位寄存器单元的结构图；
图3是本公开所述的移位寄存器单元的一具体实施例的电路图；
图4是本公开如图3所示的移位寄存器单元的具体实施例的工作时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。在实际操作时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
如图1所示，本公开实施例所述的移位寄存器单元包括：起始模块11、第一电容模块12、第一节点控制模块13、电位控制模块14、第二电容模块15、第二节点控制模块16、输出模块17及第三节点控制模块18。
其中，起始模块11分别与第一时钟信号输入端CKA、第一节点N1和起始电压输入端STV连接。起始模块11用于在所述第一时钟信号输入端CKA的控制下控制所述第一节点N1与所述起始电压输入端STV连接或断开。
第一电容模块12的第一端与第二时钟信号输入端CKB连接。第一电容 模块12的第二端与所述第一节点N1连接。
第一节点控制模块13分别与第三节点N3、输入第一电平V1的第一电平输入端和所述第一节点N1连接。第一节点控制模块13用于在所述第三节点N3的控制下控制所述第一节点N1与所述输入第一电平V1的第一电平输入端连接或断开。
电位控制模块14分别与所述第一节点N1、输入第二电平V2的第二电平输入端和第二节点N2连接。电位控制模块14用于在所述第一节点N1的控制下控制所述第二节点N2与所述输入第二电平V2的第二电平输入端连接或断开。
第二电容模块15的第一端与所述第二节点N2连接。第二电容模块15的第二端与栅极驱动信号输出端GOUT连接。
第二节点控制模块16分别与第三节点N3、输入第一电平V1的第一电平输入端和所述第二节点N2连接。
输出模块17分别与所述第二节点N2、所述第三节点N3、所述栅极驱动信号输出端GOUT、第三时钟信号输入端CKC和所述输入第一电平V1的第一电平输入端连接。
第三节点控制模块18分别与第四时钟信号输入端CKD、所述输入第二电平V2的第二电平输入端、所述第二节点N2和所述第三节点N3连接。
本公开实施例所述的移位寄存器单元通过设置第一电容模块12、第一节点控制模块13和电位控制模块14，并通过第一电容模块12在每一显示周期的第二阶段的自举作用来控制第一节点N1的电位，以使得在该第一节点N1的控制下电位控制模块14能够比相关技术更好的控制第二节点N2与第二电平输入端连接。本公开实施例所述的移位寄存器单元还通过第二电容模块15在每一显示周期的第三阶段的自举作用，以使得第二节点N2的电位在该第三阶段能够控制输出模块包括的输出晶体管会更好的打开，增强输出晶体管的驱动能力，实现窄脉宽下的信号的正常传递。
可选的，如图2所示，本公开实施例所述的移位寄存器单元还可以包括第三电容模块19。所述第三电容模块19的第一端与所述第三节点N3连接。所述第三电容模块19的第二端与所述第一电平输入端连接。
所述第二节点控制模块16用于在所述第三节点N3的控制下，控制所述第二节点N2与所述输入第一电平V1的第一电平输入端连接或断开。
所述第三节点控制模块18用于在所述第二节点N2的控制下控制所述第三节点N3与所述第四时钟信号输入端CKD连接或断开。
所述输出模块17用于在所述第二节点N2的控制下控制所述栅极驱动信号输出端GOUT与所述第三时钟信号输入端CKC连接或断开。所述输出模块17还用于在所述第三节点N3的控制下控制所述栅极驱动信号输出端GOUT与所述输入第一电平V1的第一电平输入端连接或断开。
在一些实施例中，本公开所述的移位寄存器单元中的第三电容模块19可以更好的维持第三节点的电位。
具体的，所述起始模块可以包括：起始晶体管。起始晶体管的栅极与所述第一时钟信号输入端连接，第一极与所述第一节点连接，第二极与所述起始电压输入端连接。
所述第一电容模块可以包括第一电容。所述第一电容的第一端与第二时钟信号输入端连接。所述第一电容的第二端与所述第一节点连接。
所述第一节点控制模块可以包括：第一节点控制晶体管。第一节点控制晶体管的栅极与所述第三节点连接，第一极与所述第一电平输入端连接，第二极与所述第一节点连接。
所述电位控制模块可以包括：电位控制晶体管。电位控制晶体管的栅极与所述第一节点连接，第一极与所述第二节点连接，第二极与所述第二电平输入端连接。
具体的，第二电容模块可以包括第二电容。所述第二电容的第一端与所述第二节点连接。所述第二电容的第二端与所述栅极驱动信号输出端连接。
所述第二节点控制模块可以包括：第二节点控制晶体管。第二节点控制晶体管的栅极与第三节点连接，第一极与所述第一电平输入端连接，第二极与所述第二节点连接。
所述第三节点控制模块可以包括：第一控制晶体管和第二控制晶体管。第一控制晶体管的栅极与所述第四时钟信号输入端连接，第一极与所述第三节点连接，第二极与所述第二电平输入端连接。
第二控制晶体管的栅极与所述第二节点连接，第一极与所述第三节点连接，第二极与所述第四时钟信号输入端连接。
所述输出模块可以包括：第一输出晶体管和第二输出晶体管。第一输出晶体管的栅极与所述第二节点连接，第一极与所述栅极驱动信号输出端连接，第二极与所述第三时钟信号输入端连接。
第二输出晶体管的栅极与所述第三节点连接，第一极与所述第一电平输入端连接，第二极与所述栅极驱动信号输出端连接。
在一些实施例中，所述起始晶体管、所述第一节点控制晶体管、所述电位控制晶体管、所述第二节点控制晶体管、所述第一控制晶体管、所述第二控制晶体管、所述第一输出晶体管和所述第二输出晶体管可以都为p型晶体管。所述第一电平输入端为高电平输入端，所述第二电平输入端为高电平输入端。
在另一些实施例中，所述起始晶体管、所述第一节点控制晶体管、所述电位控制晶体管、所述第二节点控制晶体管、所述第一控制晶体管、所述第二控制晶体管、所述第一输出晶体管和所述第二输出晶体管可以都为n型晶体管。所述第一电平输入端为低电平输入端，所述第二电平输入端为高电平输入端。
下面通过一具体实施例来说明本公开所述的移位寄存器单元。
如图3所示，本公开所述的移位寄存器单元的一具体实施例包括起始模块11、第一电容模块12、第一节点控制模块13、电位控制模块14、第二电容模块15、第二节点控制模块16、输出模块17、第三节点控制模块18和第三电容模块19。
其中，所述起始模块11包括：起始晶体管M1。起始晶体管M1的栅极与所述第一时钟信号输入端CKA连接，源极与所述第一节点N1连接，漏极与所述起始电压输入端STV连接。
所述第一电容模块12包括第一电容C1。所述第一电容C1的第一端与第二时钟信号输入端CKB连接。所述第一电容C1的第二端与所述第一节点N1连接。
所述第一节点控制模块13包括：第一节点控制晶体管M2。第一节点控 制晶体管M2的栅极与所述第三节点N3连接，漏极与输入高电平VGH的高电平输入端连接，源极与所述第一节点N1连接。
所述电位控制模块14包括：电位控制晶体管M3。电位控制晶体管M3的栅极与所述第一节点N1连接，源极与所述第二节点N2连接，漏极与输入低电平VGL的低电平输入端连接。
所述第二电容模块15包括第二电容C2。所述第二电容C2的第一端与所述第二节点N2连接。所述第二电容C2的第二端与所述栅极驱动信号输出端GOUT连接。
所述第二节点控制模块16包括：第二节点控制晶体管M6。第二节点控制晶体管M6的栅极与第三节点N3连接，漏极与所述输入高电平VGH的高电平输入端连接，源极与所述第二节点N2连接。
所述第三节点控制模块18包括：第一控制晶体管M4和第二控制晶体管M5。第一控制晶体管M4的栅极与所述第四时钟信号输入端CKD连接，源极与所述第三节点N3连接，漏极与输入低电平VGL的低电平输入端连接。
第二控制晶体管M5的栅极与所述第二节点N2连接，源极与所述第三节点N3连接，漏极与所述第四时钟信号输入端CKD连接。
所述输出模块17包括：第一输出晶体管M7和第二输出晶体管M8。第一输出晶体管M7的栅极与所述第二节点N2连接，源极与所述栅极驱动信号输出端GOUT连接，漏极与所述第三时钟信号输入端CKC连接。
第二输出晶体管M8的栅极与所述第三节点N3连接，漏极与所述输入高电平VGH的高电平输入端连接，源极与所述栅极驱动信号输出端GOUT连接。
所述第三电容模块19包括第三电容C3。所述第三电容C3的第一端与所述第三节点N3连接。所述第三电容C3的第二端与所述输入高电平VGH的高电平输入端连接。
在图3所示的实施例中，所有的晶体管都为p型晶体管，在实际操作时，以上晶体管也可以被替换为n型晶体管，在此对晶体管的类型不作限定。
在实际操作时，GOUT通过依次串联的负载电阻和负载电容接地。
如图4所示，本公开如图3所示的移位寄存器单元的具体实施例在工作 时，在每一显示周期，包括以下几个阶段。
在第一阶段t1，STV和CKA都输入低电平VGL，CKB、CKC和CKD都输入高电平VGH，M1开启，将STV输入的低电平传递到N1，由于p型晶体管传递低电平有阈值损失，则N1的电位变为VGL-Vth1，Vth1为所述起始单元包括的起始晶体管的阈值电压(由于M1为p型晶体管，所以Vth1为负值)；M3开启，直至N2的电位变为VGL-Vth1-Vth2，Vth2为电位控制模块包括的电位控制晶体管的阈值电压(由于M2为p型晶体管，所以Vth2为负值)；在N2的控制下，M7开启，GOUT与CKC连接，以使得GOUT输出高电平VGH；在N2的控制下，M5开启，以控制N3与CKD连接，以使得N3的电位为高电平VGH，在N3的控制下，M8断开，以控制GOUT与输入高电平VGH的高电平输入端之间断开。
在第二阶段t2，CKB输入低电平VGL，STV、CKA、CKC和CKD都输入高电平VGH，由于C1的第一端的电位由VGH跳变为VGL，使得N1的电位相应变为2VGL-Vth1-VGH，在N1的控制下，M3开启，以控制N2与输入低电平VGL的低电平输入端连接，以使得N2的电位为低电平VGL；在N2的控制下，M7开启，以控制GOUT与CKC端连接，以使得GOUT输出高电平VGH；在N2的控制下，M5开启，以控制N3与CKD连接，以使得N3的电位为高电平VGH，在N3的控制下，M8断开，以控制GOUT与所述输入高电平VGH的高电平输入端之间断开。
在第三阶段t3，CKC输入低电平VGL，STV、CKA、CKB和CKD都输入高电平VGH，由于C1的第一端的电位由VGL跳变为VGH，使得N1的电位相应变为VGL-Vth1，在N1的控制下，M3断开，以控制N2与输入低电平VGL的低电平输入端之间断开；在N2的控制下，M7开启，以控制GOUT与CKC连接，以使得GOUT输出低电平VGL，由于C2的第二端的电位由VGH跳变为VGL，则N2的电位跳变为2VGL-VGH；在所述第二节点N2的控制下，M5开启，以控制N3与CKD连接，以使得N3的电位为高电平VGH，在N3的控制下，M8关断，以控制GOUT与输入高电平VGH的高电平输入端之间断开。
在第四阶段t4，CKD输入低电平VGL，STV、CKA、CKB和CKC都输 入高电平VGH，在CKD的控制下，M4开启，以控制N3与输入低电平VGL的低电平输入端连接，在N3的控制下，M6开启，以控制N2与输入高电平VGH的高电平输入端连接，在N2的控制下，M7断开；在N3的控制下，M8开启，以控制GOUT输出高电平VGH。
在第五阶段t5，CKA输入低电平VGL，STV、CKB、CKC和CKD都输入高电平VGH，M1开启，STV输入的高电平传递至N1，以使得M3断开，N2的电位仍旧为高电平，N3的电位仍旧为低电平，M7断开，M8开启，GOUT仍旧输出高电平VGH。
在第四阶段t4结束之后，GOUT仍旧输出高电平VGH，直至STV和CKA再一次同时输入低电平。
本公开所述的移位寄存器单元的具体实施例通过设置C1、M2和M3，并利用两次电容的自举效应：在第二阶段t2第一电容C1的自举效应，以使得N1的电位能够控制M3很好的打开，从而使得N2接入VGL；在第三阶段t3第二电容C2的自举效应，以使得N2的电位能够控制输出模块包括的第一输出晶体管M7会更好的打开，增强第一输出晶体管M7的驱动能力，实现窄脉宽下的信号的正常传递。
如图4所示，CKA输入的第一时钟信号的占空比、CKB输入的第二时钟信号的占空比、CKC输入的第三时钟信号的占空比和CKD输入的第四时钟信号的占空比可以都为1/4。
所述第一时钟信号的周期、所述第二时钟信号的周期、所述第三时钟信号的周期和所述第四时钟信号的周期可以都为T。
所述第二时钟信号比所述第一时钟信号推迟T/4，所述第三时钟信号比所述第二时钟信号推迟T/4，所述第四时钟信号比所述第三时钟信号推迟T/4。
本公开实施例所述的移位寄存器单元的驱动方法，用于驱动上述的移位寄存器单元，所述移位寄存器单元的驱动方法包括：在每一显示周期，包括以下几个阶段。
在第一阶段，起始信号输入端和第一时钟信号输入端都输入第二电平V2，第二时钟信号输入端、第三时钟信号输入端和第四时钟信号输入端都输入第一电平V1，起始单元控制所述起始信号输入端与第一节点连接，直至所述第 一节点的电位变为V2-Vth1，Vth1为所述起始单元包括的起始晶体管的阈值电压；电位控制模块在所述第一节点的控制下控制第二节点与第二电平输入端连接，直至所述第二节点的电位变为V2-Vth1-Vth2，Vth2为电位控制模块包括的电位控制晶体管的阈值电压；输出模块在所述第二节点的控制下控制栅极驱动信号输出端与所述第三时钟信号输入端连接，以使得所述栅极驱动信号输出端输出第一电平V1。
在第二阶段，第二时钟信号输入端输入第二电平V2，起始信号输入端、第一时钟信号输入端、第三时钟信号输入端和第四时钟信号输入端都输入第一电平V1，由于第一电容模块的第一端的电位由V1跳变为V2，使得所述第一节点的电位相应变为2V2-Vth1-V1，电位控制模块在所述第一节点的控制下控制所述第二节点与所述第二电平输入端连接，以使得所述第二节点的电位为第二电平V2；输出模块在所述第二节点的控制下控制栅极驱动信号输出端与所述第三时钟信号输入端连接，以使得所述栅极驱动信号输出端输出第一电平V1。
在第三阶段，第三时钟信号输入端输入第二电平V2，起始信号输入端、第一时钟信号输入端、第二时钟信号输入端和第四时钟信号输入端都输入第一电平V1，由于第一电容模块的第一端的电位由V2跳变为V1，使得所述第一节点的电位相应变为V2-Vth1，电位控制模块在所述第一节点的控制下控制所述第二节点与所述第二电平输入端之间断开；输出模块在所述第二节点的控制下控制栅极驱动信号输出端与所述第三时钟信号输入端连接，以使得所述栅极驱动信号输出端输出第二电平V2，由于第二电容模块的第二端的电位由V1跳变为V2，则所述第二节点的电位跳变为2V2-V1。
在第四阶段，第四时钟信号输入端输入第二电平V2，起始信号输入端、第一时钟信号输入端、第二时钟信号输入端和第三时钟信号输入端都输入第一电平V1，第三节点控制模块在所述第四时钟信号输入端的控制下控制所述第三节点与所述第二电平输入端连接，第二节点控制单元在所述第三节点的控制下控制所述第二节点与第一电平输入端连接，输出模块在第三节点的控制下控制所述栅极驱动信号输出端输出第一电平V1。
在本公开实施例所述的移位寄存器单元的驱动方法中，以通过第一电容 模块在每一显示周期的第二阶段的自举作用来控制第一节点的电位，以使得在该第一节点的控制下电位控制模块能够比相关技术更好的控制第二节点与第二电平输入端连接。本公开实施例所述的移位寄存器单元还通过第二电容模块15在每一显示周期的第三阶段的自举作用，以使得第二节点N2的电位在该第三阶段能够控制输出模块包括的输出晶体管会更好的打开，增强输出晶体管的驱动能力，实现窄脉宽下的信号的正常传递。
具体的，本公开实施例所述的移位寄存器单元的驱动方法还包括：
在所述第一阶段、所述第二阶段和所述第三阶段，在所述第二节点的控制下，第三节点控制模块控制第三节点与所述第四时钟信号输入端连接，以使得所述第三节点的电位为第一电平V1，所述输出模块在所述第三节点的控制下控制所述栅极驱动信号输出端与所述第一电平输入端之间断开。
具体的，由所述第一时钟信号输入端输入的第一时钟信号的占空比、由所述第二时钟信号输入端输入的第二时钟信号的占空比、由所述第三时钟信号输入端输入的第三时钟信号的占空比和由所述第四时钟信号输入端输入的第四时钟信号的占空比可以都为1/4。
所述第一时钟信号的周期、所述第二时钟信号的周期、所述第三时钟信号的周期和所述第四时钟信号的周期可以都为T。
所述第二时钟信号比所述第一时钟信号推迟T/4，所述第三时钟信号比所述第二时钟信号推迟T/4，所述第四时钟信号比所述第三时钟信号推迟T/4。
本公开实施例所述的栅极驱动电路包括M个级联的上述的移位寄存器单元；M为大于1的整数。
其中，M个级联的移位寄存器单元中的第4N+1级移位寄存器单元、第4N+2级移位寄存器单元、第4N+3级移位寄存器单元和第4N+4级移位寄存器单元的工作过程如下所述，其中，N为大于等于零的整数，且4N+4小于或等于所述M。
第4N+1级移位寄存器单元的第一时钟信号输入端接入第一时钟信号，第4N+1级移位寄存器单元的第二时钟信号输入端接入第二时钟信号，第4N+1级移位寄存器单元的第三时钟信号输入端接入第三时钟信号，第4N+1级移位寄存器单元的第四时钟信号输入端接入第四时钟信号。
此时，第4N+2级移位寄存器单元的第一时钟信号输入端接入第二时钟信号，第4N+2级移位寄存器单元的第二时钟信号输入端接入第三时钟信号，第4N+2级移位寄存器单元的第三时钟信号输入端接入第四时钟信号，第4N+2级移位寄存器单元的第四时钟信号输入端接入第一时钟信号。
同时，第4N+3级移位寄存器单元的第一时钟信号输入端接入第三时钟信号，第4N+3级移位寄存器单元的第二时钟信号输入端接入第四时钟信号，第4N+3级移位寄存器单元的第三时钟信号输入端接入第一时钟信号，第4N+3级移位寄存器单元的第四时钟信号输入端接入第二时钟信号。
与此同时，第4N+4级移位寄存器单元的第一时钟信号输入端接入第四时钟信号，第4N+4级移位寄存器单元的第二时钟信号输入端接入第一时钟信号，第4N+4级移位寄存器单元的第三时钟信号输入端接入第二时钟信号，第4N+4级移位寄存器单元的第四时钟信号输入端接入第三时钟信号。
本公开实施例所述的显示装置包括上述的栅极驱动电路。
本公开实施例所述的显示装置可以包括液晶显示装置，例如液晶面板、液晶电视、手机、液晶显示器。除了液晶显示装置外，本公开实施例所述的还可以包括有机发光显示器或者其他类型的显示装置，比如电子阅读器等。
以上所述是本公开的可选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (18)

  1. 一种移位寄存器单元，包括：
    起始模块，分别与第一时钟信号输入端、第一节点和起始电压输入端连接，用于在所述第一时钟信号输入端的控制下控制所述第一节点与所述起始电压输入端连接或断开；
    第一电容模块，第一端与第二时钟信号输入端连接，第二端与所述第一节点连接；
    第一节点控制模块，分别与第三节点、第一电平输入端和所述第一节点连接，用于在所述第三节点的控制下控制所述第一节点与所述第一电平输入端连接或断开；
    电位控制模块，分别与所述第一节点、第二电平输入端和第二节点连接，用于在所述第一节点的控制下控制所述第二节点与所述第二电平输入端连接或断开；
    第二电容模块，第一端与所述第二节点连接，第二端与栅极驱动信号输出端连接；
    第二节点控制模块，分别与第三节点、第一电平输入端和所述第二节点连接；
    输出模块，分别与所述第二节点、第三节点、所述栅极驱动信号输出端、第三时钟信号输入端和所述第一电平输入端连接；以及，
    第三节点控制模块，分别与第四时钟信号输入端、第二电平输入端、所述第二节点和所述第三节点连接。
  2. 如权利要求1所述的移位寄存器单元，，还包括第三电容模块；所述第三电容模块的第一端与所述第三节点连接，所述第三电容模块的第二端与所述第一电平输入端连接；
    所述第二节点控制模块用于在所述第三节点的控制下，控制所述第二节点与所述第一电平输入端连接或断开；
    所述第三节点控制模块用于在所述第二节点的控制下控制所述第三节点与所述第四时钟信号输入端连接或断开；
    所述输出模块用于在所述第二节点的控制下控制所述栅极驱动信号输出端与所述第三时钟信号输入端连接或断开，在所述第三节点的控制下控制所述栅极驱动信号输出端与所述第一电平输入端连接或断开。
  3. 如权利要求2所述的移位寄存器单元，其中，所述起始模块包括：起始晶体管；所述起始晶体管的栅极与所述第一时钟信号输入端连接，第一极与所述第一节点连接，第二极与所述起始电压输入端连接。
  4. 如权利要求3所述的移位寄存器单元，其中，所述第一电容模块包括第一电容；所述第一电容的第一端与第二时钟信号输入端连接，所述第一电容的第二端与所述第一节点连接。
  5. 如权利要求4所述的移位寄存器单元，其中，所述第一节点控制模块包括：第一节点控制晶体管；所述第一节点控制晶体管的栅极与所述第三节点连接，第一极与所述第一电平输入端连接，第二极与所述第一节点连接。
  6. 如权利要求5所述的移位寄存器单元，其中，所述电位控制模块包括：电位控制晶体管；所述电位控制晶体管的栅极与所述第一节点连接，第一极与所述第二节点连接，第二极与所述第二电平输入端连接。
  7. 如权利要求6所述的移位寄存器单元，其中，所述第二电容模块包括第二电容；所述第二电容的第一端与所述第二节点连接，所述第二电容的第二端与所述栅极驱动信号输出端连接。
  8. 如权利要求7所述的移位寄存器单元，其中，所述第二节点控制模块包括：第二节点控制晶体管；所述第二节点控制晶体管的栅极与第三节点连接，第一极与所述第一电平输入端连接，第二极与所述第二节点连接。
  9. 如权利要求8所述的移位寄存器单元，其中，所述第三节点控制模块包括：第一控制晶体管和第二控制晶体管；所述第一控制晶体管的栅极与所述第四时钟信号输入端连接，第一极与所述第三节点连接，第二极与所述第二电平输入端连接；
    所述第二控制晶体管的栅极与所述第二节点连接，第一极与所述第三节点连接，第二极与所述第四时钟信号输入端连接。
  10. 如权利要求9所述的移位寄存器单元，其中，所述输出模块包括：第一输出晶体管和第二输出晶体管；所述第一输出晶体管的栅极与所述第二 节点连接，第一极与所述栅极驱动信号输出端连接，第二极与所述第三时钟信号输入端连接；
    所述第二输出晶体管的栅极与所述第三节点连接，第一极与所述第一电平输入端连接，第二极与所述栅极驱动信号输出端连接。
  11. 如权利要求10所述的移位寄存器单元，其中，所述起始晶体管、所述第一节点控制晶体管、所述电位控制晶体管、所述第二节点控制晶体管、所述第一控制晶体管、所述第二控制晶体管、所述第一输出晶体管和所述第二输出晶体管都为p型晶体管，所述第二电平输入端为低电平输入端，所述第一电平输入端为高电平输入端。
  12. 如权利要求10所述的移位寄存器单元，其中，所述起始晶体管、所述第一节点控制晶体管、所述电位控制晶体管、所述第二节点控制晶体管、所述第一控制晶体管、所述第二控制晶体管、所述第一输出晶体管和所述第二输出晶体管都为n型晶体管，所述第二电平输入端为高电平输入端，所述第一电平输入端为低电平输入端。
  13. 一种移位寄存器单元的驱动方法，用于驱动如权利要求至12中任一权利要求所述的移位寄存器单元，其中，所述移位寄存器单元的驱动方法包括：在每一显示周期，
    在第一阶段，起始信号输入端和第一时钟信号输入端都输入第二电平V2，第二时钟信号输入端、第三时钟信号输入端和第四时钟信号输入端都输入第一电平V1，起始单元控制所述起始信号输入端与第一节点连接，直至所述第一节点的电位变为V2-Vth1，Vth1为所述起始单元包括的起始晶体管的阈值电压；电位控制模块在所述第一节点的控制下控制第二节点与第二电平输入端连接，直至所述第二节点的电位变为V2-Vth1-Vth2，Vth2为电位控制模块包括的电位控制晶体管的阈值电压；输出模块在所述第二节点的控制下控制栅极驱动信号输出端与所述第三时钟信号输入端连接，以使得所述栅极驱动信号输出端输出第一电平V1；
    在第二阶段，第二时钟信号输入端输入第二电平V2，起始信号输入端、第一时钟信号输入端、第三时钟信号输入端和第四时钟信号输入端都输入第一电平V1，由于第一电容模块的第一端的电位由V1跳变为V2，使得所述第 一节点的电位相应变为2V2-Vth1-V1，电位控制模块在所述第一节点的控制下控制所述第二节点与所述第二电平输入端连接，以使得所述第二节点的电位为第二电平V2；输出模块在所述第二节点的控制下控制栅极驱动信号输出端与所述第三时钟信号输入端连接，以使得所述栅极驱动信号输出端输出第一电平V1；
    在第三阶段，第三时钟信号输入端输入第二电平V2，起始信号输入端、第一时钟信号输入端、第二时钟信号输入端和第四时钟信号输入端都输入第一电平V1，由于第一电容模块的第一端的电位由V2跳变为V1，使得所述第一节点的电位相应变为V2-Vth1，电位控制模块在所述第一节点的控制下控制所述第二节点与所述第二电平输入端之间断开；输出模块在所述第二节点的控制下控制栅极驱动信号输出端与所述第三时钟信号输入端连接，以使得所述栅极驱动信号输出端输出第二电平V2，由于第二电容模块的第二端的电位由V1跳变为V2，则所述第二节点的电位跳变为2V2-V1；
    在第四阶段，第四时钟信号输入端输入第二电平V2，起始信号输入端、第一时钟信号输入端、第二时钟信号输入端和第三时钟信号输入端都输入第一电平V1，第三节点控制模块在所述第四时钟信号输入端的控制下控制所述第三节点与所述第二电平输入端连接，第二节点控制单元在所述第三节点的控制下控制所述第二节点与第一电平输入端连接，输出模块在第三节点的控制下控制所述栅极驱动信号输出端输出第一电平V1。
  14. 如权利要求13所述的移位寄存器单元的驱动方法，还包括：
    在所述第一阶段、所述第二阶段和所述第三阶段，在所述第二节点的控制下，第三节点控制模块控制第三节点与所述第四时钟信号输入端连接，以使得所述第三节点的电位为第一电平V1，所述输出模块在所述第三节点的控制下控制所述栅极驱动信号输出端与所述第一电平输入端之间断开。
  15. 如权利要求13或14所述的移位寄存器单元的驱动方法，其中，由所述第一时钟信号输入端输入的第一时钟信号的占空比、由所述第二时钟信号输入端输入的第二时钟信号的占空比、由所述第三时钟信号输入端输入的第三时钟信号的占空比和由所述第四时钟信号输入端输入的第四时钟信号的占空比都为1/4；
    所述第一时钟信号的周期、所述第二时钟信号的周期、所述第三时钟信号的周期和所述第四时钟信号的周期都为T；
    所述第二时钟信号比所述第一时钟信号推迟T/4，所述第三时钟信号比所述第二时钟信号推迟T/4，所述第四时钟信号比所述第三时钟信号推迟T/4。
  16. 一种栅极驱动电路，包括M个级联的如权利要求1至12任一项所述的移位寄存器单元；M为大于1的整数。
  17. 一种栅极驱动电路的驱动方法，所述栅极驱动电路包括M个级联的如权利要求1至12任一项所述的移位寄存器单元，M为大于1的整数；
    其中，所述栅极驱动电路的驱动方法包括：
    对于M个级联的移位寄存器单元中的第4N+1级移位寄存器单元、第4N+2级移位寄存器单元、第4N+3级移位寄存器单元、第4N+4级移位寄存器单元，N为大于等于零的整数，且4N+4小于或等于所述M，
    第4N+1级移位寄存器单元的第一时钟信号输入端接入第一时钟信号，第4N+1级移位寄存器单元的第二时钟信号输入端接入第二时钟信号，第4N+1级移位寄存器单元的第三时钟信号输入端接入第三时钟信号，第4N+1级移位寄存器单元的第四时钟信号输入端接入第四时钟信号；
    第4N+2级移位寄存器单元的第一时钟信号输入端接入第二时钟信号，第4N+2级移位寄存器单元的第二时钟信号输入端接入第三时钟信号，第4N+2级移位寄存器单元的第三时钟信号输入端接入第四时钟信号，第4N+2级移位寄存器单元的第四时钟信号输入端接入第一时钟信号；
    第4N+3级移位寄存器单元的第一时钟信号输入端接入第三时钟信号，第4N+3级移位寄存器单元的第二时钟信号输入端接入第四时钟信号，第4N+3级移位寄存器单元的第三时钟信号输入端接入第一时钟信号，第4N+3级移位寄存器单元的第四时钟信号输入端接入第二时钟信号；
    第4N+4级移位寄存器单元的第一时钟信号输入端接入第四时钟信号，第4N+4级移位寄存器单元的第二时钟信号输入端接入第一时钟信号，第4N+4级移位寄存器单元的第三时钟信号输入端接入第二时钟信号，第4N+4级移位寄存器单元的第四时钟信号输入端接入第三时钟信号。
  18. 一种显示装置，包括如权利要求16所述的栅极驱动电路。
PCT/CN2018/096221 2017-07-20 2018-07-19 移位寄存器单元、移位寄存器单元的驱动方法、栅极驱动电路、栅极驱动电路的驱动方法和显示装置 WO2019015630A1 (zh)

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