WO2018233306A1 - 移位寄存器及其驱动方法、栅极驱动电路、显示装置 - Google Patents

移位寄存器及其驱动方法、栅极驱动电路、显示装置 Download PDF

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Publication number
WO2018233306A1
WO2018233306A1 PCT/CN2018/076384 CN2018076384W WO2018233306A1 WO 2018233306 A1 WO2018233306 A1 WO 2018233306A1 CN 2018076384 W CN2018076384 W CN 2018076384W WO 2018233306 A1 WO2018233306 A1 WO 2018233306A1
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WIPO (PCT)
Prior art keywords
pull
voltage
node
transistor
terminal
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PCT/CN2018/076384
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English (en)
French (fr)
Inventor
杜瑞芳
曹子君
马小叶
马睿
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US16/077,369 priority Critical patent/US10950196B2/en
Publication of WO2018233306A1 publication Critical patent/WO2018233306A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register and a driving method thereof, a gate driving circuit, and a display device.
  • Liquid crystal display has the advantages of low radiation, small size and low energy consumption, and is widely used in electronic products such as notebook computers, flat-panel televisions or mobile phones.
  • a GOA Gate Driver on Array
  • the GOA circuit scans the gate lines progressively from top to bottom or bottom to top. For example, scanning the gate line from the top to the bottom, after scanning the last row of gate lines, the GOA circuit needs to return from the last line to the first line to enter the scanning step of the next image frame.
  • the above-mentioned time from the last line back to the first line requires no signal output from any shift register in the GOA circuit, and this time is blanking time (Blank).
  • Embodiments of the present disclosure provide a shift register and a driving method thereof, a gate driving circuit, and a display device.
  • An aspect of an embodiment of the present disclosure provides a shift register including a pull-up control circuit, a pull-up circuit, a pull-down control circuit, a pull-down circuit, a reset circuit, and a noise reduction control circuit;
  • the pull-up control circuit is connected to a signal input end And a pull-up node, configured to output, by the signal input end, a voltage of the signal input end to the pull-up node;
  • the pull-up circuit is connected to the pull-up node, the first clock signal input end, and a signal output end, configured to store a potential of the pull-up node, and output a voltage of the first clock signal input end to the signal output end under the control of the pull-up node;
  • the pull-down control circuit is connected a clock signal input terminal, the pull-up node, a pull-down node, and a first voltage terminal, configured to output a voltage of the second clock signal input end to the pull-down node under control of the second clock signal input end Or for pulling down
  • the noise reduction control circuit is composed of a first transistor; a gate and a first pole of the first transistor are connected to the noise reduction control signal end, and a second pole is connected to the pull-down node.
  • the pull-up control circuit includes a second transistor; a gate and a first pole of the second transistor are connected to the signal input terminal, and a second pole is connected to the pull-up node.
  • the pull-up circuit includes a driving transistor and a storage capacitor; a gate of the driving transistor is connected to the pull-up node, a first pole is connected to the first clock signal input terminal, a second pole is connected to the signal output The terminal is connected; one end of the storage capacitor is connected to the pull-up node, and the other end is connected to the signal output end.
  • the pull-down control circuit includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; a gate and a first pole of the third transistor are connected to the second clock signal input end, and the second pole Connected to a gate of the fourth transistor; a first pole of the fourth transistor is coupled to the second clock signal input terminal, a second pole is coupled to the pull-down node; and a gate of the fifth transistor Connecting the pull-up node, the first pole is connected to the second pole of the third transistor, the second pole is connected to the first voltage end; the gate of the sixth transistor is connected to the pull-up node, One pole is connected to the pull-down node, and the second pole is connected to the first voltage terminal.
  • the pull-down circuit includes a seventh transistor and an eighth transistor; a gate of the seventh transistor is connected to the pull-down node, a first pole is connected to the pull-up node, and a second pole is connected to the first voltage terminal The gate of the eighth transistor is connected to the pull-down node, the first pole is connected to the signal output end, and the second pole is connected to the first voltage terminal.
  • the reset circuit includes a ninth transistor and a tenth transistor; a gate of the ninth transistor is connected to the reset signal terminal, a first pole is connected to the pull-up node, and a second pole is connected to the first voltage The terminal is connected; the gate of the tenth transistor is connected to the reset signal terminal, the first pole is connected to the signal output terminal, and the second pole is connected to the first voltage terminal.
  • the auxiliary noise reduction module is further connected to the second clock signal input end, the signal output end and the first voltage end for controlling under the control of the second clock signal input end.
  • the voltage at the signal output is pulled down to the voltage at the first voltage terminal.
  • the auxiliary noise reduction module includes an eleventh transistor; a gate of the eleventh transistor is connected to the second clock signal input end, and a first pole is connected to the signal output end, and the second pole is connected The first voltage terminals are connected.
  • the pull-up control circuit is further connected to the second clock signal input end for outputting the voltage of the signal input terminal to the pull-up node under the control of the second clock signal input end;
  • the pull-up control circuit further includes a twelfth transistor; a gate of the twelfth transistor is connected to the second clock signal input end, a first pole is connected to the signal input end, and a second pole is connected to the pull-up node connection.
  • a gate driving circuit including a plurality of cascaded shift registers as described above; a signal input end of the first stage shift register is coupled to the start signal terminal; In addition to the first stage shift register, the signal output of the shift register of the previous stage is connected to the signal input of the shift register of the next stage; except for the shift register of the next stage, the signal of the shift register of the next stage The output end is connected to the reset signal end of the shift register of the previous stage; the reset signal end of the last stage shift register is connected to the start signal end.
  • a display device including the above-described gate driving circuit is provided.
  • a method for driving any of the shift registers as described above, in an image frame comprising: in an input phase: under control of a signal input, The pull-up control circuit outputs the voltage of the signal input terminal to the pull-up node; the pull-up circuit stores the potential of the pull-up node, and outputs the voltage of the first clock signal input terminal to the signal output under the control of the pull-up node Under the control of the pull-up node, the pull-down control circuit pulls down the voltage of the pull-down node to the voltage of the first voltage terminal; in the output stage: the pull-up circuit outputs the signal stored in the previous stage to the pull-up node, Under the control of the pull-up node, the pull-up circuit outputs a voltage of the first clock signal input terminal to the signal output end, and the signal output terminal outputs a gate scan signal; at the pull-up node Under control, the pull-down control circuit pulls down the voltage of the pull-
  • the method further includes: at the input phase and the reset phase: at the second clock signal input Under control, the auxiliary noise reduction module pulls down the voltage of the signal output terminal to the voltage of the first voltage terminal.
  • FIG. 1 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a specific structure corresponding to each module in FIG. 1;
  • FIG. 3 is a schematic structural diagram of another shift register according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a specific structure corresponding to each module in FIG. 3;
  • Figure 5 is a timing diagram of respective control signals for driving the shift register shown in Figure 2 or Figure 4;
  • FIG. 6 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • 10- pull-up control circuit 20-pull-up circuit; 30-pull-down control circuit; 40-down-down circuit; 50-reset circuit; 60-noise reduction control circuit; 70-auxiliary noise reduction module; I-signal input terminal; CLK - first clock signal terminal input terminal; CLKB - second clock signal input terminal; O-signal output terminal; R-reset signal terminal; VSS - first voltage terminal; STV_in - noise reduction control signal terminal.
  • the embodiment of the present disclosure provides a shift register, as shown in FIG. 1, including a pull-up control circuit 10, a pull-up circuit 20, a pull-down control circuit 30, a pull-down circuit 40, a reset circuit 50, and a noise reduction control circuit 60.
  • the pull-up control circuit 10 is connected to the signal input terminal I and the pull-up node PU.
  • the pull-up control circuit 10 is configured to output the voltage of the signal input terminal I to the pull-up node PU under the control of the signal input terminal 1.
  • the pull-up circuit 20 is connected to the pull-up node PU, the first clock signal input terminal CLK, and the signal output terminal O.
  • the pull-up circuit 20 is configured to store the potential of the pull-up node PU and output the voltage of the first clock signal input terminal CLK to the signal output terminal O under the control of the pull-up node PU.
  • the pull-down control circuit 30 is connected to the second clock signal input terminal CLKB, the pull-up node PU, the pull-down node PD, and the first voltage terminal VSS.
  • the pull-down control circuit 30 is configured to output the voltage of the second clock signal input terminal CLKB to the pull-down node PD under the control of the second clock signal input terminal CLKB.
  • the pull-down control circuit 30 is configured to pull down the voltage of the pull-down node PD to the voltage of the first voltage terminal VSS under the control of the pull-up node PU.
  • the pull-down circuit 40 is connected to the pull-down node PD, the pull-up node PU, the signal output terminal O, and the first voltage terminal VSS.
  • the pull-down circuit 40 is configured to pull down the voltage of the pull-up node PU and the signal output terminal O to the voltage of the first voltage terminal VSS under the control of the pull-down node PD, respectively.
  • the reset circuit 50 is connected to the reset signal terminal R, the pull-up node PU, the signal output terminal O, and the first voltage terminal VSS.
  • the reset circuit 50 is configured to pull down the voltage of the pull-up node PU and the signal output terminal O to the voltage of the first voltage terminal VSS under the control of the reset signal terminal R, respectively.
  • the noise reduction control circuit 60 is connected to the noise reduction control signal terminal STV_in and the pull-down node PD.
  • the noise reduction control circuit 60 is configured to output the voltage of the noise reduction control signal terminal STV_in to the pull-down node PD under the control of the noise reduction control signal terminal STV_in at a blanking time of an image frame, so that the pull-down node PD is pulled down.
  • the pull-down circuit 40 pulls down the voltage of the pull-up node PU and the signal output terminal O to the voltage of the first voltage terminal VSS, respectively.
  • the potential of the pull-up node PU can be controlled by the pull-up control circuit 10 in an image frame. Based on this, under the control of the pull-up node PU, the pull-up circuit 20 can output the voltage of the first clock signal input terminal CLK to the signal output terminal O, so that the signal output terminal O can be in the shift register. In the output stage, a gate scan signal is output to the gate line connected to the signal output terminal O.
  • the pull-down control circuit 30 can control the potential of the pull-down node PD such that under the control of the pull-down node PD, the pull-down circuit 40 can pull down the potential of the pull-up node PU and the signal output terminal O to the voltage of the first voltage terminal VSS.
  • the reset circuit 50 can also pull down the potential of the pull-up node PU and the signal output terminal O to the voltage of the first voltage terminal VSS, thereby pulling up the PU and signal output of the node.
  • the potential of the terminal O is reset to prevent the charge remaining on the pull-up node PU and the signal output terminal O from affecting the display image of the next image frame.
  • the voltage of the noise reduction control signal terminal STV_in may be output through the noise reduction control circuit 60. Pulling down the node PD to control the potential of the pull-down node PD, so that under the control of the pull-down node PD, the pull-down circuit 40 can pull down the voltage of the pull-up node PU and the signal output terminal O to the first voltage terminal VSS, respectively.
  • the voltage so as to release the charge stored in the pull-up node PU and the signal output terminal O, achieves the purpose of noise reduction processing.
  • the noise reduction control circuit 60 described above is constituted by the first transistor M1 as shown in FIG.
  • the gate of the first transistor M1 and the first pole are connected to the noise reduction control signal terminal STV_in, and the second pole is connected to the pull-down node PD.
  • the pull-up control circuit 10 includes a second transistor M2.
  • the gate of the second transistor M2 and the first pole are connected to the signal input terminal I, and the second pole is connected to the pull-up node PU.
  • the pull-up control circuit 40 when the pull-up control circuit 40 is further connected to the second clock signal input terminal CLKB, the pull-up control circuit 40 is further used under the control of the second clock signal input terminal CLKB.
  • the voltage at the signal input terminal I is output to the pull-up node PU.
  • the pull-up control circuit 40 further includes a twelfth transistor M12 as shown in FIG.
  • the gate of the twelfth transistor M12 is connected to the second clock signal input terminal CLKB, the first pole is connected to the signal input terminal I, and the second pole is connected to the pull-up node PU.
  • both the second transistor M2 and the twelfth transistor M12 when both the second transistor M2 and the twelfth transistor M12 are turned on, both of the above transistors output a signal of the signal input terminal I to the pull-up node PU. Therefore, the second transistor M2 and the twelfth transistor M12 have the same function. In this way, the pull-up control circuit 40 can still operate normally when one of the transistors is damaged.
  • the pull-up circuit includes a driving transistor Md and a storage capacitor Cst.
  • the gate of the driving transistor Md is connected to the pull-up node PU, the first pole is connected to the first clock signal input terminal CLK, and the second pole is connected to the signal output terminal O.
  • the driving transistor Md is connected to the signal output terminal O, and the signal output terminal O is connected to the gate line in the array substrate, the driving transistor Md is connected with a load, which needs to have a certain driving capability.
  • the drive transistor Md has a large size of the drive transistor Md with respect to other transistors that only function as a switch.
  • one end of the storage capacitor Cst is connected to the pull-up node PU, and the other end is connected to the signal output terminal O.
  • the storage capacitor Cst can store the voltage input to the pull-up node PU, and can also discharge the stored voltage to the gate of the driving transistor Md.
  • the pull-down control circuit 30 includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6.
  • the gate of the third transistor M3 and the first electrode are connected to the second clock signal input terminal CLKB, and the second electrode is connected to the gate of the fourth transistor M4.
  • the first electrode of the fourth transistor M4 is connected to the second clock signal input terminal CLKB, and the second electrode is connected to the pull-down node PD.
  • the gate of the fifth transistor M5 is connected to the pull-up node PU, the first pole is connected to the second pole of the third transistor M3, and the second pole is connected to the first voltage terminal VSS.
  • the gate of the sixth transistor M6 is connected to the pull-up node PU, the first pole is connected to the pull-down node PD, and the second pole is connected to the first voltage terminal VSS.
  • the pull-down circuit 40 includes a seventh transistor M7 and an eighth transistor M8.
  • the gate of the seventh transistor M7 is connected to the pull-down node PD, the first pole is connected to the pull-up node PU, and the second pole is connected to the first voltage terminal VSS.
  • the gate of the eighth transistor M8 is connected to the pull-down node PD, the first pole is connected to the signal output terminal O, and the second pole is connected to the first voltage terminal VSS.
  • the reset circuit 50 includes a ninth transistor M9 and a tenth transistor M10.
  • the gate of the ninth transistor M9 is connected to the reset signal terminal R, the first pole is connected to the pull-up node PU, and the second pole is connected to the first voltage terminal VSS.
  • the gate of the tenth transistor M10 is connected to the reset signal terminal R, the first pole is connected to the signal output terminal O, and the second pole is connected to the first voltage terminal VSS.
  • the above-described shift register as an example further includes an auxiliary noise reduction module 70 as shown in FIG.
  • the auxiliary noise reduction module 70 is connected to the second clock signal input terminal CLKB, the signal output terminal O and the first voltage terminal VSS.
  • the auxiliary noise reduction module 70 is configured to pull down the voltage of the signal output terminal O to the voltage of the first voltage terminal VSS under the control of the second clock signal input terminal CLKB.
  • the auxiliary noise reduction module described above may include an eleventh transistor M11 as shown in FIG.
  • the second clock signal input terminal CLKB of the eleventh transistor M11 has a first pole connected to the signal output terminal O, and the second pole is connected to the first voltage terminal VSS.
  • the transistor may be an N-type transistor.
  • the first pole of the transistor may be a drain and the second pole may be a source.
  • the transistor may be a P-type transistor.
  • the first electrode of the transistor may be a source and the second electrode may be a drain.
  • the transistor may be an enhancement transistor or a depletion transistor, which is not limited in the disclosure.
  • each transistor in the shift register shown in FIG. 4 is in an image frame.
  • the on/off conditions of different stages P1 to P3, and blanking time) are exemplified in detail.
  • the description is made by taking the first voltage terminal VSS as a constant output low level as an example.
  • the signal input terminal I outputs a high level
  • the second transistor M2 is turned on
  • the second clock signal input terminal CLKB outputs a high level
  • the twelfth transistor M12 is turned on, thereby making the signal input terminal I high.
  • the level can be transmitted to the pull-up node PU through the second transistor M2 and the twelfth transistor M12, thereby charging the pull-up node PU such that the potential of the pull-up node PU rises.
  • the storage capacitor Cst stores the voltage input to the pull-up node PU.
  • the driving transistor Md is turned on, thereby transmitting the low level of the output of the first clock signal input terminal CLK to the signal output terminal O.
  • the fifth transistor M5 and the sixth transistor M6 are turned on. Therefore, even if the second clock signal input terminal CLKB outputs a high level, the third transistor M3 is turned on, and the turned-on fifth transistor M5 pulls down the gate potential of the second transistor M3 and the fourth transistor M4. Up to the first voltage terminal VSS, so that the fourth transistor M4 can be prevented from being turned on, so that the high level of the second clock signal input terminal CLKB cannot be output to the pull-down node PD through the fourth transistor M4, and the pull-down node PD is low-powered at this time. level.
  • the sixth transistor M6 since the sixth transistor M6 is turned on, the potential of the pull-down node PD can be pulled down to the first voltage terminal VSS. In this case, the seventh transistor M7 and the eighth transistor M8 are both in an off state. Further, since the reset signal terminal R outputs a low level, the ninth transistor M9 and the tenth transistor M10 are both in an off state.
  • the signal output terminal O outputs a low level in the above input phase P1, so that the shift register is in the non-output phase at this stage, and the gate drive signal is not output.
  • the signal input terminal I outputs a low level
  • the second transistor M2 is in an off state
  • the second clock signal input terminal CLKB inputs a low level
  • the twelfth transistor M12 the third transistor M3 is turned off
  • the fourth transistor M4 is in the off state.
  • the above-described storage capacitor Cst releases the high level stored in the input phase P1 to charge the pull-up node PU, thereby keeping the drive transistor Md in an on state.
  • the high level of the first clock signal input terminal CLK is output to the signal output terminal O through the driving transistor Md.
  • the potential of the pull-up node PU is further increased to maintain the driving transistor Md in an on state, thereby making the first clock signal input terminal CLK high.
  • the level can be used as a gate scan signal for a continuously stable output to the gate line connected to the signal output terminal O.
  • the fifth transistor M5 and the sixth transistor M6 are turned on.
  • the sixth transistor M6 pulls the potential of the pull-down node PD to a low level of the first voltage terminal VGL.
  • the seventh transistor M7 and the eighth transistor M8 are in an off state as in the input phase P1 described above.
  • the reset signal terminal R outputs a low level, and the ninth transistor M9 and the tenth transistor M10 are both in an off state.
  • the signal output terminal O outputs a high level in the output phase P2, and the high level is output as a gate scan signal to a gate line connected to the signal output terminal O to the gate line.
  • the controlled sub-pixels are gated.
  • the reset signal terminal R outputs a high level
  • the ninth transistor M9 and the tenth transistor M10 are turned on, and the potential of the pull-up node PU is pulled down to the first voltage terminal VSS through the ninth transistor M9 to pull up.
  • the node PU performs resetting; the potential of the signal output terminal O is pulled down to the first voltage terminal VSS through the tenth transistor M10 to reset the signal output terminal O.
  • the second clock signal input terminal CLKB outputs a high level to turn on the third transistor M3, and the second clock signal input terminal CLKB outputs a high level through the third transistor M3 to the gate of the fourth transistor M4.
  • the four-transistor M4 is turned on, so that the second clock signal input terminal CLKB outputs a high level to be transmitted to the pull-down node PD through the fourth transistor M4, and the pull-down node PD is at a high level.
  • the seventh transistor M7 and the eighth transistor M8 are turned on, and the potential of the pull-up node PU is pulled down to the first voltage terminal VSS through the seventh transistor M7; the signal output terminal O is output through the eighth transistor M8. The potential is pulled down to the first voltage terminal VSS.
  • the driving transistor Md, the fifth transistor M5, and the sixth transistor M6 are turned off.
  • the signal output terminal O outputs a low level in the above reset phase P3, so the shift register is in the non-output phase at this stage, and the gate drive signal is not output.
  • the first transistor M1 under the control that the noise reduction control signal terminal STV_in outputs a high level, the first transistor M1 is turned on, thereby outputting the noise reduction control signal terminal STV_in output high level through the first transistor M1 to the pull-down node PD. . In this way, at the above blanking time, the pull-down node PD can continue to maintain a high level.
  • the seventh transistor M7 and the eighth transistor M8 are turned on, and the potential of the pull-up node PU is pulled down to the first voltage terminal VSS through the seventh transistor M7, so that During the blanking time, the pull-up node PU may continue to perform noise reduction; and the potential of the signal output terminal O is continuously pulled down to the first voltage terminal VSS through the eighth transistor M8, so that the signal can be aligned during the blanking time Output O continues to reduce noise. Therefore, the influence of noise on the display effect can be effectively avoided.
  • Embodiments of the present disclosure provide a gate driving circuit, as shown in FIG. 6, including a plurality of cascaded shift registers (RS1, RS2, ..., RSn) as described above. Where n ⁇ 2, n is a positive integer.
  • the signal input terminal I of the first stage shift register RS1 is connected to the start signal terminal STV.
  • the signal output terminal I of the shift register of the previous stage is connected to the signal input terminal I of the shift register of the next stage.
  • the signal input terminal I of the remaining shift registers is connected to the signal output terminal O of the previous stage shift register, based on which the pull-up control circuit 10 of the remaining shift registers is based thereon.
  • the twelfth transistor M12 is further included as shown in FIG. 4, under the control of the second clock signal input terminal CLKB, the noise of the signal output terminal O of the previous stage shift register can be transmitted to the twelfth transistor M12 through the above-mentioned twelfth transistor M12.
  • the above-mentioned pull-up node PU is then noise-reduced by the reset circuit 50, the pull-down circuit 40, and the noise reduction control circuit 60 in the stage shift register to achieve The purpose of step-by-step noise reduction.
  • start signal terminal STV is used to output a start signal
  • the signal input end I of the first stage shift register RS1 of the gate drive circuit receives the start signal
  • the plurality of stages The associated shift register scans the gate lines (G1, G2, ..., Gn) connected to their respective signal output terminals O row by row.
  • the signal output terminal O of the next stage shift register is connected to the reset signal terminal R of the previous stage shift register.
  • the reset signal terminal R of the last stage shift register RSn can be connected to the above-mentioned start signal terminal STV. In this way, when the start signal of the start signal terminal STV is input to the signal input terminal I of the first stage shift register RS1, the reset signal terminal R of the last stage shift register RSn can start from the start signal terminal STV.
  • the start signal is used as a reset signal to reset the signal output terminal O of the last stage shift register RSn and the pull-up node PU.
  • the noise reduction control signal terminal STV_in connected to each shift register is independently set as shown in FIG. 6.
  • the phases are opposite.
  • the first clock signal input terminal CLK and the second clock signal input terminal CLKB on the different shift registers are alternately connected to the first system clock signal input terminal CLK1 and the second system clock signal input terminal CLK2, respectively.
  • the first clock signal input terminal CLK of the first stage shift register RS1 is connected to the first system clock signal input terminal CLK1, and the second clock signal input terminal CLKB is connected to the second system clock signal input terminal CLK2;
  • the second stage shift register The first clock signal input terminal CLK of RS2 is connected to the second system clock signal input terminal CLK2, and the second clock signal input terminal CLKB is connected to the first system clock signal input terminal CLK3.
  • the following shift registers are connected as described above.
  • Embodiments of the present disclosure provide a display device including the gate drive circuit as described above.
  • the gate driving circuit in the display device has the same structure and advantageous effects as the gate driving circuit provided in the foregoing embodiment. Since the foregoing embodiment has been described in detail for the structure and advantageous effects of the gate driving circuit, details are not described herein again.
  • Embodiments of the present disclosure provide a method for driving any one of the shift registers as described above.
  • the method includes:
  • the pull-up control circuit 10 shown in FIG. 1 or FIG. 3 outputs the voltage of the signal input terminal I to the pull-up node PU.
  • the pull-up circuit stores the potential of the 20 pull-up node PU, and outputs the voltage of the first clock signal input terminal CLK to the signal output terminal O under the control of the pull-up node PU.
  • the pull-down control circuit 30 pulls down the voltage of the pull-down node PD to the voltage of the first voltage terminal VSS.
  • the pull-up circuit 20 outputs the signal stored in the previous stage to the pull-up node PU. Under the control of the pull-up node PU, the pull-up circuit 20 outputs the voltage of the first clock signal input terminal CLK to the signal output terminal O, so that the The signal output terminal O outputs a gate scan signal.
  • the pull-down control circuit 30 pulls down the voltage of the pull-down node PU to the voltage of the first voltage terminal VSS.
  • the reset circuit 50 pulls down the voltage of the pull-up node PU and the signal output terminal O to the voltage of the first voltage terminal VSS, respectively.
  • the pull-down control circuit 30 outputs the voltage of the second clock signal input terminal CLKB to the pull-down node PD.
  • the pull-down circuit 40 pulls down the voltage of the pull-up node PU and the signal output terminal O to the voltage of the first voltage terminal VSS, respectively.
  • the noise reduction control circuit 60 Under the control of the noise reduction control signal terminal STV_in, the noise reduction control circuit 60 outputs the voltage of the noise reduction control signal terminal STV_in to the pull-down node PD. Under the control of the pull-down node PD, the pull-down circuit 40 pulls down the voltage of the pull-up node PU and the signal output terminal O to the voltage of the first voltage terminal VSS, respectively.
  • each module in the above shift register is as shown in FIG. 2 or FIG. 4, and the transistors in each module are N-type transistors, the transistors in the above-mentioned respective modules are turned on and off in the above stages. The description will not be repeated here.
  • the method further includes:
  • the auxiliary noise reduction module 70 pulls down the voltage of the signal output terminal O to the voltage of the first voltage terminal VSS.
  • the eleventh transistor M11 can be input at the second clock signal.
  • the terminal CLKB outputs a high level, it is in an on state, thereby pulling down the voltage of the signal output terminal O to the voltage of the first voltage terminal VSS.
  • the foregoing program may be stored in a computer readable storage medium, and the program is executed when executed.
  • the foregoing steps include the steps of the foregoing method embodiments; and the foregoing storage medium includes: a medium that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.

Abstract

一种移位寄存器及其驱动方法、栅极驱动电路、显示装置。移位寄存器包括上拉控制电路（10），将信号输入端（I）的电压输出至上拉节点（PU）；上拉电路（20），将第一时钟信号输入端（CLK）的电压输出至信号输出端（O）；下拉控制电路（30），将第二时钟信号输入端（CLKB）的电压输出至下拉节点（PD），或者将下拉节点（PD）的电压下拉至第一电压端（VSS）；下拉电路（40），分别将上拉节点（PU）和信号输出端（O）的电压下拉至第一电压端（VSS）；复位电路（50），分别将上拉节点（PU）和信号输出端（O）的电压下拉至第一电压端（VSS）；降噪控制电路（60），在一图像帧的消隐时间，将降噪控制信号端（STV_in）的电压输出至下拉节点（PD）。移位寄存器用于驱动与其相连接的栅线。

Description

移位寄存器及其驱动方法、栅极驱动电路、显示装置
相关申请
本申请要求2017年6月21日提交、申请号为201710478926.5的中国专利申请的优先权，该申请的全部内容通过引用并入本文。
技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器及其驱动方法、栅极驱动电路、显示装置。
背景技术
液晶显示器(Liquid Crystal Display，简称LCD)具有低辐射、体积小及低耗能等优点，被广泛地应用在笔记本电脑、平面电视或移动电话等电子产品中。
现有技术中，通常在液晶显示器中阵列基板的周边设置GOA(Gate Driver on Array，阵列基板行驱动)电路，用于对栅线进行逐行扫描。示例地，在一图像帧内，GOA电路会从上至下或从下至上对栅线进行逐行扫描。以从上直下对栅线进行扫描为例，当对最后一行栅线扫描之后，GOA电路需要从最后一行回到第一行，进入下一图像帧的扫描步骤。为了避免对显示造成影响，上述从最后一行回到第一行的这段时间，需要该GOA电路中任意一个移位寄存器均无信号输出，这段时间为消隐时间(Blank)。
然而，在上述消隐时间内，受到GOA电路结构以及其内部晶体管自身耦合电容的影响，使得GOA电路部分节点或者晶体管存储的电荷没有得到充分的释放，这样一来，在上述消隐时间内，会对GOA电路中移位寄存器的输出端造成噪声干扰，降低GOA电路的稳定性。
发明内容
本公开的实施例提供一种移位寄存器及其驱动方法、栅极驱动电路、显示装置。
本公开的实施例采用如下技术方案：
本公开实施例的一方面，提供一种移位寄存器，包括上拉控制电路、上拉电路、下拉控制电路、下拉电路、复位电路以及降噪控制电路；所述上拉控制电路连接信号输入端以及上拉节点，用于在所述信号输入端的控制下，将所述信号输入端的电压输出至所述上拉节点； 所述上拉电路连接所述上拉节点、第一时钟信号输入端以及信号输出端，用于将上拉节点的电位进行存储，并在所述上拉节点的控制下将所述第一时钟信号输入端的电压输出至所述信号输出端；所述下拉控制电路连接第二时钟信号输入端、所述上拉节点、下拉节点以及第一电压端，用于在所述第二时钟信号输入端的控制下，将所述第二时钟信号输入端的电压输出至所述下拉节点，或者用于在所述上拉节点的控制下，将所述下拉节点的电压下拉至所述第一电压端的电压；所述下拉电路连接所述下拉节点、所述上拉节点、所述信号输出端以及所述第一电压端，用于在所述下拉节点的控制下，分别将所述上拉节点和所述信号输出端的电压下拉至所述第一电压端的电压；所述复位电路连接复位信号端、所述上拉节点、所述信号输出端以及所述第一电压端，用于在所述复位信号端的控制下，分别将所述上拉节点和所述信号输出端的电压下拉至所述第一电压端的电压；所述降噪控制电路连接降噪控制信号端、所述下拉节点，用于在一图像帧的消隐时间，在所述降噪控制信号端的控制下，将所述降噪控制信号端的电压输出至所述下拉节点。
示例地，所述降噪控制电路由第一晶体管构成；所述第一晶体管的栅极和第一极连接所述降噪控制信号端，第二极与所述下拉节点相连接。
示例地，所述上拉控制电路包括第二晶体管；所述第二晶体管的栅极和第一极连接所述信号输入端，第二极与所述上拉节点相连接。
示例地，所述上拉电路包括驱动晶体管和存储电容；所述驱动晶体管的栅极连接所述上拉节点，第一极连接所述第一时钟信号输入端，第二极与所述信号输出端相连接；所述存储电容的一端连接所述上拉节点，另一端与所述信号输出端相连接。
示例地，所述下拉控制电路包括第三晶体管、第四晶体管、第五晶体管以及第六晶体管；所述第三晶体管的栅极和第一极连接所述第二时钟信号输入端，第二极与所述第四晶体管的栅极相连接；所述第四晶体管的第一极连接所述第二时钟信号输入端，第二极与所述下拉节点相连接；所述第五晶体管的栅极连接所述上拉节点，第一极连接所述第三晶体管的第二极，第二极与所述第一电压端相连接；所述第六晶体管的栅极连接所述上拉节点，第一极连接所述下拉节点，第二 极与所述第一电压端相连接。
示例地，所述下拉电路包括第七晶体管和第八晶体管；所述第七晶体管的栅极连接所述下拉节点，第一极连接所述上拉节点，第二极与所述第一电压端相连接；所述第八晶体管的栅极连接所述下拉节点，第一极连接所述信号输出端，第二极与所述第一电压端相连接。
示例地，所述复位电路包括第九晶体管和第十晶体管；所述第九晶体管的栅极连接所述复位信号端，第一极连接所述上拉节点，第二极与所述第一电压端相连接；所述第十晶体管的栅极连接所述复位信号端，第一极连接所述信号输出端，第二极与所述第一电压端相连接。
示例地，还包括辅助降噪模块，所述辅助降噪模块连接所述第二时钟信号输入端，信号输出端以及第一电压端，用于在所述第二时钟信号输入端的控制下，将所述信号输出端的电压下拉至所述第一电压端的电压。
进一步示例地，所述辅助降噪模块包括第十一晶体管；所述第十一晶体管的栅极连接所述第二时钟信号输入端，第一极连接所述信号输出端，第二极与所述第一电压端相连接。
进一步示例地，所述上拉控制电路还连接第二时钟信号输入端，用于在所述第二时钟信号输入端的控制下，将所述信号输入端的电压输出至所述上拉节点；所述上拉控制电路还包括第十二晶体管；所述第十二晶体管的栅极连接所述第二时钟信号输入端，第一极连接所述信号输入端，第二极与所述上拉节点相连接。
本公开实施例的另一方面，提供一种栅极驱动电路，包括多个级联的如上所述的任意一种移位寄存器；第一级移位寄存器的信号输入端连接起始信号端；除了第一级移位寄存器以外，上一级移位寄存器的信号输出端与下一级移位寄存器的信号输入端相连接；除了最后一级移位寄存器以外，下一级移位寄存器的信号输出端与上一级移位寄存器的复位信号端相连接；最后一级移位寄存器的复位信号端连接所述起始信号端。
本公开实施例的又一方面，提供一种显示装置，包括上述栅极驱动电路。
本公开实施例的再一方面，提供一种用于驱动如上所述的任意一种移位寄存器的方法，在一图像帧内，所述方法包括：在输入阶段： 在信号输入端的控制下，上拉控制电路将信号输入端的电压输出至上拉节点；上拉电路将所述上拉节点的电位进行存储，并在所述上拉节点的控制下将第一时钟信号输入端的电压输出至信号输出端；在所述上拉节点的控制下，下拉控制电路将下拉节点的电压下拉至第一电压端的电压；在输出阶段：上拉电路将上一阶段存储的信号输出至所述上拉节点，在所述上拉节点的控制下，所述上拉电路将所述第一时钟信号输入端的电压至所述信号输出端，所述信号输出端输出栅极扫描信号；在所述上拉节点的控制下，所述下拉控制电路将所述下拉节点的电压下拉至所述第一电压端的电压；在复位阶段：在复位信号端的控制下，复位电路分别将所述上拉节点和所述信号输出端的电压下拉至所述第一电压端的电压；在第二时钟信号输入端的控制下，所述下拉控制电路将所述第二时钟信号输入端的电压输出至所述下拉节点；在所述下拉节点的控制下，下拉电路分别将所述上拉节点和所述信号输出端的电压下拉至所述第一电压端的电压；在消隐时间：在降噪控制信号端的控制下，降噪控制电路将所述降噪控制信号端的电压输出至所述下拉节点；在所述下拉节点的控制下，所述下拉电路分别将所述上拉节点和所述信号输出端的电压下拉至所述第一电压端的电压。
示例地，在所述移位寄存器包括辅助降噪模块的情况下，在一图像帧内，所述方法还包括：在所述输入阶段和所述复位阶段：在所述第二时钟信号输入端的控制下，所述辅助降噪模块将所述信号输出端的电压下拉至所述第一电压端的电压。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的一种移位寄存器的结构示意图；
图2为图1中各个模块对应的具体结构示意图；
图3为本公开实施例提供的另一种移位寄存器的结构示意图；
图4为图3中各个模块对应的具体结构示意图；
图5为用于驱动图2或图4所示的移位寄存器的各个控制信号的 时序图；
图6为本公开实施例提供的一种栅极驱动电路的结构示意图。
附图标记：
10-上拉控制电路；20-上拉电路；30-下拉控制电路；40-下拉电路；50-复位电路；60-降噪控制电路；70-辅助降噪模块；I-信号输入端；CLK-第一时钟信号端输入端；CLKB-第二时钟信号输入端；O-信号输出端；R-复位信号端；VSS-第一电压端；STV_in-降噪控制信号端。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开实施例提供一种移位寄存器，如图1所示，包括上拉控制电路10、上拉电路20、下拉控制电路30、下拉电路40、复位电路50以及降噪控制电路60。
示例地，上拉控制电路10连接信号输入端I以及上拉节点PU。该上拉控制电路10用于在信号输入端I的控制下，将该信号输入端I的电压输出至上拉节点PU。
上拉电路20连接上拉节点PU、第一时钟信号输入端CLK以及信号输出端O。该上拉电路20用于将上拉节点PU的电位进行存储，并在上拉节点PU的控制下将第一时钟信号输入端CLK的电压输出至信号输出端O。
下拉控制电路30连接第二时钟信号输入端CLKB、上拉节点PU、下拉节点PD以及第一电压端VSS。该下拉控制电路30用于在第二时钟信号输入端CLKB的控制下，将第二时钟信号输入端CLKB的电压输出至下拉节点PD。或者，上述下拉控制电路30用于在上拉节点PU的控制下，将下拉节点PD的电压下拉至第一电压端VSS的电压。
下拉电路40连接下拉节点PD、上拉节点PU、信号输出端O以及第一电压端VSS。该下拉电路40用于在下拉节点PD的控制下，分别将上拉节点PU和信号输出端O的电压下拉至第一电压端VSS的电压。
复位电路50连接复位信号端R、上拉节点PU、信号输出端O以 及第一电压端VSS。该复位电路50用于在复位信号端R的控制下，分别将上拉节点PU和信号输出端O的电压下拉至第一电压端VSS的电压。
降噪控制电路60连接降噪控制信号端STV_in、下拉节点PD。该降噪控制电路60用于在一图像帧(Frame)的消隐时间，在降噪控制信号端STV_in的控制下，将降噪控制信号端STV_in的电压输出至下拉节点PD，以使得在下拉节点PD的控制下，下拉电路40分别将上拉节点PU和信号输出端O的电压下拉至第一电压端VSS的电压。
综上所述，在一图像帧内，通过上拉控制电路10可以对上拉节点PU的电位进行控制。基于此，在该上拉节点PU的控制下，上述上拉电路20，可以将第一时钟信号输入端CLK的电压输出至信号输出端O，以使得该信号输出端O能够在该移位寄存器的输出阶段，向与该信号输出端O相连接的栅线输出栅极扫描信号。此外，下拉控制电路30能够控制下拉节点PD的电位，以使得在该下拉节点PD的控制下，下拉电路40可以将上拉节点PU和信号输出端O的电位下拉至第一电压端VSS的电压，从而可以在移位寄存器的非输出阶段，保证该移位寄存器的信号输出端O无信号输出。在此基础上，在复位信号端R的控制下，复位电路50还可以将上拉节点PU和信号输出端O的电位下拉至第一电压端VSS的电压，从而对上拉节点PU和信号输出端O的电位进行复位，以避免该上拉节点PU和信号输出端O上残留的电荷对下一图像帧的显示画面造成影响。
此外，在上述一图像帧的消隐时间，为了避免移位寄存器中上拉节点PD以及晶体管存储的电荷没有得到充分的释放，可以通过降噪控制电路60将降噪控制信号端STV_in的电压输出至下拉节点PD，以对该下拉节点PD的电位进行控制，使得在下拉节点PD的控制下，下拉电路40能够分别将上拉节点PU和信号输出端O的电压下拉至第一电压端VSS的电压，从而对上拉节点PU和信号输出端O存储的电荷进行释放，达到降噪处理的目的。
以下对图1所示的移位寄存器中各个模块的结构进行详细的举例说明。
示例地，上述降噪控制电路60如图2所示，由第一晶体管M1构成。该第一晶体管M1的栅极和第一极连接降噪控制信号端STV_in， 第二极与下拉节点PD相连接。
上拉控制电路10包括第二晶体管M2。
其中，第二晶体管M2的栅极和第一极连接信号输入端I，第二极与上拉节点PU相连接。
在此基础上，如图3所示，当该上拉控制电路40还连接第二时钟信号输入端CLKB时，该上拉控制电路40还用于在第二时钟信号输入端CLKB的控制下，将信号输入端I的电压输出至上拉节点PU。
在此情况下，上拉控制电路40如图4所示还包括第十二晶体管M12。其中，该第十二晶体管M12的栅极连接第二时钟信号输入端CLKB，第一极连接信号输入端I，第二极与上拉节点PU相连接。
由上述可知，当第二晶体管M2和第十二晶体管M12都导通时，上述两个晶体管均是将信号输入端I的信号输出至上拉节点PU。因此第二晶体管M2和第十二晶体管M12的作用相同。这样一来，当其中一个晶体管损坏时，该上拉控制电路40仍然可以正常工作。
在此基础上，如图2所示，上拉电路包括驱动晶体管Md和存储电容Cst。
其中，驱动晶体管Md的栅极连接上拉节点PU，第一极连接第一时钟信号输入端CLK，第二极与信号输出端O相连接。
需要说明的是，由于驱动晶体管Md与信号输出端O相连接，而信号输出端O又与阵列基板中的栅线相连接，所以驱动晶体管Md连接有负载，其需要具备一定的驱动能力。在此情况下，上述驱动晶体管Md相对于其他仅起到开关作用的晶体管而言，该驱动晶体管Md的尺寸较大。
此外，存储电容Cst的一端连接上拉节点PU，另一端与信号输出端O相连接。该存储电容Cst可以对输入至上拉节点PU的电压进行存储，还可以将存储的电压释放至驱动晶体管Md的栅极。
进一步地，下拉控制电路30包括第三晶体管M3、第四晶体管M4、第五晶体管M5以及第六晶体管M6。
其中，第三晶体管M3的栅极和第一极连接第二时钟信号输入端CLKB，第二极与第四晶体管M4的栅极相连接。
第四晶体管M4的第一极连接第二时钟信号输入端CLKB，第二极与下拉节点PD相连接。
第五晶体管M5的栅极连接上拉节点PU，第一极连接第三晶体管M3的第二极，第二极与第一电压端VSS相连接。
第六晶体管M6的栅极连接上拉节点PU，第一极连接下拉节点PD，第二极与第一电压端VSS相连接。
此外，下拉电路40包括第七晶体管M7和第八晶体管M8。
其中，第七晶体管M7的栅极连接下拉节点PD，第一极连接上拉节点PU，第二极与第一电压端VSS相连接。
第八晶体管M8的栅极连接下拉节点PD，第一极连接信号输出端O，第二极与第一电压端VSS相连接。
复位电路50包括第九晶体管M9和第十晶体管M10。
其中，第九晶体管M9的栅极连接复位信号端R，第一极连接上拉节点PU，第二极与第一电压端VSS相连接。
第十晶体管M10的栅极连接复位信号端R，第一极连接信号输出端O，第二极与第一电压端VSS相连接。
在此基础上，为了进一步提高对移位寄存器的降噪效果，示例地上述移位寄存器如图3所示还包括辅助降噪模块70。
示例地，该辅助降噪模块70连接第二时钟信号输入端CLKB，信号输出端O以及第一电压端VSS。该辅助降噪模块70用于在第二时钟信号输入端CLKB的控制下，将信号输出端O的电压下拉至第一电压端VSS的电压。
基于此，上述辅助降噪模块如图4所示，可以包括第十一晶体管M11。
其中，第十一晶体管M11的栅极第二时钟信号输入端CLKB，第一极连接信号输出端O，第二极与第一电压端VSS相连接。
需要说明的是，上述晶体管可以为N型晶体管，在此情况下，晶体管的第一极可以为漏极，第二极可以为源极。或者，上述晶体管也可以为P型晶体管，在此情况下，晶体管的第一极可以为源极，第二极为漏极。此外，上述晶体管可以为增强型晶体管，也可以为耗尽型晶体管，本公开对此不作限定。
以下以上述晶体管以及与栅线相连接的位于亚像素内的各个晶体管均为N型晶体管为例，并结合图5对如图4所示的移位寄存器中的各个晶体管，在一图像帧的不同的阶段(P1～P3，以及消隐时间)的通 断情况进行详细的举例说明。其中，本公开实施例中是以第一电压端VSS恒定输出低电平为例进行的说明。
输入阶段P1：STV_in＝0；CLK＝0，CLKB＝1；I＝1，R＝0，O＝0；其中“0”表示低电平，“1”表示高电平。
在此情况下，信号输入端I输出高电平，第二晶体管M2导通，且第二时钟信号输入端CLKB输出高电平，第十二晶体管M12导通，从而使得信号输入端I的高电平能够通过第二晶体管M2和第十二晶体管M12，传输至上拉节点PU，从而对上拉节点PU进行充电，使得该上拉节点PU的电位升高。
此时，存储电容Cst对输入至上拉节点PU的电压进行存储。此外，随着上拉节点PU的电位逐渐升高，驱动晶体管Md导通，从而将第一时钟信号输入端CLK输出的低电平传输至信号输出端O。
此外，在上述上拉节点PU高电位的控制下，第五晶体管M5和第六晶体管M6导通。因此，即使第二时钟信号输入端CLKB输出高电平将导通第三晶体管M3，上述导通的第五晶体管M5也会将第三晶体管M3第二极以及第四晶体管M4的栅极电位下拉至第一电压端VSS，从而可以避免第四晶体管M4导通，以使得第二时钟信号输入端CLKB的高电平无法通过第四晶体管M4输出至下拉节点PD，此时下拉节点PD为低电平。
基于此，由于第六晶体管M6导通，因此可以将下拉节点PD的电位下拉至第一电压端VSS。在此情况下，第七晶体管M7和第八晶体管M8均处于截止状态。此外，由于复位信号端R输出低电平，因此第九晶体管M9和第十晶体管M10均处于截止状态。
综上所述，信号输出端O在上述输入阶段P1输出低电平，因此该阶段移位寄存器处于非输出阶段，而不输出栅极驱动信号。
输出阶段P2：STV_in＝0；CLK＝1，CLKB＝0；I＝0，R＝0，O＝1。
在此情况下，信号输入端I输出低电平，第二晶体管M2处于截止状态，且第二时钟信号输入端CLKB输入低电平，第十二晶体管M12、第三晶体管M3截止以及第四晶体管M4处于截止状态。
此外，上述存储电容Cst将输入阶段P1存储的高电平进行释放，以对上拉节点PU进行充电，从而使得驱动晶体管Md保持开启状态。在此情况下，第一时钟信号输入端CLK的高电平通过驱动晶体管Md 输出至信号输出端O。在此基础上，在存储电容Cst的自举(Bootstrapping)作用下，上拉节点PU的电位进一步升高，以维持驱动晶体管Md处于导通的状态，从而使得第一时钟信号输入端CLK的高电平能够作为栅极扫描信号，持续稳定的输出至与该信号输出端O相连接的栅线上。
此外，在上拉节点PU高电位的控制下，第五晶体管M5和第六晶体管M6导通。第六晶体管M6将下拉节点PD的电位拉低至第一电压端VGL的低电平。在此情况下，与上述输入阶段P1相同，第七晶体管M7、第八晶体管M8处于截止状态。复位信号端R输出低电平，第九晶体管M9和第十晶体管M10均处于截止状态。
综上所述，信号输出端O在上述输出阶段P2输出高电平，该高电平作为栅极扫描信号，输出至与上述信号输出端O相连接的栅线上，以对该行栅线控制的亚像素进行选通。
复位阶段P3：STV_in＝0；CLK＝0，CLKB＝1；I＝0，R＝1，O＝0。
在此情况下，复位信号端R输出高电平，第九晶体管M9和第十晶体管M10导通，通过第九晶体管M9将上拉节点PU的电位下拉至第一电压端VSS，以对上拉节点PU进行复位；通过第十晶体管M10将信号输出端O的电位下拉至第一电压端VSS，以对信号输出端O进行复位。
此外，第二时钟信号输入端CLKB输出高电平将第三晶体管M3导通，且第二时钟信号输入端CLKB输出高电平通过第三晶体管M3传输至第四晶体管M4的栅极，该第四晶体管M4导通，使得第二时钟信号输入端CLKB输出高电平通过上述第四晶体管M4传输至下拉节点PD，该下拉节点PD为高电平。
在下拉节点PD的控制下，第七晶体管M7和第八晶体管M8导通，通过第七晶体管M7将上拉节点PU的电位下拉至第一电压端VSS；通过第八晶体管M8将信号输出端O的电位下拉至第一电压端VSS。
此外，由于上拉节点PU的电位被拉低，因此驱动晶体管Md、第五晶体管M5以及第六晶体管M6截止。
综上所述，信号输出端O在上述复位阶段P3输出低电平，因此该阶段移位寄存器处于非输出阶段，而不输出栅极驱动信号。
消隐时间：STV_in＝1；I＝0，R＝0，O＝0。
在此情况下，在降噪控制信号端STV_in输出高电平的控制下，第一晶体管M1导通，从而将降噪控制信号端STV_in输出高电平通过该第一晶体管M1传输至下拉节点PD。这样一来，在上述消隐时间，下拉节点PD能够持续保持高电平。在此情况下，在下拉节点PD的控制下，第七晶体管M7和第八晶体管M8导通，通过第七晶体管M7将上拉节点PU的电位下拉持续至第一电压端VSS，从而可以在上述消隐时间内，可以对上拉节点PU持续进行降噪；并且通过第八晶体管M8将信号输出端O的电位持续下拉至第一电压端VSS，从而可以在上述消隐时间内，可以对信号输出端O持续进行降噪。从而可以有效避免噪声对显示效果造成的影响。
需要说明的是，上述实施例中晶体管的通、断过程是以所有晶体管为N型晶体管为例进行说明的，当所有晶体管均为P型时，需要对图5中的部分控制信号进行翻转，而移位寄存器中各个模块的晶体管的通断过程同上所述，此处不再赘述。
本公开实施例提供一种栅极驱动电路，如图6所示，包括多个级联的如上述所述的任意一种移位寄存器(RS1、RS2......RSn)。其中，n≥2，n为正整数。
第一级移位寄存器RS1的信号输入端I连接起始信号端STV。除了第一级移位寄存器RS1以外，上一级移位寄存器的信号输出端I与下一级移位寄存器的信号输入端I相连接。
由上述可知，除了第一级移位寄存器RS1以外，其余移位寄存器的信号输入端I连接上一级移位寄存器的信号输出端O，基于此，上述其余移位寄存器的上拉控制电路10如图4所述还包括第十二晶体管M12时，在第二时钟信号输入端CLKB的控制下，可以将上一级移位寄存器的信号输出端O的噪声通过上述第十二晶体管M12传输至下一级移位寄存器中的上拉节点PU处，然后在通过该级移位寄存器中的复位电路50、下拉电路40以及降噪控制电路60对上述上拉节点PU进行降噪，以通过达到逐级降噪的目的。
需要说明的是，其中，起始信号端STV用于输出起始信号，该栅极驱动电路的第一级移位寄存器RS1的信号输入端I在接收到上述起始信号后，上述多个级联的移位寄存器逐行对与其各自的信号输出端O相连接的栅线(G1、G2......Gn)进行扫描。
此外，除了最后一级移位寄存器RSn以外，下一级移位寄存器的信号输出端O与上一级移位寄存器的复位信号端R相连接。最后一级移位寄存器RSn的复位信号端R可以连接上述起始信号端STV。这样一来，当起始信号端STV的起始信号输入第一级移位寄存器RS1的信号输入端I时，最后一级移位寄存器RSn的复位信号端R可以将起始信号端STV的起始信号作为复位信号对最后一级移位寄存器RSn的信号输出端O以及上拉节点PU进行复位。
在此基础上，每个移位寄存器连接的降噪控制信号端STV_in如图6所示，均独立设置。
需要说明的是，为了使得每一个移位寄存器的第一时钟信号输入端CLK与第二时钟信号输入端CLKB输出的信号如图5所示波形的频率、振幅相同，相位相反。可以如图6所示，不同移位寄存器上的第一时钟信号输入端CLK和第二时钟信号输入端CLKB分别与第一系统时钟信号输入端CLK1和第二系统时钟信号输入端CLK2交替连接。
例如，第一级移位寄存器RS1的第一时钟信号输入端CLK连接第一系统时钟信号输入端CLK1，第二时钟信号输入端CLKB连接第二系统时钟信号输入端CLK2；第二级移位寄存器RS2的第一时钟信号输入端CLK连接第二系统时钟信号输入端CLK2，第二时钟信号输入端CLKB连接第一系统时钟信号输入端CLK3。以下移位寄存器的连接方式同上所述。
本公开实施例提供一种显示装置，包括如上所述的栅极驱动电路。该显示装置中的栅极驱动电路具有与前述实施例提供的栅极驱动电路相同的结构和有益效果。由于前述实施例已经对栅极驱动电路的结构和有益效果进行了详细的描述，此处不再赘述。
本公开实施例提供一种用于驱动如上所述的任意一种移位寄存器的方法，在一图像帧内，上述方法包括：
在如图5所示的输入阶段P1：
在信号输入端I的控制下，如图1或图3所示的上拉控制电路10将信号输入端I的电压输出至上拉节点PU。上拉电路将20上拉节点PU的电位进行存储，并在上拉节点PU的控制下将第一时钟信号输入端CLK的电压输出至信号输出端O。在上拉节点的控制下，下拉控制电路30将下拉节点PD的电压下拉至第一电压端VSS的电压。
在输出阶段P2：
上拉电路20将上一阶段存储的信号输出至上拉节点PU，在上拉节点PU的控制下，上拉电路20将第一时钟信号输入端CLK的电压输出至信号输出端O，以使得该信号输出端O输出栅极扫描信号。
此外，在上拉节点PU的控制下，下拉控制电路30将下拉节点PU的电压下拉至第一电压端VSS的电压。
在复位阶段P3：
在复位信号端R的控制下，复位电路50分别将上拉节点PU和信号输出端O的电压下拉至第一电压端VSS的电压。在第二时钟信号输入端CLKB的控制下，下拉控制电路30将第二时钟信号输入端CLKB的电压输出至下拉节点PD。
在此情况下，在下拉节点PD的控制下，下拉电路40分别将上拉节点PU和信号输出端O的电压下拉至第一电压端VSS的电压。
在消隐时间：
在降噪控制信号端STV_in的控制下，降噪控制电路60将降噪控制信号端STV_in的电压输出至下拉节点PD。在下拉节点PD的控制下，下拉电路40分别将上拉节点PU和信号输出端O的电压下拉至第一电压端VSS的电压。
示例地，当上述移位寄存器中各个模块的结构如图2或图4所示，且各个模块中的晶体管均为N型晶体管时，上述各个模块中的晶体管在上述各个阶段的通断状态同上所述，此处不再赘述。
在此基础上，如图3所示，在移位寄存器包括辅助降噪模块70的情况下，在一图像帧内，上述方法还包括：
在上述输入阶段P1和复位阶段P3：
在第二时钟信号输入端CLKB的控制下，辅助降噪模块70将信号输出端O的电压下拉至第一电压端VSS的电压。
示例地，当上述辅助降噪模块70的结构如图4所示包括第十一晶体管M11，且该第十一晶体管M11为N型晶体管时，该第十一晶体管M11可以在第二时钟信号输入端CLKB输出高电平时，处于导通状态，从而将信号输出端O的电压下拉至第一电压端VSS的电压。
本领域普通技术人员可以理解：实现上述方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成，前述的程序可以存储于 一计算机可读取存储介质中，该程序在执行时，执行包括上述方法实施例的步骤；而前述的存储介质包括：ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种移位寄存器，其特征在于，包括上拉控制电路、上拉电路、下拉控制电路、下拉电路、复位电路以及降噪控制电路；
    所述上拉控制电路连接信号输入端以及上拉节点，用于在所述信号输入端的控制下，将所述信号输入端的电压输出至所述上拉节点；
    所述上拉电路连接所述上拉节点、第一时钟信号输入端以及信号输出端，用于将上拉节点的电位进行存储，并在所述上拉节点的控制下将所述第一时钟信号输入端的电压输出至所述信号输出端；
    所述下拉控制电路连接第二时钟信号输入端、所述上拉节点、下拉节点以及第一电压端，用于在所述第二时钟信号输入端的控制下，将所述第二时钟信号输入端的电压输出至所述下拉节点，或者用于在所述上拉节点的控制下，将所述下拉节点的电压下拉至所述第一电压端的电压；
    所述下拉电路连接所述下拉节点、所述上拉节点、所述信号输出端以及所述第一电压端，用于在所述下拉节点的控制下，分别将所述上拉节点和所述信号输出端的电压下拉至所述第一电压端的电压；
    所述复位电路连接复位信号端、所述上拉节点、所述信号输出端以及所述第一电压端，用于在所述复位信号端的控制下，分别将所述上拉节点和所述信号输出端的电压下拉至所述第一电压端的电压；以及
    所述降噪控制电路连接降噪控制信号端、所述下拉节点，用于在一图像帧的消隐时间，在所述降噪控制信号端的控制下，将所述降噪控制信号端的电压输出至所述下拉节点。
  2. 根据权利要求1所述的移位寄存器，其特征在于，所述降噪控制电路由第一晶体管构成；以及
    所述第一晶体管的栅极和第一极连接所述降噪控制信号端，第二极与所述下拉节点相连接。
  3. 根据权利要求1所述的移位寄存器，其特征在于，所述上拉控制电路包括第二晶体管；以及
    所述第二晶体管的栅极和第一极连接所述信号输入端，第二极与所述上拉节点相连接。
  4. 根据权利要求1所述的移位寄存器，其特征在于，所述上拉电路包括驱动晶体管和存储电容；
    所述驱动晶体管的栅极连接所述上拉节点，第一极连接所述第一时钟信号输入端，第二极与所述信号输出端相连接；以及
    所述存储电容的一端连接所述上拉节点，另一端与所述信号输出端相连接。
  5. 根据权利要求1所述的移位寄存器，其特征在于，所述下拉控制电路包括第三晶体管、第四晶体管、第五晶体管以及第六晶体管；
    所述第三晶体管的栅极和第一极连接所述第二时钟信号输入端，第二极与所述第四晶体管的栅极相连接；
    所述第四晶体管的第一极连接所述第二时钟信号输入端，第二极与所述下拉节点相连接；
    所述第五晶体管的栅极连接所述上拉节点，第一极连接所述第三晶体管的第二极，第二极与所述第一电压端相连接；以及
    所述第六晶体管的栅极连接所述上拉节点，第一极连接所述下拉节点，第二极与所述第一电压端相连接。
  6. 根据权利要求1所述的移位寄存器，其特征在于，所述下拉电路包括第七晶体管和第八晶体管；
    所述第七晶体管的栅极连接所述下拉节点，第一极连接所述上拉节点，第二极与所述第一电压端相连接；以及
    所述第八晶体管的栅极连接所述下拉节点，第一极连接所述信号输出端，第二极与所述第一电压端相连接。
  7. 根据权利要求1所述的移位寄存器，其特征在于，所述复位电路包括第九晶体管和第十晶体管；
    所述第九晶体管的栅极连接所述复位信号端，第一极连接所述上拉节点，第二极与所述第一电压端相连接；以及
    所述第十晶体管的栅极连接所述复位信号端，第一极连接所述信号输出端，第二极与所述第一电压端相连接。
  8. 根据权利要求1所述的移位寄存器，其特征在于，还包括辅助降噪模块，所述辅助降噪模块连接所述第二时钟信号输入端，信号输出端以及第一电压端，用于在所述第二时钟信号输入端的控制下，将所述信号输出端的电压下拉至所述第一电压端的电压。
  9. 根据权利要求8所述的移位寄存器，其特征在于，所述辅助降噪模块包括第十一晶体管；
    所述第十一晶体管的栅极连接所述第二时钟信号输入端，第一极连接所述信号输出端，第二极与所述第一电压端相连接。
  10. 根据权利要求3所述的移位寄存器，其特征在于，所述上拉控制电路还连接第二时钟信号输入端，用于在所述第二时钟信号输入端的控制下，将所述信号输入端的电压输出至所述上拉节点；以及
    所述上拉控制电路还包括第十二晶体管；所述第十二晶体管的栅极连接所述第二时钟信号输入端，第一极连接所述信号输入端，第二极与所述上拉节点相连接。
  11. 一种栅极驱动电路，其特征在于，包括多个级联的如权利要求1-10任一项所述的移位寄存器；
    第一级移位寄存器的信号输入端连接起始信号端；
    除了第一级移位寄存器以外，上一级移位寄存器的信号输出端与下一级移位寄存器的信号输入端相连接；
    除了最后一级移位寄存器以外，下一级移位寄存器的信号输出端与上一级移位寄存器的复位信号端相连接；以及
    最后一级移位寄存器的复位信号端连接所述起始信号端。
  12. 一种显示装置，其特征在于，包括如权利要求11所述的栅极驱动电路。
  13. 一种用于驱动如权利要求1-10任一项所述的移位寄存器的方法，其特征在于，在一图像帧内，所述方法包括：
    在输入阶段：
    在信号输入端的控制下，上拉控制电路将信号输入端的电压输出至上拉节点；
    上拉电路将所述上拉节点的电位进行存储，并在所述上拉节点的控制下将第一时钟信号输入端的电压输出至信号输出端；以及
    在所述上拉节点的控制下，下拉控制电路将下拉节点的电压下拉至第一电压端的电压；
    在输出阶段：
    上拉电路将上一阶段存储的信号输出至所述上拉节点，在所述上拉节点的控制下，所述上拉电路将所述第一时钟信号输入端的电压至 所述信号输出端，所述信号输出端输出栅极扫描信号；以及
    在所述上拉节点的控制下，所述下拉控制电路将所述下拉节点的电压下拉至所述第一电压端的电压；
    在复位阶段：
    在复位信号端的控制下，复位电路分别将所述上拉节点和所述信号输出端的电压下拉至所述第一电压端的电压；
    在第二时钟信号输入端的控制下，所述下拉控制电路将所述第二时钟信号输入端的电压输出至所述下拉节点；以及
    在所述下拉节点的控制下，下拉电路分别将所述上拉节点和所述信号输出端的电压下拉至所述第一电压端的电压；
    在消隐时间：
    在降噪控制信号端的控制下，降噪控制电路将所述降噪控制信号端的电压输出至所述下拉节点；以及
    在所述下拉节点的控制下，所述下拉电路分别将所述上拉节点和所述信号输出端的电压下拉至所述第一电压端的电压。
  14. 根据权利要求13所述的方法，其特征在于，在所述移位寄存器包括辅助降噪模块的情况下，在一图像帧内，所述方法还包括：
    在所述输入阶段和所述复位阶段：
    在所述第二时钟信号输入端的控制下，所述辅助降噪模块将所述信号输出端的电压下拉至所述第一电压端的电压。
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