WO2016192267A1 - 移位寄存器、栅极驱动电路和显示装置 - Google Patents

移位寄存器、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2016192267A1
WO2016192267A1 PCT/CN2015/092294 CN2015092294W WO2016192267A1 WO 2016192267 A1 WO2016192267 A1 WO 2016192267A1 CN 2015092294 W CN2015092294 W CN 2015092294W WO 2016192267 A1 WO2016192267 A1 WO 2016192267A1
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WIPO (PCT)
Prior art keywords
transistor
pull
signal
node
shift register
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PCT/CN2015/092294
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English (en)
French (fr)
Inventor
青海刚
祁小敬
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/122,592 priority Critical patent/US9805658B2/en
Priority to EP15882910.1A priority patent/EP3306602B1/en
Publication of WO2016192267A1 publication Critical patent/WO2016192267A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/025—Reduction of instantaneous peaks of current

Definitions

  • the present invention relates to the field of display technologies, and in particular to a shift register, a gate drive circuit, and a display device.
  • an external driving chip is generally used to drive pixels on a display panel to display a picture.
  • techniques for directly fabricating the structure of the driving circuit on the display panel have been gradually adopted, for example, The technology of integrating the gate driving circuit into the array driver on array (GOA) of the array substrate.
  • GOA array driver on array
  • a gate driving circuit composed of a multi-stage shift register supplies a scan signal.
  • the conventional shift register uses a diode divider in the pull-down control unit to provide a signal to the gate of the transistor, thereby causing a problem that the instantaneous current of the high level of one end of the diode is discharged through the diode to ground.
  • the invention provides a shift register, a gate driving circuit and a display device, which overcomes the problem of excessive instantaneous current caused by using a diode partial voltage method, avoids a large discharge current, and reduces power consumption.
  • a shift register comprising: a set and reset unit, a pull-down control unit, a pull-down unit, and an output unit.
  • the set and reset unit sets or resets the pull-up node in the output unit in response to the set signal or the reset signal, and when the pull-up node is set to be in the first level state, the output unit responds to the A control signal outputs an output signal through the output of the shift register.
  • the pull-down control unit sets a pull-down node in the pull-down unit in response to the second control signal, and when the pull-down node is set to be in the first level state, the pull-up node is pulled down to A second level state in which the first level state is different.
  • the pull-down control unit includes a transistor and a capacitor, and the second control signal is applied to a gate of the transistor through the capacitor.
  • the pull-up node is set to be in the first level state
  • a gate of a transistor of the pull-down control unit and a pull-down node of the pull-down unit are in the second level state.
  • the output unit may include a first transistor and a first a capacitor, the first control signal is applied to a drain of the first transistor, a gate of the first transistor and a first pole of the first capacitor are commonly connected to the pull-up node, and a source of the first transistor and the first The second pole of the capacitor is connected to the output of the shift register.
  • the pull-down unit may include a second transistor, a third transistor, a fifth transistor and a sixth transistor, and a second capacitor, a gate of the second transistor, a gate of the third transistor, a drain of the fifth transistor, and a second capacitor a first pole connected in common to the pull-down node, a gate of the fifth transistor and a gate of the sixth transistor and a drain of the third transistor are commonly connected to the pull-up node, and a drain of the second transistor is connected to the drain An output of the bit register, a drain of the sixth transistor is coupled to a gate of the transistor of the pull-down control unit, and a second electrode of the second capacitor is coupled to the second transistor, the third transistor, the fifth transistor, and the sixth transistor The various sources.
  • the transistor of the pull-down control unit may be a fourth transistor, and the capacitor of the pull-down control unit may be a third capacitor, and the source of the fourth transistor is connected to the pull-down node.
  • the set and reset unit may include a seventh transistor and an eighth transistor, the set signal being applied to one of a gate of the seventh transistor and a gate of the eighth transistor, the reset signal being applied to the seventh transistor The other of the gate and the gate of the eighth transistor.
  • the first level state may be a high level state
  • the second level state may be a low level state
  • the first to eighth transistors may both be N-type transistors .
  • a high level signal or the second control signal may be applied to a drain of the fourth transistor, and a low level signal may be applied to respective sources of the second transistor, the third transistor, the fifth transistor, and the sixth transistor .
  • the pull-down node is set to be in a high state, and the pull-up node is pulled down to a low state.
  • a source of the seventh transistor and a drain of the eighth transistor may be commonly connected to the pull-up node, and a high level signal may be applied to a drain of the seventh transistor, and a low level signal may be applied to the eighth transistor Source.
  • the drain of the seventh transistor and the source of the eighth transistor may be commonly connected to the pull-up node, and a high level signal may be applied to the drain of the eighth transistor, and a low level signal may be applied to The source of the seventh transistor.
  • the first level state may be a low level state
  • the second level state may be a high level state
  • the first to eighth transistors may both be P Type transistor.
  • a low level signal or the second control signal may be applied to a drain of the fourth transistor, and a high level signal may be applied to the second transistor, the third crystal
  • a drain of the seventh transistor and a source of the eighth transistor may be commonly connected to the pull-up node, and may apply a high level signal to a source of the seventh transistor and a low level signal to the eighth transistor Drain.
  • the source of the seventh transistor and the drain of the eighth transistor may be commonly connected to the pull-up node, and a high level signal may be applied to the source of the eighth transistor, and a low level signal may be applied to The drain of the seventh transistor.
  • the output unit may further include an N-type ninth transistor, and apply a high level signal to a gate of the ninth transistor, the set and reset unit and the pull-down unit pass the Nine transistors are connected to the pull up node.
  • the output unit may further include a P-type ninth transistor, and apply a low level signal to a gate of the ninth transistor, the set and reset unit and the pull-down unit Connected to the pull up node by a ninth transistor.
  • a gate driving circuit comprising n cascaded shift registers according to the present invention, the n being an integer greater than one.
  • the output signal of the shift register of the previous stage is used for the set signal of the shift register of the latter stage, and the output signal of the shift register of the subsequent stage is used for the reset signal of the shift register of the previous stage, or the latter
  • the output signal of the shift register of the stage is used for the set signal of the shift register of the previous stage, and the output signal of the shift register of the previous stage is used for the reset signal of the shift register of the subsequent stage.
  • a display device comprising a gate drive circuit in accordance with the present invention.
  • the gate driving circuit and the display device of the present invention it is possible to overcome the problem of excessive instantaneous current caused by the method of dividing the diode, avoiding a large discharge current and reducing power consumption.
  • Figure 1 schematically illustrates a circuit of a shift register in accordance with one embodiment of the present invention
  • FIG. 2 schematically shows a shift register according to another embodiment of the present invention.
  • FIG. 3 schematically shows a circuit of a shift register according to another embodiment of the present invention
  • FIG. 4 schematically shows a circuit of a shift register according to another embodiment of the present invention.
  • Figure 5 is a signal timing diagram of the shift register shown in Figures 1 to 3;
  • FIG. 6 is a signal timing diagram of the shift register shown in FIG. 4;
  • FIG. 7 is a diagram of a gate driving circuit in accordance with an embodiment of the present invention.
  • FIG. 1 schematically shows a circuit of a shift register in accordance with one embodiment of the present invention.
  • a shift register may include: a set and reset unit, a pull-down control unit, a pull-down unit, and an output unit.
  • the set and reset unit sets or resets the pull-up node PU in the output unit in response to a set or reset signal.
  • the set signal and the reset signal are shown as output signals Out(n-1) and Out(n+1) from the previous stage shift register and the next stage shift register, respectively.
  • the set and reset unit includes two transistors T7 and T8, and a set signal and a reset signal are applied to the gates of the transistors T7 and T8, respectively.
  • control signals CN and CNB are applied to the sources or drains of transistors T7 and T8, respectively.
  • One of the control signals CN and CNB is a high level VGH and the other is a low level VGL.
  • the manner in which the levels of the control signals CN and CNB are selected determines the direction in which the gate drive circuit (shown in Figure 7) is formed in a cascade manner. If CN is high and CNB is low, the scan direction is from top to bottom; taking N-type transistor as an example, the source of transistor T7 and the drain of transistor T8 can be connected together to pull-up node PU And a high level signal CN can be applied to the drain of the transistor T7, and a low level signal CNB can be applied to the source of the transistor T8. If CN is low and CNB is high, the scanning direction is from bottom to top.
  • the drain of transistor T7 and the source of transistor T8 can be To be connected in common to the pull-up node PU, and a high level signal CNB can be applied to the drain of the transistor T8, and a low level signal CN can be applied to the source of the transistor T7.
  • a high level signal CNB can be applied to the drain of the transistor T8
  • a low level signal CN can be applied to the source of the transistor T7.
  • the P-type TFT7 and TFT8 are connected on the opposite side due to different scanning directions, specifically: if CN is high level and CNB is low level, the scanning direction is from top to bottom;
  • the drain of the transistor T7 and the source of the transistor T8 may be commonly connected to the pull-up node PU, and a high level signal CN may be applied to the source of the transistor T7, and a low level signal CNB may be applied to the drain of the transistor T8.
  • the scanning direction is from bottom to top, and the source of transistor T7 and the drain of transistor T8 can be connected in common to pull-up node PU, and can be high-level signal CNB Applied to the source of transistor T8, a low level signal CN is applied to the drain of transistor T7.
  • the output unit includes a transistor T1 and a capacitor C1.
  • the first control signal CK is applied to the drain of the transistor T1, the gate of the transistor T1 and the first pole of the capacitor C1 are commonly connected to the pull-up node PU, and the source of the transistor T1 and the second pole of the capacitor C1 are connected to the shift register The output.
  • the output unit may output through the output of the shift register in response to the first control signal CK Output signal Out(n).
  • the gate of transistor T2, the gate of transistor T3, the drain of transistor T5, and the first pole of capacitor C2 are commonly connected to pull-down node PD.
  • the gate of the transistor T5 and the gate of the transistor T6 and the drain of the transistor T3 are commonly connected to the pull-up node PU.
  • the drain of transistor T2 is coupled to the output of the shift register.
  • the drain of the transistor T6 is connected to the gate of the transistor T4 in the pull-down control unit, and the second pole of the capacitor C2 is connected to the respective sources of the transistor T2, the transistor T3, the transistor T5, and the transistor T6.
  • the pull-down control unit includes a transistor T4 and a capacitor C3, and a second control signal CKB is applied to the gate of the transistor T4 through the capacitor C3.
  • the source of the transistor T4 is connected to the pull-down node PD.
  • the pull-down control unit may set the pull-down node PD in response to the second control signal CKB.
  • the pull-down node PD When the pull-down node PD is set to be in a first level state (eg, a high level state), the pull-up node PU may be pulled down to a second level state different from the first level state (for example, low state).
  • the gate of the transistor T4 of the pull-down control unit and the pull-down node PD are at the second level State (for example, low state).
  • a signal is supplied to the gate of the transistor T4 by using the capacitor C3, thereby avoiding the problem of excessive instantaneous current caused by the method of dividing the diode, avoiding a large discharge current and reducing power consumption.
  • FIG. 2 schematically shows a circuit of a shift register in accordance with another embodiment of the present invention.
  • the embodiment shown in FIG. 2 differs from the embodiment shown in FIG. 1 in that in the circuit of the shift register shown in FIG. 1, a high level signal VGH is applied to the drain of the transistor T4 of the pull-down control unit. In the circuit of the shift register shown in FIG. 2, the second control signal CKB is applied to the drain of the transistor T4 of the pull-down control unit.
  • the respective transistors T1 to T8 are shown as N-type transistors in FIGS. 1 and 2, and the first level state is a high level state and the second level state is a low level state.
  • the set and reset unit sets or resets the pull-up node PU in response to a high-level set signal or a reset signal, and the output unit outputs an output through the output of the shift register in response to the first control signal CK of the high level.
  • the signal Out(n), and the pull-down control unit sets the pull-down node PD in response to the second control signal CKB of the high level.
  • the low level signal VGL is applied to the respective sources of the transistor T2, the transistor T3, the transistor T5, and the transistor T6.
  • a high level signal VGH (FIG. 1) applied to the drain of the transistor T4 or a second control signal CKB (FIG. 2) of a high level may cause the pull-down node PD to be placed Bit is in a high state.
  • the low level signal VGL applied to the source of the transistor T3 causes the pull-up node PU to be pulled down to a low state.
  • each of the transistors T1 to T8 may also be a P-type transistor (as shown in FIG. 4), and the first level state may be a low level state, the second The level state can be a high state.
  • the set and reset unit sets or resets the pull-up node PU in response to a low level set signal or reset signal, and the output unit passes the shift register in response to the low level first control signal CK.
  • the output terminal outputs an output signal Out(n), and the pull-down control unit sets the pull-down node PD in response to the second control signal CKB of the low level.
  • a low level signal can be It is applied to the drain of the transistor T4 of the pull-down control unit, and applies a high level signal to the respective sources of the transistor T2, the transistor T3, the transistor T5, and the transistor T6.
  • a low level signal applied to the drain of the transistor T4 or a second control signal CKB at a low level may cause the pull-down node PD to be set to be in a low state.
  • a high level signal applied to the source of the transistor T3 causes the pull-up node PU to be pulled down to a high state.
  • FIG. 5 is a signal timing diagram of the shift register shown in FIG. 1.
  • the first control signal CK and the second control signal CKB are complementary square wave signals with a duty ratio of 50%
  • the control signal CN is a high level VGH
  • the control signal CNB is a low level VGL
  • the output signal of the previous stage shift register (ie, the set signal) Out(n-1) and the second control signal CKB are at the high level VGH, the next stage.
  • the output signal of the shift register (ie, the reset signal) Out(n+1) and the first control signal CK are at a low level VGL.
  • transistor T7 is turned on and transistor T8 is turned off.
  • the high level VGH of the control signal CN charges the capacitor C1 through the transistor T7, thereby setting the pull-up node PU to a high level state (i.e., the first level state).
  • the transistors T5 and T6 are turned on, such that the gate of the transistor T4 of the pull-down control unit is pulled down to a low level VGL through T6, that is, the gate of the transistor T4 of the pull-down control unit is The low state (ie, the second level state), and thus the transistor T4 is turned off. Further, the pull-down node PD discharges the capacitor C2 through the transistor T5, so that the pull-down node PD is pulled down to the low level VGL, that is, the pull-down node PD is in the low level state (ie, the second level state), and thus the transistors T2 and T3 shut down.
  • the first control signal CK is at a low level VGL and the transistor T1 is turned on because the pull-up node PU is in a high state, and thus the output signal Out(n) outputted from the output of the shift register is first controlled by the transistor T1. CK is pulled down to a low level VGL.
  • the output signal Out(n-1) of the shift register of the previous stage, the output signal Out(n+1) of the shift register of the next stage, and the second control signal CKB Both are low level VGL, so transistors T7, T8 and T4 are both off.
  • the pull-up node PU has no discharge path and thus remains at a high level VGH, so that transistors T1, T5, and T6 remain Turned on, and the pull-down node PD remains in a low state. Since the transistor T1 is turned on, the output signal Out(n) outputted from the output terminal of the shift register is pulled up to the high level VGH by the first control signal CK through the transistor T1.
  • the pull-up node PU is coupled to a higher voltage through capacitor C1 and transistor T1, thereby increasing the charging current.
  • the output signal of the subsequent stage shift register (ie, the reset signal) Out(n+1) and the second control signal CKB are at the high level VGH, and the previous stage shift
  • the output signal of the bit register (ie, the set signal) Out(n-1) and the first control signal CK are at a low level VGL.
  • transistor T8 is turned on and transistor T7 is turned off.
  • the pull-up node PU is discharged through the path formed by the transistor T8, thereby resetting the pull-up node PU to a low state (ie, a second level state).
  • transistors T1, T5, and T6 are turned off.
  • the transition of the second control signal CKB from low level to high level couples the gate of the transistor T4 to a high level through the capacitor C3, so that the transistor T4 is turned on.
  • the high level VGH charges the capacitor C2 through the transistor T4, thereby setting the pull-down node PD to a high level.
  • the transistors T2 and T3 are turned on, so that the output signal Out(n) outputted from the output of the shift register is pulled down to the low level VGL through the transistor T2.
  • the first control signal CK periodically becomes the high level VGH and the second control signal CKB periodically becomes the low level VGL, and the pull-down node PD remains In the high state state, the noise accumulation of the pull-up node PU and the output of the shift register is suppressed, and the normal operation of the shift register is ensured.
  • FIG. 3 and 4 schematically show a circuit of a shift register according to another embodiment of the present invention
  • FIG. 6 is a signal timing chart of the shift register shown in FIG. Figure 3 shows each transistor as an N-type transistor
  • Figure 4 shows each transistor as a P-type transistor. Therefore, only the circuit of the shift register shown in FIG. 3 will be described below, and the difference due to the N-type transistor and the P-type transistor will not be described again.
  • the workflow of the shift register shown in FIG. 6 is substantially the same as the workflow described with reference to FIG. 5 except that the setting modes of the high level and the low level are interchanged, and thus will not be described again.
  • the embodiment shown in FIG. 3 differs from the embodiment shown in FIG. 1 in that in the circuit of the shift register shown in FIG. 3, the output unit further includes an N-type transistor T9, and a high-level signal is used. Applied to the gate of the transistor T9, the set and reset unit and the pull-down unit are connected to the pull-up node PU through the transistor T9. Due to the introduction of transistor T9, in the output stage During the period B, when the pull-up node PU is at a higher level (greater than VGH), the transistor T9 can function as a current limiting clamp for the capacitor C1.
  • FIG. 7 is a diagram of a gate driving circuit in accordance with an embodiment of the present invention.
  • the shift register may be one of the shift registers described in accordance with FIGS. 1 through 6 or an equivalent variant thereof.
  • the output signal of the shift register of the previous stage is used for the set signal of the shift register of the subsequent stage, and the subsequent stage is The output signal of the shift register is used for the reset signal of the shift register of the previous stage; when CN is low and CNB is high, the output signal of the shift register of the latter stage is used for the shift of the previous stage.
  • the set signal of the register, and the output signal of the shift register of the previous stage is used for the reset signal of the shift register of the latter stage.
  • the first shift register and the last shift register that are cascaded pass through a dedicated STV signal to serve as a set signal and/or a reset signal.
  • the complementary square wave signals CK and CKB having a duty ratio of 50% are used as the first control signal and the second control signal of the respective shift registers, respectively.
  • the first control signal and the second control signal between adjacent two shift registers are opposite to each other. For example, if the signal CK is used as the first control signal of the kth shift register and the signal CKB is used as the second control signal of the kth shift register, the signal CKB is used as the k+1th shift register.
  • a control signal and signal CK are used as the second control signal for the k+1th shift register.

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Abstract

一种移位寄存器、栅极驱动电路和显示装置。所述移位寄存器包括置位与复位单元、下拉控制单元、下拉单元和输出单元。置位与复位单元响应于置位信号或复位信号对输出单元中的上拉节点(PU)进行置位或复位，当上拉节点(PU)处于第一电平状态时，输出单元响应于第一控制信号输出输出信号。下拉控制单元响应于第二控制信号对下拉单元中的下拉节点(PD)进行置位，当下拉节点(PD)被置位而处于第一电平状态时，上拉节点(PU)被下拉为与第一电平状态不同的第二电平状态。下拉控制单元包括晶体管(T4)和电容器(C3)，并且通过电容器(C3)将第二控制信号施加至晶体管(T4)的栅极。当上拉节点(PU)被置位而处于第一电平状态时，下拉控制单元的晶体管(T4)的栅极与下拉单元的下拉节点(PD)处于第二电平状态。

Description

移位寄存器、栅极驱动电路和显示装置 技术领域
本发明涉及显示技术领域，具体而言，涉及一种移位寄存器、栅极驱动电路和显示装置。
背景技术
在传统显示器中，一般利用外部驱动芯片来驱动显示面板上的像素以显示画面，但为了减少元件数目并降低制造成本，目前已逐渐采用将驱动电路的结构直接制作在显示面板上的技术，例如，将栅极驱动电路整合于阵列基板的阵列基板行驱动技术(Gate Driver on Array，GOA)的技术。在应用GOA技术的显示面板中，由多级移位寄存器组成的栅极驱动电路提供扫描信号。
然而，传统的移位寄存器在下拉控制单元中使用二极管分压为晶体管的栅极提供信号，从而造成了二极管的一端的高电平通过二极管对地放电的瞬时电流过大的问题。
发明内容
本发明提供一种移位寄存器、栅极驱动电路和显示装置，克服了使用二极管分压的方法造成的瞬时电流过大的问题，避免了大的放电电流，降低了功耗。
根据本发明的一方面，提供一种移位寄存器，包括：置位与复位单元、下拉控制单元、下拉单元以及输出单元。置位与复位单元响应于置位信号或复位信号对输出单元中的上拉节点进行置位或复位，当所述上拉节点被置位而处于第一电平状态时，输出单元响应于第一控制信号通过移位寄存器的输出端输出输出信号。下拉控制单元响应于第二控制信号对下拉单元中的下拉节点进行置位，当所述下拉节点被置位而处于所述第一电平状态时，所述上拉节点被下拉为与所述第一电平状态不同的第二电平状态。所述下拉控制单元包括晶体管和电容器，并且通过所述电容器将所述第二控制信号施加至所述晶体管的栅极。当所述上拉节点被置位而处于所述第一电平状态时，所述下拉控制单元的晶体管的栅极与所述下拉单元的下拉节点处于所述第二电平状态。
根据本发明的实施例，所述输出单元可以包括第一晶体管和第一 电容器，所述第一控制信号施加至第一晶体管的漏极，第一晶体管的栅极和第一电容器的第一极共同连接至所述上拉节点，并且第一晶体管的源极和第一电容器的第二极连接至移位寄存器的输出端。所述下拉单元可以包括第二晶体管、第三晶体管、第五晶体管和第六晶体管以及第二电容器，第二晶体管的栅极、第三晶体管的栅极、第五晶体管的漏极以及第二电容器的第一极共同连接至所述下拉节点，第五晶体管的栅极和第六晶体管的栅极以及第三晶体管的漏极共同连接至所述上拉节点，第二晶体管的漏极连接至移位寄存器的输出端，第六晶体管的漏极连接至所述下拉控制单元的晶体管的栅极，并且第二电容器的第二极连接至第二晶体管、第三晶体管、第五晶体管和第六晶体管的各个源极。所述下拉控制单元的晶体管可以为第四晶体管，并且所述下拉控制单元的电容器可以为第三电容器，第四晶体管的源极连接至所述下拉节点。所述置位与复位单元可以包括第七晶体管和第八晶体管，所述置位信号施加至第七晶体管的栅极和第八晶体管的栅极中的一个，所述复位信号施加至第七晶体管的栅极和第八晶体管的栅极中的另一个。
根据本发明的实施例，所述第一电平状态可以为高电平状态，所述第二电平状态可以为低电平状态，并且所述第一至第八晶体管可以均为N型晶体管。可以将高电平信号或所述第二控制信号施加至第四晶体管的漏极，并且可以将低电平信号施加至第二晶体管、第三晶体管、第五晶体管和第六晶体管的各个源极。当所述第二控制信号为高电平时，所述下拉节点被置位而处于高电平状态，所述上拉节点被下拉为低电平状态。第七晶体管的源极和第八晶体管的漏极可以共同连接至所述上拉节点，并且可以将高电平信号施加至第七晶体管的漏极，将低电平信号施加至第八晶体管的源极。可替换地，第七晶体管的漏极和第八晶体管的源极可以共同连接至所述上拉节点，并且可以将高电平信号施加至第八晶体管的漏极，将低电平信号施加至第七晶体管的源极。
根据本发明的另一实施例，所述第一电平状态可以为低电平状态，所述第二电平状态可以为高电平状态，并且所述第一至第八晶体管可以均为P型晶体管。可以将低电平信号或所述第二控制信号施加至第四晶体管的漏极，并且可以将高电平信号施加至第二晶体管、第三晶 体管、第五晶体管和第六晶体管的各个源极。当所述第二控制信号为低电平时，所述下拉节点被置位而处于低电平状态，所述上拉节点被下拉为高电平状态。第七晶体管的漏极和第八晶体管的源极可以共同连接至所述上拉节点，并且可以将高电平信号施加至第七晶体管的源极，将低电平信号施加至第八晶体管的漏极。可替换地，第七晶体管的源极和第八晶体管的漏极可以共同连接至所述上拉节点，并且可以将高电平信号施加至第八晶体管的源极，将低电平信号施加至第七晶体管的漏极。
根据本发明的实施例，所述输出单元还可以包括N型的第九晶体管，并且将高电平信号施加至第九晶体管的栅极，所述置位与复位单元和所述下拉单元通过第九晶体管连接至所述上拉节点。
根据本发明的另一实施例，所述输出单元还可以包括P型的第九晶体管，并且将低电平信号施加至第九晶体管的栅极，所述置位与复位单元和所述下拉单元通过第九晶体管连接至所述上拉节点。
根据本发明的另一方面，提供了一种栅极驱动电路，其包括n个级联的根据本发明的移位寄存器，所述n为大于1的整数。前一级的移位寄存器的输出信号用于后一级的移位寄存器的置位信号，而后一级的移位寄存器的输出信号用于前一级的移位寄存器的复位信号，或者后一级的移位寄存器的输出信号用于前一级的移位寄存器的置位信号，而前一级的移位寄存器的输出信号用于后一级的移位寄存器的复位信号。
根据本发明的另一方面，提供了一种显示装置，包括根据本发明的栅极驱动电路。
根据本发明的移位寄存器、栅极驱动电路和显示装置，能够克服使用二极管分压的方法所造成的瞬时电流过大的问题，避免了大的放电电流，降低了功耗。
附图说明
通过以下结合附图的详细描述，将更加清楚地理解以上和其它方面、特征和其它优点，其中：
图1示意性地示出了根据本发明的一个实施例的移位寄存器的电路；
图2示意性地示出了根据本发明的另一个实施例的移位寄存器的 电路；
图3示意性地示出了根据本发明的另一个实施例的移位寄存器的电路；
图4示意性地示出了根据本发明的另一个实施例的移位寄存器的电路；
图5为图1至图3所示的移位寄存器的信号时序图；
图6为图4所示的移位寄存器的信号时序图；以及
图7为根据本发明的实施例的栅极驱动电路的示图。
具体实施方式
下文中，将参照附图详细描述本发明构思的示例性实施例。
然而，本发明构思可按照许多不同形式例示，并且不应理解为限于本文阐述的特定实施例。此外，提供这些实施例是为了使得本公开将是彻底和完整的，并且将把本发明构思的范围完全传递给本领域技术人员。
图1示意性地示出了根据本发明的一个实施例的移位寄存器的电路。
如图1所示，根据本发明的实施例的移位寄存器可以包括：置位与复位单元、下拉控制单元、下拉单元以及输出单元。
置位与复位单元响应于置位信号或复位信号对输出单元中的上拉节点PU进行置位或复位。在图1中，将置位信号和复位信号示出为分别来自前一级移位寄存器和来自后一级移位寄存器的输出信号Out(n-1)和Out(n+1)。如图1所示，置位与复位单元包括两个晶体管T7和T8，置位信号和复位信号分别施加于晶体管T7和T8的栅极。此外，控制信号CN和CNB分别施加于晶体管T7和T8的源极或漏极。控制信号CN和CNB两者中一个是高电平VGH，另一个是低电平VGL。控制信号CN和CNB的电平的选择方式决定了以级联方式构成的栅极驱动电路(如图7所示)的扫描的方向。如果CN为高电平并且CNB为低电平，则扫描方向则是从上向下的方向；以N型晶体管为例，晶体管T7的源极和晶体管T8的漏极可以共同连接至上拉节点PU，并且可以将高电平信号CN施加至晶体管T7的漏极，将低电平信号CNB施加至晶体管T8的源极。如果CN为低电平并且CNB为高电平，则扫描方向为从下向上的方向，相应的，晶体管T7的漏极和晶体管T8的源极可 以共同连接至上拉节点PU，并且可以将高电平信号CNB施加至晶体管T8的漏极，将低电平信号CN施加至晶体管T7的源极。应当认识到，这里所指的“从上向下”和/或“从下向上”为图7所显示的方向。当附图中的器件发生旋转时(例如，旋转180°)，则应当相应地解释图中所示的方向。可以理解，P型的TFT7、TFT8在连接上由于扫描方向的不同，连接上相反，具体为：如果CN为高电平并且CNB为低电平，则扫描方向则是从上向下的方向；晶体管T7的漏极和晶体管T8的源极可以共同连接至上拉节点PU，并且可以将高电平信号CN施加至晶体管T7的源极，将低电平信号CNB施加至晶体管T8的漏极。如果CN为低电平并且CNB为高电平，则扫描方向为从下向上的方向，晶体管T7的源极和晶体管T8的漏极可以共同连接至上拉节点PU，并且可以将高电平信号CNB施加至晶体管T8的源极，将低电平信号CN施加至晶体管T7的漏极。
如图1所示，输出单元包括晶体管T1和电容器C1。第一控制信号CK施加至晶体管T1的漏极，晶体管T1的栅极和电容器C1的第一极共同连接至上拉节点PU，并且晶体管T1的源极和电容器C1的第二极连接至移位寄存器的输出端。
当通过置位与复位单元使上拉节点PU被置位而处于第一电平状态(例如，高电平状态)时，输出单元可以响应于第一控制信号CK通过移位寄存器的输出端输出输出信号Out(n)。
晶体管T2的栅极、晶体管T3的栅极、晶体管T5的漏极以及电容器C2的第一极共同连接至下拉节点PD。晶体管T5的栅极和晶体管T6的栅极以及晶体管T3的漏极共同连接至上拉节点PU。晶体管T2的漏极连接至移位寄存器的输出端。晶体管T6的漏极连接至下拉控制单元中的晶体管T4的栅极，并且电容器C2的第二极连接至晶体管T2、晶体管T3、晶体管T5和晶体管T6的各个源极。
如图1所示，下拉控制单元包括晶体管T4和电容器C3，并且通过电容器C3将第二控制信号CKB施加至晶体管T4的栅极。晶体管T4的源极连接至下拉节点PD。
下拉控制单元可以响应于第二控制信号CKB对下拉节点PD进行置位。当下拉节点PD被置位而处于第一电平状态(例如，高电平状态)时，上拉节点PU可以被下拉为与第一电平状态不同的第二电平状态 (例如，低电平状态)。
当通过置位与复位单元使上拉节点PU被置位而处于第一电平状态(例如，高电平状态)时，下拉控制单元的晶体管T4的栅极与下拉节点PD处于第二电平状态(例如，低电平状态)。
在下拉控制单元中，通过使用电容器C3为晶体管T4的栅极提供信号，从而避免了使用二极管分压的方法造成的瞬时电流过大的问题，避免了大的放电电流，并降低了功耗。
图2示意性地示出了根据本发明的另一个实施例的移位寄存器的电路。
图2所示的实施例与图1所示的实施例的不同之处在于，在图1所示的移位寄存器的电路中，将高电平信号VGH施加至下拉控制单元的晶体管T4的漏极；在图2所示的移位寄存器的电路中，将第二控制信号CKB施加至下拉控制单元的晶体管T4的漏极。
在图1和图2中将各个晶体管T1至T8示出为N型晶体管，并且所述第一电平状态为高电平状态，所述第二电平状态为低电平状态。置位与复位单元响应于高电平的置位信号或复位信号对上拉节点PU进行置位或复位，输出单元响应于高电平的第一控制信号CK通过移位寄存器的输出端输出输出信号Out(n)，并且下拉控制单元响应于高电平的第二控制信号CKB对下拉节点PD进行置位。此外，在图1和图2中，将低电平信号VGL施加至晶体管T2、晶体管T3、晶体管T5和晶体管T6的各个源极。响应于第二控制信号CKB为高电平，施加在晶体管T4的漏极的高电平信号VGH(图1)或高电平的第二控制信号CKB(图2)可以使得下拉节点PD被置位而处于高电平状态。响应于下拉节点PD处于高电平状态，施加在晶体管T3的源极的低电平信号VGL使得上拉节点PU被下拉为低电平状态。
然而，本领域技术人员还应当清楚的是，各个晶体管T1至T8也可以为P型晶体管(如图4所示)，并且所述第一电平状态可以为低电平状态，所述第二电平状态可以为高电平状态。在此情况下，置位与复位单元响应于低电平的置位信号或复位信号对上拉节点PU进行置位或复位，输出单元响应于低电平的第一控制信号CK通过移位寄存器的输出端输出输出信号Out(n)，并且下拉控制单元响应于低电平的第二控制信号CKB对下拉节点PD进行置位。因而，可以将低电平信号 施加至下拉控制单元的晶体管T4的漏极，并且将高电平信号施加至晶体管T2、晶体管T3、晶体管T5和晶体管T6的各个源极。响应于第二控制信号CKB为低电平，施加在晶体管T4的漏极的低电平信号或低电平的第二控制信号CKB可以使得下拉节点PD被置位而处于低电平状态。响应于下拉节点PD处于低电平状态，施加在晶体管T3的源极的高电平信号使得上拉节点PU被下拉为高电平状态。
下面，以图1所示的实施例为例，对根据本发明的移位寄存器的电路的工作原理进行简要说明。
图5为图1所示的移位寄存器的信号时序图。
参见图1和图5，第一控制信号CK和第二控制信号CKB为占空比为50％的互补方波信号，控制信号CN为高电平VGH，并且控制信号CNB为低电平VGL，即，图1所示的移位寄存器的所级联的栅极驱动的扫描方向为“从上向下”的方向。
在输入阶段(图5所示的阶段A)，前一级移位寄存器的输出信号(即，置位信号)Out(n-1)和第二控制信号CKB为高电平VGH，后一级移位寄存器的输出信号(即，复位信号)Out(n+1)和第一控制信号CK为低电平VGL。在此情况下，晶体管T7开启，而晶体管T8关闭。控制信号CN的高电平VGH通过晶体管T7对电容器C1进行充电，从而将上拉节点PU置位为高电平状态(即，第一电平状态)。响应于上拉节点PU处于高电平状态，晶体管T5和T6开启，使得下拉控制单元的晶体管T4的栅极通过T6被下拉为低电平VGL，即，下拉控制单元的晶体管T4的栅极处于低电平状态(即，第二电平状态)，因而晶体管T4关闭。此外，下拉节点PD通过晶体管T5将电容器C2放电，使得下拉节点PD被下拉为低电平VGL，即，下拉节点PD处于低电平状态(即，第二电平状态)，因而晶体管T2和T3关闭。第一控制信号CK为低电平VGL并且由于上拉节点PU处于高电平状态而使得晶体管T1开启，因而移位寄存器的输出端输出的输出信号Out(n)通过晶体管T1被第一控制信号CK下拉为低电平VGL。
在输出阶段(图5所示的阶段B)，前一级移位寄存器的输出信号Out(n-1)、后一级移位寄存器的输出信号Out(n+1)和第二控制信号CKB均为低电平VGL，因而晶体管T7、T8和T4均关闭。上拉节点PU没有放电路径，因而保持为高电平VGH，从而晶体管T1、T5和T6保持 开启，并且下拉节点PD保持在低电平状态。由于晶体管T1开启，因而移位寄存器的输出端输出的输出信号Out(n)通过晶体管T1被第一控制信号CK上拉为高电平VGH。此外，上拉节点PU通过电容器C1和晶体管T1被耦合到更高的电压，从而增大充电电流。
在复位阶段(图5所示的阶段C)，后一级移位寄存器的输出信号(即，复位信号)Out(n+1)和第二控制信号CKB为高电平VGH，前一级移位寄存器的输出信号(即，置位信号)Out(n-1)和第一控制信号CK为低电平VGL。在此情况下，晶体管T8开启，而晶体管T7关闭。上拉节点PU通过晶体管T8形成的路径放电，从而将上拉节点PU复位为低电平状态(即，第二电平状态)。响应于上拉节点PU处于低电平状态，晶体管T1、T5和T6关闭。由于晶体管T6关闭，因此第二控制信号CKB从低电平到高电平的跳变通过电容器C3将晶体管T4的栅极耦合为高电平，从而晶体管T4开启。高电平VGH通过晶体管T4对电容器C2进行充电，从而将下拉节点PD设置为高电平。响应于下拉节点PD处于高电平状态，晶体管T2和T3开启，从而移位寄存器的输出端输出的输出信号Out(n)通过晶体管T2被下拉为低电平VGL。
在一帧内除阶段A至C以外的其他时间段内，第一控制信号CK周期性地变为高电平VGH而第二控制信号CKB周期性地变为低电平VGL，下拉节点PD保持在高电平状态，从而抑制上拉节点PU和移位寄存器的输出端的噪声积累，保证移位寄存器的正常工作。
图3和图4示意性地示出了根据本发明的另一个实施例的移位寄存器的电路，并且图6为图4所示的移位寄存器的信号时序图。图3将各个晶体管示出为N型晶体管，而图4将各个晶体管示出为P型晶体管。因此，下面将仅以对图3所示的移位寄存器的电路进行说明，而不再赘述由于N型晶体管和P型晶体管所导致的差别。此外，除了将高电平和低电平的设置方式互换以外，图6所示的移位寄存器的工作流程与参考图5描述的工作流程实质上相同，因而不再赘述。
图3所示的实施例与图1所示的实施例的不同之处在于，在图3所示的移位寄存器的电路中，输出单元还包括N型的晶体管T9，并且将高电平信号施加至晶体管T9的栅极，置位与复位单元和下拉单元通过晶体管T9连接至上拉节点PU。由于引入了晶体管T9，在输出阶段 B期间，当上拉节点PU为更高的高电平(大于VGH)时，晶体管T9可以对电容器C1能起到限流钳位的作用。
图7为根据本发明的实施例的栅极驱动电路的示图。
在图7所示的栅极驱动电路中包括了多个级联的移位寄存器。移位寄存器可以为根据图1至图6描述的移位寄存器之一或其等效变形。以N型晶体管的情况为例，当CN为高电平而CNB为低电平时，前一级的移位寄存器的输出信号用于后一级的移位寄存器的置位信号，而后一级的移位寄存器的输出信号用于前一级的移位寄存器的复位信号；当CN为低电平而CNB为高电平时，后一级的移位寄存器的输出信号用于前一级的移位寄存器的置位信号，而前一级的移位寄存器的输出信号用于后一级的移位寄存器的复位信号。此外，为级联的第一个移位寄存器和最后一个移位寄存器通过专用的STV信号以用作置位信号和/或复位信号。
占空比为50％的互补方波信号CK和CKB分别用作各个移位寄存器的第一控制信号和第二控制信号。相邻两个移位寄存器之间的第一控制信号和第二控制信号是彼此相反的。例如，如果信号CK用作第k个移位寄存器的第一控制信号而信号CKB用作第k个移位寄存器的第二控制信号，则信号CKB用作第k+1个移位寄存器的第一控制信号而信号CK用作第k+1个移位寄存器的第二控制信号。
虽然已经示出并说明了各个示例性实施例，但本领域普通技术人员应当理解的是，可以对这些示例性实施例在形式和细节方面做出各种改变而不背离由所附权利要求书限定的本发明构思的精神和范围。

Claims (8)

  1. 一种移位寄存器，包括：置位与复位单元、下拉控制单元、下拉单元以及输出单元，
    其中，置位与复位单元响应于置位信号或复位信号对输出单元中的上拉节点进行置位或复位，当所述上拉节点被置位而处于第一电平状态时，输出单元响应于第一控制信号通过移位寄存器的输出端输出输出信号，并且
    其中，下拉控制单元响应于第二控制信号对下拉单元中的下拉节点进行置位，当所述下拉节点被置位而处于所述第一电平状态时，所述上拉节点被下拉为与所述第一电平状态不同的第二电平状态，
    所述下拉控制单元包括晶体管和电容器，并且通过所述电容器将所述第二控制信号施加至所述晶体管的栅极，
    当所述上拉节点被置位而处于所述第一电平状态时，所述下拉控制单元的晶体管的栅极与所述下拉单元的下拉节点处于所述第二电平状态。
  2. 根据权利要求1所述的移位寄存器，其中，
    所述输出单元包括第一晶体管和第一电容器，所述第一控制信号施加至第一晶体管的漏极，第一晶体管的栅极和第一电容器的第一极共同连接至所述上拉节点，并且第一晶体管的源极和第一电容器的第二极连接至移位寄存器的输出端，
    所述下拉单元包括第二晶体管、第三晶体管、第五晶体管和第六晶体管以及第二电容器，第二晶体管的栅极、第三晶体管的栅极、第五晶体管的漏极以及第二电容器的第一极共同连接至所述下拉节点，第五晶体管的栅极和第六晶体管的栅极以及第三晶体管的漏极共同连接至所述上拉节点，第二晶体管的漏极连接至移位寄存器的输出端，第六晶体管的漏极连接至所述下拉控制单元的晶体管的栅极，并且第二电容器的第二极连接至第二晶体管、第三晶体管、第五晶体管和第六晶体管的各个源极，
    所述下拉控制单元的晶体管为第四晶体管，并且所述下拉控制单元的电容器为第三电容器，第四晶体管的源极连接至所述下拉节点，
    所述置位与复位单元包括第七晶体管和第八晶体管，所述置位信 号施加至第七晶体管的栅极和第八晶体管的栅极中的一个，所述复位信号施加至第七晶体管的栅极和第八晶体管的栅极中的另一个。
  3. 根据权利要求2所述的移位寄存器，其中，
    所述第一电平状态为高电平状态，所述第二电平状态为低电平状态，并且所述第一至第八晶体管均为N型晶体管，
    其中，将高电平信号或所述第二控制信号施加至第四晶体管的漏极，将低电平信号施加至第二晶体管、第三晶体管、第五晶体管和第六晶体管的各个源极，并且
    其中，当所述第二控制信号为高电平时，所述下拉节点被置位而处于高电平状态，所述上拉节点被下拉为低电平状态，
    第七晶体管的源极和第八晶体管的漏极共同连接至所述上拉节点，并且将高电平信号施加至第七晶体管的漏极，将低电平信号施加至第八晶体管的源极；或者
    第七晶体管的漏极和第八晶体管的源极共同连接至所述上拉节点，并且将高电平信号施加至第八晶体管的漏极，将低电平信号施加至第七晶体管的源极。
  4. 根据权利要求2所述的移位寄存器，其中，
    所述第一电平状态为低电平状态，所述第二电平状态为高电平状态，并且所述第一至第八晶体管均为P型晶体管，
    其中，将低电平信号或所述第二控制信号施加至第四晶体管的漏极，将高电平信号施加至第二晶体管、第三晶体管、第五晶体管和第六晶体管的各个源极，并且
    其中，当所述第二控制信号为低电平时，所述下拉节点被置位而处于低电平状态，所述上拉节点被下拉为高电平状态，
    第七晶体管的漏极和第八晶体管的源极共同连接至所述上拉节点，并且将高电平信号施加至第七晶体管的源极，将低电平信号施加至第八晶体管的漏极；或者
    第七晶体管的源极和第八晶体管的漏极共同连接至所述上拉节点，并且将高电平信号施加至第八晶体管的源极，将低电平信号施加至第七晶体管的漏极。
  5. 根据权利要求3所述的移位寄存器，其中，
    所述输出单元还包括N型的第九晶体管，并且将高电平信号施加 至第九晶体管的栅极，所述置位与复位单元和所述下拉单元通过第九晶体管连接至所述上拉节点。
  6. 根据权利要求4所述的移位寄存器，其中，
    所述输出单元还包括P型的第九晶体管，并且将低电平信号施加至第九晶体管的栅极，所述置位与复位单元和所述下拉单元通过第九晶体管连接至所述上拉节点。
  7. 一种栅极驱动电路，包括n个级联的如权利要求1至6中任一项所述的移位寄存器，所述n为大于1的整数，
    其中，前一级的移位寄存器的输出信号用于后一级的移位寄存器的置位信号，而后一级的移位寄存器的输出信号用于前一级的移位寄存器的复位信号，或者
    后一级的移位寄存器的输出信号用于前一级的移位寄存器的置位信号，而前一级的移位寄存器的输出信号用于后一级的移位寄存器的复位信号。
  8. 一种显示装置，包括如权利要求7所述的栅极驱动电路。
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