WO2017133155A1 - 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置 - Google Patents

移位寄存器单元及其驱动方法、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2017133155A1
WO2017133155A1 PCT/CN2016/085702 CN2016085702W WO2017133155A1 WO 2017133155 A1 WO2017133155 A1 WO 2017133155A1 CN 2016085702 W CN2016085702 W CN 2016085702W WO 2017133155 A1 WO2017133155 A1 WO 2017133155A1
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Prior art keywords
clock signal
shift register
register unit
pull
noise reduction
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PCT/CN2016/085702
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English (en)
French (fr)
Inventor
陈华斌
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US15/504,551 priority Critical patent/US10607529B2/en
Publication of WO2017133155A1 publication Critical patent/WO2017133155A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0823—Several active elements per pixel in active matrix panels used to establish symmetry in driving, e.g. with polarity inversion
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes

Definitions

  • the present disclosure relates to the field of display driving technologies, and in particular, to a shift register unit and a driving method thereof, a gate driving circuit, and a display device.
  • the shift register unit in the related art controls the pull-down gate drive signal by the pull-down node in the output cut-off hold phase.
  • the pull-down time of the gate drive signal during the output cut-off hold phase is 50%, and the gate drive signal may not remain due to the leakage of the pull-up transistor during the other period in which the gate drive signal is not pulled down. Low level, therefore, no good noise reduction for the gate drive signal.
  • a main object of the present disclosure is to provide a shift register unit and a driving method thereof, a gate driving circuit, and a display device, which solve the related art in which the pull-down time of the gate driving signal is 50% in the output cut-off holding phase, and
  • the gate drive signal may not be kept low due to the leakage of the pull-up transistor during the pull-down of the gate drive signal, so that the gate drive signal cannot be used by the existing gate drive signal output module. Good noise reduction problem.
  • the present disclosure provides a shift register unit including a pull-up node control module, a pull-down node control module, a gate driving signal output terminal, and a gate driving signal output module, and the gate driving signal output module Connected to the pull-up node, the pull-down node, the positive-phase clock signal input end, and the gate drive signal output end respectively; the pull-down node control module is respectively connected to the pull-down node and the inverted clock signal input end;
  • the shift register unit further includes: a noise reduction module, which is respectively connected to the noise reduction control signal output end and the gate drive signal output end.
  • the pull-down node control module is configured to control a potential of the pull-down node to be the same as a potential of the inverted clock signal during an output cut-off hold phase; and during a output cut-off hold phase, a noise reduction control signal and the inverse The phase clock signals are mutually inverted; the noise reduction module is configured to control the gate drive signal output terminal to be connected to a low level when the noise reduction control signal is valid; the positive phase clock signal and the reverse phase The clock signals are inverted from each other.
  • the noise reduction control signal output end is connected to a pull-down node of the N+nth stage shift register unit.
  • n is a positive integer
  • N is the number of stages of the shift register unit in the gate drive circuit.
  • the noise reduction control signal output terminal is further connected to the pull-down node of the N+m-stage shift register unit, and m is a positive integer smaller than n.
  • the noise reduction control signal output end is connected to a pull-down node of an adjacent next-stage shift register unit;
  • the noise reduction module includes: a noise reduction transistor, the gate is connected to the pull-down node of the adjacent next-stage shift register unit, the first pole is connected to the gate drive signal output end, and the second pole is connected to the low level;
  • the signal input terminal provides a positive phase clock signal for the shift register unit of the stage, and the input signal of the second clock signal is provided with an inverted clock signal for the shift register unit of the stage; the input end of the second clock signal is adjacent to the next stage.
  • the bit register unit provides a positive phase clock signal, and the first clock signal input terminal provides an inverted clock signal for the adjacent next stage shift register unit.
  • the noise reduction control signal output end is connected to the pull-down node of the N+2th stage shift register unit;
  • the noise reduction module includes: a first noise reduction transistor having a gate connected to a pull-down node of the N+2 stage shift register unit, a first pole connected to the gate drive signal output terminal, and a second pole connected to a low level;
  • a clock signal input terminal provides a positive phase clock signal for the stage shift register unit, and the third clock signal input terminal provides an inverted clock signal for the stage shift register unit; and the third clock signal input terminal is the N+2
  • the stage shift register unit provides a positive phase clock signal, and the first clock signal input terminal provides an inverted clock signal for the N+2th stage shift register unit; the first clock signal and the third clock signal are inverted;
  • the second clock signal Deferred by 0.25 clock cycles from the first clock signal, the fourth clock signal is delayed by 0.25 clock cycles than the third clock signal, the first clock signal, the second clock signal, and the third clock
  • the noise reduction module includes: a second noise reduction transistor, a gate connected to the pull-down node of the (N+1)th shift register unit, and a first pole and the gate driving signal output The terminal is connected, the second pole is connected to the low level; the second clock signal input terminal provides the positive phase clock signal for the (N+1)th shift register unit, and the fourth clock signal input terminal is the N+1th shift
  • the register unit provides an inverted clock signal.
  • the present disclosure also provides a driving method of a shift register unit, which is applied to the shift register unit described above, the driving method includes: controlling an electric potential of a pull-down node and a potential of an inverted clock signal in an output cut-off holding phase; In the output cut-off holding phase, the control noise reduction control signal and the inverted clock signal are mutually inverted; when the noise reduction control signal is valid, the noise reduction module controls the gate drive signal output terminal to be connected to a low level.
  • the present disclosure also provides a gate driving circuit including a plurality of stages of the above shift register unit.
  • the noise reduction control signal output end of the Nth stage shift register unit is connected to the pulldown node of the N+nth stage shift register unit.
  • n and N are positive integers.
  • the noise reduction control signal output terminal of the Nth stage shift register unit is further connected to the pulldown node of the N+mth stage shift register unit, and m is a positive integer smaller than n.
  • the noise reduction control signal output end of the Nth stage shift register unit is connected to the pull-down node of the N+1th stage shift register unit.
  • the noise reduction control signal output end of the Nth stage shift register unit is connected to the pulldown node of the N+2 stage shift register unit.
  • Providing a positive phase clock signal for the Nth stage shift register unit by the first clock signal input terminal, and providing an inverted clock signal for the Nth stage shift register unit by the third clock signal input end; and the third clock signal input end by the third clock signal input end Providing a positive phase clock signal for the N+2 stage shift register unit, and providing an inverted clock signal for the N+2th stage shift register unit by the first clock signal input terminal; the first clock signal
  • the third clock signal is inverted by a second clock signal; the second clock signal is delayed by 0.25 clock cycles from the first clock signal, and the fourth clock signal is delayed by 0.25 clock cycles from the third clock signal, the duty ratio of the first clock signal, and the second
  • the duty ratio of the clock signal, the duty ratio of the third clock signal, and the duty ratio of the fourth clock signal are both 0.5.
  • m is equal to 1; the second clock signal input terminal provides a positive phase clock signal for the (N+1)th shift register unit, and the fourth clock signal input terminal provides an inverted phase for the N+1th shift register unit. Clock signal.
  • the present disclosure also provides a display device including the above-described gate drive circuit.
  • the gate driving circuit and the display device of the present disclosure employ a noise reduction module controlled by a noise reduction control signal together with a gate driving signal output module in the related art
  • the control denoises the gate drive signal, and the gate drive signal is also pulled down during a period in which the positive phase clock signal is at a high level during the output off-hold phase, thereby improving the noise reduction effect.
  • 1A is a circuit diagram of a shift register unit in the related art
  • FIG. 1B is a timing chart showing the operation of the shift register unit shown in FIG. 1A;
  • FIG. 2 is a block diagram of a shift register unit of at least some embodiments of the present disclosure
  • 3A is a timing chart showing the operation of the shift register unit shown in FIG. 2 when two clock signals are connected;
  • FIG. 3B is a timing chart showing the operation when the shift register unit shown in FIG. 2 is connected to four clock signals;
  • FIG. 4 is a circuit diagram of a shift register unit of at least some embodiments of the present disclosure.
  • Figure 5 is a timing chart showing the operation of the shift register unit shown in Figure 4.
  • FIG. 6 is a circuit diagram of a shift register unit of at least some embodiments of the present disclosure.
  • Figure 7 is a timing chart showing the operation of the shift register unit shown in Figure 6;
  • FIG. 8 is a block diagram of a gate drive circuit of at least some embodiments of the present disclosure.
  • FIG. 9 is a block diagram of a gate drive circuit of at least some embodiments of the present disclosure.
  • FIG. 10 is a timing chart when the gate driving circuit shown in FIG. 9 is connected to four clock signals.
  • FIG. 1A is a circuit diagram of a shift register unit in the related art
  • FIG. 1B is an operation timing chart of the shift register unit shown in FIG. 1A.
  • S1 represents an input phase
  • S2 represents an output phase
  • S3 represents a reset phase
  • S4 represents the output cutoff holding phase.
  • INPUT represents the input terminal
  • CLK represents the positive phase clock signal input terminal
  • RESET represents the reset terminal
  • VSS represents the low level
  • M1 is the input transistor
  • M2 is the first reset transistor
  • M3 is the pull-up transistor
  • M4 is a second reset transistor
  • M5 is a first pull-down node control transistor
  • M6 is a second pull-down node control transistor
  • M8 is a first pull-down control node control transistor
  • M9 is a second pull-down control node control transistor
  • M10 is a pull-up node Control transistor
  • C1 is the storage capacitor
  • PD_CN indicates the pull-down control node
  • PU indicates the pull-up node.
  • the shift register unit in the related art denoises the gate drive signal output terminal OUTPUT only through the pull-down node PD, but the pull-down node PD inputs the waveform at the output off-hold phase and the inverted clock signal input terminal CLKB.
  • the waveform of the inverted clock signal is the same, that is, the gate potential of the pull-down transistor M11 for pulling down the gate drive signal is only 50%. Since the size of the pull-up transistor M3 in FIG. 1A is relatively large, the parasitic capacitance of M3 is relatively large; as shown in FIG. 1B, in the output off-hold phase S4, the parasitic capacitance between the CLK and the pull-up node PU is relatively large.
  • the leakage current of the M3 is relatively large, so that the M3 is not completely turned off, so that the gate drive signal of the OUTPUT output at this time is made. It is not low, so it cannot degrade the gate drive signal very well.
  • embodiments of the present disclosure provide a shift register unit.
  • the shift register unit of the embodiment of the present disclosure includes a pull-up node control module 21, a pull-down node control module 22, a gate drive signal output terminal OUTPUT (N), and a gate drive signal output module 23 .
  • N is a positive integer
  • N is the number of stages of the shift register unit in the entire gate drive circuit according to the embodiment of the disclosure.
  • the pull-down node control module 22 is respectively connected to the pull-down node PD (N) and the inverted clock signal input terminal CLKB.
  • the shift register unit further includes: a noise reduction module 24 connected to the noise reduction control signal output terminal Ctrl and the gate drive signal output terminal OUTPUT (N), respectively.
  • the shift register unit uses the noise reduction module controlled by the noise reduction control signal to control the gate drive signal denoising together with the gate drive signal output module in the related art, and is in the output cutoff holding phase.
  • the period in which the phase clock signal is at a high level also pulls down the gate drive signal, thereby improving the noise reduction effect.
  • the pull-up node control module 21 is coupled to the pull-up node PU(N) for controlling the potential of the pull-up node PU(N).
  • the pull-down node control module 22 is configured to control the potential of the pull-down node and the inverse in an output cut-off hold phase.
  • the phase clock signal has the same potential.
  • the inverted clock signal input from the inverted clock signal input terminal CLKB and the noise reduction control signal outputted from the noise reduction control signal output terminal Ctrl are inverted from each other.
  • the noise reduction module 24 is configured to control the gate drive signal output terminal OUTPUT (N) to enter a low level when the noise reduction control signal is valid.
  • the positive phase clock signal and the inverted clock signal are mutually inverted.
  • the gate driving signal output module includes a gate of the pull-down transistor for denoising the gate driving signal output end and a pull-down node, and the pull-down transistor is turned on when the potential of the pull-down node is valid.
  • the waveform of the signal accessed by the pull-down node in the output cut-off hold phase is the same as the waveform of the inverted clock signal, that is, the pull-down time of the gate drive signal in the output cut-off hold phase is 50%, so only
  • the gate drive signal can not be well denoised by the gate drive signal output module in the related art, and the shift register unit of the embodiment of the present disclosure sets the noise reduction control signal to be inverted with the inverted clock signal.
  • the gate driving signal is discharged by the noise reduction module controlled by the noise reduction control signal, so that the pull-down time of the gate driving signal is increased from 50% to 100%, thereby enhancing the noise reduction of the gate driving signal. effect.
  • the noise reduction control signal output end is shifted from the N+nth stage.
  • the pull-down node of the register unit is connected, n is a positive integer, and N is the number of stages of the shift register unit in the gate drive circuit.
  • the noise reduction control signal output end is The pull-down node PD(N+1) of the N+1th shift register unit is connected, that is, when the positive phase clock signal input end of the Nth stage shift register unit is connected to the first clock signal CLK1, the Nth stage shift register
  • the inverted clock signal input end of the unit is connected to the second clock signal CLK2
  • the positive phase clock signal input end of the (N+1)th shift register unit is connected to the second clock signal CLK2
  • the N+1th shift register unit The inverted clock signal input terminal is connected to the first clock signal CLK1.
  • the signal accessed by PD(N+1) is the same as CLK1
  • the signal accessed by PD(N) is the same as CLK2
  • PD(N The +1) access signal is inverted from the PD(N) access signal.
  • the gate driving circuit accesses the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4, the noise reduction control signal output end and the The pull-down node PD(N+2) of the N+2 stage shift register unit is connected, CLK1 and CLK3 are inverted, and CLK2 and CLK4 are inverted.
  • the noise reduction control signal The output end is connected to the pull-down node of the N+3 stage shift register unit, the first clock signal is inverted with the fourth clock signal, the second clock signal is inverted with the fifth clock signal, and the third clock signal is sixth.
  • the clock signal is inverted, when the positive phase clock signal input end of the Nth stage shift register unit is connected to the first clock signal, and the inverted clock signal input end of the Nth stage shift register unit is connected to the fourth clock signal,
  • the positive phase clock signal input end of the N+1 stage shift register unit is connected to the second clock signal, and the inverted clock signal input end of the N+1th stage shift register unit is connected to the fifth clock signal, the N+2 stage
  • the positive phase clock signal input end of the shift register unit is connected to the third clock signal, and the inverted clock signal input end of the N+2 stage shift register unit is connected to the sixth clock signal, and the N+3th stage shift register unit is
  • the positive phase clock signal input end is connected to the fourth clock signal, and the inverted clock signal input end of the N+3 stage shift register unit is connected to the first clock signal, and the positive phase clock of the N+4th stage shift register unit is The signal input end is connected to the fifth clock signal, and the inverted clock signal input end of the N+4 stage shift register
  • the N+5 shift The inverted clock signal input end of the unit is connected to the third clock signal; the signal of the pull-down node of the N+3 shift register unit is the same as the first clock signal, and the pull-down node of the N-th shift register unit is connected
  • the incoming signal is the same as the fourth clock signal, and the signal accessed by the pull-down node of the N+3 stage shift register unit is inverted with the signal accessed by the pull-down node of the N-th stage shift register unit.
  • n is equal to a larger positive integer of 4, 5, etc., and so on.
  • the noise reduction control signal output terminal is further connected to the pull-down node of the N+m-stage shift register unit, and m is a positive integer smaller than n.
  • the noise reduction control signal output can also be connected to the pull-down node of other stage shift register units to further optimize the noise reduction effect.
  • the noise reduction control signal output terminal is connected to a pull-down node of an adjacent next-stage shift register unit.
  • the noise reduction module includes: a noise reduction transistor, a gate connected to a pull-down node of the adjacent next-stage shift register unit, a first pole connected to the gate drive signal output end, and a second pole connected low Level.
  • the first clock signal input terminal provides a positive phase clock signal for the stage shift register unit
  • the second clock signal input terminal provides an inverted clock signal for the stage shift register unit
  • the second clock signal input terminal provides a positive phase clock signal for the adjacent next stage shift register unit
  • the first clock signal input terminal provides an inverted clock signal for the adjacent next stage shift register unit.
  • the noise reduction control signal output terminal is connected to a pull-down node of the N+2th stage shift register unit.
  • the noise reduction module includes: a first noise reduction transistor, a gate connected to the pull-down node of the N+2 stage shift register unit, a first pole connected to the gate drive signal output end, and a second pole connection Go low.
  • the first clock signal input terminal provides a positive phase clock signal for the stage shift register unit
  • the third clock signal input terminal provides an inverted clock signal for the stage shift register unit.
  • the third clock signal input terminal provides a positive phase clock signal for the N+2 stage shift register unit, and the first clock signal input terminal provides an inverted clock signal for the N+2 stage shift register unit.
  • the first clock signal and the third clock signal are inverted.
  • the second clock signal is delayed by 0.25 clock cycles from the first clock signal
  • the fourth clock signal is delayed by 0.25 clock cycles than the third clock signal, the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal
  • the duty cycle is 0.5.
  • the noise reduction control signal output terminal is further connected to the pull-down node of the (N+1)th shift register unit.
  • the noise reduction module includes: a second noise reduction transistor, a gate connected to the pull-down node of the N+1th stage shift register unit, a first pole connected to the gate drive signal output end, and a second pole connection Enter a low level to further optimize the noise reduction effect.
  • the second clock signal input terminal provides a positive phase clock signal for the (N+1)th shift register unit
  • the fourth clock signal input terminal provides an inverted clock signal for the (N+1)th shift register unit.
  • the first embodiment of the shift register unit of the present disclosure includes a pull-up node control module 11, a pull-down node control module 12, a gate drive signal output terminal OUTPUT (N), and a gate drive signal.
  • the pull-up node control module 11 includes:
  • the first pull-up node controls the transistor M111, the gate and the source are both connected to the input terminal INPUT, and the drain is connected to the pull-up node PU(N);
  • the second pull-up node controls the transistor M112, the gate is connected to the reset terminal RESET, the source is connected to the pull-up node PU(N), and the source is connected to the low level VSS;
  • the third pull-up node controls the transistor M113, the gate is connected to the pull-down node PD(N), the source is connected to the pull-up node PU(N), and the source is connected to the low level VSS;
  • the storage capacitor C1 has a first end connected to the pull-up node PU(N) and a second end connected to the gate drive signal output terminal OUTPUT(N).
  • M111, M112, and M113 are drawn in a dotted line frame labeled 11, although the storage capacitor C1 is not drawn in the dotted line frame labeled 11 due to inconvenience in drawing, the storage capacitor C1 is also included in Pull up the node control module 11.
  • the pull-down node control module 12 includes:
  • the first pull-down control node controls the transistor M121, the gate and the source are both connected to the inverted clock signal input terminal CLKB, and the drain is connected to the pull-down control node PD_CN;
  • the second pull-down control node controls the transistor M122, the gate is connected to the pull-up node PU(N), the source is connected to the pull-down control node PD_CN, and the drain is connected to the low level VSS;
  • the first pull-down node controls the transistor M123, the gate is connected to the pull-down control node PD_CN, the source is connected to the inverted clock signal input terminal CLKB, and the drain is connected to the pull-down node PD(N);
  • the second pull-down node controls the transistor M124, the gate is connected to the pull-up node PU(N), the source is connected to the pull-down node PD(N), and the drain is connected to the low level VSS.
  • the gate driving signal output module 13 includes:
  • a first gate drive signal output transistor M131 a gate connected to the pull-up node PU(N), a source connected to the positive phase clock signal input terminal CLK, and a drain connected to the gate drive signal output terminal OUTPUT(N);
  • a second gate driving signal outputting transistor M132 a gate connected to the pull-down node PD(N), a source connected to the gate driving signal output terminal OUTPUT(N), and a drain connected to a low level VSS;
  • the third gate driving signal output transistor M133 has a gate connected to the reset terminal RESET, a source connected to the gate driving signal output terminal OUTPUT (N), and a drain connected to the low level VSS.
  • the noise reduction module 14 includes:
  • all of the transistors are n-type transistors, but in actual operation, the transistors may also employ p-type transistors, and the types of transistors are not limited.
  • the input phase is indicated as S1
  • the output phase is indicated as S2
  • the reset phase is indicated as S3
  • the output cut-off phase is indicated as S4.
  • the signal accessed by the PD (N) and the signal accessed by the PD (N+1) are inverted.
  • the input signal input by the INPUT is high level
  • the CLKB input is high level
  • the CLK input is low.
  • Level, RESET input low level M111 is turned on, PU(N) potential is pulled high, M131 is turned on, but since CLK input is low level at this time, OUTPUT(N) outputs low level; and because of this
  • the potential of PU(N) is high, both M122 and M123 are turned on, and the potential of PD(N) and the potential of PD_CN are pulled low.
  • INPUT input low level, CLKB input high level, CLK input low level, RESET input high level, M112 and M133 are turned on to output PU(N) potential and OUTPUT(N)
  • the gate drive signal is pulled low; at this time, M121 is turned on, and the potential of PD_CN is high, to open M123, thereby pulling up the potential of PD(N), and the potential of PD(N+1) is low.
  • both INPUT and RESET input low level, CLKB and CLK alternately output high level and low level
  • the signal of PD(N) access signal is the same as CLKB, that is, when CLKB is input high level, The potential of PD(N) is high.
  • CLKB is input low
  • the potential of PD(N) is low.
  • the signal of PD(N+1) is connected with PD(N). The incoming signal is inverted.
  • a second embodiment of the shift register unit of the present disclosure includes a pull-up node control module 11, a pull-down node control module 12, a gate drive signal output terminal OUTPUT (N), and a gate drive signal.
  • the pull-up node control module 11 includes:
  • the first pull-up node controls the transistor M111, the gate and the source are both connected to the input terminal INPUT, and the drain is connected to the pull-up node PU(N);
  • the second pull-up node controls the transistor M112, the gate is connected to the reset terminal RESET, the source is connected to the pull-up node PU(N), and the drain is connected to the low level VSS;
  • the third pull-up node controls the transistor M113, the gate is connected to the pull-down node PD(N), the source is connected to the pull-up node PU(N), and the drain is connected to the low level VSS;
  • the storage capacitor C1 has a first end connected to the pull-up node PU(N) and a second end connected to the gate drive signal output terminal OUTPUT(N).
  • M111, M112, and M113 are drawn in a dotted line frame labeled 11, although the storage capacitor C1 is not drawn in the dotted line frame labeled 11 due to inconvenience in drawing, the storage capacitor C1 is also included in Pull up the node control module 11.
  • the pull-down node control module 12 includes:
  • the first pull-down control node controls the transistor M121, the gate and the source are both connected to the inverted clock signal input terminal CLKB, and the drain is connected to the pull-down control node PD_CN;
  • the second pull-down control node controls the transistor M122, the gate is connected to the pull-up node PU(N), the source is connected to the pull-down control node PD_CN, and the drain is connected to the low level VSS;
  • the first pull-down node controls the transistor M123, the gate is connected to the pull-down control node PD_CN, the source is connected to the inverted clock signal input terminal CLKB, and the drain is connected to the pull-down node PD(N);
  • the second pull-down node controls the transistor M124, the gate is connected to the pull-up node PU(N), the source is connected to the pull-down node PD(N), and the drain is connected to the low level VSS.
  • the gate driving signal output module 13 includes:
  • a first gate drive signal output transistor M131 a gate connected to the pull-up node PU(N), a source connected to the positive phase clock signal input terminal CLK, and a drain connected to the gate drive signal output terminal OUTPUT(N);
  • a second gate driving signal outputting transistor M132 a gate connected to the pull-down node PD(N), a source connected to the gate driving signal output terminal OUTPUT(N), and a drain connected to a low level VSS;
  • the third gate driving signal output transistor M133 the gate is connected to the reset terminal RESET, and the source Connected to the gate drive signal output terminal OUTPUT (N), the drain is connected to the low level VSS.
  • the noise reduction module 14 includes:
  • the first noise reduction transistor M141 has a gate connected to the pull-down node PD(N+2) of the N+2 stage shift register unit, a source connected to the gate drive signal output terminal OUTPUT(N), and a low drain connection.
  • Level VSS and,
  • the second noise reduction transistor M142 has a gate connected to the pull-down node PD(N+1) of the N+1th stage shift register unit, a source connected to the gate drive signal output terminal OUTPUT(N), and a low drain connection.
  • Level VSS The second noise reduction transistor M142 has a gate connected to the pull-down node PD(N+1) of the N+1th stage shift register unit, a source connected to the gate drive signal output terminal OUTPUT(N), and a low drain connection.
  • Level VSS Level VSS.
  • all of the transistors are n-type transistors, but in actual operation, the transistors may also employ p-type transistors, and the types of transistors are not limited.
  • the positive phase clock signal input terminal CLK inputs the first clock signal CLK1, and the inverted clock signal input terminal CLKB is connected to the second embodiment.
  • the PD (N) access signal and the PD (N+2) access signal are inverted.
  • the second clock signal CLK2 is inverted from the fourth clock signal CLK4.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other device having the same characteristics.
  • one of the poles is referred to as a source and the other pole is referred to as a drain.
  • the transistor can be classified into an n-type transistor or a p-type transistor according to the characteristics of the transistor.
  • all of the transistors are described by taking an n-type transistor as an example. It is conceivable that those skilled in the art can perform without creative work when implemented by using a p-type transistor. It is easily conceivable and therefore also within the scope of the embodiments of the present disclosure.
  • the present disclosure also provides a driving method of a shift register unit, which is applied to the above shift register unit, and the driving method includes:
  • the potential of the pull-down node is controlled to be the same as the potential of the inverted clock signal
  • control noise reduction control signal and the inverted clock signal are mutually inverted
  • the noise reduction module controls the gate drive signal output terminal to be connected to a low level.
  • the driving method of the shift register unit according to the embodiment of the present disclosure controls the denoising of the gate driving signal by using the noise reduction module controlled by the noise reduction control signal and the gate driving signal output module in the related art to improve noise reduction. Effect.
  • the present disclosure also provides a gate driving circuit including a plurality of stages of the above shift register unit.
  • the noise reduction control signal output end of the Nth stage shift register unit is connected to the pulldown node of the N+nth stage shift register unit.
  • n and N are positive integers.
  • the noise reduction control signal output end of the Nth stage shift register unit is further connected to the pulldown node of the N+mth stage shift register unit, and m is a positive integer smaller than n.
  • the noise reduction control signal output end of the Nth stage shift register unit is connected to the pull-down node of the N+1th stage shift register unit.
  • Providing a positive phase clock signal for the Nth stage shift register unit by the first clock signal input terminal, an inverted clock signal for the Nth stage shift register unit by the second clock signal input terminal, and a second clock signal input end by the second clock signal input end A positive phase clock signal is provided for the N+1th stage shift register unit, and an inverted clock signal is provided by the first clock signal input terminal for the (N+1)th shift register unit.
  • the noise reduction control signal output end of the Nth stage shift register unit is connected to the pulldown node of the N+2 stage shift register unit.
  • Providing a positive phase clock signal for the Nth stage shift register unit by the first clock signal input terminal, and providing an inverted clock signal for the Nth stage shift register unit by the third clock signal input end; and the third clock signal input end by the third clock signal input end Providing a positive phase clock signal for the N+2 stage shift register unit, and providing an inverted clock signal for the N+2th stage shift register unit by the first clock signal input terminal; the first clock signal and the third clock signal are inverted .
  • the second clock signal is delayed by 0.25 clock cycles from the first clock signal
  • the fourth clock signal is delayed by 0.25 clock cycles than the third clock signal, the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal
  • the duty cycle is 0.5.
  • the noise reduction control signal output end of the Nth stage shift register unit is further connected to the pulldown node of the N+1th stage shift register unit; and the second clock signal input end is the N+1th stage shift
  • the register unit provides a positive phase clock signal, and the fourth clock signal input terminal provides an inverted clock signal for the (N+1)th shift register unit.
  • the gate drive circuit of the present disclosure will be described below by two specific embodiments.
  • a first embodiment of the gate drive circuit of the present disclosure includes a multi-stage shift register unit.
  • G1 indicates the first stage shift register unit
  • G2 indicates the second stage shift register unit
  • GN indicates the Nth stage shift register unit
  • GN+1 indicates the N+1th shift register unit
  • the gate driving circuit is connected to the first clock signal CLK1 and the second clock signal CLK2 which are mutually inverted; the positive phase clock signal input end of G1 is connected to CLK1, and the inverted clock signal input end of G1 is connected to CLK2;
  • the positive phase clock signal input terminal is connected to CLK2, the inverted clock signal input end of G2 is connected to CLK1; the GN positive phase clock signal input end is connected to CLK1, and the GN inverted clock signal input end is connected to CLK2; GN+1
  • the input of the positive phase clock signal is connected to CLK2, and the input of the inverted clock signal of GN+1 is connected to CLK1; the input of G1 is connected to the start signal STV.
  • the noise reduction control signal output of each stage shift register is connected to a pull-down node of an adjacent lower stage shift register unit.
  • the noise reduction control signal output end of G1 is connected to the pull-down node PD(2) of G2; the noise reduction control signal output end of G2 is connected to the pull-down node PD(3) of G3 (G3 is not shown in FIG. 8);
  • the GN noise reduction control signal output terminal is connected to the GN+1 pull-down node PD(N+1); the GN+1 noise reduction control signal output terminal and GN+2 (GN+2 is not shown in FIG. 8)
  • the pull-down node PD (N+2) is connected.
  • each stage shift register unit is connected to the gate drive signal output end of the adjacent next stage shift register unit;
  • the input of each stage shift register unit is connected to the gate drive signal output of the adjacent upper stage shift register unit.
  • OUTPUT(1) indicates the gate drive signal output of the first stage shift register unit
  • OUTPUT(2) indicates the gate drive signal output of the second stage shift register unit
  • OUTPUT(N) indicates The gate drive signal output end of the Nth stage shift register unit
  • OUTPUT(N+1) indicates the gate drive signal output end of the N+1th shift register unit
  • INPUT2 At the input of G2, INPUT3 indicates the input of G3 (G3 is not shown in Figure 8)
  • INPUTN indicates the input of GN
  • INPUTN+1 indicates the input of GN+1
  • INPUTN+2 indicates the input of GN+2.
  • RESET1 indicates the reset end of G1
  • RESET2 indicates the reset end of G2
  • RESETN indicates the reset end of GN
  • RESETN+1 indicates the reset end of GN+1.
  • the shift register unit included in the first embodiment of the gate driving circuit of the present disclosure may adopt the first specific embodiment of the shift register unit of the present disclosure, but other forms of shifting may also be employed.
  • Bit register unit not limited to this.
  • the first embodiment of the gate driving circuit of the present disclosure includes each stage of the shift register unit not only discharging the gate driving signal under the control of the pull-down node of the shift register unit of the current stage, but also at the same time
  • the gate driving signal is discharged under the control of the pull-down node of the next-stage shift register unit, and the signal of the pull-down node of each shift register unit of each stage is shifted in the output cut-off holding phase and the adjacent next stage shift
  • the signal accessed by the pull-down node of the register unit is inverted, so that the pull-down time of the gate drive signal is increased from 50% to 100% during the output cut-off hold phase, thereby optimizing the noise reduction effect of the gate drive signal.
  • a second embodiment of the gate drive circuit of the present disclosure includes a multi-stage shift register unit.
  • GN indicates the Nth stage shift register unit
  • GN+1 indicates the N+1th shift register unit
  • GN+2 indicates the N+2 shift register unit
  • GN+3 indicates the N+ 3-stage shift register unit
  • N is a positive integer
  • INPUT indicates the input
  • RESET indicates the reset.
  • the gate driving circuit is connected to the first clock signal CLK1 and the second clock signal CLK3 which are mutually inverted, and the gate driving circuit further inputs the second clock signal CLK2 and the fourth clock signal CLK4 which are mutually inverted.
  • the second clock signal CLK2 is delayed by 0.25 clock cycles T than the first clock signal CLK1
  • the fourth clock signal CLK4 is delayed by 0.25 clock cycles T than the third clock signal CLK3, and the duty of the first clock signal CLK1 is
  • the ratio, the duty ratio of the second clock signal CLK2, the duty ratio of the third clock signal CLK3, and the duty ratio of the fourth clock signal CLK4 are both 0.5.
  • the GN positive phase clock signal input terminal is connected to CLK1, the GN inverted clock signal input terminal is connected to CLK3; the GN+1 positive phase clock signal input terminal is connected to CLK2, and the GN+1 inverted clock signal input terminal is connected.
  • the noise reduction control signal output terminals of each stage of the shift register are respectively connected to the pull-down node of the adjacent next-stage shift register unit and the pull-down node of the adjacent lower-stage shift register unit.
  • the first noise reduction control signal output end of the GN is connected to the GN+1 pulldown node PD(N+1), and the GN second noise reduction control signal output end and the GN+2 pulldown node PD(N+2).
  • the first noise reduction control signal output end of GN+1 is connected with the GN+2 pull-down node PD(N+2), the second noise reduction control signal output end of GN+1 and the GN+3 pull-down node PD ( N+3) connection;
  • the first noise reduction control signal output end of GN+2 is connected with the GN+3 pull-down node PD(N+3), and the second noise reduction control signal output end of GN+2 is GN+4 ( The GN+4 is connected to the pull-down node PD(N+4) not shown in FIG.
  • OUTPUT(N) indicates the gate drive signal output terminal of the Nth stage shift register unit
  • OUTPUT(N+1) indicates the gate drive signal output terminal of the N+1th shift register unit
  • OUTPUT. (N+2) indicates the gate drive signal output terminal of the N+2 stage shift register unit
  • OUTPUT (N+3) indicates the gate drive signal output terminal of the N+3th stage shift register unit.
  • the second embodiment of the gate driving circuit of the present disclosure includes a shift register unit that can employ the second embodiment of the shift register unit of the present disclosure, but other forms of shifting can also be employed.
  • Bit register unit not limited to this.
  • the second embodiment of the gate driving circuit of the present disclosure includes each stage of the shift register unit not only discharging the gate driving signal under the control of the pull-down node of the shift register unit of the current stage, but also at the same time
  • the gate driving signal is discharged under the control of the pull-down node of the next-stage shift register unit and the pull-down node of the adjacent lower-stage shift register unit, and the pull-down register unit is pulled down in each stage of the output-off-hold phase.
  • the signal accessed by the node and the signal accessed by the pull-down node of the adjacent lower two-stage shift register unit are inverted, so that the time for pulling down the gate drive signal during the output cut-off hold phase is increased from 50% to 100%, thereby optimizing
  • the noise reduction effect of the gate driving signal further, the second embodiment of the gate driving circuit of the present disclosure drives the gate of the current level under the control of the pull-down node of the adjacent next-stage shift register unit The signal is discharged to further enhance the noise reduction effect on the gate drive signal.
  • the present disclosure also provides a display device including the above-described gate drive circuit.

Abstract

一种移位寄存器单元及其驱动方法、栅极驱动电路和显示装置。所述移位寄存器单元，包括上拉节点控制模块（21）、下拉节点控制模块（22）、栅极驱动信号输出端（OUTPUT(N)）和栅极驱动信号输出模块（23），所述栅极驱动信号输出模块（23）分别与上拉节点（PU(N)）、下拉节点（PD(N)）、正相时钟信号输入端（CLK）和所述栅极驱动信号输出端（OUTPUT(N)）连接；所述下拉节点控制模块（22），分别与所述下拉节点（PD(N)）和反相时钟信号输入端（CLKB）连接；所述移位寄存器单元还包括：降噪模块（24），分别与降噪控制信号输出端（Ctrl）和栅极驱动信号输出端（OUTPUT(N)）连接。

Description

移位寄存器单元及其驱动方法、栅极驱动电路和显示装置
相关申请的交叉引用
本申请主张在2016年2月1日在中国提交的中国专利申请号No.201610068705.6的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示驱动技术领域，尤其涉及一种移位寄存器单元及其驱动方法、栅极驱动电路和显示装置。
背景技术
相关技术中的移位寄存器单元由下拉节点在输出截止保持阶段控制下拉栅极驱动信号。然而，在输出截止保持阶段对栅极驱动信号进行下拉的时间为50％，而在另外的不对栅极驱动信号进行下拉的时间里可能由于上拉晶体管的漏电而导致栅极驱动信号不能保持为低电平，因此，不能对栅极驱动信号很好的降噪。
发明内容
本公开的主要目的在于提供一种移位寄存器单元及其驱动方法、栅极驱动电路和显示装置，解决相关技术中在输出截止保持阶段对栅极驱动信号进行下拉的时间为50％，而在另外的不对栅极驱动信号进行下拉的时间里可能由于上拉晶体管的漏电而导致栅极驱动信号不能保持为低电平，从而通过现有的栅极驱动信号输出模块不能对栅极驱动信号很好的降噪的问题。
为了达到上述目的，本公开提供了一种移位寄存器单元，包括上拉节点控制模块、下拉节点控制模块、栅极驱动信号输出端和栅极驱动信号输出模块，所述栅极驱动信号输出模块分别与上拉节点、下拉节点、正相时钟信号输入端和所述栅极驱动信号输出端连接；所述下拉节点控制模块，分别与所述下拉节点和反相时钟信号输入端连接；所述移位寄存器单元还包括：降噪模块，分别与降噪控制信号输出端和栅极驱动信号输出端连接。
实施时，所述下拉节点控制模块，用于在输出截止保持阶段，控制所述下拉节点的电位与所述反相时钟信号的电位相同；在输出截止保持阶段，降噪控制信号和所述反相时钟信号相互反相；所述降噪模块，用于当所述降噪控制信号有效时控制所述栅极驱动信号出端接入低电平；所述正相时钟信号和所述反相时钟信号相互反相。
实施时，当包括多级所述移位寄存器单元的栅极驱动电路与2n个时钟信号输入端连接时，所述降噪控制信号输出端与第N+n级移位寄存器单元的下拉节点连接，n为正整数，N为本级移位寄存器单元在栅极驱动电路中的级数。
实施时，当n大于1时，所述降噪控制信号输出端还与第N+m级移位寄存器单元的下拉节点连接，m为小于n的正整数。
实施时，当所述栅极驱动电路与两个时钟信号输出端连接时，所述降噪控制信号输出端与相邻下一级移位寄存器单元的下拉节点连接；所述降噪模块包括：降噪晶体管，栅极与所述相邻下一级移位寄存器单元的下拉节点连接，第一极与所述栅极驱动信号输出端连接，第二极接入低电平；由第一时钟信号输入端为本级移位寄存器单元提供正相时钟信号，由第二时钟信号输入端为本级移位寄存器单元提供反相时钟信号；由第二时钟信号输入端为相邻下一级移位寄存器单元提供正相时钟信号，由第一时钟信号输入端为相邻下一级移位寄存器单元提供反相时钟信号。
实施时，当所述栅极驱动电路与四个时钟信号输出端连接时，所述降噪控制信号输出端与第N+2级移位寄存器单元的下拉节点连接；所述降噪模块包括：第一降噪晶体管，栅极与所述第N+2级移位寄存器单元的下拉节点连接，第一极与所述栅极驱动信号输出端连接，第二极接入低电平；由第一时钟信号输入端为本级移位寄存器单元提供正相时钟信号，由第三时钟信号输入端为本级移位寄存器单元提供反相时钟信号；由第三时钟信号输入端为第N+2级移位寄存器单元提供正相时钟信号，由第一时钟信号输入端为第N+2级移位寄存器单元提供反相时钟信号；第一时钟信号和第三时钟信号反相；第二时钟信号比第一时钟信号推迟0.25个时钟周期，第四时钟信号比第三时钟信号推迟0.25个时钟周期，第一时钟信号、第二时钟信号、第三时钟信号 和第四时钟信号的占空比都为0.5。
实施时，m等于1；所述降噪模块包括：第二降噪晶体管，栅极与所述第N+1级移位寄存器单元的下拉节点连接，第一极与所述栅极驱动信号输出端连接，第二极接入低电平；由第二时钟信号输入端为第N+1级移位寄存器单元提供正相时钟信号，由第四时钟信号输入端为第N+1级移位寄存器单元提供反相时钟信号。
本公开还提供了一种移位寄存器单元的驱动方法，应用于上述的移位寄存器单元，所述驱动方法包括：在输出截止保持阶段，控制下拉节点的电位与反相时钟信号的电位相同；在输出截止保持阶段，控制降噪控制信号和所述反相时钟信号相互反相；当所述降噪控制信号有效时，降噪模块控制栅极驱动信号出端接入低电平。
本公开还提供了一种栅极驱动电路，包括多级上述的移位寄存器单元。
实施时，当所述栅极驱动电路与2n个时钟信号输入端连接时，所述第N级移位寄存器单元的降噪控制信号输出端与第N+n级移位寄存器单元的下拉节点连接，n和N都为正整数。
实施时，当n大于1时，所述第N级移位寄存器单元的降噪控制信号输出端还与第N+m级移位寄存器单元的下拉节点连接，m为小于n的正整数。
实施时，当所述栅极驱动电路与两个时钟信号输出端连接时，所述第N级移位寄存器单元的降噪控制信号输出端与第N+1级移位寄存器单元的下拉节点连接；由第一时钟信号输入端为第N级移位寄存器单元提供正相时钟信号，由第二时钟信号输入端为第N级移位寄存器单元提供反相时钟信号；由第二时钟信号输入端为第N+1级移位寄存器单元提供正相时钟信号，由第一时钟信号输入端为第N+1级移位寄存器单元提供反相时钟信号。
实施时，当所述栅极驱动电路与四个时钟信号输出端连接时，所述第N级移位寄存器单元的降噪控制信号输出端与第N+2级移位寄存器单元的下拉节点连接；由第一时钟信号输入端为第N级移位寄存器单元提供正相时钟信号，由第三时钟信号输入端为第N级移位寄存器单元提供反相时钟信号；由第三时钟信号输入端为第N+2级移位寄存器单元提供正相时钟信号，由第一时钟信号输入端为第N+2级移位寄存器单元提供反相时钟信号；第一时钟信 号和第三时钟信号反相；第二时钟信号比第一时钟信号推迟0.25个时钟周期，第四时钟信号比第三时钟信号推迟0.25个时钟周期，第一时钟信号的占空比、第二时钟信号的占空比、第三时钟信号的占空比和第四时钟信号的占空比都为0.5。
实施时，m等于1；由第二时钟信号输入端为第N+1级移位寄存器单元提供正相时钟信号，由第四时钟信号输入端为第N+1级移位寄存器单元提供反相时钟信号。
本公开还提供了一种显示装置，包括上述的栅极驱动电路。
与相关技术相比，本公开所述的移位寄存器单元及其驱动方法、栅极驱动电路和显示装置采用由降噪控制信号控制的降噪模块与相关技术中的栅极驱动信号输出模块一起控制对栅极驱动信号去噪，在输出截止保持阶段内正相时钟信号为高电平的时间段也对栅极驱动信号进行下拉，从而提高降噪的效果。
附图说明
图1A是相关技术中的移位寄存器单元的电路图；
图1B是图1A所示的移位寄存器单元的工作时序图；
图2是本公开至少一些实施例的移位寄存器单元的结构图；
图3A是图2所示的移位寄存器单元接入两个时钟信号时的工作时序图；
图3B是图2所示的移位寄存器单元接入四个时钟信号时的工作时序图；
图4是本公开至少一些实施例的移位寄存器单元的电路图；
图5是图4所示的移位寄存器单元的工作时序图；
图6是本公开至少一些实施例的移位寄存器单元的电路图；
图7是图6所示的移位寄存器单元的工作时序图；
图8是本公开至少一些实施例的栅极驱动电路的结构图；
图9是本公开至少一些实施例的栅极驱动电路的结构图；
图10是图9所示的栅极驱动电路接入四个时钟信号时的时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
图1A是相关技术中的移位寄存器单元的电路图，图1B是图1A所示的移位寄存器单元的工作时序图，在图1B中，S1表示输入阶段，S2表示输出阶段，S3表示复位阶段，S4表示输出截止保持阶段。在图1A中，INPUT表示输入端，CLK表示正相时钟信号输入端，RESET表示复位端，VSS表示低电平，M1为输入晶体管，M2为第一复位晶体管，M3为上拉晶体管，M4为第二复位晶体管，M5为第一下拉节点控制晶体管，M6为第二下拉节点控制晶体管，M8为第一下拉控制节点控制晶体管，M9为第二下拉控制节点控制晶体管，M10为上拉节点控制晶体管，C1为存储电容，PD_CN表示下拉控制节点，PU标示上拉节点。
如图1A所示，相关技术中的移位寄存器单元仅通过下拉节点PD对栅极驱动信号输出端OUTPUT去噪，但是下拉节点PD在输出截止保持阶段的波形与反相时钟信号输入端CLKB输入的反相时钟信号的波形相同，即用于对栅极驱动信号进行下拉的下拉晶体管M11的栅极电位为高电平的时间只有50％。由于图1A中的上拉晶体管M3的尺寸比较大，从而M3的寄生电容会比较大；如图1B所示，在输出截止保持阶段S4，由于CLK与上拉节点PU之间的寄生电容比较大，因此在正相时钟信号输入端CLK输入高电平时，尤其是在高温等特殊环境下M3的漏电流也会比较大，从而导致M3并非完全关断，使得此时OUTPUT输出的栅极驱动信号不为低电平，因此不能对栅极驱动信号很好的降噪。
为克服上述问题，本公开实施例提供一种移位寄存器单元。
如图2所示，本公开实施例所述的移位寄存器单元，包括上拉节点控制模块21、下拉节点控制模块22、栅极驱动信号输出端OUTPUT(N)和栅极驱动信号输出模块23。其中，N为正整数，N为本公开实施例所述的移位寄存器单元在整个栅极驱动电路中处于的级数。
其中，所述栅极驱动信号输出模块23分别与上拉节点PU(N)、下拉节 点PD(N)、正相时钟信号输入端CLK和所述栅极驱动信号输出端OUTPUT(N)连接。
所述下拉节点控制模块22，分别与所述下拉节点PD(N)和反相时钟信号输入端CLKB连接。
所述移位寄存器单元还包括：降噪模块24，分别与降噪控制信号输出端Ctrl和栅极驱动信号输出端OUTPUT(N)连接。
本公开实施例所述的移位寄存器单元采用由降噪控制信号控制的降噪模块与相关技术中的栅极驱动信号输出模块一起控制对栅极驱动信号去噪，在输出截止保持阶段内正相时钟信号为高电平的时间段也对栅极驱动信号进行下拉，从而提高降噪的效果。
在如图2所示的移位寄存器单元的实施中，所述上拉节点控制模块21与上拉节点PU(N)连接，用于控制上拉节点PU(N)的电位。
可选的，本公开如图2所示的移位寄存器单元的实施例在工作时，所述下拉节点控制模块22，用于在输出截止保持阶段，控制所述下拉节点的电位与所述反相时钟信号的电位相同。
在输出截止保持阶段，由反相时钟信号输入端CLKB输入的反相时钟信号和由降噪控制信号输出端Ctrl输出的降噪控制信号相互反相。
所述降噪模块24，用于当所述降噪控制信号有效时控制所述栅极驱动信号出端OUTPUT(N)接入低电平。
所述正相时钟信号和所述反相时钟信号相互反相。
在实际操作时，栅极驱动信号输出模块包括的用于对栅极驱动信号输出端进行去噪的下拉晶体管的栅极与下拉节点连接，当下拉节点的电位有效时所述下拉晶体管导通，在一般情况下，在输出截止保持阶段所述下拉节点接入的信号的波形与反相时钟信号的波形相同，即在输出截止保持阶段对栅极驱动信号进行下拉的时间为50％，因此仅通过相关技术中的栅极驱动信号输出模块不能对栅极驱动信号很好的降噪，本公开实施例所述的移位寄存器单元通过将降噪控制信号设置为与反相时钟信号相互反相，并同时通过由降噪控制信号控制的降噪模块对栅极驱动信号进行放电，使得对栅极驱动信号进行下拉的时间由50％增加到100％，从而加强对栅极驱动信号的降噪效果。
根据一种可选的实施方式，当包括多级所述移位寄存器单元的栅极驱动电路与2n个时钟信号输入端连接时，所述降噪控制信号输出端与第N+n级移位寄存器单元的下拉节点连接，n为正整数，N为本级移位寄存器单元在栅极驱动电路中的级数。
在该可选的实施方式中，如图3A所示，当所述栅极驱动电路接入相互反相的第一时钟信号CLK1和第二时钟信号CLK2时，所述降噪控制信号输出端与第N+1级移位寄存器单元的下拉节点PD(N+1)连接，即当第N级移位寄存器单元的正相时钟信号输入端接入第一时钟信号CLK1，第N级移位寄存器单元的反相时钟信号输入端接入第二时钟信号CLK2时，第N+1级移位寄存器单元的正相时钟信号输入端接入第二时钟信号CLK2，第N+1级移位寄存器单元的反相时钟信号输入端接入第一时钟信号CLK1，在输出截止保持阶段，PD(N+1)接入的信号与CLK1相同，PD(N)接入的信号与CLK2相同，PD(N+1)接入的信号与PD(N)接入的信号反相。
如图3B所示，当所述栅极驱动电路接入第一时钟信号CLK1、第二时钟信号CLK2、第三时钟信号CLK3和第四时钟信号CLK4时，所述降噪控制信号输出端与第N+2级移位寄存器单元的下拉节点PD(N+2)连接，CLK1与CLK3反相，CLK2与CLK4反相，当第N级移位寄存器单元的正相时钟信号输入端接入CLK1，第N级移位寄存器单元的反相时钟信号输入端接入CLK3时，第N+1级移位寄存器单元的正相时钟信号输入端接入CLK2，第N+1级移位寄存器单元的反相时钟信号输入端接入CLK4，第N+2级移位寄存器单元的正相时钟信号输入端接入CLK3，第N+2级移位寄存器单元的反相时钟信号输入端接入CLK1，第N+3级移位寄存器单元的正相时钟信号输入端接入CLK4，第N+3级移位寄存器单元的反相时钟信号输入端接入CLK2；在输出截止保持阶段，PD(N+2)接入的信号与CLK1相同，PD(N)接入的信号与CLK3相同，PD(N+2)接入的信号与PD(N)接入的信号反相。更进一步的，当所述栅极驱动电路接入第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号、第五时钟信号和第六时钟信号时，所述降噪控制信号输出端与第N+3级移位寄存器单元的下拉节点连接，第一时钟信号与第四时钟信号反相，第二时钟信号与第五时钟信号反相，第三时钟信号与第六 时钟信号反相，当第N级移位寄存器单元的正相时钟信号输入端接入第一时钟信号，第N级移位寄存器单元的反相时钟信号输入端接入第四时钟信号时，第N+1级移位寄存器单元的正相时钟信号输入端接入第二时钟信号，第N+1级移位寄存器单元的反相时钟信号输入端接入第五时钟信号，第N+2级移位寄存器单元的正相时钟信号输入端接入第三时钟信号，第N+2级移位寄存器单元的反相时钟信号输入端接入第六时钟信号，第N+3级移位寄存器单元的正相时钟信号输入端接入第四时钟信号，第N+3级移位寄存器单元的反相时钟信号输入端接入第一时钟信号，第N+4级移位寄存器单元的正相时钟信号输入端接入第五时钟信号，第N+4级移位寄存器单元的反相时钟信号输入端接入第二时钟信号，第N+5级移位寄存器单元的正相时钟信号输入端接入第六时钟信号，第N+5级移位寄存器单元的反相时钟信号输入端接入第三时钟信号；第N+3级移位寄存器单元的下拉节点接入的信号与第一时钟信号相同，第N级移位寄存器单元的下拉节点接入的信号与第四时钟信号相同，第N+3级移位寄存器单元的下拉节点接入的信号与第N级移位寄存器单元的下拉节点接入的信号反相。当n等于4、5等更大的正整数时，依次类推。
可选的，当n大于1时，所述降噪控制信号输出端还与第N+m级移位寄存器单元的下拉节点连接，m为小于n的正整数。在可选情况下，降噪控制信号输出端还可以与其他级移位寄存器单元的下拉节点连接，以进一步优化降噪效果。
根据一种具体实施方式，当所述栅极驱动电路与两个时钟信号输出端连接时，所述降噪控制信号输出端与相邻下一级移位寄存器单元的下拉节点连接。
所述降噪模块包括：降噪晶体管，栅极与所述相邻下一级移位寄存器单元的下拉节点连接，第一极与所述栅极驱动信号输出端连接，第二极接入低电平。
由第一时钟信号输入端为本级移位寄存器单元提供正相时钟信号，由第二时钟信号输入端为本级移位寄存器单元提供反相时钟信号。
由第二时钟信号输入端为相邻下一级移位寄存器单元提供正相时钟信号，由第一时钟信号输入端为相邻下一级移位寄存器单元提供反相时钟信号。在 之后的移位寄存器的第一具体实施例里将具体说明该具体实施方式。
根据另一种具体实施方式，当所述栅极驱动电路与四个时钟信号输出端连接时，所述降噪控制信号输出端与第N+2级移位寄存器单元的下拉节点连接。
所述降噪模块包括：第一降噪晶体管，栅极与所述第N+2级移位寄存器单元的下拉节点连接，第一极与所述栅极驱动信号输出端连接，第二极接入低电平。
由第一时钟信号输入端为本级移位寄存器单元提供正相时钟信号，由第三时钟信号输入端为本级移位寄存器单元提供反相时钟信号。
由第三时钟信号输入端为第N+2级移位寄存器单元提供正相时钟信号，由第一时钟信号输入端为第N+2级移位寄存器单元提供反相时钟信号。
第一时钟信号和第三时钟信号反相。
第二时钟信号比第一时钟信号推迟0.25个时钟周期，第四时钟信号比第三时钟信号推迟0.25个时钟周期，第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号的占空比都为0.5。在之后的移位寄存器的第二具体实施例里将具体说明该具体实施方式。
可选的，所述降噪控制信号输出端还与第N+1级移位寄存器单元的下拉节点连接。
所述降噪模块包括：第二降噪晶体管，栅极与所述第N+1级移位寄存器单元的下拉节点连接，第一极与所述栅极驱动信号输出端连接，第二极接入低电平，以进一步优化降噪效果。
由第二时钟信号输入端为第N+1级移位寄存器单元提供正相时钟信号，由第四时钟信号输入端为第N+1级移位寄存器单元提供反相时钟信号。
如图4所示，本公开所述的移位寄存器单元的第一具体实施例包括上拉节点控制模块11、下拉节点控制模块12、栅极驱动信号输出端OUTPUT(N)、栅极驱动信号输出模块13和降噪模块14。
所述上拉节点控制模块11包括：
第一上拉节点控制晶体管M111，栅极和源极都与输入端INPUT连接，漏极与上拉节点PU(N)连接；
第二上拉节点控制晶体管M112，栅极与复位端RESET连接，源极与所述上拉节点PU(N)连接，源极接入低电平VSS；
第三上拉节点控制晶体管M113，栅极与下拉节点PD(N)连接，源极与所述上拉节点PU(N)连接，源极接入低电平VSS；以及，
存储电容C1，第一端与所述上拉节点PU(N)连接，第二端与栅极驱动信号输出端OUTPUT(N)连接。
在图4中，M111、M112和M113被绘制于标有11的虚线框中，虽然由于绘制时的不便，存储电容C1没有被绘制于标有11的虚线框中，但是存储电容C1也包含于上拉节点控制模块11中。
所述下拉节点控制模块12包括：
第一下拉控制节点控制晶体管M121，栅极和源极都与反相时钟信号输入端CLKB连接，漏极与下拉控制节点PD_CN连接；
第二下拉控制节点控制晶体管M122，栅极与所述上拉节点PU(N)连接，源极与所述下拉控制节点PD_CN连接，漏极接入低电平VSS；
第一下拉节点控制晶体管M123，栅极与下拉控制节点PD_CN连接，源极与反相时钟信号输入端CLKB连接，漏极与下拉节点PD(N)连接；以及，
第二下拉节点控制晶体管M124，栅极与所述上拉节点PU(N)连接，源极与下拉节点PD(N)连接，漏极接入低电平VSS。
所述栅极驱动信号输出模块13包括：
第一栅极驱动信号输出晶体管M131，栅极与上拉节点PU(N)连接，源极与正相时钟信号输入端CLK连接，漏极与栅极驱动信号输出端OUTPUT(N)连接；
第二栅极驱动信号输出晶体管M132，栅极与下拉节点PD(N)连接，源极与栅极驱动信号输出端OUTPUT(N)连接，漏极接入低电平VSS；以及，
第三栅极驱动信号输出晶体管M133，栅极与复位端RESET连接，源极与栅极驱动信号输出端OUTPUT(N)连接，漏极接入低电平VSS。
所述降噪模块14包括：
第一降噪晶体管M141，栅极与第N+1级移位寄存器单元的下拉节点PD (N+1)连接，源极与栅极驱动信号输出端OUTPUT(N)连接，漏极接入低电平VSS。
在图4所示的移位寄存器单元的第一具体实施例中，所有的晶体管都为n型晶体管，但是在实际操作时，上述晶体管也可以采用p型晶体管，晶体管的类型并不作限定。
如图5所示，标示为S1的为输入阶段，标示为S2的为输出阶段，标示为S3的为复位阶段，标示为S4的为输出截止保持阶段，由图5可知，在输出截止保持阶段S4，PD(N)接入的信号和PD(N+1)接入的信号反相。
如图5所示，本公开所述的移位寄存器单元的第一具体实施例在工作时，在输入阶段S1，由INPUT输入的输入信号为高电平，CLKB输入高电平，CLK输入低电平，RESET输入低电平，M111导通，PU(N)的电位被拉高，M131导通，但是由于此时CLK输入低电平，因此OUTPUT(N)输出低电平；并由于此时PU(N)的电位为高电平，M122和M123都导通，将PD(N)的电位和PD_CN的电位拉低。
在输出阶段S2，INPUT输入低电平，CLKB输入低电平，CLK输入高电平，RESET输入低电平，PU(N)的电位由C1自举拉升，PD(N)的电位和PD_CN的电位持续被拉低，M131导通，OUTPUT(N)输出高电平。
在复位阶段S3，INPUT输入低电平，CLKB输入高电平，CLK输入低电平，RESET输入高电平，M112和M133导通，以将PU(N)的电位和OUTPUT(N)输出的栅极驱动信号拉低；此时M121导通，PD_CN的电位为高电平，以打开M123，从而拉高PD(N)的电位，此时PD(N+1)的电位为低电平。
在输出截止保持阶段S4，INPUT和RESET都输入低电平，CLKB和CLK交替输出高电平和低电平，PD(N)接入的信号的波形与CLKB相同，即当CLKB输入高电平时，PD(N)的电位为高电平，当CLKB输入低电平时，PD(N)的电位为低电平；在输出截止保持阶段S4，PD(N+1)接入的信号与PD(N)接入的信号反相。
如图6所示，本公开所述的移位寄存器单元的第二具体实施例包括上拉节点控制模块11、下拉节点控制模块12、栅极驱动信号输出端OUTPUT(N)、栅极驱动信号输出模块13和降噪模块14。
所述上拉节点控制模块11包括：
第一上拉节点控制晶体管M111，栅极和源极都与输入端INPUT连接，漏极与上拉节点PU(N)连接；
第二上拉节点控制晶体管M112，栅极与复位端RESET连接，源极与所述上拉节点PU(N)连接，漏极接入低电平VSS；
第三上拉节点控制晶体管M113，栅极与下拉节点PD(N)连接，源极与所述上拉节点PU(N)连接，漏极接入低电平VSS；以及，
存储电容C1，第一端与所述上拉节点PU(N)连接，第二端与栅极驱动信号输出端OUTPUT(N)连接。
在图6中，M111、M112和M113被绘制于标有11的虚线框中，虽然由于绘制时的不便，存储电容C1没有被绘制于标有11的虚线框中，但是存储电容C1也包含于上拉节点控制模块11中。
所述下拉节点控制模块12包括：
第一下拉控制节点控制晶体管M121，栅极和源极都与反相时钟信号输入端CLKB连接，漏极与下拉控制节点PD_CN连接；
第二下拉控制节点控制晶体管M122，栅极与所述上拉节点PU(N)连接，源极与所述下拉控制节点PD_CN连接，漏极接入低电平VSS；
第一下拉节点控制晶体管M123，栅极与下拉控制节点PD_CN连接，源极与反相时钟信号输入端CLKB连接，漏极与下拉节点PD(N)连接；以及，
第二下拉节点控制晶体管M124，栅极与所述上拉节点PU(N)连接，源极与下拉节点PD(N)连接，漏极接入低电平VSS。
所述栅极驱动信号输出模块13包括：
第一栅极驱动信号输出晶体管M131，栅极与上拉节点PU(N)连接，源极与正相时钟信号输入端CLK连接，漏极与栅极驱动信号输出端OUTPUT(N)连接；
第二栅极驱动信号输出晶体管M132，栅极与下拉节点PD(N)连接，源极与栅极驱动信号输出端OUTPUT(N)连接，漏极接入低电平VSS；以及，
第三栅极驱动信号输出晶体管M133，栅极与复位端RESET连接，源极 与栅极驱动信号输出端OUTPUT(N)连接，漏极接入低电平VSS。
所述降噪模块14包括：
第一降噪晶体管M141，栅极与第N+2级移位寄存器单元的下拉节点PD(N+2)连接，源极与栅极驱动信号输出端OUTPUT(N)连接，漏极接入低电平VSS；以及，
第二降噪晶体管M142，栅极与第N+1级移位寄存器单元的下拉节点PD(N+1)连接，源极与栅极驱动信号输出端OUTPUT(N)连接，漏极接入低电平VSS。
在图6所示的移位寄存器单元的第二具体实施例中，所有的晶体管都为n型晶体管，但是在实际操作时，上述晶体管也可以采用p型晶体管，晶体管的类型并不作限定。
如图7所示，如图6所示的移位寄存器单元的第二具体实施例在工作时，正相时钟信号输入端CLK输入第一时钟信号CLK1，反相时钟信号输入端CLKB接入第三时钟信号CLK3；标示为S1的为输入阶段，标示为S2的为输出阶段，标示为S3的为复位阶段，标示为S4的为输出截止保持阶段，由图7可知，在输出截止保持阶段S4，PD(N)接入的信号和PD(N+2)接入的信号反相。
PD(N+2)控制的第一降噪晶体管M141和PD(N+1)控制的第二降噪晶体管M142与M132一起对OUTPUT(N)进行降噪。
第二时钟信号CLK2与第四时钟信号CLK4反相。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。此外，按照晶体管的特性区分可以将晶体管分为n型晶体管或p型晶体管。在本公开实施例提供的驱动电路中，所有晶体管均是以n型晶体管为例进行的说明，可以想到的是在采用p型晶体管实现时是本领域技术人员可在没有做出创造性劳动前提下轻易想到的，因此也是在本公开的实施例保护范围内的。
本公开还提供了一种移位寄存器单元的驱动方法，应用于上述的移位寄存器单元，所述驱动方法包括：
在输出截止保持阶段，控制下拉节点的电位与反相时钟信号的电位相同；
在输出截止保持阶段，控制降噪控制信号和所述反相时钟信号相互反相；
当所述降噪控制信号有效时，降噪模块控制栅极驱动信号出端接入低电平。
本公开实施例所述的移位寄存器单元的驱动方法通过采用由降噪控制信号控制的降噪模块与相关技术中的栅极驱动信号输出模块一起控制对栅极驱动信号去噪，提高降噪的效果。
本公开还提供了一种栅极驱动电路，包括多级上述的移位寄存器单元。
具体的，当所述栅极驱动电路与2n个时钟信号输入端连接时，所述第N级移位寄存器单元的降噪控制信号输出端与第N+n级移位寄存器单元的下拉节点连接，n和N都为正整数。
具体的，当n大于1时，所述第N级移位寄存器单元的降噪控制信号输出端还与第N+m级移位寄存器单元的下拉节点连接，m为小于n的正整数。
具体的，当所述栅极驱动电路与两个时钟信号输出端连接时，所述第N级移位寄存器单元的降噪控制信号输出端与第N+1级移位寄存器单元的下拉节点连接；由第一时钟信号输入端为第N级移位寄存器单元提供正相时钟信号，由第二时钟信号输入端为第N级移位寄存器单元提供反相时钟信号；由第二时钟信号输入端为第N+1级移位寄存器单元提供正相时钟信号，由第一时钟信号输入端为第N+1级移位寄存器单元提供反相时钟信号。
具体的，当所述栅极驱动电路与四个时钟信号输出端连接时，所述第N级移位寄存器单元的降噪控制信号输出端与第N+2级移位寄存器单元的下拉节点连接；由第一时钟信号输入端为第N级移位寄存器单元提供正相时钟信号，由第三时钟信号输入端为第N级移位寄存器单元提供反相时钟信号；由第三时钟信号输入端为第N+2级移位寄存器单元提供正相时钟信号，由第一时钟信号输入端为第N+2级移位寄存器单元提供反相时钟信号；第一时钟信号和第三时钟信号反相。
第二时钟信号比第一时钟信号推迟0.25个时钟周期，第四时钟信号比第三时钟信号推迟0.25个时钟周期，第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号的占空比都为0.5。
具体的，所述第N级移位寄存器单元的降噪控制信号输出端还与第N+1级移位寄存器单元的下拉节点连接；由第二时钟信号输入端为第N+1级移位寄存器单元提供正相时钟信号，由第四时钟信号输入端为第N+1级移位寄存器单元提供反相时钟信号。
下面通过两个具体实施例来说明本公开所述的栅极驱动电路。
如图8所示，本公开所述的栅极驱动电路的第一具体实施例包括多级移位寄存器单元。在图8中，G1标示第一级移位寄存器单元，G2标示第二级移位寄存器单元，GN标示第N级移位寄存器单元，GN+1标示第N+1级移位寄存器单元；N为大于2的正整数。
所述栅极驱动电路接入相互反相的第一时钟信号CLK1和第二时钟信号CLK2；G1的正相时钟信号输入端接入CLK1，G1的反相时钟信号输入端接入CLK2；G2的正相时钟信号输入端接入CLK2，G2的反相时钟信号输入端接入CLK1；GN的正相时钟信号输入端接入CLK1，GN的反相时钟信号输入端接入CLK2；GN+1的正相时钟信号输入端接入CLK2，GN+1的反相时钟信号输入端接入CLK1；G1的输入端接入起始信号STV。
每一级移位寄存器的降噪控制信号输出端与相邻下一级移位寄存器单元的下拉节点连接。例如，G1的降噪控制信号输出端与G2的下拉节点PD(2)连接；G2的降噪控制信号输出端与G3(G3在图8中未示出)的下拉节点PD(3)连接；GN的降噪控制信号输出端与GN+1的下拉节点PD(N+1)连接；GN+1的降噪控制信号输出端与GN+2(GN+2在图8中未示出)的下拉节点PD(N+2)连接。
并且，除了最后一级移位移位寄存器单元之外，每一级移位寄存器单元的复位端都与相邻下一级移位寄存器单元的栅极驱动信号输出端连接；除了第一级移位寄存器单元之外，每一级移位寄存器单元的输入端都与相邻上一级移位寄存器单元的栅极驱动信号输出端连接。
在图8中，OUTPUT(1)标示第一级移位寄存器单元的栅极驱动信号输出端，OUTPUT(2)标示第二级移位寄存器单元的栅极驱动信号输出端，OUTPUT(N)标示第N级移位寄存器单元的栅极驱动信号输出端，OUTPUT(N+1)标示第N+1级移位寄存器单元的栅极驱动信号输出端；INPUT2标 示G2的输入端，INPUT3标示G3(G3在图8中未示出)的输入端，INPUTN标示GN的输入端，INPUTN+1标示GN+1的输入端，INPUTN+2标示GN+2的输入端；RESET1标示G1的复位端，RESET2标示G2的复位端，RESETN标示GN的复位端，RESETN+1标示GN+1的复位端。
具体的，本公开所述的栅极驱动电路的第一具体实施例包括的移位寄存器单元可以采用本公开所述的移位寄存器单元的第一具体实施例，但是也可以采用其他形式的移位寄存器单元，并不以此为限。
本公开所述的栅极驱动电路的第一具体实施例包括的每一级移位寄存器单元不仅在本级移位寄存器单元的下拉节点的控制下对栅极驱动信号进行放电，同时还在相邻下一级移位寄存器单元的下拉节点的控制下对栅极驱动信号进行放电，并且在输出截止保持阶段每一级移位寄存器单元的下拉节点接入的信号和相邻下一级移位寄存器单元的下拉节点接入的信号反相，使得在输出截止保持阶段对栅极驱动信号进行下拉的时间由50％增加到100％，从而优化栅极驱动信号的降噪效果。
如图9所示，本公开所述的栅极驱动电路的第二具体实施例包括多级移位寄存器单元。在图9中，GN标示第N级移位寄存器单元，GN+1标示第N+1级移位寄存器单元，GN+2标示第N+2级移位寄存器单元，GN+3标示第N+3级移位寄存器单元；N为正整数；INPUT标示输入端，RESET标示复位端。
所述栅极驱动电路接入相互反相的第一时钟信号CLK1和第二时钟信号CLK3，所述栅极驱动电路还接入相互反相的第二时钟信号CLK2和第四时钟信号CLK4。
如图10所示，第二时钟信号CLK2比第一时钟信号CLK1推迟0.25个时钟周期T，第四时钟信号CLK4比第三时钟信号CLK3推迟0.25个时钟周期T，第一时钟信号CLK1的占空比、第二时钟信号CLK2的占空比、第三时钟信号CLK3的占空比和第四时钟信号CLK4的占空比都为0.5。
GN的正相时钟信号输入端接入CLK1，GN的反相时钟信号输入端接入CLK3；GN+1的正相时钟信号输入端接入CLK2，GN+1的反相时钟信号输入端接入CLK4；GN+2的正相时钟信号输入端接入CLK3，GN的反相时钟 信号输入端接入CLK1；GN+3的正相时钟信号输入端接入CLK4，GN+1的反相时钟信号输入端接入CLK2。
每一级移位寄存器的降噪控制信号输出端分别与相邻下一级移位寄存器单元的下拉节点和相邻下两级移位寄存器单元的下拉节点连接。例如，GN的第一降噪控制信号输出端与GN+1的下拉节点PD(N+1)连接，GN的第二降噪控制信号输出端与GN+2的下拉节点PD(N+2)连接；GN+1的第一降噪控制信号输出端与GN+2的下拉节点PD(N+2)连接，GN+1的第二降噪控制信号输出端与GN+3的下拉节点PD(N+3)连接；GN+2的第一降噪控制信号输出端与GN+3的下拉节点PD(N+3)连接，GN+2的第二降噪控制信号输出端与GN+4(GN+4在图9中未示出)的下拉节点PD(N+4)连接。
在图9中，OUTPUT(N)标示第N级移位寄存器单元的栅极驱动信号输出端，OUTPUT(N+1)标示第N+1级移位寄存器单元的栅极驱动信号输出端，OUTPUT(N+2)标示第N+2级移位寄存器单元的栅极驱动信号输出端，OUTPUT(N+3)标示第N+3级移位寄存器单元的栅极驱动信号输出端。
具体的，本公开所述的栅极驱动电路的第二具体实施例包括的移位寄存器单元可以采用本公开所述的移位寄存器单元的第二具体实施例，但是也可以采用其他形式的移位寄存器单元，并不以此为限。
本公开所述的栅极驱动电路的第二具体实施例包括的每一级移位寄存器单元不仅在本级移位寄存器单元的下拉节点的控制下对栅极驱动信号进行放电，同时还在相邻下一级移位寄存器单元的下拉节点和相邻下两级移位寄存器单元的下拉节点的控制下对栅极驱动信号进行放电，并且在输出截止保持阶段每一级移位寄存器单元的下拉节点接入的信号和相邻下两级移位寄存器单元的下拉节点接入的信号反相，使得在输出截止保持阶段对栅极驱动信号进行下拉的时间由50％增加到100％，从而优化栅极驱动信号的降噪效果；更进一步的，本公开所述的栅极驱动电路的第二具体实施例还在相邻下一级移位寄存器单元的下拉节点的控制下对本级栅极驱动信号进行放电，进一步加强对栅极驱动信号的降噪效果。
本公开还提供了一种显示装置，包括上述的栅极驱动电路。
以上所述是本公开的可选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

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  1. 一种移位寄存器单元，包括上拉节点控制模块、下拉节点控制模块、栅极驱动信号输出端和栅极驱动信号输出模块，所述栅极驱动信号输出模块分别与上拉节点、下拉节点、正相时钟信号输入端和所述栅极驱动信号输出端连接；所述下拉节点控制模块分别与所述下拉节点和反相时钟信号输入端连接；
    所述移位寄存器单元还包括：降噪模块，分别与降噪控制信号输出端和所述栅极驱动信号输出端连接。
  2. 如权利要求1所述的移位寄存器单元，其中，所述下拉节点控制模块，用于在输出截止保持阶段，控制所述下拉节点的电位与所述反相时钟信号的电位相同；
    在输出截止保持阶段，降噪控制信号和所述反相时钟信号相互反相；
    所述降噪模块，用于当所述降噪控制信号有效时控制所述栅极驱动信号出端接入低电平；
    所述正相时钟信号和所述反相时钟信号相互反相。
  3. 如权利要求2所述的移位寄存器单元，其中，当包括多级所述移位寄存器单元的栅极驱动电路与2n个时钟信号输入端连接时，所述降噪控制信号输出端与第N+n级移位寄存器单元的下拉节点连接，n为正整数，N为本级移位寄存器单元在栅极驱动电路中的级数。
  4. 如权利要求3所述的移位寄存器单元，其中，当n大于1时，所述降噪控制信号输出端还与第N+m级移位寄存器单元的下拉节点连接，m为小于n的正整数。
  5. 如权利要求3所述的移位寄存器单元，其中，当所述栅极驱动电路与两个时钟信号输出端连接时，所述降噪控制信号输出端与相邻下一级移位寄存器单元的下拉节点连接；
    所述降噪模块包括：降噪晶体管，栅极与所述相邻下一级移位寄存器单元的下拉节点连接，第一极与所述栅极驱动信号输出端连接，第二极接入低电平；
    由第一时钟信号输入端为本级移位寄存器单元提供正相时钟信号，由第二时钟信号输入端为本级移位寄存器单元提供反相时钟信号；
    由第二时钟信号输入端为相邻下一级移位寄存器单元提供正相时钟信号，由第一时钟信号输入端为相邻下一级移位寄存器单元提供反相时钟信号。
  6. 如权利要求4所述的移位寄存器单元，其中，当所述栅极驱动电路与四个时钟信号输出端连接时，所述降噪控制信号输出端与第N+2级移位寄存器单元的下拉节点连接；
    所述降噪模块包括：第一降噪晶体管，栅极与所述第N+2级移位寄存器单元的下拉节点连接，第一极与所述栅极驱动信号输出端连接，第二极接入低电平；
    由第一时钟信号输入端为本级移位寄存器单元提供正相时钟信号，由第三时钟信号输入端为本级移位寄存器单元提供反相时钟信号；
    由第三时钟信号输入端为第N+2级移位寄存器单元提供正相时钟信号，由第一时钟信号输入端为第N+2级移位寄存器单元提供反相时钟信号；
    第一时钟信号和第三时钟信号反相；
    第二时钟信号比第一时钟信号推迟0.25个时钟周期，第四时钟信号比第三时钟信号推迟0.25个时钟周期，第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号的占空比都为0.5。
  7. 如权利要求6所述的移位寄存器单元，其中，m等于1；
    所述降噪模块包括：第二降噪晶体管，栅极与所述第N+1级移位寄存器单元的下拉节点连接，第一极与所述栅极驱动信号输出端连接，第二极接入低电平；
    由第二时钟信号输入端为第N+1级移位寄存器单元提供正相时钟信号，由第四时钟信号输入端为第N+1级移位寄存器单元提供反相时钟信号。
  8. 一种移位寄存器单元的驱动方法，应用于如权利要求1至7中任一权利要求所述的移位寄存器单元，其中，所述驱动方法包括：
    在输出截止保持阶段，控制下拉节点的电位与反相时钟信号的电位相同；
    在输出截止保持阶段，控制降噪控制信号和所述反相时钟信号相互反相；
    当所述降噪控制信号有效时，降噪模块控制栅极驱动信号出端接入低电 平。
  9. 一种栅极驱动电路，包括多级如权利要求1至7中任一权利要求所述的移位寄存器单元。
  10. 如权利要求9所述的栅极驱动电路，其中，当所述栅极驱动电路与2n个时钟信号输入端连接时，所述第N级移位寄存器单元的降噪控制信号输出端与第N+n级移位寄存器单元的下拉节点连接，n和N都为正整数。
  11. 如权利要求10所述的栅极驱动电路，其中，当n大于1时，所述第N级移位寄存器单元的降噪控制信号输出端还与第N+m级移位寄存器单元的下拉节点连接，m为小于n的正整数。
  12. 如权利要求10所述的栅极驱动电路，其中，当所述栅极驱动电路与两个时钟信号输出端连接时，所述第N级移位寄存器单元的降噪控制信号输出端与第N+1级移位寄存器单元的下拉节点连接；
    由第一时钟信号输入端为第N级移位寄存器单元提供正相时钟信号，由第二时钟信号输入端为第N级移位寄存器单元提供反相时钟信号；
    由第二时钟信号输入端为第N+1级移位寄存器单元提供正相时钟信号，由第一时钟信号输入端为第N+1级移位寄存器单元提供反相时钟信号。
  13. 如权利要求11所述的栅极驱动电路，其中，当所述栅极驱动电路与四个时钟信号输出端连接时，所述第N级移位寄存器单元的降噪控制信号输出端与第N+2级移位寄存器单元的下拉节点连接；
    由第一时钟信号输入端为第N级移位寄存器单元提供正相时钟信号，由第三时钟信号输入端为第N级移位寄存器单元提供反相时钟信号；
    由第三时钟信号输入端为第N+2级移位寄存器单元提供正相时钟信号，由第一时钟信号输入端为第N+2级移位寄存器单元提供反相时钟信号；
    第一时钟信号和第三时钟信号反相；
    第二时钟信号比第一时钟信号推迟0.25个时钟周期，第四时钟信号比第三时钟信号推迟0.25个时钟周期，第一时钟信号的占空比、第二时钟信号的占空比、第三时钟信号的占空比和第四时钟信号的占空比都为0.5。
  14. 如权利要求13所述的栅极驱动电路，其中，m等于1；
    由第二时钟信号输入端为第N+1级移位寄存器单元提供正相时钟信号， 由第四时钟信号输入端为第N+1级移位寄存器单元提供反相时钟信号。
  15. 一种显示装置，包括如权利要求9至14中任一权利要求所述的栅极驱动电路。
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