WO2017020517A1 - 移位寄存器、栅极驱动电路、显示面板及其驱动方法和显示装置 - Google Patents

移位寄存器、栅极驱动电路、显示面板及其驱动方法和显示装置 Download PDF

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WO2017020517A1
WO2017020517A1 PCT/CN2015/099334 CN2015099334W WO2017020517A1 WO 2017020517 A1 WO2017020517 A1 WO 2017020517A1 CN 2015099334 W CN2015099334 W CN 2015099334W WO 2017020517 A1 WO2017020517 A1 WO 2017020517A1
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Prior art keywords
signal
timing
group
control signals
output
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PCT/CN2015/099334
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English (en)
French (fr)
Inventor
李付强
樊君
陈小川
董学
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京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to US15/118,303 priority Critical patent/US9847067B2/en
Priority to EP15896602.8A priority patent/EP3333842A4/en
Publication of WO2017020517A1 publication Critical patent/WO2017020517A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0213—Addressing of scan or signal lines controlling the sequence of the scanning lines with respect to the patterns to be displayed, e.g. to save power
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0272—Details of drivers for data electrodes, the drivers communicating data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the present disclosure relates to the field of display technologies, and more particularly to a shift register, a gate driving circuit, a display panel, a driving method thereof, and a display device.
  • liquid crystal displays have been widely used in electronic display products such as televisions, computers, mobile phones and personal digital assistants.
  • the liquid crystal display includes a data driver (Source Driver), a gate driver (Gate Driver), a liquid crystal display panel, and the like.
  • the liquid crystal display panel has a pixel array, and the gate driving device is configured to sequentially open corresponding pixel rows in the pixel array to transmit the pixel data output by the data driver to the pixels, thereby displaying the image to be displayed.
  • the gate driving device is generally formed on the array substrate of the liquid crystal display by an array process, that is, a Gate Driver on Array (GOA) process, which not only saves cost, but also can realize a liquid crystal panel ( Panel) symmetrical aesthetic design on both sides, at the same time, the bonding area of the integrated circuit of IC (Integrated Circuit) and the wiring space of the Fan-out area are omitted, so that a narrow bezel can be realized. Design; and, this integrated process also eliminates the Bonding process in the direction of the gate scan line, which increases throughput and yield.
  • GOA Gate Driver on Array
  • the gate driving device is generally composed of a plurality of cascaded shift registers, such that the driving signal output ends of the shift registers of the respective stages correspond to a gate line, respectively, for sequentially outputting the scanning signals to the respective gate lines in the scanning direction.
  • the structure of the specific shift register is as shown in FIG. 1 , and includes: an input unit 1, a reset unit 2, a node control unit 3, a pull-up unit 4, a pull-down unit 5, an input signal terminal Input, a reset signal end Reset, and a first clock signal.
  • the input unit 1 is configured to control the potential of the first node PU under the control of the input signal terminal Input
  • the reset unit 2 is configured to control the potential of the first node PU under the control of the reset signal end Reset
  • the node control unit 3 is used to control the One node PU and The potential of the second node PD
  • the pull-up unit 4 is configured to provide the signal of the first clock signal terminal ck to the driving signal output terminal Out under the control of the first no
  • the shift register in the gate driving device in the display panel is generally as shown in FIG. 1.
  • the display panel sequentially outputs scanning signals to the respective gate lines in the scanning direction through the shift registers of the stages.
  • the power consumption of the display panel also increases with the increase of the resolution, resulting in a greatly reduced standby time. Therefore, how to reduce the power consumption of the display product to improve the standby time is a technical problem that those skilled in the art need to solve.
  • the embodiments of the present invention provide a shift register, a driving method of the display panel, and related devices, which are used to reduce the resolution of the display panel under special circumstances, thereby reducing the power consumption of the display panel.
  • a shift register provided by an embodiment of the present invention includes: an input unit, a reset unit, a node control unit, a pull-up unit, a pull-down unit, an input signal end, a reset signal end, a first clock signal end, and a reference signal end;
  • the output end of the input unit, the output end of the reset unit, the first end of the node control unit, and the control end of the pull-up unit are all connected to a first node, and the node control unit
  • the control ends of the two-terminal and pull-down units are both connected to the second node; the output end of the pull-up unit and the output end of the pull-down unit are both connected to the drive signal output end of the shift register;
  • the input unit Controlling a potential of the first node under control of an input signal terminal, the reset unit for controlling a potential of the first node under control of a reset signal terminal, the node control unit for controlling the first a potential of the node and the second node, the pull-up unit is configured
  • the first input end of the selection output unit is connected to the first node, the second input end is connected to the second node, the third input end is connected to the selection control signal end, and the output end is used as the shift register. Select the drive output;
  • the selection output unit is configured to output, when the selection control signal end receives the selection control signal, the same signal as the output of the drive signal of the shift register.
  • the selection output unit specifically includes: a first switching transistor, a second switching transistor, a third switching transistor, and a fourth switching transistor; among them,
  • the first switching transistor has a gate connected to a gate of the second switching transistor and the selection control signal end, a source connected to the first node, and a drain and a gate of the third switching transistor Extremely connected
  • the second switching transistor has a source connected to the second node and a drain connected to a gate of the fourth switching transistor;
  • the third switching transistor has a source connected to the first clock signal end and a drain connected to the selective driving output end;
  • the fourth switching transistor has a source connected to the reference signal terminal and a drain connected to the selective driving output terminal.
  • the first switching transistor and the second switching transistor are both P-type transistors or N-type transistors;
  • the third switching transistor and the fourth switching transistor are both P-type transistors or N-type transistors.
  • the embodiment of the present invention further provides a gate driving circuit, including a plurality of the above-mentioned shift registers provided by the embodiments of the present invention;
  • the signal input end of the first stage shift register is used to receive the trigger signal
  • the drive signal output ends of each of the shift registers of each stage are respectively connected to the reset signal end of the shift register of the previous stage adjacent thereto;
  • the selection drive output of each stage of the shift register is used to connect to the gate line.
  • an embodiment of the present invention further provides a display panel including 4N gate lines, a first gate driving circuit and a third gate driving circuit on one side of the display panel, which are located on the other side of the display panel. a second gate driving circuit and a fourth gate driving circuit; the first gate driving circuit, the second gate driving circuit, the third gate driving circuit, and the fourth gate driving circuit A gate driving circuit provided by an embodiment of the present invention;
  • the selected driving output terminals of the shift registers of the first gate driving circuit are respectively connected to the 4n+1th gate line, and the selected driving output of each shift register in the second gate driving circuit
  • the terminals are respectively connected to the 4th+2th gate lines, and the selected driving output ends of the shift registers of the third gate driving circuit are respectively connected to the 4n+3 gate lines, and the fourth gate driving circuit is respectively connected
  • the selected drive output terminals of the shift registers of the middle stages are respectively connected to the 4n+4 gate lines; wherein n is an integer greater than and equal to 0 and less than N;
  • the display panel further includes: at least for outputting a selection control signal to each gate driving circuit and outputting a first group of timing control signals to the first gate driving circuit, a second group of timing control signals output by the second gate driving circuit, outputting a third group of timing control signals to the third gate driving circuit, and outputting a fourth group of timing control signals to the fourth gate driving circuit Driving control circuit; wherein each group of timing control signals includes at least a trigger signal and a clock signal, and the trigger signals have the same width in each group of timing control signals, and each of the gate driving circuits is configured to receive a corresponding group of timing control signals The scan signal is outputted by the drive signal output terminal in turn under control.
  • the display panel provided by the embodiment of the present invention further includes: a mode switching circuit connected to the driving control circuit; and the value of each m is respectively connected to the 3m+1th gate line and a switching device between the 3m+2 gate lines, and a switching device respectively connected between the 3m+2 gate lines and the 3m+3 gate lines for each m value, and each of the The switching devices are all connected to the mode switching circuit; wherein m is an integer greater than and equal to 0; the mode switching circuit is configured to: when receiving the first mode control signal:
  • the selection control signal terminals of the shift register each output a selection control signal, or control the drive control circuit to output a selection control signal to a selection control signal terminal of a shift register connected to the 3m+3 gate lines.
  • the mode switching circuit is further configured to: when receiving the second mode control signal:
  • the mode switching circuit is further configured to: when receiving the third mode control signal:
  • timings of respective signals in the first group of timing control signals to be the same as timings of corresponding signals in the second group of timing control signals, and timings of signals in the third group of timing control signals and the fourth group
  • the timings of the corresponding signals in the timing control signals are the same, and the timing of each of the third group of timing control signals is delayed by one trigger signal width from the timing of the corresponding signals in the first group of timing control signals;
  • the mode switching circuit is further configured to: when receiving the fourth mode control signal:
  • timing of a signal in the first group of timing control signals and a timing of a corresponding signal in the second group of timing control signals, a timing of a corresponding signal in the third group of timing control signals, and the fourth group of timings are the same;
  • the embodiment of the present invention further provides a display device, which includes any of the above display panels provided by the embodiments of the present invention.
  • an embodiment of the present invention further provides a driving method for the foregoing display panel, including:
  • the mode switching circuit When the mode switching circuit receives the first mode control signal: controlling all of the switching devices to be in an on state; causing timing of each of the second group of timing control signals to be compared to the first group of timing control signals The timing of the corresponding signal is delayed by one-half of the trigger signal width; the timing of each signal in the third group of timing control signals is delayed by one-half of the timing of the corresponding signal in the second group of timing control signals Width; delaying a timing of each signal in the fourth group of timing control signals by a trigger signal width of one-half of a timing of a corresponding signal in the third group of timing control signals; and controlling the driving control circuit to
  • the selection control signal terminal of the shift register connected to the 3m+1 gate lines outputs a selection control signal, or controls the drive control circuit to output to the selection control signal terminal of the shift register connected to the 3m+2 gate lines. Selecting a control signal, or controlling the drive control circuit to output a selection control signal to a selection control signal terminal of a shift register connected to
  • the mode switching circuit when the mode switching circuit receives the second mode control signal: controlling all of the switching devices to be in an off state; causing timing of each of the second group of timing control signals to be shorter than the first group of timing control signals The timing of the corresponding signal is delayed by one-half of the trigger signal width; the timing of each signal in the third group of timing control signals is delayed by one-half of the timing of the corresponding signal in the second group of timing control signals a signal width; delaying a timing of each of the fourth set of timing control signals by a ratio of a trigger signal width of a corresponding one of the third set of timing control signals; and controlling the drive control circuit to all
  • the selection control signal terminal of the shift register outputs a selection control signal;
  • the mode switching circuit when the mode switching circuit receives the third mode control signal: controlling all of the switching devices to be in an off state; timing of each signal in the group of timing control signals and corresponding signals in the second group of timing control signals The timing is the same, the timing of each signal in the third group of timing control signals is the same as the timing of the corresponding signal in the fourth group of timing control signals, and the timing ratio of each signal in the third group of timing control signals is The timing of the corresponding signal in the first group of timing control signals is delayed by a trigger signal width; and the driving control circuit is controlled to output a selection control signal to the selection control signal terminals of all the shift registers;
  • the mode switching circuit when the mode switching circuit receives the fourth mode control signal: controlling all of the switching devices to be in an off state; and causing timing of each of the first group of timing control signals and the second group of timing control signals The timing of the corresponding signal, the timing of the corresponding signal in the third group of timing control signals, and the timing of the corresponding signal in the fourth group of timing control signals are the same; and controlling the driving control circuit to all the shift registers Select control signal terminal to output selection control letter number.
  • the shift register is equivalent to adding a selection output unit and a selection control signal end to the existing shift register;
  • the output terminal outputs the same signal as the drive signal output terminal of the shift register. Therefore, it is possible to determine whether or not the scan output is selected at the drive output by selecting the control signal terminal and the control of the selection output unit.
  • the gate driving circuit including the shift register described above it is possible to selectively output a scanning signal to a partial gate line.
  • the gate driving circuit is used, and switching devices respectively connected between the 3m+1th gate line and the 3m+2 gate lines are added, and respectively connected.
  • 1 is a schematic structural diagram of a conventional shift register
  • FIG. 2 is a schematic structural diagram of a shift register according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a selection output unit according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a shift register according to an embodiment of the present invention.
  • FIG. 5 is a timing chart of input and output corresponding to the shift register shown in FIG. 4;
  • FIG. 6 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 7a and 7b are schematic structural views of a display panel according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a first gate driving circuit according to an embodiment of the present invention.
  • FIG. 8b is a timing diagram of input and output corresponding to the first gate driving circuit shown in FIG. 8a;
  • 9a is a schematic structural diagram of a display panel according to an embodiment of the present invention.
  • 9b is a schematic structural diagram of a display panel when the mode switching circuit receives the first mode control signal
  • 10a is a timing diagram of four sets of timing control signals output by the control driving control circuit when the mode switching circuit receives the first mode control signal or the third mode control signal in the display panel according to an embodiment of the present disclosure
  • FIG. 10b is a timing diagram of scan signals on a corresponding gate line when a mode switching circuit receives a first mode control signal in a display panel according to an embodiment of the present invention
  • FIG. 11 is a timing diagram of scan signals on a corresponding gate line when a mode switching circuit receives a second mode control signal in a display panel according to an embodiment of the present disclosure
  • 12a is a timing diagram of controlling four sets of timing control signals output by a driving control circuit when a mode switching circuit receives a third mode control signal in a display panel according to an embodiment of the present disclosure
  • FIG. 12b is a timing diagram of scan signals on a corresponding gate line when a mode switching circuit receives a third mode control signal in a display panel according to an embodiment of the present invention
  • 13a is a timing diagram of controlling four sets of timing control signals output by a driving control circuit when a mode switching circuit receives a fourth mode control signal in a display panel according to an embodiment of the present disclosure
  • FIG. 13b is a timing diagram of scan signals on a corresponding gate line when a mode switching circuit receives a fourth mode control signal in a display panel according to an embodiment of the present invention.
  • first, second, third, etc. may be used herein to describe various elements, components and/or portions, these elements, components and/or portions are not limited by these terms. These terms are only used to distinguish one element, component or part. Thus, a first element, component or portion discussed below may be referred to as a second element, component or portion without departing from the teachings of the invention.
  • the gate drive circuit uses a specially designed shift register.
  • the specific embodiments of the shift register, the driving method of the display panel, and related devices provided by the embodiments of the present invention are described in detail below with reference to the accompanying drawings.
  • a shift register provided by an embodiment of the present invention includes: an input unit 1, a reset unit 2, a node control unit 3, a pull-up unit 4, a pull-down unit 5, an input signal terminal Input, and a reset signal end.
  • the signal output terminal Out is connected; the input unit 1 is used to control the potential of the first node PU under the control of the input signal terminal Input, and the reset unit 2 is configured to control the potential of the first node PU under the control of the reset signal terminal Reset, and the node control
  • the unit 3 is configured to control the potentials of the first node A and the second node B, and the pull-up unit 4 is configured to provide the signal of the first clock signal terminal ck1 to the driving signal output terminal Out under the control of the first node PU, and the pull-down unit 5 for Under the control of the second node PD, the signal of the reference signal terminal Vref is supplied to the driving signal output terminal Out; further comprising: a selection output unit 6 and a selection control signal terminal EN; wherein
  • the first input terminal of the selection output unit 6 is connected to the first node PU, the second input terminal is connected to the second node PD, the third input terminal is connected to the selection control signal terminal EN, and the output terminal is used as the selection drive output terminal of the shift register. Output;
  • the selection output unit 6 is for outputting the same signal as the drive signal output terminal Out when the selection control signal terminal EN receives the selection control signal.
  • the above shift register provided by the embodiment of the present invention is equivalent to adding a selection output unit and a selection control signal end to the existing shift register; wherein the first input end of the selection output unit is connected to the first node, The second input end is connected to the second node, the third input end is connected to the selection control signal end, the output end is connected to the selected drive output end of the shift register; and the selection output unit is configured to receive the selection control signal when the selection control signal end receives Its output outputs the same signal as the drive signal output of the shift register. Therefore, it is possible to determine whether or not the scan output is selected at the drive output by selecting the control signal terminal and the control of the selection output unit. Further, in the gate driving circuit including the shift register described above, it is possible to selectively output a scanning signal to a partial gate line.
  • the output unit 6 is selected, and specifically includes: a first switching transistor T1, a second switching transistor T2, a third switching transistor T3, and a Four switching transistor T4; wherein
  • a first switching transistor T1 having a gate connected to a gate of the second switching transistor T2 and a selection control signal terminal EN, a source connected to the first node PU, and a drain connected to a gate of the third switching transistor T3;
  • a second switching transistor T2 having a source connected to the second node PD and a drain connected to the gate of the fourth switching transistor T4;
  • a third switching transistor T3 having a source connected to the first clock signal terminal ck1 and a drain connected to the selective driving output terminal Output;
  • the fourth switching transistor T4 has a source connected to the reference signal terminal Vref and a drain connected to the selective driving output terminal Output.
  • the potential of the gate of the third switching transistor is the same as the potential of the first node
  • the fourth switching transistor is The potential of the gate is the same as the potential of the second node, so that when the pull-up unit supplies the signal of the first clock signal terminal to the output of the driving signal under the control of the first node, the third switching transistor also generates the first clock signal.
  • the signal of the terminal is supplied to the selective driving output terminal.
  • the pull-down unit supplies the signal of the reference signal terminal to the output of the driving signal under the control of the second node
  • the fourth switching transistor also supplies the signal of the reference signal terminal to the selected driving output terminal. This ensures that the signal selected at the drive output is the same as the signal at the output of the drive signal.
  • the first switching transistor and the second switching transistor are both P-type transistors or N-type transistors;
  • the third switching transistor and the fourth switching transistor are both P-type transistors or both are N-type transistors.
  • the first switching transistor and the second switching transistor, the third switching transistor, and the fourth switching transistor are all P-type transistors or both are N. Type transistor.
  • the above is only a specific structure for selecting an output unit in the shift register.
  • the specific structure of the output unit is not limited to the above-mentioned structure provided by the embodiment of the present invention, and may be other structures known to those skilled in the art. There is no limit here.
  • the node control unit is specific And controlling the potential of the second node according to the potential of the first node, and controlling the potential of the first node according to the potential of the second node, thereby implementing the basic function of the shift register by controlling the potentials of the first node and the second node.
  • the structures of the input unit, the reset unit, the node control unit, the pull-up unit, and the pull-down unit are the same as those in the prior art, and are not described in detail herein. The following is explained by a specific embodiment, but is not limited thereto.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the input unit 1 may include a fifth switching transistor T5; the reset unit 2 may include a sixth switching transistor T6; and the node control unit 3 may include a seventh switching transistor T7, an eighth switching transistor T8, and a nine-switching transistor T9 and a tenth switching transistor T10 and a first capacitor C1; the pull-up unit 4 may include an eleventh switching transistor T11 and a second capacitor C2; the pull-down unit 5 may include a twelfth switching transistor T12; wherein, the fifth The gate of the switching transistor T5 is connected to the input signal terminal Input, the source is connected to the first DC signal terminal VDD, the drain is connected to the pull-up node PU, and the gate of the sixth switching transistor T6 is connected to the reset signal terminal Reset.
  • the pole is connected to the second DC signal terminal VSS, and the drain is connected to the first node PU; the gate and the source of the seventh switching transistor T7 are both connected to the second clock signal terminal ckb1, and the drain is connected to the second node PD;
  • the gate of the eight-switch transistor T8 is connected to the second node PD, the source is connected to the reference signal terminal Vref, the drain is connected to the first node PU, and the gate of the ninth switching transistor T9 is connected to the first node PU, the source
  • the reference signal terminal Vref is connected, the drain is connected to the second node PD;
  • the gate of the tenth switching transistor T10 is connected to the driving signal output terminal Out, the source is connected to the reference signal terminal Vref, and the drain is connected to the second node PD;
  • the gate of the eleventh switching transistor T11 is connected to the first node PU, the source is connected to the first clock signal terminal ck1, the drain is connected to the driving signal output terminal Out
  • all of the switching transistors in FIG. 4 are N-type transistors.
  • all switching transistors may also be P-type transistors, or some of the transistors are N-type transistors, and some of the transistors are P-type transistors. Not limited.
  • the shift register repeats the fourth phase and the fifth phase until the potential of the input signal terminal Input becomes high again.
  • the switching transistor mentioned in the above embodiment of the present invention may be a thin film transistor (TFT) or a metal oxide semiconductor field effect transistor (MOS, Metal Oxide Semiconductor), which is not limited herein. .
  • TFT thin film transistor
  • MOS metal oxide semiconductor field effect transistor
  • the source and the drain of these switching transistors are interchangeable according to the type of the transistor and the input signal, and no specific distinction is made here.
  • an embodiment of the present invention further provides a gate driving circuit, as shown in FIG. 6, including a plurality of cascaded shift registers provided by the embodiments of the present invention: SR(1), SR(2 )...SR(m)...SR(N-1), SR(N) (total N shift registers, 1 ⁇ m ⁇ N);
  • the signal input terminal Input of the first stage shift register SR(1) is for receiving a trigger signal
  • the drive signal output terminals OUT_m of each of the shift register SR(m) are respectively adjacent to the upper stage shift register SR(m-1) adjacent thereto.
  • the reset signal terminal Reset is connected;
  • the selection drive output Output_m of each stage shift register SR(m) is used to be connected to the gate line.
  • the gate driving circuit is connected to the corresponding gate line gatem through the selective driving output terminal Output_m of each stage shift register SR(m) for sequentially outputting the scanning signal to the corresponding gate line.
  • the mth gate line is only when the selected output unit in the mth stage shift register is in an on state under the control of the corresponding selection control signal terminal. There is a scan signal output.
  • the gate drive circuit sequentially outputs scan signals to the corresponding gate lines.
  • the first clock signal terminal ck1 of the odd-numbered shift register and the second clock signal terminal ckb1 of the even-numbered shift register are used.
  • Receiving the same clock signal (indicated as CK1 in the figure), the second clock signal terminal ckb1 of the odd-numbered shift register and the first clock signal terminal ck1 of the even-numbered shift register are used to receive the same clock signal (shown as CKB1 in the figure) ).
  • an embodiment of the present invention further provides a display panel, as shown in FIG. 7a and FIG. 7b, including 4N gate lines (gate1, gate2, gate3, ...), and a first gate on one side of the display panel.
  • the driving circuit GOA1 and the third gate driving circuit GOA3 are located on the other side of the display panel, the second gate driving circuit GOA2 and the fourth gate driving circuit GOA4; wherein, the first gate driving circuit GOA1 and the second gate driving The circuit GOA2, the third gate driving circuit GOA3, and the fourth gate driving circuit GOA4 are all the above-mentioned gate driving circuits provided by the embodiments of the present invention;
  • the selected driving output ends of the shift registers of the first gate driving circuit GOA1 are respectively connected to the 4n+1th gate lines (gate1, gate5, gate9...), and the second gate driving circuit GOA2 moves in various stages.
  • the selection drive output terminal of the bit register is respectively connected to the 4n+2 gate lines (gate2, gate6, gate10%), and the selected drive output terminals of the shift registers of the third gate drive circuit GOA3 are respectively associated with the 4n+3
  • the gate lines (gate3, gate7, gate11...) are connected, and the selected drive outputs of the shift registers of the fourth gate drive circuit GOA4 are respectively connected to the 4n+4 gate lines (gate4, gate8, gate12...);
  • n is an integer greater than and equal to 0 and less than N;
  • the display panel further includes: at least for outputting a selection control signal to each of the gate driving circuits (GOA1, GOA2, GOA3, and GOA4) and to the first gate, connected to each of the gate driving circuits (GOA1, GOA2, GOA3, and GOA4)
  • the pole drive circuit GOA1 outputs a first set of timing control signals (including at least a first trigger signal STV1, a first clock signal CK1 and a second clock signal CKB1), and a second set of timing control signals outputted to the second gate drive circuit GOA2 ( Include at least a second trigger signal STV2, a third clock signal CK2, and a fourth clock signal CKB2), and output a third group of timing control signals to the third gate driving circuit GOA3 (including at least a third trigger signal STV3, a fifth clock signal CK3) And the sixth clock signal CKB3), the drive control circuit 10 of the fourth group of timing control signals (including at least the fourth trigger signal STV4, the seventh clock signal CK4, and the eighth clock signal CKB4) output
  • the drive control circuit 10 inputs a first trigger signal STV1 to the first stage shift register SR(1) to the first clock signal terminal ck1 and the even-number shift register of the odd-numbered shift register, respectively.
  • the second clock signal terminal ckb1 inputs the first clock signal CK1, and inputs the second clock signal CKB1 to the second clock signal terminal ckb1 of the odd-numbered shift register and the first clock signal terminal ck1 of the even-numbered shift register.
  • the driving signal output terminal Out_1 After the first stage shift register SR(1) receives the first trigger signal STV1, when the first clock signal terminal ck1 receives the first clock signal CK1 for the first time, the driving signal output terminal Out_1 outputs a scan signal.
  • the selection output terminal Output_1 When the corresponding selection output unit receives the selection control signal and is in the on state, the selection output terminal Output_1 outputs the scan signal to the first gate line gate1, and the first stage shift register SR(1) drives the signal.
  • the scan signal outputted by the output terminal Out_1 is supplied to the input signal terminal Input of the second stage shift register SR(2); when the second stage shift register SR(2) receives the output of the first stage shift register SR(1) After the signal is scanned, when the first clock signal terminal ck1 receives the second clock signal CKB1 for the first time, the driving signal output terminal Out_2 outputs the scan signal.
  • the drive output terminal Output_2 is selected to output a scan signal to the fifth gate line gate5, and the scan signal outputted by the second stage shift register SR(2) drive signal output terminal Out_2 is supplied to the third stage shift.
  • the driving output terminal Output_3 is selected to the ninth strip.
  • the gate line gate9 outputs a scan signal, and the scan signal outputted by the third stage shift register SR(3) drive signal output terminal Out_3 is supplied to the input signal terminal Input of the fourth stage shift register SR(4), and so on.
  • the bit register sequentially outputs a scan signal to the corresponding gate line.
  • the input and output timing diagram corresponding to the specific first gate driving circuit is as shown in FIG. 8b.
  • the driving control circuit inputs a second trigger signal to the first stage shift register of the second gate driving circuit to the first clock signal end of the odd-numbered shift register and the second clock signal of the even-numbered shift register, respectively.
  • the terminal inputs a third clock signal, and inputs a fourth clock signal to the second clock signal end of the odd-numbered shift register and the first clock signal end of the even-numbered shift register.
  • the driving control circuit inputs a third trigger signal to the first stage shift register of the third gate driving circuit, and inputs to the first clock signal end of the odd-numbered shift register and the second clock signal end of the even-numbered shift register, respectively.
  • the fifth clock signal inputs a sixth clock signal to the second clock signal end of the odd-numbered shift register and the first clock signal end of the even-numbered shift register.
  • the driving control circuit inputs a fourth trigger signal to the first stage shift register of the fourth gate driving circuit, and inputs the first trigger signal to the first clock signal end of the odd-numbered shift register and the second clock signal end of the even-numbered shift register, respectively.
  • the seven clock signals input an eighth clock signal to the second clock signal end of the odd-numbered shift register and the first clock signal end of the even-numbered shift register.
  • the method further includes: a mode switching circuit 20 connected to the driving control circuit 10; for each m value, respectively connected to the 3m a switching device 30 between the +1 gate line and the 3m+2 gate line; and a value for each m, respectively connected between the 3m+2 gate line and the 3m+3 gate line
  • the switching device 30; and each switching device 30 is connected to the mode switching circuit 20; wherein m is an integer greater than and equal to 0; the mode switching circuit 20 is configured to: when receiving the first mode control signal:
  • the timing of each of the second group of timing control signals is compared to the first group of timing control signals (including at least the first trigger signal STV1, The timing of the corresponding signal in one of the clock signal CK1 and the second clock signal CKB1) is delayed by one-half of the trigger signal width; the third group of timing control signals (including at least the third trigger signal STV3, the fifth clock signal CK3 and the sixth) The timing of each signal in the clock signal CKB3) is delayed by one-half of the trigger signal width than the timing of the corresponding signal in the second group of timing control signals; the fourth group of timing control signals (including at least the fourth trigger signal STV4, the seventh clock) The timing of each signal in the signal CK4 and the eighth clock signal CKB4) is delayed by one-half of the trigger signal width than the timing of the corresponding signal in the third group of timing control signals, and the timing diagrams of the specific four sets of timing control signals are as shown in FIG. 10
  • the drive control circuit And controlling the drive control circuit to output a selection control signal to the selection control signal terminal of the shift register connected to the 3m+1th gate line, or to control the drive control circuit to shift register connected to the 3m+2 gate lines Selecting a control signal terminal to output a selection control signal, or controlling a drive control circuit to output a selection control signal to a selection control signal terminal of a shift register connected to the 3m+3 gate lines; the purpose is to make each gate driving circuit only And sequentially outputting a scan signal to the 3m+1th gate line, or the 3m+2 gate line or the 3m+3 gate line; to control the drive control circuit 10 to the 3m+2
  • the selection control signal of the shift register connected to the gate gate line gate3m+2 is an example of outputting the selection control signal, and the gate drive circuit is connected to the 3m+1th gate line and the 3m+2 gate line.
  • the selection of the bit register controls the signal terminal output selection control signal, and the shift register connected to the 3m+1th gate line and the shift register connected to the 3m+2 gate lines can output the scan signal, as shown in FIG. 9b.
  • the black line at the beginning of the gate line indicates that the selection control signal terminal of the shift register in the gate driving circuit has a selection control signal, and the corresponding selection driving output terminal can output a scanning signal, and the starting end of the gate line is a circle. It is indicated that the selection control signal end of the shift register in the gate driving circuit does not select the control signal, and the corresponding selected driving output terminal does not output the scan signal;
  • the purpose is to make the scanning signals of the 3m+1th gate line and the 3m+2 gate lines and the 3m+3 gate lines the same, thereby realizing the adjacent three gate lines as a gate line group along the scanning direction.
  • Each gate line group sequentially receives the scan signal, that is, the display panel is scanned simultaneously by three gate lines, and the resolution of the display panel is reduced to 1/3 resolution.
  • the display panel provided by the embodiment of the present invention controls the drive control circuit 10 to shift the shift register connected to the 3m+2 gate line gate3m+2 when the mode switching circuit receives the first mode control signal.
  • the control signal terminal to output the selection control signal as an example, the timing chart of the scanning signals on the respective gate lines on the display panel along the scanning direction is as shown in FIG. 10b.
  • a selection output unit is added to each shift register compared with the conventional display panel, and the connection is further increased to the 3m+1 grid line and the 3m+2 A switching device between the gate lines, and a switching device respectively connected between the 3m+2 gate lines and the 3m+3 gate lines, and a mode switching circuit connected to the driving control circuit.
  • the mode switching circuit receives the first mode control signal
  • the display panel can realize the adjacent three gate lines as a gate line group along the scanning direction, and sequentially receive the scan signals in each of the gate line groups along the scanning direction, even if the display is performed.
  • the resolution of the panel is reduced to 1/3 resolution, which allows the display panel to reduce power consumption and extend standby time.
  • the switching devices respectively connected between the 3m+1th gate line and the 3m+2 gate lines are respectively connected between the 3m+1th gate line and the 3m+2 gate lines.
  • the mode switching circuit is further configured to: when receiving the second mode control signal:
  • Controlling all switching devices to be in a closed state the purpose is to ensure that the signals of the respective gate lines do not affect each other;
  • the control drive control circuit outputs a selection control signal to all of the selection control signal terminals of the shift register; the purpose is to make the selected drive output end of each shift register the same as the signal of the corresponding drive signal output end;
  • the timing of each signal in the second group of timing control signals is delayed by one-half of the trigger signal width from the timing of the corresponding signals in the first group of timing control signals; and the timing of each signal in the third group of timing control signals is compared to the second group
  • the timing of the corresponding signal in the timing control signal is delayed by one-half of the trigger signal width; the timing of each signal in the fourth group of timing control signals is delayed by one-half of the timing of the corresponding signal in the third group of timing control signals.
  • the mode switching circuit controls the four sets of timing control signals output by the control driving control circuit when receiving the second mode control signal, and controls the control driving circuit output by the mode switching circuit when receiving the first mode control signal
  • the group timing control signal is the same; the specific timing diagram is shown in FIG. 10a, that is, the purpose is to enable the driving signal output end of each shift register to have a scanning signal output, thereby realizing the function of scanning line by line in the scanning direction, that is, displaying
  • the panel has a higher resolution.
  • the above display panel provided by the embodiment of the present invention can be set to low-resolution display not only when power saving is required, but also can realize high-resolution display when power saving is not required.
  • the mode switching circuit when the mode switching circuit receives the second mode control signal, the timing chart of the scanning signals on the respective gate lines on the display panel in the scanning direction is as shown in FIG. 11 .
  • the mode switching circuit is further configured to: when receiving the third mode control signal:
  • Controlling all switching devices to be in a closed state the purpose is to ensure that the signals of the respective gate lines do not affect each other;
  • the control drive control circuit outputs a selection control signal to all of the selection control signal terminals of the shift register; the purpose is to make the selected drive output end of each shift register the same as the signal of the corresponding drive signal output end;
  • the timing of each signal in the first group of timing control signals is the same as the timing of the corresponding signals in the second group of timing control signals, so that the timing of each signal in the third group of timing control signals and the timing of the corresponding signals in the fourth group of timing control signals The same, and the timing of each signal in the third group of timing control signals is delayed by one trigger signal width from the timing of the corresponding signals in the first group of timing control signals;
  • the specific timing diagram is as shown in FIG. 12a; the purpose is to achieve in the scanning direction
  • the adjacent two gate lines are a group of gate lines, and the scanning lines are sequentially received in the scanning direction, that is, the display panel is simultaneously scanned by two gate lines, and the resolution of the display panel is reduced to 1/2 resolution. .
  • the mode switching circuit when the mode switching circuit receives the third mode control signal, the timing chart of the scanning signals on the respective gate lines on the display panel in the scanning direction is as shown in FIG. 12b.
  • the mode switching circuit is further configured to: when receiving the fourth mode control signal:
  • Controlling all switching devices to be in a closed state the purpose is to ensure that the signals of the respective gate lines do not affect each other;
  • the control drive control circuit outputs a selection control signal to all of the selection control signal terminals of the shift register; the purpose is to make the selected drive output end of each shift register the same as the signal of the corresponding drive signal output end;
  • FIG. 13a a timing of each signal in the first group of timing control signals and a timing of a corresponding signal in the second group of timing control signals, a timing of a corresponding signal in the third group of timing control signals, and a timing of a corresponding signal in the fourth group of timing control signals
  • the purpose is to realize that the adjacent four gate lines are a gate line group along the scanning direction, and the scan lines are sequentially received in the scanning direction, that is, the display panel is four gates.
  • the resolution of the display panel is reduced to 1/4 resolution.
  • the mode switching circuit when the mode switching circuit receives the fourth mode control signal, the timing chart of the scanning signals on the respective gate lines on the display panel in the scanning direction is as shown in FIG. 13b.
  • the switching device may be a switching transistor, or may be another electronic switch control module, which is not limited herein.
  • the sustain duration of each mode control signal is a scan. Integer multiple of the duration used by 4N grid lines, and any two mode control The switching point between the signals is synchronized with the starting point of the scanning gate line.
  • the display panel provided by the embodiment of the present invention reduces the resolution by setting a selection output unit in the shift register, adding a switching device between the gate lines, and controlling timing of the four sets of timing control signals, although the present invention
  • the embodiment only gives four cases, but the display panel which realizes 1/5 resolution, 1/6 resolution, etc. based on the above idea also belongs to the protection scope of the present invention.
  • the user can send a mode control signal to the mode switching circuit through the operation interface of the display panel according to actual requirements, which is not limited herein.
  • the display panel provided by the embodiment of the invention may be a liquid crystal display panel or an organic electroluminescence display panel, which is not limited herein.
  • an embodiment of the present invention further provides a display device, including any of the above display panels provided by the embodiments of the present invention.
  • the display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • an embodiment of the present invention further provides a driving method for the foregoing display panel, including:
  • the mode switching circuit When the mode switching circuit receives the first mode control signal: controlling all the switching devices to be in an on state; causing the timing of each signal in the second group of timing control signals to be delayed from the timing of the corresponding signals in the first group of timing control signals.
  • One of the trigger signal widths; the timing of each signal in the third group of timing control signals is delayed by one-half of the trigger signal width of the corresponding signal in the second group of timing control signals; and the fourth group of timing control signals is The timing of each signal is delayed by one-half of the trigger signal width than the timing of the corresponding signal in the third group of timing control signals; and the control control circuit is controlled to the selection control signal terminal of the shift register connected to the 3m+1th gate line
  • Each of the output selection control signals, or the control drive control circuit outputs a selection control signal to the selection control signal terminal of the shift register connected to the 3m+2 gate lines, or controls the drive control circuit to the 3m+3 gate lines.
  • the selection control signal terminal of the connected shift register outputs a
  • the mode switching circuit when the mode switching circuit receives the second mode control signal: controlling all of the switching devices to be in an off state; delaying a timing of each of the signals in the second group of timing control signals from a timing of a corresponding signal in the first group of timing control signals One-half of the trigger signal width; the timing of each of the third set of timing control signals is delayed by one-half the timing of the corresponding one of the second set of timing control signals Trigger signal width; delaying the timing of each signal in the fourth group of timing control signals by one-half of the trigger signal width of the corresponding signal in the third group of timing control signals; and controlling the driving control circuit to all shift registers Selecting a control signal terminal to output a selection control signal;
  • the mode switching circuit receives the third mode control signal: controlling all of the switching devices to be in a closed state; the timing of each of the signals in the set of timing control signals is the same as the timing of the corresponding signals in the second group of timing control signals, The timing of each signal in the third group of timing control signals is the same as the timing of the corresponding signals in the fourth group of timing control signals, and the timing of each signal in the third group of timing control signals is compared with the timing of the corresponding signals in the first group of timing control signals. Delaying a trigger signal width; and controlling the drive control circuit to output a selection control signal to the selection control signal terminals of all the shift registers;
  • the mode switching circuit when the mode switching circuit receives the fourth mode control signal: controlling all of the switching devices to be in an off state; causing timing of each signal in the first group of timing control signals and timing of corresponding signals in the second group of timing control signals, The timings of the corresponding signals in the third group of timing control signals and the timings of the corresponding signals in the fourth group of timing control signals are the same; and the control driving control circuit outputs the selection control signals to the selection control signal terminals of all the shift registers.
  • a shift register, a driving method of a display panel, and a related device are provided in an embodiment of the present invention.
  • the shift register is equivalent to adding a selection output unit and a selection control signal end to the existing shift register; and selecting an output unit
  • the output terminal When the selection control signal is received at the selection control signal end, the output terminal outputs the same signal as the drive signal output end of the shift register. Therefore, it is possible to determine whether or not the scan output is selected at the drive output by selecting the control signal terminal and the control of the selection output unit.
  • the gate driving circuit including the shift register described above it is possible to selectively output a scanning signal to a partial gate line.
  • the gate driving circuit is used, and switching devices respectively connected between the 3m+1th gate line and the 3m+2 gate lines are added, and respectively connected.

Abstract

一种移位寄存器、显示面板的驱动方法及相关装置，该移位寄存器在现有的移位寄存器的基础上增加了选择输出单元（6）和选择控制信号端（EN）；选择输出单元（6）用于在选择控制信号端（EN）接收到选择控制信号时，其输出端输出与驱动信号输出端相同的信号。从而可以通过选择控制信号端（EN）和选择输出单元（6）的控制决定选择驱动输出端是否有扫描信号输出。进而在采用上述移位寄存器构成的栅极驱动电路中，可以实现选择性的向部分栅线输出扫描信号。进一步在显示面板中在采用上述栅极驱动电路，可以实现沿扫描方向以相邻的三条栅线为一栅线组，沿扫描方向各栅线组依次接收扫描信号，即使显示面板的分辨率降低为1/3分辨率，从而可以使显示面板降低功耗，延长待机时间。

Description

移位寄存器、栅极驱动电路、显示面板及其驱动方法和显示装置 技术领域
本公开涉及显示技术领域，尤指一种移位寄存器、栅极驱动电路、显示面板及其驱动方法和显示装置。
背景技术
在科技发展日新月异的现今时代中，液晶显示器已经广泛地应用在电子显示产品上，如电视机、计算机、手机及个人数字助理装置等。液晶显示器包括数据驱动装置(Source Driver)、栅极驱动装置(Gate Driver)及液晶显示面板等。其中，液晶显示面板中具有像素阵列，而栅极驱动装置用以依序开启像素阵列中对应的像素行，以将数据驱动器输出的像素数据传输至像素，进而显示待显图像。
目前，栅极驱动装置一般通过阵列工艺形成在液晶显示器的阵列基板上，即阵列基板行驱动(Gate Driver on Array,GOA)工艺，这种集成工艺不仅节省了成本，而且可以做到液晶面板(Panel)两边对称的美观设计，同时，也省去了栅极集成电路(IC，Integrated Circuit)的绑定(Bonding)区域以及扇出(Fan-out)区域的布线空间，从而可以实现窄边框的设计；并且，这种集成工艺还可以省去栅极扫描线方向的Bonding工艺，从而提高了产能和良率。
栅极驱动装置通常由多个级联的移位寄存器构成，这样将各级移位寄存器的驱动信号输出端分别对应一条栅线，用于沿扫描方向依次向各栅线输出扫描信号。具体移位寄存器的结构如图1所示，包括：输入单元1、复位单元2、节点控制单元3、上拉单元4、下拉单元5、输入信号端Input、复位信号端Reset、第一时钟信号端ck和参考信号端Vref；其中，输入单元1的输出端、复位单元2的输出端、节点控制单元3的第一端、以及上拉单元4的控制端均与第一节点PU相连，节点控制单元3的第二端和下拉单元5的控制端均与第二节点PD相连；上拉单元4的输出端和下拉单元5的输出端均与移位在寄存器的驱动信号输出端Out相连；输入单元1用于在输入信号端Input的控制下控制第一节点PU的电位，复位单元2用于在复位信号端Reset的控制下控制第一节点PU的电位，节点控制单元3用于控制第一节点PU和 第二节点PD的电位，上拉单元4用于在第一节点PU的控制下将第一时钟信号端ck的信号提供给驱动信号输出端Out，下拉单元5用于在第二节点PD的控制下，将参考信号端Vref的信号提供给驱动信号输出端Out。
目前，显示面板中的栅极驱动装置中移位寄存器一般均如图1所示，显示面板通过各级移位寄存器沿扫描方向依次向各栅线输出扫描信号。但是随着显示产品分辨率越来越高，显示面板的功耗也随着分辨率的增大而增大，导致待机时间大大减小。因此如何降低显示产品的功耗，以提高待机时间是本领域技术人员亟需解决的技术问题。
发明内容
本发明的另外方面和优点部分将在后面的描述中阐述，还有部分可从描述中明显地看出，或者可以在本发明的实践中得到。
有鉴于此，本发明实施例提供一种移位寄存器、显示面板的驱动方法及相关装置，用于实现可以在特殊情况下降低显示面板的分辨率，从而降低显示面板的功耗。
本发明实施例提供的一种移位寄存器，包括：输入单元、复位单元、节点控制单元、上拉单元、下拉单元、输入信号端、复位信号端、第一时钟信号端和参考信号端；其中，所述输入单元的输出端、所述复位单元的输出端、所述节点控制单元的第一端、以及所述上拉单元的控制端均与第一节点相连，所述节点控制单元的第二端和下拉单元的控制端均与第二节点相连；所述上拉单元的输出端和所述下拉单元的输出端均与所述移位在寄存器的驱动信号输出端相连；所述输入单元用于在输入信号端的控制下控制所述第一节点的电位，所述复位单元用于在复位信号端的控制下控制所述第一节点的电位，所述节点控制单元用于控制所述第一节点和所述第二节点的电位，所述上拉单元用于在所述第一节点的控制下将第一时钟信号端的信号提供给驱动信号输出端，所述下拉单元用于在所述第二节点的控制下，将参考信号端的信号提供给所述提供给驱动信号输出端；还包括：选择输出单元和选择控制信号端；其中，
所述选择输出单元的第一输入端与所述第一节点相连，第二输入端与所述第二节点相连，第三输入端与选择控制信号端相连，输出端作为所述移位寄存器的选择驱动输出端；
所述选择输出单元用于在所述选择控制信号端接收到选择控制信号时，其输出端输出与所述移位寄存器的驱动信号输出端相同的信号。
在一种可能的实施方式中，在本发明实施例提供的移位寄存器中，所述选择输出单元，具体包括：第一开关晶体管、第二开关晶体管、第三开关晶体管和第四开关晶体管；其中，
所述第一开关晶体管，其栅极与所述第二开关晶体管的栅极以及所述选择控制信号端相连，源极与所述第一节点相连，漏极与所述第三开关晶体管的栅极相连；
所述第二开关晶体管，其源极与所述第二节点相连，漏极与所述第四开关晶体管的栅极相连；
所述第三开关晶体管，其源极与所述第一时钟信号端相连，漏极与所述选择驱动输出端相连；
所述第四开关晶体管，其源极与所述参考信号端相连，漏极与所述选择驱动输出端相连。
较佳地，在本发明实施例提供的移位寄存器中，所述第一开关晶体管和第二开关晶体管均为P型晶体管或均为N型晶体管；
所述第三开关晶体管和所述第四开关晶体管均为P型晶体管或均为N型晶体管。
相应地，本发明实施例还提供了一种栅极驱动电路，包括级联的多个本发明实施例提供的上述任一种移位寄存器；其中，
除最后一级移位寄存器之外，其余每一级移位寄存器的驱动信号输出端分别与与其相邻的下一级移位寄存器的输入信号端相连；
第一级移位寄存器的信号输入端用于接收触发信号；
除第一级移位寄存器之外，其余每一级移位寄存器的驱动信号输出端分别与与其相邻的上一级移位寄存器的复位信号端相连；
各级移位寄存器的选择驱动输出端用于与栅线相连。
相应地，本发明实施例还提供了一种显示面板，包括4N条栅线，位于所述显示面板一侧的第一栅极驱动电路和第三栅极驱动电路，位于显示面板另一侧的第二栅极驱动电路和第四栅极驱动电路；所述第一栅极驱动电路、所述第二栅极驱动电路、所述第三栅极驱动电路和所述第四栅极驱动电路均为本发明实施例提供的栅极驱动电路；
其中，所述第一栅极驱动电路中各级移位寄存器的选择驱动输出端分别与第4n+1条栅线连接，所述第二栅极驱动电路中各级移位寄存器的选择驱动输出端分别与第4n+2条栅线连接，所述第三栅极驱动电路中各级移位寄存器的选择驱动输出端分别与第4n+3条栅线连接，所述第四栅极驱动电路中各级移位寄存器的选择驱动输出端分别与第4n+4条栅线连接；其中，n为大于且等于0且小于N的整数；
所述显示面板还包括：与各栅极驱动电路连接的至少用于向各栅极驱动电路输出选择控制信号、以及向所述第一栅极驱动电路输出第一组时序控制信号，向所述第二栅极驱动电路输出的第二组时序控制信号，向所述第三栅极驱动电路输出第三组时序控制信号，向所述第四栅极驱动电路输出的第四组时序控制信号的驱动控制电路；其中，各组时序控制信号至少包括触发信号和时钟信号，且各组时序控制信号中触发信号的宽度相同，各所述栅极驱动电路用于在接收的对应组时序控制信号的控制下依次由驱动信号输出端输出扫描信号。
较佳地，在本发明实施例提供的上述显示面板中，还包括：与所述驱动控制电路连接的模式切换电路；针对每一个m的取值，分别连接在第3m+1条栅线与第3m+2条栅线之间的开关器件，以及针对每一个m的取值，分别连接在第3m+2条栅线与第3m+3条栅线之间的开关器件，且各所述开关器件均与所述模式切换电路连接；其中，m为大于且等于0的整数；所述模式切换电路用于在接收到第一模式控制信号时：
控制所有的开关器件处于导通状态；
使所述第二组时序控制信号中各信号的时序比所述第一组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；使所述第三组时序控制信号中各信号的时序比所述第二组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；使所述第四组时序控制信号中各信号的时序比所述第三组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；
并且控制所述驱动控制电路向与第3m+1条栅线连接的移位寄存器的选择控制信号端均输出选择控制信号，或控制所述驱动控制电路向与第3m+2条栅线连接的移位寄存器的选择控制信号端均输出选择控制信号，或控制所述驱动控制电路向与第3m+3条栅线连接的移位寄存器的选择控制信号端均输出选择控制信号。
较佳地，在本发明实施例提供的上述显示面板中，所述模式切换电路还用于在接收到第二模式控制信号时：
控制所有的开关器件处于关闭状态；
使所述第二组时序控制信号中各信号的时序比所述第一组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；使所述第三组时序控制信号中各信号的时序比所述第二组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；使所述第四组时序控制信号中各信号的时序比所述第三组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；
并且控制所述驱动控制电路向所有移位寄存器的选择控制信号端均输出选择控制信号。
较佳地，在本发明实施例提供的上述显示面板中，所述模式切换电路还用于，在接收到第三模式控制信号时：
控制所有的开关器件处于关闭状态；
使所述第一组时序控制信号中各信号的时序与所述第二组时序控制信号中对应信号的时序相同，使所述第三组时序控制信号中各信号的时序与所述第四组时序控制信号中对应信号的时序相同，并且使所述第三组时序控制信号中各信号的时序比所述第一组时序控制信号中对应信号的时序延迟一个触发信号宽度；
并且控制所述驱动控制电路向所有移位寄存器的选择控制信号端均输出选择控制信号。
较佳地，在本发明实施例提供的上述显示面板中，所述模式切换电路还用于，在接收到第四模式控制信号时：
控制所有的开关器件处于关闭状态；
使所述第一组时序控制信号中各信号的时序与所述第二组时序控制信号中对应信号的时序、所述第三组时序控制信号中对应信号的时序、以及所述第四组时序控制信号中对应信号的时序均相同；
并且控制所述驱动控制电路向所有移位寄存器的选择控制信号端均输出选择控制信号。
相应地，本发明实施例还提供了一种显示装置，包括本发明实施例提供的上述任一种显示面板。
相应地，本发明实施例还提供了一种上述显示面板的驱动方法，包括：
当所述模式切换电路在接收到第一模式控制信号时：控制所有的开关器件处于导通状态；使所述第二组时序控制信号中各信号的时序比所述第一组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；使所述第三组时序控制信号中各信号的时序比所述第二组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；使所述第四组时序控制信号中各信号的时序比所述第三组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；并且控制所述驱动控制电路向与第3m+1条栅线连接的移位寄存器的选择控制信号端均输出选择控制信号，或控制所述驱动控制电路向与第3m+2条栅线连接的移位寄存器的选择控制信号端均输出选择控制信号，或控制所述驱动控制电路向与第3m+3条栅线连接的移位寄存器的选择控制信号端均输出选择控制信号；
或者，当所述模式切换电路在接收到第二模式控制信号时：控制所有的开关器件处于关闭状态；使所述第二组时序控制信号中各信号的时序比所述第一组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；使所述第三组时序控制信号中各信号的时序比所述第二组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；使所述第四组时序控制信号中各信号的时序比所述第三组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；并且控制所述驱动控制电路向所有移位寄存器的选择控制信号端均输出选择控制信号；
或者，当所述模式切换电路在接收到第三模式控制信号时：控制所有的开关器件处于关闭状态；一组时序控制信号中各信号的时序与所述第二组时序控制信号中对应信号的时序相同，使所述第三组时序控制信号中各信号的时序与所述第四组时序控制信号中对应信号的时序相同，并且使所述第三组时序控制信号中各信号的时序比所述第一组时序控制信号中对应信号的时序延迟一个触发信号宽度；并且控制所述驱动控制电路向所有移位寄存器的选择控制信号端均输出选择控制信号；
或者，当所述模式切换电路在接收到第四模式控制信号时：控制所有的开关器件处于关闭状态；使所述第一组时序控制信号中各信号的时序与所述第二组时序控制信号中对应信号的时序、所述第三组时序控制信号中对应信号的时序、以及所述第四组时序控制信号中对应信号的时序均相同；并且控制所述驱动控制电路向所有移位寄存器的选择控制信号端均输出选择控制信 号。
本发明实施例提供的上述移位寄存器、显示面板的驱动方法及相关装置，移位寄存器相当于在现有的移位寄存器的基础上增加了选择输出单元和选择控制信号端；选择输出单元用于在选择控制信号端接收到选择控制信号时，其输出端输出与移位寄存器的驱动信号输出端相同的信号。从而可以通过选择控制信号端和选择输出单元的控制决定选择驱动输出端是否有扫描信号输出。进而在采用上述移位寄存器构成的栅极驱动电路中，可以实现选择性的向部分栅线输出扫描信号。进一步在本发明实施例提供的显示面板中在采用上述栅极驱动电路，并且还增加了分别连接在第3m+1条栅线与第3m+2条栅线之间的开关器件，以及分别连接在第3m+2条栅线与第3m+3条栅线之间的开关器件，以及与驱动控制电路连接的模式切换电路。这样当模式切换电路在接收到第一模式控制信号时，可以使显示面板实现沿扫描方向以相邻的三条栅线为一栅线组，沿扫描方向各栅线组依次接收扫描信号，即使显示面板的分辨率降低为1/3分辨率，从而可以使显示面板降低功耗，延长待机时间。
附图说明
通过结合附图对本发明的优选实施例进行详细描述，本发明的上述和其他目的、特性和优点将会变得更加清楚，其中相同的标号指定相同结构的单元，并且在其中：
图1为现有的移位寄存器的结构示意图；
图2为本发明实施例提供的移位寄存器的结构示意图；
图3为本发明实施例提供的选择输出单元的具体结构示意图；
图4为本发明实施例提供的移位寄存器的具体结构示意图；
图5为图4所示的移位寄存器对应的输入输出时序图；
图6为本发明实施例提供的栅极驱动电路的结构示意图；
图7a和图7b分别为本发明实施例提供的显示面板的结构示意图；
图8a为本发明实施例提供的第一栅极驱动电路的结构示意图；
图8b为图8a所示的第一栅极驱动电路对应的输入输出时序图；
图9a为本发明实施例提供的显示面板的结构示意图；
图9b为当模式切换电路在接收到第一模式控制信号时显示面板的结构示意图；
图10a为本发明实施例提供的显示面板中当模式切换电路接收到第一模式控制信号时或第三模式控制信号时控制驱动控制电路输出的四组时序控制信号的时序图；
图10b为本发明实施例提供的显示面板中当模式切换电路接收到第一模式控制信号时所对应的栅线上的扫描信号时序图；
图11为本发明实施例提供的显示面板中当模式切换电路接收到第二模式控制信号时所对应的栅线上的扫描信号时序图；
图12a为本发明实施例提供的显示面板中当模式切换电路接收到第三模式控制信号时控制驱动控制电路输出的四组时序控制信号的时序图；
图12b为本发明实施例提供的显示面板中当模式切换电路接收到第三模式控制信号时所对应的栅线上的扫描信号时序图；
图13a为本发明实施例提供的显示面板中当模式切换电路接收到第四模式控制信号时控制驱动控制电路输出的四组时序控制信号的时序图；
图13b为本发明实施例提供的显示面板中当模式切换电路接收到第四模式控制信号时所对应的栅线上的扫描信号时序图。
具体实施方式
下面将参照示出本发明实施例的附图充分描述本发明。然而，本发明可以以许多不同的形式实现，而不应当认为限于这里所述的实施例。相反，提供这些实施例以便使本公开透彻且完整，并且将向本领域技术人员充分表达本发明的范围。在附图中，为了清楚起见放大了组件。
应当理解，尽管这里可以使用术语第一、第二、第三等描述各个元件、组件和/或部分，但这些元件、组件和/或部分不受这些术语限制。这些术语仅仅用于将元件、组件或部分相互区分开来。因此，下面讨论的第一元件、组件或部分在不背离本发明教学的前提下可以称为第二元件、组件或部分。
除非另有定义，这里使用的所有术语(包括技术和科学术语)具有与本发明所属领域的普通技术人员共同理解的相同含义。还应当理解，诸如在通常字典里定义的那些术语应当被解释为具有与它们在相关技术的上下文中的含义相一致的含义，而不应用理想化或极度形式化的意义来解释，除非这里明确地这样定义。
为了实现一种可以降低功耗的显示面板，本发明实施例提供的显示面板 的栅极驱动电路采用了特殊设计的移位寄存器。下面结合附图，对本发明实施例提供的移位寄存器、显示面板的驱动方法及相关装置的具体实施方式进行详细地说明。
下面先对本发明实施例提供的移位寄存器进行说明。
本发明实施例提供的一种移位寄存器，如图2所示，包括：输入单元1、复位单元2、节点控制单元3、上拉单元4、下拉单元5、输入信号端Input、复位信号端Reset、第一时钟信号端ck1和参考信号端Vref；其中，输入单元1的输出端、复位单元2的输出端、节点控制单元3的第一端、以及上拉单元4的控制端均与第一节点PU相连，节点控制单元3的第二端、下拉单元5的控制端均与第二节点PD相连；上拉单元4的输出端和下拉单元5的输出端均与移位在寄存器的驱动信号输出端Out相连；输入单元1用于在输入信号端Input的控制下控制第一节点PU的电位，复位单元2用于在复位信号端Reset的控制下控制第一节点PU的电位，节点控制单元3用于控制第一节点A和第二节点B的电位，上拉单元4用于在第一节点PU的控制下将第一时钟信号端ck1的信号提供给驱动信号输出端Out，下拉单元5用于在第二节点PD的控制下，将参考信号端Vref的信号提供给驱动信号输出端Out；还包括：选择输出单元6和选择控制信号端EN；其中，
选择输出单元6的第一输入端与第一节点PU相连，第二输入端与第二节点PD相连，第三输入端与选择控制信号端EN相连，输出端作为移位寄存器的选择驱动输出端Output；
选择输出单元6用于在选择控制信号端EN接收到选择控制信号时，其输出端输出与驱动信号输出端Out相同的信号。
本发明实施例提供的上述移位寄存器，相当于在现有的移位寄存器的基础上增加了选择输出单元和选择控制信号端；其中，选择输出单元的第一输入端与第一节点相连，第二输入端与第二节点相连，第三输入端与选择控制信号端相连，输出端与移位寄存器的选择驱动输出端相连；选择输出单元用于在选择控制信号端接收到选择控制信号时，其输出端输出与移位寄存器的驱动信号输出端相同的信号。从而可以通过选择控制信号端和选择输出单元的控制决定选择驱动输出端是否有扫描信号输出。进而在采用上述移位寄存器构成的栅极驱动电路中，可以实现选择性的向部分栅线输出扫描信号。
下面结合具体实施例，对本发明进行详细说明。需要说明的是，本实施 例中是为了更好的解释本公开，但不限制本公开。
较佳地，在本发明实施例提供的上述移位寄存器中，如图3所示，选择输出单元6，具体包括：第一开关晶体管T1、第二开关晶体管T2、第三开关晶体管T3和第四开关晶体管T4；其中，
第一开关晶体管T1，其栅极与第二开关晶体管T2的栅极以及选择控制信号端EN相连，源极与第一节点PU相连，漏极与第三开关晶体管T3的栅极相连；
第二开关晶体管T2，其源极与第二节点PD相连，漏极与第四开关晶体管T4的栅极相连；
第三开关晶体管T3，其源极与第一时钟信号端ck1相连，漏极与选择驱动输出端Output相连；
第四开关晶体管T4，其源极与参考信号端Vref相连，漏极与选择驱动输出端Output相连。
在具体实施时，当第一开关晶体管和第二开关晶体管在选择控制信号端的控制下处于导通状态时，第三开关晶体管的栅极的电位与第一节点的电位相同，第四开关晶体管的栅极的电位与第二节点的电位相同，从而当上拉单元在第一节点的控制下将第一时钟信号端的信号提供给驱动信号输出端的同时，第三开关晶体管同样会将第一时钟信号端的信号提供给选择驱动输出端，当下拉单元在第二节点的控制下将参考信号端的信号提供给驱动信号输出端的同时，第四开关晶体管同样会将参考信号端的信号提供给选择驱动输出端，从而保证选择驱动输出端的信号与驱动信号输出端的信号相同。
具体地，在本发明实施例提供的上述移位寄存器中，第一开关晶体管和第二开关晶体管均为P型晶体管或均为N型晶体管；
第三开关晶体管和第四开关晶体管均为P型晶体管或均为N型晶体管。
较佳地，为了简化制作工艺，在本发明实施例提供的上述移位寄存器中，第一开关晶体管和第二开关晶体管、第三开关晶体管和第四开关晶体管均为P型晶体管或均为N型晶体管。
以上仅是举例说明移位寄存器中选择输出单元的具体结构，在具体实施时，选择输出单元的具体结构不限于本发明实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
具体地，在本发明实施例提供的上述移位寄存器中，节点控制单元具体 用于根据第一节点的电位控制第二节点的电位，根据第二节点的电位控制第一节点的电位，从而通过控制第一节点和第二节点的电位，实现移位寄存器的基本功能。
进一步地，在本发明实施例提供的上述移位寄存器中，输入单元、复位单元、节点控制单元、上拉单元和下拉单元的结构均与现有技术相同，在此不作详述。下面通过一个具体实施例说明，但是不限于此。
实施例一：
具体地，如图4所示，输入单元1可以包括第五开关晶体管T5；复位单元2可以包括第六开关晶体管T6；节点控制单元3可以包括第七开关晶体管T7、第八开关晶体管T8、第九开关晶体管T9和第十开关晶体管T10和第一电容C1；上拉单元4可以包括第十一开关晶体管T11和第二电容C2；下拉单元5可以包括第十二开关晶体管T12；其中，第五开关晶体管T5的栅极与输入信号端Input相连，源极与第一直流信号端VDD相连，漏极与上拉节点PU相连；第六开关晶体管T6的栅极与复位信号端Reset相连，源极与第二直流信号端VSS相连，漏极与第一节点PU相连；第七开关晶体管T7的栅极与源极均与第二时钟信号端ckb1相连，漏极与第二节点PD相连；第八开关晶体管T8的栅极与第二节点PD相连，源极与参考信号端Vref相连，漏极与第一节点PU相连；第九开关晶体管T9的栅极与第一节点PU相连，源极与参考信号端Vref相连，漏极与第二节点PD相连；第十开关晶体管T10的栅极与驱动信号输出端Out相连，源极与参考信号端Vref相连，漏极与第二节点PD相连；第十一开关晶体管T11的栅极与第一节点PU相连，源极与第一时钟信号端ck1相连，漏极与驱动信号输出端Out相连；第十二开关晶体管T12的栅极与第二节点PD相连，源极与参考信号端Vref相连，漏极与驱动信号输出端Out相连；第一电容C1连接于第二节点PD与参考信号端Vref之间；第二电容C2连接于第一节点PU与驱动信号输出端Out之间。
具体地，在图4中所有开关晶体管均为N型晶体管，当然在具体实施时，所有开关晶体管也可以均为P型晶体管，或者部分晶体管为N型晶体管，部分晶体管为P型晶体管，在此不作限定。
具体地，以图4所示的移位寄存器为例对本发明实施例提供的移位寄存器的工作原理进行说明。对应的工作时序图如图5所示，可以分为t1、t2、t3、t4和t5五个阶段。下述描述中以1表示高电位信号，0表示低电位信号。
在第一阶段t1，Input＝1，ck1＝0，ckb1＝1，Reset＝0，EN＝1。
由于Input＝1，第五开关晶体管T1导通，第一节点PU的电位为高电位，第十一开关晶体管T11导通，驱动信号输出端Out的电位为低电位。由于ckb1＝1，第七开关晶体管T7导通，同时由于第一节点PU的电位为高电位，第九开关晶体管T9导通，第二节点PD的电位为低电位。由于EN＝1，第一开关晶体管T1和第二开关晶体管T2导通，第三开关晶体管T3的栅极的电位为高电位，第三开关晶体管T3导通，选择驱动输出端Output的电位为低电位。
在第二阶段t2，Input＝0，ck1＝1，ckb1＝0，Reset＝0，EN＝1。
由于ck1＝1，由于第二电容的自举作用，第一节点PU的电位被进一步拉高，第十一开关晶体管T11导通，驱动信号输出端Out的电位为高电位。由于第一节点PU的电位为高电位，第九开关晶体管T9导通，第二节点PD的电位为低电位。由于驱动信号输出端Out的电位为高电位，第十开关晶体管T10导通，第二节点PD的电位为低电位。由于EN＝1，第一开关晶体管T1导通和第二开关晶体管T2导通，第三开关晶体管T3的栅极的电位为高电位，第三开关晶体管T3导通，选择驱动输出端Output的电位为高电位。
在第三阶段t3，Input＝0，ck1＝0，ckb1＝1，Reset＝1，EN＝1。
由于Reset＝1，第六开关晶体管T1导通，第一节点PU的电位为低电位。由于ckb1＝1，第七开关晶体管T7导通，第二节点PD的电位为高电位，第十二开关晶体管T12导通，驱动信号输出端Out的电位为低电位。由于第二节点PD的电位为高电位，第八开关晶体管T8导通，第一节点PU的电位为低电位。由于EN＝1，第一开关晶体管T1和第二开关晶体管T2导通，第四开关晶体管T4的栅极的电位为高电位，第四开关晶体管T4导通，选择驱动输出端Output的电位为低电位。
在第四阶段t4，Input＝0，ck1＝1，ckb1＝0，Reset＝0，EN＝1。
由于第一电容C1的作用，第二节点PD的电位仍保持为高电位，第十二开关晶体管T12导通，驱动信号输出端Out的电位为低电位。由于第二节点PD的电位为高电位，第八开关晶体管T8导通，第一节点PU的电位为低电位。由于EN＝1，第一开关晶体管T1和第二开关晶体管T2导通，第四开关晶体管T4的栅极的电位为高电位，第四开关晶体管T4导通，选择驱动输出端Output的电位为低电位。
在第五阶段t5，Input＝0，ck1＝0，ckb1＝1，Reset＝0，EN＝1。
由于ckb1＝1，第七开关晶体管T7导通，第二节点PD的电位为高电位，第十二开关晶体管T12导通，驱动信号输出端Out的电位为低电位。由于第二节点PD的电位为高电位，第八开关晶体管T8导通，第一节点PU的电位为低电位。由于EN＝1，第一开关晶体管T1和第二开关晶体管T2导通，第四开关晶体管T4的栅极的电位为高电位，第四开关晶体管T4导通，选择驱动输出端Output的电位为低电位。
之后，移位寄存器一直重复第四阶段和第五阶段，直至输入信号端Input的电位再次变为高电位。
需要说明的是本发明上述实施例中提到的开关晶体管可以是薄膜晶体管(TFT，Thin Film Transistor)，也可以是金属氧化物半导体场效应管(MOS，Metal Oxide Semiconductor)，在此不做限定。在具体实施中，这些开关晶体管的源极和漏极根据晶体管类型以及输入信号的不同，其功能可以互换，在此不做具体区分。
基于同一发明构思，本发明实施例还提供了一种栅极驱动电路，如图6所示，包括级联的多个本发明实施例提供的上述移位寄存器：SR(1)、SR(2)…SR(m)…SR(N-1)、SR(N)(共N个移位寄存器，1≤m≤N)；其中，
除最后一级移位寄存器SR(N)之外，其余每一级移位寄存器SR(m)的驱动信号输出端OUT_m(1≤m≤N)分别与与其相邻的下一级移位寄存器SR(m+1)的输入信号端Input相连；
第一级移位寄存器SR(1)的信号输入端Input用于接收触发信号；
除第一级移位寄存器SR(1)之外，其余每一级移位寄存器SR(m)的驱动信号输出端OUT_m分别与与其相邻的上一级移位寄存器SR(m-1)的复位信号端Reset相连；
各级移位寄存器SR(m)的选择驱动输出端Output_m用于与栅线相连。
上述栅极驱动电路通过各级移位寄存器SR(m)的选择驱动输出端Output_m与对应的栅线gatem连接，用于顺序地向对应的栅线输出扫描信号。
在本发明实施例提供的上述栅极驱动电路中，只有当第m级移位寄存器中的选择输出单元在对应的选择控制信号端的控制下处于导通状态时，第m条栅线上才会有扫描信号输出。当所有级移位寄存器中的选择输出单元均导通时，栅极驱动电路顺序地向对应的栅线输出扫描信号。
进一步地，在本发明实施例提供的上述栅极驱动电路中，如图6所示，一般奇数级移位寄存器的第一时钟信号端ck1与偶数级移位寄存器的第二时钟信号端ckb1用于接收同一时钟信号(图中表示为CK1)，奇数级移位寄存器的第二时钟信号端ckb1与偶数级移位寄存器的第一时钟信号端ck1用于接收同一时钟信号(图中表示为CKB1)。
基于同一发明构思，本发明实施例还提供了一种显示面板，如图7a和图7b所示，包括4N条栅线(gate1、gate2、gate3…)，位于显示面板一侧的第一栅极驱动电路GOA1和第三栅极驱动电路GOA3，位于显示面板另一侧的第二栅极驱动电路GOA2和第四栅极驱动电路GOA4；其中，第一栅极驱动电路GOA1、第二栅极驱动电路GOA2、第三栅极驱动电路GOA3和第四栅极驱动电路GOA4均为本发明实施例提供的上述栅极驱动电路；
其中，第一栅极驱动电路GOA1中各级移位寄存器的选择驱动输出端分别与第4n+1条栅线(gate1、gate5、gate9…)连接，第二栅极驱动电路GOA2中各级移位寄存器的选择驱动输出端分别与第4n+2条栅线(gate2、gate6、gate10…)连接，第三栅极驱动电路GOA3中各级移位寄存器的选择驱动输出端分别与第4n+3条栅线(gate3、gate7、gate11…)连接，第四栅极驱动电路GOA4中各级移位寄存器的选择驱动输出端分别与第4n+4条栅线(gate4、gate8、gate12…)连接；其中，n为大于且等于0且小于N的整数；
显示面板还包括：与各栅极驱动电路(GOA1、GOA2、GOA3和GOA4)连接的至少用于向各栅极驱动电路(GOA1、GOA2、GOA3和GOA4)输出选择控制信号、以及向第一栅极驱动电路GOA1输出第一组时序控制信号(至少包括第一触发信号STV1、第一时钟信号CK1和第二时钟信号CKB1)，向第二栅极驱动电路GOA2输出的第二组时序控制信号(至少包括第二触发信号STV2、第三时钟信号CK2和第四时钟信号CKB2)，向第三栅极驱动电路GOA3输出第三组时序控制信号(至少包括第三触发信号STV3，第五时钟信号CK3和第六时钟信号CKB3)，向第四栅极驱动电路GOA4输出的第四组时序控制信号(至少包括第四触发信号STV4、第七时钟信号CK4和第八时钟信号CKB4)的驱动控制电路10；其中，各组时序控制信号至少包括触发信号和时钟信号，且各组时序控制信号中触发信号的宽度相同，各栅极驱动电路(GOA1、GOA2、GOA3和GOA4)用于在接收的对应组时序控制信号的控制下依次由驱动信号输出端输出扫描信号。
下面通以第一栅极驱动电路GOA1为例，具体说明一组时序控制信号对一个栅极驱动电路的控制。如图8a所示，驱动控制电路10向第一级移位寄存器SR(1)输入第一触发信号STV1，分别向奇数级移位寄存器的第一时钟信号端ck1和偶数级移位寄存器的第二时钟信号端ckb1输入第一时钟信号CK1，向奇数级移位寄存器的第二时钟信号端ckb1和偶数级移位寄存器的第一时钟信号端ck1输入第二时钟信号CKB1。
当第一级移位寄存器SR(1)收到第一触发信号STV1后，当第一时钟信号端ck1第一次接收到第一时钟信号CK1时驱动信号输出端Out_1输出扫描信号，此时若对应的选择输出单元在选择控制信号端接收到选择控制信号而处于导通状态，则选择驱动输出端Output_1向第1条栅线gate1输出扫描信号，第一级移位寄存器SR(1)驱动信号输出端Out_1输出的扫描信号提供给第二级移位寄存器SR(2)的输入信号端Input；当第二级移位寄存器SR(2)收到第一级移位寄存器SR(1)输出的扫描信号后，当其第一时钟信号端ck1第一次接收到第二时钟信号CKB1驱动信号输出端Out_2输出扫描信号，此时若对应的选择输出单元在选择控制信号端接收到选择控制信号而处于导通状态，则选择驱动输出端Output_2向第5条栅线gate5输出扫描信号，第二级移位寄存器SR(2)驱动信号输出端Out_2输出的扫描信号提供给第三级移位寄存器SR(3)的输入信号端Input；当第三级移位寄存器SR(3)收到第二级移位寄存器SR(2)输出的扫描信号后，当其第一时钟信号端ck1接收到第一时钟信号CK1时驱动信号输出端Out_3输出扫描信号，此时若对应的选择输出单元在选择控制信号端接收到选择控制信号而处于导通状态，则选择驱动输出端Output_3向第9条栅线gate9输出扫描信号，第三级移位寄存器SR(3)驱动信号输出端Out_3输出的扫描信号提供给第四级移位寄存器SR(4)的输入信号端Input，依次类推，各级移位寄存器依次向对应的栅线输出扫描信号。具体第一栅极驱动电路对应的输入输出时序图如图8b所示。
具体地，驱动控制电路向第二栅极驱动电路的第一级移位寄存器输入第二触发信号，分别向奇数级移位寄存器的第一时钟信号端和偶数级移位寄存器的第二时钟信号端输入第三时钟信号，向奇数级移位寄存器的第二时钟信号端和偶数级移位寄存器的第一时钟信号端输入第四时钟信号。驱动控制电路向第三栅极驱动电路的第一级移位寄存器输入第三触发信号，分别向奇数级移位寄存器的第一时钟信号端和偶数级移位寄存器的第二时钟信号端输入 第五时钟信号，向奇数级移位寄存器的第二时钟信号端和偶数级移位寄存器的第一时钟信号端输入第六时钟信号。驱动控制电路向第四栅极驱动电路的第一级移位寄存器输入第四触发信号，分别向奇数级移位寄存器的第一时钟信号端和偶数级移位寄存器的第二时钟信号端输入第七时钟信号，向奇数级移位寄存器的第二时钟信号端和偶数级移位寄存器的第一时钟信号端输入第八时钟信号。
第二栅极驱动电路、第三栅极驱动电路和第四栅极驱动电路的具体工作原理与第一栅极驱动电路的工作原理相同，在此不作赘述。
较佳地，在本发明实施例提供的上述显示面板中，如图9a所示，还包括：与驱动控制电路10连接的模式切换电路20；针对每一个m的取值，分别连接在第3m+1条栅线与第3m+2条栅线之间的开关器件30；以及针对每一个m的取值，分别连接在第3m+2条栅线与第3m+3条栅线之间的开关器件30；且各开关器件30均与模式切换电路20连接；其中，m为大于且等于0的整数；模式切换电路20用于在接收到第一模式控制信号时：
使第二组时序控制信号(至少包括第二触发信号STV2、第三时钟信号CK2和第四时钟信号CKB2)中各信号的时序比第一组时序控制信号(至少包括第一触发信号STV1、第一时钟信号CK1和第二时钟信号CKB1)中对应信号的时序延迟二分之一个触发信号宽度；使第三组时序控制信号(至少包括第三触发信号STV3，第五时钟信号CK3和第六时钟信号CKB3)中各信号的时序比第二组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；使第四组时序控制信号(至少包括第四触发信号STV4、第七时钟信号CK4和第八时钟信号CKB4)中各信号的时序比第三组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度，具体四组时序控制信号时序图如图10a所示；目的是为了使各级移位寄存的驱动信号输出端依次有扫描信号输出；
并且控制驱动控制电路向与第3m+1条栅线连接的移位寄存器的选择控制信号端均输出选择控制信号，或控制驱动控制电路向与第3m+2条栅线连接的移位寄存器的选择控制信号端均输出选择控制信号，或控制驱动控制电路向与第3m+3条栅线连接的移位寄存器的选择控制信号端均输出选择控制信号；目的是为了使各栅极驱动电路仅向第3m+1条栅线，或第3m+2条栅线或第3m+3条栅线依次输出扫描信号；以控制驱动控制电路10向与第3m+2 条栅线gate3m+2连接的移位寄存器的选择控制信号端均输出选择控制信号为例，说明栅极驱动电路向与第3m+1条栅线，与第3m+2条栅线连接的移位寄存器的选择控制信号端输出选择控制信号，则与第3m+1条栅线连接的移位寄存器和与第3m+2条栅线连接的移位寄存器是可以输出扫描信号的，如图9b所示，栅线起始端为黑点表示栅极驱动电路中移位寄存器的选择控制信号端是有选择控制信号的，对应的选择驱动输出端是可以输出扫描信号的，栅线起始端为圆圈表示栅极驱动电路中移位寄存器的选择控制信号端是没有选择控制信号的，对应的选择驱动输出端是不输出扫描信号的；
控制所有的开关器件30处于导通状态；从而使第3m+1条栅线与第3m+2条栅线导通，使第3m+2条栅线与第3m+3条栅线导通；目的是为了使第3m+1条栅线与第3m+2条栅线以及第3m+3条栅线上的扫描信号相同，从而实现沿扫描方向以相邻的三条栅线为一栅线组，各栅线组依次接收扫描信号，即显示面板是以三条栅线同时扫描的，显示面板的分辨率降低为1/3分辨率。
具体地，本发明实施例提供的上述显示面板，当模式切换电路接收到第一模式控制信号时，以控制驱动控制电路10向与第3m+2条栅线gate3m+2连接的移位寄存器的选择控制信号端均输出选择控制信号为例，沿扫描方向显示面板上各栅线上扫描信号的时序图如图10b所示。
本发明实施例提供的上述显示面板，与现有的显示面板相比，在各移位寄存器中增加了选择输出单元，并且还增加了分别连接在第3m+1条栅线与第3m+2条栅线之间的开关器件，以及分别连接在第3m+2条栅线与第3m+3条栅线之间的开关器件，以及与驱动控制电路连接的模式切换电路。这样当模式切换电路在接收到第一模式控制信号时，可以使显示面板实现沿扫描方向以相邻的三条栅线为一栅线组，沿扫描方向各栅线组依次接收扫描信号，即使显示面板的分辨率降低为1/3分辨率，从而可以使显示面板降低功耗，延长待机时间。
需要说明的是，分别连接在第3m+1条栅线与第3m+2条栅线之间的开关器件，以及分别连接在第3m+1条栅线与第3m+2条栅线之间的开关器件是指来在第1条栅线(m＝1)与第2条栅线(m＝1)之间设置有开关器件，在第2条栅线(m＝1)与第3条栅线(m＝1)之间设置有开关器件；在第4条栅线(m＝2)与第5条栅线(m＝2)之间设置有开关器件，在第5条栅线(m＝2)与第5条栅线(m＝2)之间设置有开关器件；依次类推，即仅在第3x(x为大于0 的整数)条栅线与第3x+1条栅线之间不设置开关器件，其它相邻栅线之间均设置有开关器件。
进一步地，在本发明实施例提供的上述显示面板中，模式切换电路还用于在接收到第二模式控制信号时：
控制所有的开关器件处于关闭状态；目的是为了保证各栅线的信号之间互相不影响；
控制驱动控制电路向所有移位寄存器的选择控制信号端均输出选择控制信号；目的是为了使各移位寄存器的选择驱动输出端与对应的驱动信号输出端的信号相同；
使第二组时序控制信号中各信号的时序比第一组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；使第三组时序控制信号中各信号的时序比第二组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；使第四组时序控制信号中各信号的时序比第三组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度，(即模式切换电路在接收到第二模式控制信号时控制控制驱动控制电路输出的四组时序控制信号，与模式切换电路在接收到第一模式控制信号时控制控制驱动控制电路输出的四组时序控制信号相同)；具体时序图如图10a所示，即目的是为了使各级移位寄存的驱动信号输出端依次有扫描信号输出，从而实现沿扫描方向逐行扫描的功能，即显示面板具有较高的分辨率。这样本发明实施例提供的上述显示面板，不仅可以在需要省电的时候，设置为低分辨率显示，并且可以在不需要省电的时候实现高分辨率显示。
具体地，本发明实施例提供的上述显示面板，当模式切换电路接收到第二模式控制信号时，沿扫描方向显示面板上各栅线上扫描信号的时序图如图11所示。
进一步地，在本发明实施例提供的上述显示面板中，模式切换电路还用于，在接收到第三模式控制信号时：
控制所有的开关器件处于关闭状态；目的是为了保证各栅线的信号之间互相不影响；
控制驱动控制电路向所有移位寄存器的选择控制信号端均输出选择控制信号；目的是为了使各移位寄存器的选择驱动输出端与对应的驱动信号输出端的信号相同；
使第一组时序控制信号中各信号的时序与第二组时序控制信号中对应信号的时序相同，使第三组时序控制信号中各信号的时序与第四组时序控制信号中对应信号的时序相同，并且使第三组时序控制信号中各信号的时序比第一组时序控制信号中对应信号的时序延迟一个触发信号宽度；具体时序图如图12a所示；目的是为了实现沿扫描方向以相邻的两条栅线为一栅线组，沿扫描方向各栅线组依次接收扫描信号，即显示面板是以两条栅线同时扫描的，显示面板的分辨率降低为1/2分辨率。
具体地，本发明实施例提供的上述显示面板，当模式切换电路接收到第三模式控制信号时，沿扫描方向显示面板上各栅线上扫描信号的时序图如图12b所示。
进一步地，在本发明实施例提供的上述显示面板中，模式切换电路还用于，在接收到第四模式控制信号时：
控制所有的开关器件处于关闭状态；目的是为了保证各栅线的信号之间互相不影响；
控制驱动控制电路向所有移位寄存器的选择控制信号端均输出选择控制信号；目的是为了使各移位寄存器的选择驱动输出端与对应的驱动信号输出端的信号相同；
使第一组时序控制信号中各信号的时序与第二组时序控制信号中对应信号的时序、第三组时序控制信号中对应信号的时序、以及第四组时序控制信号中对应信号的时序均相同；具体时序图如图13a所示；目的是为了实现沿扫描方向以相邻的四条栅线为一栅线组，沿扫描方向各栅线组依次接收扫描信号，即显示面板是以四条栅线同时扫描的，显示面板的分辨率降低为1/4分辨率。
具体地，本发明实施例提供的上述显示面板，当模式切换电路接收到第四模式控制信号时，沿扫描方向显示面板上各栅线上扫描信号的时序图如图13b所示。
进一步地，本发明实施例提供的上述显示面板，开关器件可以是开关晶体管，也可以是其它电子开关控制模块，在此不作限定。
需要说明的是，在本发明实施例提供的显示面板中，第一模式控制信号、第二模式控制信号、第三模式控制信号和第四模式控制信号中，各模式控制信号的维持时长是扫描4N条栅线所用的时长的整数倍，且任意两个模式控 制信号之间的切换点与扫描栅线的起始点同步。
具体地，本发明实施例提供的上述显示面板，通过在移位寄存器中设置选择输出单元，在栅线之间增加开关器件，以及控制四组时序控制信号的时序达到降低分辨率，虽然本发明实施例只是给出了四种情况，但是基于上述思想得到的实现1/5分辨、1/6分辨等的显示面板也属于本发明的保护范围。
在具体实施时，在本发明实施例提供的上述显示面板，使用者可以根据实际需求通过该显示面板的操作界面向模式切换电路发送模式控制信号，在此不作限定。
进一步地，发明实施例提供的上述显示面板，既可以是液晶显示面板，也可以是有机电致发光显示面板，在此不作限定。
基于同一发明构思，本发明实施例还提供了一种显示装置，包括本发明实施例提供的上述任一种显示面板。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置的实施可以参见上述显示面板的实施例，重复之处不再赘述。
基于同一发明构思，本发明实施例还提供了上述显示面板的驱动方法，包括：
当模式切换电路在接收到第一模式控制信号时：控制所有的开关器件处于导通状态；使第二组时序控制信号中各信号的时序比第一组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；使第三组时序控制信号中各信号的时序比第二组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；使第四组时序控制信号中各信号的时序比第三组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；并且控制驱动控制电路向与第3m+1条栅线连接的移位寄存器的选择控制信号端均输出选择控制信号，或控制驱动控制电路向与第3m+2条栅线连接的移位寄存器的选择控制信号端均输出选择控制信号，或控制驱动控制电路向与第3m+3条栅线连接的移位寄存器的选择控制信号端均输出选择控制信号；
或者，当模式切换电路在接收到第二模式控制信号时：控制所有的开关器件处于关闭状态；使第二组时序控制信号中各信号的时序比第一组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；使第三组时序控制信号中各信号的时序比第二组时序控制信号中对应信号的时序延迟二分之一 个触发信号宽度；使第四组时序控制信号中各信号的时序比第三组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；并且控制驱动控制电路向所有移位寄存器的选择控制信号端均输出选择控制信号；
或者，当模式切换电路在接收到第三模式控制信号时：控制所有的开关器件处于关闭状态；一组时序控制信号中各信号的时序与第二组时序控制信号中对应信号的时序相同，使第三组时序控制信号中各信号的时序与第四组时序控制信号中对应信号的时序相同，并且使第三组时序控制信号中各信号的时序比第一组时序控制信号中对应信号的时序延迟一个触发信号宽度；并且控制驱动控制电路向所有移位寄存器的选择控制信号端均输出选择控制信号；
或者，当模式切换电路在接收到第四模式控制信号时：控制所有的开关器件处于关闭状态；使第一组时序控制信号中各信号的时序与第二组时序控制信号中对应信号的时序、第三组时序控制信号中对应信号的时序、以及第四组时序控制信号中对应信号的时序均相同；并且控制驱动控制电路向所有移位寄存器的选择控制信号端均输出选择控制信号。
本发明实施例提供的一种移位寄存器、显示面板的驱动方法及相关装置，移位寄存器相当于在现有的移位寄存器的基础上增加了选择输出单元和选择控制信号端；选择输出单元用于在选择控制信号端接收到选择控制信号时，其输出端输出与移位寄存器的驱动信号输出端相同的信号。从而可以通过选择控制信号端和选择输出单元的控制决定选择驱动输出端是否有扫描信号输出。进而在采用上述移位寄存器构成的栅极驱动电路中，可以实现选择性的向部分栅线输出扫描信号。进一步在本发明实施例提供的显示面板中在采用上述栅极驱动电路，并且还增加了分别连接在第3m+1条栅线与第3m+2条栅线之间的开关器件，以及分别连接在第3m+2条栅线与第3m+3条栅线之间的开关器件，以及与驱动控制电路连接的模式切换电路。这样当模式切换电路在接收到第一模式控制信号时，可以使显示面板实现沿扫描方向以相邻的三条栅线为一栅线组，沿扫描方向各栅线组依次接收扫描信号，即使显示面板的分辨率降低为1/3分辨率，从而可以使显示面板降低功耗，延长待机时间。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。
本申请要求于2015年08月06日递交的中国专利申请第201510477072.X号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (11)

  1. 一种移位寄存器，包括：输入单元、复位单元、节点控制单元、上拉单元、下拉单元、输入信号端、复位信号端、第一时钟信号端和参考信号端；其中，所述输入单元的输出端、所述复位单元的输出端、所述节点控制单元的第一端、以及所述上拉单元的控制端均与第一节点相连，所述节点控制单元的第二端和下拉单元的控制端均与第二节点相连；所述上拉单元的输出端和所述下拉单元的输出端均与所述移位在寄存器的驱动信号输出端相连；所述输入单元用于在输入信号端的控制下控制所述第一节点的电位，所述复位单元用于在复位信号端的控制下控制所述第一节点的电位，所述节点控制单元用于控制所述第一节点和所述第二节点的电位，所述上拉单元用于在所述第一节点的控制下将第一时钟信号端的信号提供给驱动信号输出端，所述下拉单元用于在所述第二节点的控制下，将参考信号端的信号提供给所述提供给驱动信号输出端；还包括：选择输出单元和选择控制信号端；其中，
    所述选择输出单元的第一输入端与所述第一节点相连，第二输入端与所述第二节点相连，第三输入端与选择控制信号端相连，输出端作为所述移位寄存器的选择驱动输出端；
    所述选择输出单元用于在所述选择控制信号端接收到选择控制信号时，其输出端输出与所述移位寄存器的驱动信号输出端相同的信号。
  2. 如权利要求1所述的移位寄存器，其中，所述选择输出单元，具体包括：第一开关晶体管、第二开关晶体管、第三开关晶体管和第四开关晶体管；其中，
    所述第一开关晶体管，其栅极与所述第二开关晶体管的栅极以及所述选择控制信号端相连，源极与所述第一节点相连，漏极与所述第三开关晶体管的栅极相连；
    所述第二开关晶体管，其源极与所述第二节点相连，漏极与所述第四开关晶体管的栅极相连；
    所述第三开关晶体管，其源极与所述第一时钟信号端相连，漏极与所述选择驱动输出端相连；
    所述第四开关晶体管，其源极与所述参考信号端相连，漏极与所述选择驱动输出端相连。
  3. 如权利要求2所述的移位寄存器，其中，所述第一开关晶体管和第二开关晶体管均为P型晶体管或均为N型晶体管；
    所述第三开关晶体管和所述第四开关晶体管均为P型晶体管或均为N型晶体管。
  4. 一种栅极驱动电路，包括级联的多个如权利要求1-3任一项所述的移位寄存器；其中，
    除最后一级移位寄存器之外，其余每一级移位寄存器的驱动信号输出端分别与与其相邻的下一级移位寄存器的输入信号端相连；
    第一级移位寄存器的信号输入端用于接收触发信号；
    除第一级移位寄存器之外，其余每一级移位寄存器的驱动信号输出端分别与与其相邻的上一级移位寄存器的复位信号端相连；
    各级移位寄存器的选择驱动输出端用于与栅线相连。
  5. 一种显示面板，包括4N条栅线，位于所述显示面板一侧的第一栅极驱动电路和第三栅极驱动电路，位于显示面板另一侧的第二栅极驱动电路和第四栅极驱动电路；其中:所述第一栅极驱动电路、所述第二栅极驱动电路、所述第三栅极驱动电路和所述第四栅极驱动电路均为如权利要求4所述的栅极驱动电路；
    其中，所述第一栅极驱动电路中各级移位寄存器的选择驱动输出端分别与第4n+1条栅线连接，所述第二栅极驱动电路中各级移位寄存器的选择驱动输出端分别与第4n+2条栅线连接，所述第三栅极驱动电路中各级移位寄存器的选择驱动输出端分别与第4n+3条栅线连接，所述第四栅极驱动电路中各级移位寄存器的选择驱动输出端分别与第4n+4条栅线连接；其中，n为大于且等于0且小于N的整数；
    所述显示面板还包括：与各栅极驱动电路连接的至少用于向各栅极驱动电路输出选择控制信号、以及向所述第一栅极驱动电路输出第一组时序控制信号，向所述第二栅极驱动电路输出的第二组时序控制信号，向所述第三栅极驱动电路输出第三组时序控制信号，向所述第四栅极驱动电路输出的第四组时序控制信号的驱动控制电路；其中，各组时序控制信号至少包括触发信号和时钟信号，且各组时序控制信号中触发信号的宽度相同，各所述栅极驱动电路用于在接收的对应组时序控制信号的控制下依次由驱动信号输出端输出扫描信号。
  6. 如权利要求5所述的显示面板，还包括：与所述驱动控制电路连接的模式切换电路；针对每一个m的取值，分别连接在第3m+1条栅线与第3m+2条栅线之间的开关器件；以及针对每一个m的取值，分别连接在第3m+2条栅线与第3m+3条栅线之间的开关器件；且各所述开关器件均与所述模式切换电路连接；其中，m为大于且等于0的整数；所述模式切换电路用于在接收到第一模式控制信号时：
    控制所有的开关器件处于导通状态；
    使所述第二组时序控制信号中各信号的时序比所述第一组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；使所述第三组时序控制信号中各信号的时序比所述第二组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；使所述第四组时序控制信号中各信号的时序比所述第三组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；
    并且控制所述驱动控制电路向与第3m+1条栅线连接的移位寄存器的选择控制信号端均输出选择控制信号，或控制所述驱动控制电路向与第3m+2条栅线连接的移位寄存器的选择控制信号端均输出选择控制信号，或控制所述驱动控制电路向与第3m+3条栅线连接的移位寄存器的选择控制信号端均输出选择控制信号。
  7. 如权利要求6所述的显示面板，其中，所述模式切换电路还用于在接收到第二模式控制信号时：
    控制所有的开关器件处于关闭状态；
    使所述第二组时序控制信号中各信号的时序比所述第一组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；使所述第三组时序控制信号中各信号的时序比所述第二组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；使所述第四组时序控制信号中各信号的时序比所述第三组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；
    并且控制所述驱动控制电路向所有移位寄存器的选择控制信号端均输出选择控制信号。
  8. 如权利要求7所述的显示面板，其中，所述模式切换电路还用于，在接收到第三模式控制信号时：
    控制所有的开关器件处于关闭状态；
    使所述第一组时序控制信号中各信号的时序与所述第二组时序控制信号 中对应信号的时序相同，使所述第三组时序控制信号中各信号的时序与所述第四组时序控制信号中对应信号的时序相同，并且使所述第三组时序控制信号中各信号的时序比所述第一组时序控制信号中对应信号的时序延迟一个触发信号宽度；
    并且控制所述驱动控制电路向所有移位寄存器的选择控制信号端均输出选择控制信号。
  9. 如权利要求8所述的显示面板，其中，所述模式切换电路还用于，在接收到第四模式控制信号时：
    控制所有的开关器件处于关闭状态；
    使所述第一组时序控制信号中各信号的时序与所述第二组时序控制信号中对应信号的时序、所述第三组时序控制信号中对应信号的时序、以及所述第四组时序控制信号中对应信号的时序均相同；
    并且控制所述驱动控制电路向所有移位寄存器的选择控制信号端均输出选择控制信号。
  10. 一种显示装置，包括如权利要求5-9任一项所述的显示面板。
  11. 一种如权利要求9所述的显示面板的驱动方法，包括：
    当所述模式切换电路在接收到第一模式控制信号时：控制所有的开关器件处于导通状态；使所述第二组时序控制信号中各信号的时序比所述第一组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；使所述第三组时序控制信号中各信号的时序比所述第二组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；使所述第四组时序控制信号中各信号的时序比所述第三组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；并且控制所述驱动控制电路向与第3m+1条栅线连接的移位寄存器的选择控制信号端均输出选择控制信号，或控制所述驱动控制电路向与第3m+2条栅线连接的移位寄存器的选择控制信号端均输出选择控制信号，或控制所述驱动控制电路向与第3m+3条栅线连接的移位寄存器的选择控制信号端均输出选择控制信号；
    或者，当所述模式切换电路在接收到第二模式控制信号时：控制所有的开关器件处于关闭状态；使所述第二组时序控制信号中各信号的时序比所述第一组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；使所述第三组时序控制信号中各信号的时序比所述第二组时序控制信号中对应信 号的时序延迟二分之一个触发信号宽度；使所述第四组时序控制信号中各信号的时序比所述第三组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；并且控制所述驱动控制电路向所有移位寄存器的选择控制信号端均输出选择控制信号；
    或者，当所述模式切换电路在接收到第三模式控制信号时：控制所有的开关器件处于关闭状态；一组时序控制信号中各信号的时序与所述第二组时序控制信号中对应信号的时序相同，使所述第三组时序控制信号中各信号的时序与所述第四组时序控制信号中对应信号的时序相同，并且使所述第三组时序控制信号中各信号的时序比所述第一组时序控制信号中对应信号的时序延迟一个触发信号宽度；并且控制所述驱动控制电路向所有移位寄存器的选择控制信号端均输出选择控制信号；
    或者，当所述模式切换电路在接收到第四模式控制信号时：控制所有的开关器件处于关闭状态；使所述第一组时序控制信号中各信号的时序与所述第二组时序控制信号中对应信号的时序、所述第三组时序控制信号中对应信号的时序、以及所述第四组时序控制信号中对应信号的时序均相同；并且控制所述驱动控制电路向所有移位寄存器的选择控制信号端均输出选择控制信号。
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US20170178582A1 (en) 2017-06-22
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