WO2021189492A1 - 栅极驱动电路及其驱动方法、显示面板 - Google Patents

栅极驱动电路及其驱动方法、显示面板 Download PDF

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Publication number
WO2021189492A1
WO2021189492A1 PCT/CN2020/081875 CN2020081875W WO2021189492A1 WO 2021189492 A1 WO2021189492 A1 WO 2021189492A1 CN 2020081875 W CN2020081875 W CN 2020081875W WO 2021189492 A1 WO2021189492 A1 WO 2021189492A1
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WIPO (PCT)
Prior art keywords
shift register
switch unit
terminal
control signal
stage
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PCT/CN2020/081875
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English (en)
French (fr)
Inventor
白枭
杨盛际
卢鹏程
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/260,254 priority Critical patent/US11600224B2/en
Priority to PCT/CN2020/081875 priority patent/WO2021189492A1/zh
Priority to CN202080000410.XA priority patent/CN113906492B/zh
Priority to EP20897641.5A priority patent/EP4131228A4/en
Publication of WO2021189492A1 publication Critical patent/WO2021189492A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a gate driving circuit and a driving method thereof, and a display panel.
  • the display panel displays images in a manner of sequentially displaying one frame after another. Due to the mutual interference between frames, the display panel usually causes dynamic blur when displaying images.
  • a black picture is usually inserted between the frame and the frame display to improve the problem of image dynamic blur.
  • the method of inserting the black picture will reduce the display time of one frame of the picture, thereby causing problems such as image flicker and low display brightness.
  • a gate driving circuit applied to a display panel, the display panel including a plurality of rows of pixel units
  • the gate driving circuit includes: a plurality of shift register units, a switch unit group ,
  • the shift register units are arranged in cascade, the output terminal of the previous stage shift register unit is connected to the input terminal of the adjacent next stage shift register unit, each of the shift register units and at least one row of pixel units are arranged correspondingly ,
  • the switch unit group includes: a first switch unit, a second switch unit Two switch unit.
  • the first switch unit is connected to the output terminal of the previous stage shift register unit, and is adjacent to the input terminal of the next stage shift register unit, for responding to a control signal to turn on the output terminal and phase of the previous stage shift register unit.
  • Adjacent to the input end of the next-stage shift register unit; the second switch unit is connected to the output end of the upper-stage shift register unit, adjacent to the output end of the next-stage shift register unit, for responding to a control signal to turn on The output terminal of the previous stage shift register unit and the output terminal of the adjacent next stage shift register unit; wherein, the first switch unit and the second switch unit are turned on alternatively during the driving period.
  • the first switch unit is further connected to a control signal terminal for responding to the signal of the control signal terminal to turn on the output terminal of the previous stage shift register unit and the adjacent next stage.
  • the input terminal of the shift register unit of the stage; the second switch unit is also connected to the control signal terminal for responding to the signal of the control signal terminal to turn on the output terminal of the shift register unit of the previous stage and the adjacent lower
  • each of the shift register units corresponds to a row of pixel units, and is used to provide an enable signal to the corresponding row of pixel units.
  • each of the shift register units corresponds to multiple rows of pixel units, and is used to provide an enable signal to the corresponding multiple rows of pixel units.
  • one switch unit group is arranged between each adjacent shift register, wherein the Nth stage switch unit group is arranged between the Nth stage shift register unit and the N+1th stage Between shift register units, N is a positive integer greater than or equal to 1.
  • the number of shift register units is m*2 n , where m is a positive integer greater than or equal to 2, and n is a positive integer greater than or equal to 1, and the km+M level switch
  • the unit group is commonly connected to the first control signal terminal, k is a positive integer greater than or equal to 0, M is a positive integer less than m and greater than 0, and km+M is less than or equal to m*2 n ;
  • the second q *m+2 q+ 1 *m*p level switch unit group is commonly connected to the q+2 control signal terminal; where q and p are positive integers greater than or equal to 0, and 2 q *m+2 q+1 *m*p is less than or equal to m* 2 n .
  • the first control signal terminal and the q+2th control signal terminal form the control signal terminal.
  • m is equal to 2
  • n is equal to 2
  • the first-level switch unit group, the third-level switch unit group, the fifth-level switch unit group, and the seventh-level switch unit group are commonly connected to the first Control signal terminal
  • the second-level switch unit group and the sixth-level switch unit group are commonly connected to the second control signal terminal
  • the fourth-level switch unit group is connected to the third control signal terminal.
  • each shift register unit is connected to a plurality of enable signal lines, and each of the plurality of enable signal lines is used to provide the enable signal to a row of pixel units. Signal.
  • the gate driving circuit further includes: a first power terminal, a plurality of third switch units, and the plurality of third switch units are arranged in a one-to-one correspondence with the shift register unit,
  • the third switch unit is connected to the first power terminal and the output terminal of the shift register unit, and at least one enable signal line is used to transmit the first power terminal in response to a signal from the output terminal of the shift register unit To the at least one enable signal line; wherein at least one of the enable signal lines is used to provide the enable signal to a row of pixel units.
  • the number of rows of pixel units corresponding to each shift register unit is the same.
  • multiple rows of pixel units corresponding to the same shift register unit are arranged adjacently.
  • the first switch unit is a P-type transistor, and the second switch unit is an N-type transistor;
  • the first switch unit is an N-type transistor
  • the second switch unit is a P-type transistor
  • the first switch unit is a P-type transistor, the gate of the first switch unit is connected to the control signal terminal, and the first pole is connected to the upper stage of the shift register unit.
  • the output terminal, the second pole is connected to the input terminal of the adjacent next-stage shift register unit;
  • the second switch unit is an N-type transistor, the gate of the second switch unit is connected to the control signal terminal, the first pole is connected to the output terminal of the previous stage shift register unit, and the second pole is connected to the adjacent next stage.
  • the first switch unit is an N-type transistor, the gate of the first switch unit is connected to the control signal terminal, the first pole is connected to the output terminal of the shift register unit of the previous stage, and the second pole is connected to the adjacent The input terminal of the next stage shift register unit;
  • the second switch unit is a P-type transistor, the gate of the second switch unit is connected to the control signal terminal, the first pole is connected to the output terminal of the previous stage shift register unit, and the second pole is connected to the adjacent next stage.
  • the output terminal of the stage shift register unit is a P-type transistor, the gate of the second switch unit is connected to the control signal terminal, the first pole is connected to the output terminal of the previous stage shift register unit, and the second pole is connected to the adjacent next stage.
  • the third switch unit is a switch transistor, the gate of the third switch unit is connected to the output terminal of the shift register unit, and the first pole is connected to the first power supply Terminal, the second pole is connected to the at least one enable signal line.
  • a gate driving circuit driving method for driving the above-mentioned gate driving circuit which includes:
  • the first switch unit or the second switch unit of the same switch unit group is selectively turned on.
  • the driving method includes:
  • the first initial signal is input to the input terminal of the first stage shift register, and the first logic level is input to the first control signal terminal, the second control signal terminal, and the third control signal terminal to guide Turn on the first switch unit in the first to seventh stage switch unit group, while turning off the second switch unit in the first to seventh stage switch unit group;
  • a second initial signal is input to the input terminal of the first stage shift register, and a second logic level is input to the first control signal terminal to turn on the first stage switch unit group and the third stage switch
  • the second switch unit in the unit group, the fifth-level switch unit group, and the seventh-level switch unit group simultaneously inputs the first logic level to the second control signal terminal and the third control signal terminal to turn on the second-level switch
  • the third initial signal is input to the input terminal of the first stage shift register, and the second logic level is input to the first control signal terminal and the second control signal terminal to turn on the first stage switching unit Group, the third-level switch unit group, the fifth-level switch unit group, the seventh-level switch unit group, the second-level switch unit group, the second-level switch unit group, the second switch unit in the sixth-level switch unit group, at the same time to the third control signal terminal Input the first logic level to turn on the first switch unit in the fourth-stage switch unit group;
  • the fourth initial signal is input to the input terminal of the first stage shift register, and the second logic level is input to the first control signal terminal, the second control signal terminal, and the third control signal terminal to guide
  • the second switch unit in the first to seventh stage switch unit groups is turned on, and the first switch unit in the first to seventh stage switch unit groups is turned off at the same time.
  • a display panel including the above-mentioned gate driving circuit.
  • the display panel is a silicon-based OLED display panel.
  • the silicon-based OLED display panel includes: a display area, a first dummy area, a detection area, a second dummy area, a cathode ring area, a third dummy area, and a first driving circuit integration Zone, second drive circuit integration zone.
  • the first virtual area is located on one side of the display area; the detection area is located on the side of the first virtual area away from the display area; the second virtual area is located at a side of the detection area away from the display area.
  • the cathode ring area located on the side of the second virtual area away from the display area; the third virtual area, located on the side of the cathode ring area away from the display area; the first driver circuit integration area, located The third dummy area is far away from the display area and is used to integrate a first gate drive circuit, the first gate drive circuit is used to generate a gate drive signal; the second drive circuit integration area is located in the The first driving circuit integration area is on a side far away from the display area, and is used to integrate the above-mentioned gate driving circuit.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit of the present disclosure
  • FIG. 2 is a timing diagram of some nodes in an exemplary embodiment of the pixel driving circuit of FIG. 1;
  • FIG. 3 is a timing diagram of some nodes in another exemplary embodiment of the pixel driving circuit of FIG. 1;
  • FIG. 4 is a schematic structural diagram of an exemplary embodiment of the gate driving circuit of the present disclosure.
  • FIG. 5 is a timing diagram of each node of the gate driving circuit of the present disclosure.
  • Figure 6 is a display state diagram of the display panel in the T1 time period
  • Figure 7 is a diagram of the display state of the display panel in the T2 time period
  • FIG. 8 is a timing diagram of each node of the gate driving circuit shown in FIG. 4 in a second driving state
  • Fig. 9 is a display state diagram of the display panel in the T1 time period
  • Figure 10 is a diagram of the display state of the display panel in the T2 time period
  • FIG. 11 is a timing diagram of each node of the gate driving circuit shown in FIG. 4 in a third driving state
  • Figure 12 is a display state diagram of the display panel in the T1 time period
  • Figure 13 is a display state diagram of the display panel in the T2 time period
  • FIG. 14 is a timing diagram of each node of the gate driving circuit shown in FIG. 4 in a fourth driving state
  • 15 is a schematic structural diagram of a shift register unit in an exemplary embodiment of the gate driving circuit of the present disclosure
  • 16 is a timing diagram of some nodes in an exemplary embodiment of the shift register unit in FIG. 15;
  • FIG. 17 is a schematic structural diagram of another exemplary embodiment of the gate driving circuit of the present disclosure.
  • FIG. 18 is a schematic structural diagram of another exemplary embodiment of the gate driving circuit of the present disclosure.
  • 19 is a schematic structural diagram of another exemplary embodiment of the gate driving circuit of the present disclosure.
  • 20 is a timing diagram of each node of the gate driving circuit of FIG. 19 in the first driving state
  • FIG. 21 is a timing diagram of each node of the gate driving circuit of FIG. 19 in the first driving state
  • FIG. 22 is a timing diagram of each node of the gate driving circuit of FIG. 19 in the first driving state
  • FIG. 23 is a schematic structural diagram of an exemplary embodiment of a silicon-based OLED display panel of the present disclosure.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit of the present disclosure.
  • FIG. 2 is a timing diagram of some nodes in an exemplary embodiment of the pixel driving circuit of FIG. 1.
  • the pixel driving circuit may include a first P-type transistor T1, a second N-type transistor T2, a driving transistor DT, a third P-type transistor T3, a fourth N-type transistor T4, a capacitor C, and a light-emitting unit OLED.
  • the control terminal of the first P-type transistor T1 is connected to the second control terminal G2, the first terminal is connected to the data signal terminal Data, and the second terminal is connected to the node G; the control terminal of the second N-type transistor T2 is connected to the first control terminal G1, The terminal is connected to the data signal terminal Data, the second terminal is connected to the node G; the control terminal of the third P-type transistor T3 is connected to the enable signal terminal EM, the first terminal is connected to the node S, and the second terminal is connected to the first power supply VDD; the fourth N-type The control terminal of the transistor T4 is connected to the reset signal terminal Reset, the first terminal is connected to the initialization signal terminal Vinit, and the second terminal is connected to the node S; the control terminal of the driving transistor DT is connected to the node G, the first terminal is connected to the node S, and the light-emitting power source OLED is connected to the second power source Between the terminal VSS and the second terminal of the driving transistor DT; the capacitor is connected between the ground terminal
  • the driving method of the pixel driving circuit includes: a reset phase, a data writing phase, and a light emitting phase.
  • the reset phase T1 the reset signal terminal Reset is at a high level
  • the fourth N-type transistor T4 is turned on under the action of the reset signal terminal Reset at the high level, so that the initial signal terminal Vinit resets the node S.
  • the data writing stage T2 the data signal terminal Data is a high-level signal
  • the first control terminal G1 is a high-level signal
  • the second control terminal G2 is a low-level signal
  • the enable signal terminal EM is a high-level signal.
  • the third P-type transistor T3 is turned off under the effect of the high level of the enable signal terminal EM, the first P-type transistor T1 is turned on under the effect of the low level of the second control terminal G2, and the second N-type transistor T2 is in the first control
  • the terminal G1 is turned on under the action of the high level to transmit the high level signal of the data signal terminal Data to the node G and store it in the capacitor C; in the light-emitting phase T3, the enable signal terminal EM is a low level signal,
  • the triple P-type transistor T3 is turned on under the effect of the low level of the enable signal terminal EM, so that the light-emitting unit OLED emits light.
  • the signal of the enable signal terminal EM can adjust the light-emitting duration of the pixel unit.
  • FIG. 3 it is a timing diagram of some nodes in another exemplary embodiment of the pixel driving circuit of FIG. 1.
  • the enable signal EM can be continuously at a high level, so that the light-emitting unit OLED is in the off state, and the black screen can be inserted between frames by controlling the duration of T4.
  • the enable signal received by each pixel drive circuit remains high.
  • each pixel unit does not Lights, the display panel is in the black insertion stage; when the last row of pixel units completes the data writing stage, the enable signal received by each pixel drive circuit turns to a low level. At this time, all pixel units of the display panel emit light at the same time, and display The panel is in the light-emitting stage.
  • the actual light-emitting time of the display panel is relatively small. This causes problems such as flickering of the image on the display panel and low display brightness.
  • the exemplary embodiment provides a gate driving circuit.
  • FIG. 4 it is a schematic structural diagram of an exemplary embodiment of the gate driving circuit of the present disclosure.
  • the gate driving circuit can be applied to a display panel.
  • the display panel includes multiple rows of pixel units, and the gate driving circuit may include 8 shift register units GOA1-GOA8 and 7 switch unit groups. 8 shift register units are arranged in cascade, the output terminal Out of the previous shift register unit is connected to the input terminal Input of the adjacent next stage shift register unit; among them, the output terminal Out of each shift register unit can be connected with A plurality of rows of the pixel units are correspondingly arranged so as to simultaneously input an enable signal to the plurality of rows of the pixel units.
  • a switch unit group can be arranged between each adjacent shift register unit; wherein, the Nth stage switch unit group is arranged between the Nth stage shift register unit and the N+1th stage shift register unit.
  • the first-level switch unit group includes a first switch unit M11 and a second switch unit M12
  • the second-level switch unit group includes a first switch unit M21 and a second switch unit M22
  • the third-level switch unit group includes a first switch.
  • the unit M31 and the second switch unit M32, the fourth-stage switch unit group includes the first switch unit M41 and the second switch unit M42, the fifth-stage switch unit group includes the first switch unit M51 and the second switch unit M52, the sixth stage The switch unit group includes a first switch unit M61 and a second switch unit M62, and the seventh-stage switch unit group includes a first switch unit M71 and a second switch unit M72.
  • Each switch unit group is correspondingly connected to a control signal terminal, the first-level switch unit group, the third-level switch unit group, the fifth-level switch unit group, and the seventh-level switch unit group are connected to the first control signal terminal SW1; the second The first-level switch unit group and the sixth-level switch unit group are commonly connected to the second control signal terminal SW2; the fourth-level switch unit group is connected to the third control signal terminal SW3.
  • the first switch unit in each switch unit group is connected to the output terminal Out of the previous stage shift register unit, the input terminal Input of the adjacent next stage shift register unit, and the control signal terminal for responding to the control
  • the signal at the signal terminal turns on the output terminal of the previous stage shift register unit and the input terminal of the adjacent next stage shift register unit
  • the second switch unit in each switch unit group is connected to the previous stage shift register unit
  • the output terminal Out of the next stage shift register unit, the output terminal Out of the adjacent next stage shift register unit, and the control signal terminal are used to respond to the signal of the control signal terminal to turn on the output terminal of the previous stage shift register unit and the adjacent The output terminal of the shift register unit of the next stage; wherein, the conduction level logic of the first switch unit and the second switch unit are opposite.
  • the same row of pixel units may refer to pixel units connected to the same gate line.
  • each shift register unit may be connected to a plurality of enable signal lines EM line, and each of the enable signal lines EM line is used to transmit to a row of pixel units. Provide the enable signal.
  • the number of enable signal lines connected to each shift register unit can be the same, and the enable signal lines connected to the same shift register unit can be arranged adjacently.
  • the conduction level logic of the first switch unit and the second switch unit may also be the same.
  • the first switch unit and the second switch unit may be at different control signal terminals. Select one to turn on under the action.
  • the driving period is the driving period of the gate driving circuit.
  • the first switch units M11, M21, M31, M41, M51, M61, and M71 may be N-type transistors
  • the second switch units M12, M22, M32, M42, M52, M62 and M72 can be P-type transistors.
  • the first switch units M11, M21, M31, M41, M51, M61, M71 may also be P-type transistors
  • the second switch units M12, M22, M32, M42, M52 , M62, M72 can also be N-type transistors.
  • the gate drive circuit shown in Figure 4 can be switched in four operating modes.
  • the first driving mode the first initial signal can be input to the input terminal Input of the first stage shift register, and the first logic level can be input to the first control signal terminal, the second control signal terminal, and the third control signal terminal. So as to turn on the first switch unit in the first to seventh stage switch unit groups, and at the same time turn off the second switch unit in the first to seventh stage switch unit groups.
  • the first logic level may be a high level.
  • the first mode as shown in FIG.
  • Out5 is the timing diagram of the output terminal of the fifth-stage shift register unit GOA5 Figure;
  • Out6 is the timing diagram of the output terminal of the sixth stage shift register unit GOA6;
  • Out7 is the timing diagram of the output terminal of the seventh stage shift register unit GOA7;
  • Out8 is the timing diagram of the output terminal of the eighth stage shift register unit GOA8.
  • the first-stage shift register unit GOA outputs a high-level signal under the action of the initialization signal, as shown in Figure 6, which is the display state diagram of the display panel in the T1 time period, where GOAn is the shift from the nth stage.
  • the bit register unit corresponds to the connected pixel unit area.
  • the pixel units in the GOA1 area receive a high-level enable signal. Therefore, the pixel units in the GOA1 area do not emit light during the T1 time period (that is, the GOA1 area is blacked out). As shown in FIG.
  • FIG. 7 it is a display state diagram of the display panel in the T2 time period, where GOAn is the pixel unit area connected to the n-th stage shift register unit.
  • GOAn is the pixel unit area connected to the n-th stage shift register unit.
  • the second-stage shift register unit outputs a high-level signal
  • the pixel unit corresponding to the second-stage shift register unit receives a high-level enable signal.
  • the pixel unit in the GOA2 area No light (that is, the GOA2 area is inserted black).
  • the second initial signal is input to the input terminal Input of the first stage shift register, and the second logic level is input to the first control signal terminal to turn on the first stage switch unit group and the third stage.
  • the second switch unit in the switch unit group, the fifth-level switch unit group, and the seventh-level switch unit group turn off the first-level switch unit group, the third-level switch unit group, the fifth-level switch unit group, and the seventh-level switch
  • the first switch unit in the unit group at the same time input the first logic level to the second control signal terminal and the third control signal terminal to turn on the second level switch unit group, the sixth level switch unit group, and the fourth level switch
  • the first switch unit in the unit group turns off the second switch unit in the second level switch unit group, the sixth level switch unit group, and the fourth level switch unit group.
  • the first logic level is a high level
  • the second logic level is a low level.
  • the input terminals of the second-stage shift register GOA2, the fourth-stage shift register GOA4, and the sixth-stage shift register GOA6 cannot receive the output signal of the previous-stage shift register. Therefore, the second The shift register GOA2, the fourth-stage shift register GOA4, and the sixth-stage shift register GOA6 do not output shift signals.
  • the first-stage shift register unit can provide a multi-row pixel unit corresponding to the second-stage shift register unit.
  • the third-stage shift register unit can also send a multi-row pixel unit corresponding to the fourth-stage shift register unit Provides an enable signal; since the input end of the fifth-stage shift register unit is connected to the output end of the sixth-stage shift register unit, the fifth-stage shift register unit can also transfer multiple rows corresponding to the sixth-stage shift register unit
  • the pixel unit provides an enable signal; since the input end of the seventh-stage shift register unit is connected to the output end of the eighth-stage shift register unit, the seventh-stage shift register unit can also send the signal corresponding to the eighth-stage shift register unit. Multiple rows of pixel units provide enable signals.
  • FIG. 8 it is a timing diagram of each node of the gate driving circuit shown in FIG. 4 in the second driving state, where Out1 is the timing diagram of the output terminal of the first-stage shift register unit GOA1; Out2 is the second-stage shift The timing diagram of the output terminal of the bit register unit GOA2; Out3 is the timing diagram of the output terminal of the third stage shift register unit GOA3; Out4 is the timing diagram of the output terminal of the fourth stage shift register unit GOA4; Out5 is the output terminal of the fifth stage shift register unit GOA5 Out6 is the timing diagram of the output terminal of the sixth-stage shift register unit GOA6; Out7 is the timing diagram of the output terminal of the seventh-stage shift register unit GOA7; Out8 is the timing diagram of the output terminal of the eighth-stage shift register unit GOA8.
  • the output terminal of the first stage shift register unit GOA1 outputs a high level signal.
  • the first-stage shift register unit outputs a high-level signal
  • the pixel units corresponding to the first-stage shift register unit and the second-stage shift register unit receive the high-level enable signal.
  • the pixel units in the GOA1 and GOA2 regions do not emit light (that is, the GOA1 and GOA2 regions are inserted in black).
  • FIG. 10 it is a display state diagram of the display panel in the T2 time period, where GOAn is the pixel unit area connected to the n-th stage shift register unit.
  • the third-stage shift register unit outputs a high-level signal
  • the pixel units corresponding to the third-stage shift register unit and the fourth-stage shift register unit are connected to the pixel unit to receive the high-level enable signal.
  • the pixel units in the GOA3 and GOA4 regions do not emit light (that is, the GOA3 and GOA4 regions are inserted in black).
  • the pixel units corresponding to the fifth-stage shift register unit and the sixth-stage shift register unit do not emit light (that is, in the T3 time period, the GOA5 and GOA6 areas are inserted in black), and in the T4 time period , The pixel units corresponding to the seventh-stage shift register unit and the eighth-stage shift register unit do not emit light (that is, in the T4 period, the GOA7 and GOA8 areas are inserted in black).
  • the third initial signal is input to the input terminal of the first stage shift register, and the second logic level is input to the first control signal terminal and the second control signal terminal to turn on the first stage switching unit Group, the third-level switch unit group, the fifth-level switch unit group, the seventh-level switch unit group, the second-level switch unit group, the second switch unit in the sixth-level switch unit group, turn off the first-level switch unit group ,
  • the first switch unit in the third-level switch unit group, the fifth-level switch unit group, the seventh-level switch unit group, the second-level switch unit group, and the sixth-level switch unit group input to the third control signal terminal at the same time
  • the first logic level is used to turn on the first switch unit in the fourth-level switch unit group and turn off the second switch unit in the fourth-level switch unit group.
  • the first logic level is a high level
  • the second logic level is a low level.
  • only the input end of the fifth-stage shift register unit can receive the signal from the output end of the first-stage shift register unit, the second-stage shift register unit, the third-stage shift register unit, and the fourth-stage shift register unit
  • the stage shift register unit, the sixth stage shift register unit, the seventh stage shift register unit, and the eighth stage shift register unit do not output shift signals.
  • the first-stage shift register unit can also Provide enable signals to the multiple rows of pixel units corresponding to the second-stage shift register unit, the third-stage shift register unit, and the fourth-stage shift register unit; since the output end of the fifth-stage shift register unit is connected to the sixth-stage shift register unit.
  • the multi-row pixel units corresponding to the eighth-stage shift register unit and the eighth-stage shift register unit provide enable signals.
  • FIG. 11 it is a timing diagram of each node of the gate driving circuit shown in FIG. 4 in the third driving state, where Out1 is the timing diagram of the output terminal of the first-stage shift register unit GOA1; Out2 is the second-stage shift The timing diagram of the output terminal of the bit register unit GOA2; Out3 is the timing diagram of the output terminal of the third stage shift register unit GOA3; Out4 is the timing diagram of the output terminal of the fourth stage shift register unit GOA4; Out5 is the output terminal of the fifth stage shift register unit GOA5 Out6 is the timing diagram of the output terminal of the sixth-stage shift register unit GOA6; Out7 is the timing diagram of the output terminal of the seventh-stage shift register unit GOA7; Out8 is the timing diagram of the output terminal of the eighth-stage shift register unit GOA8.
  • the output terminal of the first-stage shift register unit GOA1 outputs a high level signal.
  • the pixel unit area connected to the nth stage shift register unit.
  • the first-stage shift register unit outputs a high-level signal, and the pixel units in the GOA1, GOA2, GOA3, and GOA4 regions receive a high-level enable signal. Therefore, in the T1 period, GOA1, GOA2, GOA3, The pixel units in the GOA4 area do not emit light (that is, in the T1 time period, the GOA1, GOA2, GOA3, and GOA4 areas are inserted in black). As shown in FIG.
  • GOAn is the pixel unit area connected to the n-th stage shift register unit.
  • the fifth-stage shift register unit outputs a high-level signal. Therefore, in the T2 period, the pixel units in the GOA5, GOA6, GOA7, and GOA8 regions do not emit light (that is, in the T2 period, GOA5, GOA6, GOA7 , Insert black in GOA8 area).
  • the fourth initial signal is input to the input terminal of the first stage shift register, and the second logic level is input to the first control signal terminal, the second control signal terminal, and the third control signal terminal to guide
  • the second switch unit in the first to seventh stage switch unit groups is turned on, and the first switch unit in the first to seventh stage switch unit groups is turned off at the same time.
  • the first logic level is a high level
  • the second logic level is a low level.
  • the second-stage shift register unit, the third-stage shift register unit, the fourth-stage shift register unit, the fifth-stage shift register unit, the sixth-stage shift register unit, and the seventh-stage shift register unit The shift register unit and the eighth stage shift register unit will not output shift signals.
  • the first-stage shift register unit can communicate with the second-stage shift register unit, the third-stage shift register unit, and the second-stage shift register unit Multiple rows of pixel units corresponding to the four-stage shift register unit, the fifth-stage shift register unit, the sixth-stage shift register unit, the seventh-stage shift register unit, and the eighth-stage shift register unit provide enable signals.
  • FIG. 14 it is a timing diagram of each node of the gate driving circuit shown in FIG. 4 in the fourth driving state, where Out1 is the timing diagram of the output terminal of the first-stage shift register unit GOA1; Out2 is the second-stage shift The timing diagram of the output terminal of the bit register unit GOA2; Out3 is the timing diagram of the output terminal of the third stage shift register unit GOA3; Out4 is the timing diagram of the output terminal of the fourth stage shift register unit GOA4; Out5 is the output terminal of the fifth stage shift register unit GOA5 Out6 is the timing diagram of the output terminal of the sixth-stage shift register unit GOA6; Out7 is the timing diagram of the output terminal of the seventh-stage shift register unit GOA7; Out8 is the timing diagram of the output terminal of the eighth-stage shift register unit GOA8.
  • the output terminal of the first stage shift register unit GOA1 outputs a high level signal, which is connected with the first stage shift register unit, the second stage shift register unit, the third stage shift register unit, and the fourth stage shift register unit.
  • the output terminals of the shift register unit, the fifth-stage shift register unit, the sixth-stage shift register unit, the seventh-stage shift register unit, and the eighth-stage shift register unit are correspondingly connected to the pixel unit to receive a high-level enable signal , Therefore, the display panel does not emit light in the full screen during the T1 time period.
  • the first shift register unit outputs a low-level signal, which is connected with the first shift register unit, the second shift register unit, the third shift register unit, and the fourth shift register unit.
  • the output terminals of the fifth-stage shift register unit, the sixth-stage shift register unit, the seventh-stage shift register unit, and the eighth-stage shift register unit are connected to the pixel unit to receive the low-level enable signal. Therefore, in T2 The time zone display panel glows in full screen.
  • the fourth driving mode is the frame-to-frame black insertion method described in the related art.
  • the gate driving circuit can control the gate driving circuit to switch between different driving modes through the first control signal terminal, the second control signal terminal, and the third control signal terminal.
  • the gate driving circuit works in the first driving mode, the second driving mode, and the third driving mode
  • the display panel can realize the rolling black insertion, thereby avoiding the technical problem of the dynamic blur of the display panel picture;
  • this rolling black insertion method can increase the light-emitting time of each pixel unit, thereby avoiding problems such as flickering of the display panel image and low display brightness.
  • the first-stage shift register unit needs to output a high-level active duration different, for example, in the first driving mode, the first-stage shift register unit output is active high The duration needs to cover the data writing period of the multiple rows of pixel units corresponding to the first-stage shift register unit; in the second drive mode, the high-level active duration output by the first-stage shift register unit needs to cover the first-stage shift register unit The data writing period of the multiple rows of pixel units corresponding to the first-stage shift register unit and the second-stage shift register unit; in the third driving mode, the high-level effective time of the first-stage shift register unit needs to be Covers the data writing period of multiple rows of pixel units corresponding to the first-stage shift register unit, the second-stage shift register unit, the third-stage shift register unit, and the fourth-stage shift register unit; In the driving mode, the high-level active duration output by the first-stage shift register unit needs to cover the data writing period of all pixel units. Therefore, correspondingly, in different
  • the gate driving circuit may be arranged corresponding to the pixel driving circuit in FIG. 1. It should be understood that in other exemplary embodiments, the gate driving circuit provided by the present disclosure may also be arranged corresponding to other pixel driving circuits.
  • the pixel driving circuit may have a pixel structure such as 2T1C, 7T1C, and so on.
  • FIG. 15 is a schematic structural diagram of a shift register unit in an exemplary embodiment of the gate drive circuit of the present disclosure
  • FIG. 16 is a part of an exemplary embodiment of the shift register unit in FIG. 15
  • the shift register unit includes a fifth transistor T5 to a fourteenth transistor T14, a first capacitor C1 to a third capacitor C3, and an inverter PI.
  • the fifth transistor T5 to the fourteenth transistor T14 may be P-type transistors, the first power signal terminal VGL continues to be low level, and the second power signal terminal VGH continues to be high level.
  • the shift register unit driving mode includes 5 stages.
  • the first clock signal terminal CLK1 is low level
  • the second clock signal terminal CLK2 is high level
  • the input terminal Input is Low level
  • the fifth transistor T5, the sixth transistor T6, and the fourteenth transistor T14 are turned on
  • the second power supply terminal VGH precharges a high level signal to the third capacitor C3, and the output terminal Eout is high level
  • the first clock signal terminal CLK1 is at high level
  • the second clock signal terminal CLK2 is at high level
  • the input terminal Input is at low level
  • the eleventh transistor T11 is turned on
  • the first clock signal terminal charges the capacitor C2 Input a high level signal to turn off the twelfth transistor T12, and the output terminal Eout outputs a high level
  • the third phase T3 the first clock signal terminal CLK1 is high level, and the front part of the second clock signal terminal CLK2 is low Level
  • the input terminal Input is low level
  • the eighth transistor T8 is turned off under the action of the high level of the capacitor C2, and the output terminal E
  • the shift register unit is used to output a shift signal. It should be understood that in other exemplary embodiments, the shift register unit may have more structures to choose from, which belong to The scope of protection of this disclosure.
  • the gate driving circuit may further include: a first power supply terminal VDD and a plurality of third switch units M3, the third switch unit M3 is arranged in a one-to-one correspondence with the shift register unit, and the third switch unit M3 is connected to the The first power supply terminal VDD, the output terminal Out of the shift register unit, and multiple enable signal lines EM line are used to transmit the first power terminal VDD to the output terminal Out of the shift register unit in response to the signal Multiple enable signal lines; wherein each enable signal line is used to provide the enable signal to a row of pixel units.
  • the third switch unit M3 can be an N-type transistor, and this arrangement can enhance the output capability of the gate driving circuit through the first power supply terminal VDD. It should be understood that if the effective level output by the shift register unit is a low level, the third switch unit can be set as a P-type transistor, and the level input to the enable signal line can also be performed through the third switch unit. Logic conversion.
  • the number of switch unit groups may also be other numbers, and it is not necessary to provide a switch unit group between each adjacent shift register unit.
  • FIG. 18 it is a gate drive circuit of the present disclosure.
  • the fifth-stage shift A switch unit group is provided between the register unit and the sixth-stage shift register unit, and between the seventh-stage shift register unit and the eighth-stage shift register unit; the second-stage shift register unit and the third-stage shift register There is no switch unit group between the units, between the fourth-stage shift register unit and the fifth-stage shift register unit, and between the sixth-stage shift register unit and the seventh-stage shift register unit.
  • This exemplary embodiment can control the gate driving circuit to operate in the above-mentioned first driving mode and second driving mode by controlling the logic level output from the first control signal terminal SW1.
  • the gate drive circuit When the first control signal terminal SW1 outputs a high-level signal, the gate drive circuit operates in the above-mentioned first driving mode; when the first control signal terminal SW1 outputs a low-level signal, the gate drive circuit operates in the above-mentioned Work in the second drive mode.
  • the number of shift register units may also be other numbers.
  • the number of shift register units may be m*2 n , where m is a positive integer greater than or equal to 2, and n is greater than or equal to A positive integer of 1, a switch unit group can be arranged between each adjacent shift register; wherein, the Nth stage switch unit group is arranged between the Nth stage shift register unit and the N+1th stage shift register unit.
  • the km+M level switch unit group is connected to the first control signal terminal, k is a positive integer greater than or equal to 0, M is a positive integer less than m and greater than 0, and km+M is less than or equal to m*2 n ; the second q *m+2 q+1 *m*p-level switch unit groups are commonly connected to the q+2 control signal terminal; where q and p are positive integers greater than or equal to 0, and 2 q *m+2 q+1 *m *p is less than or equal to m*2 n .
  • the first-stage switch unit group, the second-stage switch unit group, the fourth-stage switch unit group, the fifth-stage switch unit group, the seventh-stage switch unit group, and the eighth-stage switch Unit group 10th level switch unit group, 11th level switch unit group, 13th level switch unit group, 14th level switch unit group, 16th level switch unit group, 17th level switch unit group,
  • the nineteenth level switch unit group, the twentieth level switch unit group, the 22nd level switch unit group, and the 23rd level switch unit group are jointly connected to the first control signal terminal;
  • Level switch unit group, 15th level switch unit group, 21st level switch unit group are connected to the second control signal terminal; 6th level switch unit group, 18th stage switch unit group are connected to the third control signal terminal ;
  • the twelfth second-level switch unit group is commonly connected to the fourth control signal terminal.
  • the gate driving circuit can realize 5 different driving modes by controlling the signals from the first control signal terminal to the fourth control
  • each shift register unit may be arranged corresponding to a row of pixel units, and each shift register unit is used to provide an enable signal to a row of pixel units.
  • FIG. 19 it is a schematic structural diagram of another exemplary embodiment of the gate driving circuit of the present disclosure.
  • the display panel may include 270 rows of pixel units.
  • the gate driving circuit may include 270 (m*2 n , m equals to 135, n equals to 1) cascaded shift register units.
  • the km+M-level switch unit group is commonly connected to the first control signal end, that is, the control signal end of the first-level switch unit group to the 134th-level switch unit group, and the control signal end of the 136th-level switch unit group to the 269th-level switch unit group.
  • the second q *m+2 q+1 *m*p level switch unit group is commonly connected to the q+2 control signal terminal, that is, the control terminal signal terminal of the 135th level switch unit group is connected to the first Two control signal terminal SW2.
  • the gate drive circuit can work in three drive modes:
  • FIG. 20 it is a timing diagram of each node of the gate drive circuit of FIG. 19 in the first driving state, where Out1 is the timing diagram of the output terminal of the first-stage shift register unit GOA1; Out2 is the second-stage shift register The timing diagram of the output terminal of the unit GOA2; Out3 is the timing diagram of the output terminal of the third stage shift register unit GOA3; ... Out270 is the timing diagram of the output terminal of the 270th stage shift register unit GOA270.
  • both the first control signal terminal and the second control signal terminal input high-level signals, the first switch unit in each switch unit group is turned on, the second switch unit is turned off, and the gate drive
  • Each shift register unit of the circuit outputs a shift signal stage by stage, so that each pixel unit lights up row by row.
  • Out136 is the timing diagram of the output terminal of the 136th stage shift register unit GOA136;
  • Out270 is the output of the 270th stage shift register unit GOA270 Timing diagram of the terminal.
  • the first control signal terminal SW1 inputs a low level signal
  • the second control signal terminal inputs a high level signal
  • the output terminal of the first stage shift register unit to the 135th stage shift register unit is shorted
  • the output terminals of the 136th stage shift register unit to the 270th stage shift register unit are short-circuited.
  • the first stage shift register unit to the 135th stage shift register unit output high level, and the pixel units corresponding to the first stage shift register unit to the 135th stage shift register unit are in the black insertion stage;
  • the first stage shift register unit to the 135th stage shift register unit output low level, and the pixel units corresponding to the first stage shift register unit to the 135th stage shift register unit are in the lighting stage.
  • the 136th stage shift register unit to the 270th stage shift register unit output a high level, and the pixel units corresponding to the 136th stage shift register unit to the 270th stage shift register unit are in the black insertion stage.
  • FIG. 22 it is a timing diagram of each node of the gate driving circuit of FIG. 19 in the first driving state, where Out1 is the timing diagram of the output terminal of the first-stage shift register unit GOA1; Out2 is the second-stage shift register The timing diagram of the output terminal of the unit GOA2; Out3 is the timing diagram of the output terminal of the third stage shift register unit GOA3; ... Out270 is the timing diagram of the output terminal of the 270th stage shift register unit GOA270.
  • both the first control signal terminal and the second control signal terminal input low-level signals, the first switch unit in each switch unit group is turned off, the second switch unit is turned on, and each shift The output terminal of the register unit is short-circuited.
  • each stage of the shift register unit In the T1 period, each stage of the shift register unit outputs a high level, and the display panel does not emit light in the full screen; in the T2 period, each stage of the shift register unit outputs a low level, and the display panel emits light in the full screen.
  • the third driving mode is the frame-to-frame black insertion method described in the related art.
  • the display panel may further include pixel units with other rows, and the switch unit group may also share the control signal terminal in other ways.
  • the display panel may include 1080 rows of pixel units.
  • the gate driving circuit includes 1080 (m*2 n , m equals to 135, n equals to 3) shift register units.
  • the km+M level switch unit group is connected to the first control signal terminal, that is, the first level switch unit group to the 134th level switch unit group, the 136th level switch unit group to the 269th level switch unit group,...
  • the control signal terminal of the 946th switch unit group to the 1079th switch unit group is connected to the first control signal terminal, and the 2nd q *m+2 q+1 *m*p switch unit group is connected to the q+2 control signal terminal in common , That is, the control terminal signal terminals of the 135th level switch unit group, the 405th level switch unit group, the 675th level switch unit group, and the 945th level switch unit group are connected to the second control signal terminal.
  • the control terminal signal terminals of the 270th level switch unit group and the 810th level switch unit group are connected to the third control signal terminal.
  • the control terminal signal terminal of the 540th level switch unit group is connected to the fourth control signal terminal.
  • the gate drive circuit can switch between five drive modes.
  • This exemplary embodiment also provides a gate driving circuit driving method for driving the above-mentioned gate driving circuit, and the driving method includes:
  • the first switch unit or the second switch unit of the same switch unit group is selectively turned on.
  • the first initial signal is input to the input terminal of the first stage shift register, and the first logic level is input to the first control signal terminal, the second control signal terminal, and the third control signal terminal to guide Turn on the first switch unit in the first to seventh stage switch unit group, while turning off the second switch unit in the first to seventh stage switch unit group;
  • a second initial signal is input to the input terminal of the first stage shift register, and a second logic level is input to the first control signal terminal to turn on the first stage switch unit group and the third stage switch
  • the second switch unit in the unit group, the fifth-level switch unit group, and the seventh-level switch unit group simultaneously inputs the first logic level to the second control signal terminal and the third control signal terminal to turn on the second-level switch
  • the third initial signal is input to the input terminal of the first stage shift register, and the second logic level is input to the first control signal terminal and the second control signal terminal to turn on the first stage switching unit Group, the third-level switch unit group, the fifth-level switch unit group, the seventh-level switch unit group, the second-level switch unit group, the second-level switch unit group, the second switch unit in the sixth-level switch unit group, at the same time to the third control signal terminal Input the first logic level to turn on the first switch unit in the fourth-stage switch unit group;
  • the fourth initial signal is input to the input terminal of the first stage shift register, and the second logic level is input to the first control signal terminal, the second control signal terminal, and the third control signal terminal to guide
  • the second switch unit in the first to seventh stage switch unit groups is turned on, and the first switch unit in the first to seventh stage switch unit groups is turned off at the same time.
  • the gate driving circuit driving method provided by this exemplary embodiment has the same technical features and working principles as the above-mentioned gate driving circuit, and the above content has been described in detail, and will not be repeated here.
  • This exemplary embodiment also provides a display panel including the above-mentioned gate driving circuit.
  • the display panel is a silicon-based OLED display panel.
  • the silicon-based OLED display panel can be applied to display devices such as VR/AR.
  • FIG. 23 it is a schematic structural diagram of an exemplary embodiment of a silicon-based OLED display panel of the present disclosure.
  • the silicon-based OLED display panel includes: a display area 1, a first dummy area 2, a detection area 3, a second dummy area 4, a cathode ring area 5, a third dummy area 6, a first driving circuit integration area 7, a second dummy area Drive circuit integration area 8.
  • the display area 1 is integrated with the enable signal line 11; the first virtual area 2 is located around the display area 1; the detection area 3 is located on the side of the first virtual area away from the display area, and is located as shown One or both sides of the display area along the extending direction of the enable signal line 11; the second dummy area 4 is located on the side of the detection area away from the display area; the cathode ring area 5 is located at the second The side of the virtual area away from the display area; the third virtual area 6 is located on the side of the cathode ring area away from the display area; the first driving circuit integration area 7 is located at the third virtual area away from the display area One side of the display area is used to integrate the first gate drive circuit, the first gate drive circuit is used to generate gate drive signals; the second drive circuit integration area 8 is located far away from the first drive circuit integration area One side of the display area is used to integrate the above-mentioned gate driving circuit.
  • a semiconductor with the same structure as that in the display area 1 may be integrated in the first dummy area 1 so that the semiconductor in the display area is far away from the edge area, thereby improving the uniformity of the semiconductor in the display area 1.
  • a detection circuit may be integrated in the detection area 3 to detect the working current of the display panel.
  • the cathode ring area 2 is used to integrate a cathode ring and a pixel drive circuit, and the cathode ring is arranged on the same layer as the common cathode to connect the cathode of the light-emitting unit to the power terminal of the pixel drive circuit through a via hole.
  • Semiconductors are integrated in the second dummy area 4 and the third dummy area 6 to improve the uniformity of the semiconductor in the cathode ring area 2.
  • the detection area 3, the second dummy area 4, the cathode ring area 5, the third dummy area 6, the first driver circuit integration area 7, and the second driver circuit integration area 8 can be arranged on two opposite sides of the display area. side.
  • the detection area 3, the second dummy area 4, the cathode ring area 5, the third dummy area 6, the first driver circuit integration area 7, the second driver circuit integration area 8 are also It can be set on only one side of the display area.

Abstract

一种栅极驱动电路及其驱动方法、显示面板，栅极驱动电路包括多个级联的移位寄存器单元（GOA1,GOA2,GOA3,GOA4,GOA5,GOA6,GOA7,GOA8）、开关单元组。每个移位寄存器单元（GOA1,GOA2,GOA3,GOA4,GOA5,GOA6,GOA7,GOA8）和至少一行像素单元对应设置；至少部分相邻两移位寄存器单元（GOA1,GOA2,GOA3,GOA4,GOA5,GOA6,GOA7,GOA8）之间设置有开关单元组，开关单元组包括第一开关单元（M11,M21,M31,M41,M51,M61,M71）和第二开关单元（M12,M22,M32,M42,M52,M62,M72）。第一开关单元（M11,M21,M31,M41,M51,M61,M71）用于响应一控制信号以导通上一级移位寄存器单元（GOA1,GOA2,GOA3,GOA4,GOA5,GOA6,GOA7,GOA8）的输出端（Out）和相邻下一级移位寄存器单元（GOA1,GOA2,GOA3,GOA4,GOA5,GOA6,GOA7,GOA8）的输入端（Input）；第二开关单元（M12,M22,M32,M42,M52,M62,M72）用于响应一控制信号以导通上一级移位寄存器单元（GOA1,GOA2,GOA3,GOA4,GOA5,GOA6,GOA7,GOA8）的输出端（Out）和相邻下一级移位寄存器单元（GOA1,GOA2,GOA3,GOA4,GOA5,GOA6,GOA7,GOA8）的输出端（Out）；其中，第一开关单元（M11,M21,M31,M41,M51,M61,M71）和第二开关单元（M12,M22,M32,M42,M52,M62,M72）在驱动时段择一导通。

Description

栅极驱动电路及其驱动方法、显示面板 技术领域
本公开涉及显示技术领域，尤其涉及一种栅极驱动电路及其驱动方法、显示面板。
背景技术
显示面板显示图像的方式为一帧一帧画面依次显示，由于帧与帧之间画面的相互干扰，通常会造成显示面板显示画面时出现动态模糊。相关技术中通常在帧与帧显示之间插入黑画面，以改善图像动态模糊的问题，然而，插入黑画面的方式会降低一帧画面的显示时长，从而造成图像闪烁、显示亮度低等问题。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
根据本公开的一个方面，提供一种栅极驱动电路，应用于显示面板，所述显示面板包括多行像素单元，其中，所述栅极驱动电路包括：多个移位寄存器单元、开关单元组，所述移位寄存器单元级联设置，上一级移位寄存器单元的输出端连接相邻下一级移位寄存器单元的输入端，每个所述移位寄存器单元和至少一行像素单元对应设置，用于向与其对应的至少一行所述像素单元输入使能信号；至少部分相邻两移位寄存器单元之间设置有所述开关单元组，所述开关单元组包括：第一开关单元、第二开关单元。第一开关单元连接上一级移位寄存器单元的输出端，相邻下一级移位寄存器单元的输入端，用于响应一控制信号以导通上一级移位寄存器单元的输出端和相邻下一级移位寄存器单元的输入端；第二开关单元连接上一级移位寄存器单元的输出端，相邻下一级移位寄存器单元的输出端，用于响应一控制信号以导通上一级移位寄存器单元的输出端和相邻下一级移位寄存器单元的输出端；其中，所述第一开关单元和第二开关单元在驱动时段择一导通。
本公开的一种示例性实施例中，所述第一开关单元还连接控制信号端，用于响应所述控制信号端的信号以导通上一级移位寄存器单元的输出端和相邻下一级级移位寄存器单元的输入端；所述第二开关单元还连接所述控制信号端，用于响应所述控制信号端的信号以导通上一级移位寄存器单元的输出端和相邻下一级移位寄存器单元 的输出端；其中，所述第一开关单元和第二开关单元的导通电平逻辑相反。
本公开的一种示例性实施例中，每个所述移位寄存器单元对应一行像素单元，用于向与其对应的一行像素单元提供使能信号。
本公开的一种示例性实施例中，每个所述移位寄存器单元对应多行像素单元，用于向与其对应的多行像素单元提供使能信号。
本公开的一种示例性实施例中，每相邻移位寄存器之间设置一所述开关单元组，其中，第N级开关单元组设置于第N级移位寄存器单元和第N+1级移位寄存器单元之间，N为大于等于1的正整数。
本公开的一种示例性实施例中，所述移位寄存器单元为m*2 n个，其中，m为大于等于2的正整数，n为大于等于1的正整数；第km+M级开关单元组共同连接第一控制信号端，k为大于等于0的正整数，M为小于m且大于0的正整数，且km+M小于等于m*2 n；第2 q*m+2 q+1*m*p级开关单元组共同连接第q+2控制信号端；其中，q、p为大于等于0的正整数，且2 q*m+2 q+1*m*p小于等于m*2 n。所述第一控制信号端、第q+2控制信号端形成所述控制信号端。
本公开的一种示例性实施例中，m等于2、n等于2；第一级开关单元组、第三级开关单元组、第五级开关单元组、第七级开关单元组共同连接第一控制信号端；第二级开关单元组、第六级开关单元组共同连接第二控制信号端；第四级开关单元组连接第三控制信号端。
本公开的一种示例性实施例中，每个移位寄存器单元的输出端连接多条使能信号线，所述多条使能信号线的每一条用于向一行像素单元提供所述使能信号。
本公开的一种示例性实施例中，所述栅极驱动电路还包括：第一电源端、多个第三开关单元，多个第三开关单元与所述移位寄存器单元一一对应设置，所述第三开关单元连接所述第一电源端、所述移位寄存器单元的输出端，至少一条使能信号线，用于响应所述移位寄存器单元的输出端的信号将第一电源端传输到所述至少一条使能信号线；其中，至少一条所述使能信号线用于向一行像素单元提供所述使能信号。
本公开的一种示例性实施例中，每个移位寄存器单元所对应的像素单元行数相同。
本公开的一种示例性实施例中，与同一移位寄存器单元对应的多行像素单元相邻设置。
本公开的一种示例性实施例中，所述第一开关单元为P型晶体管，所述第二开关单元为N型晶体管；
或，所述第一开关单元为N型晶体管，所述第二开关单元为P型晶体管。
本公开的一种示例性实施例中，所述第一开关单元为P型晶体管，所述第一开关单元的栅极连接所述控制信号端，第一极连接上一级移位寄存器单元的输出端，第二 极连接相邻下一级移位寄存器单元的输入端；
所述第二开关单元为N型晶体管，所述第二开关单元的栅极连接所述控制信号端，第一极连接上一级移位寄存器单元的输出端，第二极连接相邻下一级移位寄存器单元的输出端；
或，所述第一开关单元为N型晶体管，所述第一开关单元的栅极连接所述控制信号端，第一极连接上一级移位寄存器单元的输出端，第二极连接相邻下一级移位寄存器单元的输入端；
所述第二开关单元为P型晶体管，所述第二开关单元的栅极连接所述控制信号端，第一极连接上一级移位寄存器单元的输出端，第二极连接相邻下一级移位寄存器单元的输出端。
本公开的一种示例性实施例中，所述第三开关单元为开关晶体管，所述第三开关单元的栅极连接所述移位寄存器单元的输出端，第一极连接所述第一电源端，第二极连接所述至少一条使能信号线。
根据本公开的一个方面，提供一种栅极驱动电路驱动方法，用于驱动上述的栅极驱动电路，其中，包括：
在驱动时段，择一导通同一开关单元组的第一开关单元或第二开关单元。
本公开的一种示例性实施例中，m＝2，n＝2，所述驱动方法包括：
在第一驱动模式下，向第一级移位寄存器的输入端输入第一初始信号，向第一控制信号端、第二控制信号端、第三控制信号端输入第一逻辑电平，以导通第一到第七级开关单元组中的第一开关单元，同时关闭第一到第七级开关单元组中的第二开关单元；
在第二驱动模式下，向第一级移位寄存器的输入端输入第二初始信号，向第一控制信号端输入第二逻辑电平，以导通第一级开关单元组、第三级开关单元组、第五级开关单元组、第七级开关单元组中的第二开关单元，同时向第二控制信号端、第三控制信号端输入第一逻辑电平，以导通第二级开关单元组、第六级开关单元组、第四级开关单元组中的第一开关单元；
在第三驱动模式下，向第一级移位寄存器的输入端输入第三初始信号，向第一控制信号端、第二控制信号端输入第二逻辑电平，以导通第一级开关单元组、第三级开关单元组、第五级开关单元组、第七级开关单元组、第二级开关单元组、第六级开关单元组中的第二开关单元，同时向第三控制信号端输入第一逻辑电平，以导通第四级开关单元组中的第一开关单元；
在第四驱动模式下，向第一级移位寄存器的输入端输入第四初始信号，向第一控制信号端、第二控制信号端、第三控制信号端输入第二逻辑电平，以导通第一到第七级开关单元组中的第二开关单元，同时关闭第一到第七级开关单元组中的第一开关单 元。
根据本公开的一个方面，提供一种显示面板，其包括上述的栅极驱动电路。
本公开的一种示例性实施例中，所述显示面板为硅基OLED显示面板。
本公开的一种示例性实施例中，所述硅基OLED显示面板包括：显示区、第一虚拟区、检测区、第二虚拟区、阴极环区、第三虚拟区、第一驱动电路集成区、第二驱动电路集成区。第一虚拟区，位于所述显示区的一侧；检测区，位于所述第一虚拟区远离所述显示区的一侧；第二虚拟区，位于所述检测区远离所述显示区的一侧；阴极环区，位于所述第二虚拟区远离所述显示区的一侧；第三虚拟区，位于所述阴极环区远离所述显示区的一侧；第一驱动电路集成区，位于所述第三虚拟区远离所述显示区的一侧，用于集成第一栅极驱动电路，所述第一栅极驱动电路用于生成栅极驱动信号；第二驱动电路集成区，位于所述第一驱动电路集成区远离所述显示区的一侧，用于集成上述的栅极驱动电路。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一种像素驱动电路的结构示意图；
图2为图1像素驱动电路一种示例性实施例中部分节点的时序图；
图3为图1像素驱动电路另一种示例性实施例中部分节点的时序图；
图4为本公开栅极驱动电路一种示例性实施例的结构示意图；
图5为本公开栅极驱动电路各个节点的时序图；
图6为显示面板在T1时间段的显示状态图；
图7为显示面板在T2时间段的显示状态图；
图8为图4所示栅极驱动电路在第二驱动状态下各个节点的时序图；
图9为显示面板在T1时间段的显示状态图；
图10为在T2时间段显示面板的显示状态图；
图11为图4所示栅极驱动电路在第三驱动状态下各个节点的时序图；
图12为显示面板在T1时间段的显示状态图；
图13为显示面板在T2时间段的显示状态图；
图14为图4所示栅极驱动电路在第四驱动状态下各个节点的时序图；
图15为本公开栅极驱动电路一种示例性实施例中移位寄存器单元的结构示意图；
图16为图15中移位寄存器单元一种示例性实施例中部分节点的时序图；
图17为本公开栅极驱动电路另一种示例性实施例的结构示意图；
图18为本公开栅极驱动电路另一种示例性实施例的结构式示意图；
图19为本公开栅极驱动电路另一种示例性实施例的结构式示意图；
图20为图19栅极驱动电路在第一驱动状态下各个节点的时序图；
图21为图19栅极驱动电路在第一驱动状态下各个节点的时序图；
图22为图19栅极驱动电路在第一驱动状态下各个节点的时序图；
图23所为本公开硅基OLED显示面板一种示例性实施例的结构示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
用语“一个”、“一”、“该”和“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”和“第二”等仅作为标记使用，不是对其对象的数量限制。
如图1、2所示，图1为本公开一种像素驱动电路的结构示意图。图2为图1像素驱动电路一种示例性实施例中部分节点的时序图。该像素驱动电路可以包括第一P 型晶体管T1、第二N型晶体管T2，驱动晶体管DT，第三P型晶体管T3、第四N型晶体管T4、电容C、发光单元OLED。第一P型晶体管T1的控制端连接第二控制端G2，第一端连接数据信号端Data，第二端连接节点G；第二N型晶体管T2的控制端连接第一控制端G1，第一端连接数据信号端Data，第二端连接节点G；第三P型晶体管T3的控制端连接使能信号端EM，第一端连接节点S，第二端连接第一电源VDD；第四N型晶体管T4控制端连接复位信号端Reset，第一端连接初始化信号端Vinit，第二端连接节点S；驱动晶体管DT控制端连接节点G，第一端连接节点S，发光电源OLED连接于第二电源端VSS和驱动晶体管DT第二端之间；电容连接于接地端GND和节点G之间。该像素驱动电路的驱动方法包括：复位阶段、数据写入阶段、发光阶段。如图2所示，在复位阶段T1：复位信号端Reset为高电平，第四N型晶体管T4在复位信号端Reset高电平作用下导通，以使初始信号端Vinit对节点S复位。在数据写入阶段T2：数据信号端Data为高电平信号，第一控制端G1为高电平信号，第二控制端G2为低电平信号，使能信号端EM为高电平信号，第三P型晶体管T3在使能信号端EM高电平作用下关断，第一P型晶体管T1在第二控制端G2低电平作用下导通，第二N型晶体管T2在第一控制端G1高电平作用下导通，以将数据信号端Data的高电平信号传输到节点G，并存储在电容C内；在发光阶段T3，使能信号端EM为低电平信号，第三P型晶体管T3在使能信号端EM低电平作用下导通，以使发光单元OLED发光。使能信号端EM的信号可以调节像素单元的发光时长。例如，如图3所示，为图1像素驱动电路另一种示例性实施例中部分节点的时序图。在T4时段使能信号EM可以持续为高电平，从而使得发光单元OLED处于关闭状态，通过控制T4的时长可以实现在帧与帧之间插入黑画面。具体的，从显示面板第一行像素单元的复位阶段到最后一行像素单元的数据写入阶段，每个像素驱动电路接收的使能信号保持高电平，在该时间段，每个像素单元不发光，该显示面板处于插黑阶段；当最后一行像素单元完成数据写入阶段后，每个像素驱动电路接收的使能信号转变为低电平，此时，显示面板所有像素单元同时发光，显示面板处于发光阶段。
然而，由于显示面板的刷新频率、IC响应时间、每行像素单元复位阶段和补偿阶段时长(复位阶段和补偿阶段可以合称为数据写入阶段)等限制，显示面板的实际发光时长较小，从而造成显示面板图像闪烁、显示亮度低等问题。
基于此，本示例性实施例提供一种栅极驱动电路，如图4所示，为本公开栅极驱动电路一种示例性实施例的结构示意图，该栅极驱动电路可以应用于显示面板，所述显示面板包括多行像素单元，所述栅极驱动电路可以包括8个移位寄存器单元GOA1-GOA8和7个开关单元组。8个移位寄存器单元级联设置，上一级移位寄存器单元的输出端Out连接相邻下一级移位寄存器单元的输入端Input；其中，每个移位寄存器单元的输出端Out可以和多行所述像素单元对应设置，以向多行所述像素单元 同时输入使能信号。每相邻移位寄存器单元之间可以设置一开关单元组；其中，第N级开关单元组设置于第N级移位寄存器单元和第N+1级移位寄存器单元之间。其中，第一级开关单元组包括第一开关单元M11和第二开关单元M12，第二级开关单元组包括第一开关单元M21和第二开关单元M22，第三级开关单元组包括第一开关单元M31和第二开关单元M32，第四级开关单元组包括第一开关单元M41和第二开关单元M42，第五级开关单元组包括第一开关单元M51和第二开关单元M52，第六级开关单元组包括第一开关单元M61和第二开关单元M62，第七级开关单元组包括第一开关单元M71和第二开关单元M72。每个开关单元组对应连接一控制信号端，第一级开关单元组、第三级开关单元组、第五级开关单元组、第七级开关单元组共同连接第一控制信号端SW1；第二级开关单元组、第六级开关单元组共同连接第二控制信号端SW2；第四级开关单元组连接第三控制信号端SW3。每个开关单元组中的第一开关单元连接上一级移位寄存器单元的输出端Out、相邻下一级移位寄存器单元的输入端Input、所述控制信号端，用于响应所述控制信号端的信号以导通上一级移位寄存器单元的输出端和相邻下一级级移位寄存器单元的输入端；每个开关单元组中的第二开关单元连接上一级移位寄存器单元的输出端Out、相邻下一级移位寄存器单元的输出端Out、所述控制信号端，用于响应所述控制信号端的信号以导通上一级移位寄存器单元的输出端和相邻下一级移位寄存器单元的输出端；其中，所述第一开关单元和第二开关单元的导通电平逻辑相反。其中，同一行像素单元可以指连接于同一条栅线的像素单元。
如图4所示，本示例性实施例中，每个移位寄存器单元的输出端Out可以连接多条使能信号线EM line，每条所述使能信号线EM line用于向一行像素单元提供所述使能信号。其中，每个移位寄存器单元连接的使能信号线条数可以相同，且连接于同一移位寄存器单元的使能信号线可以相邻设置。在其他示例性实施例中，所述第一开关单元和第二开关单元的导通电平逻辑也可以相同，在驱动时段，所述第一开关单元和第二开关单元可以在不同控制信号端作用下择一导通。驱动时段即为该栅极驱动电路的驱动时段。
本示例性实施例中，如图4所示，第一开关单元M11、M21、M31、M41、M51、M61、M71可以为N型晶体管，第二开关单元M12、M22、M32、M42、M52、M62、M72可以为P型晶体管。应该理解的是，在其他示例性实施例中，第一开关单元M11、M21、M31、M41、M51、M61、M71还可以为P型晶体管，第二开关单元M12、M22、M32、M42、M52、M62、M72还可以为N型晶体管。
图4所示的栅极驱动电路可以在四种工作模式下切换。在第一驱动模式下，可以向第一级移位寄存器的输入端Input输入第一初始信号，向第一控制信号端、第二控制信号端、第三控制信号端输入第一逻辑电平，以导通第一到第七级开关单元组中的 第一开关单元，同时关闭第一到第七级开关单元组中的第二开关单元。其中，第一逻辑电平可以为高电平。在第一模式下，如图5所示，为本公开栅极驱动电路各个节点的时序图，其中，Out1为第一级移位寄存器单元GOA1输出端的时序图；Out2为第二级移位寄存器单元GOA2输出端的时序图；Out3为第三级移位寄存器单元GOA3输出端的时序图；Out4为第四级移位寄存器单元GOA4输出端的时序图；Out5为第五级移位寄存器单元GOA5输出端的时序图；Out6为第六级移位寄存器单元GOA6输出端的时序图；Out7为第七级移位寄存器单元GOA7输出端的时序图；Out8为第八级移位寄存器单元GOA8输出端的时序图。多个移位寄存器单元依次移位输出高电平信号。在T1时间段，第一级移位寄存器单元GOA在初始化信号作用下输出高电平信号，如图6所示，为显示面板在T1时间段的显示状态图，其中GOAn为与第n级移位寄存器单元对应连接的像素单元区域。在T1时间段，GOA1区域的像素单元接收高电平的使能信号，因此，在T1时间段GOA1区域的像素单元不发光(即GOA1区域插黑)。如图7所示，为显示面板在T2时间段的显示状态图，其中GOAn为与第n级移位寄存器单元连接的像素单元区域。在T2时间段，第二级移位寄存器单元输出高电平信号，与第二级移位寄存器单元对应连接的像素单元接收高电平的使能信号，在T2时间段，GOA2区域的像素单元不发光(即GOA2区域插黑)。依次类推，在第一驱动模式下，与移位寄存器单元对应的各个像素区域依次滚动插黑。
在第二驱动模式下，向第一级移位寄存器的输入端Input输入第二初始信号，向第一控制信号端输入第二逻辑电平，以导通第一级开关单元组、第三级开关单元组、第五级开关单元组、第七级开关单元组中的第二开关单元，关闭第一级开关单元组、第三级开关单元组、第五级开关单元组、第七级开关单元组中的第一开关单元；同时向第二控制信号端、第三控制信号端输入第一逻辑电平，以导通第二级开关单元组、第六级开关单元组、第四级开关单元组中的第一开关单元，关闭第二级开关单元组、第六级开关单元组、第四级开关单元组中的第二开关单元。其中，第一逻辑电平为高电平，第二逻辑电平为低电平。在第二驱动模式下，第二级移位寄存器GOA2、第四级移位寄存器GOA4、第六级移位寄存器GOA6的输入端不能接收到上一级移位寄存器的输出信号，因此，第二级移位寄存器GOA2、第四级移位寄存器GOA4、第六级移位寄存器GOA6不输出移位信号。同时，由于第一级移位寄存器单元的输入端连接第二级移位寄存器单元的输出端，第一级移位寄存器单元可以向与第二级移位寄存器单元对应的多行像素单元提供使能信号；由于第三级移位寄存器单元的输入端连接第四级移位寄存器单元的输出端，第三级移位寄存器单元还可以向与第四级移位寄存器单元对应的多行像素单元提供使能信号；由于第五级移位寄存器单元的输入端连接第六级移位寄存器单元的输出端，第五级移位寄存器单元还可以向与第六级移位寄存器单元对应的多行像素单元提供使能信号；由于第七级移位寄存器单元的输入端连接 第八级移位寄存器单元的输出端，第七级移位寄存器单元还可以向与第八级移位寄存器单元对应的多行像素单元提供使能信号。
如图8所示，为图4所示栅极驱动电路在第二驱动状态下各个节点的时序图，其中，Out1为第一级移位寄存器单元GOA1输出端的时序图；Out2为第二级移位寄存器单元GOA2输出端的时序图；Out3为第三级移位寄存器单元GOA3输出端的时序图；Out4为第四级移位寄存器单元GOA4输出端的时序图；Out5为第五级移位寄存器单元GOA5输出端的时序图；Out6为第六级移位寄存器单元GOA6输出端的时序图；Out7为第七级移位寄存器单元GOA7输出端的时序图；Out8为第八级移位寄存器单元GOA8输出端的时序图。如图8所示，在T1时间段，第一级移位寄存器单元GOA1的输出端输出高电平信号，如图9所示，为显示面板在T1时间段的显示状态图，其中GOAn为与第n级移位寄存器单元连接的像素单元区域。在T1时间段，第一级移位寄存器单元输出高电平信号，与第一级移位寄存器单元、第二级移位寄存器单元对应连接像素单元接收高电平的使能信号，在T1时间段GOA1、GOA2区域的像素单元不发光(即GOA1、GOA2区域插黑)。如图10所示，为在T2时间段显示面板的显示状态图，其中GOAn为与第n级移位寄存器单元连接的像素单元区域。在T2时间段，第三级移位寄存器单元输出高电平信号，与第三级移位寄存器单元、第四级移位寄存器单元对应连接像素单元接收高电平的使能信号，在T2时间段GOA3、GOA4区域的像素单元不发光(即GOA3、GOA4区域插黑)。依次类推，在T3时间段，与第五级移位寄存器单元、第六级移位寄存器单元对应连接的像素单元不发光(即在T3时间段，GOA5、GOA6区域插黑)，在T4时间段，与第七级移位寄存器单元、第八级移位寄存器单元对应连接的像素单元不发光(即在T4时间段，GOA7、GOA8区域插黑)。
在第三驱动模式下，向第一级移位寄存器的输入端输入第三初始信号，向第一控制信号端、第二控制信号端输入第二逻辑电平，以导通第一级开关单元组、第三级开关单元组、第五级开关单元组、第七级开关单元组、第二级开关单元组、第六级开关单元组中的第二开关单元，关闭第一级开关单元组、第三级开关单元组、第五级开关单元组、第七级开关单元组、第二级开关单元组、第六级开关单元组中的第一开关单元；同时向第三控制信号端输入第一逻辑电平，以导通第四级开关单元组中的第一开关单元，关闭第四级开关单元组中的第二开关单元。其中，第一逻辑电平为高电平，第二逻辑电平为低电平。在第三驱动模式下，只有第五级移位寄存器单元的输入端能够接受到第一级移位寄存器单元输出端的信号，第二级移位寄存器单元、第三级移位寄存器单元、第四级移位寄存器单元、第六级移位寄存器单元、第七级移位寄存器单元、第八级移位寄存器单元不会输出移位信号。同时，由于第一级移位寄存器单元的输出端连接第二级移位寄存器单元、第三级移位寄存器单元、第四级移位寄存器单元 的输入端，第一级移位寄存器单元还可以向与第二级移位寄存器单元、第三级移位寄存器单元、第四级移位寄存器单元对应的多行像素单元提供使能信号；由于第五级移位寄存器单元的输出端连接第六级移位寄存器单元、第七级移位寄存器单元、第八级移位寄存器单元的输入端，第五级移位寄存器单元还可以向与第六级移位寄存器单元、第七级移位寄存器单元、第八级移位寄存器单元对应的多行像素单元提供使能信号。
如图11所示，为图4所示栅极驱动电路在第三驱动状态下各个节点的时序图，其中，Out1为第一级移位寄存器单元GOA1输出端的时序图；Out2为第二级移位寄存器单元GOA2输出端的时序图；Out3为第三级移位寄存器单元GOA3输出端的时序图；Out4为第四级移位寄存器单元GOA4输出端的时序图；Out5为第五级移位寄存器单元GOA5输出端的时序图；Out6为第六级移位寄存器单元GOA6输出端的时序图；Out7为第七级移位寄存器单元GOA7输出端的时序图；Out8为第八级移位寄存器单元GOA8输出端的时序图。如图14所示，在T1时间段，第一级移位寄存器单元GOA1的输出端输出高电平信号，如图12所示，为显示面板在T1时间段的显示状态图，其中GOAn为与第n级移位寄存器单元连接的像素单元区域。在T1时间段，第一级移位寄存器单元输出高电平信号，GOA1、GOA2、GOA3、GOA4区域的像素单元接收高电平的使能信号，因此，在T1时间段GOA1、GOA2、GOA3、GOA4区域的像素单元不发光(即在T1时间段，GOA1、GOA2、GOA3、GOA4区域插黑)。如图13所示，为显示面板在T2时间段的显示状态图，其中GOAn为与第n级移位寄存器单元连接的像素单元区域。在T2时间段，第五级移位寄存器单元输出高电平信号，因此，在T2时间段，GOA5、GOA6、GOA7、GOA8区域的像素单元不发光(即在T2时间段，GOA5、GOA6、GOA7、GOA8区域插黑)。
在第四驱动模式下，向第一级移位寄存器的输入端输入第四初始信号，向第一控制信号端、第二控制信号端、第三控制信号端输入第二逻辑电平，以导通第一到第七级开关单元组中的第二开关单元，同时关闭第一到第七级开关单元组中的第一开关单元。其中，第一逻辑电平为高电平，第二逻辑电平为低电平。在第四驱动模式下，第二级移位寄存器单元、第三级移位寄存器单元、第四级移位寄存器单元、第五级移位寄存器单元、第六级移位寄存器单元、第七级移位寄存器单元、第八级移位寄存器单元不会输出移位信号。同时，由于第一级移位寄存器单元的输出端连接第二级移位寄存器单元、第三级移位寄存器单元、第四级移位寄存器单元、第五级移位寄存器单元、第六级移位寄存器单元、第七级移位寄存器单元、第八级移位寄存器单元的输入端，第一级移位寄存器单元可以向与第二级移位寄存器单元、第三级移位寄存器单元、第四级移位寄存器单元、第五级移位寄存器单元、第六级移位寄存器单元、第七级移位寄存器单元、第八级移位寄存器单元对应的多行像素单元提供使能信号。
如图14所示，为图4所示栅极驱动电路在第四驱动状态下各个节点的时序图，其中，Out1为第一级移位寄存器单元GOA1输出端的时序图；Out2为第二级移位寄存器单元GOA2输出端的时序图；Out3为第三级移位寄存器单元GOA3输出端的时序图；Out4为第四级移位寄存器单元GOA4输出端的时序图；Out5为第五级移位寄存器单元GOA5输出端的时序图；Out6为第六级移位寄存器单元GOA6输出端的时序图；Out7为第七级移位寄存器单元GOA7输出端的时序图；Out8为第八级移位寄存器单元GOA8输出端的时序图。在T1时间段，第一级移位寄存器单元GOA1的输出端输出高电平信号，与第一级移位寄存器单元、第二级移位寄存器单元、第三级移位寄存器单元、第四级移位寄存器单元、第五级移位寄存器单元、第六级移位寄存器单元、第七级移位寄存器单元、第八级移位寄存器单元输出端对应连接像素单元接收高电平的使能信号，因此，在T1时间段显示面板全屏不发光。在T2时间段，第一移位寄存器单元输出低电平信号，与第一级移位寄存器单元、第二级移位寄存器单元、第三级移位寄存器单元、第四级移位寄存器单元、第五级移位寄存器单元、第六级移位寄存器单元、第七级移位寄存器单元、第八级移位寄存器单元输出端对应连接像素单元接收低电平的使能信号，因此，在T2时间段显示面板全屏发光。第四驱动模式即为相关技术中所述的帧与帧之间的插黑方式。
一方面，该栅极驱动电路可以通过第一控制信号端、第二控制信号端、第三控制信号端控制栅极驱动电路在不同的驱动模式下切换工作。另一方面，当栅极驱动电路在第一驱动模式、第二驱动模式、第三驱动模式工作时，显示面板可以实现滚动插黑，从而避免了显示面板画面动态模糊的技术问题；再一方面，该滚动插黑方式相较于相关技术中的帧与帧之间的插黑方式，可以增加每个像素单元的发光时长，从而避免了显示面板图像闪烁、显示亮度低等问题。
在上述的每一种驱动模式下，第一级移位寄存器单元需要输出的高电平有效时长不同，例如，在第一种驱动模式下，第一级移位寄存器单元输出的高电平有效时长需要覆盖与第一级移位寄存器单元对应设置的多行像素单元的数据写入时段；在第二种驱动模式下，第一级移位寄存器单元输出的高电平有效时长需要覆盖与第一级移位寄存器单元、第二级移位寄存器单元对应设置的多行像素单元的数据写入时段；在第三种驱动模式下，第一级移位寄存器单元输出的高电平有效时长需要覆盖与第一级移位寄存器单元、第二级移位寄存器单元、第三级移位寄存器单元、第四级移位寄存器单元对应设置的多行像素单元的数据写入时段；在第四种驱动模式下，第一级移位寄存器单元输出的高电平有效时长需要覆盖所有像素单元的数据写入时段。因此，相应的，在不同驱动模式下，需要向第一移位寄存器单元输入不同的初始化信号，必要时，还可以通过时钟控制信号对第一级移位寄存器单元输出的高电平时长进行调节。
本示例性实施例中，该栅极驱动电路可以与图1中的像素驱动电路对应设置。应 该理解的是，在其他示例性实施例中，本公开提供的栅极驱动电路还可以与其他像素驱动电路对应设置，例如，像素驱动电路可以为2T1C、7T1C等像素结构。
如图15、16所示，图15为本公开栅极驱动电路一种示例性实施例中移位寄存器单元的结构示意图，图16为图15中移位寄存器单元一种示例性实施例中部分节点的时序图。该移位寄存器单元包括第五晶体管T5到第十四晶体管T14、第一电容C1到第三电容C3、反向器PI。如图15所示，第五晶体管T5到第十四晶体管T14可以为P型晶体管，第一电源信号端VGL持续为低电平，第二电源信号端VGH持续为高电平。如图16所示，该移位寄存器单元驱动方式包括5个阶段，在第一阶段T1，第一时钟信号端CLK1为低电平，第二时钟信号端CLK2为高电平，输入端Input为低电平，第五晶体管T5，第六晶体管T6、第十四晶体管T14导通，第二电源端VGH向第三电容C3预冲高电平信号，输出端Eout为高电平；在第二阶段T2，第一时钟信号端CLK1为高电平，第二时钟信号端CLK2为高电平，输入端Input为低电平，第十一晶体管T11导通，第一时钟信号端向电容C2充入高电平信号，以关断第十二晶体管T12，输出端Eout输出高电平；在第三阶段T3，第一时钟信号端CLK1为高电平，第二时钟信号端CLK2前部分为低电平，输入端Input为低电平，第八晶体管T8在电容C2高电平作用下关断，输出端Eout输出高电平；在第四阶段T4，第一时钟信号端CLK1为低电平，第二时钟信号端CLK2为高电平，输入端Input为低电平，第五晶体管T5，第六晶体管T6、第七晶体管T7、第十一晶体管T11导通，第一电源端VGL和第一时钟信号端向第二电容C2预冲低电平，输出端Eout输出高电平；在第五阶段T5，第一时钟信号端CLK1前部分时段为低电平，第二时钟信号端CLK2为高电平，输入端Input为高电平，第五晶体管T5导通，第六晶体管T6、第十一晶体管T11关断，输出端Eout维持上一时段的高电平。在第五阶段T5以后，第二时钟信号端CLK2变为低电平时，第八晶体管T8、第九晶体管T9、第十晶体管T10导通，输出端Eout输出低电平。
本示例性实施例中，该移位寄存器单元用于输出移位信号，应该理解的是，在其他示例性实施例中，移位寄存器单元还可以有更多的结构可供选择，这些都属于本公开的保护范围。
本示例性实施例中，如图17所示，为本公开栅极驱动电路另一种示例性实施例的结构示意图。所述栅极驱动电路还可以包括：第一电源端VDD和多个第三开关单元M3，第三开关单元M3与所述移位寄存器单元一一对应设置，所述第三开关单元M3连接所述第一电源端VDD、所述移位寄存器单元的输出端Out，多条使能信号线EM line，用于响应所述移位寄存器单元的输出端Out的信号将第一电源端VDD传输到多条使能信号线；其中，每条所述使能信号线用于向一行像素单元提供所述使能信号。其中，第三开关单元M3可以为N型晶体管，该设置可以通过第一电源端VDD 增强栅极驱动电路的输出能力。应该理解的是，如果移位寄存器单元输出的有效电平为低电平，第三开关单元可以设置为P型晶体管，通过第三开关单元还可以对输入到使能信号线上的电平进行逻辑转换。
本示例性实施例中，开关单元组还可以为其他个数，并非每一相邻移位寄存器单元之间必须设置一开关单元组，例如，如图18所示，为本公开栅极驱动电路另一种示例性实施例的结构式示意图。本示例性实施例中，仅在第一级移位寄存器单元和第二级移位寄存器单元之间、第三级移位寄存器单元和第四级移位寄存器单元之间，第五级移位寄存器单元和第六级移位寄存器单元之间，第七级移位寄存器单元和第八级移位寄存器单元之间设置有开关单元组；第二级移位寄存器单元和第三级移位寄存器单元之间、第四级移位寄存器单元和第五级移位寄存器单元之间，第六级移位寄存器单元和第七级移位寄存器单元之间没有设置开关单元组。本示例性实施例可以通过控制第一控制信号端SW1输出的逻辑电平控制该栅极驱动电路在上述的第一驱动模式和第二驱动模式下工作。当第一控制信号端SW1输出高电平信号时，该栅极驱动电路在上述的第一驱动模式下工作；当第一控制信号端SW1输出低电平信号时，该栅极驱动电路在上述的第二驱动模式下工作。
本示例性实施例中，移位寄存器单元还可以为其他的个数，例如，所述移位寄存器单元可以为m*2 n个，其中，m为大于等于2的正整数，n为大于等于1的正整数，每相邻移位寄存器之间可以设置一开关单元组；其中，第N级开关单元组设置于第N级移位寄存器单元和第N+1级移位寄存器单元之间。第km+M级开关单元组共同连接第一控制信号端，k为大于等于0的正整数，M为小于m且大于0的正整数，且km+M小于等于m*2 n；第2 q*m+2 q+1*m*p级开关单元组共同连接第q+2控制信号端；其中，q、p为大于等于0的正整数，且2 q*m+2 q+1*m*p小于等于m*2 n。例如，m＝3，n＝3时，第一级开关单元组、第二级开关单元组、第四级开关单元组、第五级开关单元组、第七级开关单元组、第八级开关单元组、第十级开关单元组、第十一级开关单元组、第十三级开关单元组、第十四级开关单元组、第十六级开关单元组、第十七级开关单元组、第十九级开关单元组、第二十级开关单元组、第二十二级开关单元组、第二十三级开关单元组共同连接第一控制信号端；第三级开关单元组、第九级开关单元组、第十五级开关单元组、第二十一级开关单元组共同连接第二控制信号端；第六级开关单元组、第十八级开关单元组共同连接第三控制信号端；第十二级开关单元组共同连接第四控制信号端。该栅极驱动电路通过控制第一控制信号端到第四控制信号端的信号可以实现5种不同的驱动模式。其中，符号“*”表示乘号。
本示例性实施例中，每个移位寄存器单元可以和一行像素单元对应设置，每个移位寄存器单元用于向一行像素单元提供使能信号。如图19所示，为本公开栅极驱动电路另一种示例性实施例的结构式示意图。该显示面板可以包括270行像素单元，相 应的，栅极驱动电路可以包括270个(m*2 n，m等于135、n等于1)级联的移位寄存器单元。其中，第km+M级开关单元组共同连接第一控制信号端，即第1级开关单元组到第134级开关单元组，第136级开关单元组到第269级开关单元组的控制信号端连接第一控制信号端SW1，第2 q*m+2 q+1*m*p级开关单元组共同连接第q+2控制信号端，即第135级开关单元组的控制端信号端连接第二控制信号端SW2。
该栅极驱动电路可以在三种驱动模式下工作：
如图20所示，为图19栅极驱动电路在第一驱动状态下各个节点的时序图，其中，Out1为第一级移位寄存器单元GOA1输出端的时序图；Out2为第二级移位寄存器单元GOA2输出端的时序图；Out3为第三级移位寄存器单元GOA3输出端的时序图；……Out270为第270级移位寄存器单元GOA270输出端的时序图。在第一驱动模式下，第一控制信号端、第二控制信号端均输入高电平信号，每个开关单元组中的第一开关单元导通，第二开关单元关断，该栅极驱动电路的每个移位寄存器单元逐级输出移位信号，以使每个像素单元逐行点亮。
如图21所示，为图19栅极驱动电路在第一驱动状态下各个节点的时序图，Out1为第一级移位寄存器单元GOA1输出端的时序图；Out2为第二级移位寄存器单元GOA2输出端的时序图；……Out135为第135级移位寄存器单元GOA135输出端的时序图；Out136为第136级移位寄存器单元GOA136输出端的时序图；……Out270为第270级移位寄存器单元GOA270输出端的时序图。在第二驱动模式下，第一控制信号端SW1输入低电平信号，第二控制信号端输入高电平信号，第一级移位寄存器单元到第135级移位寄存器单元的输出端短接，第136级移位寄存器单元到第270级移位寄存器单元的输出端短接。在T1时间段，第一级移位寄存器单元到第135级移位寄存器单元输出高电平，与第一级移位寄存器单元到第135级移位寄存器单元对应的像素单元处于插黑阶段；在T2时间段，第一级移位寄存器单元到第135级移位寄存器单元输出低电平，与第一级移位寄存器单元到第135级移位寄存器单元对应的像素单元处于点亮阶段，同时第136级移位寄存器单元到第270级移位寄存器单元输出高电平，与第136级移位寄存器单元到第270级移位寄存器单元对应的像素单元处于插黑阶段。
如图22所示，为图19栅极驱动电路在第一驱动状态下各个节点的时序图，其中，Out1为第一级移位寄存器单元GOA1输出端的时序图；Out2为第二级移位寄存器单元GOA2输出端的时序图；Out3为第三级移位寄存器单元GOA3输出端的时序图；……Out270为第270级移位寄存器单元GOA270输出端的时序图。在第三驱动模式下，第一控制信号端、第二控制信号端均输入低电平信号，每个开关单元组中的第一开关单元关断，第二开关单元导通，每个移位寄存器单元的输出端短路。在T1时间段，每一级移位寄存器单元均输出高电平，显示面板全屏不发光；在T2时间段， 每一级移位寄存器单元均输出低电平，显示面板全屏发光。该第三种驱动模式即为相关技术中所述的帧与帧之间的插黑方式。
应该理解的是，在其他示例性实施例中，显示面板还可以包括其他行数的像素单元，开关单元组还以其他的方式共用控制信号端。例如，显示面板可以包括1080行像素单元，相应的，栅极驱动电路包括1080(m*2 n，m等于135、n等于3)级移位寄存器单元。其中，第km+M级开关单元组共同连接第一控制信号端，即第1级开关单元组到第134级开关单元组，第136级开关单元组到第269级开关单元组、……第946级开关单元组到第1079级开关单元组的控制信号端连接第一控制信号端，第2 q*m+2 q+1*m*p级开关单元组共同连接第q+2控制信号端，即第135级开关单元组、第405级开关单元组、第675级开关单元组、第945级开关单元组的控制端信号端连接第二控制信号端。第270级开关单元组、第810级开关单元组的控制端信号端连接第三控制信号端。第540级开关单元组的控制端信号端连接第四控制信号端。该栅极驱动电路可以实现五种驱动模式的切换。
本示例性实施例还提供一种栅极驱动电路驱动方法，用于驱动上述的栅极驱动电路，该驱动方法包括：
在驱动时段，择一导通同一开关单元组的第一开关单元或第二开关单元。
本示例性实施例中，m＝2，n＝2，所述驱动方法可以包括：
在第一驱动模式下，向第一级移位寄存器的输入端输入第一初始信号，向第一控制信号端、第二控制信号端、第三控制信号端输入第一逻辑电平，以导通第一到第七级开关单元组中的第一开关单元，同时关闭第一到第七级开关单元组中的第二开关单元；
在第二驱动模式下，向第一级移位寄存器的输入端输入第二初始信号，向第一控制信号端输入第二逻辑电平，以导通第一级开关单元组、第三级开关单元组、第五级开关单元组、第七级开关单元组中的第二开关单元，同时向第二控制信号端、第三控制信号端输入第一逻辑电平，以导通第二级开关单元组、第六级开关单元组、第四级开关单元组中的第一开关单元；
在第三驱动模式下，向第一级移位寄存器的输入端输入第三初始信号，向第一控制信号端、第二控制信号端输入第二逻辑电平，以导通第一级开关单元组、第三级开关单元组、第五级开关单元组、第七级开关单元组、第二级开关单元组、第六级开关单元组中的第二开关单元，同时向第三控制信号端输入第一逻辑电平，以导通第四级开关单元组中的第一开关单元；
在第四驱动模式下，向第一级移位寄存器的输入端输入第四初始信号，向第一控制信号端、第二控制信号端、第三控制信号端输入第二逻辑电平，以导通第一到第七级开关单元组中的第二开关单元，同时关闭第一到第七级开关单元组中的第一开关单 元。
本示例性实施例提供的栅极驱动电路驱动方法与上述栅极驱动电路具有相同的技术特征和工作原理，上述内容已经做出详细说明，此处不再赘述。
本示例性实施例还提供一种显示面板，该显示面板包括上述的栅极驱动电路。
本示例性实施例中，所述显示面板为硅基OLED显示面板。该硅基OLED显示面板可以应用于VR/AR等显示装置中。
如图23所示，为本公开硅基OLED显示面板一种示例性实施例的结构示意图。所述硅基OLED显示面板包括：显示区1、第一虚拟区2、检测区3、第二虚拟区4、阴极环区5、第三虚拟区6、第一驱动电路集成区7、第二驱动电路集成区8。显示区1内集成有使能信号线11；第一虚拟区2位于所述显示区1的周围；检测区3，位于所述第一虚拟区远离所述显示区的一侧，且位于所示显示区的沿所述使能信号线11延伸方向的一侧或两侧；第二虚拟区4，位于所述检测区远离所述显示区的一侧；阴极环区5，位于所述第二虚拟区远离所述显示区的一侧；第三虚拟区6，位于所述阴极环区远离所述显示区的一侧；第一驱动电路集成区7，位于所述第三虚拟区远离所述显示区的一侧，用于集成第一栅极驱动电路，所述第一栅极驱动电路用于生成栅极驱动信号；第二驱动电路集成区8，位于所述第一驱动电路集成区远离所述显示区的一侧，用于集成上述的栅极驱动电路。由于半导体的制作工艺原因，通过多次构图工艺形成的多个半导体中，位于边沿的半导体的均一性较差。本示例性实施例中，第一虚拟区1内可以集成有与显示区1内相同结构的半导体，使得显示区内的半导体远离边沿区，从而提高显示区1内半导体的均一性。检测区3内可以集成有检测电路，用于检测显示面板的工作电流。阴极环区2用于集成阴极环和像素驱动电路，该阴极环与公共阴极同层设置，以将发光单元的阴极通过过孔连接到像素驱动电路的电源端。第二虚拟区4、第三虚拟区6内集成有半导体，以提高阴极环区2内半导体的均一性。如图23所示，检测区3、第二虚拟区4、阴极环区5、第三虚拟区6、第一驱动电路集成区7、第二驱动电路集成区8可以设置于显示区的相对两侧。应该理解的是，在其他示例性实施例中，检测区3、第二虚拟区4、阴极环区5、第三虚拟区6、第一驱动电路集成区7、第二驱动电路集成区8还可以仅设置于显示区的一侧。
本领域技术人员在考虑说明书及实践这里公开的公开后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (19)

  1. 一种栅极驱动电路，应用于显示面板，所述显示面板包括多行像素单元，其中，所述栅极驱动电路包括：
    多个移位寄存器单元，所述移位寄存器单元级联设置，上一级移位寄存器单元的输出端连接相邻下一级移位寄存器单元的输入端，每个所述移位寄存器单元和至少一行像素单元对应设置，用于向与其对应的至少一行所述像素单元输入使能信号；
    开关单元组，至少部分相邻两移位寄存器单元之间设置有所述开关单元组，所述开关单元组包括：
    第一开关单元，连接上一级移位寄存器单元的输出端，相邻下一级移位寄存器单元的输入端，用于响应一控制信号以导通上一级移位寄存器单元的输出端和相邻下一级移位寄存器单元的输入端；
    第二开关单元，连接上一级移位寄存器单元的输出端，相邻下一级移位寄存器单元的输出端，用于响应一控制信号以导通上一级移位寄存器单元的输出端和相邻下一级移位寄存器单元的输出端；
    其中，所述第一开关单元和第二开关单元在驱动时段择一导通。
  2. 根据权利要求1所述的栅极驱动电路，其中，
    所述第一开关单元还连接控制信号端，用于响应所述控制信号端的信号以导通上一级移位寄存器单元的输出端和相邻下一级级移位寄存器单元的输入端；
    所述第二开关单元还连接所述控制信号端，用于响应所述控制信号端的信号以导通上一级移位寄存器单元的输出端和相邻下一级移位寄存器单元的输出端；
    其中，所述第一开关单元和第二开关单元的导通电平逻辑相反。
  3. 根据权利要求1所述的栅极驱动电路，其中，每个所述移位寄存器单元对应一行像素单元，用于向与其对应的一行像素单元提供使能信号。
  4. 根据权利要求1所述的栅极驱动电路，其中，每个所述移位寄存器单元对应多行像素单元，用于向与其对应的多行像素单元提供使能信号。
  5. 根据权利要求2所述的栅极驱动电路，其中，
    每相邻移位寄存器之间设置一所述开关单元组，其中，第N级开关单元组设置于第N级移位寄存器单元和第N+1级移位寄存器单元之间，N为大于等于1的正整数。
  6. 根据权利要求5所述的栅极驱动电路，其中，
    所述移位寄存器单元为m*2 n个，其中，m为大于等于2的正整数，n为大于等于1的正整数；
    第km+M级开关单元组共同连接第一控制信号端，k为大于等于0的正整数，M为小于m且大于0的正整数，且km+M小于等于m*2 n；
    第2 q*m+2 q+1*m*p级开关单元组共同连接第q+2控制信号端；
    其中，q、p为大于等于0的正整数，且2 q*m+2 q+1*m*p小于等于m*2 n；
    所述第一控制信号端、第q+2控制信号端形成所述控制信号端。
  7. 根据权利要求6所述的栅极驱动电路，其中，m等于2、n等于2；
    第一级开关单元组、第三级开关单元组、第五级开关单元组、第七级开关单元组共同连接第一控制信号端；
    第二级开关单元组、第六级开关单元组共同连接第二控制信号端；
    第四级开关单元组连接第三控制信号端。
  8. 根据权利要求1所述的栅极驱动电路，其中，每个移位寄存器单元的输出端连接多条使能信号线，所述多条使能信号线的每一条用于向一行像素单元提供所述使能信号。
  9. 根据权利要求1所述的栅极驱动电路，其中，所述栅极驱动电路还包括：
    第一电源端；
    多个第三开关单元，与所述移位寄存器单元一一对应设置，所述第三开关单元连接所述第一电源端、所述移位寄存器单元的输出端，至少一条使能信号线，用于响应所述移位寄存器单元的输出端的信号将第一电源端传输到所述至少一条使能信号线；
    其中，所述至少一条使能信号线用于向一行像素单元提供所述使能信号。
  10. 根据权利要求4所述的栅极驱动电路，其中，每个移位寄存器单元所对应的像素单元行数相同。
  11. 根据权利要求4所述的栅极驱动电路，其中，与同一移位寄存器单元对应的多行像素单元相邻设置。
  12. 根据权利要求2所述的栅极驱动电路，其中，所述第一开关单元为P型晶体管，所述第二开关单元为N型晶体管；
    或，所述第一开关单元为N型晶体管，所述第二开关单元为P型晶体管。
  13. 根据权利要求12所述的栅极驱动电路，其中，
    所述第一开关单元为P型晶体管，所述第一开关单元的栅极连接所述控制信号端，第一极连接上一级移位寄存器单元的输出端，第二极连接相邻下一级移位寄存器单元的输入端；
    所述第二开关单元为N型晶体管，所述第二开关单元的栅极连接所述控制信号端，第一极连接上一级移位寄存器单元的输出端，第二极连接相邻下一级移位寄存器单元的输出端；
    或，所述第一开关单元为N型晶体管，所述第一开关单元的栅极连接所述控制信号端，第一极连接上一级移位寄存器单元的输出端，第二极连接相邻下一级移位寄存器单元的输入端；
    所述第二开关单元为P型晶体管，所述第二开关单元的栅极连接所述控制信号端，第一极连接上一级移位寄存器单元的输出端，第二极连接相邻下一级移位寄存器单元的输出端。
  14. 根据权利要求9所述的栅极驱动电路，其中，所述第三开关单元为开关晶体管，所述第三开关单元的栅极连接所述移位寄存器单元的输出端，第一极连接所述第一电源端，第二极连接所述至少一条使能信号线。
  15. 一种栅极驱动电路驱动方法，用于驱动权利要求1-14任一项所述的栅极驱动电路，其中，包括：
    在驱动时段，择一导通同一开关单元组的第一开关单元或第二开关单元。
  16. 根据权利要求13所述的栅极驱动电路驱动方法，其中，m＝2，n＝2，所述驱动方法包括：
    在第一驱动模式下，向第一级移位寄存器的输入端输入第一初始信号，向第一控制信号端、第二控制信号端、第三控制信号端输入第一逻辑电平，以导通第一到第七级开关单元组中的第一开关单元，同时关闭第一到第七级开关单元组中的第二开关单元；
    在第二驱动模式下，向第一级移位寄存器的输入端输入第二初始信号，向第一控制信号端输入第二逻辑电平，以导通第一级开关单元组、第三级开关单元组、第五级开关单元组、第七级开关单元组中的第二开关单元，同时向第二控制信号端、第三控制信号端输入第一逻辑电平，以导通第二级开关单元组、第六级开关单元组、第四级开关单元组中的第一开关单元；
    在第三驱动模式下，向第一级移位寄存器的输入端输入第三初始信号，向第一控制信号端、第二控制信号端输入第二逻辑电平，以导通第一级开关单元组、第三级开关单元组、第五级开关单元组、第七级开关单元组、第二级开关单元组、第六级开关单元组中的第二开关单元，同时向第三控制信号端输入第一逻辑电平，以导通第四级开关单元组中的第一开关单元；
    在第四驱动模式下，向第一级移位寄存器的输入端输入第四初始信号，向第一控制信号端、第二控制信号端、第三控制信号端输入第二逻辑电平，以导通第一到第七级开关单元组中的第二开关单元，同时关闭第一到第七级开关单元组中的第一开关单元。
  17. 一种显示面板，其中，包括权利要求1-14任一项所述的栅极驱动电路。
  18. 根据权利要求17所述的显示面板，其中，所述显示面板为硅基OLED显示面板。
  19. 根据权利要求18所述的显示面板，其中，所述硅基OLED显示面板包括：
    显示区，集成有使能信号线；
    第一虚拟区，位于所述显示区的周围；
    检测区，位于所述第一虚拟区远离所述显示区的一侧，且位于所示显示区的沿所述使能信号线延伸方向的一侧或两侧；
    第二虚拟区，位于所述检测区远离所述显示区的一侧；
    阴极环区，位于所述第二虚拟区远离所述显示区的一侧；
    第三虚拟区，位于所述阴极环区远离所述显示区的一侧；
    第三虚拟区，位于所述阴极环区远离所述显示区的一侧；
    第一驱动电路集成区，位于所述第三虚拟区远离所述显示区的一侧，用于集成第一栅极驱动电路，所述第一栅极驱动电路用于生成栅极驱动信号；
    第二驱动电路集成区，位于所述第一驱动电路集成区远离所述显示区的一侧，用于集成权利要求1-14任一项所述的栅极驱动电路。
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