WO2020253522A1 - 阵列基板及其测试方法 - Google Patents

阵列基板及其测试方法 Download PDF

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Publication number
WO2020253522A1
WO2020253522A1 PCT/CN2020/094009 CN2020094009W WO2020253522A1 WO 2020253522 A1 WO2020253522 A1 WO 2020253522A1 CN 2020094009 W CN2020094009 W CN 2020094009W WO 2020253522 A1 WO2020253522 A1 WO 2020253522A1
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Prior art keywords
clock signal
signal lines
transistor
array substrate
test
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PCT/CN2020/094009
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English (en)
French (fr)
Inventor
袁志东
李永谦
袁粲
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Priority to US17/262,775 priority Critical patent/US20210256889A1/en
Publication of WO2020253522A1 publication Critical patent/WO2020253522A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate and a testing method thereof.
  • the gate driver on array (GOA) technology can integrate the gate driving circuit on the array substrate, thereby reducing the frame of the display device.
  • the gate driving circuit may be connected to a plurality of clock signal lines and the pixel unit, and the gate driving circuit may control the operation of the pixel unit according to the clock signal provided by the clock signal line.
  • the gate drive circuit in order to ensure the product yield, can be tested for performance before leaving the factory, for example, array test (AT).
  • array test array test
  • multiple test terminals can be set on the array substrate.
  • Each test terminal can be connected to a clock signal line and a pin of the test equipment.
  • the test equipment can provide each clock signal line through each test terminal. Clock signal.
  • the present disclosure provides an array substrate and a testing method thereof.
  • the scheme is as follows:
  • an array substrate includes a gate drive circuit, a plurality of clock signal lines, and a plurality of test terminals, the number of the clock signal lines is greater than the number of the test terminals;
  • the plurality of clock signal lines are respectively connected to the gate driving circuit and the plurality of test terminals, and at least two clock signal lines are connected to the same test terminal;
  • the multiple test terminals are used to connect with test equipment.
  • the gate driving circuit includes a plurality of cascaded shift register units, and the plurality of clock signal lines includes: a plurality of first clock signal lines and a plurality of second clock signal lines, each of the The shift register unit is used for outputting the clock signal provided by the first clock signal line to the switch output terminal connected to the first gate line, and for outputting the clock signal provided by the second clock signal line to the second gate line.
  • At least two first clock signal lines are connected to the same first test terminal;
  • At least two second clock signal lines are connected to the same second test terminal.
  • the multiple test terminals include: one second test terminal, and the multiple second clock signal lines are all connected to one second test terminal.
  • At least two adjacent first clock signal lines are connected to the same first test terminal.
  • every two of the first clock signal lines are connected to the same first test terminal.
  • the plurality of clock signal lines further includes: a plurality of third clock signal lines, among the plurality of cascaded shift register units, the odd-numbered or even-numbered shift register units and the third clock signal line Connection for outputting the clock signal provided by the third clock signal line to the shift output terminal;
  • each of the third clock signal lines is connected to one of the first test terminals, and the first test terminals connected to each of the third clock signal lines are different.
  • each of the third clock signal lines is directly connected to one of the first test terminals, and the at least two first clock signal lines are all connected to one of the third clock signal lines.
  • the at least two first clock signal lines are directly connected to the same first test terminal, and each of the third clock signal lines is connected to one of the at least two first clock signal lines.
  • a clock signal line connection is optionally provided.
  • the plurality of clock signal lines includes: 10 first clock signal lines, 10 second clock signal lines, and 5 third clock signal lines.
  • each shift register unit connected to the third clock signal line is connected to the input end of the two-stage shift register unit, and the two-stage shift register unit is adjacent.
  • each of the shift register units includes: a shift sub-circuit, a first output transistor, and a second output transistor;
  • the shift sub-circuit is connected to the pull-up node
  • the gate of the first output transistor is connected to the pull-up node, the first electrode of the first output transistor is connected to the first clock signal line, and the second electrode of the first output transistor is connected to the The switch output terminal is connected;
  • the gate of the second output transistor is connected to the pull-up node, the first electrode of the second output transistor is connected to a second clock signal line, and the second electrode of the second output transistor is connected to the The detection output terminal is connected.
  • the array substrate further includes: a pull-down power line; each of the shift register units further includes: a first pull-down transistor and a second pull-down transistor; the shift sub-circuit is also connected to a pull-down node;
  • the gate of the first pull-down transistor is connected to the pull-down node, the first pole of the first pull-down transistor is connected to the pull-down power line, and the second pole of the first pull-down transistor is connected to the switch output End connection
  • the gate of the second pull-down transistor is connected to the pull-down node, the first pole of the second pull-down transistor is connected to the pull-down power line, and the second pole of the second pull-down transistor is connected to the detection output terminal. connection.
  • one of the clock signal lines is directly connected to the test terminal, and the at least two clock signal lines are connected in sequence.
  • one target clock signal line is directly connected to the test terminal, and the at least two clock signal lines except for the target
  • Each of the clock signal lines except the clock signal line is connected to the target clock signal line.
  • the array substrate further includes a plurality of pixel circuits, and each of the pixel circuits includes a switching transistor, a driving transistor, a detection transistor, and a storage capacitor;
  • the gate of the switching transistor is connected to the first gate line, the first electrode of the switching transistor is connected to the data signal terminal, and the second electrode of the switching transistor is connected to the gate of the driving transistor;
  • the first pole of the driving transistor is connected to the DC power supply terminal, and the second pole of the driving transistor is connected to one end of the light emitting element;
  • the gate of the detection transistor is connected to the second gate line, the first electrode of the detection transistor is connected to one end of the light-emitting element, and the second electrode of the detection transistor is connected to the detection signal line;
  • One end of the storage capacitor is connected to the gate of the driving transistor, and the other end is connected to one end of the light emitting element.
  • a testing method of an array substrate for testing the array substrate as described in the above aspect includes:
  • the multiple clock signal lines include: multiple first clock signal lines, multiple second clock signal lines, and multiple third clock signal lines
  • the multiple test terminals include: multiple first test lines Terminal and a second test terminal, every two of the first clock signal lines are connected to the same first test terminal, the plurality of second clock signal lines are all connected to one of the second test terminals, each One of the third clock signal lines is connected to one of the first test terminals;
  • the providing clock signals to the multiple clock signal lines in the array substrate through each of the test terminals includes:
  • the duty ratio of the clock signals provided to the plurality of first clock signal lines and the plurality of third clock signal lines is 2/5, and the duty cycle is provided to every two adjacent third clock signals
  • the interval between the rising edges of the clock signal provided by the line is 1/5 of the period of the clock signal.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of a partial structure of a shift register unit provided by an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a connection between a second clock signal line and a test terminal provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of a connection between a first clock signal line and a test terminal provided by an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a connection between a first clock signal line and a first test terminal, and a third clock signal line and a first test terminal according to an embodiment of the present disclosure
  • FIG. 8 is a schematic diagram of another connection between the first clock signal line and the first test terminal, and the third clock signal line and the first test terminal according to the embodiment of the present disclosure
  • FIG. 9 is a schematic structural diagram of still another array substrate provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a pixel circuit included in an array substrate provided by an embodiment of the present disclosure.
  • FIG. 11 is a flowchart of a method for testing an array substrate provided by an embodiment of the present disclosure.
  • FIG. 12 is a timing diagram of various signals in an array substrate provided by an embodiment of the present disclosure.
  • FIG. 13 is a timing simulation diagram of various signals in an array substrate provided by an embodiment of the present disclosure.
  • the transistors used in all the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • the transistors used in the embodiments of the present disclosure are mainly switching transistors. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable.
  • the source electrode is referred to as the first electrode and the drain electrode is referred to as the second electrode. According to the form in the figure, it is stipulated that the middle end of the transistor is the gate, the signal input end is the source, and the signal output end is the drain.
  • the switching transistors used in the embodiments of the present disclosure may include any one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is low and turned off when the gate is high. , The N-type switching transistor is turned on when the gate is high, and it is turned off when the gate is low.
  • the array substrate may generally include clock signal lines, gate driving circuits, and multiple rows of pixel circuits arranged in an array. Each row of pixel circuits may be connected to at least two gate lines, and the gate driving circuit may be connected to clock signal lines and gate lines.
  • the gate driving circuit may output the clock signal provided by the clock signal line as a gate driving signal to the gate line, the gate line may output the gate driving signal to the pixel circuit, and the pixel circuit may work under the driving of the gate driving signal.
  • the gate drive circuit can be connected to multiple clock signal lines, and for a high-resolution display panel, the number of clock signal lines that the gate drive circuit needs to connect may be more.
  • each clock signal line needs to be connected to a test terminal during testing, and each test terminal needs to be connected to a pin on the test equipment. Therefore, when the number of clock signal lines is large, the number of test terminals that need to be provided on the array substrate will be more.
  • the test equipment needs to include more pins, and the number of test terminals provided on the array substrate It may even exceed the limit of the number of pins that the test equipment can set.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure.
  • the array substrate may include: a gate driving circuit 10, a plurality of clock signal lines 20 and a plurality of test terminals 30.
  • the number of clock signal lines 20 can be greater than the number of test terminals 30.
  • multiple clock signal lines 20 may be connected to the gate driving circuit 10 and multiple test terminals 30 respectively, and at least two clock signal lines 20 may be connected to the same test terminal 30.
  • test terminals 30 can be used to connect with test equipment.
  • each test terminal 30 can be connected to a pin of the test equipment, and the pins connected to each test terminal 30 are different.
  • the test device may be an AT device for AT testing, or it may also be a CT device for CT testing.
  • every two clock signal lines 20 are connected to the same test terminal 30.
  • the array substrate includes 10 clock signal lines 20, only 5 test terminals 30 need to be provided on the array substrate. Since each clock signal line in the related art is connected to one test terminal, 10 test terminals need to be provided on the array substrate in the related art.
  • the number of test terminals required to be provided on the array substrate provided by the embodiments of the present disclosure is reduced by half compared to the number of test terminals required to be provided on the array substrate provided by the related art.
  • the number of pins required to be included in the test device connected to the test terminal on the array substrate provided by the embodiments of the present disclosure is relative to the number of pins required to be included in the test device connected to the test terminal on the array substrate provided in the related art.
  • the number of feet is also reduced by half, saving costs.
  • the embodiments of the present disclosure provide an array substrate, which includes a plurality of clock signal lines and a plurality of test terminals. Since at least two clock signal lines of the multiple clock signal lines can be connected to the same test terminal, compared to the connection of one clock signal line to one test terminal in the related art, the array substrate provided by the embodiment of the present disclosure requires The number of test terminals is relatively small. Correspondingly, the number of pins required to be included in the test device connected to the test terminal on the array substrate provided by the embodiment of the present disclosure can be less, and the production cost of the test device is lower and the volume is smaller. small.
  • FIG. 2 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure.
  • the gate driving circuit 10 may include a plurality of shift register units 101 connected in cascade.
  • the plurality of clock signal lines 20 may include: a plurality of first clock signal lines 201 and a plurality of second clock signal lines 202.
  • Each shift register unit 101 can be used to output the clock signal provided by the first clock signal line 201 to the switch output terminal OUT1 connected to the first gate line, and to output the clock signal provided by the second clock signal line 202 To the detection output terminal OUT2 connected to the second gate line.
  • the first gate line may be used to provide a gate driving signal to a switching transistor in a pixel circuit included in the array substrate
  • the second gate line may be used to provide a gate driving signal to a detection transistor in the pixel circuit.
  • FIG. 3 is a schematic diagram of a partial structure of a shift register unit provided by an embodiment of the present disclosure. 2 and 3, it can be seen that each shift register unit 101 may include a shift sub-circuit 1011, a first output transistor T1, a second output transistor T2, an input terminal STU, a first clock signal terminal CLK1 and The second clock signal terminal CLK2.
  • the shift sub-circuit 1011 may be connected to the input terminal STU and the pull-up node Q respectively.
  • the gate of the first output transistor T1 may be connected to the pull-up node Q
  • the first pole may be connected to the first clock signal terminal CLK1
  • the second pole may be connected to the switch output terminal OUT1.
  • the gate of the second output transistor T2 may be connected to the pull-up node Q
  • the first pole may be connected to the second clock signal terminal CLK1
  • the second pole may be connected to the detection output terminal OUT2.
  • the first clock signal line 201 may be connected to the first clock signal terminal CLK1 in the shift register unit
  • the second clock signal line 202 may be connected to the second clock signal terminal CLK2 in the shift register unit.
  • the switch output terminal OUT1 may also be connected to the input terminal STU of another shift register 101.
  • the switch output terminal OUT1 of the first stage shift register unit 101(1) in Fig. 2 can be connected to the input terminal STU of the fifth stage shift register unit 101(5) and the sixth stage shift register unit (Fig. 2) is connected to the input terminal STU.
  • each shift register unit 101 can transmit the clock signal provided by the first clock signal line 201 to the first clock signal terminal CLK1 through the first output transistor T1 when the pull-up node Q is at an effective potential. Output to the switch output terminal OUT1.
  • Each shift register unit 101 can output the clock signal provided by the second clock signal line 202 to the second clock signal terminal CLK2 to the detection output terminal OUT2 through the second output transistor T2 when the pull-up node Q is at an effective potential.
  • the plurality of test terminals 30 may include: a plurality of first test terminals 301 and at least one second test terminal 302.
  • the plurality of first clock signal lines 201 at least two first clock signal lines 201 can be connected to the same first test terminal 301, and each first test terminal 301 can be connected to at least one first clock signal line 201 .
  • the plurality of second clock signal lines 202 at least two second clock signal lines 202 are connected to the same second test terminal 302.
  • the plurality of clock signal lines 20 include ten first clock signal lines 201 and ten second clock signal lines 202.
  • the multiple test terminals 30 include five first test terminals 301 and one second test terminal 302. Every two first clock signal lines 201 of the ten first clock signal lines 201 are connected to the same first test terminal 301.
  • the ten second clock signal lines 202 are all connected to one second test terminal 302.
  • FIG. 4 is a schematic diagram of a connection between a second clock signal line and a second test terminal according to an embodiment of the present disclosure.
  • the multiple test terminals may include only one second test terminal 302, and multiple second clock signal lines 202 may all be connected to the one second test terminal 302.
  • the gate of the second output transistor T2 connected to the detection signal terminal OUT2 is connected to the pull-up node Q, that is, the working state of the second output transistor T2 is controlled by the potential of the pull-up node Q.
  • the potential of the pull-up node Q is controlled by the signal output from the switch output terminal OUT1 of the shift register unit 101 cascaded therewith.
  • a plurality of first test terminals 301 can be used to sequentially provide a clock signal at an effective potential to each first clock signal line 201. Accordingly, each shift register unit 101 can output a terminal to each switch. OUT1 sequentially outputs clock signals at the effective potential, so that the pull-up node Q of each shift register unit 101 can be sequentially at the effective potential, that is, the second output transistor T2 in each shift register unit 101 can be controlled to turn on sequentially.
  • a second test terminal 302 is set to be connected to all the second clock signal lines 202, and a signal at a valid potential is provided to all the second clock signal lines 202 through the one second test terminal 302, so that each shift
  • the register unit sequentially outputs signals at effective potentials to each detection output terminal OUT2, that is, sequentially outputs gate drive signals at effective potentials to multiple second gate lines.
  • the detection transistors in multiple pixel circuits located in the same column That is, it can be turned on sequentially, which can further reduce the number of test terminals 30 that need to be provided on the array substrate while ensuring the normal operation of the array substrate.
  • At least two adjacent first clock signal lines 201 may be connected to the same first test terminal 301.
  • every two adjacent first clock signal lines 201 may be connected to one first test terminal 301.
  • the wiring process can be simplified while reducing the number of test terminals that need to be provided.
  • FIG. 5 is a schematic diagram of an optional connection between the first clock signal line and the first test terminal according to an embodiment of the present disclosure.
  • FIGS. 2 and 5 it can be seen that among the plurality of first clock signal lines 201, every two first clock signal lines 201 can be connected to the same first test terminal 301.
  • each shift register unit 101 outputs the clock signal provided by the first clock signal line 201 to the switch output terminal OUT1 connected to the first gate line, when every two first clock signal lines 201 is connected to a first test When the terminal 301 is connected, the clock signals provided by the two first clock signal lines 201 connected to the same first test terminal 301 are exactly the same.
  • the two shift register units 101 connected to the two first clock signal lines 201 output the same clock signals to their switch output terminals OUT1.
  • the first gate line is used to provide gate drive signals to the switching transistors, the two first gate lines can simultaneously output gate drive signals to the switching transistors in the two rows of pixel circuits, that is, they can drive two at the same time. Row pixel unit. Under the premise of reducing the number of test terminals that need to be provided on the array substrate, the display effect of the display device when the array substrate is tested is also ensured, and the resolution of the display device is ensured.
  • FIG. 6 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure.
  • the plurality of clock signal lines 20 may further include: a plurality of third clock signal lines 203.
  • each shift register unit 101 of an odd or even number stage can be connected to a third clock signal line 203, and the clock signal provided by the third clock signal line 203 can be connected Output to the shift output terminal OUT3.
  • each odd-numbered shift register unit 101 (or each even-numbered shift register unit 101) connected to the third clock signal line 203 may further include: a third output The transistor T3 and the third clock signal terminal CLK3.
  • the gate of the third output transistor T3 can be connected to the pull-up node Q, the first electrode can be connected to the third clock signal terminal CLK3, the second electrode can be connected to the shift output terminal OUT3, and the shift output terminal OUT3 can be connected to the other two terminals.
  • the input terminal STU of the one-stage shift register unit 101 is connected, and the two-stage shift register unit 101 connected to the shift output terminal OUT3 is an adjacent two-stage shift register unit 101.
  • the shift output terminal OUT3 of the first stage shift register unit 101(1) shown in FIG. 6 can be connected to the input terminal STU of the fifth stage shift register unit 101(7) and the sixth stage shift register unit ( (Not shown in the figure) the input terminal STU connection.
  • the shift output terminal OUT3 can also be connected to the reset terminal STD of other adjacent two-stage shift register units 101.
  • the shift output terminal OUT3 of the seventh-stage shift register unit 101(7) shown in FIG. 6 may be the same as the reset terminal STD of the first-stage shift register unit 101(1) and the second-stage shift register unit 101 (2) The reset terminal STD is connected.
  • the third clock signal line 203 can be connected to the third clock signal terminal CLK3, and each odd-numbered or even-numbered shift register unit 101 connected to the third clock signal line 203 can pull up the node Q as When the potential is valid, the clock signal provided by the third clock signal line 203 to the first clock signal terminal CLK3 is output to the shift output terminal OUT3 through the third output transistor T3.
  • each third clock signal line 203 may be connected to one first test terminal 301, and each third clock signal line 203 is connected The first test terminal 301 can be different.
  • the plurality of clock signal lines 20 include five third clock signal lines 203.
  • each third clock signal line 203 may be connected to a first test terminal. 301 connection.
  • the odd-numbered (or even-numbered) shift register unit 101 can output the clock signal provided by the third clock signal line 203 to the shift output terminal OUT3, and can output the clock signal provided by the first clock signal line 201 to the second A switch output terminal OUT1 connected to a gate line
  • the switch output terminal OUT1 and the shift output terminal OUT3 output signals may be the same.
  • the timing of the clock signals provided by the third clock signal line 203 and the first clock signal line 201 may be the same. Therefore, at least two first clock signal lines 201 and each third clock signal line 203 can be provided, which are connected to the same first test terminal 301, so that the array substrate can be further reduced on the premise of ensuring the normal operation of the gate drive circuit.
  • each odd-numbered (or even-numbered) shift register unit 101 CLK1 and the third clock signal terminal CLK3 may be the same clock signal terminal.
  • each odd-numbered (or even-numbered) shift register unit 101 outputs the clock signal provided by its first clock signal terminal CLK1 to the switch output terminal OUT1 connected to the first gate line through the first output transistor T1 , And output the clock signal provided by its third clock signal terminal CLK3 to the input terminal STU of the shift register unit 101 to which it is cascaded through the third output transistor T3.
  • the first clock signal terminal CLK1 and the third clock signal terminal CLK3 may be different clock signal terminals.
  • each shift register unit 101 may further include high-level power supply terminals VGH, VDDA, VDDB, and VDD, and low-level power supply terminals VGL and LVGL. And each power terminal can be connected to its corresponding signal line.
  • the high-level power terminal VDDA is connected to the signal line VDDA.
  • Each shift register unit 101 may further include a pull-down node QB, pull-down transistors M1 and M2, and the odd-numbered (or even-numbered) shift register unit 101 connected to the third clock signal line 203 may also include a pull-down transistor M3.
  • the gates of the pull-down transistors M1 to M3 may all be connected to the pull-down node QB, and the first poles of the pull-down transistors M1 and M2 may be connected to the low-level power supply terminal VGL, and the low-level power supply terminal VGL may be connected to the low-level power supply terminal VGL. Pull down the power cord to connect.
  • the first pole of the pull-down transistor M3 may be connected to the low-level power supply terminal LVGL
  • the second pole of the pull-down transistor M1 may be connected to the switch output terminal OUT1
  • the second pole of the pull-down transistor M2 may be connected to the detection output terminal OUT2
  • the pull-down transistor M3 The first pole of can be connected to the shift output terminal OUT3.
  • the pull-down transistor M1 can output a signal (such as a low-level signal) of an invalid potential provided by the low-level power terminal VGL to the switch output terminal OUT1 when the pull-down node QB is at an effective potential, so as to reset the switch output terminal OUT1 .
  • the pull-down transistor M2 can output a signal (such as a low-level signal) of an invalid potential provided by the low-level power supply terminal VGL to the detection output terminal OUT2, thereby resetting the detection output terminal OUT2.
  • the pull-down transistor M3 can output a signal (such as a low-level signal) of an invalid potential provided by the low-level power supply terminal LVGL to the shift output terminal OUT3 when the pull-down node QB is at an effective potential, so as to reset the shift output terminal OUT3 .
  • a signal such as a low-level signal
  • the array substrate further includes a plurality of detection circuits 40 (only one detection circuit 40 is schematically shown in FIG. 3) and an electrostatic discharge circuit 50.
  • Each detection circuit 40 can be connected to the pull-up node Q, the clock signal terminal CLKA, and the enable signal terminal OE of a shift register unit 101.
  • the detection circuit 40 can be used to control the timing of the shift register unit 101 during the blank period.
  • the electrostatic discharge circuit 50 may be respectively connected to the plurality of clock signal lines 20 and the electrostatic discharge line, and the electrostatic discharge circuit 50 is used to discharge the static electricity on the plurality of clock signal lines 20 to realize electrostatic protection.
  • the electrostatic discharge circuit 50 can also be connected to other signal lines.
  • the power terminal ESD_VGH in the electrostatic discharge circuit 50 may be connected to the signal line VDDA, and the power terminal ESD_VGL may be connected to the low-level power terminal LVGL.
  • the electrostatic discharge circuit 50 may also be connected to the signal line VDD and the signal line VDDB. Among them, the signal line connected to the low-level power supply terminal LVGL is an electrostatic discharge line.
  • the embodiment of the present disclosure provides two ways for connecting the first clock signal line 201 and the third clock signal line 203 to the first test terminal 301:
  • each third clock signal line 203 may be directly connected to a first test terminal 301, and at least two first clock signal lines 201 may both be connected to a first test terminal 301.
  • the three clock signal lines 203 are connected.
  • every two first clock signal lines 201 are connected to one third clock signal line 203.
  • every two first clock signal lines 201 can be connected through a connecting line, and only one of the first clock signal lines 201 is directly connected to one third clock signal line 203.
  • each first clock signal line 201 in every two first clock signal lines 201 may be directly connected to one third clock signal line 203.
  • At least two first clock signal lines 201 may be directly connected to the same first test terminal 301, and each third clock signal line 203 may be connected to at least two One of the first clock signal lines 201 is connected.
  • every two first clock signal lines 201 are directly connected to a first test terminal 301, and every third clock signal line 203 is connected to every two first clock signal lines.
  • One of the first clock signal lines 201 in 201 is connected.
  • every two first clock signal lines 201 can be connected through a connection line, and only one of the first clock signal lines 201 is directly connected to one first test terminal 301.
  • each of the two first clock signal lines 201 may be directly connected to the same first test terminal 301 respectively.
  • the multiple clock signal lines in the array substrate may include: ten first clock signal lines 201, ten second clock signal lines 202, and five second clock signal lines 202.
  • the connection mode of the clock signal line is the same.
  • the shift register unit 101 of each even-numbered stage can be connected to a first clock signal line 201 and a second clock signal line 202 respectively.
  • two first clock signal lines 201 connected to two adjacent stages of shift registers 101 may be connected.
  • the first clock signal line 201 connected to the first-stage shift register unit 101(1) can be connected to the first clock signal line 201 connected to the second-stage shift register unit 101(2).
  • the gate driving circuit 10 may also use clocks with other phase numbers, for example, a six-phase clock and an eight-phase clock.
  • n is an integer greater than or equal to 1.
  • each shift register unit 101 of the odd number stage can be respectively connected to a first clock signal line 201 and a second clock signal line 202.
  • the input terminal STU of the first-stage shift register unit 101 may be connected to an input signal line, and the input signal line is used to provide an input signal for the first-stage shift register unit 101.
  • the input terminal STU of each stage of shift register unit in the first n+1 stages of shift register unit in the gate drive circuit 10 needs to be connected to an input signal line.
  • the array substrate when the array substrate includes 10 first clock signal lines 201, 10 second clock signal lines 202, and 5 third clock signal lines 203, by making every two first clock signal lines 201 A third clock signal line 203 is connected to the same first test terminal 301, so that all ten second clock signal lines 202 are connected to a second test terminal 302.
  • the 15 first test terminals 301 required to be set are reduced to only 5 first test terminals 301 and 10 second test terminals 302 are required. It is reduced to only one second test terminal 302.
  • the embodiments of the present disclosure provide two ways to connect at least two clock signal lines to the same test terminal:
  • one clock signal line can be directly connected to the test terminal, and at least two clock signal lines The signal lines can be connected in sequence.
  • one third clock signal line 203 is directly connected to the first test terminal 301, and the two first clock signal lines 201 and the third The clock signal line 203 can be connected in sequence through a connecting line.
  • one first clock signal line 201 is directly connected to the first test terminal 301, two first clock signal lines 201 and one third The clock signal lines 203 are sequentially connected by connecting lines.
  • one target clock signal line is directly connected to the test terminal, and among the at least two clock signal lines except for the target clock signal line Each external clock signal line is connected to the target clock signal line.
  • one target first clock signal line 201 can be directly connected to the first test terminal 301,
  • the other first clock signal line 201 and the third clock signal line 203 may be connected to the target first clock signal line 201 through connecting lines, respectively.
  • the array substrate provided by the embodiment of the present disclosure may further include a plurality of pixel circuits arranged in an array.
  • FIG. 10 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure. As shown in FIG. 10, each pixel circuit may include a switching transistor K1, a driving transistor K2, a detection transistor K3, and a storage capacitor C1.
  • the gate of the switching transistor K1 may be connected to the first gate line G1
  • the first pole of the switching transistor K1 may be connected to the data signal terminal D1
  • the second pole of the switching transistor K1 may be connected to the gate of the driving transistor T1 connection.
  • the first pole of the driving transistor K1 may be connected to the DC power supply terminal VDD, and the second pole of the driving transistor K1 may be connected to one end of the light-emitting element O1.
  • the gate of the detection transistor K3 can be connected to the second gate line G2, the first pole of the detection transistor K3 can be connected to one end of the light-emitting element O1, and the second pole of the detection transistor K3 can be connected to the detection signal line S1.
  • the driving signal applied to the light-emitting element O1 can be obtained through the detection signal line S1.
  • One end of the storage capacitor C1 may be connected to the gate of the driving transistor K1, and the other end may be connected to one end of the light-emitting element O1.
  • the transistors in the pixel circuit may all be N-type transistors.
  • the transistors in the pixel circuit may also be P-type transistors.
  • the embodiments of the present disclosure provide an array substrate, which includes a plurality of clock signal lines and a plurality of test terminals. Since at least two clock signal lines of the multiple clock signal lines can be connected to the same test terminal, compared to the connection of one clock signal line to one test terminal in the related art, the array substrate provided by the embodiment of the present disclosure requires The number of test terminals is relatively small. Correspondingly, the number of pins required to be included in the test device connected to the test terminal on the array substrate provided by the embodiment of the present disclosure can be less, and the production cost of the test device is lower and the volume is smaller. small.
  • FIG. 11 is a flowchart of a method for testing an array substrate provided by an embodiment of the present disclosure. The method may be used to test the array substrate shown in any one of FIGS. 1 to 10. As shown in FIG. 11, the method may include:
  • Step 1011 respectively connect the test equipment to each test terminal in the array substrate.
  • the test equipment may include a plurality of pins. During testing, each test terminal can be connected to a pin of the test equipment, and the pins connected to each test terminal are different.
  • Step 1012 Provide clock signals to multiple clock signal lines in the array substrate through each test terminal.
  • the test terminal may be connected to the clock signal line.
  • FIGS. 1 to 6 it can be seen that at least two clock signal lines on the array substrate provided by the embodiments of the present disclosure can be connected to the same test terminal.
  • the test equipment can provide a clock signal to each test terminal connected to it, so that each test terminal outputs the clock signal to the connected clock signal line.
  • Step 1013 Obtain driving signals applied to the light-emitting element by each pixel circuit in the array substrate.
  • the driving signal may include a driving voltage or a driving current output by the pixel circuit to the light-emitting element.
  • the gate driving circuit may be connected to the clock signal line. After the test equipment provides the clock signal to the clock signal line through the test terminal, the gate driving circuit can drive the pixel circuit to load the driving signal to the light-emitting unit under the control of the clock signal provided by the clock signal line. Furthermore, the test equipment can obtain the driving signal loaded by the pixel circuit to the light-emitting element through the detection signal line connected to the pixel circuit, and analyze the driving signal, so as to realize the performance detection of the transistor included in the pixel circuit, for example, Detection of whether the threshold voltage of the driving transistor in the pixel circuit drifts.
  • the circuit for providing the clock signal in the test equipment and the circuit for obtaining the driving signal may be two independent circuits, or may also be an integrated circuit integrated on a chip.
  • the embodiments of the present disclosure provide a testing method for an array substrate. Because of the multiple clock signal lines in the array substrate tested by the test method, at least two clock signal lines can be connected to the same test terminal. Therefore, compared with the connection of one clock signal line to one test terminal in the related art, the embodiment of the present disclosure The number of test terminals that need to be provided on the array substrate to be tested is small. Accordingly, the number of pins of the test equipment used in the test can be less, and the production cost of the test equipment is lower and the volume is smaller.
  • the multiple clock signal lines 20 in the array substrate may include: multiple first clock signal lines 201, multiple second clock signal lines 202, and multiple third clocks Signal line 203.
  • the multiple testing terminals 30 may include multiple first testing terminals 301 and one second testing terminal 302.
  • every two first clock signal lines 201 can be connected to the same first test terminal 301
  • a plurality of second clock signal lines 202 can all be connected to one second test terminal 302
  • each third clock signal line 203 can Connect with a first test terminal 301.
  • the plurality of clock signal lines 20 shown therein include ten first clock signal lines 201, ten second clock signal lines 202, and five third clock signal lines 203.
  • the multiple test terminals 30 include: 5 first test terminals 301 and 1 second test terminal 302. Among the 10 first clock signal lines 201, every two first clock signal lines 201 are connected to one first test terminal 301 , The ten second clock signal lines 202 are all connected to one second test terminal 302, and each of the five third clock signal lines 203 is connected to one first test terminal 301.
  • the above step 1012 may include: sequentially supplying clock signals to the plurality of first clock signal lines 201 and the plurality of third clock signal lines 203 through the first test terminal 301. Through the second test terminal 302, a clock signal at a valid potential is provided to a plurality of second clock signal lines 202.
  • FIG. 12 is a timing diagram of output signals from each signal terminal in a gate driving circuit provided by an embodiment of the present disclosure.
  • the test equipment can transmit the first third clock signal line 203(1), the second third clock signal line 203(1) and the second third clock signal line 203 of the five third clock signal lines 203 included in the array substrate through the first test terminal 301.
  • the signal line 203(2), the third third clock signal line 203(3), the fourth third clock signal line 203(4), and the fifth third clock signal line 203(5) sequentially provide clock signals.
  • test equipment can also pass The first test terminal 301 provides the same clock signal to the two first clock signal lines 201 connected to the third clock signal line 203.
  • the test equipment can provide a clock signal at an effective potential to each of the ten second clock signal lines 202 through a second test terminal 302.
  • the effective potential duration of the clock signal provided by the test equipment to each third clock signal line 203 can be 4a, and the invalid potential duration can be 6a, which is the duty cycle of the clock signal. It can be 40 percent (ie 2/5).
  • the interval at which the test equipment provides clock signals to two adjacent third clock signal lines 203 can be 2a. That is, the interval between the rising edges of the clock signal provided to every two adjacent third clock signal lines 203 is 1/5 of the period of the clock signal.
  • the first-stage shift register unit 101(1) when the potential provided by the test equipment for the first third clock signal line 203(1) is an effective potential, the first-stage The switch output terminal OUT1 and the shift output terminal OUT3 of the shift register unit 101(1) can output signals of effective potential.
  • the potential provided by the test equipment for the first third clock signal line 203(1) jumps to an invalid potential, the potentials of the signals output from the switch output terminal OUT1 and the shift output terminal OUT3 also jump to an invalid potential.
  • the clock signal provided by the test equipment to the second clock signal line 202 is always at a valid potential, so the first-stage shift register unit 101(1) can be valid at the potential of its input terminal STU At the time of potential, the signal of the effective potential is output through the detection output terminal OUT2.
  • the reset terminal STD of the first-stage shift register unit 101(1) is connected to the shift output terminal OUT3 of the seventh-stage shift register unit 101(7), the seventh-stage shift register unit 101 The shift output terminal OUT3 of (7) is used to output the clock signal provided by the fourth third clock signal line 203(4). Therefore, as shown in FIG.
  • the shift output terminal of the seventh stage shift register unit 101 (7) OUT3 can reset the first stage shift register unit 101(1).
  • the first-stage shift register unit 101(1) detects that the potential of the signal output from the output terminal OUT2 jumps from an effective potential to an ineffective potential.
  • the effective potential of the clock signal provided by the test device to the third clock signal line 203 through the first test terminal 301 may be 24 volts (V), and the ineffective potential may be -10V. That is, the potential change range of the clock signal can be -10V to 24V.
  • the test equipment passes through the second test terminal 302, and the potential of the clock signal of the effective potential provided to each second clock signal line 202 may be 24V.
  • the effective potential of the output signal of the switch output terminal OUT1, the detection output terminal OUT2 and the shift output terminal OUT3 can be 24V, and the invalid potential can be -6V.
  • FIG. 13 is a timing simulation diagram of a certain column of light-emitting elements in the array substrate shown in FIG. 6 as an example.
  • the horizontal axis can represent time in microseconds ( ⁇ s)
  • the vertical axis can represent voltage and current values.
  • the unit of voltage value is volt (V)
  • the unit of current value is microampere ( ⁇ A). ).
  • FIG. 13 shows three shift register units 101 located in the same column, and each shift register unit outputs a clock signal to its switch output terminal OUT1 and detection output terminal OUT2.
  • the three shift register units 101 can sequentially output clock signals to their switch output terminals OUT1, that is, the three output terminals OUT1 can sequentially output clock signals, and each shift register unit can switch to its switch output terminal OUT1.
  • the effective potential of the clock signal output by the output terminal OUT1 is about 20V, and the invalid potential is about -5V.
  • the clock signals output by the three shift register units 101 to the detection output terminal OUT2 are all the same, and the potential of the clock signal of the effective potential output by the shift register unit 101 to the detection output terminal OUT2 is about 20V.
  • the driving voltage V(O1) and the driving current I of each pixel circuit applied to the light-emitting element O1 connected to it are (O1) Same.
  • the driving voltage V(O1) of each pixel circuit applied to the light-emitting element O1 connected to it can be stabilized at the same time.
  • the three driving voltages V(O1) shown in FIG. 13 are at 53 ⁇ s, they are all about 7V.
  • the driving current I(O1) loaded by each pixel circuit to the light-emitting element O1 connected to it can also stabilize at the same time.
  • the three driving currents I(O1) shown in FIG. 13 are all approximately at 53 ⁇ s. -5 ⁇ A.
  • the embodiments of the present disclosure provide a testing method for an array substrate. Because of the multiple clock signal lines in the array substrate tested by the test method, at least two clock signal lines can be connected to the same test terminal. Therefore, compared with the connection of one clock signal line to one test terminal in the related art, the embodiment of the present disclosure The number of test terminals that need to be set on the array substrate to be tested is small. Accordingly, the number of pins of the test equipment used in the test can be less, and the production cost of the test equipment is lower and the volume is smaller.

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Abstract

提供了一种阵列基板及其测试方法，该阵列基板包括多条时钟信号线和多个测试端。由于多条时钟信号线中的至少两条时钟信号线可以与同一个测试端连接，因此相对于相关技术中一条时钟信号线与一个测试端连接，本公开实施例提供的阵列基板上所需设置的测试端数量较少，相应的，与本公开实施例提供的阵列基板上的测试端连接的测试设备所需包含的引脚数量即可以较少，测试设备的生产成本即较低，体积较小。

Description

阵列基板及其测试方法
本公开要求于2019年6月18日提交的申请号为201910528155.5、发明名称为“阵列基板及其测试方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，特别涉及一种阵列基板及其测试方法。
背景技术
阵列基板行驱动(gate driver on array，GOA)技术可以将栅极驱动电路集成在阵列基板上，从而减小显示装置的边框。栅极驱动电路可以与多条时钟信号线和像素单元连接，栅极驱动电路可以根据时钟信号线提供的时钟信号，控制像素单元工作。
相关技术中，为了保证产品良率，可以在出厂前对栅极驱动电路进行性能测试，例如，阵列测试(array test，AT)。在进行测试时，可以在阵列基板上设置多个测试端，每个测试端可以分别与一条时钟信号线和测试设备的一个引脚连接，测试设备可以通过各个测试端向各条时钟信号线提供时钟信号。
发明内容
本公开提供了一种阵列基板及其测试方法。所述方案如下：
一方面，提供了一种阵列基板，所述阵列基板包括：栅极驱动电路、多条时钟信号线和多个测试端，所述时钟信号线的数量大于所述测试端的数量；
所述多条时钟信号线分别与所述栅极驱动电路和所述多个测试端连接，且至少两条时钟信号线与同一个所述测试端连接；
所述多个测试端用于与测试设备连接。
可选的，所述栅极驱动电路包括多个级联的移位寄存器单元，所述多条时钟信号线包括：多条第一时钟信号线和多条第二时钟信号线，每个所述移位寄存器单元用于将所述第一时钟信号线提供的时钟信号输出至与第一栅线连接的 开关输出端，以及用于将所述第二时钟信号线提供的时钟信号输出至与第二栅线连接的检测输出端，所述多个测试端包括：多个第一测试端和至少一个第二测试端；
所述多条第一时钟信号线中，至少两条第一时钟信号线与同一个所述第一测试端连接；
所述多条第二时钟信号线中，至少两条第二时钟信号线与同一个所述第二测试端连接。
可选的，所述多个测试端包括：一个所述第二测试端，所述多条第二时钟信号线均与一个所述第二测试端连接。
可选的，至少两条相邻的所述第一时钟信号线与同一个所述第一测试端连接。
可选的，所述多条第一时钟信号线中，每两条所述第一时钟信号线与同一个所述第一测试端连接。
可选的，所述多条时钟信号线还包括：多条第三时钟信号线，所述多个级联的移位寄存器单元中，奇数级或偶数级移位寄存器单元与第三时钟信号线连接，用于将所述第三时钟信号线提供的时钟信号输出至移位输出端；
所述多条第三时钟信号线中，每条所述第三时钟信号线与一个所述第一测试端连接，且各个所述第三时钟信号线连接的所述第一测试端不同。
可选的，每条所述第三时钟信号线与一个所述第一测试端直接连接，且所述至少两条第一时钟信号线均与一条所述第三时钟信号线连接。
可选的，所述至少两条第一时钟信号线与同一个所述第一测试端直接连接，每条所述第三时钟信号线与所述至少两条第一时钟信号线中的一条第一时钟信号线连接。
可选的，所述多条时钟信号线包括：10条所述第一时钟信号线、10条所述第二时钟信号线和5条所述第三时钟信号线。
可选的，每个与第三时钟信号线连接的移位寄存器单元的移位输出端与两级移位寄存器单元的输入端连接，所述两级移位寄存器单元相邻。
可选的，每个所述移位寄存器单元包括：移位子电路、第一输出晶体管和第二输出晶体管；
所述移位子电路与上拉节点连接；
所述第一输出晶体管的栅极与所述上拉节点连接，所述第一输出晶体管的第一极与一条所述第一时钟信号线连接，所述第一输出晶体管的第二极与所述开关输出端连接；
所述第二输出晶体管的栅极与所述上拉节点连接，所述第二输出晶体管的第一极与一条所述第二时钟信号线连接，所述第二输出晶体管的第二极与所述检测输出端连接。
可选的，所述阵列基板还包括：下拉电源线；每个所述移位寄存器单元还包括：第一下拉晶体管和第二下拉晶体管；所述移位子电路还与下拉节点连接；
所述第一下拉晶体管的栅极与所述下拉节点连接，所述第一下拉晶体管的第一极与下拉电源线连接，所述第一下拉晶体管的第二极与所述开关输出端连接；
所述第二下拉晶体管的栅极与所述下拉节点连接，所述第二下拉晶体管的第一极与所述下拉电源线连接，所述第二下拉晶体管的第二极与所述检测输出端连接。
可选的，与同一个所述测试端连接的所述至少两条时钟信号线中，一条所述时钟信号线与所述测试端直接连接，且所述至少两条时钟信号线依次连接。
可选的，与同一个所述测试端连接的所述至少两条时钟信号线中，一条目标时钟信号线与所述测试端直接连接，且所述至少两条时钟信号线中除所述目标时钟信号线之外的每条所述时钟信号线，均与所述目标时钟信号线连接。
可选的，所述阵列基板还包括多个像素电路，每个所述像素电路包括开关晶体管、驱动晶体管、检测晶体管和存储电容；
所述开关晶体管的栅极与所述第一栅线连接，所述开关晶体管的第一极与数据信号端连接，所述开关晶体管的第二极与所述驱动晶体管的栅极连接；
所述驱动晶体管的第一极与直流电源端连接，所述驱动晶体管的第二极与发光元件的一端连接；
所述检测晶体管的栅极与所述第二栅线连接，所述检测晶体管的第一极与所述发光元件的一端连接，所述检测晶体管的第二极与检测信号线连接；
所述存储电容的一端与所述驱动晶体管的栅极连接，另一端与所述发光元件的一端连接。
另一方面，提供了一种阵列基板的测试方法，用于测试如上述方面所述的 阵列基板，所述方法包括：
将测试设备与所述阵列基板中的每个测试端分别连接；
通过每个所述测试端向所述阵列基板中的多条时钟信号线提供时钟信号；
获取所述阵列基板中各个像素电路加载至发光元件的驱动信号。
可选的，所述多条时钟信号线包括：多条第一时钟信号线、多条第二时钟信号线和多条第三时钟信号线，所述多个测试端包括：多个第一测试端和一个第二测试端，每两条所述第一时钟信号线与同一个所述第一测试端连接，所述多条第二时钟信号线均与一个所述第二测试端连接，每条所述第三时钟信号线与一个所述第一测试端连接；
所述通过每个所述测试端向所述阵列基板中的多条时钟信号线提供时钟信号，包括：
通过所述第一测试端，向所述多条第一时钟信号线和所述多条第三时钟信号线依次提供时钟信号；
通过所述第二测试端，向所述多条第二时钟信号线提供处于有效电位的时钟信号
可选的，向所述多条第一时钟信号线和所述多条第三时钟信号线提供的时钟信号的占空比为2/5，且向每相邻两条所述第三时钟信号线提供的时钟信号的上升沿的间隔为所述时钟信号的周期的1/5。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种阵列基板的结构示意图；
图2是本公开实施例提供的另一种阵列基板的结构示意图；
图3是本公开实施例提供的一种移位寄存器单元的局部结构示意图；
图4是本公开实施例提供的一种第二时钟信号线与测试端的连接示意图；
图5是本公开实施例提供的一种第一时钟信号线与测试端的连接示意图；
图6是本公开实施例提供的又一种阵列基板的结构示意图；
图7是本公开实施例提供的一种第一时钟信号线与第一测试端，以及第三时钟信号线与第一测试端的连接示意图；
图8是本公开实施例提供的另一种第一时钟信号线与第一测试端，以及第三时钟信号线与第一测试端的连接示意图；
图9是本公开实施例提供的再一种阵列基板的结构示意图；
图10是本公开实施例提供的一种阵列基板包括的像素电路的结构示意图；
图11是本公开实施例提供的一种阵列基板的测试方法流程图；
图12是本公开实施例提供的一种阵列基板中各信号的时序图；
图13是本公开实施例提供的一种阵列基板中各信号的时序仿真图。
具体实施方式
为了使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件，根据在电路中的作用本公开的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，将其中源极称为第一极，漏极称为第二极。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外，本公开实施例所采用的开关晶体管可以包括P型开关晶体管和N型开关晶体管中的任一种，其中，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型开关晶体管在栅极为高电平时导通，在栅极为低电平时截止。
为了保证产品良率，需要在阵列基板出厂前通过AT测试设备对阵列基板进行检测，并且需要通过成盒测试(cell test，CT)设备对显示面板进行检测。阵列基板上一般可以包括：时钟信号线、栅极驱动电路和阵列排布的多行像素电路。每行像素电路可以与至少两条栅线连接，栅极驱动电路可以与时钟信号线和栅线连接。栅极驱动电路可以将时钟信号线提供的时钟信号作为栅极驱动信号输出至栅线，栅线可以将栅极驱动信号输出至像素电路，像素电路可以在该栅极驱动信号的驱动下工作。
由于信号线交叉处易产生寄生电容和寄生电阻，该寄生电容和寄生电阻会造成信号的传输出现延迟。因此为了减小信号延迟的影响，栅极驱动电路可以与多条时钟信号线连接，且对于高分辨率的显示面板，栅极驱动电路所需连接的时钟信号线数量可能更多。而由于相关技术中，在进行测试时，每条时钟信号线均需要与一个测试端连接，每个测试端需要与测试设备上的一个引脚连接。因此，当时钟信号线的数量较多时，阵列基板上所需设置的测试端的数量即会较多，相应的，测试设备所需包括的引脚即会较多，阵列基板上设置的测试端的数量甚至可能超过测试设备所能设置的引脚数量的极限。
图1是本公开实施例提供的一种阵列基板的结构示意图。如图1所示，该阵列基板可以包括：栅极驱动电路10、多条时钟信号线20和多个测试端30。且时钟信号线20的数量可以大于测试端30的数量。
在本公开实施例中，多条时钟信号线20可以分别与栅极驱动电路10和多个测试端30连接，且至少两条时钟信号线20可以与同一个测试端30连接。
多个测试端30可以用于与测试设备连接。并且，每个测试端30可以与测试设备的一个引脚连接，且各个测试端30所连接的引脚不同。可选的，该测试设备可以是进行AT测试的AT设备，或者，也可以是进行CT测试的CT设备。
示例的，参考图1，该多条时钟信号线20中，每两条时钟信号线20与同一个测试端30连接。若该阵列基板包括10条时钟信号线20，则该阵列基板上仅需设置5个测试端30即可。而由于相关技术中每条时钟信号线与一个测试端连接，则相关技术中的阵列基板上即需设置10个测试端。本公开实施例提供的阵列基板上所需设置的测试端的数量，相对于相关技术提供的阵列基板上所需设置的测试端的数量减少了一半。相应的，与本公开实施例提供的阵列基板上的测试端连接的测试设备所需包括的引脚的数量，相对于相关技术提供的阵列基板上的测试端连接的测试设备所需包括的引脚的数量也减少了一半，节省成本。
综上所述，本公开实施例提供了一种阵列基板，该阵列基板包括多条时钟信号线和多个测试端。由于多条时钟信号线中的至少两条时钟信号线可以与同一个测试端连接，因此相对于相关技术中一条时钟信号线与一个测试端连接，本公开实施例提供的阵列基板上所需设置的测试端数量较少，相应的，与本公开实施例提供的阵列基板上的测试端连接的测试设备所需包含的引脚数量即可 以较少，测试设备的生产成本即较低，体积较小。
图2是本公开实施例提供的另一种阵列基板的结构示意图。如图2所示，栅极驱动电路10可以包括多个级联的移位寄存器单元101。多条时钟信号线20可以包括：多条第一时钟信号线201和多条第二时钟信号线202。
每个移位寄存器单元101可以用于将第一时钟信号线201提供的时钟信号输出至与第一栅线连接的开关输出端OUT1，以及用于将第二时钟信号线202提供的时钟信号输出至与第二栅线连接的检测输出端OUT2。其中，该第一栅线可以用于向阵列基板包括的像素电路中的开关晶体管提供栅极驱动信号，该第二栅线可以用于向像素电路中的检测晶体管提供栅极驱动信号。
可选的，图3是本公开实施例提供的一种移位寄存器单元的局部结构示意图。参考图2和图3可以看出，每个移位寄存器单元101可以包括：移位子电路1011，以及第一输出晶体管T1、第二输出晶体管T2、输入端STU、第一时钟信号端CLK1和第二时钟信号端CLK2。
参考图3，移位子电路1011可以分别与输入端STU和上拉节点Q连接。第一输出晶体管T1的栅极可以与上拉节点Q连接，第一极可以与第一时钟信号端CLK1连接，第二极可以与开关输出端OUT1连接。第二输出晶体管T2的栅极可以与上拉节点Q连接，第一极可以与第二时钟信号端CLK1连接，第二极可以与检测输出端OUT2连接。参考图2，第一时钟信号线201可以与移位寄存器单元中的第一时钟信号端CLK1连接，第二时钟信号线202可以与移位寄存器单元中的第二时钟信号端CLK2连接。
可选的，参考图2，该开关输出端OUT1还可以与其他移位寄存器101的输入端STU连接。例如，图2中的第一级移位寄存器单元101(1)的开关输出端OUT1，可以与第五级移位寄存器单元101(5)的输入端STU以及第六级移位寄存器单元(图2中未示出)的输入端STU连接。
在本公开实施例中，每个移位寄存器单元101可以在上拉节点Q为有效电位时，将第一时钟信号线201向第一时钟信号端CLK1提供的时钟信号，通过第一输出晶体管T1输出至开关输出端OUT1。每个移位寄存器单元101可以在上拉节点Q为有效电位时，将第二时钟信号线202向第二时钟信号端CLK2提供的时钟信号，通过第二输出晶体管T2输出至检测输出端OUT2。
可选的，参考图2，该多个测试端30可以包括：多个第一测试端301和至少一个第二测试端302。多条第一时钟信号线201中，至少两条第一时钟信号线201可以与同一个第一测试端301连接，且每个第一测试端301可以均与至少一条第一时钟信号线201连接。多条第二时钟信号线202中，至少两条第二时钟信号线202与同一个第二测试端302连接。
示例的，参考图2，多条时钟信号线20包括10条第一时钟信号线201和10条第二时钟信号线202。多个测试端30包括5个第一测试端301和1个第二测试端302。10条第一时钟信号线201中每两条第一时钟信号线201与同一个第一测试端301连接。10条第二时钟信号线202均与一个第二测试端302连接。
可选的，图4是本公开实施例提供的一种第二时钟信号线与第二测试端的连接示意图。参考图2和图4可以看出，该多个测试端可以仅包括：一个第二测试端302，多条第二时钟信号线202可以均与该一个第二测试端302连接。
参考图3可以看出，与检测信号端OUT2连接的第二输出晶体管T2的栅极与上拉节点Q连接，即第二输出晶体管T2的工作状态是由上拉节点Q的电位控制。上拉节点Q的电位是由与其级联的移位寄存器单元101的开关输出端OUT1输出的信号控制。
在本公开实施例中，可以通过多个第一测试端301向各条第一时钟信号线201依次提供处于有效电位的时钟信号，相应的，各个移位寄存器单元101即可以向各个开关输出端OUT1依次输出处于有效电位的时钟信号，从而使得各个移位寄存器单元101的上拉节点Q可以依次处于有效电位，即可以控制各个移位寄存器单元101中的第二输出晶体管T2依次开启。因此，设置一个第二测试端302与所有的第二时钟信号线202连接，并通过该一个第二测试端302向所有的第二时钟信号线202提供处于有效电位的信号，可以使得各个移位寄存器单元向各个检测输出端OUT2依次输出处于有效电位的信号，即向多条第二栅线依次输出处于有效电位的栅极驱动信号，相应的，位于同一列的多个像素电路中的检测晶体管即可以依次开启，可以在保证阵列基板正常工作的前提下，进一步减少阵列基板上所需设置的测试端30的数量。
可选的，在本公开实施例中，至少两条相邻的第一时钟信号线201可以与同一个第一测试端301连接。
例如，参考图2，每两条相邻的第一时钟信号线201可以与一个第一测试端 301连接。通过设置至少两条相邻的第一时钟信号线201与同一个第一测试端301连接，可以在减少所需设置的测试端数量的前提下，简化布线工艺。
可选的，图5是本公开实施例提供的第一时钟信号线与第一测试端的可选连接示意图。参考图2和图5可以看出，多条第一时钟信号线201中，每两条第一时钟信号线201可以与同一个第一测试端301连接。
由于每个移位寄存器单元101是将第一时钟信号线201提供的时钟信号输出至与第一栅线连接的开关输出端OUT1，因此当每两条第一时钟信号线201与一个第一测试端301连接时，与同一个第一测试端301连接的两条第一时钟信号线201提供的时钟信号即完全相同。相应的，与该两条第一时钟信号线201连接的两个移位寄存器单元101，向其开关输出端OUT1输出的时钟信号即完全相同。又由于第一栅线用于向开关晶体管提供栅极驱动信号，因此可以使得两条第一栅线向两行像素电路中的开关晶体管同时输出栅极驱动信号，即在同一时刻可以同时驱动两行像素单元。在减少阵列基板上所需设置的测试端数量的前提下，还保证了对阵列基板进行测试时，显示装置的显示效果，确保了显示装置的分辨率。
图6是本公开实施例提供的另一种阵列基板的结构示意图。如图6所示，该多条时钟信号线20还可以包括：多条第三时钟信号线203。该多个级联的移位寄存器单元101中，每个奇数级或偶数级的移位寄存器单元101可以与一条第三时钟信号线203连接，并可以将第三时钟信号线203提供的时钟信号输出至移位输出端OUT3。
可选的，参考图3和图6，与第三时钟信号线203连接的每个奇数级的移位寄存器单元101(或每个偶数级的移位寄存器单元101)还可以包括：第三输出晶体管T3和第三时钟信号端CLK3。第三输出晶体管T3的栅极可以与上拉节点Q连接，第一极可以与第三时钟信号端CLK3连接，第二极可以与移位输出端OUT3连接，移位输出端OUT3可以与其他两级移位寄存器单元101的输入端STU连接，且移位输出端OUT3所连接的两级移位寄存器单元101为相邻的两级移位寄存器单元101。例如，图6示出的第一级移位寄存器单元101(1)的移位输出端OUT3可以与第五级移位寄存器单元101(7)的输入端STU以及第六级移位寄存器单元(图中未示出)的输入端STU连接。
并且，该移位输出端OUT3还可以与其他相邻的两级移位寄存器单元101 的复位端STD连接。例如，图6示出的第七级移位寄存器单元101(7)的移位输出端OUT3可以与第一级移位寄存器单元101(1)的复位端STD以及第二级移位寄存器单元101(2)的复位端STD连接。
参考图3，第三时钟信号线203可以与第三时钟信号端CLK3连接，每个与该第三时钟信号线203连接的奇数级或偶数级的移位寄存器单元101可以在上拉节点Q为有效电位时，将第三时钟信号线203向第一时钟信号端CLK3提供的时钟信号，通过第三输出晶体管T3输出至移位输出端OUT3。
可选的，在本公开实施例中，该多条第三时钟信号线203中，每条第三时钟信号线203可以与一个第一测试端301连接，且各个第三时钟信号线203连接的第一测试端301可以不同。
示例的，参考图6，该多条时钟信号线20包括5条第三时钟信号线203，该5条第三时钟信号线203中，每条第三时钟信号线203可以与一个第一测试端301连接。
由于奇数级(或偶数级)移位寄存器单元101可以将第三时钟信号线203提供的时钟信号输出至移位输出端OUT3，且可以将第一时钟信号线201提供的时钟信号输出至与第一栅线连接的开关输出端OUT1，该开关输出端OUT1和移位输出端OUT3输出的信号可以相同。相应的，第三时钟信号线203与第一时钟信号线201提供的时钟信号的时序可以相同。因此可以设置至少两条第一时钟信号线201和每条第三时钟信号线203，与同一个第一测试端301连接，从而可以在保证栅极驱动电路正常工作的前提下，进一步减少阵列基板上所需设置的测试端30的数量。
由于第一时钟信号线201和第三时钟信号线203均与第一测试端301连接，因此，参考图3，每个奇数级(或偶数级)移位寄存器单元101中的第一时钟信号端CLK1和第三时钟信号端CLK3可以为同一个时钟信号端。但是，由于每个奇数级(或偶数级)移位寄存器单元101是将其第一时钟信号端CLK1提供的时钟信号，通过第一输出晶体管T1输出至与第一栅线连接的开关输出端OUT1，且是将其第三时钟信号端CLK3提供的时钟信号，通过第三输出晶体管T3输出至其所级联的移位寄存器单元101的输入端STU。因此为了避免输出至开关输出端OUT1的信号与输出至其他级移位寄存器单元101的信号之间相互干扰，即保证第一输出晶体管T1和第三输出晶体管T3的工作稳定性，在出厂 的实际产品中，该第一时钟信号端CLK1和第三时钟信号端CLK3可以为不同的时钟信号端。
可选的，参考图3和图6，每个移位寄存器单元101还可以包括高电平电源端VGH、VDDA、VDDB和VDD，低电平电源端VGL和LVGL。且各电源端可以与其对应的信号线连接，例如，参考图3，高电平电源端VDDA与信号线VDDA连接。每个移位寄存器单元101还可以包括下拉节点QB，下拉晶体管M1和M2，与第三时钟信号线203连接的奇数级(或偶数级)移位寄存器单元101还可以包括下拉晶体管M3。下拉晶体管M1至M3的栅极可以均与下拉节点QB连接，下拉晶体管M1和M2的第一极可以与低电平电源端VGL连接，该低电平电源端VGL可以与用于提供无效电位的下拉电源线连接。下拉晶体管M3的第一极可以与低电平电源端LVGL连接，下拉晶体管M1的第二极可以与开关输出端OUT1连接，下拉晶体管M2的第二极可以与检测输出端OUT2连接，下拉晶体管M3的第一极可以与移位输出端OUT3连接。
其中，下拉晶体管M1可以在下拉节点QB为有效电位时，向开关输出端OUT1输出低电平电源端VGL提供的无效电位的信号(例如低电平信号)，从而实现对开关输出端OUT1的复位。下拉晶体管M2可以在下拉节点QB为有效电位时，向检测输出端OUT2输出低电平电源端VGL提供的无效电位的信号(例如低电平信号)，从而实现对检测输出端OUT2的复位。下拉晶体管M3可以在下拉节点QB为有效电位时，向移位输出端OUT3输出低电平电源端LVGL提供的无效电位的信号(例如低电平信号)，从而实现对移位输出端OUT3的复位。
可选的，参考图3还可以看出，阵列基板还包括：多个检测电路40(图3中仅示意性示出了一个检测电路40)和一个静电释放电路50。其中每个检测电路40可以与一个移位寄存器单元101的上拉节点Q、时钟信号端CLKA以及使能信号端OE连接。该检测电路40可以用于控制移位寄存器单元101在消隐(blank)期间的时序。
该静电释放电路50可以分别与该多条时钟信号线20和静电释放线连接，该静电释放电路50用于释放该多条时钟信号线20上的静电，以实现静电保护。当然，除了时钟信号线20之外，该静电释放电路50还可以与其他信号线连接。例如参考图3，该静电释放电路50中的电源端ESD_VGH可以与信号线VDDA 连接，电源端ESD_VGL可以与低电平电源端LVGL连接。该静电释放电路50还可以与信号线VDD和信号线VDDB连接。其中，该低电平电源端LVGL所连接的信号线即为静电释放线。
可选的，本公开实施例提供了第一时钟信号线201和第三时钟信号线203与第一测试端301连接的两种方式：
作为一种可选的实现方式，参考图6和图7，每条第三时钟信号线203可以与一个第一测试端301直接连接，且至少两条第一时钟信号线201可以均与一条第三时钟信号线203连接。例如，图6和图7所示的阵列基板中，每两条第一时钟信号线201与一条第三时钟信号线203连接。
其中，如图6和图7所示，每两条第一时钟信号线201之间可以通过连接线建立连接，仅其中一条第一时钟信号线201直接与一条第三时钟信号线203连接。当然，每两条第一时钟信号线201中的每条第一时钟信号线201，可以均直接与一条第三时钟信号线203连接。
作为另一种可选的实现方式，参考图2和图8，至少两条第一时钟信号线201可以与同一个第一测试端301直接连接，每条第三时钟信号线203可以与至少两条第一时钟信号线201中的一条第一时钟信号线201连接。例如，图2和图8示出的阵列基板中，每两条第一时钟信号线201与一个第一测试端301直接连接，每条第三时钟信号线203与每两条第一时钟信号线201中的一条第一时钟信号线201连接。
其中，参考图2和图8，每两条第一时钟信号线201之间可以通过连接线建立连接，仅其中一条第一时钟信号线201直接与一个第一测试端301连接。当然，每两条第一时钟信号线201中的每条第一时钟信号线201，可以分别与同一个第一测试端301直接连接。
可选的，参考图6可以看出，本公开实施例提供的阵列基板中的多条时钟信号线可以包括：10条第一时钟信号线201、10条第二时钟信号线202和5条第三时钟信号线203。也即是，该栅极驱动电路10可以采用十相时钟，即每10级移位寄存器单元101，与10条第一时钟信号线201和10条第二时钟信号线202依次一一对应连接。
图2和图6仅示出了奇数级移位寄存器单元101，且以奇数级移位寄存器单元101与第三时钟信号线203连接为例进行示意。对于偶数级的移位寄存器单 元101，如图9所示，其与时钟信号线的连接方式同理。参考图9可以看出，每个偶数级的移位寄存器单元101可以分别与一条第一时钟信号线201和一条第二时钟信号线202连接。并且，相邻两级移位寄存器101所连接的两条第一时钟信号线201可以相连。例如，第一级移位寄存器单元101(1)所连接的第一时钟信号线201，与第二极移位寄存器单元101(2)所连接的第一时钟信号线201可以相连。栅极驱动电路10也可以采用其他相数的时钟，例如，六相时钟和八相时钟。
并且，在该连接方式中，栅极驱动电路10中的前n级移位寄存器单元中的每一级移位寄存器单元的输入端STU需要与一条输入信号线连接，该输入信号线用于为该级移位寄存器单元101提供输入信号。其中，n为大于或等于1的整数。例如，参考图9，n＝6，即前6级移位寄存器单元中的每一级移位寄存器单元的输入端STU需要与一条输入信号线连接。
若偶数级的移位寄存器单元101与第三时钟信号线203连接，则每个奇数级的移位寄存器单元101可以分别与一条第一时钟信号线201和一条第二时钟信号线202连接。并且，第一级移位寄存器单元101的输入端STU可以与一条输入信号线连接，该输入信号线用于为该第一级移位寄存器单元101提供输入信号。在该连接方式中，栅极驱动电路10中的前n+1级移位寄存器单元中的每一级移位寄存器单元的输入端STU需要与一条输入信号线连接。例如，参考图9，n＝6，则栅极驱动电路10中的前7级移位寄存器单元中的每一级移位寄存器单元的输入端STU需要与一条输入信号线连接。
基于上述分析可知，将奇数级移位寄存器单元101与第三时钟信号线203连接，可以减少栅极驱动电路10中需要连接输入信号线的移位寄存器单元101的个数。
在本公开实施例中，当阵列基板包括10条第一时钟信号线201、10条第二时钟信号线202和5条第三时钟信号线203时，通过使每两条第一时钟信号线201和一条第三时钟信号线203与同一个第一测试端301连接，使10条第二时钟信号线202均与一个第二测试端302连接。相对于相关技术中每条时钟信号线与一个测试端连接，将所需设置15个第一测试端301减少为仅需设置5个第一测试端301，所需设置10个第二测试端302减少为仅需设置1个第二测试端302。
可选的，本公开实施例提供了两种至少两条时钟信号线与同一个测试端的连接方式：
作为一种可选的实现方式，参考图2、图7和图8，与同一个测试端连接的至少两条时钟信号线中，一条时钟信号线可以与测试端直接连接，且至少两条时钟信号线之间可以依次连接。
例如，参考图7，与同一个第一测试端301连接的三条时钟信号线中，一条第三时钟信号线203直接与第一测试端301连接，两条第一时钟信号线201和该第三时钟信号线203可以通过连接线依次连接。或者，参考图8，与同一个第一测试端301连接的三条时钟信号线中，一条第一时钟信号线201直接与第一测试端301连接，两条第一时钟信号线201和一条第三时钟信号线203通过连接线依次连接。
作为另一种可选的实现方式，与同一个测试端连接的至少两条时钟信号线中，一条目标时钟信号线与测试端直接连接，且至少两条时钟信号线中除目标时钟信号线之外的每条时钟信号线，均与目标时钟信号线连接。
示例的，对于图6所示的阵列基板，与同一个第一测试端301连接的两条第一时钟信号线201中，一条目标第一时钟信号线201可以与第一测试端301直接连接，另一条第一时钟信号线201和一条第三时钟信号线203，可以分别通过连接线与该目标第一时钟信号线201连接。
本公开实施例提供的阵列基板还可以包括多个阵列排布的像素电路。图10是本公开实施例提供的一种像素电路的结构示意图。如图10所示，每个像素电路可以包括开关晶体管K1、驱动晶体管K2、检测晶体管K3和存储电容C1。
参考图10，该开关晶体管K1的栅极可以与第一栅线G1连接，开关晶体管K1的第一极可以与数据信号端D1连接，开关晶体管K1的第二极可以与驱动晶体管T1的栅极连接。
驱动晶体管K1的第一极可以与直流电源端VDD连接，驱动晶体管K1的第二极可以与发光元件O1的一端连接。
检测晶体管K3的栅极可以与第二栅线G2连接，检测晶体管K3的第一极可以与发光元件O1的一端连接，检测晶体管K3的第二极可以与检测信号线S1连接。在测试时，可以通过检测信号线S1获取加载至发光元件O1的驱动信号。
存储电容C1的一端可以与驱动晶体管K1的栅极连接，另一端可以与发光 元件O1的一端连接。
可选的，该像素电路中的晶体管可以均为N型晶体管，当然，该像素电路中的晶体管也可以均为采用P型晶体管。
综上所述，本公开实施例提供了一种阵列基板，该阵列基板包括多条时钟信号线和多个测试端。由于多条时钟信号线中的至少两条时钟信号线可以与同一个测试端连接，因此相对于相关技术中一条时钟信号线与一个测试端连接，本公开实施例提供的阵列基板上所需设置的测试端数量较少，相应的，与本公开实施例提供的阵列基板上的测试端连接的测试设备所需包含的引脚数量即可以较少，测试设备的生产成本即较低，体积较小。
图11是本公开实施例提供的一种阵列基板的测试方法流程图，该方法可以用于测试如图1至图10任一所示的阵列基板，如图11所示，该方法可以包括：
步骤1011、将测试设备与阵列基板中的每个测试端分别连接。
在本公开实施例中，测试设备可以包括多个引脚。在进行测试时，可以将每个测试端与测试设备的一个引脚连接，且各个测试端所连接的引脚不同。
步骤1012、通过每个测试端向阵列基板中的多条时钟信号线提供时钟信号。
在本公开实施例中，测试端可以与时钟信号线连接。且参考图1至图6可以看出，本公开实施例提供的阵列基板上的至少两条时钟信号线可以与同一个测试端连接。测试设备可以向其所连接的每个测试端提供时钟信号，进而使得每个测试端将该时钟信号输出至其所连接的时钟信号线。
步骤1013、获取阵列基板中各个像素电路加载至发光元件的驱动信号。
其中，该驱动信号可以包括像素电路向发光元件输出的驱动电压或驱动电流。在本公开实施例中，栅极驱动电路可以与时钟信号线连接。当测试设备通过测试端向时钟信号线提供时钟信号后，栅极驱动电路可以在时钟信号线提供的时钟信号的控制下，驱动像素电路向发光单元加载驱动信号。进而，测试设备可以通过像素电路所连接的检测信号线，获取像素电路加载至发光元件的驱动信号，并对该驱动信号进行分析，从而实现对像素电路包括的晶体管的性能检测，例如，可以检测像素电路中驱动晶体管的阈值电压是否发生漂移的检测。
测试设备中用于提供时钟信号的电路，与获取驱动信号的电路可以为相互独立的两个电路，或者也可以为集成在一个芯片上的集成电路。
综上所述，本公开实施例提供了一种阵列基板的测试方法。由于该测试方法测试的阵列基板中的多条时钟信号线，至少两条时钟信号线可以与同一个测试端连接，因此相对于相关技术中一条时钟信号线与一个测试端连接，本公开实施例测试的阵列基板上所需设置的测试端数量较少，相应的，测试时采用的测试设备的引脚数量即可以较少，测试设备的生产成本即较低，体积较小。
可选的，参考图6，本公开实施例提供的阵列基板中的多条时钟信号线20可以包括：多条第一时钟信号线201、多条第二时钟信号线202和多条第三时钟信号线203。多个测试端30可以包括：多个第一测试端301和一个第二测试端302。并且，每两条第一时钟信号线201可以与同一个第一测试端301连接，多条第二时钟信号线202可以均与一个第二测试端302连接，每条第三时钟信号线203可以与一个第一测试端301连接。
例如，参考图6，其示出的多条时钟信号线20包括10条第一时钟信号线201、10条第二时钟信号线202和5条第三时钟信号线203。多个测试端30包括：5个第一测试端301和1个第二测试端302。10条第一时钟信号线201中，每两条第一时钟信号线201与一个第一测试端301连接，10条第二时钟信号线202均与一个第二测试端302连接，5条第三时钟信号线203中每条第三时钟信号线203与一个第一测试端301连接。
相应的，上述步骤1012即可以包括：通过第一测试端301，向多条第一时钟信号线201和多条第三时钟信号线203依次提供时钟信号。通过第二测试端302，向多条第二时钟信号线202提供处于有效电位的时钟信号。
以图6所示的阵列基板为例，并以晶体管为N型晶体管为例，对本公开实施例提供的阵列基板的测试原理进行介绍：
图12是本公开实施例提供的一种栅极驱动电路中各个信号端输出信号的时序图。如图12所示，测试设备可以通过第一测试端301，向阵列基板包括的5条第三时钟信号线203中的第一条第三时钟信号线203(1)、第二条第三时钟信号线203(2)、第三条第三时钟信号线203(3)、第四条第三时钟信号线203(4)和第五条第三时钟信号线203(5)依次提供时钟信号。由于每两条第一时钟信号线201与一条第三时钟信号线203连接，因此在测试设备通过第一测试端301向某条第三时钟信号线203提供时钟信号的同时，测试设备也可以通过该第一测试端301向与该第三时钟信号线203连接的两条第一时钟信号线201 提供相同的时钟信号。并且，参考图12还可以看出，测试设备可以通过一个第二测试端302向10条第二时钟信号线202均提供处于有效电位的时钟信号。
参考图12，在每个时钟周期内，测试设备向每条第三时钟信号线203提供的时钟信号的有效电位持续时长可以为4a，无效电位持续时长可以为6a，即时钟信号的占空比可以为百分之40(即2/5)。且参考图12还可以看出，测试设备向相邻两条第三时钟信号线203提供时钟信号的间隔可以为2a。也即是，向每相邻两条第三时钟信号线203提供的时钟信号的上升沿的间隔为该时钟信号的周期的1/5。
以第一级移位寄存器单元101(1)为例，结合图9和图12，在该测试设备为第一条第三时钟信号线203(1)提供的电位为有效电位时，第一级移位寄存器单元101(1)的开关输出端OUT1和移位输出端OUT3可以输出有效电位的信号。在该测试设备为第一条第三时钟信号线203(1)提供的电位跳变为无效电位时，该开关输出端OUT1和移位输出端OUT3输出的信号的电位也跳变为无效电位。
并且，参考图12可以看出，测试设备向第二时钟信号线202提供的时钟信号始终处于有效电位，因此该第一级移位寄存器单元101(1)可以在其输入端STU的电位为有效电位时，通过其检测输出端OUT2输出有效电位的信号。参考图9，由于该第一级移位寄存器单元101(1)的复位端STD与第七级移位寄存器单元101(7)的移位输出端OUT3连接，该第七级移位寄存器单元101(7)的移位输出端OUT3用于输出第四条第三时钟信号线203(4)提供的时钟信号。因此，如图12所示，在该第四条第三时钟信号线203(4)提供的时钟信号跳变为有效电位时，该第七级移位寄存器单元101(7)的移位输出端OUT3可以对第一级移位寄存器单元101(1)进行复位。此时，该第一级移位寄存器单元101(1)检测输出端OUT2输出的信号的电位由有效电位跳变为无效电位。
可选的，测试设备通过第一测试端301，向第三时钟信号线203提供的时钟信号的有效电位可以为24伏特(V)，无效电位可以为-10V。即该时钟信号的电位变化范围可以为-10V至24V。测试设备通过第二测试端302，向每条第二时钟信号线202提供的有效电位的时钟信号的电位可以为24V。开关输出端OUT1、检测输出端OUT2和移位输出端OUT3输出信号的有效电位可以为24V，无效电位可以为-6V。
可选的，图13是以图6所示的阵列基板中的某一列发光元件为例，示出的时序仿真图。如图13所示，其横轴可以表示时间，单位为微秒(μs)，纵轴可以表示电压值和电流值，其中电压值的单位伏特(V)，电流值的单位为微安(μA)。
例如，图13示出了位于同一列的三个移位寄存器单元101中，每个移位寄存器单元向其开关输出端OUT1和检测输出端OUT2输出的时钟信号。参考图13可以看出，该三个移位寄存器单元101可以依次向其开关输出端OUT1输出时钟信号，即该三个输出端OUT1可以依次输出时钟信号，且每个移位寄存器单元向其开关输出端OUT1输出的时钟信号的有效电位约为20V，无效电位约为-5V。且该三个移位寄存器单元101向其检测输出端OUT2输出的时钟信号均相同，且移位寄存器单元101向检测输出端OUT2输出的有效电位的时钟信号的电位约为20V。
另外，参考图13还可以看出，该三个移位寄存器单元101所连接的三个像素电路中，各个像素电路加载至其所连接的发光元件O1的驱动电压V(O1)和驱动电流I(O1)相同。且各个像素电路加载至其所连接的发光元件O1的驱动电压V(O1)在同一时刻可以趋于稳定，例如，图13示出的三个驱动电压V(O1)在53μs时，均约为7V。各个像素电路加载至其所连接的发光元件O1的驱动电流I(O1)在同一时刻也可以趋于稳定，例如，图13示出的三个驱动电流I(O1)在53μs时，均约为-5μA。
由于将至少两条时钟信号线与同一个测试端连接时，位于同一列的多个像素电路中，各个像素电路加载至其所连接的发光元件O1的驱动电压V(O1)差异，以及加载至其所连接的发光元件O1的驱动电流I(O1)的差异均较小，且驱动电压V(O1)和驱动电流I(O1)均可以趋于稳定状态，因此可知，该连接方式并不会对CT检测和AT检测造成影响。
综上所述，本公开实施例提供了一种阵列基板的测试方法。由于该测试方法测试的阵列基板中的多条时钟信号线，至少两条时钟信号线可以与同一个测试端连接，因此相对于相关技术中一条时钟信号线与一个测试端连接，本公开实施例测试的阵列基板上所需设置的测试端数量较少，相应的，测试时采用的测试设备的引脚数量即可以较少，测试设备的生产成本即较低，体积较小。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的阵列基板和栅极驱动电路的具体工作过程，可以参考前述方法实施例中的对 应过程，在此不再赘述。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (20)

  1. 一种阵列基板，所述阵列基板包括：栅极驱动电路、多条时钟信号线和多个测试端，所述时钟信号线的数量大于所述测试端的数量；
    所述多条时钟信号线分别与所述栅极驱动电路和所述多个测试端连接，且至少两条时钟信号线与同一个所述测试端连接；
    所述多个测试端用于与测试设备连接。
  2. 根据权利要求1所述的阵列基板，所述栅极驱动电路包括多个级联的移位寄存器单元，所述多条时钟信号线包括：多条第一时钟信号线和多条第二时钟信号线，每个所述移位寄存器单元用于将所述第一时钟信号线提供的时钟信号输出至与第一栅线连接的开关输出端，以及用于将所述第二时钟信号线提供的时钟信号输出至与第二栅线连接的检测输出端，所述多个测试端包括：多个第一测试端和至少一个第二测试端；
    所述多条第一时钟信号线中，至少两条第一时钟信号线与同一个所述第一测试端连接；
    所述多条第二时钟信号线中，至少两条第二时钟信号线与同一个所述第二测试端连接。
  3. 根据权利要求2所述的阵列基板，所述多个测试端包括：一个所述第二测试端，所述多条第二时钟信号线均与一个所述第二测试端连接。
  4. 根据权利要求2或3所述的阵列基板，至少两条相邻的所述第一时钟信号线与同一个所述第一测试端连接。
  5. 根据权利要求2至4任一所述的阵列基板，所述多条第一时钟信号线中，每两条所述第一时钟信号线与同一个所述第一测试端连接。
  6. 根据权利要求2至5任一所述的阵列基板，所述多条时钟信号线还包括：多条第三时钟信号线，所述多个级联的移位寄存器单元中，奇数级或偶数级移 位寄存器单元与所述第三时钟信号线连接，用于将所述第三时钟信号线提供的时钟信号输出至移位输出端；
    所述多条第三时钟信号线中，每条所述第三时钟信号线与一个所述第一测试端连接，且各个所述第三时钟信号线连接的所述第一测试端不同。
  7. 根据权利要求6所述的阵列基板，每条所述第三时钟信号线与一个所述第一测试端直接连接，且所述至少两条第一时钟信号线均与一条所述第三时钟信号线连接。
  8. 根据权利要求6所述的阵列基板，所述至少两条第一时钟信号线与同一个所述第一测试端直接连接，每条所述第三时钟信号线与所述至少两条第一时钟信号线中的一条第一时钟信号线连接。
  9. 根据权利要求6至8任一所述的阵列基板，所述多条时钟信号线包括：10条所述第一时钟信号线、10条所述第二时钟信号线和5条所述第三时钟信号线。
  10. 根据权利要求6至9任一所述的阵列基板，每个与所述第三时钟信号线连接的级移位寄存器单元的移位输出端与两级移位寄存器单元的输入端连接，所述两级移位寄存器单元相邻。
  11. 根据权利要求2至10任一所述的阵列基板，所述阵列基板还包括多个像素电路，每个所述像素电路包括开关晶体管、驱动晶体管、检测晶体管和存储电容；
    所述开关晶体管的栅极与所述第一栅线连接，所述开关晶体管的第一极与数据信号端连接，所述开关晶体管的第二极与所述驱动晶体管的栅极连接；
    所述驱动晶体管的第一极与直流电源端连接，所述驱动晶体管的第二极与发光元件的一端连接；
    所述检测晶体管的栅极与所述第二栅线连接，所述检测晶体管的第一极与所述发光元件的一端连接，所述检测晶体管的第二极与检测信号线连接；
    所述存储电容的一端与所述驱动晶体管的栅极连接，另一端与所述发光元件的一端连接。
  12. 根据权利要求1至10任一所述的阵列基板，每个所述移位寄存器单元包括：移位子电路、第一输出晶体管和第二输出晶体管；
    所述移位子电路与上拉节点连接；
    所述第一输出晶体管的栅极与所述上拉节点连接，所述第一输出晶体管的第一极与一条所述第一时钟信号线连接，所述第一输出晶体管的第二极与所述开关输出端连接；
    所述第二输出晶体管的栅极与所述上拉节点连接，所述第二输出晶体管的第一极与一条所述第二时钟信号线连接，所述第二输出晶体管的第二极与所述检测输出端连接。
  13. 根据权利要求12所述的阵列基板，所述阵列基板还包括：下拉电源线；每个所述移位寄存器单元还包括：第一下拉晶体管和第二下拉晶体管；所述移位子电路还与下拉节点连接；
    所述第一下拉晶体管的栅极与所述下拉节点连接，所述第一下拉晶体管的第一极与下拉电源线连接，所述第一下拉晶体管的第二极与所述开关输出端连接；
    所述第二下拉晶体管的栅极与所述下拉节点连接，所述第二下拉晶体管的第一极与所述下拉电源线连接，所述第二下拉晶体管的第二极与所述检测输出端连接。
  14. 根据权利要求1至13任一所述的阵列基板，与同一个所述测试端连接的所述至少两条时钟信号线中，一条所述时钟信号线与所述测试端直接连接，且所述至少两条时钟信号线依次连接。
  15. 根据权利要求1至13任一所述的阵列基板，与同一个所述测试端连接的所述至少两条时钟信号线中，一条目标时钟信号线与所述测试端直接连接，且所述至少两条时钟信号线中除所述目标时钟信号线之外的每条所述时钟信号 线，均与所述目标时钟信号线连接。
  16. 根据权利要求1至15任一所述的阵列基板，所述阵列基板还包括：静电释放电路；
    所述静电释放电路分别与所述多条时钟信号线和静电释放线连接。
  17. 根据权利要求3所述的阵列基板，所述多条时钟信号线还包括：多条第三时钟信号线，所述多个级联的移位寄存器单元中，奇数级移位寄存器单元用于将所述第三时钟信号线提供的时钟信号输出至移位输出端；
    所述多条第三时钟信号线中，每条所述第三时钟信号线与一个所述第一测试端直接连接，各个所述第三时钟信号线连接的所述第一测试端不同，且所述多条第一时钟信号线中，每相邻两条所述第一时钟信号线与一条所述第三时钟信号线连接；
    每个所述移位寄存器单元包括：移位子电路、第一输出晶体管、第二输出晶体管、第一下拉晶体管和第二下拉晶体管；所述移位子电路分别与上拉节点和下拉节点连接；
    所述第一输出晶体管的栅极和所述第二输出晶体管的栅极均与所述上拉节点连接，所述第一输出晶体管的第一极与一条所述第一时钟信号线连接，所述第一输出晶体管的第二极与所述开关输出端连接；所述第二输出晶体管的第一极与一条所述第二时钟信号线连接，所述第二输出晶体管的第二极与所述检测输出端连接；
    所述第一下拉晶体管的栅极和所述第二下拉晶体管的栅极均与所述下拉节点连接，所述第一下拉晶体管的第一极和所述第二下拉晶体管的第一极均与下拉电源线连接，所述第一下拉晶体管的第二极与所述开关输出端连接，所述第二下拉晶体管的第二极与所述检测输出端连接；
    所述阵列基板还包括多个像素电路，每个所述像素电路包括开关晶体管、驱动晶体管、检测晶体管和存储电容；
    所述开关晶体管的栅极与所述第一栅线连接，所述开关晶体管的第一极与数据信号端连接，所述开关晶体管的第二极与所述驱动晶体管的栅极连接；所述驱动晶体管的第一极与直流电源端连接，所述驱动晶体管的第二极与发光元 件的一端连接；所述检测晶体管的栅极与所述第二栅线连接，所述检测晶体管的第一极与所述发光元件的一端连接，所述检测晶体管的第二极与检测信号线连接；所述存储电容的一端与所述驱动晶体管的栅极连接，另一端与所述发光元件的一端连接。
  18. 一种阵列基板的测试方法，用于测试如权利要求1至17任一所述的阵列基板，所述方法包括：
    将测试设备与所述阵列基板中的每个测试端分别连接；
    通过每个所述测试端向所述阵列基板中的多条时钟信号线提供时钟信号；
    获取所述阵列基板中各个像素电路加载至发光元件的驱动信号。
  19. 根据权利要求18所述的方法，所述多条时钟信号线包括：多条第一时钟信号线、多条第二时钟信号线和多条第三时钟信号线，所述多个测试端包括：多个第一测试端和一个第二测试端，每两条所述第一时钟信号线与同一个所述第一测试端连接，所述多条第二时钟信号线均与一个所述第二测试端连接，每条所述第三时钟信号线与一个所述第一测试端连接；
    所述通过每个所述测试端向所述阵列基板中的多条时钟信号线提供时钟信号，包括：
    通过所述第一测试端，向所述多条第一时钟信号线和所述多条第三时钟信号线依次提供时钟信号；
    通过所述第二测试端，向所述多条第二时钟信号线提供处于有效电位的时钟信号。
  20. 根据权利要求19所述的方法，向所述多条第一时钟信号线和所述多条第三时钟信号线提供的时钟信号的占空比为2/5，且向每相邻两条所述第三时钟信号线提供的时钟信号的上升沿的间隔为所述时钟信号的周期的1/5。
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