WO2016206271A1 - 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置 - Google Patents

移位寄存器单元及其驱动方法、栅极驱动电路及显示装置 Download PDF

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Publication number
WO2016206271A1
WO2016206271A1 PCT/CN2015/093749 CN2015093749W WO2016206271A1 WO 2016206271 A1 WO2016206271 A1 WO 2016206271A1 CN 2015093749 W CN2015093749 W CN 2015093749W WO 2016206271 A1 WO2016206271 A1 WO 2016206271A1
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Prior art keywords
transistor
shift register
gate
gate line
driving
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PCT/CN2015/093749
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English (en)
French (fr)
Inventor
周晓亮
王洪伟
余飞
蒋磊
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/311,386 priority Critical patent/US10283038B2/en
Priority to EP15891409.3A priority patent/EP3316236A4/en
Publication of WO2016206271A1 publication Critical patent/WO2016206271A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0218—Addressing of scan or signal lines with collection of electrodes in groups for n-dimensional addressing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register unit and a driving method thereof, a gate driving circuit, and a display device.
  • GOA Gate Driver on Array
  • the gate driving circuit adopting the GOA technology includes a plurality of shift register units, each shift register unit includes a plurality of thin film transistors (hereinafter referred to as TFTs), wherein each shift register unit corresponds to one row of gate lines. Drive the row gate to turn on and off.
  • TFTs thin film transistors
  • each shift register unit can only drive one row of gate lines to be turned on and off, in the display panel, more shift register units need to be prepared to drive multiple rows of gate lines to be turned on and off; in this case, The number of thin film transistors prepared on the array substrate is large, and thus the gate driving circuit takes up a large area, which is disadvantageous for realizing a narrow bezel.
  • a bilaterally driven technical solution can be adopted, that is, a driving signal is simultaneously input to the gate line at both ends of the gate line, but a double is adopted.
  • Side drive can cause problems such as high temperature jitter and interlaced display.
  • the area occupied by the gate driving circuit is large, and the wiring space of the protection circuit is also limited, so that the antistatic discharge (ESD) resistance of the circuit is insufficient.
  • the present disclosure proposes a shift register unit and a driving method thereof, a gate driving circuit, and a display device, which can reduce an area occupied by a gate driving circuit.
  • the present disclosure provides a shift register unit including: a driving signal generating module, configured to generate a driving signal for driving an n-line gate line to be turned on, the driving signal lasting for a time equal to scanning a time required for n rows of gate lines; said n ⁇ 2; and a selection module connected to the drive signal generation module and connected to an input end of the n-row gate line for generating the drive signal
  • the module is sequentially gated with n rows of gate lines, and the driving signals generated by the driving signal generating module are sequentially input to the n rows of gate lines.
  • the selection module includes n thin film transistors and n clock signal ends, and a control electrode of each thin film transistor is connected to a clock signal end, and a source is connected to an output end of the driving signal generating module, and the drain and the The input terminals of one of the n rows of gate lines are connected.
  • the n clock signal ends are respectively used to input clock signals to the control poles of the n thin film transistors, so that the n thin film transistors are sequentially turned on for the duration of the driving signal.
  • the n thin film transistors in the selection module are active high, and the n clock signal terminals sequentially output a high level during the duration of the driving signal, and during the duration of the driving signal. At any time, there is only one clock signal output high level.
  • the shift register unit further includes a noise reduction module, configured to reduce noise of a driving signal input into the gate line.
  • the noise reduction module includes n-1 noise reduction units, and the n-1 noise reduction units respectively One-to-one correspondence with the last opened n-1 row gate lines in the n-row gate lines; each noise reduction unit will have an input terminal and a low voltage terminal of the gate line that is turned on before the corresponding gate line is turned on connection.
  • the noise reduction unit corresponding to the m-th gate line in the n-row gate line includes m-1 thin film transistors, 2 ⁇ m ⁇ n; and the control poles of the m-1 thin film transistors are The input ends of the m-th gate lines are connected, the sources are all connected to the low-voltage terminals, and the drains are respectively connected in one-to-one correspondence with the input ends of the first to m-th row gate lines of the n-row gate lines.
  • n is equal to 2.
  • the driving signal generating module includes first to tenth transistors, a signal input end, an output end, a first high voltage end, a second high voltage end, a reset signal end, a first low voltage end, and a second low a voltage terminal, a pull-up node, a pull-down node, a first clock signal terminal and a first capacitor; a control electrode of the first transistor is connected to the signal input terminal, and a source is connected to the first high voltage terminal, and a drain a pole is connected to the pull-up node; a control pole of the second transistor is connected to the reset signal terminal, a source is connected to the first low voltage terminal, and a drain is connected to the pull-up node; a control electrode of the third transistor is connected to the pull-up node, a source is connected to the first clock signal terminal, a drain is connected to the output terminal, and a control electrode and a source of the fourth transistor are The second high voltage terminal is connected, the drain is connected to the control electrode of the fifth transistor
  • the present disclosure also provides a driving method of the above shift register unit, including:
  • the driving signals are sequentially input to n rows of gate lines.
  • the present disclosure also provides a gate drive circuit including a plurality of the above-described shift register units cascaded together.
  • a plurality of shift register units in the gate driving circuit are disposed on one side of the gate line.
  • a plurality of shift register units in the gate driving circuit are disposed on both sides of the gate line.
  • the present disclosure also provides a display device including the above-described gate driving circuit.
  • the driving signal input to the n-row gate line is generated by a driving signal generating module, which reduces the number of driving signal generating modules compared to the related art; and each driving signal is generated
  • the module generally includes a plurality of thin film transistors and capacitors, so that the area occupied by the gate driving circuit can be reduced, thereby facilitating the realization of a narrow bezel, increasing the area of the effective display area of the display device, and improving the screen of the display device. At the same time, it can also provide enough space for the layout of the protection circuit, which can improve the ESD resistance of the circuit.
  • the driving method of the shift register unit sequentially inputs a generated driving signal into n rows of gate lines, which reduces the number of driving signal generating modules for generating driving signals as compared with the related art;
  • the driving signal generating module generally includes a plurality of devices such as a thin film transistor and a capacitor, so that the area occupied by the gate driving circuit can be reduced, thereby facilitating the realization of a narrow bezel, increasing the area of the effective display area of the display device, and improving the display.
  • the screen ratio of the device at the same time, it can also provide sufficient space for the arrangement of the protection circuit, which can improve the ESD resistance of the circuit.
  • the gate driving circuit provided by the present disclosure can reduce the area occupied by the gate driving circuit, thereby contributing to achieving a narrow bezel and increasing the effective display area of the display device. Increase the screen ratio of the display device; at the same time, it can also give the protection circuit
  • the layout provides enough space to improve the circuit's ESD resistance.
  • the display device provided by the present disclosure includes the gate driving circuit provided by the present disclosure, which can reduce the area occupied by the gate driving circuit, thereby contributing to achieving a narrow bezel, increasing the area of the effective display area of the display device, and improving the display.
  • the screen ratio of the device at the same time, it can also provide sufficient space for the arrangement of the protection circuit, which can improve the ESD resistance of the circuit.
  • FIG. 1 is a schematic diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 2 is a circuit diagram of the shift register unit of FIG. 1;
  • Figure 3 is a timing diagram of signals in the circuit of Figure 2;
  • FIG. 5 is a flowchart of a method for driving a shift register unit according to an embodiment of the present disclosure.
  • 1 drive signal generation module; 2: selection module; 3: noise reduction module; 30: noise reduction unit;
  • M1 first transistor; M2: second transistor; M3: third transistor; M4: fourth transistor; M5: fifth transistor; M6: sixth transistor; M7: seventh transistor; M8: eighth transistor; M9: Ninth transistor; M10: tenth transistor; M11: eleventh transistor; M12: twelfth transistor; M13: thirteenth transistor; M14: fourteenth transistor; M15: fifteenth transistor; Transistor; C1: first capacitor;
  • INPUT signal input terminal; Reset: reset signal terminal; CLK1: first clock signal terminal; CLK2: second clock signal terminal; CLK3: third clock signal terminal; VDD: first high voltage terminal; VSS: first low voltage terminal Terminal; VGH: second high voltage terminal; VGL: second low voltage terminal / low voltage terminal; OUTPUT: output terminal;
  • Gate1 a first row of gate lines in the n-row gate line
  • Gate2 a second row of gate lines in the n-row gate line
  • Gate3 a third row of gate lines in the n-row gate line.
  • FIG. 1 is a schematic diagram of a shift register unit according to an embodiment of the present disclosure.
  • the shift register unit includes a driving signal generating module 1 and a selecting module 2, wherein the driving signal generating module 1 is configured to generate a driving signal for driving the gate line to be turned on.
  • the duration of the driving signal is equal to the time required to scan the n-row gate line; the n ⁇ 2; the selection module 2 is connected to the input end of the n-row gate line for sequentially driving the driving signal generating module 1
  • the gate signal is gated with n rows, and the generated driving signals are sequentially input to the n-row gate lines.
  • the selection module 2 sequentially gates the driving signal generating module 1 and the n-row gate lines in the n ⁇ t period, and can sequentially input the driving signals generated by the driving module generating module 1 into the n-row gate lines.
  • the n-line gate lines are driven to turn on sequentially.
  • the driving signal input to the n-th gate line is generated by one driving signal generating module 1, and the number of driving signal generating modules 1 is reduced in the gate driving circuit as compared with the related art.
  • Each driving signal generating module 1 generally includes a plurality of devices such as a thin film transistor and a capacitor, so that the area occupied by the gate driving circuit can be reduced, thereby facilitating the realization of a narrow bezel and increasing the effective display area of the display device.
  • the area of the display device is increased, and at the same time, sufficient space is provided for the arrangement of the protection circuit, which can improve the antistatic discharge ESD (ESD) resistance of the circuit.
  • ESD antistatic discharge ESD
  • the narrow frame can be implemented on the basis of the unilateral driving, so that the technical solutions for achieving the narrow frame by the bilateral driving in the prior art can improve the related defects such as high temperature jitter and interlaced display;
  • a bilateral drive at the same time to further reduce the width of the bezel, that is, to achieve a narrower border.
  • the selection module 2 may include n thin film transistors, the control electrode of each thin film transistor is connected to a clock signal end, the source is connected to the output end of the driving signal generating module 1, and the drain and the row of gate lines are connected. The input is connected. Specifically, each clock signal terminal inputs a clock signal to the gate electrode of the connected thin film transistor, and the clock signal controls opening and closing of the thin film transistor.
  • the thin film transistor is turned on, the output end of the driving signal generating module 1 and The gate lines of the drain connection of the thin film transistor are connected, thereby inputting a driving signal generated by the driving signal generating module 1 to the gate line.
  • the selection module 2 is connected to two rows of gate lines, which are a first row gate line Gate1 and a second row gate line Gate2, respectively.
  • the selection module 2 includes an eleventh transistor M11 and a twelfth transistor M12; the control electrode of the eleventh transistor M11 is connected to the second clock signal terminal CLK2, and the source is connected to the output terminal OUTPUT of the driving signal generating module 1, and the drain
  • the pole is connected to the input end of the gate line Gate1; the control electrode of the twelfth transistor M12 is connected to the third clock signal terminal CLK3, the source is connected to the output terminal OUTPUT of the driving signal generating module 1, and the input terminal of the drain and gate line Gate2 connection.
  • the driving signal generating module 1 When the driving signal generating module 1 generates the driving signal, as shown in FIG. 3, in the first phase t1, the second clock signal terminal CLK2 outputs a high level, and the third clock signal terminal CLK3 outputs a low level.
  • the eleventh transistor M11 is turned on, the twelfth transistor M12 is turned off, the driving signal generating module 1 is connected to the gate line Gate1, and the gate line Gate2 is disconnected from the driving signal generating module 1, so that In the first stage t1, the driving signal is input to the gate line Gate1;
  • the second clock signal terminal CLK2 In the second phase t2, the second clock signal terminal CLK2 outputs a low level, and the third clock signal terminal CLK3 outputs a high level.
  • the eleventh transistor M11 is turned off, and the twelfth transistor M12 is turned on.
  • the driving signal generating module 1 is connected to the gate line Gate2, and the gate line Gate1 is disconnected from the driving signal generating module 1, so that the driving signal is input to the gate line Gate2 in the second phase t2.
  • the gate lines Gate1 and Gate2 are sequentially turned on by the driving signal.
  • the shift register unit may further include a noise reduction module 3 for reducing noise of a driving signal input to the gate line, thereby improving display quality.
  • the noise reduction module 3 includes n-1 noise reduction units 30, and the n-1 noise reduction units 30 respectively correspond to the last opened n-1 row gate lines of the n rows of gate lines;
  • the noise reduction unit 30 connects the gate line that is turned on before the corresponding gate line to the low voltage terminal. Generally, after the gate line that is turned on first is turned off, there is a noise signal that interferes with the driving signal input to the gate line that is turned on thereafter.
  • the noise reduction unit 30 corresponding to the gate line connects the gate line opened before the gate line to the low voltage end, thereby reducing noise and thereby inputting
  • the driving signal in the gate line corresponding to the noise reduction unit 30 is more accurate, so that the display quality can be improved.
  • the noise reduction unit corresponding to the m-th gate line in the n-row gate line includes m-1 thin film transistors, the 2 ⁇ m ⁇ n; and the control poles of the m-1 thin film transistors are both The input ends of the m-th gate lines are connected, the sources are connected to the low-voltage terminals, and the drains are respectively connected in one-to-one correspondence with the input ends of the first to m-1-row gate lines of the n-row gate lines.
  • the noise reduction module 3 includes a noise reduction unit 30 corresponding to the gate line Gate2, and the noise reduction unit 30 is the thirteenth transistor M13, and its control pole
  • the source is connected to the input terminal of the gate line Gate2, and the source is connected to a low voltage terminal VGL (the second low voltage terminal VGL is selected in the embodiment), and the drain is connected to the input terminal of the gate line Gate1.
  • VGL the second low voltage terminal VGL is selected in the embodiment
  • the drain is connected to the input terminal of the gate line Gate1.
  • the driving signal input to the gate line Gate2 turns on the thirteenth transistor M13, thereby connecting the gate line Gate1 to the low voltage terminal VGL, and the signal clutter in the gate line Gate1. This is reduced, thereby reducing the interference with the drive signal input to the gate line Gate2.
  • the noise reduction unit 30 corresponding to the gate line Gate2 includes a thirteenth transistor M13, the control electrode is connected to the input end of the gate line Gate2, the source is connected to a low voltage terminal VGL, and the drain is connected to the gate line Gate1;
  • the driving signal input to the gate line Gate2 turns on the thirteenth transistor M13, thereby connecting the gate line Gate1 to the low voltage terminal VGL, and the signal clutter in the gate line Gate1 is This will be reduced, thereby reducing interference with the drive signal input to the gate line Gate2.
  • the noise reduction unit 30 corresponding to the gate line Gate3 includes a fifteenth transistor M15 and a sixteenth transistor M16.
  • the control electrode of the fifteenth transistor M15 is connected to the gate line Gate3, and the source is connected to the low voltage terminal VGL. Connected to the gate line Gate1; the control electrode of the sixteenth transistor M16 is connected to the gate line Gate3, the source is connected to the low voltage terminal VGL, and the drain is connected to the gate line Gate2; when the driving signal is input to the gate line Gate3, the input is The driving signal to the gate line Gate3 turns on the fifteenth transistor M15 and the sixteenth transistor M16, thereby connecting the gate lines Gate1 and Gate2 to the low voltage terminal VGL, and the signal clutter in the gate lines Gate1 and Gate2 is This will be reduced, thereby reducing interference with the drive signal input to the gate line Gate3.
  • n 2
  • the structure of the selection module 2 and the noise reduction module 3 is the simplest. Therefore, in practice, it is preferable that the value of n is 2, so that the line structure of the gate driving circuit is further improved. simple.
  • the specific structure of the driving signal generating module 1 may be as shown in FIG. 2, specifically, including first to tenth transistors M1 to M10, and a first capacitor C1; wherein the first transistor M1
  • the control electrode is connected to the signal input terminal INPUT, the source is connected to the first high voltage terminal VDD, and the drain is connected to the pull-up node PU;
  • the control electrode of the second transistor M2 is connected to the reset signal terminal Reset, and the source is The first low voltage terminal VSS is connected, the drain is connected to the pull-up node PU;
  • the control electrode of the third transistor M3 is connected to the pull-up node PU, the source is connected to the first clock signal terminal CLK1, and the drain and the output are connected.
  • a control electrode and a source of the fourth transistor M4 are connected to the second high voltage terminal VGH, a drain is connected to a control electrode of the fifth transistor M5; and a source of the fifth transistor M5 is the second highest
  • the voltage terminal VGH is connected, the drain is connected to the pull-down node PD, the control electrode of the sixth transistor M6 is connected to the pull-up node PU, the source is connected to the second low voltage terminal VGL, and the drain is connected to the pull-down node PD;
  • the control electrode of the seventh transistor M7 is connected to the first low voltage terminal VSS, the source is connected to the second low voltage terminal VGL, the drain is connected to the output terminal OUTPUT, and the gate of the eighth transistor M8 is connected to the pull-up node PU.
  • the drain and the The drain of the fourth transistor M4 is connected to the gate of the fifth transistor M5; the gate of the ninth transistor M9 is connected to the pull-down node PD, the source is connected to the second low voltage terminal VGL, and the drain and the pull-up node PU
  • the control terminal of the tenth transistor M10 is connected to the pull-down node PD, the source is connected to the second low voltage terminal VGL, and the drain is connected to the output terminal OUTPUT; the first end of the first capacitor C1 is connected with the pull-up The PU is connected, and the second end is connected to the drain of the third transistor M3.
  • the driving signal generating module 1 may be any other circuit structure capable of generating a driving signal.
  • the shift register unit provided by the embodiment of the present disclosure generates a driving signal input to the n-row gate line by a driving signal generating module 1, which reduces the number of driving signal generating modules 1 as compared with the related art.
  • Each driving signal generating module 1 generally includes a plurality of devices such as a thin film transistor and a capacitor, so that the area occupied by the gate driving circuit can be reduced, thereby facilitating the realization of a narrow bezel and increasing the effective display area of the display device.
  • the area of the display device is increased, and at the same time, sufficient space is provided for the arrangement of the protection circuit, which can improve the ESD resistance of the circuit.
  • Embodiments of the present disclosure also provide a driving method of the above shift register unit.
  • the driving method of the shift register unit includes the following steps S1 and S2:
  • the driving signals are sequentially input to n rows of gate lines.
  • a driving method of a shift register unit sequentially inputs a generated driving signal into an n-row gate line, which reduces the number of driving signal generating modules for generating a driving signal as compared with the related art.
  • the driving signal generating module generally includes a plurality of thin film transistors and capacitors, and thus, the area occupied by the gate driving circuit can be reduced, thereby facilitating the realization of a narrow bezel and increasing the effective display area of the display device. Increasing the screen ratio of the display device; at the same time, it can also provide sufficient space for the arrangement of the protection circuit, which can improve the anti-ESD capability of the circuit.
  • Embodiments of the present disclosure also provide a gate drive circuit.
  • the gate drive circuit includes a plurality of shift register units provided by the above-described embodiments that are cascaded together.
  • the gate driving circuit provided by the present disclosure includes the shift register unit provided by the above embodiment, which can reduce the area occupied by the gate driving circuit, thereby contributing to achieving a narrow bezel and increasing the effective display area of the display device. , to improve the screen ratio of the display device; at the same time, it can also provide sufficient space for the protection circuit arrangement, which can improve the circuit's anti-ESD capability.
  • Embodiments of the present disclosure also provide a display device.
  • the display device includes the gate driving circuit provided by the above embodiment.
  • the display device provided by the present disclosure includes the gate driving circuit provided by the above embodiment, which can reduce the area occupied by the gate driving circuit, thereby contributing to achieving a narrow bezel, increasing the effective display area of the display device, and improving The screen ratio of the display device; at the same time, it can also provide sufficient space for the arrangement of the protection circuit, which can improve the anti-ESD capability of the circuit.

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  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

一种移位寄存器单元及其驱动方法、栅极驱动电路及显示装置。所述移位寄存器单元包括：驱动信号生成模块（1），所述驱动信号生成模块（1）用于生成n行驱动栅线开启的驱动信号，所述驱动信号所持续的时间等于扫描n行栅线所需的时间；n≥2；选择模块（2），所述选择模块（2）与所述驱动信号生成模块（1）连接且与n行栅线的输入端连接，用于将所述驱动信号生成模块（1）依次与n行栅线选通，将所述驱动信号依次输入所述n行栅线。

Description

移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
相关申请的交叉参考
本申请主张在2015年6月24日在中国提交的中国专利申请号No.201510354969.3的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，具体地，涉及一种移位寄存器单元及其驱动方法、栅极驱动电路及显示装置。
背景技术
近些年来显示器的发展呈现出了高集成度，低成本的趋势。一项非常重要的相关技术：栅极驱动集成在阵列基板(Gate Driver on Array，缩写为GOA)技术实现了量产化。利用GOA技术将栅极驱动电路集成在显示面板的阵列基板上，可以省掉栅极驱动集成电路部分，以从材料成本和制作工艺两方面降低产品成本。
采用GOA技术的栅极驱动电路包括若干个移位寄存器单元，每个移位寄存器单元包含若干薄膜晶体管(Thin Film Transistor，以下简称为TFT)，其中，每一移位寄存器单元对应一行栅线，驱动该行栅线开启和关闭。
由于每一移位寄存器单元仅能驱动一行栅线开启和关闭，因此，在显示面板中，需要制备较多的移位寄存器单元，以驱动多行栅线开启和关闭；在此情况下，需要在阵列基板上制备的薄膜晶体管的数量较多，从而，栅极驱动电路会占用较大的面积，不利于实现窄边框。为了实现窄边框，可以采用双边驱动的技术方案，即在栅线的两端同时向栅线输入驱动信号，但采用双 边驱动会导致高温抖动、隔行显示等问题。此外，栅极驱动电路占用的面积较大，还会限制保护电路的布线空间，从而会使得电路的抗静电释放(抗ESD)能力不足。
发明内容
本公开提出了一种移位寄存器单元及其驱动方法、栅极驱动电路及显示装置，其可以减少栅极驱动电路所占用的面积。
一方面，本公开提供一种移位寄存器单元，其包括：驱动信号生成模块，所述驱动信号生成模块用于生成驱动n行栅线开启的驱动信号，所述驱动信号所持续的时间等于扫描n行栅线所需的时间；所述n≥2；以及选择模块，所述选择模块与所述驱动信号生成模块连接且与n行栅线的输入端连接，用于将所述驱动信号生成模块依次与n行栅线选通，将所述驱动信号生成模块生成的所述驱动信号依次输入所述n行栅线。
可选的，所述选择模块包括n个薄膜晶体管和n个时钟信号端，每个薄膜晶体管的控制极与一时钟信号端连接，源极与驱动信号生成模块的输出端连接，漏极与所述n行栅线中的一行栅线的输入端连接。
可选的，所述n个时钟信号端分别用于向所述n个薄膜晶体管的控制极输入时钟信号，使得所述n个薄膜晶体管在所述驱动信号持续时间内依次打开。
可选的，所述选择模块中的n个薄膜晶体管为高电平有效，所述n个时钟信号端在所述驱动信号持续时间内依次输出高电平，且在所述驱动信号持续时间内的任意时刻有且仅有一个时钟信号端输出高电平。
可选的，所述移位寄存器单元还包括降噪模块，所述降噪模块用于降低输入到栅线中的驱动信号的噪声。
可选的，所述降噪模块包括n-1个降噪单元，所述n-1个降噪单元分别 与n行栅线中最后开启的n-1行栅线一一对应；每个降噪单元在其对应的栅线开启时，将先于该栅线开启的栅线的输入端与低电压端连接。
可选的，与n行栅线中的第m行栅线对应的降噪单元包括m-1个薄膜晶体管，2≤m≤n；且所述m-1个薄膜晶体管的控制极均与该第m行栅线的输入端连接，源极均与低电压端连接，漏极分别与n行栅线中的第1至第m-1行栅线的输入端一一对应地连接。
可选的，所述n等于2。
可选的，所述驱动信号生成模块包括第一至第十晶体管，信号输入端，输出端，第一高电压端，第二高电压端，复位信号端，第一低电压端，第二低电压端，上拉结点，下拉节点，第一时钟信号端以及第一电容；所述第一晶体管的控制极与所述信号输入端连接，源极与所述第一高电压端连接，漏极与所述上拉结点连接；所述第二晶体管的控制极与所述复位信号端连接，源极与所述第一低电压端连接，漏极与所述上拉结点连接；所述第三晶体管的控制极与所述上拉结点连接，源极与所述第一时钟信号端连接，漏极与所述输出端连接；所述第四晶体管的控制极和源极与所述第二高电压端连接，漏极与第五晶体管的控制极连接；所述第五晶体管的源极与所述第二高电压端连接，漏极与所述下拉节点连接；所述第六晶体管的控制极与所述上拉节点连接，源极与所述第二低电压端连接，漏极与所述下拉节点连接；所述第七晶体管的控制极与所述第一低电压端连接，源极与所述第二低电压端连接，漏极与所述输出端连接；所述第八晶体管的控制极与所述上拉节点连接，源极与所述第二低电压端连接，漏极与所述第四晶体管的漏极和第五晶体管的控制极连接；所述第九晶体管的控制极与所述下拉节点连接，源极与所述第二低电压端连接，漏极与所述上拉结点连接；所述第十晶体管的控制极与所述下拉节点连接，源极与所述第二低电压端连接，漏极与所述输出端连接；所述第一电容的第一端与所述上拉结点连接，第二端与所述第三晶体管的漏 极连接。
另一方面，本公开还提供上述移位寄存器单元的驱动方法，其包括：
生成驱动信号，所述驱动信号所持续的时间等于扫描n行栅线所需的时间，所述n≥2；
将所述驱动信号依次输入n行栅线。
另一方面，本公开还提供一种栅极驱动电路，其包括级联在一起的多个上述移位寄存器单元。
可选的，上述栅极驱动电路中的多个移位寄存器单元设置在栅线的一侧。
可选的，上述栅极驱动电路中的多个移位寄存器单元设置在栅线的两侧。
另一方面，本公开还提供一种显示装置，其包括上述栅极驱动电路。
本公开提供的移位寄存器单元，其输入向n行栅线的驱动信号由一个驱动信号生成模块所生成，与相关技术相比，这样减少了驱动信号生成模块的数量；而每个驱动信号生成模块一般包括多个薄膜晶体管和电容等器件，因此，这样可以减少栅极驱动电路所占用的面积，从而有助于实现窄边框，增大显示装置的有效显示区的面积，提高显示装置的屏占比；同时，还可以给保护电路的布置提供足够的空间，这样可以提高电路的抗ESD能力。
本公开提供的移位寄存器单元的驱动方法，其将生成的一个驱动信号依次输入n行栅线内，与相关技术相比，这样减少了用于生成驱动信号的驱动信号生成模块的数量；而驱动信号生成模块一般包括多个薄膜晶体管和电容等器件，因此，这样可以减少栅极驱动电路所占用的面积，从而有助于实现窄边框，增大显示装置的有效显示区的面积，提高显示装置的屏占比；同时，还可以给保护电路的布置提供足够的空间，这样可以提高电路的抗ESD能力。
本公开提供的栅极驱动电路，其包括本公开提供的移位寄存器单元，可以减少栅极驱动电路所占用的面积，从而有助于实现窄边框，增大显示装置的有效显示区的面积，提高显示装置的屏占比；同时，还可以给保护电路的 布置提供足够的空间，这样可以提高电路的抗ESD能力。
本公开提供的显示装置，其包括本公开提供的栅极驱动电路，可以减少栅极驱动电路所占用的面积，从而有助于实现窄边框，增大显示装置的有效显示区的面积，提高显示装置的屏占比；同时，还可以给保护电路的布置提供足够的空间，这样可以提高电路的抗ESD能力。
附图说明
附图是用来提供对本公开的进一步理解，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1为本公开实施方式提供的移位寄存器单元的示意图；
图2为图1所述移位寄存器单元的电路图；
图3为图2所述电路中各信号的时序图；
图4为n为3时选择模块及降噪模块的电路图；
图5为本公开实施方式提供的移位寄存器单元的驱动方法的流程图。
其中，附图标记说明如下：
1：驱动信号生成模块；2：选择模块；3：降噪模块；30：降噪单元；
M1：第一晶体管；M2：第二晶体管；M3：第三晶体管；M4：第四晶体管；M5：第五晶体管；M6：第六晶体管；M7：第七晶体管；M8：第八晶体管；M9：第九晶体管；M10：第十晶体管；M11：第十一晶体管；M12：第十二晶体管；M13：第十三晶体管；M14：第十四晶体管；M15：第十五晶体管；M16：第十六晶体管；C1：第一电容；
INPUT：信号输入端；Reset：复位信号端；CLK1：第一时钟信号端；CLK2：第二时钟信号端；CLK3：第三时钟信号端；VDD：第一高电压端；VSS：第一低电压端；VGH：第二高电压端；VGL：第二低电压端/低电压端；OUTPUT：输出端；
Gate1：n行栅线中的第一行栅线；Gate2：n行栅线中的第二行栅线；Gate3：n行栅线中的第三行栅线。
具体实施方式
以下结合附图对本公开的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本公开，并不用于限制本公开。
本公开提供一种移位寄存器单元。图1为本公开实施方式提供的移位寄存器单元的示意图。如图1所示，在本实施方式中，所述移位寄存器单元包括驱动信号生成模块1和选择模块2，其中，所述驱动信号生成模块1用于生成驱动栅线开启的驱动信号，所述驱动信号所持续的时间等于扫描n行栅线所需的时间；所述n≥2；所述选择模块2与n行栅线的输入端连接，用于将所述驱动信号生成模块1依次与n行栅线选通，将所生成的所述驱动信号依次输入所述n行栅线。
首先，设一帧画面中每行栅线开启的时间为t，在此情况下，驱动信号生成模块1所生成的驱动信号所持续的时间为n×t。所述选择模块2在该n×t时段内，将驱动信号生成模块1与n行栅线依次选通，可以实现向该n行栅线内依次输入驱动模块生成模块1所生成的驱动信号，驱动该n行栅线依次开启。
由上述可知，本实施方式中，输入所述n行栅线的驱动信号由一个驱动信号生成模块1所生成，与相关技术相比，在栅极驱动电路中减少了驱动信号生成模块1的数量；而每个驱动信号生成模块1一般包括多个薄膜晶体管和电容等器件，因此，这样可以减少栅极驱动电路所占用的面积，从而有助于实现窄边框，增大显示装置的有效显示区的面积，提高显示装置的屏占比；同时，还可以给保护电路的布置提供足够的空间，这样可以提高电路的抗静电释放ESD(抗ESD)能力。
具体地，在本实施方式中，可以在单边驱动的基础上实现窄边框，这样相比现有技术中的通过双边驱动实现窄边框的技术方案，可以改善高温抖动、隔行显示等相关不良；当然，也可以同时采用双边驱动，以进一步降低边框的宽度，即实现更窄边框。
本实施方式中，所述选择模块2可以包括n个薄膜晶体管，每个薄膜晶体管的控制极与一时钟信号端连接，源极与驱动信号生成模块1的输出端连接，漏极与一行栅线的输入端连接。具体地，每个时钟信号端向连接的薄膜晶体管的控制极输入时钟信号，该时钟信号控制该薄膜晶体管的开闭，在该薄膜晶体管开启时，所述驱动信号生成模块1的输出端和与该薄膜晶体管的漏极连接的栅线连接，从而将驱动信号生成模块1所生成的驱动信号输入至所述栅线。
下面以n＝2为例，结合图2，对本实施方式提供的移位寄存器单元的工作原理和过程进行详细描述。
在n＝2时，如图2所示，所述选择模块2与两行栅线连接，分别为第一行栅线Gate1和第二行栅线Gate2。选择模块2包括第十一晶体管M11和第十二晶体管M12；所述第十一晶体管M11的控制极与第二时钟信号端CLK2连接，源极与驱动信号生成模块1的输出端OUTPUT连接，漏极与栅线Gate1的输入端连接；第十二晶体管M12的控制极与第三时钟信号端CLK3连接，源极与驱动信号生成模块1的输出端OUTPUT连接，漏极与栅线Gate2的输入端连接。
在驱动信号生成模块1生成驱动信号时，如图3所示，在第一阶段t1，所述第二时钟信号端CLK2输出高电平，第三时钟信号端CLK3输出低电平，在此情况下，所述第十一晶体管M11开启，第十二晶体管M12关闭，使驱动信号生成模块1与栅线Gate1连通，而栅线Gate2与驱动信号生成模块1之间处于断开状态，从而在该第一阶段t1内，所述驱动信号输入至栅线Gate1； 在第二阶段t2，所述第二时钟信号端CLK2输出低电平，第三时钟信号端CLK3输出高电平，在此情况下，所述第十一晶体管M11关闭，第十二晶体管M12开启，使驱动信号生成模块1与栅线Gate2连通，而栅线Gate1与驱动信号生成模块1之间处于断开状态，从而在该第二阶段t2内，所述驱动信号输入至栅线Gate2。由上可知，栅线Gate1和Gate2依次被驱动信号开启。
所述移位寄存器单元还可以包括降噪模块3，所述降噪模块3用于降低输入到栅线中的驱动信号的噪声，从而可以提高显示品质。具体地，所述降噪模块3包括n-1个降噪单元30，所述n-1个降噪单元30分别与n行栅线中最后开启的n-1行栅线一一对应；每个降噪单元30在其对应的栅线开启时，将先于该栅线开启的栅线与低电压端连接。一般地，先开启的栅线在关闭后，会存在噪声信号，对输入到在其后开启的栅线中的驱动信号造成干扰。本实施方式中，向后开启的栅线输入驱动信号时，该栅线所对应的降噪单元30将先于该栅线开启的栅线与低电压端连接，可以降低其噪声，从而使输入到该降噪单元30所对应的栅线中的驱动信号更准确，这样就可以提高显示品质。
进一步地，与n行栅线中的第m行栅线对应的降噪单元包括m-1个薄膜晶体管，所述2≤m≤n；且所述m-1个薄膜晶体管的控制极均与该第m行栅线的输入端连接，源极均与低电压端连接，漏极分别与n行栅线中的第1～m-1行栅线的输入端一一对应地连接。
仍以图2所示的n＝2的移位寄存器单元为例，降噪模块3包括一个与栅线Gate2对应的降噪单元30，该降噪单元30为第十三晶体管M13，其控制极与栅线Gate2的输入端连接，源极与一低电压端VGL(本实施例中选择第二低电压端VGL)连接，漏极与栅线Gate1的输入端连接。在向栅线Gate2输入驱动信号时，输入到栅线Gate2上的驱动信号会将第十三晶体管M13开启，从而使栅线Gate1与低电压端VGL连接，这时栅线Gate1中的信号杂波就会减少，从而降低对输入到栅线Gate2中的驱动信号的干扰。
图4示出了n＝3时，降噪模块3的具体电路结构。如图4所示，在n＝3时，选择模块2与三行栅线连接，分别为Gate1、Gate2和Gate3；选择模块2包括三个晶体管，分别为第十一晶体管M11、第十二晶体管M12和第十四晶体管M14，其漏极分别与栅线Gate1、Gate2和栅线Gate3连接；所述降噪模块3包括两个降噪单元30，该两个降噪单元30分别与栅线Gate2和Gate3对应。其中，与栅线Gate2对应的降噪单元30包括第十三晶体管M13，其控制极与栅线Gate2的输入端连接，源极与一低电压端VGL连接，漏极与栅线Gate1连接；在向栅线Gate2输入驱动信号时，输入到栅线Gate2上的驱动信号会将第十三晶体管M13开启，从而使栅线Gate1与低电压端VGL连接，这时栅线Gate1中的信号杂波就会减少，从而降低对输入到栅线Gate2中的驱动信号的干扰。与栅线Gate3对应的降噪单元30包括第十五晶体管M15和第十六晶体管M16，所述第十五晶体管M15的控制极与栅线Gate3连接，源极与低电压端VGL连接，漏极与栅线Gate1连接；所述第十六晶体管M16的控制极与栅线Gate3连接，源极与低电压端VGL连接，漏极与栅线Gate2连接；在向栅线Gate3输入驱动信号时，输入到栅线Gate3上的驱动信号会将第十五晶体管M15和第十六晶体管M16开启，从而使栅线Gate1和Gate2与低电压端VGL连接，这时栅线Gate1和Gate2中的信号杂波就会减少，从而降低对输入到栅线Gate3中的驱动信号的干扰。
以上仅以n＝2和n＝3为例，对降噪模块3的结构进行了详细描述，在n的值大于3时，所述降噪模块3的结构与上述类似，在此就不再赘述。
根据上述可知，在n＝2时，所述选择模块2和降噪模块3的结构最为简单，因此，在实际中，优选所述n的值为2，以使栅极驱动电路的线路结构更简单。
所述驱动信号生成模块1的具体结构可以如图2所示，具体地，其包括第一至第十晶体管M1至M10，以及第一电容C1；其中，所述第一晶体管M1 的控制极与信号输入端INPUT连接，源极与第一高电压端VDD连接，漏极与上拉结点PU连接；所述第二晶体管M2的控制极与复位信号端Reset连接，源极与第一低电压端VSS连接，漏极与上拉结点PU连接；所述第三晶体管M3的控制极与上拉结点PU连接，源极与第一时钟信号端CLK1连接，漏极与输出端OUTPUT连接；所述第四晶体管M4的控制极和源极与第二高电压端VGH连接，漏极与第五晶体管M5的控制极连接；所述第五晶体管M5的源极与第二高电压端VGH连接，漏极与下拉节点PD连接；所述第六晶体管M6的控制极与上拉节点PU连接，源极与第二低电压端VGL连接，漏极与下拉节点PD连接；所述第七晶体管M7的控制极与第一低电压端VSS连接，源极与第二低电压端VGL连接，漏极与输出端OUTPUT连接；所述第八晶体管M8的控制极与上拉节点PU连接，源极与第二低电压端VGL连接，漏极与所述第四晶体管M4的漏极和第五晶体管M5的控制极连接；所述第九晶体管M9的控制极与下拉节点PD连接，源极与第二低电压端VGL连接，漏极与上拉结点PU连接；所述第十晶体管M10的控制极与下拉节点PD连接，源极与第二低电压端VGL连接，漏极与输出端OUTPUT连接；所述第一电容C1的第一端与上拉结点PU连接，第二端与所述第三晶体管M3的漏极连接。
在此需要说明的是，除图2所述包括十个晶体管和一个电容的结构外，所述驱动信号生成模块1还可以为其他能够生成驱动信号的任何电路结构。
综上，本公开实施方式提供的移位寄存器单元，其输入向n行栅线的驱动信号由一个驱动信号生成模块1所生成，与相关技术相比，这样减少了驱动信号生成模块1的数量；而每个驱动信号生成模块1一般包括多个薄膜晶体管和电容等器件，因此，这样可以减少栅极驱动电路所占用的面积，从而有助于实现窄边框，增大显示装置的有效显示区的面积，提高显示装置的屏占比；同时，还可以给保护电路的布置提供足够的空间，这样可以提高电路的抗ESD能力。
本公开实施方式还提供上述移位寄存器单元的驱动方法。在该实施方式中，如图5所示，所述移位寄存器单元的驱动方法包括以下步骤S1和S2：
S1，生成驱动信号，所述驱动信号所持续的时间等于扫描n行栅线所需的时间，所述n≥2。
S2，将所述驱动信号依次输入n行栅线。
本公开实施方式提供的移位寄存器单元的驱动方法，其将生成的一个驱动信号依次输入n行栅线内，与相关技术相比，这样减少了用于生成驱动信号的驱动信号生成模块的数量；而驱动信号生成模块一般包括多个薄膜晶体管和电容等器件，因此，这样可以减少栅极驱动电路所占用的面积，从而有助于实现窄边框，增大显示装置的有效显示区的面积，提高显示装置的屏占比；同时，还可以给保护电路的布置提供足够的空间，这样可以提高电路的抗ESD能力。
本公开实施方式还提供一种栅极驱动电路。在该实施方式中，所述栅极驱动电路包括级联在一起的多个上述实施方式提供的移位寄存器单元。
本公开提供的栅极驱动电路，其包括上述实施方式提供的移位寄存器单元，可以减少栅极驱动电路所占用的面积，从而有助于实现窄边框，增大显示装置的有效显示区的面积，提高显示装置的屏占比；同时，还可以给保护电路的布置提供足够的空间，这样可以提高电路的抗ESD能力。
本公开实施方式还提供一种显示装置。在该实施方式中，所述显示装置包括上述实施方式提供的栅极驱动电路。
本公开提供的显示装置，其包括上述实施方式提供的栅极驱动电路，可以减少栅极驱动电路所占用的面积，从而有助于实现窄边框，增大显示装置的有效显示区的面积，提高显示装置的屏占比；同时，还可以给保护电路的布置提供足够的空间，这样可以提高电路的抗ESD能力。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示 例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (14)

  1. 一种移位寄存器单元，包括：
    驱动信号生成模块，所述驱动信号生成模块用于生成驱动n行栅线开启的驱动信号，所述驱动信号所持续的时间等于扫描n行栅线所需的时间；n≥2；以及
    选择模块，所述选择模块与所述驱动信号生成模块连接且与n行栅线的输入端连接，用于将所述驱动信号生成模块依次与n行栅线选通，将所述驱动信号生成模块生成的所述驱动信号依次输入所述n行栅线。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述选择模块包括n个薄膜晶体管和n个时钟信号端，每个薄膜晶体管的控制极与一时钟信号端连接，源极与驱动信号生成模块的输出端连接，漏极与所述n行栅线中的一行栅线的输入端连接。
  3. 根据权利要求2所述的移位寄存器单元，其中，所述n个时钟信号端分别用于向所述n个薄膜晶体管的控制极输入时钟信号，使得所述n个薄膜晶体管在所述驱动信号持续时间内依次打开。
  4. 根据权利要求3所述的移位寄存器单元，其中，所述选择模块中的n个薄膜晶体管为高电平有效，所述n个时钟信号端在所述驱动信号持续时间内依次输出高电平，且在所述驱动信号持续时间内的任意时刻有且仅有一个时钟信号端输出高电平。
  5. 根据权利要求1所述的移位寄存器单元，还包括降噪模块，所述降噪模块用于降低输入到栅线中的驱动信号的噪声。
  6. 根据权利要求5所述的移位寄存器单元，其中，所述降噪模块包括n-1个降噪单元，所述n-1个降噪单元分别与n行栅线中最后开启的n-1行栅线一一对应；
    每个降噪单元在其对应的栅线开启时，将先于该栅线开启的栅线的输入端与低电压端连接。
  7. 根据权利要求6所述的移位寄存器单元，其中，与n行栅线中的第m行栅线对应的降噪单元包括m-1个薄膜晶体管，2≤m≤n；
    且所述m-1个薄膜晶体管的控制极均与该第m行栅线的输入端连接，源极均与低电压端连接，漏极分别与n行栅线中的第1至第m-1行栅线的输入端一一对应地连接。
  8. 根据权利要求1至7任意一项所述的移位寄存器单元，其中，所述n等于2。
  9. 根据权利要求1至7任意一项所述的移位寄存器单元，其中，所述驱动信号生成模块包括第一至第十晶体管，信号输入端，输出端，第一高电压端，第二高电压端，复位信号端，第一低电压端，第二低电压端，上拉结点，下拉节点，第一时钟信号端以及第一电容；
    所述第一晶体管的控制极与所述信号输入端连接，源极与所述第一高电压端连接，漏极与所述上拉结点连接；
    所述第二晶体管的控制极与所述复位信号端连接，源极与所述第一低电压端连接，漏极与所述上拉结点连接；
    所述第三晶体管的控制极与所述上拉结点连接，源极与所述第一时钟信号端连接，漏极与所述输出端连接；
    所述第四晶体管的控制极和源极与所述第二高电压端连接，漏极与第五晶体管的控制极连接；
    所述第五晶体管的源极与所述第二高电压端连接，漏极与所述下拉节点连接；
    所述第六晶体管的控制极与所述上拉节点连接，源极与所述第二低电压端连接，漏极与所述下拉节点连接；
    所述第七晶体管的控制极与所述第一低电压端连接，源极与所述第二低电压端连接，漏极与所述输出端连接；
    所述第八晶体管的控制极与所述上拉节点连接，源极与所述第二低电压端连接，漏极与所述第四晶体管的漏极和第五晶体管的控制极连接；
    所述第九晶体管的控制极与所述下拉节点连接，源极与所述第二低电压端连接，漏极与所述上拉结点连接；
    所述第十晶体管的控制极与所述下拉节点连接，源极与所述第二低电压端连接，漏极与所述输出端连接；
    所述第一电容的第一端与所述上拉结点连接，第二端与所述第三晶体管的漏极连接。
  10. 一种用于驱动权利要求1至9任意一项所述的移位寄存器单元的驱动方法，包括：
    生成驱动信号，所述驱动信号所持续的时间等于扫描n行栅线所需的时间，所述n≥2；
    将所述驱动信号依次输入n行栅线。
  11. 一种栅极驱动电路，包括级联在一起的多个移位寄存器单元，所述移位寄存器单元为权利要求1至9任意一项所述的移位寄存器单元。
  12. 根据权利要求11所述的栅极驱动电路，其中所述多个移位寄存器单元设置在栅线的一侧。
  13. 根据权利要求11所述的栅极驱动电路，其中所述多个移位寄存器单元设置在栅线的两侧。
  14. 一种显示装置，包括权利要求11-13任意一项所述的栅极驱动电路。
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