WO2019157842A1 - 移位寄存器单元、栅极驱动电路、显示装置及驱动方法 - Google Patents

移位寄存器单元、栅极驱动电路、显示装置及驱动方法 Download PDF

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Publication number
WO2019157842A1
WO2019157842A1 PCT/CN2018/114827 CN2018114827W WO2019157842A1 WO 2019157842 A1 WO2019157842 A1 WO 2019157842A1 CN 2018114827 W CN2018114827 W CN 2018114827W WO 2019157842 A1 WO2019157842 A1 WO 2019157842A1
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Prior art keywords
transistor
sub
node
shift register
pull
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PCT/CN2018/114827
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English (en)
French (fr)
Inventor
冯雪欢
韦晓龙
李永谦
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP18884840.2A priority Critical patent/EP3754634A4/en
Priority to US16/468,439 priority patent/US11263973B2/en
Publication of WO2019157842A1 publication Critical patent/WO2019157842A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • Embodiments of the present disclosure relate to a shift register unit, a gate driving circuit, a display device, and a driving method.
  • a pixel array typically includes a plurality of rows of gate lines and a plurality of columns of data lines interleaved therewith.
  • the driving of the gate lines can be realized by an attached integrated driving circuit.
  • the gate line driving circuit can be directly integrated on the thin film transistor array substrate to form a GOA (Gate driver On Array) to drive the gate line.
  • a GOA composed of a plurality of cascaded shift register units may be used to provide a switching state voltage signal for a plurality of rows of gate lines of the pixel array, thereby controlling the plurality of rows of gate lines to be sequentially turned on, and corresponding to the pixel arrays by the data lines.
  • the pixel units of the row provide data signals to form the gray voltages required to display the gray levels of the image, thereby displaying each frame of image.
  • At least one embodiment of the present disclosure provides a shift register unit including a display sub-shift register and a detection sub-shift register.
  • the display sub-shift register includes a display output, the display sub-shift register configured to output a display output signal of the shift register unit from the display output during a display phase; the detection sub-shift register and The display output of the display sub-shift register is coupled to receive the display output signal, and includes a first random pulse signal terminal to receive a first random pulse signal, the detection sub-shift register configured to be at the display output The detection output signal of the shift register unit is output when the signal and the first random pulse signal are simultaneously turned on.
  • the detection sub-shift register includes a first detection input sub-circuit, a first pull-up node reset sub-circuit, and a detection output sub-circuit; the first detection The input sub-circuit is configured to charge the first pull-up node in response to the display output signal and the first random pulse signal; the first pull-up node reset sub-circuit is configured to respond to the first reset signal The first pull-up node performs resetting; the detection output sub-circuit is configured to output the first clock signal to the detection output terminal under the control of the level of the first pull-up node.
  • the detector shift register further includes a first pull-up node noise reduction sub-circuit, a first output noise reduction sub-circuit, and a first pull-down sub-circuit;
  • the first pull-up node noise reduction sub-circuit is configured to perform noise reduction on the first pull-up node under control of a level of the first pull-down node;
  • the detection output noise reduction sub-circuit is configured in the The detection output end is noise-reduced under the control of the level of the first pull-down node;
  • the first pull-down sub-circuit is configured to control the level of the first pull-up node The level of the first pulldown node is controlled.
  • the first detection input sub-circuit includes a first transistor and a second transistor; a gate of the first transistor is configured to be connected to the display output end Receiving the display output signal, the first pole of the first transistor is configured to be coupled to the second clock signal terminal to receive the second clock signal, and the second pole of the first transistor is configured to be the second transistor a first pole connection; a gate of the second transistor configured to be coupled to the first random pulse signal terminal to receive the first random pulse signal, a second pole of the second transistor, and the first Pull up the node connection.
  • the first detection input sub-circuit includes a first transistor.
  • a gate of the first transistor is configured to be coupled to the display output to receive the display output signal
  • a first pole of the first transistor is configured to be coupled to the first random pulse signal terminal to receive the a first random pulse signal
  • the second pole of the first transistor is configured to be connected to the first pull-up node
  • the gate of the first transistor is configured to be connected to the first random pulse signal end
  • a first pole of the first transistor is configured to be coupled to the display output to receive the display output signal
  • a second pole of the first transistor is configured to A pull up node is connected.
  • the first pull-up node reset sub-circuit includes a third transistor, and a gate of the third transistor is configured to be connected to the first reset terminal to receive the a first reset signal, a first pole of the third transistor is configured to be coupled to the first pull-up node, and a second pole of the third transistor is configured to be coupled to the first voltage terminal to receive the first voltage signal
  • the detection output sub-circuit includes a fourth transistor and a first storage capacitor, a gate of the fourth transistor configured to be coupled to the first pull-up node, and a first pole of the fourth transistor configured to a first clock signal terminal is coupled to receive the first clock signal, and a second pole of the fourth transistor is configured to be coupled to the detection output terminal to output the detection output signal; a first of the first storage capacitor a pole connected to the first pull-up node, a second pole of the first storage capacitor being connected to the detection output; or the first pull-up node noise reduction sub-circuit comprising
  • the first pull-down sub-circuit further includes a ninth transistor and a tenth transistor.
  • the gate of the ninth transistor is connected to the first pole, and is configured to be connected to the third voltage terminal to receive the third voltage signal, and the second pole of the ninth transistor is connected to the first pull-down node; a gate of the tenth transistor is connected to the first pull-up node, a first pole of the tenth transistor is connected to the first pull-down node, and a second pole of the tenth transistor is configured to be
  • the first voltage terminal is coupled to receive the first voltage signal.
  • the detection sub-shift register further includes a second detection input sub-circuit and a detection input.
  • the second detection input sub-circuit is configured to be coupled to the detection input to receive a detection input signal and to charge the first pull-up node in response to the detection input signal.
  • the second detection input sub-circuit includes an eleventh transistor.
  • a gate of the eleventh transistor is coupled to the first electrode, and is configured to be coupled to the detection input to receive the detection input signal, a second pole of the eleventh transistor and the first pull-up Connected to the node, or the gate of the eleventh transistor is configured to be connected to the detection input to receive the detection input signal, and the first pole of the eleventh transistor is configured to be connected to the third clock signal end To receive the third clock signal, the second pole of the eleventh transistor is connected to the first pull-up node.
  • the first pull-up node reset sub-circuit further includes a twelfth transistor. a gate of the twelfth transistor and a second reset terminal are connected to receive a second reset signal, a first pole of the twelfth transistor is connected to the first pull-up node, and a first transistor of the twelfth transistor The diode is coupled to the first voltage terminal to receive the first voltage signal.
  • the first detection input sub-circuit further includes a random pulse signal control sub-circuit and a second random pulse signal end.
  • the random pulse signal control sub-circuit is configured to be coupled to the display output, the first random pulse signal end, and the second random pulse signal end to receive the display output signal, the first random pulse signal, and the second random pulse signal, and responsive to The display output signal, the first random pulse signal, and the second random pulse signal cause the first random pulse signal and the second random pulse signal to be simultaneously active levels.
  • the random pulse signal control sub-circuit includes a fifty-first transistor, a fifty-second transistor, a fifty-third transistor, a fifty-fourth transistor, and a Five storage capacitors and a sixth storage capacitor.
  • a gate of the fifty-first transistor is connected to the first random pulse signal end, a first pole is connected to the display output, and a second pole is connected to a gate of the first transistor; a gate of the twelve transistors is connected to the second pulse signal terminal, a first pole is connected to the display output terminal, a second pole is connected to a gate of the second transistor, and a gate of the fifty-third transistor is connected a pole connected to the first clock signal terminal, a first pole connected to a gate of the first transistor, a second pole connected to the first voltage terminal, a gate of the fifty-fourth transistor and the a first clock signal terminal connected, a first pole connected to a gate of the second transistor, a second pole connected to the first voltage terminal; a first pole of the fifth storage capacitor and the first transistor a gate is connected, a second pole is connected to the first voltage terminal, a first pole of the sixth storage capacitor is connected to a gate of the second transistor, and a second pole is connected to the first voltage terminal.
  • the detection sub-shift register unit further includes a leak-proof electronic circuit.
  • the leak-proof electronic circuit is configured to maintain a high potential of the first pull-up node under control of a level of the first pull-up node.
  • the leakage prevention electronic circuit includes a thirteenth transistor, and a gate of the thirteenth transistor is connected to the first pull-up node, and the a first pole and a fourth voltage terminal of the thirteen transistor are connected to receive a fourth voltage signal, a second pole of the thirteenth transistor is connected to a feedback node; or the second detection input subcircuit includes an eleventh transistor and a fourteenth transistor; a gate of the eleventh transistor is configured to be coupled to the sense input to receive the sense input signal, and a first pole of the eleventh transistor is configured to be coupled to the third clock signal terminal for receiving a third clock signal, a second pole of the eleventh transistor is coupled to a first pole of the fourteenth transistor, and is configured to be coupled to the feedback node; a gate of the fourteenth transistor and the a gate of the eleventh transistor, the second pole of the fourteenth transistor is connected to the first pull-up node; or the first pull-up node reset sub-circuit includes
  • the display sub-shift register includes a display input sub-circuit, a second pull-up node reset sub-circuit, and a display output sub-circuit.
  • the display input sub-circuit is configured to charge the second pull-up node in response to the display input signal;
  • the second pull-up node reset sub-circuit is configured to respond to the third reset signal received by the third reset terminal The two pull-up nodes perform resetting;
  • the display output sub-circuit is configured to output a fourth clock signal to the display output terminal under the control of the level of the second pull-up node.
  • the display sub-shift register further includes a second pull-up node noise reduction circuit, a display output noise reduction sub-circuit, and a second pull-down sub-circuit;
  • the second pull-up node noise reduction sub-circuit is configured to perform noise reduction on the second pull-up node under control of a level of the second pull-down node;
  • the display output noise reduction sub-circuit is configured in the second pull-down node Under the control of the level, the display output end is noise-reduced;
  • the second pull-down sub-circuit is configured to control the power of the second pull-down node under the control of the level of the second pull-up node Level control.
  • a shift register unit provided by an embodiment of the present disclosure further includes an output control circuit.
  • the output control circuit is coupled to the first pull-up node and the first pull-down node of the detection sub-shift register and to the second pull-up node and the second pull-down node of the display sub-shift register, and configured to When one of the first pull-up node and the second pull-up node is at an active level, the other is pulled low.
  • the output control circuit includes a display output control sub-circuit and a detection output control sub-circuit.
  • the detection output control sub-circuit is configured to control levels of the second pull-up node and the second pull-down node under control of a level of the first pull-up node;
  • the display output control The sub-circuit is configured to control the levels of the first pull-up node and the first pull-down node under control of a level of the second pull-up node.
  • a shift register unit provided by an embodiment of the present disclosure further includes a logic OR circuit.
  • the logic OR circuit is coupled to the display output of the display sub-shift register and the detection output of the detection sub-shift register, and is configured to OR the display output signal and the detection output signal Get a composite output signal.
  • the logic OR circuit includes a first logic or input sub-circuit, a second logic or input sub-circuit, a first output control sub-circuit, and a second output control sub- The circuit, the first node noise reduction sub-circuit, the second node noise reduction sub-circuit, the output noise reduction control sub-circuit, and the output noise reduction sub-circuit.
  • the first logic or input subcircuit is configured to charge a first node in response to the detected output signal; the second logic or input subcircuit is configured to charge a second node in response to the display output signal;
  • the first output control sub-circuit is configured to output the detection output signal under control of a level of the first node; the second output control sub-circuit is configured to be at a level of the second node Controlling, outputting the display output signal;
  • the first node noise reduction circuit is configured to perform noise reduction on the first node under control of a level of the display output signal;
  • the circuit is configured to perform noise reduction on the second node under control of the level of the detected output signal;
  • the output noise reduction control sub-circuit is configured to be electrical at the display output signal and the detection output signal
  • the level of the third node is controlled under the control of the third node; the output noise reduction sub-circuit is configured to perform noise reduction on the logic or the output under the control of the level of the third node.
  • At least one embodiment of the present disclosure also provides a gate driving circuit including a plurality of cascaded shift register units provided by embodiments of the present disclosure.
  • a first random pulse signal end of each of the shift register units of the shift register unit is connected to the first random pulse signal line; except for the first stage display sub-shift register, the remaining stages display the sub-shift register
  • the display input terminal is connected to the display output terminal of the upper display sub-shift register; except for the last-level display sub-shift register, the third reset end and the next-level display sub-shift of the remaining stages display sub-shift register
  • the display output of the register is connected.
  • At least one embodiment of the present disclosure also provides a gate driving circuit including a plurality of cascaded shift register units provided by embodiments of the present disclosure.
  • a first random pulse signal end of each of the shift register units of the shift register unit is connected to the first random pulse signal line; except for the first stage display sub-shift register, the remaining stages display the sub-shift register
  • the display input terminal is connected with the display output terminal of the upper display sub-shift register; except for the first-level detection sub-shift register, the detection input terminal of the remaining level detection sub-shift register and the upper-level detection sub-shift register The detection output is connected.
  • At least one embodiment of the present disclosure also provides a gate driving circuit including a plurality of cascaded shift register units provided by embodiments of the present disclosure.
  • a first random pulse signal end of each of the shift register units of the shift register unit is coupled to a first random pulse signal line; a second random pulse signal of a detection sub-shift register of each of the shift register units
  • the terminal is connected to the second random pulse signal line; except for the first stage and the second stage display sub-shift register unit, the display inputs of the sub-shift register and the upper display sub-shift register of the other stage are separated by one stage
  • the display output terminal is connected; except for the first-level detection sub-shift register, the detection input ends of the remaining levels of the detection sub-shift registers are connected to the detection output ends of the upper-level detection sub-shift registers.
  • At least one embodiment of the present disclosure further provides a display device including a gate driving circuit provided by any embodiment of the present disclosure.
  • a display device further includes a random pulse generating circuit.
  • the random pulse generating circuit is configured to generate the first random pulse signal and is connected to the first random pulse signal line.
  • At least one embodiment of the present disclosure further provides a driving method of a gate driving circuit, including: a display output end of an Nth stage display sub shift register outputs a display output signal; and an Nth stage detecting sub shift register is responsive to the display The output signal and the first random pulse signal charge the first pull-up node; the Nth-level detection sub-shift register outputs a detection output signal; N is an integer greater than one.
  • At least one embodiment of the present disclosure further provides a driving method of a gate driving circuit, including: a display output end of an Nth stage display sub shift register outputs a display output signal; and an Nth stage detecting sub shift register is responsive to the display The output signal, the first random pulse signal, and the second random pulse signal charge the first pull-up node; the Nth-level detection sub-shift register outputs a detection output signal; N is an integer greater than one .
  • the shift register unit, the gate driving circuit, the display device, and the driving method provided by the embodiments of the present disclosure can eliminate the problem of the scanning line and the brightness unevenness caused by the progressive scanning by detecting the random detecting function of the sub shift register. Further, it is also allowed to more fully compensate for the non-uniformity of the threshold voltage and mobility of the driving transistor in the pixel circuit, the aging of the OLED, and the like, thereby improving the display quality of the display device.
  • 1A is a schematic diagram of a pixel circuit
  • 1B is a schematic diagram of another pixel circuit
  • 1C is a schematic diagram of still another pixel circuit
  • 1D is a schematic diagram of still another pixel circuit
  • Figure 1E is a graph of a sense voltage as a function of time
  • FIG. 2 is a schematic diagram of a shift register unit according to an embodiment of the present disclosure
  • Figure 3A is a schematic diagram of a detection sub-shift register of the shift register unit shown in Figure 2;
  • 3B is a schematic diagram of another detection sub-shift register of the shift register unit shown in FIG. 2;
  • 4A is a circuit diagram showing a specific implementation example of the detector shift register shown in FIG. 3B;
  • 4B is a circuit diagram showing another specific implementation example of the detector shift register shown in FIG. 3B;
  • 4C is a circuit diagram showing still another specific implementation example of the detector shift register shown in FIG. 3B;
  • 4D is a circuit diagram showing still another specific implementation example of the detector shift register shown in FIG. 3B;
  • 5A is a schematic diagram of another detection sub-shift register of the shift register unit shown in FIG. 2;
  • 5B is a circuit diagram showing a specific implementation example of the detector shift register shown in FIG. 5A;
  • 5C is a circuit diagram showing another specific implementation example of the detector shift register shown in FIG. 5A;
  • 5D is a circuit diagram showing still another specific implementation example of the detector shift register shown in FIG. 5A;
  • 5E is a circuit diagram of a random pulse control sub-circuit of the detector shift register shown in FIG. 5D;
  • 5F is a circuit diagram of a random pulse control sub-circuit of the detector shift register shown in FIG. 5A;
  • 5G is a circuit diagram of a random pulse control sub-circuit of the detector shift register shown in FIG. 5A;
  • 5H is a circuit diagram of a random pulse control sub-circuit of the detector shift register shown in FIG. 5A;
  • 6A is a schematic diagram of another detection sub-shift register of the shift register unit shown in FIG. 2;
  • Figure 6B is a circuit diagram showing a specific implementation example of the detector shift register shown in Figure 6A;
  • FIG. 7A is a schematic diagram of a display sub-shift register of the shift register unit shown in FIG. 2;
  • FIG. 7B is a schematic diagram of another display sub-shift register of the shift register unit shown in FIG. 2;
  • FIG. 7C is a circuit diagram showing a specific implementation example of the display sub-shift register shown in FIG. 7B;
  • FIG. 8A is a schematic diagram of another shift register unit according to an embodiment of the present disclosure.
  • FIG. 8B is a schematic diagram of another shift register unit according to an embodiment of the present disclosure.
  • FIG. 9A is a schematic diagram of an output control circuit shown in FIG. 8A;
  • FIG. 9B is a circuit diagram showing a specific implementation example of the output control circuit shown in FIG. 9A;
  • 9C is a circuit diagram showing a specific implementation example of a shift register shown in FIG. 8A;
  • 9D is a circuit diagram showing a specific implementation example of a shift register shown in FIG. 8B;
  • FIG. 10 is a schematic diagram of another shift register unit according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a logic or circuit shown in FIG. 10;
  • 11B is a circuit diagram showing a specific implementation example of the logic or circuit shown in FIG. 11A;
  • FIG. 12A is a schematic diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 12B is a schematic diagram of another gate driving circuit according to an embodiment of the present disclosure.
  • 12C is a schematic diagram of still another gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 13A is a signal timing diagram corresponding to operation of a display sub-shift register in the gate driving circuit shown in FIG. 12A; FIG.
  • FIG. 13B is a signal timing diagram corresponding to the operation of the detector shift register in the gate driving circuit shown in FIG. 12A; FIG.
  • Figure 13C is a signal timing diagram corresponding to the operation of the logic or circuit shown in Figure 11A;
  • 13D is a signal timing diagram corresponding to the operation of the display sub-shift register in the gate driving circuit shown in FIG. 12C;
  • 13E is a signal timing diagram corresponding to the operation of the detector shift register in the gate driving circuit shown in FIG. 12C;
  • FIG. 13F is another signal timing diagram corresponding to the operation of the detector shift register in the gate driving circuit shown in FIG. 12C; FIG.
  • FIG. 14A is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 14B is a schematic diagram of another display device according to an embodiment of the present disclosure.
  • the pixel circuit in the OLED display device generally adopts a matrix driving method, and is divided into an active matrix driving and a passive matrix driving according to whether or not a switching component is introduced in each pixel unit.
  • AMOLED integrates a set of thin film transistors and storage capacitors in the pixel circuit of each pixel. Through the driving control of the thin film transistor and the storage capacitor, the current flowing through the OLED is controlled, so that the OLED emits light as needed.
  • the basic pixel circuit used in the AMOLED display device is usually a 2T1C pixel circuit, that is, a function of driving the OLED to emit light by using two thin film transistors (TFTs) and one storage capacitor Cst.
  • 1A and 1B are schematic views showing two 2T1C pixel circuits, respectively.
  • a 2T1C pixel circuit includes a switching transistor T0, a driving transistor N0, and a storage capacitor Cst.
  • the gate of the switching transistor T0 is connected to the scan line to receive the scan signal Scan1; for example, the source of the switching transistor T0 is connected to the data line to receive the data signal Vdata; the drain of the switching transistor T0 is connected to the driving transistor N0.
  • the 2T1C pixel circuit is driven by two TFTs and a storage capacitor Cst to control the brightness and darkness (grayscale) of the pixel.
  • the data signal Vdata input by the data driving circuit through the data line can charge the storage capacitor Cst through the switching transistor T0, whereby the data signal Vdata can be stored in the storage capacitor Cst And the stored data signal Vdata can control the degree of conduction of the driving transistor N0, thereby controlling the magnitude of the current flowing through the driving transistor N0 to drive the OLED to emit light, that is, the current determines the gray scale of the pixel illumination.
  • the switching transistor T0 is an N-type transistor and the driving transistor N0 is a P-type transistor.
  • another 2T1C pixel circuit also includes a switching transistor T0, a driving transistor N0, and a storage capacitor Cst, but the connection mode thereof is slightly changed, and the driving transistor N0 is an N-type transistor.
  • the variation of the pixel circuit of FIG. 1B with respect to FIG. 1A includes that the positive terminal of the OLED is connected to the first voltage terminal to receive the first voltage Vdd (high voltage), and the negative terminal is connected to the drain of the driving transistor N0, and the driving transistor The source of N0 is connected to the second voltage terminal to receive the second voltage Vss (low voltage, such as ground voltage).
  • the operation mode of the 2T1C pixel circuit is basically the same as that of the pixel circuit shown in FIG. 1A, and details are not described herein again.
  • the switching transistor T0 is not limited to the N-type transistor, and may be a P-type transistor, and only the control scan signal Scan1 needs to be changed accordingly.
  • An OLED display device typically includes a plurality of pixel units arranged in an array, each of which may include, for example, the above-described pixel circuits.
  • the output current I OLED of the driving transistor N0 in the pixel circuit in a saturated state can be obtained by the following formula:
  • I OLED 1/2*K(Vg-Vs-Vth) 2
  • K W / L * C * ⁇
  • W / L is the width to length ratio of the channel of the driving transistor N0 (that is, the ratio of the width to the length)
  • ⁇ is the electron mobility
  • C is the capacitance per unit area
  • Vs is the voltage of the source of the driving transistor N0
  • Vth is the threshold voltage of the driving transistor N0.
  • K is referred to as a current coefficient of a driving transistor in the pixel circuit, and the following embodiments are the same as those described herein, and are not described again.
  • the threshold voltage Vth of the driving transistor in each pixel circuit may be different due to the fabrication process, and the threshold voltage Vth of the driving transistor may cause a drift phenomenon due to, for example, a change in temperature.
  • the current coefficient K of the driving transistor also ages over time. Therefore, the difference between the threshold voltage Vth and the current coefficient K of each of the driving transistors and aging may cause display failure (for example, display unevenness), so it is necessary to compensate the threshold voltage Vth and the current coefficient K.
  • a data signal eg, data voltage
  • Vdata may charge the storage capacitor Cst, and since the data signal Vdata may cause the driving transistor N0 to be turned on,
  • the voltage Vs of the source or the drain of the driving transistor N0 electrically connected to one end of the storage capacitor Cst may be changed correspondingly.
  • FIG. 1C shows a pixel circuit (that is, a 3T1C circuit) that can detect a threshold voltage of a driving transistor, and the driving transistor N0 is an N-type transistor.
  • the sensing transistor S0 may be introduced on the basis of the 2T1C circuit, that is, the first end of the sensing transistor S0 may be connected to the source of the driving transistor N0, and the sensing may be performed.
  • the second end of the transistor S0 is connected to a detection circuit (not shown) via a sensing line, and the gate of the sensing transistor S0 receives the compensation scan signal Scan2.
  • the compensation scan signal Scan2 can be applied, thereby charging the detecting circuit via the sensing transistor S0, so that the source potential of the driving transistor N0 is changed.
  • the driving transistor N0 is turned off.
  • the sensing voltage that is, the voltage Vb of the source after the driving transistor N0 is turned off
  • the scan signal Scan1 and the compensated scan signal Scan2 may also be provided by the same gate scan line.
  • the pixel circuit can perform current detection while illuminating the organic light emitting diode to emit light.
  • FIG. 1E shows a graph of a sense voltage as a function of time taken from the source of the drive transistor N0 via the turned-on sense transistor S0.
  • the charging speed is correspondingly lowered (that is, the speed at which the sensing voltage increases) Lower) (see FIG. 1E), because the charging current will decrease as the sensing voltage (ie, the voltage Vs of the source of the driving transistor N0) increases.
  • the output current I OLED of the driving transistor N0 in a saturated state can be obtained by the following formula:
  • I OLED 1/2*K(Vg-Vs-Vth) 2
  • K W / L * C * ⁇
  • W / L is the aspect ratio (i.e., the ratio of the width to the length) of the channel of the driving transistor N0
  • ⁇ is the electron mobility
  • C is the capacitance per unit area.
  • the corresponding GOA circuit typically also includes a display portion and a Sense portion.
  • the display portion is used for display of an image
  • the detecting portion is for detecting or compensating for the threshold voltage and mobility non-uniformity of the driving transistor N0 in the pixel circuit and the aging of the OLED, etc., both of which are indispensable.
  • the GOA circuit since the GOA circuit usually compensates by means of sequential scanning, on the one hand, along with the progressive scanning of the GOA circuit, it is displayed during the compensation process. A scan line moving line by line appears in the panel, thus seriously affecting the display quality of the OLED display panel; on the other hand, the brightness of different areas of the display panel is uneven due to the difference in compensation time caused by the progressive scan.
  • At least one embodiment of the present disclosure provides a shift register unit including a display sub-shift register and a sense (Sense) sub-shift register.
  • the display sub-shift register includes a display output configured to output a display output signal of the shift register unit from the display output terminal; the detection sub-shift register is coupled to the display output end of the display sub-shift register to receive the display output signal, and includes The first random pulse signal terminal receives the first random pulse signal.
  • the detection sub-shift register is configured to include a detection output signal of the output shift register unit when the display output signal is turned on and the first random pulse signal is turned on.
  • Embodiments of the present disclosure also provide a gate driving circuit, a display device, and a driving method corresponding to the shift register unit described above.
  • the shift register unit, the gate driving circuit, the display device, and the driving method provided by the embodiments of the present disclosure can eliminate the problem of the scanning line and the brightness unevenness caused by the progressive scanning by detecting the random detecting function of the sub shift register. Further, it is also allowed to more fully compensate for the non-uniformity of the threshold voltage and mobility of the driving transistor in the pixel circuit, the aging of the OLED, and the like, thereby improving the display quality of the display device.
  • FIG. 2 is a schematic diagram of a shift register unit according to an embodiment of the present disclosure.
  • the shift register unit 10 includes a detection sub-shift register 100 and a display sub-shift register 200.
  • display sub-shift register 200 includes a display output (not shown) and is configured to output a display output signal of the shift register unit from the display output during the display phase.
  • the display output signal output from the sub shift register 200 is displayed for controlling the image display of the display panel.
  • the display output signal output from the display sub-shift register 200 is also used for non-uniformity of threshold voltage and mobility of the driving transistor in the pixel circuit and OLED. The aging and the like are compensated.
  • the detection sub-shift register 100 is coupled to the display output of the display sub-shift register 200 to receive a display output signal.
  • the detection sub-shift register 100 further includes a first random pulse signal terminal OE1 to receive the first random pulse signal.
  • the detector shift register 100 is configured to output a detection output signal of the shift register unit when the display output signal and the first random pulse signal are simultaneously turned on.
  • the detection output signal of the detector shift register 100 is used to compensate for non-uniformity of threshold voltage and mobility of the driving transistor in the pixel circuit, aging of the OLED, and the like.
  • the detection output signal of the detection sub-shift register 100 is also used to control image display of the display panel.
  • the display output signal is transmitted as a control scan signal Scan1 through the gate scan line to the gate of the switching transistor of the pixel circuit in FIG. 1C to control the writing operation of the data signal, and the detection output signal is compensated as the compensated scan signal Scan2.
  • the scan line is transmitted to the gate of the sense transistor in FIG. 1C to control the compensation operation of the threshold voltage and mobility of the drive transistor N0.
  • the display output signal and the detection output signal can also be transmitted to the gates of the switching transistor T0 and the sensing transistor S0 in the pixel circuit shown in FIG. 1D through the same scanning line to control the writing operation and driving of the data signal.
  • the first random pulse signal is generated by a random pulse generating circuit, and the first random pulse signal is transmitted to the detecting sub shift register 100 through the first random pulse signal line.
  • the display device of the driving circuit can effectively avoid the problem of the scanning line and the brightness unevenness caused by the progressive scanning, and can further compensate the threshold voltage and the mobility of the driving transistor in the pixel circuit, thereby improving the display quality.
  • the exemplary detector shift register 100 includes a first sense input sub-circuit 110, a first pull-up node reset sub-circuit 120, and a sense output sub-circuit 130.
  • the first detection input sub-circuit 110 is configured to charge the first pull-up node PU1 in response to the display output signal and the first random pulse signal.
  • the first detection input sub-circuit 110 can be connected to the first input terminal INPUT1, the first random pulse signal terminal OE1 and the first pull-up node PU1 of the detection sub-shift register.
  • the first input INPUT1 is configured to be coupled to the display output to receive a display output signal that displays the sub-shift register 200.
  • the first detection input sub-circuit 110 is configured to enable the first pull-up node PU1 under the common control of the display output signal received by the first input terminal INPUT1 and the first random pulse signal received by the first random pulse signal terminal OE1.
  • the first input terminal INPUT1 or the first random pulse signal terminal OE1 is electrically connected or additionally provided with a high voltage terminal, so that the first input terminal INPUT1 or the first random pulse signal terminal OE1 is input with a high level signal, Or the high level signal outputted by the high voltage terminal charges the first pull-up node PU1 to increase (pull-up) the voltage of the first pull-up node PU1 to control the detection output sub-circuit 130 to be turned on.
  • the first pull-up node reset sub-circuit 120 is configured to reset the first pull-up node PU1 in response to the first reset signal, so that the voltage of the first pull-up node PU1 is decreased (pulled low), thereby causing the detection output to be Circuit 130 is no longer conducting.
  • the first reset signal is a global reset signal, which can reset all of the first pull-up nodes PU1 of the detection sub-shift register 100.
  • the first pull-up node reset sub-circuit 120 can be configured to be connected to the first reset terminal RST1, so that the first pull-up node PU1 and the low can be made under the control of the first reset signal input by the first reset terminal RST1.
  • the level signal or the low voltage terminal is electrically connected, and the low voltage terminal is, for example, the first voltage terminal VGL1, so that the first pull-up node PU1 can be pulled down and reset.
  • the first voltage terminal VGL1 can be configured to maintain an input DC low-level signal, for example, and the DC low-level signal is referred to as a first voltage signal.
  • the following embodiments are the same, and are not described again.
  • the detection output sub-circuit 130 is configured to be under the control of the level of the first pull-up node PU1, so that the first clock signal can be output to the detection output terminal OUT1 as the detection output signal of the detection sub-shift register unit 100, To compensate for the threshold voltage and mobility of the drive transistor in the pixel circuit connected thereto, and the aging of the OLED, and the like.
  • the detection output sub-circuit 130 can be configured to be turned on under the control of the level of the first pull-up node PU1 to electrically connect the first clock signal terminal CLK1 and the detection output terminal OUT1, so that the first clock signal terminal can be The first clock signal of the CLK1 input is output to the detection output terminal OUT1.
  • the detection sub-shift register 100 further includes a first pull-up node noise reduction sub-circuit 140, An output noise reduction sub-circuit 150 and a first pull-down sub-circuit 160.
  • the first pull-up node noise reduction sub-circuit 140 is configured to perform noise reduction on the first pull-up node PU1 under the control of the level of the first pull-down node PD1.
  • the first pull-up node noise reduction circuit 140 can be configured to be connected to the first voltage terminal VGL1 to enable the first pull-up node PU1 and the first voltage terminal under the control of the level of the first pull-down node PD1.
  • VGL1 is electrically connected to perform pull-down and noise reduction on the first pull-up node PU1.
  • the first output noise reduction sub-circuit 150 is configured to denoise the detection output OUT1 under the control of the level of the first pull-down node PD1.
  • the first output noise reduction sub-circuit 150 can be configured to electrically connect the detection output terminal OUT1 and the first voltage terminal VGL1 under the control of the level of the first pull-down node PD1, thereby pulling down the detection output terminal OUT1. Noise reduction.
  • the first pull-down sub-circuit 160 is configured to control the level of the first pull-down node PD1 under the control of the level of the first pull-up node PU1.
  • the first pull-down sub-circuit 160 may connect the first voltage terminal VGL1, the second voltage terminal VGH1, the first pull-up node PU1, and the first pull-down node PD1 to the level of the first pull-up node PU1.
  • Controlling, the first pull-down node PD1 and the first voltage terminal VGL1 are electrically connected, thereby controlling the level of the first pull-down node PD1, so that when the first pull-up node PU1 is at a high potential, the first pull-down Node PD1 is at a low potential.
  • the first pull-down sub-circuit 160 can electrically connect the first pull-down node PD1 and the second voltage terminal VGH1 under the control of the level of the second voltage terminal VGH1, thereby making the first pull-down node PD1 is at a high potential.
  • the second voltage terminal VGH1 may be configured to maintain an input DC high level signal, and the DC high level is referred to as a second voltage signal.
  • the embodiments of the present disclosure are the same as those herein and will not be described again.
  • the detector shift register 100 shown in FIG. 3B may be embodied in one example as the circuit structure shown in FIG. 4A.
  • each transistor is an N-type transistor as an example, and accordingly, a high level applied to its gate is an on voltage and a low level is an off voltage to realize switching control of the N-type transistor.
  • a high level applied to its gate is an on voltage and a low level is an off voltage to realize switching control of the N-type transistor.
  • these do not constitute a limitation on the embodiments of the present disclosure.
  • the first detection input sub-circuit 110 can be implemented as a first transistor T1 and a second transistor T2.
  • the gate of the first transistor T1 is configured to be connected to the display output (ie, the first input terminal INPUT1) to receive the display output signal
  • the first pole is configured to be coupled to the second clock signal terminal CLK2 to receive the second clock signal
  • second The pole is configured to be coupled to the first pole of the second transistor T2
  • the gate of the second transistor T2 is configured to be coupled to the first random pulse signal terminal OE1 to receive the first random pulse signal, the second pole and the first pull-up node PU1 Connected so that when the first transistor T1 receives the turn-on signal (high level signal) due to the first input terminal INPUT1 and the second transistor T2 receives the turn-on signal due to the first random pulse signal terminal OE1 (high level signal)
  • the first pull-up node PU1 is charged with a high level signal of the second clock signal received by the second clock signal terminal CLK2 to be
  • the first detection input sub-circuit 110 can also be implemented as only the first transistor T1.
  • the gate of the first transistor T1 is configured to be connected to the display output (ie, the first input terminal INPUT1) to receive the display output signal, and the first pole is configured to be connected to the first random pulse signal terminal OE1.
  • the second pole is configured to be coupled to the first pull-up node PU1.
  • the gate of the first transistor T1 is configured to be connected to the first random pulse signal terminal OE1 to receive the first random pulse signal, and the first pole is configured as a display output terminal (ie, the first input terminal).
  • INPUT1 is connected to receive the display output signal
  • the second pole is configured to be connected to the first pull-up node PU1.
  • the first pull-up node reset sub-circuit 120 can be implemented as a third transistor T3.
  • the gate of the third transistor T3 is configured to be coupled to the first reset terminal RST1 to receive the first reset signal, the first pole is configured to be coupled to the first pull-up node PU1, and the second pole is configured to be coupled to the first voltage terminal VGL1.
  • the third transistor T3 is turned on due to the first reset signal, the first pull-up node PU1 and the first voltage terminal VGL1 are electrically connected, so that the first pull-up node PU1 can be reset to be lowered from the high level to Low level.
  • the detection output sub-circuit 130 can be implemented as a fourth transistor T4 and a first storage capacitor C1.
  • the gate of the fourth transistor T4 is configured to be connected to the first pull-up node PU1, that is, controlled by the level of the first pull-up node PU1, that is, when the first pull-up node PU1 is at a high level, the fourth transistor T4 is turned on.
  • the first pull-up node PU1 is at a low level
  • the fourth transistor T4 is turned off, and the first electrode of the fourth transistor T4 is configured to be connected to the first clock signal terminal CLK1 to receive the first clock signal, and the second pole is configured to detect the output.
  • the terminal OUT1 is connected to output a detection output signal; the first pole of the first storage capacitor C1 is connected to the first pull-up node PU1, and the second pole is connected to the detection output terminal OUT1.
  • the fourth transistor T4 When the fourth transistor T4 is turned on, the level of the first pull-up node PU1 can be further pulled up due to the bootstrap action of the first storage capacitor C1.
  • the first pull-up node noise reduction sub-circuit 140 can be implemented as a fifth transistor T5.
  • the gate of the fifth transistor T5 is configured to be connected to the first pull-down node PD1, the first pole is configured to be connected to the first pull-up node PU1, and the second pole is configured to be connected to the first voltage terminal VGL1.
  • the fifth transistor T5 is turned on when the first pull-down node PD1 is at a high potential, and connects the first pull-up node PU1 and the first voltage terminal VGL1, so that the first pull-up node PU1 can be pulled down to achieve noise reduction.
  • the detection output noise reduction sub-circuit 150 can be implemented as a sixth transistor T6.
  • the gate of the sixth transistor T6 is configured to be connected to the first pull-down node PD1, the first pole is configured to be connected to the detection output terminal OUT1, and the second pole is configured to be connected to the first voltage terminal VGL1.
  • the sixth transistor T6 is turned on when the first pull-down node PD1 is at a high potential, and connects the detection output terminal OUT1 and the first voltage terminal VGL1, so that the detection output terminal OUT1 can be pulled down to achieve noise reduction.
  • the first pull-down sub-circuit 160 can be implemented as a seventh transistor T7 and an eighth transistor T8.
  • the gate of the seventh transistor T7 is connected to the first electrode, and is configured to be connected to the second voltage terminal VGH1 to receive the second voltage signal
  • the second pole is configured to be connected to the first pull-down node PD1
  • the gate of the eighth transistor T8 The pole is connected to the first pull-up node PU1, the first pole is connected to the first pull-down node PD1, and the second pole is configured to be connected to the first voltage terminal VGL1 to receive the first voltage signal.
  • the eighth transistor T8 When the first pull-up node PU1 is at a high level, the eighth transistor T8 is turned on, electrically connecting the first pull-down node PD1 with the first voltage terminal VGL1; by setting the on-resistances of the seventh transistor T7 and the eighth transistor T8, Thereby, when the eighth transistor T8 is turned on, the level of the first pull-down node PD1 can be pulled low.
  • the first pull-down sub-circuit 160 may further include a ninth transistor T9 and a tenth transistor T10.
  • the gate of the ninth transistor T9 is connected to the first electrode, and is configured to be connected to the third voltage terminal VGH2 to receive the third voltage signal
  • the second pole is connected to the first pull-down node PD1
  • the gate of the tenth transistor T10 is
  • the first pull-up node PU1 is connected
  • the first pole is connected to the first pull-down node PD1
  • the second pole is configured to be connected to the first voltage terminal VGL1 to receive the first voltage signal.
  • the tenth transistor T10 When the first pull-up node PU1 is at a high level, the tenth transistor T10 is turned on, electrically connecting the first pull-down node PD1 with the first voltage terminal VGL1; and by setting the on-resistance of the ninth transistor T9 and the tenth transistor T10, thereby When the tenth transistor T10 is turned on, the level of the first pull-down node PD1 can be pulled low.
  • the ninth transistor T9 and the tenth transistor T10 are introduced, and the second voltage signal and the third voltage signal are alternated to a high level and a low level, so that the seventh transistor T7 and the eighth transistor T8 and the ninth
  • the transistor T9 and the tenth transistor T10 can operate alternately, so that the stress of each transistor in the first pull-down sub-circuit can be reduced, thereby extending the service life of these transistors.
  • the first pull-down sub-circuit can also be implemented as an inverter, that is, when the first pull-up node is at a high level, the first pull-down node is at a low level, and vice versa.
  • the detection sub-shift register 100 further includes a second detection input sub-circuit 170 and a detection input terminal INPUT2. And a second reset terminal RST2.
  • the second detection input sub-circuit 170 is configured to be coupled to the detection input INPUT2 to receive the detection input signal and to charge the first pull-up node PU1 in response to the detection input signal.
  • the second detection input sub-circuit 170 may be connected to the detection input terminal INPUT2 and the first pull-up node PU1, and configured to enable the first pull-up node PU1 and the detection input terminal INPUT2 under the control of the signal input by the detection input terminal INPUT2.
  • the electrical connection or the additionally provided high voltage terminal is electrically connected, so that the high level signal input from the detection input terminal INPUT2 or the high level signal outputted from the high voltage terminal can be charged to the first pull-up node PU1, so that the first upper node
  • the voltage of the pull node PU1 is increased to control the detection output sub-circuit 130 to be turned on.
  • the detection input signal may be a detection output signal of the upper stage detection sub shift register 100.
  • the second detection input sub-circuit 170 is used to receive a circuit of the output signal of the previous stage detection sub-shift register 100 in progressive scanning.
  • the second detection input sub-circuit 170 can be implemented as the eleventh transistor T11.
  • the gate of the eleventh transistor T11 is connected to the first pole, and is configured to be connected to the detection input terminal INPUT2 to receive the detection input signal, and the second pole is connected to the first pull-up node PU1.
  • the gate of the eleventh transistor T11 is configured to be connected to the detection input terminal INPUT2 to receive the detection input signal, and the first pole is configured to be connected to the third clock signal terminal CLK3 to receive the third clock signal.
  • the second pole is connected to the first pull-up node PU1.
  • the turn-on signal (or the high-level signal) received by the detecting input terminal INPUT2 is turned on by the eleventh transistor T11, the high-level signal received by the turn-on signal or the third clock signal terminal CLK3 is used.
  • a pull-up node PU1 is charged to bring it to a high level.
  • the pull-up node reset circuit 120 in the detection sub-shift register 100 further includes a twelfth transistor T12.
  • the gate of the twelfth transistor T12 is connected to the second reset terminal RST2 to receive a second reset signal
  • the first pole is connected to the first pull-up node PU1
  • the second pole is connected to the first voltage terminal VGL1 to receive the first voltage signal.
  • the first pull-up node PU1 and the first voltage terminal VGL1 are electrically connected. Therefore, the first pull-up node PU1 can be reset to drop from a high level to a low level.
  • the detection sub-shift register 100 of this example may have a function of progressive detection in addition to the function of random detection. For example, when the first sub-pulse signal terminal OE1 of the sub-shift register 100 has no signal input, the detector sub-shift register 100 of this example can be used to continue to control the progressive voltage and mobility of the driving transistor in the pixel circuit. make up.
  • the first reset signal may turn off the function of the progressive scan of the detection sub-shift register 100, and the detection sub-shift register 100 may The output of the output signal is detected for the row based on the number of rows currently displayed by the sub-shift register 200 and the active level of the first random pulse signal.
  • the first reset signal may be implemented to reset the first pull-up node of each level of the detection sub-shift register 100, thereby suppressing the output of the sub-detection sub-shift register 100 of the remaining stages except the current line, thereby implementing the off detection sub-shift
  • the progressive scan function of the bit register 100 eliminates the scan lines generated by progressive scanning and solves the problem of uneven brightness.
  • the detection sub shift register 100 in the present example, and it is to be noted that the detection sub shift register 100 is not limited thereto, and may be other structures in the above examples.
  • the first detection input sub-circuit 110 of the detection sub-shift register 100 further includes a random The pulse signal control sub-circuit (not shown).
  • the random pulse signal control sub-circuit is configured to be coupled to the first input terminal INPUT1 (display output terminal), the first random pulse signal terminal OE1 and the second random pulse signal terminal OE2 to receive the display output signal and the first random pulse signal. And the second random pulse signal, and the first random pulse signal and the second random pulse signal are simultaneously turned on in response to the display output signal, the first random pulse signal, and the second random pulse signal.
  • the random pulse signal control sub-circuit can display the number of lines currently scanned by the sub-shift register 200 and the first random pulse signal and the second random pulse signal. The effective level of the line is used to detect the output of the output signal.
  • an example of the random pulse signal control sub-circuit can be implemented as a fifty-first transistor T51, a fifty-second transistor T52, a fifty-third transistor T53, a fifty-fourth transistor T54, and a fifth.
  • the storage capacitor C5 and the sixth storage capacitor C6 are examples of the random pulse signal control sub-circuit.
  • the gate of the first transistor T1 is connected to the first output terminal H1 of the random pulse signal control sub-circuit, and the first pole is connected to the second clock signal terminal CLK2, and the second pole is connected.
  • the gate of the second transistor is connected to the second output terminal H2 of the random pulse signal control sub-circuit, and the second pole is connected to the first pull-up node PU1; or as shown in FIG.
  • the gate of the first transistor T1 is connected to the second output terminal H2 of the random pulse signal control sub-circuit, the first pole is connected to the second clock signal terminal CLK2, and the second pole is connected to the first pole of the second transistor T2;
  • the gate of the two transistors is connected to the first output terminal H1 of the random pulse signal control sub-circuit, and the second pole is connected to the first pull-up node PU1.
  • the first detection input sub-circuit 110 may further include only the second transistor T2. For example, as shown in FIG.
  • the gate of the second transistor T2 is connected to the first output terminal H1 of the random pulse signal control sub-circuit, and the first pole is connected to the second output terminal H2 of the random pulse signal control sub-circuit, second The pole is connected to the first pull-up node PU1; or, as shown in FIG. 5H, the gate of the second transistor T2 is connected to the second output terminal H2 of the random pulse signal control sub-circuit, the first pole and the random pulse signal control sub-circuit The first output terminal H1 is connected, and the second pole is connected to the first pull-up node PU1.
  • the gate of the fifty-first transistor T51 is connected to the first random pulse signal terminal OE1, and the first pole is connected to the first input terminal INPUT1 (ie, the display output terminal OUT2).
  • the second pole is coupled to the first output terminal H1 of the random pulse signal control subcircuit.
  • the gate of the fifty-second transistor T52 is connected to the second pulse signal terminal OE2, the first pole is connected to the first input terminal INPUT1 (ie, the display output terminal OUT2), and the second pole and the second pulse of the random pulse signal control sub-circuit are connected. Terminal H2 is connected.
  • the gate of the fifty-third transistor T53 is connected to the first clock signal terminal CLK1, the first pole is connected to the first output terminal H1 of the random pulse signal control sub-circuit, and the second pole is connected to the first voltage terminal VGL1.
  • the gate of the fifty-fourth transistor T54 is connected to the first clock signal terminal CLK1, the first pole is connected to the second output terminal H2 of the random pulse signal control sub-circuit, and the second pole is connected to the first voltage terminal VGL1.
  • the first pole of the fifth storage capacitor C5 is connected to the first output terminal H1 of the random pulse signal control sub-circuit, and the second pole is connected to the first voltage terminal VGL1.
  • the first pole of the sixth storage capacitor C6 is connected to the second output terminal H2 of the random pulse signal control sub-circuit, and the second pole is connected to the first voltage terminal VGL1.
  • the detection sub-shift register 100 further includes a leak-proof electronic circuit 180 on the basis of the example illustrated in FIG. 5A.
  • the leak-proof electronic circuit 180 is configured to maintain the high potential of the first pull-up node PU1 under the control of the level of the first pull-up node PU1.
  • the leakage prevention electronic circuit 180 and the fourth voltage terminal VA, the first pull-up node PU1, the first pull-up node reset sub-circuit 120, the first pull-up node noise reduction sub-circuit 150, and the second detection input sub-circuit 170 Connected configured to be under the control of the high level of the first pull-up node PU1, so that the source and the drain of the respective transistors connected to the first pull-up node PU1 are simultaneously at a high level, thereby avoiding the first pull-up
  • the level of the node PU1 is lowered due to leakage to affect the display quality.
  • the leakage prevention electronic circuit 180 can be implemented as the thirteenth transistor T13.
  • the gate of the thirteenth transistor T13 is connected to the first pull-up node PU1, the first pole and the fourth voltage terminal VA are connected to receive the fourth voltage signal, and the second pole is connected to the feedback node OFF, so that the thirteenth transistor T13
  • the feedback node OFF and the fourth voltage terminal VA are connected, so that the feedback node OFF can also be raised to a high level.
  • the first pull-up node reset sub-circuit 120, the first pull-up node noise reduction sub-circuit 150, and the second detection input sub-circuit 170 may be implemented as a structure including two transistors, respectively.
  • the second detection input sub-circuit 170 includes an eleventh transistor T11 and a fourteenth transistor T14.
  • the gate of the eleventh transistor T11 is configured to be connected to the detection input terminal INPUT2 to receive the detection input signal
  • the first pole is configured to be connected to the third clock signal terminal CLK3 to receive the third clock signal
  • the first pole of T14 is connected;
  • the gate of the fourteenth transistor T14 is connected to the gate of the eleventh transistor T11, and is configured to be connected to the feedback node OFF, and the second pole is connected to the first pull-up node PU1.
  • the first pull-up node reset sub-circuit 120 includes a third transistor T3, a twelfth transistor T12, a fifteenth transistor T15, and a sixteenth transistor T16.
  • a gate of the third transistor T3 is configured to be coupled to the first reset terminal to receive the first reset signal
  • a first pole of the third transistor is coupled to a second pole of the fifteenth transistor T15, and configured to Connected to the feedback node OFF, the second pole is configured to be connected to the first voltage terminal VGL1
  • the gate of the twelfth transistor T12 and the second reset terminal RST2 are connected to receive the second reset signal, the first pole and the sixteenth transistor T16
  • the second pole is connected and configured to be connected to the feedback node OFF, the second pole is connected to the first voltage terminal VGL1 to receive the first voltage signal
  • the gate of the fifteenth transistor T15 is connected to the gate of the third transistor T3,
  • the first pole is connected to the first pull-up node PU1; the gate of
  • the first pull-up node noise reduction sub-circuit includes a fifth transistor T5 and a seventeenth transistor T17.
  • the gate of the fifth transistor T5 is configured to be connected to the first pull-down node PD1
  • the first pole is configured to be connected to the second pole of the seventeenth transistor, and is configured to be connected to the feedback node OFF, and the second pole is configured to be A voltage terminal VGL1 is connected
  • a gate of the seventeenth transistor T17 is connected to a gate of the fifth transistor T5, and the first pole is connected to the first pull-up node PU1.
  • the first poles of the fifteenth transistor T15 and the sixteenth transistor T16 are both connected to the first pull-up node PU1, and the second poles are both connected to the feedback node OFF, so when the first pull-up node PU1 is high level
  • the thirteenth transistor is turned on, and the feedback node OFF is connected to the fourth voltage terminal VA, so that the feedback node OFF can also be raised to a high level, thereby making the first pole of the fifteenth transistor T15 and the sixteenth transistor T16 Simultaneously maintaining a high level with the second pole, thereby avoiding a decrease in the level of the first pull-up node PU1 due to leakage of a transistor connected to the first pull-up node PU1.
  • the principle of the fourteenth transistor T14 and the seventeenth transistor T17 are the same and will not be described herein.
  • FIG. 7A is a schematic diagram of a display sub-shift register of the shift register unit shown in FIG. 2.
  • the display sub-shift register 200 includes a display input sub-circuit 210, a second pull-up node reset sub-circuit 220, and a display output sub-circuit 230.
  • the display input sub-circuit 210 is configured to charge the second pull-up node PU2 in response to the display input signal.
  • the display input sub-circuit 210 can be connected to the display input terminal INPUT3 and the second pull-up node PU2 of the display sub-shift register 200, and configured to enable the second pull-up node under the control of the signal input from the display input terminal INPUT3.
  • the PU2 and the display input terminal INPUT3 are electrically connected or additionally provided with a high voltage terminal, so that the high level signal input from the display input terminal INPUT3 or the high level signal outputted from the high voltage level terminal can be made to the second pull-up node PU2. Charging is performed such that the voltage of the second pull-up node PU2 is increased to control the display output sub-circuit 230 to be turned on.
  • the second pull-up node reset sub-circuit 220 is configured to reset the second pull-up node PU2 in response to the third reset signal received by the third reset terminal RST3, so that the voltage of the second pull-up node PU2 is reduced (pulled low) So that the display output sub-circuit 230 is no longer turned on.
  • the second pull-up node reset sub-circuit 220 can be configured to be connected to the third reset terminal RST3, so that the second pull-up node PU2 and the low can be made under the control of the third reset signal input by the third reset terminal RST3.
  • the level signal or the low voltage terminal is electrically connected, and the low voltage terminal is, for example, the first voltage terminal VGL1, so that the second pull-up node PU2 can be pulled down and reset.
  • the display output sub-circuit 230 is configured to output the fourth clock signal CLK4 to the display output terminal OUT2 under the control of the level of the second pull-up node PU2 as an output signal of the display sub-shift register 200 to drive, for example,
  • the display line is connected to the output terminal OUT2.
  • the display output sub-circuit 230 can be configured to be turned on under the control of the level of the second pull-up node PU2 to electrically connect the fourth clock signal terminal CLK4 and the display output terminal OUT2, so that the fourth clock signal terminal can be The fourth clock signal of the CLK4 input is output to the display output terminal OUT2.
  • the display sub-shift register 200 further includes a second pull-up node noise reduction sub-circuit 240, The second output noise reduction sub-circuit 250 and the second pull-down sub-circuit 260.
  • the second pull-up node noise reduction sub-circuit 240 is configured to perform noise reduction on the second pull-up node PU2 under the control of the level of the second pull-down node PD2.
  • the second pull-up node noise reduction circuit 240 can be configured to be connected to the first voltage terminal VGL1 to enable the second pull-up node PU2 and the first voltage terminal VGL1 under the control of the level of the second pull-down node PD2. Electrically connected to pull down noise reduction on the second pull-up node PU2.
  • the display output noise reduction sub-circuit 250 is configured to perform noise reduction on the display output terminal OUT2 under the control of the level of the second pull-down node PD2.
  • the second output noise reduction sub-circuit 250 can be configured to electrically connect the display output terminal OUT2 and the first voltage terminal VGL1 under the control of the level of the second pull-down node PD2, thereby pulling down the display output terminal OUT2. noise.
  • the second pull-down sub-circuit 260 is configured to control the level of the second pull-down node PD2 under the control of the level of the second pull-up node PU2.
  • the second pull-down sub-circuit 260 may connect the first voltage terminal VGL1, the second voltage terminal VGH1, the second pull-up node PU2, and the second pull-down node PD2 to be under the control of the level of the second pull-up node PU2.
  • the second pull-down node PD2 and the first voltage terminal VGL1 are electrically connected to perform pull-down control on the level of the second pull-down node PD2, so that when the second pull-up node PU2 is at a high potential, the second pull-down node PD2 is at a low level Potential.
  • the first pull-down sub-circuit 160 can electrically connect the second pull-down node PD2 and the second voltage terminal VGH1 under the control of the level of the second voltage terminal VGH1, so that the second pull-down node PD2 is High potential.
  • each transistor is an N-type transistor as an example, but it does not constitute a limitation on the embodiment of the present disclosure.
  • the display input sub-circuit 210 can be implemented as a twenty-first transistor T21.
  • the gate of the twenty-first transistor T21 is connected to the first pole, and is configured to be connected to the display input terminal INPUT3 to receive the input signal, and the second pole is configured to be connected to the second pull-up node PU2 to the second pull-up node PU2 Charge it.
  • the second pull-up node reset sub-circuit 220 can be implemented as the twenty-second transistor T22.
  • the gate of the twenty-second transistor T22 is configured to be connected to the third reset terminal RST3 to receive a reset signal
  • the first pole is configured to be connected to the second pull-up node PU2 to reset the second pull-up node PU2, the second pole It is configured to be connected to the first voltage terminal VGL1 to receive the first voltage.
  • the display output sub-circuit 230 can be implemented to include a twenty-third transistor T23 and a second storage capacitor C2.
  • the gate of the twenty-third transistor T23 is configured to be connected to the second pull-up node PU2, that is, controlled by the level of the second pull-up node PU2, that is, the second thirteenth transistor when the second pull-up node PU2 is at a high level. T23 is turned on. When the second pull-up node PU2 is low, the twenty-third transistor T23 is turned off, the first pole is configured to be connected with the fourth clock signal terminal CLK4 to receive the clock signal, and the second pole is configured to be the display output.
  • the first pole of the second storage capacitor C2 is configured to be connected to the gate of the twenty-third transistor T23, and the second pole is connected to the second pole of the twenty-third transistor T23.
  • the twenty-third transistor T23 is turned on, the level of the second pull-up node PU2 can be further pulled up due to the bootstrap action of the second storage capacitor C2.
  • the second pull-up node noise reduction sub-circuit 240 can be implemented as a twenty-fourth transistor T24.
  • the gate of the twenty-fourth transistor T24 is configured to be connected to the second pull-down node PD2, the first pole is configured to be connected to the second pull-up node PU2 to perform noise reduction on the second pull-up node PU2, and the second pole is configured as The first voltage terminal VGL1 is connected to receive the first voltage.
  • the second output noise reduction sub-circuit 250 can be implemented as a twenty-fifth transistor T25.
  • the gate of the twenty-fifth transistor T25 is configured to be connected to the second pull-down node PD2, the first pole is configured to be coupled to the display output terminal OUT2, and the second pole is configured to be coupled to the first voltage terminal VG1L to receive the first voltage.
  • the second pull-down sub-circuit 260 can be implemented as a twenty-sixth transistor T26 and a twenty-seventh transistor T27.
  • the gate of the twenty-sixth transistor T26 is connected to the first pole, and is configured to be connected to the second voltage terminal VGH1 to receive the second voltage signal, the second pole is configured to be connected to the second pull-down node PD2;
  • the gate of T27 is connected to the second pull-up node PU2, the first pole is connected to the second pull-down node PD2, and the second pole is configured to be connected with the first voltage terminal VGL1 to receive the first voltage signal.
  • the twenty-seventh transistor T27 When the second pull-up node PU2 is at a high level, the twenty-seventh transistor T27 is turned on, and the second pull-down node PD2 is electrically connected to the first voltage terminal VGL1; by setting the twenty-sixth transistor T26 and the twenty-seventh transistor T27 The on-resistance is such that when the twenty-seventh transistor T27 is turned on, the level of the second pull-down node PD2 can be pulled low.
  • the second pull-down sub-circuit 260 may further include a twenty-eighth transistor T28 and a second nine-th transistor T29.
  • the gate of the twenty-eighth transistor T28 is connected to the first pole, and is configured to be connected to the third voltage terminal VGH2 to receive the third voltage signal
  • the second pole is connected to the second pull-down node PD2
  • the second-ninth transistor T29 The gate is connected to the second pull-up node PU2
  • the first pole is connected to the second pull-down node PD2
  • the second pole is configured to be connected to the first voltage terminal VGL1 to receive the first voltage signal.
  • the twenty-ninth transistor T29 When the second pull-up node PU2 is at a high level, the twenty-ninth transistor T29 is turned on, and the second pull-down node PD2 is electrically connected to the first voltage terminal VGL1; by setting the twenty-eighth transistor T28 and the twenty-ninth transistor T29 The on-resistance is such that when the twenty-ninth transistor T29 is turned on, the level of the second pull-down node PD2 can be pulled low.
  • the twenty-eighth transistor T28 and the twenty-ninth transistor T29 are introduced, and the second voltage signal and the third voltage signal are alternated to a high level and a low level, so that the twenty-sixth transistor T26 and The twenty-seventh transistor T27 and the twenty-eighth transistor T28 and the twenty-ninth transistor T29 can alternately operate, so that the stress of each transistor in the second pull-down sub-circuit can be reduced, thereby extending the service life of the transistors.
  • the second pull-down sub-circuit can be implemented as an inverter, that is, when the second pull-up node is high, the second pull-down node is low, and vice versa.
  • FIG. 8A is a schematic diagram of another shift register unit according to an embodiment of the present disclosure. As shown in FIG. 8A, on the basis of the embodiment shown in FIG. 2, the shift register unit 10 further includes an output control circuit 300.
  • the output control circuit 300 and the first pull-up node PU1 and the first pull-down node PD1 of the sub-shift register 100 and the second pull-up node PU2 and the second of the display sub-shift register 200 are shown.
  • the pull-down node PD2 is electrically connected, and is configured to pull down the other when one of the first pull-up node PU1 and the second pull-up node PU2 is at an active level (high level). For example, when the first pull-up node PU1 is at a high level, the level of the second pull-up node PU2 is pulled down, or vice versa, thereby ensuring that the output signal of the sub-shift register 100 is not displayed during the detection output.
  • the effect of the output of the sub-shift register 200, during the display output, indicates that the output signal of the sub-shift register 200 is not affected by the detection sub-shift register 100.
  • the output control circuit 300 can directly connect the output of the detection sub-shift register 100 and the output of the display sub-shift register 200 to output a composite waveform.
  • the output control circuit 301 can also be controlled by the detection output signal of the detection output terminal OUT1 of the detection sub-shift register 100 and the second pull-up node PU2 and the second pull-down node PD2.
  • Figure 9A is a schematic diagram of an output control circuit shown in Figure 8A.
  • the output control circuit 300 includes a detection output control sub-circuit 310 and a display output control sub-circuit 320.
  • the detection output control sub-circuit 310 is configured to control the levels of the second pull-up node PU2 and the second pull-down node PD2 under the control of the level of the first pull-up node PU1.
  • the detection output control sub-circuit 310 is connected to the second pull-up node PU2, the second pull-down node PD2, and the first voltage terminal VGL1, and configured to be under the control of the level of the first pull-up node PU1, so that the second The pull node PU2 and the second pull-down node PD2 are connected to the first voltage terminal VGL1, so that the second pull-up node PU2 and the second pull-down node PD2 can be pulled down to avoid displaying the sub-shift during the output of the detection sub-shift register 100.
  • the register 200 performs output.
  • the display output control sub-circuit 320 is configured to control the levels of the first pull-up node PU1 and the first pull-down node PD1 under the control of the level of the second pull-up node PU2.
  • the display output control sub-circuit 310 is connected to the first pull-up node PU1, the first pull-down node PD1, and the first voltage terminal VGL1, and configured to be under the control of the level of the second pull-up node PU2, so that the first The pull-up node PU1 and the first pull-down node PD1 are connected to the first voltage terminal VGL1, so that the first pull-up node PU1 and the first pull-down node PD1 can be pulled down to avoid detection during the output of the display sub-shift register 100.
  • the sub shift register 100 performs output.
  • each transistor is an N-type transistor as an example, but it does not constitute a limitation on the embodiment of the present disclosure.
  • the detection output control sub-circuit 310 can be implemented as a thirty-first transistor T31 and a thirty-second transistor T32.
  • the gate of the thirty-first transistor T31 is configured to be connected to the first pull-up node PU1, the first pole is configured to be connected to the second pull-down node PD2, and the second pole is configured to be connected to the first voltage terminal VGL1;
  • the gate of the transistor T32 is configured to be connected to the first pull-up node PU1, the first pole is configured to be connected to the first voltage terminal VGL1, and the second pole is configured to be connected to the second pull-up node PU2.
  • the display output control sub-circuit 320 can be implemented as a thirty-third transistor T33 and a thirty-fourth transistor T34.
  • the gate of the thirty-third transistor T33 is configured to be connected to the second pull-up node PU2, the first pole is configured to be connected to the first pull-down node PD1, and the second pole is configured to be connected to the first voltage terminal VGL1;
  • the gate of the four transistor T34 is configured to be connected to the second pull-up node PU2, the first pole is configured to be coupled to the first voltage terminal VGL1, and the second pole is configured to be coupled to the first pull-up node PU1.
  • the output control circuit 300 can directly connect the output of the detection sub-shift register 100 and the output of the display sub-shift register 200 to output a composite waveform, together with a gate line connected to the shift register 10, for example. At the same time, the output control circuit 300 causes only the display output signal to be output during display, during which only the detection output signal is output, and it is ensured that the other sub-shift register does not interfere when one of the sub-shift registers is output.
  • the shift register unit 10 shown in FIG. 8A can be embodied in one example as the circuit configuration shown in FIG. 9C.
  • the sub-shift register described in any embodiment of the present disclosure may be used in the detection sub-shift register 100 and the display sub-shift register 200, and details are not described herein again.
  • the display sub-shift register 200 can adopt the circuit structure shown in FIG. 7C
  • the detection sub-shift register 100 can adopt the circuit structure shown in FIG. 5B
  • the output control circuit 300 can adopt the circuit shown in FIG.
  • the structure is specifically implemented in FIG.
  • the display output terminal OUT2 of the display sub-shift register 200 is connected to the first input terminal INPUT1 and the detection output terminal OUT1 of the detection sub-shift register 100 to output a composite under the control of the output control circuit 300.
  • the waveform is controlled to control the gates of the switching transistor T0 and the sensing transistor S0 in the pixel circuit connected to the gate scan line SCAN as shown in FIG. 1D.
  • the shift register unit 10 shown in FIG. 8B can also be embodied in one example as the circuit structure shown in FIG. 9D.
  • the sub-shift register described in any embodiment of the present disclosure may be used in the detection sub-shift register 100 and the display sub-shift register 200, and details are not described herein again.
  • the display sub-shift register 200 can adopt the circuit configuration shown in FIG. 7C
  • the detection sub-shift register 100 can adopt the circuit configuration shown in FIG. 5B.
  • the output control circuit 300 is implemented by the thirty-fifth transistor T35, the thirty-sixth transistor T36, and the thirty-seventh transistor T37.
  • the gate of the thirty-fifth transistor T35 is configured to be connected to the detection output terminal OUT1 to receive the detection output signal, the first pole is configured to be connected to the second pull-down node PD2, and the second pole is configured to be the first The voltage terminal VGL1 is connected; the gate of the thirty-sixth transistor T36 is configured to be connected to the detection output terminal OUT1 to receive the detection output signal, the first pole is configured to be connected to the second pull-up node PU2, and the second pole is configured to be the first The voltage terminal VGL1 is connected; the gate of the thirty-seventh transistor T37 is configured to be connected to the detection output terminal OUT1 to receive the detection output signal, and the first pole is configured to be connected to the fifth clock signal terminal to receive the fifth clock signal, the second pole It is configured to be connected to the output composite output terminal OUT4 and the display output terminal OUT2.
  • the working principle of the shift register 10 includes: when the detection output terminal OUT1 outputs a high level signal, the thirty-fifth transistor T35 and the thirty-sixth transistor T36 are turned on, and the second pull-up node of the sub-shift register 200 is displayed.
  • the PU2 and the second pull-down node PD2 are connected to the first voltage terminal VGL1 and are pulled down to a low level, so that the display output terminal OUT2_N is pulled low to a low level, thereby indicating that the sub-shift register 200 does not affect the detection sub-shift register 100.
  • the thirty-seventh transistor T37 is also turned on, thereby outputting the high level of the fifth clock signal to the output composite output terminal OUT4.
  • the first pull-down node PD1 of the detection sub-shift register is at a high potential, so the output of the detection output terminal OUT1 is low, so that the thirty-seventh transistor T37 is turned off, and the composite output terminal OUT4 is output. Only the display output signal output from the display output terminal OUT2 is output.
  • FIG. 10 is a schematic diagram of another shift register unit according to an embodiment of the present disclosure. As shown in FIG. 10, the shift register unit 10 further includes a logic OR circuit 400 on the basis of the embodiment shown in FIG.
  • the logic OR circuit 400 is connected to the display output terminal OUT2 of the display sub-shift register 200 and the detection output terminal OUT1 of the detection sub-shift register 100, and is configured to perform a display output signal and a detection output signal or Operate to get a composite output signal.
  • the function of the logic OR circuit 400 and the output control circuit 300 is similar, and the output signal of the detection sub-shift register 100 and the output signal of the display sub-shift register 200 may be combined to drive, for example, the shift register 10 together. Connected grid lines.
  • Figure 11A is a schematic illustration of one of the logic or circuits shown in Figure 10.
  • the logic OR circuit 400 includes a first logic or input sub-circuit 410, a second logic or input sub-circuit 420, a first output control sub-circuit 430, a second output control sub-circuit 440, and a first node drop.
  • the noise sub-circuit 450, the second node noise reduction sub-circuit 460, the output noise reduction control sub-circuit 470, and the output noise reduction sub-circuit 480 The noise sub-circuit 450, the second node noise reduction sub-circuit 460, the output noise reduction control sub-circuit 470, and the output noise reduction sub-circuit 480.
  • the first logic or input sub-circuit 410 is configured to charge the first node N1 in response to detecting the output signal.
  • the first logic or input sub-circuit 410 can be connected to the detection output terminal OUT1 and the first node N1, and configured to enable the first node N1 and the detection output under the control of the detection output signal outputted by the detection output terminal OUT1. Electrically connected, the high level signal input to the detection output terminal OUT1 can be charged to the first node N1 such that the voltage of the first node N1 is increased to control the first output control sub-circuit 430 to be turned on.
  • the second logic or input sub-circuit 420 is configured to charge the second node N2 in response to the display output signal.
  • the second logic or input sub-circuit 420 can be connected to the display output terminal OUT2 and the second node N2, and configured to enable the second node N2 and the display output terminal OUT2 under the control of the display output signal outputted by the display output terminal OUT2. Electrically connected, the high level signal input to the display output terminal OUT2 can be charged to the second node N2 such that the voltage of the second node N2 is increased to control the second output control sub-circuit 440 to be turned on.
  • the first output control sub-circuit 430 is configured to output a detection output signal under the control of the level of the first node N1.
  • the first output control sub-circuit 430 can be configured to be turned on under the control of the level of the first node N1 to electrically connect the detection output terminal OUT1 and the logic or output terminal OUT3, so that the output of the detection output terminal OUT1 can be output.
  • the detection output signal is output to the logic or output terminal OUT3.
  • the second output control sub-circuit 440 is configured to output a display output signal under the control of the level of the second node N2.
  • the second output control sub-circuit 440 can be configured to be turned on under the control of the level of the second node N2 to electrically connect the display output terminal OUT2 and the logic or output terminal OUT3 so that the output of the display output terminal OUT2 can be output.
  • the display output signal is output to the logic or output terminal OUT3.
  • the first node noise reduction circuit 450 is configured to perform noise reduction on the first node N1 under the control of the level at which the output signal is displayed.
  • the first node noise reduction circuit 450 can be configured to be connected to the fifth voltage terminal VGL2 to electrically connect the first node N1 and the fifth voltage terminal VGL2 under the control of the level of the display output signal, thereby A node N1 performs pull-down noise reduction.
  • the second node noise reduction circuit 460 is configured to perform noise reduction on the second node N2 under the control of detecting the level of the output signal.
  • the second node noise reduction circuit 460 can be configured to be connected to the fifth voltage terminal VGL2 to electrically connect the second node N2 and the fifth voltage terminal VGL2 under the control of detecting the level of the output signal, thereby The two nodes N2 perform pulldown and noise reduction.
  • the output noise reduction control sub-circuit 470 is configured to control the level of the third node N3 under the control of the level of the display output signal and the detection output signal.
  • the output noise reduction control sub-circuit 470 is configured to be connected to the first voltage terminal VGL1, the second voltage terminal VGH1, the third voltage terminal VGH2, the detection output terminal OUT1, the display output terminal OUT2, and the third node N3, and is configured to be Under the control of the high level of one of the output signal and the detection output signal, the third node N3 is connected to the first voltage terminal VGL1 to be at a low potential, or at the same time as displaying the output signal and detecting the output signal Under the control of the low level, the third node N3 is connected to one of the second voltage terminal VGH1 or the third voltage terminal VGH2 so as to be at a high potential.
  • the output noise reduction sub-circuit 480 is configured to denoise the logic or output OUT3 under the control of the level of the third node N3.
  • the output noise reduction sub-circuit 480 is connected to the third node N3, the fifth voltage terminal VGL2, the ground terminal GND, and the logic or output terminal OUT3, and is configured to be under the control of the level of the third node N3 such that the logic or the output terminal OUT3 is connected to the fifth voltage terminal VGL2 to perform pull-down noise reduction on the logic or output terminal OUT3.
  • each transistor is an N-type transistor as an example, but it does not constitute a limitation on the embodiment of the present disclosure.
  • the first logic or input sub-circuit 410 can be implemented as a forty-first transistor T41.
  • the gate of the forty-first transistor T41 is connected to the first pole, and is configured to be connected to the detection output terminal OUT1 to receive the detection output signal, and the second pole is configured to be connected to the first node N1.
  • the first output control sub-circuit 430 can be implemented as a forty-second transistor T42 and a third storage capacitor C3.
  • the gate of the forty-second transistor T42 is connected to the first node N1, the first pole is connected to the detection output terminal OUT1 to receive the detection output signal, and the second pole is connected to the first pole of the third storage capacitor C3; the third storage capacitor The second pole of C3 is connected to the first node N1.
  • the first node noise reduction sub-circuit 450 can be implemented as a forty-third transistor T43.
  • the gate of the forty-third transistor T43 is connected to the display output terminal OUT2 to receive the display output signal
  • the first pole is connected to the first node N1
  • the second pole is connected to the fifth voltage terminal VGL2 to receive the fifth voltage signal.
  • the second logic or input sub-circuit 420 can be implemented as a forty-fourth transistor T44.
  • the gate of the forty-fourth transistor T44 is coupled to the first pole and is configured to be coupled to the display output OUT2 to receive the display output signal, the second pole being configured to be coupled to the second node N2.
  • the second output control sub-circuit 440 can be implemented as a forty-fifth transistor T45 and a fourth storage capacitor C4.
  • the gate of the forty-fifth transistor T45 is connected to the second node N2, the first pole is connected to the display output terminal OUT2 to receive the display output signal, and the second pole is connected to the first pole of the fourth storage capacitor C4; the fourth storage capacitor The second pole of C4 is connected to the second node N2.
  • the second node noise reduction sub-circuit 460 is a forty-sixth transistor T46.
  • the gate of the forty-sixth transistor T46 is connected to the detection output terminal OUT1 to receive the detection output signal
  • the first pole is connected to the second node N2
  • the second pole is connected to the fifth voltage terminal VGL2 to receive the fifth voltage signal.
  • the output noise reduction control sub-circuit 470 can be implemented as a forty-seventh transistor T47, a forty-eighth transistor T48, a forty-ninth transistor T49, and a fiftyth transistor T50.
  • the gate of the forty-seventh transistor T47 is connected to the first pole, and is configured to be connected to the second voltage terminal VGH1, the second pole is connected to the third node N3; the gate of the forty-eighth transistor T48 and the first The pole is connected and configured to be connected to the third voltage terminal VGH2, the second pole is configured to be connected to the third node N3;
  • the gate of the forty-ninth transistor T49 is connected to the detection output terminal OUT1 to receive the detection output signal, the first pole Connected to the third node N3, the second pole is connected to the first voltage terminal VGL1;
  • the gate of the fiftyth transistor T50 is connected to the display output terminal OUT2 to receive the display output signal, the first pole is connected to the third node N3, and the second
  • the output noise reduction sub-circuit 480 can be implemented as a fifty-first transistor T51 and a first resistor R1 and a fifth storage capacitor C5.
  • the gate of the fifty-first transistor T51 and the third node are connected to N3, the first pole is connected to the logic or output terminal OUT3, and the second pole and the fifth voltage terminal VGL2 are connected to receive the fifth voltage signal;
  • the first resistor R1 The first end is connected to the logic or output terminal OUT3, the second end is connected to the first pole of the fifth storage capacitor C5, and the second pole of the fifth storage capacitor C5 is connected to the ground GND.
  • the fifth voltage terminal VGL2 holds, for example, an input DC low level signal, and the DC low level is referred to as a fifth voltage.
  • the following embodiments are the same as those described herein and will not be described again.
  • the transistors used in the embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other switching device having the same characteristics.
  • a thin film transistor is taken as an example for description.
  • the source and drain of the transistor used here may be structurally symmetrical, so that the source and the drain may be structurally indistinguishable.
  • the embodiment of the present disclosure in order to distinguish the two poles of the transistor except the gate, one of the first poles and the other pole are directly described.
  • the transistors in the embodiments of the present disclosure are all described by taking an N-type transistor as an example.
  • the first pole of the transistor is the drain and the second pole is the source.
  • the present disclosure includes but is not limited thereto.
  • one or more transistors in the shift register unit provided by the embodiment of the present disclosure may also adopt a P-type transistor.
  • the first pole of the transistor is the source and the second pole is the drain, and only needs to be selected.
  • the polarities of the respective poles of the transistor of the type may be connected in accordance with the polarities of the respective poles of the respective transistors in the embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a gate drive circuit 20 that includes a plurality of cascaded shift register units 10, as shown in FIG. 12A.
  • the shift register unit 10 can employ any of the shift register units provided in the above embodiments.
  • each shift register unit 10 includes a detection sub-shift register unit 100 and a display sub-shift register unit 200.
  • the first input terminal INPUT1 of each of the detector shift register units 100 and the display output terminal OUT2 of the display sub-shift register unit 200 are connected.
  • the gate driving circuit 20 can be directly integrated on the array substrate of the display device by using the same process as the thin film transistor to realize the progressive scan driving function.
  • the display sub-shift register 200 can employ the circuit configuration of FIG. 7C
  • the detection sub-shift register 100 can employ the circuit configuration of FIG. 4D.
  • the gate driving circuit 20 further includes a first random pulse signal line OEA and a total reset line TRST.
  • the first random pulse signal terminal OE1 of each stage of the detection sub-shift register unit 100 is connected to the first random pulse signal line OEA; the first reset terminal RST1 of each level of the detection sub-shift register unit 100 is connected to the total reset line TRST.
  • the remaining stages display the display of the third reset terminal RST3 of the sub-shift register unit 200 and the next-level display sub-shift register unit 200.
  • the output terminal OUT2 is connected; except for the first stage display sub-shift register unit 200, the remaining stages display the display input terminal INPUT3 of the sub-shift register unit 200 and the display output terminal of the upper-level display sub-shift register unit 200 of the previous stage. OUT2 connection.
  • one shift register unit B is a lower shift register unit of another shift register unit A, and the gate scan signal outputted by the shift register unit B is late in timing.
  • the gate scan signal outputted from the shift register unit A is the upper shift register unit of the other shift register unit A.
  • the gate scan signal output from the shift register unit B is earlier in timing than the gate output from the shift register unit A. Scan the signal.
  • the gate driving circuit 20 further includes a first clock signal line CLKA and a second clock signal line CLKB.
  • the first clock signal line CLKA and the second n-1 (n is an integer greater than 0) stage display the clock signal terminal CLK4 of the sub-shift register unit 200; the second clock signal line CLKB and the second n-level display sub-
  • the clock signal terminal CLK4 of the shift register unit 200 is connected.
  • the embodiment of the present disclosure includes, but is not limited to, the foregoing connection manner.
  • the first clock signal line CLKA and the clock signal terminal CLK4 of the second n-level display sub-shift register unit 200 are connected, and the second clock is connected.
  • the signal line CLKB is connected to the clock signal terminal CLK4 of the 2n-1th stage display sub-shift register unit 200.
  • the gate driving circuit 20 further includes a third clock signal line CLKC, a fourth clock signal line CLKD, and a fifth clock signal line CLKE.
  • the third clock signal line CLKC is connected to the clock signal terminal CLK1 of the 2n-1th stage detection sub shift register unit 100; the clock signal of the fourth clock signal line CLKD and the 2nth stage detection sub shift register unit 100
  • the terminal CLK1 is connected, and the fifth clock signal line CLKE is connected to the second clock signal terminal CLK2 of each stage of the detection sub-shift register 100 to input a second clock signal.
  • OUT1_N-1 and OUT2_N-1 shown in FIG. 12A respectively indicate the output of the N-1th stage (N is an integer greater than 1) of the sub-shift register unit 100 and the display sub-shift register unit 200.
  • the terminals OUT1_N and OUT2_N represent the output terminals of the Nth stage detection sub shift register unit 100 and the display sub shift register unit 200, respectively, and OUT1_N+1 and OUT_N+1 represent the (N+1th stage) detection sub shift register unit 100, respectively.
  • the output of the sub-shift register unit 200 is displayed.
  • the reference numerals in the following embodiments are similar to this and will not be described again.
  • the display input terminal INPUT1 of the first stage display sub-shift register unit may be configured to receive the trigger signal STV
  • the third reset terminal RST3 of the last stage display sub-shift register unit 200 may be configured to receive the reset signal RESET,
  • the trigger signal STV and the reset signal RESET are not shown in FIG. 12A.
  • the gate drive circuit 20 may further include a timing controller 500.
  • the timing controller 500 can be configured to and the first clock signal line CLKA, the second clock signal line CLKB, the third clock signal line CLKC, the fourth clock signal line CLKD, the fifth clock signal line CLKE, and the total reset line.
  • the TRST and the first random pulse signal line OEA are connected to provide a clock signal, a first random pulse signal, and a first reset signal to the display sub-shift register unit 200 and the detection sub-shift register unit 100.
  • the timing controller 500 can also be configured to provide a trigger signal STV and a reset signal RESET.
  • the detector shift register 100 in the gate driving circuit 20 does not have a progressive scan function, and determines the detection sub-shift register 100 only by the first random pulse signal and the detection output signal of the display sub-shift register connected thereto. Detect the output of the output signal.
  • FIG. 12B shows a schematic diagram of another gate drive circuit 20.
  • the difference between the gate drive circuit 20 and the gate drive circuit shown in FIG. 12A is that the detection input terminal INPUT2 and the detection output terminal OUT1 of the respective stages of the sub-shift register 100 are connected differently.
  • the display sub-shift register 200 can employ the circuit configuration of FIG. 7C
  • the detection sub-shift register 100 can employ the circuit configuration of FIG. 5B.
  • the second reset terminal RST2 of the remaining stages of the detection sub-shift register unit 100 is connected to the detection output terminal OUT1 of the next-stage detection sub-shift register unit 100;
  • the detection input terminal INPUT2 of the remaining stages of the detection sub-shift register unit 100 and the detection output terminal OUT1 of the previous stage detection sub-shift register unit 100 are connected to the first stage detection sub-shift register unit 100.
  • the connection manner of the first random pulse signal terminal OE1 and the first reset terminal RST1 is the same as that shown in FIG. 12A, and details are not described herein again.
  • the gate driving circuit 20 in this example can turn off the progressive scan function by the first reset signal when implementing the random detection function, to avoid the problem of generating scan lines and uneven brightness due to progressive scanning;
  • the threshold voltage and mobility of the driving transistor in the pixel circuit can also be compensated by the progressive scan function to improve the display quality.
  • the random detection function and the progressive scan function in this example can be switched as needed. For example, in addition to the control of the total reset line TRST, it can also be implemented by switching circuits or the like, and details are not described herein again.
  • FIG. 12C shows a schematic diagram of another gate drive circuit 20.
  • the difference between the gate driving circuit 20 and the gate driving circuit shown in FIG. 12B is that the connection manners of the fourth clock signal terminal CLK4, the display input terminal INPIT3, and the third reset terminal RST3 of the sub-display sub-shift register 100 are different.
  • the display sub-shift register 200 can adopt the circuit configuration in FIG. 7C
  • the detection sub-shift register 100 can adopt the circuit configuration shown in FIGS. 5D and 5E.
  • the remaining stages display the display of the third reset terminal RST3 of the sub-shift register unit and the lower-level display sub-shift register 200 of one stage.
  • the output terminal OUT2 is connected.
  • the display input terminal INPUT3 of the remaining stage display sub-shift register 200 is connected to the display output terminal OUT2 of the upper display sub-shift register 200 of one stage other than the first stage and the second stage display sub-shift register unit.
  • the connection manner may be that the third reset terminal RST3 of the sub-shift register 200 and the lower level of the two stages are displayed in addition to the last three-level display sub-shift register 200.
  • the display output terminal OUT2 of the display sub shift register 200 is connected.
  • the display input terminal INPUT3 of the remaining stage display sub-shift register 200 is connected to the display output terminal OUT2 of the upper display sub-shift register 200 of one stage other than the first stage and the second stage display sub-shift register unit.
  • the gate drive circuit 20 further includes a clock controller 500.
  • the clock controller 500 includes a first clock signal line CLKA, a second clock signal line CLKB, a sixth clock signal line CLKF, and a seventh clock signal line CLKG.
  • the first clock signal line CLKA is connected to the clock signal terminal CLK4 of the sub-shift register, for example, and the 4n-3 (n is an integer greater than 0) level;
  • the second clock signal line CLKB is, for example, The 4n-2 stage display clock signal terminal CLK4 of the sub shift register 200 is connected;
  • the sixth clock signal line CLK3 is connected, for example, to the fourth clock signal terminal CLK4 of the 4n-1th stage display sub shift register 200;
  • the fourth clock signal line CLK4 is connected, for example, to the fourth clock signal terminal CLK4 of the 4nth stage display sub-shift register 200.
  • the clock controller 500 also includes a second random pulse signal line (not shown).
  • the second random pulse signal line is connected to a second random pulse signal end (not shown) of the detection sub-shift register 100, and the random pulse signal line OEA and the first random pulse signal of the detection sub-shift register 100 are detected.
  • the connection of the other ports of the detection sub-shift register 100 is the same as that of the connection of the other ports of the detection sub-shift register 100, and will not be described herein.
  • the gate driving circuit 20 provided in the embodiment of the present disclosure may further include six, eight, and other clock signal lines, which are not limited by the embodiments of the present disclosure.
  • the gate driving circuit in this example can also ensure that only one of the detection sub-shift registers is ensured in the case where the multi-level display sub-shift register is simultaneously outputted. Output is performed to avoid the problem of scan lines and uneven brightness due to progressive scanning.
  • the operation principle of displaying the sub-shift register portion in the gate driving circuit 20 shown in Fig. 12A will be described with reference to the signal timing chart shown in Fig. 13A.
  • the operation principle of the display sub-shift register 200 shown in FIG. 7C will be described with reference to the signal timing chart shown in FIG. 13A, in the first stage 1 and the second stage shown in FIG. 13A.
  • the display sub-shift register 200 can perform the following operations respectively.
  • the display input terminal INPUT3 of the Nth stage display sub-shift register unit 200 receives the high-level signal provided by the N-1th stage as a display input signal, and thus the display input signal is under the control of the display input signal.
  • the high level charges the second pull-up node PU2_N of the shift register unit 200 such that the potential of the second pull-up node PU2_N is charged to the first high level;
  • the second clock signal line CLKB provides the low level signal, Since the clock signal terminal CLK4 of the Nth stage display sub shift register unit 200 and the second clock signal line CLKB are connected, at this stage, the clock signal terminal CLK4 of the Nth stage display sub shift register unit 200 is input to the low level.
  • the clock signal terminal CLK4 is input low under the control of the second pull-up node PU2_N high level.
  • the level is output to the display output terminal OUT2_N of the Nth stage sub-shift register unit 200, whereby it displays the output signal at a low level.
  • the first clock signal line CLKA provides a low level signal
  • the second clock signal line CLKB provides a high level signal
  • the clock signal terminal CLK4 of the sub-shift register unit 200 is input to input a high level signal
  • the second pull-up node PU2_N of the Nth stage display sub-shift register unit 200 is at a high level
  • the high-level output of the clock signal terminal CLK4 is input under the control of the high level of the second pull-up node PU2_N.
  • the sub-shift register unit 200 output terminal OUT2_N is displayed, whereby it displays the output signal at a high level.
  • the second pull-up node PU2_N is further charged to the second high level due to the bootstrap effect of the capacitor.
  • the Nth stage displays the high level outputted by the output terminal OUT_N of the sub shift register unit 200 as the display input signal of the (N+1)th stage display sub-shift register unit 200, so that the (N+1)th stage display sub-shift register
  • the second pull-up node PU2_N+1 of the cell 200 is pulled up to the first high level, and the output terminal OUT2_N+1 of the N+1th stage display sub-shift register unit 200 outputs the low power provided by the first clock signal line CLKA. level.
  • the first clock signal line CLKA provides a high level signal
  • the clock signal terminal CLK4 of the sub-shift register unit 200 is input with a high level signal
  • the (N+1)th stage display sub-shift register
  • the second pull-up node PU2_N+1 of the cell 200 is at a high level, so under the control of the high level of the second pull-up node PU2_N+1, the high-level output of the clock signal terminal CLK4 is output to the (N+1)th stage.
  • the output terminal OUT_N+1 of the sub-shift register unit 200 is displayed, while the second pull-up node PU2_N+1 is charged to the second high level due to the bootstrap effect of the capacitance.
  • the sub-shift register unit Since the output terminal OUT_N+1 of the (N+1)th stage display sub-shift register unit 200 is connected to the third reset terminal RST3 of the N-th stage display sub-shift register unit 200, the sub-shift register unit is displayed at the (N+1)th stage.
  • the second pull-up node PU2_N of the N-th stage display sub-shift register unit 200 is reset, and is pulled down to the low level, so that the second pull-down node PD2_N It is pulled up to a high level, so that the display output terminal OUT_N of the Nth stage is connected to the first voltage terminal VGL1, so that its display output signal is pulled down to a low level.
  • the level of the potential of the signal timing diagram shown in FIG. 13A is only schematic, and does not represent a true potential value or a relative ratio.
  • the high level signal corresponds to the turn-on signal of the N-type transistor.
  • the low level signal corresponds to the N-type transistor as the off signal, whereby the operation of the pixel circuit using the N-type transistor as the switching transistor in the display panel can be controlled.
  • the operation principle of the detection sub-shift register portion in the gate driving circuit 20 shown in Fig. 12A will be described with reference to the signal timing chart shown in Fig. 13B.
  • the operation principle of the detecting sub-shift register 100 shown in FIG. 4D will be described with reference to the signal timing chart shown in FIG. 13B, in the first stage 1 and the second stage shown in FIG. 13B.
  • the detector shift register can perform the following operations separately.
  • the random pulse terminal inputs a high level signal
  • the display output terminal OUT2_N of the Nth stage display sub shift register also outputs a high level signal
  • the first input terminal INPUT1_N and the first stage of the Nth stage detection sub shift register 100 The display output terminal OUT2_N of the N-level display sub-shift register is connected, so the first input terminal INPUT1_N of the Nth-level detection sub-shift register 100 inputs a high-level signal; at this stage, the second clock signal terminal CLK2 inputs a high level.
  • the first pull-up node PU1_N is connected to the second clock signal terminal CLK2 under the control of the random pulse signal and the high level of the display output signal, so that the first pull-up node PU1_N is charged to the first high Level; at this stage, the fourth clock signal line CLKD provides a low level signal, and since the clock signal terminal CLK1 of the Nth stage detection sub shift register unit 100 is connected to the fourth clock signal line CLKD, at this stage, The clock signal terminal CLK1 of the N-stage detection sub-shift register unit 100 inputs a low-level signal; and since the first pull-up node PU1_N of the N-th generation sub-shift register unit 100 is at the first high level, In the high-level first control PU1_N pull-up node, a low level clock signal input terminal CLK1 is output to the N-stage shift register unit detects the detector output terminal of OUT1_N 100.
  • the fourth clock signal line CLKD provides a high level signal, so at this stage, the clock signal terminal CLK1 of the sub-shift register unit 100 is detected to input a high-level signal; and in turn, the N-th stage detection sub-shift register unit 100
  • the first pull-up node PU1_N is at the first high level, so under the control of the high level of the first pull-up node PU1_N, the high level input of the clock signal terminal CLK1 is output to the N-th stage detection sub-shift register unit.
  • the output terminal OUT1_N is 100, and at the same time, the first pull-up node PU1_N is charged to the second high level due to the bootstrap effect of the capacitor.
  • the first pull-up node PU_N+1 of the (N+1)th stage sub-shift register 100 is charged to the first high level at this stage.
  • the total reset line TRST provides a high level signal. Since the first reset terminal RST1 of each stage of the sub-shift register 100 is connected to the total reset line, the first reset end of each stage of the sub-shift register 100 is detected. RST1 is input to a high level, so the first pull-up node PU1 of each level detecting sub-shift register 100 is pulled down to a low level, so that the first pull-down node PD1 is pulled up to a high level, thereby detecting each level The output terminal OUT1 is pulled down to a low level. Therefore, the function of the progressive scan of the detector shift register shown in FIG. 12B is turned off, avoiding the problem of generating scan lines and uneven brightness due to progressive scanning.
  • the operation of the gate driving circuit 20 shown in FIG. 12B is substantially the same as that of the gate driving circuit 20 shown in FIG. 12A, except that the detection sub-shift in the gate driving circuit 20 shown in FIG. 12B is shown.
  • the bit register also has a function of progressive scan, and its specific working principle is similar to that of the display sub-shift register, and will not be described herein.
  • 13C is a timing chart showing the operation of the logic output circuit of FIG. 11B in which the display output signal of the gate drive circuit 20 and the detection output signal are combined.
  • the display output terminal OUT2 outputs a display output signal of a high level
  • the detection output terminal OUT1 outputs a detection output signal of a low level, thereby causing the second node N2 and the display under the control of the high level of the display output signal.
  • the output terminal OUT2 is connected such that the second node N2 is charged to a high level; under the control of the high level of the second node N2, the logic or output terminal OUT3 is connected to the display output terminal OUT2, so that the logic or the output terminal OUT3 outputs the display.
  • the high level of the output signal is connected such that the second node N2 is charged to a high level; under the control of the high level of the second node N2, the logic or output terminal OUT3 is connected to the display output terminal OUT2, so that the logic or the output terminal OUT3 outputs the display.
  • the high level of the output signal is connected such that the second node N2 is charged to a high level; under the control of the high level of the second no
  • the display output terminal OUT2 outputs a low-level display output signal
  • the detection output terminal OUT1 outputs a low-level detection output signal
  • the second voltage terminal VGH1 inputs a high-level signal
  • the third voltage terminal VGH2 inputs a low level.
  • the third node N3 is connected to the second voltage terminal VGH1 under the control of the high level of the second voltage terminal VGH1 (when the third voltage terminal VGH1 is at a high level, connected to the third voltage terminal VGH2)
  • the third node N3 is charged to a high level; under the control of the third node N3, the logic OR output terminal OUT3 is connected to the fifth voltage terminal VGL2, so that the logic or output terminal OUT3 is pulled down to a low level.
  • the detection output terminal OUT1 outputs a high-level detection output signal
  • the output terminal OUT2 outputs a low-level display output signal, so that the first node N1 and the detection are made under the control of detecting the high level of the output signal.
  • the output terminal OUT1 is connected such that the first node N1 is charged to a high level; under the control of the high level of the first node N1, the logic or output terminal OUT3 is connected to the detection output terminal OUT1, so that the logic or the output terminal OUT3 outputs the detection.
  • the high level of the output signal is connected such that the first node N1 is charged to a high level; under the control of the high level of the first node N1, the logic or output terminal OUT3 is connected to the detection output terminal OUT1, so that the logic or the output terminal OUT3 outputs the detection.
  • the high level of the output signal is connected such that the first node N1 is charged to a high level; under the control of the high level of the first node N1, the
  • the logic or output terminal OUT3 may cause the gate driving circuit 20 to output a display output signal during display to drive, for example, a gate scan line connected thereto, and output a detection output signal during detection to drive, for example, a gate scan line connected thereto, and
  • the detection output signal is used for compensation of a threshold voltage and a mobility of a driving transistor of a pixel circuit connected to the gate scanning line, and the outputs of the display output signal and the detection output signal do not interfere with each other.
  • the operation principle of displaying the sub-shift register portion in the gate driving circuit 20 shown in Fig. 12C will be described with reference to the signal timing chart shown in Fig. 13D.
  • the operation principle of the display sub-shift register 200 shown in FIG. 7C is explained in conjunction with the signal timing chart shown in FIG. 13D, in the first stage 1 and the second stage shown in FIG. 13D. 2.
  • the display sub-shift register 200 can perform the following operations.
  • the first clock signal line CLKA provides a high level signal
  • the clock signal terminal CLK4 of the N-1th stage display sub-shift register 200 is connected to the first clock signal line CLKA, at this stage,
  • the fourth clock signal terminal CLK4 of the N-1 stage display sub-shift register 200 inputs a high-level signal; and since the N-1th stage displays the second pull-up node PU2_N-1 of the sub-shift register 200 is at a high level, Therefore, under the control of the second pull-up node PU2_N-1 high level, the high level input from the fourth clock signal terminal CLK4 is output to the output terminal OUT2_N-1 of the N-1th stage display sub-shift register 200.
  • the level of the potential of the signal timing diagram shown in FIG. 13D is only illustrative and does not represent a true potential value.
  • the second clock signal line CLKB provides a high level signal
  • the fourth clock signal terminal CLK4 of the Nth stage display sub shift register 200 is connected to the second clock signal line CLKB, at this stage, the Nth The fourth clock signal terminal CLK4 of the stage display sub-shift register 200 inputs a high-level signal; and since the second pull-up node PU2_N of the N-th stage display sub-shift register 200 is at a high level, the second pull-up node Under the control of the high level of PU2_N, the high level input from the fourth clock signal terminal CLK4 is output to the output terminal OUT2_N of the Nth stage display sub shift register 200.
  • the sixth clock signal line CLKF provides a high level signal
  • the fourth clock signal terminal CLK4 of the N+1th stage display sub shift register 200 is connected to the sixth clock signal line CLKF, at this stage
  • the fourth clock signal terminal CLK4 of the N+1th stage display sub-shift register 200 inputs a high-level signal; and the second pull-up node PU2_N+1 of the sub-next stage display sub-shift register 200 is at a high level. Therefore, under the control of the second pull-up node PU2_N+1 high level, the high level input from the fourth clock signal terminal CLK4 is output to the output terminal OUT2_N+1 of the (N+1)th stage sub-shift register 200.
  • the seventh clock signal line CLKG provides a high level signal
  • the fourth clock signal terminal CLK4 of the N+2 stage display sub shift register 200 is connected to the seventh clock signal line CLKG, at this stage
  • the fourth clock signal terminal CLK4 of the N+2 stage display sub-shift register 200 inputs a high-level signal; and the second pull-up node PU2_N+2 of the sub-++ level display sub-shift register 200 is at a high level. Therefore, under the control of the second pull-up node PU2_N+2 high level, the high level input from the fourth clock signal terminal CLK4 is output to the output terminal OUT2_N+2 of the N+2th stage display sub-shift register 200.
  • the operation principle of the detection sub-shift register portion in the gate driving circuit 20 shown in Fig. 12C will be described with reference to the signal timing chart shown in Fig. 13E.
  • the operation principle of the detecting sub-shift register 100 shown in FIGS. 5D and 5E will be described with reference to the signal timing chart shown in FIG. 13E, in the first stage shown in FIG. 13E.
  • the detector shift register can perform the following operations.
  • the operation principle of the N-1th-level detection sub-shift register is described.
  • the working principle of the remaining levels of the detection sub-shift register 100 is similar to that of the N-1th-level detection sub-shift register. I will not repeat them here.
  • the first random pulse terminal OE1 inputs a high level signal
  • the display output terminal OUT2_N-1 of the N-1th stage display sub-shift register 200 also outputs a high level signal
  • the N-1th level detection sub-shift The first input terminal INPUT1_N-1 of the bit register 100 is connected to the display output terminal OUT2_N-1 of the N-1th stage display sub-shift register 200, so the first input terminal INPUT1_N of the N-1th stage detection sub-shift register 100 is detected.
  • the first output terminal H1 and the Nth of the random pulse signal control subcircuit are controlled under the control of the first random pulse signal and the high level of the display output signal of the N-1th stage
  • the first input terminal INPUT1_N-1 of the -1 detection sub-shift register 100 is connected, and the first output terminal H1 of the random pulse signal control sub-circuit is charged to a high level due to the bootstrap effect of the capacitor, and therefore, at random
  • the first transistor T1 is turned on under the control of the high level of the first output terminal H1 of the pulse signal control sub-circuit.
  • the second output terminal H2 of the random pulse signal control sub-circuit is at a low level, so the second transistor T2 is at the second output end of the random pulse signal control sub-circuit.
  • the control of the low level of H2 is turned off, so at this stage, the detection output terminal OUT1_N-1 of the N-1th stage detection sub shift register unit 100 is at a low level.
  • the first random pulse terminal OE1 inputs a low level signal
  • the second random pulse terminal OE2 inputs a high level
  • the display output terminal OUT2_N-1 of the N-1th stage display sub-shift register 200 also outputs a high voltage.
  • the flat signal, the first input terminal INPUT1_N-1 of the N-1th stage detection sub shift register 100 is connected to the display output terminal OUT2_N-1 of the N-1th stage display sub shift register 200, so the N-1th level detection
  • the first input terminal INPUT1_N-1 of the sub shift register 100 inputs a high level signal; therefore, the random pulse signal is controlled under the control of the second random pulse signal and the high level of the display output signal of the N-1th stage.
  • the second output terminal H2 of the sub-circuit is connected to the first input terminal INPUT1_N-1 of the N-2th stage detection sub-shift register 100, so that the second output terminal H2 of the random pulse signal control sub-circuit is charged to a high level.
  • the second transistor T2 is turned on under the control of the high level of the second output terminal H2 of the random pulse signal control sub-circuit; and because the first output terminal H1 of the random pulse signal control sub-circuit is still high at this stage Level, so the first transistor T1 is also turned on, so Under the control of the high level of the first output terminal H1 and the second output terminal H2 of the random pulse signal control sub-circuit, the first pull-up node PU_N-1 of the detection sub-shift register 100 is connected to the second clock signal terminal so that The first pull-up node PU1_N-1 is charged to a first high level; at this stage, the third clock signal line CLKC provides a low level signal, and the clock signal of the sub-shift register unit 100 is detected due to the (N-1)th stage.
  • the terminal CLK1 is connected to the third clock signal line CLKC, so at this stage, the clock signal terminal CLK1 of the (N-1)th detection sub-shift register unit 100 inputs a low-level signal; and the N-1-level detection sub-shift The first pull-up node PU1_N-1 of the register unit 100 is at the first high level, so under the control of the first pull-up node PU1_N-1 high level, the low level input of the clock signal terminal CLK1 is output to the N-th
  • the level 1 detects the detection output terminal OUT1_N-2 of the sub shift register unit 100.
  • the display output terminal OUT2_N of the Nth stage display sub shift register outputs a high level signal, and the display of the first input terminal INPUT1_N of the Nth stage detection sub shift register 100 and the Nth stage display sub shift register 200
  • the output terminal OUT2_N is connected, so the first input terminal INPUT1_N of the Nth stage detection sub shift register 100 inputs a high level signal. Since the first random pulse terminal OE1 inputs a low level signal at this stage, the first output terminal H1 of the random pulse signal control subcircuit is still at a low level, and therefore, the first transistor is in the random pulse signal control subcircuit.
  • the control of the low level of an output terminal H1 is turned off, so the first pull-up node PU_N of the Nth-level detection sub-shift register is still at a low level, and thus, at this stage, the N-th stage detection sub-shift register
  • the output terminal OUT1_N is at a low level, thereby ensuring that the function of the progressive scan in the gate driving circuit 20 is turned off, and only the output control of the primary detecting sub shift register is performed.
  • the third clock signal line CLKC provides a high level signal, so at this stage, the clock signal terminal CLK1 of the sub-shift register unit 100 is detected to input a high level signal; and since the Nth stage detection sub-shift register unit The first pull-up node PU1_N-1 of 100 is at the first high level, so under the control of the high level of the first pull-up node PU1_N-1, the high level input of the clock signal terminal CLK1 is output to the N-1th
  • the stage detects the output terminal OUT1_N-1 of the sub-shift register unit 100, and at the same time, the first pull-up node PU1_N-1 is charged to the second high level due to the bootstrap effect of the capacitance.
  • the first output terminal H1 and the second output terminal H2 of the random pulse signal control sub-circuit are connected to the first voltage terminal VGL1, thereby causing a random pulse signal.
  • the first output terminal H1 and the second output terminal H2 of the control sub-circuit are brought to a low level, thereby realizing resetting of the first output terminal H1 and the second output terminal H2 of the random pulse signal control sub-circuit.
  • the total reset line TRST provides a high level signal. Since the first reset terminal RST1 of each stage of the detection sub-shift register 100 is connected to the total reset line, the first reset of each stage of the sub-shift register 100 is detected.
  • the terminal RST1 is input to a high level, so the first pull-up node PU1 of each level detecting sub-shift register 100 is pulled down to a low level, so that the first pull-down node PD1 is pulled up to a high level, thereby The detection output OUT1 is pulled down to a low level. Therefore, at this stage, the output terminal OUT1_N-1 of the N-1th stage detecting sub shift register unit 100 outputs a low level.
  • the level of the first pull-up node can be pulled down twice.
  • An embodiment of the present disclosure further provides a display device 1 including a gate driving circuit 20 provided by an embodiment of the present disclosure, as shown in FIG. 14A.
  • the display device 1 includes an array of a plurality of pixel units 50, each of which employs, for example, a 3T1C pixel circuit shown in FIG. 1D, or another pixel circuit based on the 3T1C structure.
  • the display device 1 may further include a data driving circuit 30.
  • the data driving circuit 30 is for providing a data signal to the pixel array;
  • the gate driving circuit 20 is for providing a gate scanning signal to the pixel array.
  • the gate scan signal includes a composite signal including a display output signal and a detection output signal output from the logic or output terminal OUT3 or the output composite output terminal OUT4.
  • the display output signal is used to drive organic light emitting diodes of the pixel circuits in the pixel array to emit light.
  • the detection output signal is used to compensate for the threshold voltage and mobility of the drive transistor of the pixel circuit in the pixel array.
  • the data driving circuit 30 is electrically connected to the pixel unit 50 through the data line 31, and the gate driving circuit 20 is electrically connected to the pixel unit 50 through the gate line 21.
  • the display device 1 further includes a random pulse generating circuit 40.
  • the random pulse generating circuit 40 is configured to generate a first random pulse signal and is connected to the first random pulse signal line 41.
  • the random pulse generating circuit 40 may be further configured to generate a second random pulse signal and connect with a second random pulse signal line (not shown).
  • the random pulse circuit 40 can be various circuits or devices that can generate pulses, such as a central processing unit (CPU), a data signal processor (DSP), etc., and can also be implemented by a field programmable gate array (FPGA) or the like. .
  • CPU central processing unit
  • DSP data signal processor
  • FPGA field programmable gate array
  • the display device 1 in this embodiment may be: a liquid crystal panel, a liquid crystal television, a display, an OLED panel, an OLED television, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigation device, and the like.
  • the display device 1 may further include other conventional components such as a display panel, which is not limited by the embodiments of the present disclosure.
  • FIG. 14B is a schematic diagram of a display device 1 according to another example provided by an embodiment of the present disclosure.
  • the display device 1 shown in FIG. 14B differs from the display device 1 shown in FIG. 14A in that the gate scanning line of the gate driving circuit 20 includes the scanning line 22 and the compensation scanning line 23, and the scanning line 22 and the compensation scanning line 23 Connected to the scan end Scan1 and the compensating scan end Scan2 in the pixel unit 50, respectively, to supply the scan signal Scan1 to the switching transistor T0 in the pixel unit 50 through the scan line 22, and to compensate the scan line 23 to the sense transistor in the pixel unit 50.
  • S0 provides a compensation scan signal Scan2.
  • Each of the pixel units 50 in this example employs, for example, a 3T1C pixel circuit shown in FIG. 1C, or other pixel circuits based on the 3T1C structure, and the like.
  • the symbol Scan1 may represent both the scanning end and the scanning signal; the symbol Scan2 may represent the compensation scanning end or the compensation scanning signal.
  • Embodiments of the present disclosure also provide a driving method of a gate driving circuit which can be applied to the gate driving circuit 20 of the shift register unit 10 provided by the embodiment of the present disclosure.
  • the driving method of the gate driving circuit 20, for the Nth stage shift register unit 10 includes the following operation: the Nth (N is an integer greater than 1) level display sub-shift register display output terminal OUT2_N output display output signal;
  • the Nth stage detection sub shift register OUT1_N charges its first pull-up node PU1_N in response to the display output signal and the first random pulse signal;
  • the Nth-level detection sub-shift register outputs a detection output signal.
  • Embodiments of the present disclosure also provide another driving method of the gate driving circuit, which can be applied to the gate driving circuit 20 of the shift register unit 10 provided by the embodiment of the present disclosure.
  • the driving method of the gate driving circuit 20, for the Nth stage shift register unit 10 includes the following operations: the display output of the Nth stage display sub shift register outputs a display output signal; the Nth stage detection sub shift register response The first pull-up node is charged on the display output signal, the first random pulse signal and the second random pulse signal; the Nth-level detection sub-shift register outputs a detection output signal.

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Abstract

一种移位寄存器单元(10)、栅极驱动电路(20)、显示装置(1)及驱动方法。移位寄存器单元(10)包括显示子移位寄存器(200)和检测子移位寄存器(100)。显示子移位寄存器(200)包括显示输出端(OUT2)，显示子移位寄存器(200)配置为在显示阶段从显示输出端(OUT2)输出移位寄存器单元(10)的显示输出信号；检测子移位寄存器(100)与显示子移位寄存器(200)的显示输出端(OUT2)连接以接收显示输出信号，且包括第一随机脉冲信号端(OE1)以接收第一随机脉冲信号。检测子移位寄存器(100)配置为包括在显示输出信号为开启电平且第一随机脉冲信号为开启电平时，输出移位寄存器单元(10)的检测输出信号。移位寄存器单元(10)可以消除显示过程中出现的扫描线以及解决显示面板的亮度差异问题。

Description

移位寄存器单元、栅极驱动电路、显示装置及驱动方法
本申请要求于2018年2月14日递交的中国专利申请第201810151698.5号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种移位寄存器单元、栅极驱动电路、显示装置及驱动方法。
背景技术
在显示技术领域，像素阵列通常包括多行栅线和与之交错的多列数据线。对栅线的驱动可以通过贴附的集成驱动电路实现。近几年随着非晶硅薄膜工艺的不断提高，也可以将栅线驱动电路直接集成在薄膜晶体管阵列基板上构成GOA(Gate driver On Array)来对栅线进行驱动。
例如，可以采用由多个级联的移位寄存器单元构成的GOA为像素阵列的多行栅线提供开关态电压信号，从而控制多行栅线依序打开，并由数据线向像素阵列中对应行的像素单元提供数据信号，以形成显示图像的各灰阶所需要的灰度电压，进而显示每一帧图像。
发明内容
本公开至少一实施例提供一种移位寄存器单元，包括显示子移位寄存器和检测子移位寄存器。所述显示子移位寄存器包括显示输出端，所述显示子移位寄存器配置为在显示阶段从所述显示输出端输出所述移位寄存器单元的显示输出信号；所述检测子移位寄存器与所述显示子移位寄存器的显示输出端连接以接收所述显示输出信号，且包括第一随机脉冲信号端以接收第一随机脉冲信号，所述检测子移位寄存器配置为在所述显示输出信号和所述第一随机脉冲信号同时为开启电平时，输出所述移位寄存器单元的检测输出信号。
例如，在本公开一实施例提供的移位寄存器单元中，所述检测子移位寄 存器包括第一检测输入子电路、第一上拉节点复位子电路和检测输出子电路；所述第一检测输入子电路配置为响应于所述显示输出信号和所述第一随机脉冲信号对第一上拉节点进行充电；所述第一上拉节点复位子电路配置为响应于第一复位信号对所述第一上拉节点进行复位；所述检测输出子电路配置为在所述第一上拉节点的电平的控制下，将第一时钟信号输出至检测输出端。
例如，在本公开一实施例提供的移位寄存器单元中，所述检测子移位寄存器还包括第一上拉节点降噪子电路、第一输出降噪子电路和第一下拉子电路；所述第一上拉节点降噪子电路配置为在第一下拉节点的电平的控制下，对所述第一上拉节点进行降噪；所述检测输出降噪子电路配置在所述第一下拉节点的电平的控制下，对所述检测输出端进行降噪；所述第一下拉子电路配置为在所述第一上拉节点的电平的控制下，对所述第一下拉节点的电平进行控制。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一检测输入子电路包括第一晶体管和第二晶体管；所述第一晶体管的栅极配置为和所述显示输出端连接以接收所述显示输出信号，所述第一晶体管的第一极配置为和第二时钟信号端连接以接收第二时钟信号，所述第一晶体管的第二极配置为和所述第二晶体管的第一极连接；所述第二晶体管的栅极配置为和所述第一随机脉冲信号端连接以接收所述第一随机脉冲信号，所述第二晶体管的第二极和所述第一上拉节点连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一检测输入子电路包括第一晶体管。所述第一晶体管的栅极配置为和所述显示输出端连接以接收所述显示输出信号，所述第一晶体管的第一极配置为和所述第一随机脉冲信号端连接以接收所述第一随机脉冲信号，所述第一晶体管的第二极配置为和所述第一上拉节点连接，或者，所述第一晶体管的栅极配置为和所述第一随机脉冲信号端连接以接收所述第一随机脉冲信号，所述第一晶体管的第一极配置为和所述显示输出端连接以接收所述显示输出信号，所述第一晶体管的第二极配置为和所述第一上拉节点连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一上拉节点复位子电路包括第三晶体管，所述第三晶体管的栅极配置为和第一复位端连接以接收所述第一复位信号，所述第三晶体管的第一极配置为和所述第一上 拉节点连接，所述第三晶体管的第二极配置为和第一电压端连接以接收第一电压信号；或所述检测输出子电路包括第四晶体管和第一存储电容，所述第四晶体管的栅极配置为和所述第一上拉节点连接，所述第四晶体管的第一极配置为和第一时钟信号端连接以接收所述第一时钟信号，所述第四晶体管的第二极配置为和所述检测输出端连接以输出所述检测输出信号；所述第一存储电容的第一极和所述第一上拉节点连接，所述第一存储电容的第二极和所述检测输出端连接；或所述第一上拉节点降噪子电路包括第五晶体管，所述第五晶体管的栅极配置为和所述第一下拉节点连接，所述第五晶体管的第一极配置为和所述第一上拉节点连接，所述第五晶体管的第二极配置为和所述第一电压端连接；或所述检测输出降噪子电路包括第六晶体管，所述第六晶体管的栅极配置为和所述第一下拉节点连接，所述第六晶体管的第一极配置为和所述检测输出端连接，所述第六晶体管的第二极配置为和所述第一电压端连接；或所述第一下拉子电路包括第七晶体管和第八晶体管，所述第七晶体管的栅极与第一极连接，且配置为与第二电压端连接以接收第二电压信号，所述第七晶体管的第二极配置为与所述第一下拉节点连接；所述第八晶体管的栅极与所述第一上拉节点连接，所述第八晶体管的第一极与所述第一下拉节点连接，所述第八晶体管的第二极配置为与所述第一电压端连接以接收所述第一电压信号。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一下拉子电路还包括第九晶体管和第十晶体管。所述第九晶体管的栅极和第一极连接，且配置为与第三电压端连接以接收第三电压信号，所述第九晶体管的第二极与所述第一下拉节点连接；所述第十晶体管的栅极与所述第一上拉节点连接，所述第十晶体管的第一极与所述第一下拉节点连接，所述第十晶体管的第二极配置为与所述第一电压端连接以接收所述第一电压信号。
例如，在本公开一实施例提供的移位寄存器单元中，所述检测子移位寄存器还包括第二检测输入子电路和检测输入端。所述第二检测输入子电路配置为和检测输入端连接以接收检测输入信号且响应于所述检测输入信号对所述第一上拉节点进行充电。
例如，在本公开一实施例提供的移位寄存器单元中，所述第二检测输入子电路包括第十一晶体管。所述第十一晶体管的栅极和第一极连接，且配置 为和所述检测输入端连接以接收所述检测输入信号，所述第十一晶体管的第二极和所述第一上拉节点连接，或者，所述第十一晶体管的栅极配置为和所述检测输入端连接以接收所述检测输入信号，所述第十一晶体管的第一极配置为和第三时钟信号端连接以接收第三时钟信号，所述第十一晶体管的第二极和所述第一上拉节点连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一上拉节点复位子电路还包括第十二晶体管。所述第十二晶体管的栅极和第二复位端连接以接收第二复位信号，所述第十二晶体管的第一极和所述第一上拉节点连接，所述第十二晶体管的第二极和所述第一电压端连接以接收所述第一电压信号。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一检测输入子电路还包括随机脉冲信号控制子电路和第二随机脉冲信号端。所述随机脉冲信号控制子电路配置为和显示输出端、第一随机脉冲信号端和第二随机脉冲信号端连接以接收显示输出信号、第一随机脉冲信号和第二随机脉冲信号，且响应于所述显示输出信号、所述第一随机脉冲信号和所述第二随机脉冲信号使所述第一随机脉冲信号和所述第二随机脉冲信号同时为有效电平。
例如，在本公开一实施例提供的移位寄存器单元中，所述随机脉冲信号控制子电路包括第五十一晶体管、第五十二晶体管、第五十三晶体管、第五十四晶体管、第五存储电容和第六存储电容。所述第五十一晶体管的栅极和所述第一随机脉冲信号端连接，第一极和所述显示输出端连接，第二极和所述第一晶体管的栅极连接；所述第五十二晶体管的栅极和所述第二脉冲信号端连接，第一极和所述显示输出端连接，第二极和所述第二晶体管的栅极连接；所述第五十三晶体管的栅极和所述第一时钟信号端连接，第一极和所述第一晶体管的栅极连接，第二极和所述第一电压端连接；所述第五十四晶体管的栅极和所述第一时钟信号端连接，第一极和所述第二晶体管的栅极连接，第二极和所述第一电压端连接；所述第五存储电容的第一极和所述第一晶体管的栅极连接，第二极和所述第一电压端连接；所述第六存储电容的第一极和所述第二晶体管的栅极连接，第二极和所述第一电压端连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述检测子移位寄存器单元还包括防漏电子电路。所述防漏电子电路配置为在所述第一上拉节 点的电平的控制下，保持所述第一上拉节点的高电位。
例如，在本公开一实施例提供的移位寄存器单元中，所述防漏电子电路包括第十三晶体管，所述第十三晶体管的栅极和所述第一上拉节点连接，所述第十三晶体管的第一极和第四电压端连接以接收第四电压信号，所述第十三晶体管的第二极和反馈节点连接；或所述第二检测输入子电路包括第十一晶体管和第十四晶体管；所述第十一晶体管的栅极配置为和检测输入端连接以接收所述检测输入信号，所述第十一晶体管的第一极配置为和第三时钟信号端连接以接收第三时钟信号，所述第十一晶体管的第二极和所述第十四晶体管的第一极连接，且配置为和所述反馈节点连接；所述第十四晶体管的栅极和所述第十一晶体管的栅极连接，所述第十四晶体管的第二极和所述第一上拉节点连接；或所述第一上拉节点复位子电路包括第三晶体管、第十二晶体管、第十五晶体管和第十六晶体管；所述第三晶体管的栅极配置为和所述第一复位端连接以接收所述第一复位信号，所述第三晶体管的第一极和所述第十五晶体管的第二极连接，且配置为和所述反馈节点连接，所述第三晶体管的第二极配置为和第一电压端连接；所述第十二晶体管的栅极和所述第二复位端连接以接收所述第二复位信号，所述第十二晶体管的第一极和所述第十六晶体管的第二极连接，且配置为和所述反馈节点连接，所述第十二晶体管的第二极和所述第一电压端连接以接收第一电压信号；所述第十五晶体管的栅极和所述第三晶体管的栅极连接，所述第十五晶体管的第一极和所述第一上拉节点连接；所述第十六晶体管的栅极和所述第十二晶体管的栅极连接，所述第十六晶体管的第一极和所述第一上拉节点连接；或所述第一上拉节点降噪子电路包括第五晶体管和第十七晶体管；所述第五晶体管的栅极配置为和所述第一下拉节点连接，所述第五晶体管的第一极配置为和所述第十七晶体管的第二极连接，且配置为和所述反馈节点连接，所述第五晶体管的第二极配置为和所述第一电压端连接；所述第十七晶体管的栅极和所述第五晶体管的栅极连接，所述第十七晶体管的第一极和所述第一上拉节点连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述显示子移位寄存器包括显示输入子电路、第二上拉节点复位子电路和显示输出子电路。所述显示输入子电路配置为响应于显示输入信号对第二上拉节点进行充电；所述第二上拉节点复位子电路配置为响应于第三复位端接收的第三复位信号对 所述第二上拉节点进行复位；所述显示输出子电路配置为在所述第二上拉节点的电平的控制下，将第四时钟信号输出至所述显示输出端。
例如，在本公开一实施例提供的移位寄存器单元中，所述显示子移位寄存器还包括第二上拉节点降噪电路、显示输出降噪子电路和第二下拉子电路；所述第二上拉节点降噪子电路配置为在第二下拉节点的电平的控制下，对所述第二上拉节点进行降噪；所述显示输出降噪子电路配置在所述第二下拉节点的电平的控制下，对所述显示输出端进行降噪；所述第二下拉子电路配置为在所述第二上拉节点的电平的控制下，对所述第二下拉节点的电平进行控制。
例如，本公开一实施例提供的移位寄存器单元，还包括输出控制电路。所述输出控制电路与所述检测子移位寄存器的第一上拉节点和第一下拉节点以及与所述显示子移位寄存器的第二上拉节点和第二下拉节点连接，且配置为当所述第一上拉节点和所述第二上拉节点之一为有效电平时则拉低另一个。
例如，在本公开一实施例提供的移位寄存器单元中，所述输出控制电路包括显示输出控制子电路和检测输出控制子电路。所述检测输出控制子电路配置为在所述第一上拉节点的电平的控制下，对所述第二上拉节点和所述第二下拉节点的电平进行控制；所述显示输出控制子电路配置为在所述第二上拉节点的电平的控制下，对所述第一上拉节点和所述第一下拉节点的电平进行控制。
例如，本公开一实施例提供的移位寄存器单元，还包括逻辑或电路。所述逻辑或电路与所述显示子移位寄存器的显示输出端和所述检测子移位寄存器的检测输出端连接，且配置为将所述显示输出信号和所述检测输出信号进行或运算以得到复合输出信号。
例如，在本公开一实施例提供的移位寄存器单元中，所述逻辑或电路包括第一逻辑或输入子电路、第二逻辑或输入子电路、第一输出控制子电路、第二输出控制子电路、第一节点降噪子电路、第二节点降噪子电路、输出降噪控制子电路和输出降噪子电路。所述第一逻辑或输入子电路配置为响应于所述检测输出信号对第一节点进行充电；所述第二逻辑或输入子电路配置为响应于所述显示输出信号对第二节点进行充电；所述第一输出控制子电路配 置为在所述第一节点的电平的控制下，输出所述检测输出信号；所述第二输出控制子电路配置为在所述第二节点的电平的控制下，输出所述显示输出信号；所述第一节点降噪电路配置为在所述显示输出信号的电平的控制下，对所述第一节点进行降噪；所述第二节点降噪电路配置为在所述检测输出信号的电平的控制下，对所述第二节点进行降噪；所述输出降噪控制子电路配置为在所述显示输出信号和所述检测输出信号的电平的控制下对第三节点的电平进行控制；所述输出降噪子电路配置为在所述第三节点的电平的控制下，对逻辑或输出端进行降噪。
本公开至少一实施例还提供一种栅极驱动电路，包括多个级联的本公开实施例提供的移位寄存器单元。每个所述移位寄存器单元的检测子移位寄存器的第一随机脉冲信号端与第一随机脉冲信号线连接；除第一级显示子移位寄存器外，其余各级显示子移位寄存器的显示输入端和上一级显示子移位寄存器的显示输出端连接；除最后一级显示子移位寄存器外，其余各级显示子移位寄存器的第三复位端和下一级显示子移位寄存器的显示输出端连接。
本公开至少一实施例还提供一种栅极驱动电路，包括多个级联的本公开实施例提供的移位寄存器单元。每个所述移位寄存器单元的检测子移位寄存器的第一随机脉冲信号端与第一随机脉冲信号线连接；除第一级显示子移位寄存器外，其余各级显示子移位寄存器的显示输入端和上一级显示子移位寄存器的显示输出端连接；除第一级检测子移位寄存器外，其余各级检测子移位寄存器的检测输入端和上一级检测子移位寄存器的检测输出端连接。
本公开至少一实施例还提供一种栅极驱动电路，包括多个级联的本公开实施例提供的移位寄存器单元。每个所述移位寄存器单元的检测子移位寄存器的第一随机脉冲信号端与第一随机脉冲信号线连接；每个所述移位寄存器单元的检测子移位寄存器的第二随机脉冲信号端与第二随机脉冲信号线连接；除第一级和第二级显示子移位寄存器单元外，其余各级显示子移位寄存器的显示输入端和与其相隔一级的上级显示子移位寄存器的显示输出端连接；除第一级检测子移位寄存器外，其余各级检测子移位寄存器的检测输入端和上一级检测子移位寄存器的检测输出端连接。
本公开至少一实施例还提供一种显示装置，包括本公开任一实施例提供的栅极驱动电路。
例如，本公开一实施例提供的显示装置，还包括随机脉冲发生电路。所述随机脉冲发生电路配置为生成所述第一随机脉冲信号且与所述第一随机脉冲信号线连接。
本公开至少一实施例还提供一种栅极驱动电路的驱动方法，包括：第N级显示子移位寄存器的显示输出端输出显示输出信号；第N级检测子移位寄存器响应于所述显示输出信号和所述第一随机脉冲信号对所述第一上拉节点进行充电；所述第N级检测子移位寄存器输出检测输出信号；N为大于1的整数。
本公开至少一实施例还提供一种栅极驱动电路的驱动方法，包括：第N级显示子移位寄存器的显示输出端输出显示输出信号；第N级检测子移位寄存器响应于所述显示输出信号、所述第一随机脉冲信号和所述第二随机脉冲信号对所述第一上拉节点进行充电；所述第N级检测子移位寄存器输出检测输出信号；N为大于1的整数。
本公开的实施例提供的移位寄存器单元、栅极驱动电路、显示装置以及驱动方法，可以通过检测子移位寄存器的随机检测功能消除由于逐行扫描产生的扫描线以及亮度不均匀的问题，进一步还允许对像素电路中的驱动晶体管的阈值电压和迁移率的非均匀性以及OLED的老化等进行更充分地补偿，进而可以提高显示装置的显示质量。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为一种像素电路的示意图；
图1B为另一种像素电路的示意图；
图1C为再一种像素电路的示意图；
图1D为又一种像素电路的示意图；
图1E为一种感测电压随时间变化的曲线图；
图2为本公开一实施例提供的一种移位寄存器单元的示意图；
图3A为图2中所示的移位寄存器单元的一种检测子移位寄存器的示意 图；
图3B为图2中所示的移位寄存器单元的另一种检测子移位寄存器的示意图；
图4A为图3B中所示的检测子移位寄存器的一种具体实现示例的电路示意图；
图4B为图3B中所示的检测子移位寄存器的另一种具体实现示例的电路示意图；
图4C为图3B中所示的检测子移位寄存器的再一种具体实现示例的电路示意图；
图4D为图3B中所示的检测子移位寄存器的又一种具体实现示例的电路示意图；
图5A为图2中所示的移位寄存器单元的另一种检测子移位寄存器的示意图；
图5B为图5A中所示的检测子移位寄存器的一种具体实现示例的电路示意图；
图5C为图5A中所示的检测子移位寄存器的另一种具体实现示例的电路示意图；
图5D为图5A中所示的检测子移位寄存器的又一种具体实现示例的电路示意图；
图5E为图5D中所示的检测子移位寄存器的随机脉冲控制子电路的电路示意图；
图5F为图5A中所示的检测子移位寄存器的随机脉冲控制子电路的电路示意图；
图5G为图5A中所示的检测子移位寄存器的随机脉冲控制子电路的电路示意图；
图5H为图5A中所示的检测子移位寄存器的随机脉冲控制子电路的电路示意图；
图6A为图2中所示的移位寄存器单元的另一种检测子移位寄存器的示意图；
图6B为图6A中所示的检测子移位寄存器的一种具体实现示例的电路示 意图；
图7A为图2中所示的移位寄存器单元的一种显示子移位寄存器的示意图；
图7B为图2中所示的移位寄存器单元的另一种显示子移位寄存器的示意图；
图7C为图7B中所示的显示子移位寄存器的一种具体实现示例的电路示意图；
图8A为本公开一实施例提供的另一种移位寄存器单元的示意图；
图8B为本公开一实施例提供的另一种移位寄存器单元的示意图；
图9A为图8A中所示的一种输出控制电路的示意图；
图9B为图9A中所示的输出控制电路的一种具体实现示例的电路示意图；
图9C为图8A中所示的一种移位寄存器的一种具体实现示例的电路示意图；
图9D为图8B中所示的一种移位寄存器的一种具体实现示例的电路示意图；
图10为本公开一实施例提供的另一种移位寄存器单元的示意图；
图11A为图10中所示的一种逻辑或电路的示意图；
图11B为图11A中所示的逻辑或电路的一种具体实现示例的电路示意图；
图12A为本公开一实施例提供的一种栅极驱动电路的示意图；
图12B为本公开一实施例提供的另一种栅极驱动电路的示意图；
图12C为本公开一实施例提供的又一种栅极驱动电路的示意图；
图13A为对应于图12A中所示的栅极驱动电路中的显示子移位寄存器工作时的信号时序图；
图13B为对应于图12A中所示的栅极驱动电路中的检测子移位寄存器工作时的信号时序图；
图13C为对应于图11A中所示的逻辑或电路工作时的信号时序图；
图13D为对应于图12C中所示的栅极驱动电路中的显示子移位寄存器工作时的信号时序图；
图13E为对应于图12C中所示的栅极驱动电路中的检测子移位寄存器工作时的信号时序图；
图13F为对应于图12C中所示的栅极驱动电路中的检测子移位寄存器工作时的另一种信号时序图；
图14A为本公开一实施例提供的一种显示装置的示意图；以及
图14B为本公开一实施例提供的另一种显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
OLED显示装置中的像素电路一般采用矩阵驱动方式，根据每个像素单元中是否引入开关元器件分为有源矩阵(Active Matrix)驱动和无源矩阵(Passive Matrix)驱动。AMOLED在每一个像素的像素电路中都集成了一组薄膜晶体管和存储电容，通过对薄膜晶体管和存储电容的驱动控制，实现对流过OLED的电流的控制，从而使OLED根据需要发光。
AMOLED显示装置中使用的基础像素电路通常为2T1C像素电路，即利用两个薄膜晶体管(Thin-film transistor，TFT)和一个存储电容Cst来实现驱 动OLED发光的功能。图1A和图1B分别为示出了两种2T1C像素电路的示意图。
如图1A所示，一种2T1C像素电路包括开关晶体管T0、驱动晶体管N0以及存储电容Cst。例如，该开关晶体管T0的栅极连接扫描线以接收扫描信号Scan1；例如，该开关晶体管T0的源极连接到数据线以接收数据信号Vdata；该开关晶体管T0的漏极连接到驱动晶体管N0的栅极；驱动晶体管N0的源极连接到第一电压端以接收第一电压Vdd(高电压)，驱动晶体管N0的漏极连接到OLED的正极端；存储电容Cst的一端连接到开关晶体管T0的漏极以及驱动晶体管N0的栅极，另一端连接到驱动晶体管N0的源极以及第一电压端；OLED的负极端连接到第二电压端以接收第二电压Vss(低电压，例如接地电压)。该2T1C像素电路的驱动方式是通过两个TFT和存储电容Cst来控制像素的明暗(灰阶)。当通过扫描线施加扫描信号Scan1以开启开关晶体管T0时，数据驱动电路通过数据线输入的数据信号Vdata可以通过开关晶体管T0对存储电容Cst充电，由此可以将数据信号Vdata存储在存储电容Cst中，且此存储的数据信号Vdata可以控制驱动晶体管N0的导通程度，由此可以控制流过驱动晶体管N0以驱动OLED发光的电流大小，即此电流决定该像素发光的灰阶。在图1A所示的2T1C像素电路中，开关晶体管T0为N型晶体管而驱动晶体管N0为P型晶体管。
如图1B所示，另一种2T1C像素电路也包括开关晶体管T0、驱动晶体管N0以及存储电容Cst，但是其连接方式略有改变，且驱动晶体管N0为N型晶体管。图1B的像素电路相对于图1A的变化之处包括：OLED的正极端连接到第一电压端以接收第一电压Vdd(高电压)，而负极端连接到驱动晶体管N0的漏极，驱动晶体管N0的源极连接到第二电压端以接收第二电压Vss(低电压，例如接地电压)。存储电容Cst的一端连接到开关晶体管T0的漏极以及驱动晶体管N0的栅极，另一端连接到驱动晶体管N0的源极以及第二电压端。该2T1C像素电路的工作方式与图1A所示的像素电路基本相同，这里不再赘述。
此外，对于图1A和图1B所示的像素电路，开关晶体管T0不限于N型晶体管，也可以为P型晶体管，只需要控制扫描信号Scan1进行相应地改变即可。
OLED显示装置通常包括多个按阵列排布的像素单元，每个像素单元例如可以包括上述像素电路。在像素电路进行显示操作时，像素电路中的驱动晶体管N0处于饱和状态下的输出电流I OLED可以通过如下公式得到：
I OLED＝1/2*K(Vg-Vs-Vth) 2
这里，K＝W/L*C*μ，W/L为驱动晶体管N0的沟道的宽长比(即，宽度与长度的比值)，μ为电子迁移率，C为单位面积的电容，Vg为驱动晶体管N0栅极的电压，Vs为驱动晶体管N0源极的电压，Vth为驱动晶体管N0的阈值电压。需要说明的是，在本公开的实施例中，将K称为像素电路中的驱动晶体管的电流系数，以下各实施例与此相同，不再赘述。
各个像素电路中的驱动晶体管的阈值电压Vth由于制备工艺可能存在差异，而且由于例如温度变化的影响，驱动晶体管的阈值电压Vth可能会产生漂移现象。同时，驱动晶体管的电流系数K随着时间也会发生老化现象。因此，各个驱动晶体管的阈值电压Vth以及电流系数K的不同以及老化可能会导致显示不良(例如显示不均匀)，所以就需要对阈值电压Vth以及电流系数K进行补偿。
例如，在经由开关晶体管T0向驱动晶体管N0的栅极施加数据信号(例如，数据电压)Vdata之后，数据信号Vdata可以对存储电容Cst充电，而且由于数据信号Vdata可以使得驱动晶体管N0导通，则与存储电容Cst的一端电连接的驱动晶体管N0的源极或漏极的电压Vs可能相应地改变。
例如，图1C示出了一种可以检测驱动晶体管的阈值电压的像素电路(也即，3T1C电路)，驱动晶体管N0为N型晶体管。例如，如图1C所示，为了实现补偿功能，可以在2T1C电路的基础上引入感测晶体管S0，也即，可以将感测晶体管S0的第一端连接到驱动晶体管N0的源极，感测晶体管S0的第二端经由感测线与检测电路(未示出)连接，感测晶体管S0的栅极接收补偿扫描信号Scan2。由此当驱动晶体管N0导通之后，可以施加补偿扫描信号Scan2，由此经由感测晶体管S0对检测电路充电，使得驱动晶体管N0的源极电位改变。当驱动晶体管N0的源极的电压Vs等于驱动晶体管N0的栅极电压Vg与驱动晶体管的阈值电压Vth的差值时，驱动晶体管N0截止。此时，可以在驱动晶体管N0截止后，再经由导通的感测晶体管S0从驱动晶体管N0的源极获取感测电压(也即，驱动晶体管N0截止后的源极的电压 Vb)。在获取驱动晶体管N0截止后的源极的电压Vb之后，则可以获取驱动晶体管的阈值电压Vth＝Vdata-Vb，由此可以基于每个像素电路中驱动晶体管的阈值电压针对每个像素电路建立(也即，确定)补偿数据，进而可以实现显示面板各个子像素的阈值电压补偿功能。
例如，如图1D所示，该扫描信号Scan1和补偿扫描信号Scan2也可以由同一条栅极扫描线提供。该像素电路既可以进行电流检测，同时又可以点亮有机发光二极管使其发光。
例如，图1E示出了一种经由导通的感测晶体管S0从驱动晶体管N0的源极获取的感测电压随时间变化的曲线图。例如，施加数据信号Vdata之后，在经由感测线对检测电路充电的过程中，随着对存储电容Cst等的充电时间的增加，充电速度将相应地降低(也即，感测电压增加的速度降低)(参见图1E)，这是因为充电电流将随着感测电压(也即，驱动晶体管N0的源极的电压Vs)的增加而降低。具体地，驱动晶体管N0处于饱和状态下输出电流I OLED可以通过如下公式得到：
I OLED＝1/2*K(Vg-Vs-Vth) 2
＝1/2*K(Vdata-Vs-Vth) 2
＝1/2*K((Vdata-Vth)-Vs) 2。
这里，K＝W/L*C*μ，W/L为驱动晶体管N0的沟道的宽长比(即，宽度与长度的比值)，μ为电子迁移率，C为单位面积的电容。
在驱动晶体管N0的源极的电压Vs增加至Vdata-Vth的过程中，随着Vs的增加，[(Vdata-Vth)-Vs]的值将不断降低，对应地，驱动晶体管N0输出的电流I OLED以及充电速度也将随之不断降低，因此，从充电起始到驱动晶体管N0截止所需的时间Ts较长，因此通常需要在显示面板结束正常显示之后的关机过程中进行阈值电压的检测。
在采用如图1C或图1D所示的像素电路的OLED面板中，相应的GOA电路通常也包括显示部分和检测(Sense)部分。显示部分用于图像的显示，检测部分用于检测或补偿上述像素电路中的驱动晶体管N0的阈值电压和迁移率的非均匀性以及OLED的老化等，二者缺一不可。然而，在检测部分进行阈值电压和迁移率的非均匀性的补偿的过程中，由于GOA电路通常采用顺序扫描的方式进行补偿，一方面，伴随GOA电路的逐行扫描，在补偿的 过程中显示面板会出现一条逐行移动的扫描线，因此严重影响了OLED显示面板的显示质量；另一方面，由于逐行扫描造成的补偿时间的差异，使得显示面板的不同区域的亮度不均匀。
本公开至少一实施例提供一种移位寄存器单元，包括显示子移位寄存器和检测(Sense)子移位寄存器。显示子移位寄存器包括显示输出端，配置为从显示输出端输出移位寄存器单元的显示输出信号；检测子移位寄存器与显示子移位寄存器的显示输出端连接以接收显示输出信号，且包括第一随机脉冲信号端以接收第一随机脉冲信号。检测子移位寄存器配置为包括在显示输出信号为开启电平且第一随机脉冲信号为开启电平时，输出移位寄存器单元的检测输出信号。
本公开的实施例还提供对应于上述移位寄存器单元的栅极驱动电路、显示装置以及驱动方法。
本公开的实施例提供的移位寄存器单元、栅极驱动电路、显示装置以及驱动方法，可以通过检测子移位寄存器的随机检测功能消除由于逐行扫描产生的扫描线以及亮度不均匀的问题，进一步还允许对像素电路中的驱动晶体管的阈值电压和迁移率的非均匀性以及OLED的老化等进行更充分地补偿，进而可以提高显示装置的显示质量。
下面结合附图对本公开的实施例及其示例进行详细说明。
图2为本公开一实施例提供的一种移位寄存器单元的示意图。如图2所示，该移位寄存器单元10包括检测子移位寄存器100和显示子移位寄存器200。
例如，显示子移位寄存器200包括显示输出端(图中未示出)，且配置为在显示阶段从显示输出端输出移位寄存器单元的显示输出信号。例如，显示子移位寄存器200输出的显示输出信号，用于控制显示面板的图像显示。例如，当采用图1D所示的像素电路的连接方式时，显示子移位寄存器200输出的显示输出信号，也用于对像素电路中的驱动晶体管的阈值电压和迁移率的非均匀性以及OLED的老化等进行补偿。
例如，检测子移位寄存器100与显示子移位寄存器200的显示输出端连接以接收显示输出信号。例如，检测子移位寄存器100还包括第一随机脉冲信号端OE1以接收第一随机脉冲信号。该检测子移位寄存器100配置为在显 示输出信号和第一随机脉冲信号同时为开启电平时，输出移位寄存器单元的检测输出信号。例如，该检测子移位寄存器100的检测输出信号用于对像素电路中驱动晶体管的阈值电压和迁移率的非均匀性以及OLED的老化等进行补偿。例如，当采用图1D所示的像素电路的连接方式时，检测子移位寄存器100的检测输出信号也用于控制显示面板的图像显示。
例如，该显示输出信号作为控制扫描信号Scan1通过栅极扫描线传输至图1C中的像素电路的开关晶体管的栅极，以控制数据信号的写入操作，检测输出信号作为补偿扫描信号Scan2通过补偿扫描线传输至图1C中的感测晶体管的栅极，以控制驱动晶体管N0的阈值电压和迁移率的补偿操作。例如，该显示输出信号和检测输出信号还可以通过同一条扫描线传输至图1D所示的像素电路中的开关晶体管T0和感测晶体管S0的栅极，以控制数据信号的写入操作和驱动晶体管N0的阈值电压和迁移率以及OLED的老化等的补偿操作。例如，该第一随机脉冲信号由随机脉冲发生电路产生，并通过第一随机脉冲信号线将第一随机脉冲信号发送至检测子移位寄存器100。
由于该第一随机脉冲信号在发生时间上具有随机性，并且检测子移位寄存器100的输出与否由显示输出信号和第一随机脉冲信号共同控制，因此采用该移位寄存器单元用于栅极驱动电路的显示装置可有效避免因逐行扫描而产生的扫描线以及亮度不均匀的问题，进一步还能够对像素电路中的驱动晶体管的阈值电压和迁移率进行补偿，进而可以提高显示质量。
图3A为图2中所示的一种检测子移位寄存器的示意图。如图3A所示，该示例性的检测子移位寄存器100包括第一检测输入子电路110、第一上拉节点复位子电路120和检测输出子电路130。
该第一检测输入子电路110配置为响应于显示输出信号和第一随机脉冲信号对第一上拉节点PU1进行充电。例如，该第一检测输入子电路110可以与该检测子移位寄存器的第一输入端INPUT1、第一随机脉冲信号端OE1和第一上拉节点PU1连接。例如，第一输入端INPUT1配置为与显示输出端连接以接收显示子移位寄存器200的显示输出信号。例如，该第一检测输入子电路110配置为在第一输入端INPUT1接收的显示输出信号和第一随机脉冲信号端OE1接收的第一随机脉冲信号的共同控制下，使第一上拉节点PU1和第一输入端INPUT1或第一随机脉冲信号端OE1电连接或另外提供的高电 压端电连接，从而可以使第一输入端INPUT1或第一随机脉冲信号端OE1输入的高电平信号，又或高电压端输出的高电平信号对第一上拉节点PU1进行充电，以使得第一上拉节点PU1的电压增加(拉高)，以控制检测输出子电路130导通。
该第一上拉节点复位子电路120配置为响应于第一复位信号对第一上拉节点PU1进行复位，以使得第一上拉节点PU1的电压减小(拉低)，从而使得检测输出子电路130不再导通。例如，该第一复位信号为全局复位信号，该全局复位信号可以对所有的检测子移位寄存器100的第一上拉节点PU1进行复位。例如，该第一上拉节点复位子电路120可以配置为和第一复位端RST1连接，从而可以在第一复位端RST1输入的第一复位信号的控制下，使得第一上拉节点PU1和低电平信号或低电压端电连接，该低电压端例如为第一电压端VGL1，从而可以对第一上拉节点PU1进行下拉复位。需要说明的是，第一电压端VGL1例如可以配置为保持输入直流低电平信号，将该直流低电平称为第一电压信号，以下各实施例与此相同，不再赘述。
该检测输出子电路130配置为在第一上拉节点PU1的电平的控制下，从而可以将第一时钟信号输出至检测输出端OUT1，作为该检测子移位寄存器单元100的检测输出信号，以控制与之相连接的像素电路中的驱动晶体管的阈值电压和迁移率以及OLED的老化等的补偿。例如，该检测输出子电路130可以配置为在第一上拉节点PU1的电平的控制下导通，使第一时钟信号端CLK1和检测输出端OUT1电连接，从而可以将第一时钟信号端CLK1输入的第一时钟信号输出至检测输出端OUT1。
例如，如图3B所示，在本公开实施例的另一个示例中，在图3A所示的示例的基础上，检测子移位寄存器100还包括第一上拉节点降噪子电路140、第一输出降噪子电路150和第一下拉子电路160。
该第一上拉节点降噪子电路140配置为在第一下拉节点PD1的电平的控制下，对第一上拉节点PU1进行降噪。例如，该第一上拉节点降噪电路140可以配置为和第一电压端VGL1连接，以在第一下拉节点PD1的电平的控制下，使第一上拉节点PU1和第一电压端VGL1电连接，从而对第一上拉节点PU1进行下拉降噪。
该第一输出降噪子电路150配置为在第一下拉节点PD1的电平的控制 下，对检测输出端OUT1进行降噪。例如，该第一输出降噪子电路150可以配置为在第一下拉节点PD1的电平的控制下，使检测输出端OUT1和第一电压端VGL1电连接，从而对检测输出端OUT1进行下拉降噪。
该第一下拉子电路160配置为在第一上拉节点PU1的电平的控制下，对第一下拉节点PD1的电平进行控制。例如，该第一下拉子电路160可以连接第一电压端VGL1、第二电压端VGH1、第一上拉节点PU1和第一下拉节点PD1，以在第一上拉节点PU1的电平的控制下，使第一下拉节点PD1和第一电压端VGL1电连接，从而对第一下拉节点PD1的电平进行控制，使得当第一上拉节点PU1处于高电位时，第一下拉节点PD1处于低电位。如图所示，该第一下拉子电路160可以在第二电压端VGH1的电平的控制下，使第一下拉节点PD1和第二电压端VGH1电连接，从而使第一下拉节点PD1处于高电位。例如第二电压端VGH1可以配置为保持输入直流高电平信号，将该直流高电平称为第二电压信号，以下本公开的各实施例与此相同，不再赘述。
例如，图3B中所示的检测子移位寄存器100在一个示例中可以具体实现为图4A所示的电路结构。在下面的说明中以各晶体管为N型晶体管为例进行说明，相应地下文中施加至其栅极的高电平为开启电压而低电平为截止电压以实现对该N型晶体管的开关控制，但这些并不构成对本公开实施例的限制。
第一检测输入子电路110可以实现为第一晶体管T1和第二晶体管T2。第一晶体管T1的栅极配置为和显示输出端(即第一输入端INPUT1)连接以接收显示输出信号，第一极配置为和第二时钟信号端CLK2连接以接收第二时钟信号，第二极配置为和第二晶体管T2的第一极连接；第二晶体管T2的栅极配置为和第一随机脉冲信号端OE1连接以接收第一随机脉冲信号，第二极和第一上拉节点PU1连接,从而当第一晶体管T1由于第一输入端INPUT1接收到的导通信号(高电平信号)和第二晶体管T2由于第一随机脉冲信号端OE1接收到的导通信号(高电平信号)同时导通时，使用第二时钟信号端CLK2接收的第二时钟信号的高电平信号对第一上拉节点PU1进行充电，使其处于高电平。
例如，在另一个示例中，该第一检测输入子电路110还可以实现为只有第一晶体管T1。例如，如图4B所示，第一晶体管T1的栅极配置为和显示 输出端(即第一输入端INPUT1)连接以接收显示输出信号，第一极配置为和第一随机脉冲信号端OE1连接以接收第一随机脉冲信号，第二极配置为和第一上拉节点PU1连接。又例如，如图4C所示，第一晶体管T1的栅极配置为和第一随机脉冲信号端OE1连接以接收第一随机脉冲信号，第一极配置为和显示输出端(即第一输入端INPUT1)连接以接收显示输出信号，第二极配置为和第一上拉节点PU1连接。
第一上拉节点复位子电路120可以实现为第三晶体管T3。第三晶体管T3的栅极配置为和第一复位端RST1连接以接收第一复位信号，第一极配置为和第一上拉节点PU1连接，第二极配置为和第一电压端VGL1连接。第三晶体管T3由于第一复位信号而导通时，将第一上拉节点PU1和第一电压端VGL1电连接，从而可以对第一上拉节点PU1进行复位，使其从高电平下降至低电平。
检测输出子电路130可以实现为第四晶体管T4和第一存储电容C1。第四晶体管T4的栅极配置为和第一上拉节点PU1连接，即受第一上拉节点PU1的电平控制，即当第一上拉节点PU1为高电平时第四晶体管T4导通，当第一上拉节点PU1为低电平时第四晶体管T4截止，第四晶体管T4的第一极配置为和第一时钟信号端CLK1连接以接收第一时钟信号，第二极配置为和检测输出端OUT1连接以输出检测输出信号；第一存储电容C1的第一极和第一上拉节点PU1连接，第二极和检测输出端OUT1连接。在第四晶体管T4导通时，由于第一存储电容C1的自举作用，可以进一步拉高第一上拉节点PU1的电平。
第一上拉节点降噪子电路140可以实现为第五晶体管T5。第五晶体管T5的栅极配置为和第一下拉节点PD1连接，第一极配置为和第一上拉节点PU1连接，第二极配置为和第一电压端VGL1连接。第五晶体管T5由于第一下拉节点PD1处于高电位时导通，将第一上拉节点PU1和第一电压端VGL1连接，从而可以对第一上拉节点PU1下拉以实现降噪。
检测输出降噪子电路150可以实现为第六晶体管T6。第六晶体管T6的栅极配置为和第一下拉节点PD1连接，第一极配置为和检测输出端OUT1连接，第二极配置为和第一电压端VGL1连接。第六晶体管T6由于第一下拉节点PD1处于高电位时导通，将检测输出端OUT1和第一电压端VGL1连接， 从而可以对检测输出端OUT1下拉以实现降噪。
例如，第一下拉子电路160可以实现为第七晶体管T7和第八晶体管T8。第七晶体管T7的栅极与第一极连接，且配置为与第二电压端VGH1连接以接收第二电压信号，第二极配置为与第一下拉节点PD1连接；第八晶体管T8的栅极与第一上拉节点PU1连接，第一极与第一下拉节点PD1连接，第二极配置为与第一电压端VGL1连接以接收第一电压信号。当第一上拉节点PU1处于高电平时第八晶体管T8导通，将第一下拉节点PD1与第一电压端VGL1电连接；通过设置第七晶体管T7和第八晶体管T8的导通电阻，从而使得第八晶体管T8导通时，能够将第一下拉节点PD1的电平拉低。
又例如，如图4D所示，第一下拉子电路160还可以包括第九晶体管T9和第十晶体管T10。第九晶体管T9的栅极和第一极连接，且配置为与第三电压端VGH2连接以接收第三电压信号，第二极与第一下拉节点PD1连接；第十晶体管T10的栅极与第一上拉节点PU1连接，第一极与第一下拉节点PD1连接，第二极配置为与第一电压端VGL1连接以接收第一电压信号。当第一上拉节点PU1处于高电平时第十晶体管T10导通，将第一下拉节点PD1与第一电压端VGL1电连接；通过设置第九晶体管T9和第十晶体管T10导通电阻，从而使得第十晶体管T10导通时，能够将第一下拉节点PD1的电平拉低。在该示例中，引入了第九晶体管T9和第十晶体管T10，且使得第二电压信号和第三电压信号交替为高电平和低电平，从而第七晶体管T7和第八晶体管T8与第九晶体管T9和第十晶体管T10可以交替工作，从而可以减小第一下拉子电路中各个晶体管的应力，从而延长这些晶体管的使用寿命。需要注意的是，该第一下拉子电路还可以实现为反相器，即第一上拉节点为高电平时，第一下拉节点为低电平，反之亦然。
例如，如图5A所示，在本公开实施例的另一个示例中，在图3B所示的示例的基础上，检测子移位寄存器100还包括第二检测输入子电路170、检测输入端INPUT2以及第二复位端RST2。
第二检测输入子电路170配置为和检测输入端INPUT2连接以接收检测输入信号且响应于检测输入信号对第一上拉节点PU1进行充电。例如，第二检测输入子电路170可以与检测输入端INPUT2和第一上拉节点PU1连接，配置为在检测输入端INPUT2输入的信号的控制下，使第一上拉节点PU1和 检测输入端INPUT2电连接或另外提供的高电压端电连接，从而可以使检测输入端INPUT2输入的高电平信号或高电压端输出的高电平信号对第一上拉节点PU1进行充电，以使得第一上拉节点PU1的电压增加以控制检测输出子电路130导通。例如，该检测输入信号可以是上一级检测子移位寄存器100的检测输出信号。例如，该第二检测输入子电路170用于逐行扫描时接收上一级检测子移位寄存器100的输出信号的电路。
例如，如图5B所示，在图4D的基础上，该第二检测输入子电路170可以实现为第十一晶体管T11。第十一晶体管T11的栅极和第一极连接，且配置为和检测输入端INPUT2连接以接收检测输入信号，第二极和第一上拉节点PU1连接。又例如，如图5C所示，第十一晶体管T11的栅极配置为和检测输入端INPUT2连接以接收检测输入信号，第一极配置为和第三时钟信号端CLK3连接以接收第三时钟信号，第二极和第一上拉节点PU1连接。从而当第十一晶体管T11由于检测输入端INPUT2接收到的导通信号(或高电平信号)导通时，使用该导通信号或第三时钟信号端CLK3接收的高电平信号以对第一上拉节点PU1进行充电，使其处于高电平。
例如，如图5B所示，对应于第二检测输入子电路170，该检测子移位寄存器100中的上拉节点复位电路120还包括第十二晶体管T12。第十二晶体管T12的栅极和第二复位端RST2连接以接收第二复位信号，第一极和第一上拉节点PU1连接，第二极和第一电压端VGL1连接以接收第一电压信号。例如，该第十二晶体管T12响应于来自下一级检测子移位寄存器100的检测输出信号作为第二复位信号而导通时，将第一上拉节点PU1和第一电压端VGL1电连接，从而可以对第一上拉节点PU1进行复位，使其从高电平下降至低电平。
该示例的检测子移位寄存器100除了具有随机检测的功能外，还可以具有逐行检测的功能。例如，当检测子移位寄存器100第一随机脉冲信号端OE1没有信号输入时，可以利用该示例的检测子移位寄存器100继续控制对像素电路中的驱动晶体管的阈值电压和迁移率的逐行补偿。
当该检测子移位寄存器100第一随机脉冲信号端OE1正常工作时，该第一复位信号可以将该检测子移位寄存器100的逐行扫描的功能关闭，且该检测子移位寄存器100可以根据显示子移位寄存器200当前具体扫描的行数以 及第一随机脉冲信号的有效电平，对该行进行检测输出信号的输出。例如，第一复位信号可以实现对各级检测子移位寄存器100的第一上拉节点进行复位，从而抑制除当前行外其余各级检测子移位寄存器100的输出，从而实现关闭检测子移位寄存器100的逐行扫描的功能，以消除因逐行扫描产生的扫描线以及解决亮度不均匀的问题。
下面的描述中，均在本示例中的检测子移位寄存器100的结构的基础上进行描述，需要注意的是，检测子移位寄存器100不限于此，还可以是以上示例中的其他结构。
例如，如图5D和图5E所示，在本公开实施例的另一个示例中，在图5B所示的示例的基础上，检测子移位寄存器100的第一检测输入子电路110还包括随机脉冲信号控制子电路(图中未示出)。例如，该随机脉冲信号控制子电路配置为和第一输入端INPUT1(显示输出端)、第一随机脉冲信号端OE1和第二随机脉冲信号端OE2连接以接收显示输出信号、第一随机脉冲信号和第二随机脉冲信号，且响应于显示输出信号、第一随机脉冲信号和第二随机脉冲信号使第一随机脉冲信号和第二随机脉冲信号同时为开启电平。
通过该随机脉冲信号控制子电路对第一随机脉冲信号和第二随机脉冲信号的控制，使得检测子移位寄存器只有在第一随机脉冲信号和第二随机脉冲信号同时为开启电平时可以输出移位寄存器单元的检测输出信号。另一方面，在显示子移位寄存器同时有多级输出时，该随机脉冲信号控制子电路可以根据显示子移位寄存器200当前具体扫描的行数以及第一随机脉冲信号和第二随机脉冲信号的有效电平，对该行进行检测输出信号的输出。
例如，如图5E所示，该随机脉冲信号控制子电路的示例可以实现为第五十一晶体管T51、第五十二晶体管T52、第五十三晶体管T53、第五十四晶体管T54、第五存储电容C5和第六存储电容C6。
例如，在本示例中，如图5D所示，第一晶体管T1的栅极和随机脉冲信号控制子电路的第一输出端H1连接，第一极和第二时钟信号端CLK2连接，第二极和第二晶体管T2的第一极连接；第二晶体管的栅极和随机脉冲信号控制子电路的第二输出端H2连接，第二极和第一上拉节点PU1连接；或者如图5F所示，第一晶体管T1的栅极和随机脉冲信号控制子电路的第二输出 端H2连接，第一极和第二时钟信号端CLK2连接，第二极和第二晶体管T2的第一极连接；第二晶体管的栅极和随机脉冲信号控制子电路的第一输出端H1连接，第二极和第一上拉节点PU1连接。例如，该第一检测输入子电路110还可以只包括第二晶体管T2。例如，如图5G所示，第二晶体管T2的栅极和随机脉冲信号控制子电路的第一输出端H1连接，第一极和随机脉冲信号控制子电路的第二输出端H2连接，第二极和第一上拉节点PU1连接；或者，如图5H所示，第二晶体管T2的栅极和随机脉冲信号控制子电路的第二输出端H2连接，第一极和随机脉冲信号控制子电路的第一输出端H1连接，第二极和第一上拉节点PU1连接。
例如，在本示例中，如图5E所示，第五十一晶体管T51的栅极和第一随机脉冲信号端OE1连接，第一极和第一输入端INPUT1(即显示输出端OUT2)连接，第二极和随机脉冲信号控制子电路的第一输出端H1连接。第五十二晶体管T52的栅极和第二脉冲信号端OE2连接，第一极和第一输入端INPUT1(即显示输出端OUT2)连接，第二极和随机脉冲信号控制子电路的第二输出端H2连接。第五十三晶体管T53的栅极和第一时钟信号端CLK1连接，第一极和随机脉冲信号控制子电路的第一输出端H1连接，第二极和第一电压端VGL1连接。第五十四晶体管T54的栅极和第一时钟信号端CLK1连接，第一极和随机脉冲信号控制子电路的第二输出端H2连接，第二极和第一电压端VGL1连接。第五存储电容C5的第一极和随机脉冲信号控制子电路的第一输出端H1连接，第二极和第一电压端VGL1连接。第六存储电容C6的第一极和随机脉冲信号控制子电路的第二输出端H2连接，第二极和第一电压端VGL1连接。
例如，如图6A所示，在本公开实施例的另一个示例中，在图5A所示的示例的基础上，检测子移位寄存器100还包括防漏电子电路180。
该防漏电子电路180配置为在第一上拉节点PU1的电平的控制下，保持第一上拉节点PU1的高电位。例如，该防漏电子电路180与第四电压端VA、第一上拉节点PU1、第一上拉节点复位子电路120、第一上拉节点降噪子电路150以及第二检测输入子电路170连接，配置为在第一上拉节点PU1的高电平的控制下，使得与第一上拉节点PU1相连的各个晶体管的源极和漏极同时为高电平，从而避免了第一上拉节点PU1的电平因为漏电而降低，以影响 显示质量。
例如，如图6B所示，防漏电子电路180可以实现为第十三晶体管T13。第十三晶体管T13的栅极和第一上拉节点PU1连接，第一极和第四电压端VA连接以接收第四电压信号，第二极和反馈节点OFF连接，从而当第十三晶体管T13由于第一上拉节点PU1的高电平导通时，将反馈节点OFF和第四电压端VA连接，从而可以将反馈节点OFF也提升为高电平。
例如，为了实现防漏电功能，相应地，第一上拉节点复位子电路120、第一上拉节点降噪子电路150以及第二检测输入子电路170可以分别实现为包括两个晶体管的结构。
例如，第二检测输入子电路170包括第十一晶体管T11和第十四晶体管T14。第十一晶体管T11的栅极配置为和检测输入端INPUT2连接以接收检测输入信号，第一极配置为和第三时钟信号端CLK3连接以接收第三时钟信号，第二极和第十四晶体管T14的第一极连接；第十四晶体管T14的栅极和第十一晶体管T11的栅极连接，且配置为和反馈节点OFF连接，第二极和第一上拉节点PU1连接。
第一上拉节点复位子电路120包括第三晶体管T3、第十二晶体管T12、第十五晶体管T15和第十六晶体管T16。第三晶体管T3的栅极配置为和第一复位端连接以接收所述第一复位信号，所述第三晶体管的第一极和所述第十五晶体管T15的第二极连接，且配置为和反馈节点OFF连接，第二极配置为和第一电压端VGL1连接；第十二晶体管T12的栅极和第二复位端RST2连接以接收第二复位信号，第一极和第十六晶体管T16的第二极连接，且配置为和反馈节点OFF连接，第二极和第一电压端VGL1连接以接收第一电压信号；第十五晶体管T15的栅极和第三晶体管T3的栅极连接，第一极和第一上拉节点PU1连接；第十六晶体管T16的栅极和第十二晶体管T12的栅极连接，第一极和第一上拉节点PU1连接。
第一上拉节点降噪子电路包括第五晶体管T5和第十七晶体管T17。第五晶体管T5的栅极配置为和第一下拉节点PD1连接，第一极配置为和第十七晶体管的第二极连接，且配置为和反馈节点OFF连接，第二极配置为和第一电压端VGL1连接；第十七晶体管T17的栅极和第五晶体管T5的栅极连接，第一极和第一上拉节点PU1连接。
例如，第十五晶体管T15和第十六晶体管T16的第一极均和第一上拉节点PU1连接，第二极均与反馈节点OFF连接，因此，当第一上拉节点PU1为高电平时，第十三晶体管导通，将反馈节点OFF和第四电压端VA连接，从而可以将反馈节点OFF也提升为高电平，从而使得第十五晶体管T15和第十六晶体管T16的第一极和第二极同时保持高电平，从而避免了因为与第一上拉节点PU1相连的晶体管漏电而使得第一上拉节点PU1的电平的降低。第十四晶体管T14和第十七晶体管T17的原理一样，在此不再赘述。
本公开实施例的移位寄存器单元的显示子移位寄存器200可以实现为各种适当的寄存器电路，只要能够输出显示输出信号，或还可以更进一步级联。例如，图7A为图2中所示的移位寄存器单元的一种显示子移位寄存器的示意图。如图7A所示，显示子移位寄存器200包括显示输入子电路210、第二上拉节点复位子电路220和显示输出子电路230。
该显示输入子电路210配置为响应于显示输入信号对第二上拉节点PU2进行充电。例如，该显示输入子电路210可以与该显示子移位寄存器200的显示输入端INPUT3和第二上拉节点PU2连接，配置为在显示输入端INPUT3输入的信号的控制下使第二上拉节点PU2和显示输入端INPUT3电连接或另外提供的高电压端电连接，从而可以使显示输入端INPUT3输入的高电平信号或高电压电平端输出的高电平信号对第二上拉节点PU2进行充电，以使得第二上拉节点PU2的电压增加以控制显示输出子电路230导通。
该第二上拉节点复位子电路220配置为响应于第三复位端RST3接收的第三复位信号对第二上拉节点PU2进行复位，以使得第二上拉节点PU2的电压减小(拉低)，从而使得显示输出子电路230不再导通。例如，该第二上拉节点复位子电路220可以配置为和第三复位端RST3连接，从而可以在第三复位端RST3输入的第三复位信号的控制下，使得第二上拉节点PU2和低电平信号或低电压端电连接，该低电压端例如为第一电压端VGL1，从而可以对第二上拉节点PU2进行下拉复位。
显示输出子电路230配置为在第二上拉节点PU2的电平的控制下，将第四时钟信号CLK4输出至显示输出端OUT2，作为该显示子移位寄存器200的输出信号，以驱动例如与该显示输出端OUT2连接的栅线。例如，该显示输出子电路230可以配置为在第二上拉节点PU2的电平的控制下导通，使第 四时钟信号端CLK4和显示输出端OUT2电连接，从而可以将第四时钟信号端CLK4输入的第四时钟信号输出至显示输出端OUT2。
例如，如图7B所示，在本公开实施例的另一个示例中，在图7A所示的示例的基础上，显示子移位寄存器200还包括第二上拉节点降噪子电路240、第二输出降噪子电路250和第二下拉子电路260。
第二上拉节点降噪子电路240配置为在第二下拉节点PD2的电平的控制下，对第二上拉节点PU2进行降噪。例如，该第二上拉节点降噪电路240可以配置为和第一电压端VGL1连接，以在第二下拉节点PD2的电平的控制下，使第二上拉节点PU2和第一电压端VGL1电连接，从而对第二上拉节点PU2进行下拉降噪。
显示输出降噪子电路250配置在第二下拉节点PD2的电平的控制下，对显示输出端OUT2进行降噪。例如，该第二输出降噪子电路250可以配置为在第二下拉节点PD2的电平的控制下，使显示输出端OUT2和第一电压端VGL1电连接，从而对显示输出端OUT2进行下拉降噪。
第二下拉子电路260配置为在第二上拉节点PU2的电平的控制下，对第二下拉节点PD2的电平进行控制。例如，该第二下拉子电路260可以连接第一电压端VGL1、第二电压端VGH1、第二上拉节点PU2和第二下拉节点PD2，以在第二上拉节点PU2的电平的控制下，使第二下拉节点PD2和第一电压端VGL1电连接，从而对第二下拉节点PD2的电平进行下拉控制，使得当第二上拉节点PU2处于高电位时，第二下拉节点PD2处于低电位。如图所示，该第一下拉子电路160可以在第二电压端VGH1的电平的控制下，使第二下拉节点PD2和第二电压端VGH1电连接，从而使第二下拉节点PD2处于高电位。
例如，图7B中所示的显示子移位寄存器200在一个示例中可以具体实现为图7C所示的电路结构。在下面的说明中以各晶体管为N型晶体管为例进行说明，但并不构成对本公开实施例的限制。
显示输入子电路210可以实现为第二十一晶体管T21。第二十一晶体管T21的栅极和第一极连接，且配置为和显示输入端INPUT3连接以接收输入信号，第二极配置为和第二上拉节点PU2连接以对第二上拉节点PU2进行充电。
第二上拉节点复位子电路220可以实现为第二十二晶体管T22。第二十二晶体管T22的栅极配置为和第三复位端RST3连接以接收复位信号，第一极配置为和第二上拉节点PU2连接以对第二上拉节点PU2进行复位，第二极配置为和第一电压端VGL1连接以接收第一电压。
显示输出子电路230可以实现为包括第二十三晶体管T23和第二存储电容C2。第二十三晶体管T23的栅极配置为和第二上拉节点PU2连接，即受第二上拉节点PU2的电平控制，即当第二上拉节点PU2为高电平时第二十三晶体管T23导通，当第二上拉节点PU2为低电平时第二十三晶体管T23截止，第一极配置为和第四时钟信号端CLK4连接以接收时钟信号，第二极配置为和显示输出端OUT2连接；第二存储电容C2的第一极配置为和第二十三晶体管T23的栅极连接，第二极和第二十三晶体管T23的第二极连接。在第二十三晶体管T23导通时，由于第二存储电容C2的自举作用，可以进一步拉高第二上拉节点PU2的电平。
第二上拉节点降噪子电路240可以实现为第二十四晶体管T24。第二十四晶体管T24的栅极配置为和第二下拉节点PD2连接，第一极配置为和第二上拉节点PU2连接以对第二上拉节点PU2进行降噪，第二极配置为和第一电压端VGL1连接以接收第一电压。
第二输出降噪子电路250可以实现为第二十五晶体管T25。第二十五晶体管T25的栅极配置为和第二下拉节点PD2连接，第一极配置为和显示输出端OUT2连接，第二极配置为和第一电压端VG1L连接以接收第一电压。
第二下拉子电路260可以实现为第二十六晶体管T26和第二十七晶体管T27。第二十六晶体管T26的栅极与第一极连接，且配置为与第二电压端VGH1连接以接收第二电压信号，第二极配置为与第二下拉节点PD2连接；第二十七晶体管T27的栅极与第二上拉节点PU2连接，第一极与第二下拉节点PD2连接，第二极配置为与第一电压端VGL1连接以接收第一电压信号。当第二上拉节点PU2处于高电平时第二十七晶体管T27导通，将第二下拉节点PD2与第一电压端VGL1电连接；通过设置第二十六晶体管T26和第二十七晶体管T27的导通电阻，从而使得第二十七晶体管T27导通时，能够将第二下拉节点PD2的电平拉低。
又例如，第二下拉子电路260还可以包括第二十八晶体管T28和第二十 九晶体管T29。第二十八晶体管T28的栅极和第一极连接，且配置为与第三电压端VGH2连接以接收第三电压信号，第二极与第二下拉节点PD2连接；第二十九晶体管T29的栅极与第二上拉节点PU2连接，第一极与第二下拉节点PD2连接，第二极配置为与第一电压端VGL1连接以接收第一电压信号。当第二上拉节点PU2处于高电平时第二十九晶体管T29导通，将第二下拉节点PD2与第一电压端VGL1电连接；通过设置第二十八晶体管T28和第二十九晶体管T29的导通电阻，从而使得第二十九晶体管T29导通时，能够将第二下拉节点PD2的电平拉低。在该示例中，引入了第二十八晶体管T28和第二十九晶体管T29，且使得第二电压信号和第三电压信号交替为高电平和低电平，从而第第二十六晶体管T26和第第二十七晶体管T27与第第二十八晶体管T28和第第二十九晶体管T29可以交替工作，从而可以减小第二下拉子电路中各个晶体管的应力，从而延长这些晶体管的使用寿命。需要注意的是，第二下拉子电路可以实现为反相器，即当第二上拉节点为高电平时，第二下拉节点为低电平，反之亦然。
图8A为本公开一实施例提供的另一种移位寄存器单元的示意图。如图8A所示，在图2所示的实施例的基础上，该移位寄存器单元10还包括输出控制电路300。
如图8A所示，该输出控制电路300与检测子移位寄存器100的第一上拉节点PU1和第一下拉节点PD1以及与显示子移位寄存器200的第二上拉节点PU2和第二下拉节点PD2电连接，且配置为当将第一上拉节点PU1和第二上拉节点PU2之一为有效电平(高电平)时则拉低另一个。例如，当第一上拉节点PU1为高电平时，则拉低第二上拉节点PU2的电平，或者相反，由此以保证在检测输出期间检测子移位寄存器100的输出信号不受显示子移位寄存器200的输出的影响，在显示输出期间显示子移位寄存器200的输出信号不受检测子移位寄存器100的影响。例如，该输出控制电路300可以将检测子移位寄存器100的输出端和显示子移位寄存器200的输出端直接相连，以输出复合波形。
如图8B所示，在图8A的基础上，输出控制电路301还可以通过由检测子移位寄存器100的检测输出端OUT1的检测输出信号以及第二上拉节点PU2和第二下拉节点PD2控制的方式实现，其具体连接方式以及工作原理将 在下面进行介绍。
图9A为图8A中所示的一种输出控制电路的示意图。如图9A所示，该输出控制电路300包括检测输出控制子电路310和显示输出控制子电路320。
该检测输出控制子电路310配置为在第一上拉节点PU1的电平的控制下，对第二上拉节点PU2和第二下拉节点PD2的电平进行控制。例如，该检测输出控制子电路310和第二上拉节点PU2、第二下拉节点PD2以及第一电压端VGL1连接，配置为在第一上拉节点PU1的电平的控制下，使得第二上拉节点PU2和第二下拉节点PD2与第一电压端VGL1连接，从而可以对第二上拉节点PU2和第二下拉节点PD2进行下拉，以避免在检测子移位寄存器100输出期间显示子移位寄存器200进行输出。
该显示输出控制子电路320配置为在第二上拉节点PU2的电平的控制下，对第一上拉节点PU1和第一下拉节点PD1的电平进行控制。例如，该显示输出控制子电路310和第一上拉节点PU1、第一下拉节点PD1以及第一电压端VGL1连接，配置为在第二上拉节点PU2的电平的控制下，使得第一上拉节点PU1和第一下拉节点PD1与第一电压端VGL1连接，从而可以对第一上拉节点PU1和第一下拉节点PD1进行下拉，以避免在显示子移位寄存器100输出期间检测子移位寄存器100进行输出。
例如，图9A中所示的输出控制电路300在一个示例中可以具体实现为图9B所示的电路结构。在下面的说明中以各晶体管为N型晶体管为例进行说明，但并不构成对本公开实施例的限制。
检测输出控制子电路310可以实现为第三十一晶体管T31和第三十二晶体管T32。第三十一晶体管T31的栅极配置为和第一上拉节点PU1连接，第一极配置为和第二下拉节点PD2连接，第二极配置为和第一电压端VGL1连接；第三十二晶体管T32的栅极配置为和第一上拉节点PU1连接，第一极配置为和第一电压端VGL1连接，第二极配置为和第二上拉节点PU2连接。
显示输出控制子电路320可以实现为第三十三晶体管T33和第三十四晶体管T34。第三十三晶体管T33的栅极配置为和第二上拉节点PU2连接，第一极配置为和第一下拉节点PD1连接，第二极配置为和第一电压端VGL1连接；第三十四晶体管T34的栅极配置为和第二上拉节点PU2连接，第一极配置为和第一电压端VGL1连接，第二极配置为和第一上拉节点PU1连接。
该输出控制电路300可以将检测子移位寄存器100的输出端和显示子移位寄存器200的输出端直接相连，以输出复合波形，一同驱动例如与该移位寄存器10相连的栅线。同时该输出控制电路300使得在显示期间只输出显示输出信号，在间隔期间，只输出检测输出信号，并且保证了在其中一个子移位寄存器输出时，另一个子移位寄存器不会有干扰。
图8A中所示的移位寄存器单元10在一个示例中可以具体实现为图9C所示的电路结构。例如，检测子移位寄存器100和显示子移位寄存器200可以采用本公开任一实施例所述的子移位寄存器，在此不再赘述。例如，在本示例中，显示子移位寄存器200可以采用图7C所示的电路结构，检测子移位寄存器100可以采用图5B所示的电路结构，输出控制电路300可以采用9B所示的电路结构，在图9C中具体实现为第三十一晶体管T31、第三十二晶体管T32、第三十三晶体管T33和第三十四晶体管T34，其具体连接方式和工作原理如上述实施例所述，在此不再赘述。
例如，如图9C所示，显示子移位寄存器200的显示输出端OUT2与检测子移位寄存器100的第一输入端INPUT1以及检测输出端OUT1连接，以在输出控制电路300的控制下输出复合波形，以控制如图1D中所示的与栅极扫描线SCAN相连的像素电路中的开关晶体管T0和感测晶体管S0的栅极。
图8B中所示的移位寄存器单元10在一个示例中还可以具体实现为图9D所示的电路结构。例如，检测子移位寄存器100和显示子移位寄存器200可以采用本公开任一实施例所述的子移位寄存器，在此不再赘述。例如，在本示例中，显示子移位寄存器200可以采用图7C所示的电路结构，检测子移位寄存器100可以采用图5B所示的电路结构。如图9D所示，输出控制电路300通过第三十五晶体管T35、第三十六晶体管T36和第三十七晶体管T37实现。
如图9D所示，第三十五晶体管T35的栅极配置为和检测输出端OUT1连接以接收检测输出信号，第一极配置为和第二下拉节点PD2连接，第二极配置为和第一电压端VGL1连接；第三十六晶体管T36的栅极配置为和检测输出端OUT1连接以接收检测输出信号，第一极配置为和第二上拉节点PU2连接，第二极配置为和第一电压端VGL1连接；第三十七晶体管T37的栅极 配置为和检测输出端OUT1连接以接收检测输出信号，第一极配置为和第五时钟信号端连接以接收第五时钟信号，第二极配置为和输出复合输出端OUT4以及显示输出端OUT2连接。
该移位寄存器10的工作原理包括：当检测输出端OUT1输出高电平信号时，第三十五晶体管T35和第三十六晶体管T36导通，显示子移位寄存器200的第二上拉节点PU2和第二下拉节点PD2与第一电压端VGL1连接，被下拉至低电平，从而显示输出端OUT2_N被拉低至低电位，从而显示子移位寄存器200不影响检测子移位寄存器100的正常工作；同时，第三十七晶体管T37也导通，从而输出第五时钟信号的高电平至输出复合输出端OUT4。当显示输出端OUT2输出高电平时，检测子移位寄存器的第一下拉节点PD1为高电位，因此检测输出端OUT1输出为低电位，从而第三十七晶体管T37截止，输出复合输出端OUT4仅输出显示输出端OUT2输出的显示输出信号。
图10为本公开一实施例提供的另一种移位寄存器单元的示意图。如图10所示，在图2所示的实施例的基础上，该移位寄存器单元10还包括逻辑或电路400。
如图10所示，该逻辑或电路400与显示子移位寄存器200的显示输出端OUT2和检测子移位寄存器100的检测输出端OUT1连接，且配置为将显示输出信号和检测输出信号进行或运算以得到复合输出信号。
该逻辑或电路400和输出控制电路300的实现的功能类似，也可以将检测子移位寄存器100的输出信号和显示子移位寄存器200的输出信号结合起来，一同驱动例如与该移位寄存器10相连的栅线。
图11A为图10中所示的一种逻辑或电路的示意图。如图10所示，该逻辑或电路400包括第一逻辑或输入子电路410、第二逻辑或输入子电路420、第一输出控制子电路430、第二输出控制子电路440、第一节点降噪子电路450、第二节点降噪子电路460、输出降噪控制子电路470和输出降噪子电路480。
第一逻辑或输入子电路410配置为响应于检测输出信号对第一节点N1进行充电。例如，该第一逻辑或输入子电路410可以与检测输出端OUT1和第一节点N1连接，且配置为在检测输出端OUT1输出的检测输出信号的控制下，使第一节点N1和检测输出端电连接，从而可以使检测输出端OUT1 输入的高电平信号对第一节点N1进行充电，以使得第一节点N1的电压增加以控制第一输出控制子电路430导通。
第二逻辑或输入子电路420配置为响应于显示输出信号对第二节点N2进行充电。例如，第二逻辑或输入子电路420可以与显示输出端OUT2和第二节点N2连接，且配置为在显示输出端OUT2输出的显示输出信号的控制下，使第二节点N2和显示输出端OUT2电连接，从而可以使显示输出端OUT2输入的高电平信号对第二节点N2进行充电，以使得第二节点N2的电压增加以控制第二输出控制子电路440导通。
第一输出控制子电路430配置为在第一节点N1的电平的控制下，输出检测输出信号。例如，该第一输出控制子电路430可以配置为在第一节点N1的电平的控制下导通，使检测输出端OUT1和逻辑或输出端OUT3电连接，从而可以将检测输出端OUT1输出的检测输出信号输出至逻辑或输出端OUT3。
第二输出控制子电路440配置为在第二节点N2的电平的控制下，输出显示输出信号。例如，该第二输出控制子电路440可以配置为在第二节点N2的电平的控制下导通，使显示输出端OUT2和逻辑或输出端OUT3电连接，从而可以将显示输出端OUT2输出的显示输出信号输出至逻辑或输出端OUT3。
第一节点降噪电路450配置为在显示输出信号的电平的控制下，对第一节点N1进行降噪。例如，该第一节点降噪电路450可以配置为和第五电压端VGL2连接，以在显示输出信号的电平的控制下，使第一节点N1和第五电压端VGL2电连接，从而对第一节点N1进行下拉降噪。
第二节点降噪电路460配置为在检测输出信号的电平的控制下，对第二节点N2进行降噪。例如，该第二节点降噪电路460可以配置为和第五电压端VGL2连接，以在检测输出信号的电平的控制下，使第二节点N2和第五电压端VGL2电连接，从而对第二节点N2进行下拉降噪。
输出降噪控制子电路470配置为在显示输出信号和检测输出信号的电平的控制下对第三节点N3的电平进行控制。例如，该输出降噪控制子电路470配置为和第一电压端VGL1、第二电压端VGH1、第三电压端VGH2、检测输出端OUT1、显示输出端OUT2以及第三节点N3连接，配置为在显示输 出信号和检测输出信号的其中之一的高电平的控制下，使得第三节点N3与第一电压端VGL1连接，使其处于低电位，或者在显示输出信号和检测输出信号的同时为低电平的控制下，使得第三节点N3与第二电压端VGH1或第三电压端VGH2的其中之一连接，从而使其处于高电位。
输出降噪子电路480配置为在第三节点N3的电平的控制下，对逻辑或输出端OUT3进行降噪。例如，输出降噪子电路480与第三节点N3、第五电压端VGL2、接地端GND以及逻辑或输出端OUT3连接，配置为在第三节点N3的电平的控制下，使得逻辑或输出端OUT3与第五电压端VGL2连接，从而对逻辑或输出端OUT3进行下拉降噪。
例如，图11A中所示的逻辑或电路400在一个示例中可以具体实现为图11B所示的电路结构。在下面的说明中以各晶体管为N型晶体管为例进行说明，但并不构成对本公开实施例的限制。
第一逻辑或输入子电路410可以实现为第四十一晶体管T41。第四十一晶体管T41的栅极和第一极连接，且配置为和检测输出端OUT1连接以接收检测输出信号，第二极配置为和第一节点N1连接。
第一输出控制子电路430可以实现为第四十二晶体管T42和第三存储电容C3。第四十二晶体管T42的栅极和第一节点N1连接，第一极和检测输出端OUT1连接以接收检测输出信号，第二极和第三存储电容C3的第一极连接；第三存储电容C3的第二极和第一节点N1连接。
第一节点降噪子电路450可以实现为第四十三晶体管T43。例如，第四十三晶体管T43的栅极与显示输出端OUT2连接以接收显示输出信号，第一极与第一节点N1连接，第二极与第五电压端VGL2连接以接收第五电压信号。
第二逻辑或输入子电路420可以实现为第四十四晶体管T44。例如，第四十四晶体管T44的栅极和第一极连接，且配置为和显示输出端OUT2连接以接收显示输出信号，第二极配置为和第二节点N2连接。
第二输出控制子电路440可以实现为第四十五晶体管T45和第四存储电容C4。第四十五晶体管T45的栅极和第二节点N2连接，第一极和显示输出端OUT2连接以接收显示输出信号，第二极和第四存储电容C4的第一极连接；第四存储电容C4的第二极和第二节点N2连接。
第二节点降噪子电路460第四十六晶体管T46。例如，第四十六晶体管T46的栅极与检测输出端OUT1连接以接收检测输出信号，第一极与第二节点N2连接，第二极与第五电压端VGL2连接以接收第五电压信号。
输出降噪控制子电路470可以实现为第四十七晶体管T47、第四十八晶体管T48、第四十九晶体管T49和第五十晶体管T50。例如，第四十七晶体管T47的栅极和第一极连接，且配置为和第二电压端VGH1连接，第二极和第三节点N3连接；第四十八晶体管T48的栅极和第一极连接，且配置为和第三电压端VGH2连接，第二极配置为和第三节点N3连接；第四十九晶体管T49的栅极和检测输出端OUT1连接以接收检测输出信号，第一极和第三节点N3连接，第二极和第一电压端VGL1连接；第五十晶体管T50的栅极和显示输出端OUT2连接以接收显示输出信号，第一极和第三节点N3连接，第二极和第一电压端VGL1连接。
输出降噪子电路480可以实现为第五十一晶体管T51以及第一电阻R1和第五存储电容C5。例如，第五十一晶体管T51的栅极和第三节点连接N3，第一极和逻辑或输出端OUT3连接，第二极和第五电压端VGL2连接以接收第五电压信号；第一电阻R1的第一端和逻辑或输出端OUT3连接，第二端和第五存储电容C5的第一极连接；第五存储电容C5的第二极和接地端GND连接。需要说明的是，第五电压端VGL2例如保持输入直流低电平信号，将该直流低电平称为第五电压。以下各实施例与此相同，不再赘述。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
另外，在本公开的实施例中的晶体管均以N型晶体管为例进行说明，此时，晶体管的第一极是漏极，第二极是源极。需要说明的是，本公开包括但不限于此。例如，本公开的实施例提供的移位寄存器单元中的一个或多个晶体管也可以采用P型晶体管，此时，晶体管第一极是源极，第二极是漏极，只需将选定类型的晶体管的各极的极性按照本公开的实施例中的相应晶体管 的各极的极性相应连接即可。
本公开的实施例提供一种栅极驱动电路20，如图12A所示，该栅极驱动电路20包括多个级联的移位寄存器单元10。例如，该移位寄存器单元10可以采用上述实施例中提供的任一移位寄存器单元。例如，每个移位寄存器单元10包括检测子移位寄存器单元100和显示子移位寄存器单元200。例如，每个检测子移位寄存器单元100的第一输入端INPUT1和显示子移位寄存器单元200的显示输出端OUT2连接。该栅极驱动电路20可以采用与薄膜晶体管同样制程的工艺直接集成在显示装置的阵列基板上，实现逐行扫描驱动功能。例如，在本示例中，显示子移位寄存器200可以采用图7C中的电路结构，检测子移位寄存器100可以采用图4D中的电路结构。
例如，栅极驱动电路20还包括第一随机脉冲信号线OEA和总复位线TRST。各级检测子移位寄存器单元100的第一随机脉冲信号端OE1与第一随机脉冲信号线OEA连接；各级检测子移位寄存器单元100的第一复位端RST1与总复位线TRST连接。
例如，如图12A所示，除最后一级显示子移位寄存器单元200外，其余各级显示子移位寄存器单元200的第三复位端RST3和下一级显示子移位寄存器单元200的显示输出端OUT2连接；除第一级显示子移位寄存器单元200外，其余各级显示子移位寄存器单元200的显示输入端INPUT3和上一级的上级显示子移位寄存器单元200的显示输出端OUT2连接。
需要说明的是，在本公开的实施例中，一个移位寄存器单元B是另一个移位寄存器单元A的下级移位寄存器单元表示：移位寄存器单元B输出的栅极扫描信号在时序上晚于移位寄存器单元A输出的栅极扫描信号。相应地，一个移位寄存器单元B是另一个移位寄存器单元A的上级移位寄存器单元表示：移位寄存器单元B输出的栅极扫描信号在时序上早于移位寄存器单元A输出的栅极扫描信号。以下各实施例与此相同，不再赘述。
例如，栅极驱动电路20还包括第一时钟信号线CLKA和第二时钟信号线CLKB。所述第一时钟信号线CLKA和第2n-1(n为大于0的整数)级显示子移位寄存器单元200的时钟信号端CLK4连接；所述第二时钟信号线CLKB和第2n级显示子移位寄存器单元200的时钟信号端CLK4连接。需要说明的是，本公开的实施例包括但不限于上述连接方式，例如还可以采用： 第一时钟信号线CLKA和第2n级显示子移位寄存器单元200的时钟信号端CLK4连接，第二时钟信号线CLKB和第2n-1级显示子移位寄存器单元200的时钟信号端CLK4连接。
例如，本公开一实施例提供的栅极驱动电路20还包括第三时钟信号线CLKC、第四时钟信号线CLKD和第五时钟信号线CLKE。所述第三时钟信号线CLKC和第2n-1级检测子移位寄存器单元100的时钟信号端CLK1连接；所述第四时钟信号线CLKD和第2n级检测子移位寄存器单元100的时钟信号端CLK1连接，所述第五时钟信号线CLKE与各级检测子移位寄存器100的第二时钟信号端CLK2连接以输入第二时钟信号。
需要说明的是，图12A中所示的OUT1_N-1和OUT2_N-1分别表示第N-1级(N为大于1的整数)检测子移位寄存器单元100和显示子移位寄存器单元200的输出端，OUT1_N和OUT2_N分别表示第N级检测子移位寄存器单元100和显示子移位寄存器单元200的输出端，OUT1_N+1和OUT_N+1分别表示第N+1级检测子移位寄存器单元100和显示子移位寄存器单元200的输出端。以下各实施例中的附图标记与此类似，不再赘述。
例如，第一级显示子移位寄存器单元的显示输入端INPUT1可以被配置为接收触发信号STV，最后一级显示子移位寄存器单元200的第三复位端RST3可以被配置为接收复位信号RESET，触发信号STV和复位信号RESET在图12A中未示出。
例如，如图12A所示，该栅极驱动电路20还可以包括时序控制器500。例如，该时序控制器500可以被配置为和第一时钟信号线CLKA、第二时钟信号线CLKB、第三时钟信号线CLKC、第四时钟信号线CLKD、第五时钟信号线CLKE、总复位线TRST以及第一随机脉冲信号线OEA连接，以向各级显示子移位寄存器单元200和检测子移位寄存器单元100提供时钟信号、第一随机脉冲信号和第一复位信号。时序控制器500还可以被配置为提供触发信号STV以及复位信号RESET。
该栅极驱动电路20中的检测子移位寄存器100不具备逐行扫描功能，仅通过第一随机脉冲信号和与其相连的显示子移位寄存器的检测输出信号决定该检测子移位寄存器100的检测输出信号的输出。
例如，图12B示出了另一种栅极驱动电路20的示意图。该栅极驱动电 路20与图12A所示的栅极驱动电路的区别在于各级检测子移位寄存器100的检测输入端INPUT2和检测输出端OUT1的连接方式不同。例如，在本示例中，显示子移位寄存器200可以采用图7C中的电路结构，检测子移位寄存器100可以采用图5B中的电路结构。
例如，除最后一级检测子移位寄存器单元100外，其余各级检测子移位寄存器单元100的第二复位端RST2和下一级检测子移位寄存器单元100的检测输出端OUT1连接；除第一级检测子移位寄存器单元100外，其余各级检测子移位寄存器单元100的检测输入端INPUT2和上一级检测子移位寄存器单元100的检测输出端OUT1连接。在本示例中，第一随机脉冲信号端OE1和第一复位端RST1的连接方式与图12A所示的连接方式相同，在此不再赘述。
本示例中，其余部分的连接方式与图12A中所示的连接方式相同，在此不再赘述。本示例中的栅极驱动电路20，一方面，在实现随机检测功能时，可以通过第一复位信号将逐行扫描功能关闭，以避免因逐行扫描而产生扫描线以及亮度不均匀的问题；另一方面，在第一随机脉冲信号不工作时，还可以通过逐行扫描功能对像素电路中的驱动晶体管的阈值电压和迁移率进行补偿，以提高显示质量。该示例中的随机检测功能和逐行扫描功能可以根据需要切换。例如，除了通过总复位线TRST的控制外，还可以通过切换电路等方式实现，在此不再赘述。
例如，图12C示出了另一种栅极驱动电路20的示意图。该栅极驱动电路20与图12B所示的栅极驱动电路的区别在于各级显示子移位寄存器100第四时钟信号端CLK4、显示输入端INPIT3以及第三复位端RST3的连接方式不同。例如，在本示例中，显示子移位寄存器200可以采用图7C中的电路结构，检测子移位寄存器100可以采用图5D和图5E中所示的电路结构。
例如，如图12C所示，除最后两级显示子移位寄存器单元外，其余各级显示子移位寄存器单元的第三复位端RST3和与其相隔一级的下级显示子移位寄存器200的显示输出端OUT2连接。除第一级和第二级显示子移位寄存器单元外，其余各级显示子移位寄存器200的显示输入端INPUT3和与其相隔一级的上级显示子移位寄存器200的显示输出端OUT2连接。需要注意的是，不限于此，例如其连接方式还可以是除最后三级显示子移位寄存器200 外，其余各级显示子移位寄存器200的第三复位端RST3和与其相隔两级的下级显示子移位寄存器200的显示输出端OUT2连接。除第一级和第二级显示子移位寄存器单元外，其余各级显示子移位寄存器200的显示输入端INPUT3和与其相隔一级的上级显示子移位寄存器200的显示输出端OUT2连接。
例如，如图12C所示，该栅极驱动电路20还包括时钟控制器500。例如，该时钟控制器500包括第一时钟信号线CLKA、第二时钟信号线CLKB、第六时钟信号线CLKF和第七时钟信号线CLKG。例如，在本示例中，第一时钟信号线CLKA例如和第4n-3(n为大于0的整数)级显示子移位寄存器的时钟信号端连CLK4连接；第二时钟信号线CLKB例如和第4n-2级显示子移位寄存器200的时钟信号端CLK4连接；第六时钟信号线CLK3例如和第4n-1级显示子移位寄存器200的第四时钟信号端CLK4连接；第四时钟信号线CLK4例如和第4n级显示子移位寄存器200的第四时钟信号端CLK4连接。
该时钟控制器500还包括第二随机脉冲信号线(图中未示出)。例如，该第二随机脉冲信号线与检测子移位寄存器100的第二随机脉冲信号端(图中未示出)连接，随机脉冲信号线OEA与检测子移位寄存器100的第一随机脉冲信号端OE1连接，关于检测子移位寄存器100的其他端口的连接方式与图12A和图12B中所示的连接方式相同，在此不再赘述。
需要说明的是，本公开的实施例中提供的栅极驱动电路20还可以包括六条、八条等更多条时钟信号线，本公开的实施例对此不作限定。
本示例中的栅极驱动电路除了具有上述实施例中的栅极驱动电路的效果外，还可以保证在多级显示子移位寄存器同时输出的情况下，只保证其中一级检测子移位寄存器进行输出，以避免因逐行扫描而产生扫描线以及亮度不均匀的问题。
下面结合图13A所示的信号时序图，对图12A中所示的栅极驱动电路20中显示子移位寄存器部分的工作原理进行说明。例如，在本示例中，结合图13A所示的信号时序图，对图7C中所示的显示子移位寄存器200的工作原理进行说明，在图13A所示的第一阶段1、第二阶段2以及第三阶段3共三个阶段中，该显示子移位寄存器200可以分别进行如下操作。
第一阶段，第N级显示子移位寄存器单元200的显示输入端INPUT3接受第N-1级提供的高电平信号作为显示输入信号，因此在该显示输入信号的控制下，该显示输入信号的高电平对该移位寄存器单元200的第二上拉节点PU2_N进行充电，使得第二上拉节点PU2_N的电位充电至第一高电平；第二时钟信号线CLKB提供低电平信号，由于第N级显示子移位寄存器单元200的时钟信号端CLK4和第二时钟信号线CLKB连接，所以在此阶段，第N级显示子移位寄存器单元200的时钟信号端CLK4被输入低电平信号；又由于第N级显示子移位寄存器单元200的第二上拉节点PU2_N为第一高电平，所以在第二上拉节点PU2_N高电平的控制下，时钟信号端CLK4输入的低电平输出至第N级显示子移位寄存器单元200的显示输出端OUT2_N，由此其显示输出信号为低电平。
第二阶段，第一时钟信号线CLKA提供低电平信号，第二时钟信号线CLKB提供高电平信号，所以在此阶段显示子移位寄存器单元200的时钟信号端CLK4输入高电平信号；又由于第N级显示子移位寄存器单元200的第二上拉节点PU2_N为高电平，所以在第二上拉节点PU2_N的高电平的控制下，时钟信号端CLK4输入的高电平输出至第N级显示子移位寄存器单元200输出端OUT2_N，由此其显示输出信号为高电平。同时，第二上拉节点PU2_N由于电容的自举效应被进一步充电至第二高电平。而且，该第N级显示子移位寄存器单元200输出端OUT_N输出的高电平作为第N+1级显示子移位寄存器单元200的显示输入信号，从而第N+1级显示子移位寄存器单元200的第二上拉节点PU2_N+1被上拉至第一高电平，第N+1级显示子移位寄存器单元200的输出端OUT2_N+1输出第一时钟信号线CLKA提供的低电平。
第三阶段，第一时钟信号线CLKA提供高电平信号，所以在此阶段显示子移位寄存器单元200的时钟信号端CLK4输入高电平信号；又由于第N+1级显示子移位寄存器单元200的第二上拉节点PU2_N+1为高电平，所以在第二上拉节点PU2_N+1的高电平的控制下，时钟信号端CLK4输入的高电平输出至第N+1级显示子移位寄存器单元200输出端OUT_N+1，同时，第二上拉节点PU2_N+1由于电容的自举效应被充电至第二高电平。由于第N+1级显示子移位寄存器单元200输出端OUT_N+1连接第N级显示子移位寄存器单元200的第三复位端RST3，因此，在第N+1级显示子移位寄存器单元 200输出端OUT_N+1输出的高电平的控制下，对第N级显示子移位寄存器单元200的第二上拉节点PU2_N进行复位，将其下拉至低电平，从而第二下拉节点PD2_N被上拉至高电平，使得第N级的显示输出端OUT_N与第一电压端VGL1相连，从而其显示输出信号被下拉至低电平。
需要说明的是，图13A中所示的信号时序图的电位的高低仅是示意性的，不代表真实电位值或相对比例，对应于上述示例，高电平信号对应于N型晶体管的开启信号，而低电平信号对应于N型晶体管为截止信号，由此可以控制显示面板中采用N型晶体管作为开关晶体管的像素电路的操作。
下面结合图13B所示的信号时序图，对图12A中所示的栅极驱动电路20中检测子移位寄存器部分的工作原理进行说明。例如，在本示例中，结合图13B所示的信号时序图，对图4D中所示的检测子移位寄存器100的工作原理进行说明，在图13B所示的第一阶段1、第二阶段2以及第三阶段3共三个阶段中，该检测子移位寄存器可以分别进行如下操作。
第一阶段，随机脉冲端输入高电平信号，第N级显示子移位寄存器的显示输出端OUT2_N也输出高电平信号，第N级检测子移位寄存器100的第一输入端INPUT1_N与第N级显示子移位寄存器的显示输出端OUT2_N连接，因此第N级检测子移位寄存器100的第一输入端INPUT1_N输入高电平信号；在此阶段，第二时钟信号端CLK2输入高电平信号，因此，在随机脉冲信号和显示输出信号的高电平的控制下，使得第一上拉节点PU1_N与第二时钟信号端CLK2相连，使得该第一上拉节点PU1_N被充电至第一高电平；在此阶段，第四时钟信号线CLKD提供低电平信号，由于第N级检测子移位寄存器单元100的时钟信号端CLK1和第四时钟信号线CLKD连接，所以在此阶段，第N级检测子移位寄存器单元100的时钟信号端CLK1输入低电平信号；又由于第N级检测子移位寄存器单元100的第一上拉节点PU1_N为第一高电平，所以在第一上拉节点PU1_N高电平的控制下，时钟信号端CLK1输入的低电平输出至第N级检测子移位寄存器单元100的检测输出端OUT1_N。
第二阶段，第四时钟信号线CLKD提供高电平信号，所以在此阶段检测子移位寄存器单元100的时钟信号端CLK1输入高电平信号；又由于第N级检测子移位寄存器单元100的第一上拉节点PU1_N为第一高电平，所以在 第一上拉节点PU1_N的高电平的控制下，时钟信号端CLK1输入的高电平输出至第N级检测子移位寄存器单元100输出端OUT1_N，同时，第一上拉节点PU1_N由于电容的自举效应被充电至第二高电平。例如，在图12B中所示的栅极驱动电路中，在此阶段第N+1级检测子移位寄存器100的第一上拉节点PU_N+1被充电至第一高电平。
第三阶段，总复位线TRST提供高电平信号，由于各级检测子移位寄存器100的第一复位端RST1与该总复位线连接，因此各级检测子移位寄存器100的第一复位端RST1都被输入高电平，所以各级检测子移位寄存器100的第一上拉节点PU1被下拉至低电平，从而第一下拉节点PD1被上拉至高电平，从而各级的检测输出端OUT1被下拉至低电平。因此，图12B中所示的检测子移位寄存器的逐行扫描的功能被关闭，避免了因逐行扫描而产生扫描线以及亮度不均匀的问题。
图12B中所示的栅极驱动电路20的工作原理与图12A中所示的栅极驱动电路20的工作原理基本相同，区别在于图12B中所示的栅极驱动电路20中的检测子移位寄存器还具有逐行扫描的功能，其具体的工作原理与显示子移位寄存器的工作原理类似，在此不再赘述。
图13C为图11B中所示的逻辑或电路将栅极驱动电路20的显示输出信号和检测输出信号复合输出的工作原理时序图。
第一阶段，显示输出端OUT2输出高电平的显示输出信号，检测输出端OUT1输出低电平的检测输出信号，从而在显示输出信号的高电平的控制下，使得第二节点N2和显示输出端OUT2连接，使得第二节点N2被充电至高电平；在第二节点N2的高电平的控制下，使得逻辑或输出端OUT3与显示输出端OUT2连接，从而逻辑或输出端OUT3输出显示输出信号的高电平。
第二阶段，显示输出端OUT2输出低电平的显示输出信号，检测输出端OUT1输出低电平的检测输出信号，第二电压端VGH1输入高电平信号，第三电压端VGH2输入低电平信号，从而在第二电压端VGH1的高电平的控制下，使得第三节点N3与第二电压端VGH1连接(当第三电压端VGH1为高电平时，与第三电压端连VGH2接)，从而使得第三节点N3被充电至高电平；在第三节点N3的控制下，使得逻辑或输出端OUT3与第五电压端VGL2连接，从而逻辑或输出端OUT3被下拉至低电平。
第三阶段，检测输出端OUT1输出高电平的检测输出信号，显示输出端OUT2输出低电平的显示输出信号，从而在检测输出信号的高电平的控制下，使得第一节点N1和检测输出端OUT1连接，使得第一节点N1被充电至高电平；在第一节点N1的高电平的控制下，使得逻辑或输出端OUT3与检测输出端OUT1连接，从而逻辑或输出端OUT3输出检测输出信号的高电平。
该逻辑或输出端OUT3可以使得栅极驱动电路20在显示期间输出显示输出信号以驱动例如与其连接的栅极扫描线，在检测期间输出检测输出信号以驱动例如与其连接的栅极扫描线，并将该检测输出信号用于与该栅极扫描线连接的像素电路的驱动晶体管的阈值电压和迁移率的补偿，且该显示输出信号和检测输出信号的输出互不干扰。
下面结合图13D所示的信号时序图，对图12C中所示的栅极驱动电路20中显示子移位寄存器部分的工作原理进行说明。例如，在本示例中，结合图13D所示的信号时序图，对图7C中所示的显示子移位寄存器200的工作原理进行说明，在图13D所示的第一阶段1、第二阶段2、第三阶段3以及第四阶段4共四个阶段中，该显示子移位寄存器200可以分别进行如下操作。
在第一阶段1，第一时钟信号线CLKA提供高电平信号，由于第N-1级显示子移位寄存器200的时钟信号端CLK4和第一时钟信号线CLKA连接，所以在此阶段，第N-1级显示子移位寄存器200的第四时钟信号端CLK4输入高电平信号；又由于第N-1级显示子移位寄存器200的第二上拉节点PU2_N-1为高电平，所以在第二上拉节点PU2_N-1高电平的控制下，第四时钟信号端CLK4输入的高电平输出至第N-1级显示子移位寄存器200的输出端OUT2_N-1。需要说明的是，图13D中所示的信号时序图的电位的高低仅是示意性的，不代表真实电位值。
在第二阶段2，第二时钟信号线CLKB提供高电平信号，由于第N级显示子移位寄存器200的第四时钟信号端CLK4和第二时钟信号线CLKB连接，所以在此阶段第N级显示子移位寄存器200的第四时钟信号端CLK4输入高电平信号；又由于第N级显示子移位寄存器200的第二上拉节点PU2_N为高电平，所以在第二上拉节点PU2_N高电平的控制下，第四时钟信号端CLK4输入的高电平输出至第N级显示子移位寄存器200的输出端OUT2_N。
在第三阶段3，第六时钟信号线CLKF提供高电平信号，由于第N+1级 显示子移位寄存器200的第四时钟信号端CLK4和第六时钟信号线CLKF连接，所以在此阶段第N+1级显示子移位寄存器200的第四时钟信号端CLK4输入高电平信号；又由于第N+1级显示子移位寄存器200的第二上拉节点PU2_N+1为高电平，所以在第二上拉节点PU2_N+1高电平的控制下，第四时钟信号端CLK4输入的高电平输出至第N+1级显示子移位寄存器200的输出端OUT2_N+1。
在第四阶段4，第七时钟信号线CLKG提供高电平信号，由于第N+2级显示子移位寄存器200的第四时钟信号端CLK4和第七时钟信号线CLKG连接，所以在此阶段第N+2级显示子移位寄存器200的第四时钟信号端CLK4输入高电平信号；又由于第N+2级显示子移位寄存器200的第二上拉节点PU2_N+2为高电平，所以在第二上拉节点PU2_N+2高电平的控制下，第四时钟信号端CLK4输入的高电平输出至第N+2级显示子移位寄存器200的输出端OUT2_N+2。
下面结合图13E所示的信号时序图，对图12C中所示的栅极驱动电路20中检测子移位寄存器部分的工作原理进行说明。例如，在本示例中，结合图13E所示的信号时序图，对图5D和图5E中所示的检测子移位寄存器100的工作原理进行说明，在图13E所示的第一阶段1、第二阶段2、第三阶段3以及第四阶段4共四个阶段中，该检测子移位寄存器可以分别进行如下操作。例如，本示例中以第N-1级检测子移位寄存器的工作原理进行说明，其余各级检测子移位寄存器100的工作原理与第N-1级检测子移位寄存器的工作原理类似，在此不再赘述。
第一阶段1，第一随机脉冲端OE1输入高电平信号，第N-1级显示子移位寄存器200的显示输出端OUT2_N-1也输出高电平信号，第N-1级检测子移位寄存器100的第一输入端INPUT1_N-1与第N-1级显示子移位寄存器200的显示输出端OUT2_N-1连接，因此第N-1级检测子移位寄存器100的第一输入端INPUT1_N-1输入高电平信号；因此，在第一随机脉冲信号和第N-1级的显示输出信号的高电平的控制下，使得随机脉冲信号控制子电路的第一输出端H1与第N-1级检测子移位寄存器100的第一输入端INPUT1_N-1相连，由于电容的自举效应，使得该随机脉冲信号控制子电路的第一输出端H1被充电至高电平，因此，在随机脉冲信号控制子电路的第一输出端H1的高 电平的控制下第一晶体管T1导通。由于，在此阶段第二随机脉冲信号为低电平，所以随机脉冲信号控制子电路的第二输出端H2为低电平，所以第二晶体管T2在随机脉冲信号控制子电路的第二输出端H2的低电平的控制下截止，所以，在此阶段，第N-1级检测子移位寄存器单元100的检测输出端OUT1_N-1为低电平。
第二阶段2，第一随机脉冲端OE1输入低电平信号，第二随机脉冲端OE2输入高电平，第N-1级显示子移位寄存器200的显示输出端OUT2_N-1也输出高电平信号，第N-1级检测子移位寄存器100的第一输入端INPUT1_N-1与第N-1级显示子移位寄存器200的显示输出端OUT2_N-1连接，因此第N-1级检测子移位寄存器100的第一输入端INPUT1_N-1输入高电平信号；因此，在第二随机脉冲信号和第N-1级的显示输出信号的高电平的控制下，使得随机脉冲信号控制子电路的第二输出端H2与第N-2级检测子移位寄存器100的第一输入端INPUT1_N-1相连，使得该随机脉冲信号控制子电路的第二输出端H2被充电至高电平，因此，在随机脉冲信号控制子电路的第二输出端H2的高电平的控制下第二晶体管T2导通；又由于，在此阶段随机脉冲信号控制子电路的第一输出端H1依然为高电平，因此第一晶体管T1也导通，因此在随机脉冲信号控制子电路的第一输出端H1和第二输出端H2的高电平的控制下，使得检测子移位寄存器100的第一上拉节点PU_N-1与第二时钟信号端连接使得该第一上拉节点PU1_N-1被充电至第一高电平；在此阶段，第三时钟信号线CLKC提供低电平信号，由于第N-1级检测子移位寄存器单元100的时钟信号端CLK1和第三时钟信号线CLKC连接，所以在此阶段，第N-1级检测子移位寄存器单元100的时钟信号端CLK1输入低电平信号；又由于第N-1级检测子移位寄存器单元100的第一上拉节点PU1_N-1为第一高电平，所以在第一上拉节点PU1_N-1高电平的控制下，时钟信号端CLK1输入的低电平输出至第N-1级检测子移位寄存器单元100的检测输出端OUT1_N-2。
在此阶段，第N级显示子移位寄存器的显示输出端OUT2_N输出高电平信号，第N级检测子移位寄存器100的第一输入端INPUT1_N与第N级显示子移位寄存器200的显示输出端OUT2_N连接，因此第N级检测子移位寄存器100的第一输入端INPUT1_N输入高电平信号。由于在此阶段，第 一随机脉冲端OE1输入低电平信号，因此随机脉冲信号控制子电路的第一输出端H1依然为低电平，因此，第一晶体管在随机脉冲信号控制子电路的第一输出端H1的低电平的控制下截止，因此第N级检测子移位寄存器的第一上拉节点PU_N依然为低电平，从而，在此阶段，第N级检测子移位寄存器的输出端OUT1_N为低电平，从而保证了栅极驱动电路20中逐行扫描的功能关闭，只对一级检测子移位寄存器进行输出控制。
第三阶段3，第三时钟信号线CLKC提供高电平信号，所以在此阶段检测子移位寄存器单元100的时钟信号端CLK1输入高电平信号；又由于第N级检测子移位寄存器单元100的第一上拉节点PU1_N-1为第一高电平，所以在第一上拉节点PU1_N-1的高电平的控制下，时钟信号端CLK1输入的高电平输出至第N-1级检测子移位寄存器单元100输出端OUT1_N-1，同时，第一上拉节点PU1_N-1由于电容的自举效应被充电至第二高电平。同时，在第一时钟信号端CLK1输入的高电平的控制下，使得随机脉冲信号控制子电路的第一输出端H1和第二输出端H2与第一电压端VGL1连接，从而使得随机脉冲信号控制子电路的第一输出端H1和第二输出端H2变为低电平，从而实现对随机脉冲信号控制子电路的第一输出端H1和第二输出端H2的复位。
第四阶段4，总复位线TRST提供高电平信号，由于各级检测子移位寄存器100的第一复位端RST1与该总复位线连接，因此各级检测子移位寄存器100的第一复位端RST1都被输入高电平，所以各级检测子移位寄存器100的第一上拉节点PU1被下拉至低电平，从而第一下拉节点PD1被上拉至高电平，从而各级的检测输出端OUT1被下拉至低电平。因此在此阶段，第N-1级检测子移位寄存器单元100输出端OUT1_N-1输出低电平。又例如，如图13F所示，在第四晶体管和第六晶体管只采用一个宽长比较大的晶体管时，第一上拉节点的电平可以分两次下拉。
本公开的实施例还提供一种显示装置1，如图14A所示，该显示装置1包括本公开实施例提供的栅极驱动电路20。该显示装置1包括由多个像素单元50构成的阵列，每个像素单元例如采用图1D所示的3T1C的像素电路，或基于该3T1C结构的其他像素电路等。例如，该显示装置1还可以包括数据驱动电路30。数据驱动电路30用于提供数据信号给像素阵列；栅极驱动电路20用于提供栅极扫描信号给像素阵列。例如，该栅极扫描信号包括从逻 辑或输出端OUT3或输出复合输出端OUT4输出的包括显示输出信号和检测输出信号的复合信号。例如，该显示输出信号用于驱动该像素阵列中像素电路的有机发光二极管发光。例如，该检测输出信号用于对像素阵列中像素电路的驱动晶体管的阈值电压和迁移率进行补偿。数据驱动电路30通过数据线31与像素单元50电连接，栅极驱动电路20通过栅线21与像素单元50电连接。
例如，该显示装置1还包括随机脉冲发生电路40。该随机脉冲发生电路40配置为生成第一随机脉冲信号且与第一随机脉冲信号线41连接。例如，该随机脉冲发生电路40还可以配置为生成第二随机脉冲信号且与第二随机脉冲信号线(图中未示出)连接。例如，该随机脉冲电路40可以是各种可以产生脉冲的电路或装置，例如中央处理单元(CPU)、数据信号处理器(DSP)等，还可以通过现场可编程门阵列(FPGA)等方式实现。
需要说明的是，本实施例中的显示装置1可以为：液晶面板、液晶电视、显示器、OLED面板、OLED电视、电子纸显示装置、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置1还可以包括显示面板等其他常规部件，本公开的实施例对此不作限定。
图14B示出了本公开一实施例提供的另一示例的显示装置1的示意图。图14B所示的显示装置1与图14A中所示的显示装置1的区别在于栅极驱动电路20的栅极扫描线包括扫描线22和补偿扫描线23，且扫描线22和补偿扫描线23分别与像素单元50中的扫描端Scan1和补偿扫描端Scan2连接，以通过扫描线22向像素单元50中的开关晶体管T0提供扫描信号Scan1，通过补偿扫描线23向像素单元50中的感测晶体管S0提供补偿扫描信号Scan2。该示例中的每个像素单元50例如采用图1C所示的3T1C的像素电路，或基于该3T1C结构的其他像素电路等。
需要说明的是，在本公开实施例中，符号Scan1既可以表示扫描端，也可以表示扫描信号；符号Scan2既可以表示补偿扫描端，也可以表示补偿扫描信号。
本公开的实施例提供的显示装置1的技术效果可以参考上述实施例中关于栅极驱动电路20的相应描述，这里不再赘述。
本公开的实施例还提供一种栅极驱动电路的驱动方法，其可以适用于采 用本公开的实施例提供的移位寄存器单元10的栅极驱动电路20。
该栅极驱动电路20的驱动方法，对于第N级移位寄存器单元10，包括如下操作：第N(N为大于1的整数)级显示子移位寄存器的显示输出端OUT2_N输出显示输出信号；第N级检测子移位寄存器OUT1_N响应于显示输出信号和第一随机脉冲信号对其第一上拉节点PU1_N进行充电；第N级检测子移位寄存器输出检测输出信号。
本公开的实施例还提供另一种栅极驱动电路的驱动方法，其可以适用于采用本公开的实施例提供的移位寄存器单元10的栅极驱动电路20。
该栅极驱动电路20的驱动方法，对于第N级移位寄存器单元10，包括如下操作：第N级显示子移位寄存器的显示输出端输出显示输出信号；第N级检测子移位寄存器响应于显示输出信号、第一随机脉冲信号和第二随机脉冲信号对第一上拉节点进行充电；第N级检测子移位寄存器输出检测输出信号。
本公开的实施例提供的栅极驱动电路20的驱动方法的技术效果可以参考上述实施例中关于栅极驱动电路20的相应描述，这里不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (27)

  1. 一种移位寄存器单元，包括显示子移位寄存器和检测子移位寄存器；其中，
    所述显示子移位寄存器包括显示输出端，所述显示子移位寄存器配置为在显示阶段从所述显示输出端输出所述移位寄存器单元的显示输出信号；
    所述检测子移位寄存器与所述显示子移位寄存器的显示输出端连接以接收所述显示输出信号，且包括第一随机脉冲信号端以接收第一随机脉冲信号，
    其中，所述检测子移位寄存器配置为包括在所述显示输出信号为开启电平且所述第一随机脉冲信号为开启电平时，输出所述移位寄存器单元的检测输出信号。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述检测子移位寄存器包括第一检测输入子电路、第一上拉节点复位子电路和检测输出子电路；其中，
    所述第一检测输入子电路配置为响应于所述显示输出信号和所述第一随机脉冲信号对第一上拉节点进行充电；
    所述第一上拉节点复位子电路配置为响应于第一复位信号对所述第一上拉节点进行复位；
    所述检测输出子电路配置为在所述第一上拉节点的电平的控制下，将第一时钟信号输出至检测输出端。
  3. 根据权利要求2所述的移位寄存器单元，其中，所述检测子移位寄存器还包括第一上拉节点降噪子电路、第一输出降噪子电路和第一下拉子电路；其中，
    所述第一上拉节点降噪子电路配置为在第一下拉节点的电平的控制下，对所述第一上拉节点进行降噪；
    所述检测输出降噪子电路配置在所述第一下拉节点的电平的控制下，对所述检测输出端进行降噪；
    所述第一下拉子电路配置为在所述第一上拉节点的电平的控制下，对所述第一下拉节点的电平进行控制。
  4. 根据权利要求3所述的移位寄存器单元，其中，所述第一检测输入子 电路包括第一晶体管和第二晶体管；其中，
    所述第一晶体管的栅极配置为和所述显示输出端连接以接收所述显示输出信号，所述第一晶体管的第一极配置为和第二时钟信号端连接以接收第二时钟信号，所述第一晶体管的第二极配置为和所述第二晶体管的第一极连接；
    所述第二晶体管的栅极配置为和所述第一随机脉冲信号端连接以接收所述第一随机脉冲信号，所述第二晶体管的第二极和所述第一上拉节点连接。
  5. 根据权利要求3所述的移位寄存器单元，其中，所述第一检测输入子电路包括：
    第一晶体管，其中，所述第一晶体管的栅极配置为和所述显示输出端连接以接收所述显示输出信号，所述第一晶体管的第一极配置为和所述第一随机脉冲信号端连接以接收所述第一随机脉冲信号，所述第一晶体管的第二极配置为和所述第一上拉节点连接，或者，
    所述第一晶体管的栅极配置为和所述第一随机脉冲信号端连接以接收所述第一随机脉冲信号，所述第一晶体管的第一极配置为和所述显示输出端连接以接收所述显示输出信号，所述第一晶体管的第二极配置为和所述第一上拉节点连接。
  6. 根据权利要求4或5所述的移位寄存器单元，其中，
    所述第一上拉节点复位子电路包括：
    第三晶体管，其中，所述第三晶体管的栅极配置为和第一复位端连接以接收所述第一复位信号，所述第三晶体管的第一极配置为和所述第一上拉节点连接，所述第三晶体管的第二极配置为和第一电压端连接以接收第一电压信号；或
    所述检测输出子电路包括：
    第四晶体管，其中，所述第四晶体管的栅极配置为和所述第一上拉节点连接，所述第四晶体管的第一极配置为和第一时钟信号端连接以接收所述第一时钟信号，所述第四晶体管的第二极配置为和所述检测输出端连接以输出所述检测输出信号；以及
    第一存储电容，其中，所述第一存储电容的第一极和所述第一上拉节点连接，所述第一存储电容的第二极和所述检测输出端连接；或
    所述第一上拉节点降噪子电路包括：
    第五晶体管，其中，所述第五晶体管的栅极配置为和所述第一下拉节点连接，所述第五晶体管的第一极配置为和所述第一上拉节点连接，所述第五晶体管的第二极配置为和所述第一电压端连接；或
    所述检测输出降噪子电路包括：
    第六晶体管，其中，所述第六晶体管的栅极配置为和所述第一下拉节点连接，所述第六晶体管的第一极配置为和所述检测输出端连接，所述第六晶体管的第二极配置为和所述第一电压端连接；或
    所述第一下拉子电路包括：
    第七晶体管，其中，所述第七晶体管的栅极与第一极连接，且配置为与第二电压端连接以接收第二电压信号，所述第七晶体管的第二极配置为与所述第一下拉节点连接；
    第八晶体管，其中，所述第八晶体管的栅极与所述第一上拉节点连接，所述第八晶体管的第一极与所述第一下拉节点连接，所述第八晶体管的第二极配置为与所述第一电压端连接以接收所述第一电压信号。
  7. 根据权利要求6所述的移位寄存器单元，其中，所述第一下拉子电路还包括：
    第九晶体管，其中，所述第九晶体管的栅极和第一极连接，且配置为与第三电压端连接以接收第三电压信号，所述第九晶体管的第二极与所述第一下拉节点连接；
    第十晶体管，其中，所述第十晶体管的栅极与所述第一上拉节点连接，所述第十晶体管的第一极与所述第一下拉节点连接，所述第十晶体管的第二极配置为与所述第一电压端连接以接收所述第一电压信号。
  8. 根据权利要求6所述的移位寄存器单元，其中，所述检测子移位寄存器还包括第二检测输入子电路和检测输入端；其中，
    所述第二检测输入子电路配置为和检测输入端连接以接收检测输入信号且响应于所述检测输入信号对所述第一上拉节点进行充电。
  9. 根据权利要求8所述的移位寄存器单元，其中，所述第二检测输入子电路包括：
    第十一晶体管，其中，所述第十一晶体管的栅极和第一极连接，且配置为和所述检测输入端连接以接收所述检测输入信号，所述第十一晶体管的第 二极和所述第一上拉节点连接，或者，
    所述第十一晶体管的栅极配置为和所述检测输入端连接以接收所述检测输入信号，所述第十一晶体管的第一极配置为和第三时钟信号端连接以接收第三时钟信号，所述第十一晶体管的第二极和所述第一上拉节点连接。
  10. 根据权利要求9所述的移位寄存器单元，其中，所述第一上拉节点复位子电路还包括：
    第十二晶体管，其中，所述第十二晶体管的栅极和第二复位端连接以接收第二复位信号，所述第十二晶体管的第一极和所述第一上拉节点连接，所述第十二晶体管的第二极和所述第一电压端连接以接收所述第一电压信号。
  11. 根据权利要求10所述的移位寄存器单元，其中，所述第一检测输入子电路还包括随机脉冲信号控制子电路和第二随机脉冲信号端；其中，
    所述随机脉冲信号控制子电路配置为和所述显示输出端、所述第一随机脉冲信号端和所述第二随机脉冲信号端连接以接收所述显示输出信号、所述第一随机脉冲信号和第二随机脉冲信号，且响应于所述显示输出信号、所述第一随机脉冲信号和所述第二随机脉冲信号使所述第一随机脉冲信号和所述第二随机脉冲信号同时为开启电平。
  12. 根据权利要求11所述的移位寄存器单元，其中，所述随机脉冲信号控制子电路包括：
    第五十一晶体管，其中，所述第五十一晶体管的栅极和所述第一随机脉冲信号端连接，第一极和所述显示输出端连接，第二极和所述第一晶体管的栅极连接；
    第五十二晶体管，其中，所述第五十二晶体管的栅极和所述第二脉冲信号端连接，第一极和所述显示输出端连接，第二极和所述第二晶体管的栅极连接；
    第五十三晶体管，其中，所述第五十三晶体管的栅极和所述第一时钟信号端连接，第一极和所述第一晶体管的栅极连接，第二极和所述第一电压端连接；
    第五十四晶体管，其中，所述第五十四晶体管的栅极和所述第一时钟信号端连接，第一极和所述第二晶体管的栅极连接，第二极和所述第一电压端连接；
    第五存储电容，其中，所述第五存储电容的第一极和所述第一晶体管的栅极连接，第二极和所述第一电压端连接；
    第六存储电容，其中，所述第六存储电容的第一极和所述第二晶体管的栅极连接，第二极和所述第一电压端连接。
  13. 根据权利要求10所述的移位寄存器单元，其中，所述检测子移位寄存器单元还包括防漏电子电路；其中，
    所述防漏电子电路配置为在所述第一上拉节点的电平的控制下，保持所述第一上拉节点的高电位。
  14. 根据权利要求13所述的移位寄存器单元，其中，
    所述防漏电子电路包括：
    第十三晶体管，其中，所述第十三晶体管的栅极和所述第一上拉节点连接，所述第十三晶体管的第一极和第四电压端连接以接收第四电压信号，所述第十三晶体管的第二极和反馈节点连接；或
    所述第二检测输入子电路包括第十一晶体管和第十四晶体管；其中，
    所述第十一晶体管的栅极配置为和检测输入端连接以接收所述检测输入信号，所述第十一晶体管的第一极配置为和第三时钟信号端连接以接收第三时钟信号，所述第十一晶体管的第二极和所述第十四晶体管的第一极连接，且配置为和所述反馈节点连接；
    所述第十四晶体管的栅极和所述第十一晶体管的栅极连接，所述第十四晶体管的第二极和所述第一上拉节点连接；或
    所述第一上拉节点复位子电路包括第三晶体管、第十二晶体管、第十五晶体管和第十六晶体管；其中，
    所述第三晶体管的栅极配置为和所述第一复位端连接以接收所述第一复位信号，所述第三晶体管的第一极和所述第十五晶体管的第二极连接，且配置为和所述反馈节点连接，所述第三晶体管的第二极配置为和第一电压端连接；
    所述第十二晶体管的栅极和所述第二复位端连接以接收所述第二复位信号，所述第十二晶体管的第一极和所述第十六晶体管的第二极连接，且配置为和所述反馈节点连接，所述第十二晶体管的第二极和所述第一电压端连接以接收第一电压信号；
    所述第十五晶体管的栅极和所述第三晶体管的栅极连接，所述第十五晶体管的第一极和所述第一上拉节点连接；
    所述第十六晶体管的栅极和所述第十二晶体管的栅极连接，所述第十六晶体管的第一极和所述第一上拉节点连接；或
    所述第一上拉节点降噪子电路包括第五晶体管和第十七晶体管；其中，
    所述第五晶体管的栅极配置为和所述第一下拉节点连接，所述第五晶体管的第一极配置为和所述第十七晶体管的第二极连接，且配置为和所述反馈节点连接，所述第五晶体管的第二极配置为和所述第一电压端连接；
    所述第十七晶体管的栅极和所述第五晶体管的栅极连接，所述第十七晶体管的第一极和所述第一上拉节点连接。
  15. 根据权利要求3-5任一所述的移位寄存器单元，其中，所述显示子移位寄存器包括显示输入子电路、第二上拉节点复位子电路和显示输出子电路；其中，
    所述显示输入子电路配置为响应于显示输入信号对第二上拉节点进行充电；
    所述第二上拉节点复位子电路配置为响应于第三复位端接收的第三复位信号对所述第二上拉节点进行复位；
    所述显示输出子电路配置为在所述第二上拉节点的电平的控制下，将第四时钟信号输出至所述显示输出端。
  16. 根据权利要求15所述的移位寄存器单元，其中，所述显示子移位寄存器还包括第二上拉节点降噪电路、显示输出降噪子电路和第二下拉子电路；其中，
    所述第二上拉节点降噪子电路配置为在第二下拉节点的电平的控制下，对所述第二上拉节点进行降噪；
    所述显示输出降噪子电路配置在所述第二下拉节点的电平的控制下，对所述显示输出端进行降噪；
    所述第二下拉子电路配置为在所述第二上拉节点的电平的控制下，对所述第二下拉节点的电平进行控制。
  17. 根据权利要求16所述的移位寄存器单元，还包括输出控制电路；其中，
    所述输出控制电路与所述检测子移位寄存器的第一上拉节点和第一下拉节点以及与所述显示子移位寄存器的第二上拉节点和第二下拉节点连接，且配置为当所述第一上拉节点和所述第二上拉节点之一为有效电平时则拉低另一个。
  18. 根据权利要求17所述的移位寄存器单元，其中，所述输出控制电路包括显示输出控制子电路和检测输出控制子电路；其中，
    所述检测输出控制子电路配置为在所述第一上拉节点的电平的控制下，对所述第二上拉节点和所述第二下拉节点的电平进行控制；
    所述显示输出控制子电路配置为在所述第二上拉节点的电平的控制下，对所述第一上拉节点和所述第一下拉节点的电平进行控制。
  19. 根据权利要求1-5任一所述的移位寄存器单元，还包括逻辑或电路；其中，
    所述逻辑或电路与所述显示子移位寄存器的显示输出端和所述检测子移位寄存器的检测输出端连接，且配置为将所述显示输出信号和所述检测输出信号进行或运算以得到复合输出信号。
  20. 根据权利要求19所述的移位寄存器单元，其中，所述逻辑或电路包括第一逻辑或输入子电路、第二逻辑或输入子电路、第一输出控制子电路、第二输出控制子电路、第一节点降噪子电路、第二节点降噪子电路、输出降噪控制子电路和输出降噪子电路；其中，
    所述第一逻辑或输入子电路配置为响应于所述检测输出信号对第一节点进行充电；
    所述第二逻辑或输入子电路配置为响应于所述显示输出信号对第二节点进行充电；
    所述第一输出控制子电路配置为在所述第一节点的电平的控制下，输出所述检测输出信号；
    所述第二输出控制子电路配置为在所述第二节点的电平的控制下，输出所述显示输出信号；
    所述第一节点降噪电路配置为在所述显示输出信号的电平的控制下，对所述第一节点进行降噪；
    所述第二节点降噪电路配置为在所述检测输出信号的电平的控制下，对 所述第二节点进行降噪；
    所述输出降噪控制子电路配置为在所述显示输出信号和所述检测输出信号的电平的控制下对第三节点的电平进行控制；
    所述输出降噪子电路配置为在所述第三节点的电平的控制下，对逻辑或输出端进行降噪。
  21. 一种栅极驱动电路，包括多个级联的如权利要求1-7、15-19任一所述的移位寄存器单元，其中，
    每个所述移位寄存器单元的检测子移位寄存器的第一随机脉冲信号端与第一随机脉冲信号线连接；
    除第一级显示子移位寄存器外，其余各级显示子移位寄存器的显示输入端和上一级显示子移位寄存器的显示输出端连接；
    除最后一级显示子移位寄存器外，其余各级显示子移位寄存器的第三复位端和下一级显示子移位寄存器的显示输出端连接。
  22. 一种栅极驱动电路，包括多个级联的如权利要求8-10、13-14任一所述的移位寄存器单元，其中，
    每个所述移位寄存器单元的检测子移位寄存器的第一随机脉冲信号端与第一随机脉冲信号线连接；
    除第一级显示子移位寄存器外，其余各级显示子移位寄存器的显示输入端和上一级显示子移位寄存器的显示输出端连接；
    除第一级检测子移位寄存器外，其余各级检测子移位寄存器的检测输入端和上一级检测子移位寄存器的检测输出端连接。
  23. 一种栅极驱动电路，包括多个级联的如权利要求11或12所述的移位寄存器单元，其中，
    每个所述移位寄存器单元的检测子移位寄存器的第一随机脉冲信号端与第一随机脉冲信号线连接；
    每个所述移位寄存器单元的检测子移位寄存器的第二随机脉冲信号端与第二随机脉冲信号线连接；
    除第一级和第二级显示子移位寄存器单元外，其余各级显示子移位寄存器的显示输入端和与其相隔一级的上级显示子移位寄存器的显示输出端连接；
    除第一级检测子移位寄存器外，其余各级检测子移位寄存器的检测输入端和上一级检测子移位寄存器的检测输出端连接。
  24. 一种显示装置，包括权利要求21-23任一所述的栅极驱动电路。
  25. 根据权利要求24所述的显示装置，还包括随机脉冲发生电路，其中，所述随机脉冲发生电路配置为生成所述第一随机脉冲信号且与所述第一随机脉冲信号线连接。
  26. 一种权利要求21或22所述的栅极驱动电路的驱动方法，包括：
    第N级显示子移位寄存器的显示输出端输出显示输出信号；
    第N级检测子移位寄存器响应于所述显示输出信号和所述第一随机脉冲信号对所述第一上拉节点进行充电；
    所述第N级检测子移位寄存器输出检测输出信号；
    N为大于1的整数。
  27. 一种权利要求23所述的栅极驱动电路的驱动方法，包括：
    第N级显示子移位寄存器的显示输出端输出显示输出信号；
    第N级检测子移位寄存器响应于所述显示输出信号、所述第一随机脉冲信号和所述第二随机脉冲信号对所述第一上拉节点进行充电；
    所述第N级检测子移位寄存器输出检测输出信号；
    N为大于1的整数。
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US11263973B2 (en) 2022-03-01
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