WO2019037457A1 - 一种移位寄存器、其驱动方法、驱动控制电路及显示装置 - Google Patents

一种移位寄存器、其驱动方法、驱动控制电路及显示装置 Download PDF

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Publication number
WO2019037457A1
WO2019037457A1 PCT/CN2018/084219 CN2018084219W WO2019037457A1 WO 2019037457 A1 WO2019037457 A1 WO 2019037457A1 CN 2018084219 W CN2018084219 W CN 2018084219W WO 2019037457 A1 WO2019037457 A1 WO 2019037457A1
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Prior art keywords
node
signal
control
switching transistor
circuit
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PCT/CN2018/084219
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English (en)
French (fr)
Inventor
羊振中
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京东方科技集团股份有限公司
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Priority to EP18829714.7A priority Critical patent/EP3675128B1/en
Priority to US16/317,361 priority patent/US11011117B2/en
Publication of WO2019037457A1 publication Critical patent/WO2019037457A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • the present disclosure relates to a shift register, a driving method thereof, a driving control circuit, and a display device.
  • the Gate Driver on Array (GOA) technology integrates a Thin Film Transistor (TFT) gate switch drive control circuit on the array substrate of the display panel to form a gate of the TFT in the display panel.
  • Control which can eliminate the bonding area of the integrated circuit (IC) and the wiring space of the fan-out area, which can reduce the product cost both in terms of material cost and preparation process. And can make the display panel achieve the aesthetic design of two sides symmetrical and narrow border.
  • this integrated process also eliminates the Bonding process in the direction of the gate scan line, thereby increasing throughput and yield.
  • the driving control circuit as the gate driving circuit is composed of a plurality of cascaded shift registers, and the gate scanning signals are sequentially input to the respective gate lines on the display panel through the shift registers of the stages.
  • An embodiment of the present disclosure provides a shift register including: an input sub-circuit, a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, a node stabilization sub-circuit, a first output sub-circuit, and a second output Subcircuit
  • the input sub-circuit is respectively connected to the input signal end, the first clock signal end, the first node and the second node, and is configured to provide the signal of the input signal end to the control under the control of the first clock signal end a first node, and providing a signal of the first clock signal end to the second node;
  • the first control sub-circuit is respectively connected to the first reference signal end, the first node, and the second node, and is configured to provide the signal of the first reference signal end to the control of the first node to The second node;
  • the second control sub-circuit is respectively connected to the first reference signal end, the second reference signal end, the first node, the second node, and the third node, for signals at the first node Providing, by the control, the signal of the first reference signal end to the third node, and providing the signal of the second reference signal end to the third node under the control of the signal of the second node;
  • the third control sub-circuit is connected to the first reference signal end, the first node, and the third node, respectively, for transmitting the signal of the first reference signal end under the control of the third node Provided to the first node;
  • the node stabilization sub-circuit is connected to the first node, and is configured to stabilize a potential of the first node;
  • the first output sub-circuit is respectively connected to the first node, the second reference signal end, and an output signal end of the shift register, and is configured to be used under the control of a signal of the first node.
  • a signal of the second reference signal end is provided to the output signal end;
  • the second output sub-circuit is respectively connected to the third node, the first reference signal end, and the output signal end, and configured to use the first reference signal under the control of a signal of the third node
  • the signal of the terminal is supplied to the output signal terminal.
  • the input sub-circuit includes: a first switching transistor and a second switching transistor;
  • a control electrode of the first switching transistor is connected to the first clock signal end, a first pole of the first switching transistor is connected to the input signal terminal, a second pole of the first switching transistor is The first node is connected;
  • control pole and the first pole of the second switching transistor are both connected to the first clock signal end, and the second pole of the second switching transistor is connected to the second node.
  • the first control sub-circuit includes: a third switching transistor
  • a control electrode of the third switching transistor is connected to the first node, a first pole of the third switching transistor is connected to the first reference signal terminal, and a second pole of the third switching transistor is The second node is connected.
  • the second control sub-circuit includes: a fourth switching transistor and a fifth switching transistor;
  • a control electrode of the fourth switching transistor is connected to the first node, a first pole of the fourth switching transistor is connected to the first reference signal end, and a second pole of the fourth switching transistor is The third node is connected;
  • a control electrode of the fifth switching transistor is connected to the second node, a first pole of the fifth switching transistor is connected to the second reference signal terminal, and a second pole of the fifth switching transistor is The third node is connected.
  • the third control sub-circuit includes: a sixth switching transistor
  • a control electrode of the sixth switching transistor is connected to the third node, a first pole of the sixth switching transistor is connected to the first reference signal end, and a second pole of the sixth switching transistor is The first node is connected.
  • the first output sub-circuit includes: a seventh switching transistor
  • a control electrode of the seventh switching transistor is connected to the first node, a first pole of the seventh switching transistor is connected to the second reference signal terminal, and a second pole of the seventh switching transistor is The output signals are connected.
  • the second output sub-circuit includes: an eighth switching transistor
  • a control electrode of the eighth switching transistor is connected to the third node, a first pole of the eighth switching transistor is connected to the first reference signal terminal, and a second pole of the eighth switching transistor is The output signals are connected.
  • each of the switching transistors is a P-type transistor, a source of the first extreme P-type transistor of each switching transistor, and a second extreme P-type of each switching transistor. The drain of the transistor.
  • each of the switching transistors is an N-type transistor, a drain of a first very N-type transistor of each switching transistor, and a second extremely N-type of each switching transistor.
  • the source of the transistor is an N-type transistor, a drain of a first very N-type transistor of each switching transistor, and a second extremely N-type of each switching transistor.
  • the node stabilization sub-circuit includes a capacitor; the first end of the capacitor is connected to the first node, and the second end of the capacitor is The two clock signals are connected.
  • an embodiment of the present disclosure further provides a driving control circuit, including: a plurality of cascaded shift registers provided by the embodiments of the present disclosure;
  • the input signal end of the first stage shift register is connected to the start signal end;
  • the input signal terminals of the remaining stages of shift registers are respectively connected to the output signal ends of the adjacent upper stage shift registers.
  • an embodiment of the present disclosure further provides a display device, including the above-mentioned driving control circuit provided by an embodiment of the present disclosure.
  • the display device includes a plurality of light emission control signal lines; a signal output end of each stage shift register in the drive control circuit and a light emission control signal Wire connection.
  • the driving control circuit is a gate driving circuit.
  • the embodiment of the present disclosure further provides a driving method of any one of the above shift registers provided by the embodiment of the present disclosure, including: a first phase, a second phase, a third phase, and a fourth phase;
  • the input sub-circuit provides a signal of the input signal end to the first node under the control of the first clock signal end, and provides a signal of the first clock signal end to The second node;
  • the second control sub-circuit provides the signal of the second reference signal end to the third node under the control of the signal of the second node;
  • the third control sub-circuit is in the a signal of the first reference signal end is provided to the first node under control of a third node;
  • the second output sub-circuit is configured to control the first reference signal end under the control of a signal of the third node a signal is provided to the output signal terminal;
  • the second control sub-circuit provides a signal of the second reference signal end to the third node under the control of a signal of the second node;
  • the third control sub-circuit is Providing, by the control of the third node, the signal of the first reference signal end to the first node;
  • the second output sub-circuit is configured to control the first reference signal under the control of a signal of the third node a signal of the terminal is provided to the output signal terminal;
  • the input sub-circuit provides a signal of the input signal end to the first node under the control of the first clock signal end, and provides a signal of the first clock signal end to The second node;
  • the first control sub-circuit provides a signal of the first reference signal end to the second node under control of the first node;
  • the second control sub-circuit is in the a signal of the first reference signal end is provided to the third node under control of a signal of a node;
  • the first output sub-circuit is to control the second reference signal end under the control of a signal of the first node a signal is provided to the output signal terminal;
  • the node stabilizing sub-circuit stabilizes the potential of the first node;
  • the first control sub-circuit provides the signal of the first reference signal end to the control under the control of the first node a second node;
  • the second control sub-circuit provides a signal of the first reference signal end to the third node under control of a signal of the first node;
  • the first output sub-circuit is in the The signal of the second reference signal end is supplied to the output signal terminal under the control of the signal of the first node.
  • the insertion phase includes the first Inserting a sub-phase and a second inserting sub-phase
  • the second control sub-circuit provides a signal of the second reference signal end to the third node under the control of a signal of the second node;
  • the third control sub- The circuit provides the signal of the first reference signal end to the first node under the control of the third node;
  • the second output sub-circuit will be the first under the control of the signal of the third node a signal of the reference signal end is supplied to the output signal terminal;
  • the input sub-circuit provides a signal of the input signal end to the first node and a signal of the first clock signal end under the control of the first clock signal end Providing to the second node; the second control sub-circuit provides a signal of the second reference signal end to the third node under control of a signal of the second node; the third control sub-circuit Providing a signal of the first reference signal end to the first node under control of the third node; the second output sub-circuit is to use the first reference under control of a signal of the third node A signal at the signal end is supplied to the output signal terminal.
  • the period of the signal of the first clock signal end is the same as the period of the signal of the second clock signal end, and the duration of the effective pulse signal of the first clock signal end
  • the percentage of the duration of one clock cycle is the same as the percentage of the duration of the effective pulse signal of the second clock signal end of one clock cycle
  • the duration of the effective pulse signal of the first clock signal end is less than or equal to 50% of the duration of one of the clock cycles.
  • FIG. 1 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure
  • 2a is a schematic structural diagram of a shift register provided by an embodiment of the present disclosure
  • 2b is a schematic structural diagram of a shift register provided by an embodiment of the present disclosure.
  • Figure 3a is a schematic input and output timing diagram of the shift register shown in Figure 2a;
  • Figure 3b is a schematic input and output timing diagram of the shift register shown in Figure 2a;
  • Figure 3c is a schematic input and output timing diagram of the shift register shown in Figure 2a;
  • 4a is a schematic diagram of a schematic simulation in an embodiment of the present disclosure.
  • 4b is a schematic diagram of a schematic simulation in an embodiment of the present disclosure.
  • 4c is a schematic diagram of a schematic simulation in an embodiment of the present disclosure.
  • FIG. 5 is a flowchart of a driving method according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a driving control circuit according to an embodiment of the present disclosure.
  • the output of the gate scan signal can be realized by inputting a plurality of control signals of different functions
  • the number of switching transistors constituting the shift registers of the gate driving circuit is large, and the switching transistors are respectively
  • the specific structure of the connection is also complicated, which leads to increased process difficulty, increased production cost, and even the use of more signal lines to input control signals of various functions into the shift registers of various stages, thereby causing the opening of the display panel.
  • the rate is reduced, making the display panel uncompetitive.
  • Embodiments of the present disclosure provide a shift register, a driving method thereof, a driving control circuit, and a display device for stably outputting signals by a simple structure.
  • the shift register, the driving method thereof, the driving control circuit and the display device provided by the embodiment of the present disclosure include: an input sub-circuit, a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, a node stabilization sub-circuit, The first output sub-circuit and the second output sub-circuit; through the mutual cooperation of the above seven sub-circuits, the output signal end can be stably outputted by a simple structure and fewer signal lines, thereby simplifying the preparation Process to reduce production costs.
  • An embodiment of the present disclosure provides a shift register, as shown in FIG. 1, comprising: an input sub-circuit 1, a first control sub-circuit 2, a second control sub-circuit 3, a third control sub-circuit 4, and a node stabilization sub-circuit 5. a first output sub-circuit 6 and a second output sub-circuit 7;
  • the input sub-circuit 1 is respectively connected to the input signal terminal Input (input terminal), the first clock signal terminal CK1, the first node A and the second node B, and is used for inputting the signal terminal under the control of the first clock signal terminal CK1.
  • the input (input) signal is provided to the first node A, and the signal of the first clock signal terminal CK1 is provided to the second node B;
  • the first control sub-circuit 2 is connected to the first reference signal terminal Vref1, the first node A and the second node B, respectively, for providing the signal of the first reference signal terminal Vref1 to the second node under the control of the first node A B;
  • the second control sub-circuit 3 is connected to the first reference signal terminal Vref1, the second reference signal terminal Vref2, the first node A, the second node B, and the third node C, respectively, for controlling under the signal of the first node A. Supplying the signal of the first reference signal terminal Vref1 to the third node C, and providing the signal of the second reference signal terminal Vref2 to the third node C under the control of the signal of the second node B;
  • the third control sub-circuit 4 is connected to the first reference signal terminal Vref1, the first node A and the third node C, respectively, for providing the signal of the first reference signal terminal Vref1 to the first node under the control of the third node C. A;
  • the node stabilizing sub-circuit 5 is connected to the first node A for stabilizing the potential of the first node A;
  • the first output sub-circuit 6 is connected to the first node A, the second reference signal terminal Vref2, and the output signal terminal Output (output terminal) of the shift register, respectively, for using the second reference under the control of the signal of the first node A.
  • the signal of the signal terminal Vref2 is supplied to the output signal terminal Output (output terminal);
  • the second output sub-circuit 7 is respectively connected to the third node C, the first reference signal terminal Vref1 and the output signal terminal Output (output terminal) for using the first reference signal terminal Vref1 under the control of the signal of the third node C.
  • the signal is supplied to the output signal output.
  • the shift register provided by the embodiment of the present disclosure includes: an input sub-circuit 1, a first control sub-circuit 2, a second control sub-circuit 3, a third control sub-circuit 4, a node stabilization sub-circuit 5, and a first output sub-circuit 6.
  • the input sub-circuit 1 is configured to provide a signal of the input signal end to the first node and a signal of the first clock signal end to the second node under the control of the first clock signal end;
  • the control sub-circuit 2 is configured to provide a signal of the first reference signal end to the second node under the control of the first node;
  • the second control sub-circuit 3 is configured to transmit the signal of the first reference signal end under the control of the signal of the first node Provided to the third node, the signal of the second reference signal end is provided to the third node under the control of the signal of the second node;
  • the third control sub-circuit 4 is configured to transmit the signal of the first reference signal end under the control of the third node Provided to the first node;
  • the node stabilizing sub-circuit 5 is for stabilizing the potential of the first node;
  • the first output sub-circuit 6 is for providing the signal of the second reference signal end under the control of the signal of the first node The output signal terminal is used;
  • the shift register provided by the embodiment of the present disclosure can make the output signal terminal output the shifted signal stably through a simple structure and fewer signal lines through the mutual cooperation of the above seven sub-circuits, thereby simplifying the preparation process and reducing the manufacturing process. Cost of production. And through the mutual cooperation of the above seven sub-circuits, the duration of the effective pulse signal of the signal outputted by the signal output end can be controlled only by changing the duration of the effective pulse signal at the input signal end, without the need for circuit modification and process change. Thereby, the preparation process can be simplified, the production cost can be reduced, and the narrow bezel design of the panel in the display device can be realized.
  • the effective pulse signal of the input signal terminal is a high potential signal
  • the signal of the first reference signal end is a high potential signal
  • the signal of the second reference signal end is a low potential. signal.
  • the effective pulse signal at the input signal terminal is a low potential signal
  • the signal at the first reference signal terminal is a low potential signal
  • the signal at the second reference signal terminal is a high potential signal.
  • the input sub-circuit 1 may include, for example, a first switching transistor M1 and a second switching transistor M2;
  • the control electrode of the first switching transistor M1 is connected to the first clock signal terminal CK1, the first pole of the first switching transistor M1 is connected to the input signal terminal Input (input terminal), and the second pole of the first switching transistor M1 is connected to the first node A connected;
  • the control pole and the first pole of the second switching transistor M2 are both connected to the first clock signal terminal CK1, and the second pole of the second switching transistor M2 is connected to the second node B.
  • the first switching transistor M1 and the second switching transistor M2 may be P-type transistors.
  • the first switching transistor M1 and the second switching transistor M2 may also be N-type transistors, which are not limited herein.
  • the signal of the input signal end when the first switching transistor is in an on state under the control of the signal of the first clock signal end, the signal of the input signal end may be provided to the first node.
  • the second switching transistor when the second switching transistor is in an on state under the control of the signal at the first clock signal end, the signal of the first clock signal terminal may be provided to the second node.
  • the first control sub-circuit 2 may include, for example, a third switching transistor M3;
  • the control electrode of the third switching transistor M3 is connected to the first node A, the first pole of the third switching transistor M3 is connected to the first reference signal terminal Vref1, and the second pole of the third switching transistor M3 is connected to the second node B.
  • the third switching transistor M3 may be a P-type transistor.
  • the third switching transistor M3 may also be an N-type transistor, which is not limited herein.
  • the third switching transistor when the third switching transistor is in an on state under the control of the signal of the first node, the signal of the first reference signal end may be provided to the second node.
  • the second control sub-circuit 3 may include, for example, a fourth switching transistor M4 and a fifth switching transistor M5;
  • the control pole of the fourth switching transistor M4 is connected to the first node A, the first pole of the fourth switching transistor M4 is connected to the first reference signal terminal Vref1, and the second pole of the fourth switching transistor M4 is connected to the third node C;
  • the control electrode of the fifth switching transistor M5 is connected to the second node B, the first pole of the fifth switching transistor M5 is connected to the second reference signal terminal Vref2, and the second pole of the fifth switching transistor M5 is connected to the third node C.
  • the fourth switching transistor M4 and the fifth switching transistor M5 may be P-type transistors.
  • the fourth switching transistor M4 and the fifth switching transistor M5 may also be N-type transistors, which are not limited herein.
  • the fourth switching transistor when the fourth switching transistor is in an on state under the control of the signal of the first node, the signal of the first reference signal end may be provided to the third node.
  • the fifth switching transistor when the fifth switching transistor is in an on state under the control of the signal of the second node, the signal of the second reference signal terminal may be provided to the third node.
  • the third control sub-circuit 4 may specifically include: a sixth switching transistor M6;
  • the control electrode of the sixth switching transistor M6 is connected to the third node C.
  • the first pole of the sixth switching transistor M6 is connected to the first reference signal terminal Vref1, and the second pole of the sixth switching transistor M6 is connected to the first node A.
  • the sixth switching transistor M6 may be a P-type transistor.
  • the sixth switching transistor M6 may also be an N-type transistor, which is not limited herein.
  • the signal of the first reference signal end may be provided to the first node.
  • the first output sub-circuit 6 may include, for example, a seventh switching transistor M7;
  • the control pole of the seventh switching transistor M7 is connected to the first node A, the first pole of the seventh switching transistor M7 is connected to the second reference signal terminal Vref2, and the second pole of the seventh switching transistor M7 is connected to the output signal terminal (output terminal) ) connected.
  • the seventh switching transistor M7 may be a P-type transistor.
  • the seventh switching transistor M7 may also be an N-type transistor, which is not limited herein.
  • the signal of the second reference signal end when the seventh switching transistor is in an on state under the control of the signal of the first node, the signal of the second reference signal end may be provided to the output signal. end.
  • the second output sub-circuit 7 may include, for example, an eighth switching transistor M8;
  • the control electrode of the eighth switching transistor M8 is connected to the third node C, the first pole of the eighth switching transistor M8 is connected to the first reference signal terminal Vref1, and the second pole of the eighth switching transistor M8 is connected to the output signal terminal (output terminal) ) connected.
  • the eighth switching transistor M8 may be a P-type transistor.
  • the eighth switching transistor M8 may also be an N-type transistor, which is not limited herein.
  • the eighth switching transistor when the eighth switching transistor is in an on state under the control of the signal of the third node, the signal of the first reference signal end may be provided to the output signal. end.
  • the node stabilizing sub-circuit 5 may include, for example, a capacitor Cst; the first end of the capacitor Cst and the first node A is connected, and the second end of the capacitor Cst is connected to the second clock signal terminal CK2.
  • the capacitor in the shift register provided by the embodiment of the present disclosure, can maintain the potential of the signal of the first node stable. And when the first node is in the floating state, the voltage difference between the two ends of the capacitor can be stabilized due to the coupling of the capacitors, that is, the voltage difference between the first node and the second clock signal terminal is kept stable.
  • each sub-circuit in the shift register provided by the embodiment of the present disclosure.
  • the structure of each sub-circuit is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may be Other structures known to those skilled in the art are not limited herein.
  • all the switching transistors may be P-type transistors; or, as shown in FIG. 2b, all of them are exemplarily implemented.
  • the switching transistors can also be N-type transistors.
  • the P-type transistor is turned off under the action of the high potential signal, and is turned on under the action of the low potential signal;
  • the N-type transistor is turned on under the action of the high potential signal, and is turned off by the low potential signal.
  • the switching transistor mentioned in the above embodiments of the present disclosure may be a thin film transistor (TFT) or a metal oxide semiconductor field effect transistor (MOS) (Metal Oxide Scmiconductor), which is not limited herein.
  • TFT thin film transistor
  • MOS metal oxide semiconductor field effect transistor
  • the gates of the respective switching transistors are used as their gates, and according to the signals of the gates of the respective switching transistors and their types, the first pole may be used as a source and the second pole as a drain; or The first pole can be used as the drain and the second pole can be used as the source, which is not limited herein.
  • the signal of the first clock signal end is the same as the period of the signal of the second clock signal end, and the duration of the effective pulse signal of the first clock signal end accounts for one clock.
  • the percentage of the duration of the period is also the same as the percentage of the duration of the effective pulse signal at the second clock signal terminal for one clock cycle.
  • the effective pulse signal of the first clock signal terminal is used to control the first transistor and the fifth transistor to be turned on.
  • the duration of the effective pulse signal of the first clock signal terminal may be equal to 50% of the length of one clock cycle.
  • the second reference signal terminal connected to the seventh transistor is turned on and the first reference signal terminal connected to the eighth transistor is turned on.
  • the loss caused by the short circuit to the shift register when exemplarily implemented, the duration of the effective pulse signal of the first clock signal terminal may also be less than 50% of the length of one clock cycle.
  • the duration of the effective pulse signal of the first clock signal terminal CK1 is a percentage of the duration of one clock cycle and the duration of the effective pulse signal of the second clock signal terminal CK2 for one clock cycle. The percentage is less than 50%.
  • the effective pulse signal of the input signal input terminal is a high potential signal
  • the effective pulse signal of the first clock signal terminal CK1 and the effective pulse signal of the second clock signal terminal CK2 are both Low potential signal.
  • the effective pulse signal of the input signal terminal may also be a low potential signal
  • the effective pulse signal of the first clock signal end and the effective pulse signal of the second clock signal end are both high potential signals. In practical applications, the above percentage needs to be determined according to the actual application environment, and is not limited herein.
  • the signal of the first reference signal terminal Vref1 is a high potential signal
  • the signal of the second reference signal terminal Vref2 is a low potential signal
  • the output timing diagram is shown in Figure 3a. For example, four stages of T1, T2, T3, and T4 in the input-output timing diagram shown in Figure 3a are selected.
  • both the first switching transistor M1 and the second switching transistor M2 are turned on.
  • the first switching transistor M1 that is turned on supplies the high potential signal of the input signal terminal Input to the first node A, so that the signal of the first node A is a high potential signal, so the third switching transistor M3 and the fourth switching transistor M4 And the seventh switching transistor M7 is turned off.
  • the turned-on second switching transistor M2 supplies the low potential signal of the first clock signal terminal CK1 to the second node B, so that the signal of the second node B is a low potential signal, so the fifth switching transistor M5 is turned on to be the second
  • the low potential signal of the reference signal terminal Vref2 is supplied to the third node C, so that the signal of the third node C is a low potential signal, so that the sixth switching transistor M6 and the eighth switching transistor M8 are both turned on.
  • the turned-on sixth switching transistor M6 supplies the high potential signal of the first reference signal terminal Vref1 to the first node A, further causing the signal of the first node A to be a high potential signal.
  • the turned-on eighth switching transistor M8 supplies the high potential signal of the first reference signal terminal Vref1 to the output signal terminal Output (output terminal), so that the output signal terminal Output (output terminal) outputs a high potential signal.
  • both the first switching transistor M1 and the second switching transistor M2 are turned off. Since no additional signal is input to the second node B to charge it, the second node B remains as a low potential signal, so that the fifth switching transistor M5 is turned on to provide the low potential signal of the second reference signal terminal Vref2 to the first
  • the three-node C makes the signal of the third node C a low-potential signal, so that the sixth switching transistor M6 and the eighth switching transistor M8 are both turned on.
  • the turned-on sixth switching transistor M6 supplies the high potential signal of the first reference signal terminal Vref1 to the first node A, so that the signal of the first node A is a high potential signal, and thus the third switching transistor M3 and the fourth switching transistor M4 And the seventh switching transistor M7 is turned off.
  • the turned-on eighth switching transistor M8 supplies the high-potential signal of the first reference signal terminal Vref1 to the output signal terminal Output (output terminal), so that the output signal terminal Output (output terminal) outputs a high-potential signal.
  • the first reference signal terminal Vref1 of the M8 connection is turned on to short-circuit the loss caused by the shift register, thereby making the circuit output more stable.
  • both the first switching transistor M1 and the second switching transistor M2 are turned on.
  • the turned-on first switching transistor M1 supplies the low potential signal of the input signal terminal Input (input terminal) to the first node A, so that the signal of the first node A is a low potential signal, so the third switching transistor M3,
  • the four switching transistor M4 and the seventh switching transistor M7 are both turned on and the capacitor Cst is charged.
  • the turned-on third switching transistor M3 supplies the high potential signal of the first reference signal terminal Vref1 to the second node B, so that the signal of the second node B is a high potential signal, and thus the fifth switching transistor M5 is turned off.
  • the turned-on fourth switching transistor M4 supplies the high potential signal of the first reference signal terminal Vref1 to the third node C, so that the signal of the third node C is a high potential signal, and thus the sixth switching transistor M6 and the eighth switching transistor M8 Both are closed.
  • the turned-on seventh switching transistor M7 supplies the low potential signal of the second reference signal terminal Vref2 to the output signal terminal Output (output terminal), so that the output signal terminal Output (output terminal) outputs a low potential signal.
  • the fully turned-on third switching transistor M3 supplies the high potential signal of the first reference signal terminal Vref with no voltage loss to the second node B, so that the signal of the second node B is a high potential signal, thus making the fifth switching transistor M5 Completely cut off.
  • the fully turned-on fourth switching transistor M4 supplies the high-potential signal of the first reference signal terminal Vref1 with no voltage loss to the third node C, so that the signal of the third node C is a high-potential signal, thus making the sixth switching transistor M6 Both the eighth switching transistor M8 and the eighth switching transistor are completely turned off.
  • the fully turned-on seventh switching transistor M7 supplies the low-potential signal of the second reference signal terminal Vref2 with no voltage loss to the output signal terminal Output (output terminal), so that the output signal terminal Output (output terminal) completely outputs the low-potential signal.
  • the above shift register provided by the embodiment of the present disclosure repeats the operations of the T3 phase and the T4 phase until the next frame starts after the T4 phase.
  • the above shift register provided by the embodiment of the present disclosure can realize a signal stable shift output only by a simple structure of eight switching transistors and one capacitor.
  • the VGL represents the voltage of the low potential signal of the input signal terminal Input, the voltage of the low potential signal of the second reference signal terminal Vref2, and the voltage of the low potential signal of the second clock signal terminal CK2, respectively, and VGH represents the first
  • the voltage of the high potential signal of the two clock signal terminals CK2 and the threshold voltages of the respective switching transistors are all set to V th will be described as an example. In practical applications, when the gate of the P-type switching transistor is a low potential signal, the function of the switching transistor to transmit a low potential signal is related to its threshold voltage.
  • the gate of the first switching transistor M1 and the signal that needs to be transmitted are both low potential signals, so that the transmission to the first The voltage of the signal of node A is VGL-V th .
  • the gate of the seventh switching transistor and the signal that needs to be transmitted are also low-potential signals, so that the voltage of the signal outputted from the output terminal of the signal output terminal is VGL-2V th , resulting in the output terminal of the signal output.
  • the voltage of the low potential signal outputted by the terminal cannot reach VGL.
  • the potential of the signal of the first node A can be further pulled down due to the coupling action of the capacitance Cst, so that the first node A
  • the voltage of the signal jumps to VGL-V th -(VGH+
  • An exemplary working process is described by taking the structure of the shift register shown in FIG. 2a as an example.
  • An insertion phase T01 is inserted between the T1 phase and the T2 phase in the timing diagram of the embodiment shown in FIG. 3a.
  • the duration of the effective pulse signal of the input signal input (input) is extended by one clock cycle, and the corresponding input and output timing diagram is as shown in FIG. 3b.
  • five stages of T1, T01, T2, T3, and T4 are selected, wherein the insertion stage T01 is further divided into a first insertion sub-stage T011 and a second insertion sub-stage T012.
  • the specific working process at this stage is basically the same as the working process of the T1 phase in the embodiment shown in FIG. 3a above, and will not be described in detail herein.
  • both the first switching transistor M1 and the second switching transistor M2 are turned off. Since no additional signal is input to the second node B to charge it, the second node B remains as a low potential signal, so that the fifth switching transistor M5 is turned on to provide the low potential signal of the second reference signal terminal Vref2 to the first
  • the three-node C makes the signal of the third node C a low-potential signal, so that the sixth switching transistor M6 and the eighth switching transistor M8 are both turned on.
  • the turned-on sixth switching transistor M6 supplies the high potential signal of the first reference signal terminal Vref1 to the first node A, so that the signal of the first node A is a high potential signal, and thus the third switching transistor M3 and the fourth switching transistor M4 And the seventh switching transistor M7 is turned off.
  • the turned-on eighth switching transistor M8 supplies the high potential signal of the first reference signal terminal Vref1 to the output signal terminal Output (output terminal), so that the output signal terminal Output (output terminal) outputs a high potential signal.
  • both the first switching transistor M1 and the second switching transistor M2 are turned on.
  • the first switching transistor M1 that is turned on supplies the high potential signal of the input signal terminal Input to the first node A, so that the signal of the first node A is a high potential signal, so the third switching transistor M3 and the fourth switching transistor M4 And the seventh switching transistor M7 is turned off.
  • the turned-on second switching transistor M2 supplies the low potential signal of the first clock signal terminal CK1 to the second node B, so that the signal of the second node B is a low potential signal, so the fifth switching transistor M5 is turned on to be the second
  • the low potential signal of the reference signal terminal Vref2 is supplied to the third node C, so that the signal of the third node C is a low potential signal, so that the sixth switching transistor M6 and the eighth switching transistor M8 are both turned on.
  • the turned-on sixth switching transistor M6 supplies the high potential signal of the first reference signal terminal Vref1 to the first node A, further causing the signal of the first node A to be a high potential signal.
  • the turned-on eighth switching transistor M8 supplies the high potential signal of the first reference signal terminal Vref1 to the output signal terminal Output (output terminal), so that the output signal terminal Output (output terminal) outputs a high potential signal.
  • the specific working process at this stage is basically the same as the working process of the T2 phase in the embodiment shown in FIG. 3a above, and will not be described in detail herein.
  • the specific working process at this stage is basically the same as the working process of the T3 phase in the embodiment shown in FIG. 3a above, and will not be described in detail herein.
  • the specific working process at this stage is basically the same as the working process of the T4 stage in the embodiment shown in FIG. 3a above, and will not be described in detail herein.
  • the above shift register provided by the embodiment of the present disclosure repeats the operations of the T3 phase and the T4 phase until the next frame starts after the T4 phase.
  • the above shift register provided by the embodiment of the present disclosure can realize a signal stable shift output only by a simple structure of eight switching transistors and one capacitor.
  • the simulation process of the shift register is simulated by using the simulation simulation timing diagrams of the input signals shown in FIG. 4a and FIG. 4b.
  • the ordinate represents voltage and the abscissa represents time, wherein L1 in Fig. 4a represents the signal of the input signal input (Input), and L2 in Fig. 4b represents the first clock signal terminal CK1.
  • Signal, L3 represents the signal of the second clock signal terminal CK2.
  • the signal of the output signal output (output) changes as shown in FIG. 4c.
  • the ordinate represents voltage and the abscissa represents time, and as can be seen from FIG. 4c, the implementation of the present disclosure
  • the above-mentioned shift register provided by the example is stable in operation, and can output the signal L4 which is stable at the output end of the signal output terminal.
  • FIG. 2a An exemplary working process is described by taking the structure of the shift register shown in FIG. 2a as an example.
  • Two insertion stages T01 are inserted between the T1 phase and the T2 phase in the timing diagram of the embodiment shown in FIG. 3a.
  • T02 that is, based on the embodiment shown in FIG. 3a above, the duration of the effective pulse signal of the input signal input (input) is extended by two clock cycles, and the corresponding input and output timing diagram is as shown in FIG. 3c.
  • FIG. 3c In the timing diagram shown in FIG.
  • T01 is further divided into a first insertion sub-stage T011 and a second insertion sub-stage T012
  • T02 is further divided into a first insertion sub-phase T021 and a second insertion sub-phase T022.
  • the specific working process at this stage is basically the same as the working process of the T1 phase in the embodiment shown in FIG. 3a above, and will not be described in detail herein.
  • both the first switching transistor M1 and the second switching transistor M2 are turned off. Since no additional signal is input to the second node B to charge it, the second node B remains as a low potential signal, so that the fifth switching transistor M5 is turned on to provide the low potential signal of the second reference signal terminal Vref2 to the first
  • the three-node C makes the signal of the third node C a low-potential signal, so that the sixth switching transistor M6 and the eighth switching transistor M8 are both turned on.
  • the turned-on sixth switching transistor M6 supplies the high potential signal of the first reference signal terminal Vref1 to the first node A, so that the signal of the first node A is a high potential signal, and thus the third switching transistor M3 and the fourth switching transistor M4 And the seventh switching transistor M7 is turned off.
  • the turned-on eighth switching transistor M8 supplies the high potential signal of the first reference signal terminal Vref1 to the output signal terminal Output (output terminal), so that the output signal terminal Output (output terminal) outputs a high potential signal.
  • both the first switching transistor M1 and the second switching transistor M2 are turned on.
  • the turned-on first switching transistor M1 supplies the high-potential signal of the input signal terminal Input (input terminal) to the first node A, so that the signal of the first node A is a high-potential signal, so the third switching transistor M3,
  • the four switching transistors M4 and the seventh switching transistor M7 are both turned off.
  • the turned-on second switching transistor M2 supplies the low potential signal of the first clock signal terminal CK1 to the second node B, so that the signal of the second node B is a low potential signal, so the fifth switching transistor M5 is turned on to be the second
  • the low potential signal of the reference signal terminal Vref2 is supplied to the third node C, so that the signal of the third node C is a low potential signal, so that the sixth switching transistor M6 and the eighth switching transistor M8 are both turned on.
  • the turned-on sixth switching transistor M6 supplies the high potential signal of the first reference signal terminal Vref1 to the first node A, further causing the signal of the first node A to be a high potential signal.
  • the turned-on eighth switching transistor M8 supplies the high potential signal of the first reference signal terminal Vref1 to the output signal terminal Output (output terminal), so that the output signal terminal Output (output terminal) outputs a high potential signal.
  • both the first switching transistor M1 and the second switching transistor M2 are turned off. Since no additional signal is input to the second node B to charge it, the second node B remains as a low potential signal, so that the fifth switching transistor M5 is turned on to provide the low potential signal of the second reference signal terminal Vref2 to the first
  • the three-node C makes the signal of the third node C a low-potential signal, so that the sixth switching transistor M6 and the eighth switching transistor M8 are both turned on.
  • the turned-on sixth switching transistor M6 supplies the high potential signal of the first reference signal terminal Vref1 to the first node A, so that the signal of the first node A is a high potential signal, and thus the third switching transistor M3 and the fourth switching transistor M4 And the seventh switching transistor M7 is turned off.
  • the turned-on eighth switching transistor M8 supplies the high potential signal of the first reference signal terminal Vref1 to the output signal terminal Output (output terminal), so that the output signal terminal Output (output terminal) outputs a high potential signal.
  • both the first switching transistor M1 and the second switching transistor M2 are turned on.
  • the turned-on first switching transistor M1 supplies the high-potential signal of the input signal terminal Input (input terminal) to the first node A, so that the signal of the first node A is a high-potential signal, so the third switching transistor M3,
  • the four switching transistors M4 and the seventh switching transistor M7 are both turned off.
  • the turned-on second switching transistor M2 supplies the low potential signal of the first clock signal terminal CK1 to the second node B, so that the signal of the second node B is a low potential signal, so the fifth switching transistor M5 is turned on to be the second
  • the low potential signal of the reference signal terminal Vref2 is supplied to the third node C, so that the signal of the third node C is a low potential signal, so that the sixth switching transistor M6 and the eighth switching transistor M8 are both turned on.
  • the turned-on sixth switching transistor M6 supplies the high potential signal of the first reference signal terminal Vref1 to the first node A, further causing the signal of the first node A to be a high potential signal.
  • the turned-on eighth switching transistor M8 supplies the high potential signal of the first reference signal terminal Vref1 to the output signal terminal Output (output terminal), so that the output signal terminal Output (output terminal) outputs a high potential signal.
  • the above shift register provided by the embodiment of the present disclosure repeats the operations of the T3 phase and the T4 phase until the next frame starts after the T4 phase.
  • the above shift register provided by the embodiment of the present disclosure can realize a signal stable shift output only by a simple structure of eight switching transistors and one capacitor.
  • the above-mentioned shift register provided by the embodiment of the present disclosure extends the duration of the effective pulse signal of the input signal terminal by one clock based on the signal of the input signal terminal of the embodiment shown in FIG. 3a.
  • the signal period, the output signal end can output the signal of the corresponding duration in the embodiment shown in FIG. 3b, and extend the duration of the effective pulse signal at the input signal end by two clock signal periods, and the output signal end can output the above-mentioned FIG. 3c.
  • the signal corresponding to the duration, and so on, by extending the duration of the effective pulse signal the output signal terminal can output a signal of the same duration as the effective pulse signal of the input signal terminal.
  • the above shift register can control the duration of the effective pulse signal of the signal outputted by the output signal terminal only by changing the duration of the effective pulse signal at the input signal terminal, without the need for circuit modification and process change, thereby reducing the complexity of the process. ,cut costs.
  • the signal of the first reference signal terminal Vref1 is a low potential signal
  • the second reference signal terminal is The signal of Vref2 is a high potential signal
  • the signal of the input signal terminal Input (input terminal) is shown in FIG. 3a.
  • the potentials of the corresponding signals in Fig. 3b and Fig. 3c are opposite, that is, the high potential of each signal in Figs. 3a, 3b, and 3c becomes a low potential, and the low potential of each signal becomes a high potential.
  • each of the switching transistors in the shift register is an N-type transistor
  • the operation process when each of the switching transistors in the shift register is an N-type transistor can be referred to the operation process in the above embodiments, and only the high-potential signal of the control electrode of each switching transistor in each of the above embodiments is used. It is only necessary to change the low potential signal and the low potential signal of the control electrode of each switching transistor to a high potential signal.
  • the embodiment of the present disclosure further provides a driving method for any one of the above shift registers provided by the embodiment of the present disclosure. As shown in FIG. 5, the method includes: a first stage, a second stage, a third stage, and Fourth stage;
  • the input sub-circuit provides the signal of the input signal end to the first node under the control of the first clock signal end, and provides the signal of the first clock signal end to the second node;
  • the second control sub-circuit is The signal of the second reference signal end is provided to the third node under the control of the signal of the second node;
  • the third control sub-circuit provides the signal of the first reference signal end to the first node under the control of the third node;
  • the second output sub- The circuit supplies the signal of the first reference signal end to the output signal end under the control of the signal of the third node;
  • the second control sub-circuit provides the signal of the second reference signal end to the third node under the control of the signal of the second node;
  • the third control sub-circuit sets the first reference under the control of the third node.
  • the signal of the signal end is provided to the first node;
  • the second output sub-circuit provides the signal of the first reference signal end to the output signal end under the control of the signal of the third node;
  • the input sub-circuit provides the signal of the input signal end to the first node under the control of the first clock signal end, and provides the signal of the first clock signal end to the second node;
  • the first control sub-circuit is The signal of the first reference signal end is provided to the second node under the control of the first node;
  • the second control sub-circuit provides the signal of the first reference signal end to the third node under the control of the signal of the first node;
  • the first output sub- The circuit provides the signal of the second reference signal end to the output signal end under the control of the signal of the first node;
  • the node stabilization sub-circuit stabilizes the potential of the first node; the first control sub-circuit provides the signal of the first reference signal end to the second node under the control of the first node; the second control sub-circuit is in the The signal of the first reference signal end is supplied to the third node under the control of the signal of the node; the first output sub-circuit provides the signal of the second reference signal end to the output signal end under the control of the signal of the first node.
  • the driving method of the above shift register provided by the embodiment of the present disclosure can stably output the shifted signal, simplify the preparation process, and reduce the production cost.
  • the method may further include: at least one insertion phase; wherein the insertion phase includes the first insertion sub-phase And the second insertion sub-phase;
  • the second control sub-circuit provides the signal of the second reference signal end to the third node under the control of the signal of the second node;
  • the third control sub-circuit sets the first reference under the control of the third node The signal of the signal end is provided to the first node;
  • the second output sub-circuit provides the signal of the first reference signal end to the output signal end under the control of the signal of the third node;
  • the input sub-circuit provides the signal of the input signal end to the first node under the control of the first clock signal end, and provides the signal of the first clock signal end to the second node;
  • the second control sub-circuit is The signal of the second reference signal end is provided to the third node under the control of the signal of the second node;
  • the third control sub-circuit provides the signal of the first reference signal end to the first node under the control of the third node;
  • the second output sub- The circuit supplies the signal of the first reference signal terminal to the output signal terminal under the control of the signal of the third node.
  • the above driving method provided by the embodiment of the present disclosure can control the duration of the effective pulse signal of the signal outputted by the signal output terminal by inserting at least one insertion phase, without requiring circuit modification and process change, thereby simplifying
  • the preparation process reduces the production cost and is beneficial to realize the narrow bezel design of the panel in the display device.
  • an insertion phase is inserted between the first phase and the second phase, and the working process corresponds to the embodiment shown in FIG. 3b above.
  • Two insertion phases are inserted between the first phase and the second phase, the working process of which corresponds to the embodiment shown in Figure 3c above.
  • three, four or more insertion phases can be inserted between the first phase and the second phase, and so on, and will not be described herein.
  • the signal of the first clock signal end is the same as the period of the signal of the second clock signal end, and the duration of the effective pulse signal of the first clock signal end accounts for one clock cycle.
  • the percentage of the duration is also the same as the percentage of the duration of the effective pulse signal of the second clock signal for one clock cycle.
  • the effective pulse signal of the first clock signal terminal is used to control the first transistor and the fifth transistor to be turned on.
  • the duration of the effective pulse signal of the first clock signal terminal may be equal to 50% of the length of one clock cycle.
  • the second reference signal terminal connected to the seventh transistor is turned on and the first reference signal terminal connected to the eighth transistor is turned on.
  • the loss caused by the short circuit to the shift register in a specific implementation, the duration of the effective pulse signal of the first clock signal end may be less than 50% of the length of one clock cycle.
  • the duration of the effective pulse signal of the first clock signal terminal CK1 occupies a percentage of the duration of one clock cycle and the duration of the effective pulse signal of the second clock signal terminal CK2 occupies one clock cycle. The percentage of the duration is less than 50%.
  • the effective pulse signal of the input signal input terminal is a high potential signal
  • the effective pulse signal of the first clock signal terminal CK1 and the effective pulse signal of the second clock signal terminal CK2 are both Is a low potential signal
  • the effective pulse signal of the input signal terminal may also be a low potential signal
  • the effective pulse signal of the first clock signal end and the effective pulse signal of the second clock signal end are both high potential signals.
  • the above percentage needs to be determined according to the actual application environment, and is not limited herein.
  • an embodiment of the present disclosure further provides a driving control circuit, as shown in FIG. 6, including: a plurality of cascaded shift registers provided by the embodiments of the present disclosure: SR(1), SR (2)...SR(n)...SR(N-1), SR(N) (total N shift registers, 1 ⁇ n ⁇ N); N is a positive integer, and n is a positive integer;
  • the input signal input (input) of the first stage shift register SR(1) is connected to the start signal terminal STV;
  • the input signal inputs Input (input) of the remaining stages of shift registers SR(n) are respectively adjacent to the previous stage shift register SR(n-1)
  • the output signal terminals are connected.
  • each shift register in the above-mentioned drive control circuit is the same as the above-described shift register of the present disclosure, and the details are not described again.
  • the above-mentioned driving control circuit provided by the embodiment of the present disclosure can be applied to the illumination control signal for providing the illumination control transistor, and can also be applied to the gate scan signal for providing the scan control transistor, which is not limited herein.
  • the first clock signal terminal CK1 of the 2k-1th stage shift register and the second clock signal of the 2kth stage shift register are shown in FIG.
  • the terminal CK2 is connected to the same clock terminal, that is, the first clock terminal ck1; the second clock signal terminal CK2 of the 2k-1th stage shift register and the first clock signal terminal CK1 of the 2kth stage shift register are both connected to the same clock terminal.
  • the second clock terminal ck2 is connected; wherein k is a positive integer.
  • the first reference signal terminals Vref1 of the shift registers SR(n) of the respective stages are the same as the same signal terminal, that is, the first The reference terminal vref1 is connected; the second reference signal terminal Vref2 of each stage shift register SR(n) is connected to the same signal end, that is, the second reference terminal vref1.
  • an embodiment of the present disclosure further provides a display device including the above-described drive control circuit provided by an embodiment of the present disclosure.
  • a display device including the above-described drive control circuit provided by an embodiment of the present disclosure.
  • the display device reference may be made to the embodiment of the shift register described above, and the repeated description is omitted.
  • the exemplary display device provided by the embodiment of the present disclosure may be an organic light emitting display device, or may be a liquid crystal display device, which is not limited herein.
  • a plurality of organic light emitting diodes, a pixel compensation circuit connected to each of the organic light emitting diodes, a plurality of gate lines, and a plurality of light emission control signal lines are generally provided.
  • a general pixel compensation circuit is provided with an emission control transistor for controlling the illumination of the organic light emitting diode and a scan control transistor for controlling the input of the data signal.
  • the control electrode of the light-emitting control transistor is connected to the light-emission control signal line corresponding to the row for receiving the light-emitting control signal; the control electrode of the scan control transistor is connected with the gate line corresponding to the row, and is used for receiving the gate scan signal.
  • the driving control circuit can be applied to the light emission control signal for providing the light emission control transistor, and each stage shift in the drive control circuit
  • the signal output of the bit register is connected to an illumination control signal line.
  • the drive control circuit can also be applied to a gate scan signal that provides a scan control transistor.
  • the drive control circuit is a gate drive circuit, and a signal output terminal and a gate line of each stage shift register in the drive control circuit are driven. connection.
  • two driving control circuits may be disposed, wherein one driving control circuit is applied to an illumination control signal for providing an illumination control transistor, and the driving control circuit is The signal output end of each stage shift register is connected to one illumination control signal line; the other drive control circuit is applied as a gate drive circuit to the gate scan signal for providing the scan control transistor, and each stage in the drive control circuit The signal output end of the shift register is connected to a gate line, which is not limited herein.
  • the display device provided by the embodiment of the present disclosure is a liquid crystal display device
  • a plurality of pixel electrodes, a switching transistor connected to each pixel electrode, and a plurality of gates are generally disposed.
  • the control electrode of each row of switching transistors is connected to the corresponding gate line of the row.
  • the above-described driving control circuit provided by the embodiment of the present disclosure can be applied as a gate driving circuit to a gate driving signal for providing a switching transistor, and a signal output terminal of each stage shift register in the driving control circuit is connected to a gate line.
  • the display device may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • Other indispensable components of the display device are understood by those skilled in the art, and are not described herein, nor should they be construed as limiting the disclosure.
  • the shift register, the driving method thereof, the driving control circuit and the display device include: an input sub-circuit, a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, a node stabilization sub-circuit, a first output sub-circuit and a second output sub-circuit;
  • the input sub-circuit is configured to provide a signal of the input signal end to the first node under the control of the first clock signal end, and provide the signal of the first clock signal end to the second node a first control sub-circuit for providing a signal of the first reference signal end to the second node under the control of the first node;
  • the second control sub-circuit for using the first reference signal end under the control of the signal of the first node
  • the signal is provided to the third node, and the signal of the second reference signal end is provided to the third node under the control of the signal of the second node;
  • the third control sub-circuit is configured to transmit the signal of the first reference signal end under
  • the shift register provided by the embodiment of the present disclosure can make the output signal terminal output the shifted signal stably through a simple structure and fewer signal lines through the mutual cooperation of the above seven sub-circuits, thereby simplifying the preparation process and reducing the manufacturing process. Cost of production. And through the mutual cooperation of the above seven sub-circuits, the duration of the effective pulse signal of the signal outputted by the signal output end can be controlled only by changing the duration of the effective pulse signal at the input signal end, without the need for circuit modification and process change. Thereby, the preparation process can be simplified, the production cost can be reduced, and the narrow bezel design of the panel in the display device can be realized.

Abstract

公开了一种移位寄存器、其驱动方法、驱动控制电路以及显示装置。该移位寄存器包括：输入子电路（1）、第一控制子电路（2）、第二控制子电路（3）、第三控制子电路（4）、节点稳定子电路（5）、第一输出子电路（6）以及第二输出子电路（7）。

Description

一种移位寄存器、其驱动方法、驱动控制电路及显示装置
相关申请的交叉引用
本申请要求于2017年8月21日提交的中国专利申请第201710717661.X号的优先权，该申请的公开通过引用被全部合并于此。
技术领域
本公开涉及一种移位寄存器、其驱动方法、驱动控制电路及显示装置。
背景技术
随着显示技术的飞速发展，显示面板越来越向着高集成度和低成本的方向发展。其中，阵列基板行驱动(Gate Driver on Array，GOA)技术将薄膜晶体管(Thin Film Transistor，TFT)栅极开关驱动控制电路集成在显示面板的阵列基板上以形成对显示面板中的TFT的栅极的控制，从而可以省去栅极集成电路(Integrated Circuit，IC)的绑定(Bonding)区域以及扇出(Fan-out)区域的布线空间，不仅可以在材料成本和制备工艺两方面降低产品成本，而且可以使显示面板做到两边对称和窄边框的美观设计。并且，这种集成工艺还可以省去栅极扫描线方向的Bonding工艺，从而提高产能和良率。
一般作为栅极驱动电路的驱动控制电路是由多个级联的移位寄存器组成，通过各级移位寄存器实现依次向显示面板上的各行栅线输入栅极扫描信号。
发明内容
本公开实施例提供了一种移位寄存器，包括：输入子电路、第一控制子电路、第二控制子电路、第三控制子电路、节点稳定子电路、第一输出子电路以及第二输出子电路；
所述输入子电路分别与输入信号端、第一时钟信号端、第一节点以及第二节点相连，用于在所述第一时钟信号端的控制下，将所述输入信号端的信号提供给所述第一节点，以及将所述第一时钟信号端的信号提供给所述第二节点；
所述第一控制子电路分别与第一参考信号端、所述第一节点以及所述第二节点相 连，用于在所述第一节点的控制下将所述第一参考信号端的信号提供给所述第二节点；
所述第二控制子电路分别与所述第一参考信号端、第二参考信号端、所述第一节点、所述第二节点以及第三节点相连，用于在所述第一节点的信号的控制下将所述第一参考信号端的信号提供给所述第三节点，在所述第二节点的信号的控制下将所述第二参考信号端的信号提供给所述第三节点；
所述第三控制子电路分别与所述第一参考信号端、所述第一节点以及所述第三节点相连，用于在所述第三节点的控制下将所述第一参考信号端的信号提供给所述第一节点；
所述节点稳定子电路与所述第一节点相连，用于稳定所述第一节点的电位；
所述第一输出子电路分别与所述第一节点、所述第二参考信号端以及所述移位寄存器的输出信号端相连，用于在所述第一节点的信号的控制下将所述第二参考信号端的信号提供给所述输出信号端；
所述第二输出子电路分别与所述第三节点、所述第一参考信号端以及所述输出信号端相连，用于在所述第三节点的信号的控制下将所述第一参考信号端的信号提供给所述输出信号端。
可选地，在本公开实施例提供的上述移位寄存器中，所述输入子电路包括：第一开关晶体管与第二开关晶体管；
所述第一开关晶体管的控制极与所述第一时钟信号端相连，所述第一开关晶体管的第一极与所述输入信号端相连，所述第一开关晶体管的第二极与所述第一节点相连；
所述第二开关晶体管的控制极与第一极均与所述第一时钟信号端相连，所述第二开关晶体管的第二极与所述第二节点相连。
可选地，在本公开实施例提供的上述移位寄存器中，所述第一控制子电路包括：第三开关晶体管；
所述第三开关晶体管的控制极与所述第一节点相连，所述第三开关晶体管的第一极与所述第一参考信号端相连，所述第三开关晶体管的第二极与所述第二节点相连。
可选地，在本公开实施例提供的上述移位寄存器中，所述第二控制子电路包括：第四开关晶体管与第五开关晶体管；
所述第四开关晶体管的控制极与所述第一节点相连，所述第四开关晶体管的第一极与所述第一参考信号端相连，所述第四开关晶体管的第二极与所述第三节点相连；
所述第五开关晶体管的控制极与所述第二节点相连，所述第五开关晶体管的第一极与所述第二参考信号端相连，所述第五开关晶体管的第二极与所述第三节点相连。
可选地，在本公开实施例提供的上述移位寄存器中，所述第三控制子电路包括：第六开关晶体管；
所述第六开关晶体管的控制极与所述第三节点相连，所述第六开关晶体管的第一极与所述第一参考信号端相连，所述第六开关晶体管的第二极与所述第一节点相连。
可选地，在本公开实施例提供的上述移位寄存器中，所述第一输出子电路包括：第七开关晶体管；
所述第七开关晶体管的控制极与所述第一节点相连，所述第七开关晶体管的第一极与所述第二参考信号端相连，所述第七开关晶体管的第二极与所述输出信号端相连。
可选地，在本公开实施例提供的上述移位寄存器中，所述第二输出子电路包括：第八开关晶体管；
所述第八开关晶体管的控制极与所述第三节点相连，所述第八开关晶体管的第一极与所述第一参考信号端相连，所述第八开关晶体管的第二极与所述输出信号端相连。
可选地，在本公开实施例提供的上述移位寄存器中，各个开关晶体管均为P型晶体管，各个开关晶体管的第一极为P型晶体管的源极，以及各个开关晶体管的第二极为P型晶体管的漏极。
可选地，在本公开实施例提供的上述移位寄存器中，各个开关晶体管均为N型晶体管，各个开关晶体管的第一极为N型晶体管的漏极，以及各个开关晶体管的第二极为N型晶体管的源极。
可选地，在本公开实施例提供的上述移位寄存器中，所述节点稳定子电路包括电容；所述电容的第一端与所述第一节点相连，所述电容的第二端与第二时钟信号端相连。
相应地，本公开实施例还提供了一种驱动控制电路，包括：多个级联的本公开实施例提供的上述任一种移位寄存器；
第一级移位寄存器的输入信号端与起始信号端相连；
除所述第一级移位寄存器之外，其余各级移位寄存器的输入信号端分别与其相邻的上一级移位寄存器的输出信号端相连。
相应地，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述驱动控制电路。
可选地，在本公开实施例提供的上述显示装置中，所述显示装置包括多条发光控制信号线；所述驱动控制电路中的每一级移位寄存器的信号输出端与一条发光控制信号线连接。
可选地，在本公开实施例提供的上述显示装置中，所述驱动控制电路为栅极驱动电路。
相应地，本公开实施例还提供了一种本公开实施例提供的上述任一种移位寄存器的驱动方法，包括：第一阶段、第二阶段、第三阶段以及第四阶段；
在所述第一阶段，所述输入子电路在所述第一时钟信号端的控制下，将所述输入信号端的信号提供给所述第一节点，以及将所述第一时钟信号端的信号提供给所述第二节点；所述第二控制子电路在所述第二节点的信号的控制下将所述第二参考信号端的信号提供给所述第三节点；所述第三控制子电路在所述第三节点的控制下将所述第一参考信号端的信号提供给所述第一节点；所述第二输出子电路在所述第三节点的信号的控制下将所述第一参考信号端的信号提供给所述输出信号端；
在所述第二阶段，所述第二控制子电路在所述第二节点的信号的控制下将所述第二参考信号端的信号提供给所述第三节点；所述第三控制子电路在所述第三节点的控制下将所述第一参考信号端的信号提供给所述第一节点；所述第二输出子电路在所述第三节点的信号的控制下将所述第一参考信号端的信号提供给所述输出信号端；
在所述第三阶段，所述输入子电路在所述第一时钟信号端的控制下，将所述输入信号端的信号提供给所述第一节点，以及将所述第一时钟信号端的信号提供给所述第二节点；所述第一控制子电路在所述第一节点的控制下将所述第一参考信号端的信号提供给所述第二节点；所述第二控制子电路在所述第一节点的信号的控制下将所述第一参考信号端的信号提供给所述第三节点；所述第一输出子电路在所述第一节点的信号的控制下将所述第二参考信号端的信号提供给所述输出信号端；
在所述第四阶段，所述节点稳定子电路稳定所述第一节点的电位；所述第一控制子电路在所述第一节点的控制下将所述第一参考信号端的信号提供给所述第二节点；所述第二控制子电路在所述第一节点的信号的控制下将所述第一参考信号端的信号提供给所述第三节点；所述第一输出子电路在所述第一节点的信号的控制下将所述第二参考信号端的信号提供给所述输出信号端。
可选地，在本公开实施例提供的上述驱动方法中，在所述第一阶段之后，且在所述 第二阶段之前，还包括：至少一个插入阶段；其中，所述插入阶段包括第一插入子阶段与第二插入子阶段；
在所述第一插入子阶段，所述第二控制子电路在所述第二节点的信号的控制下将所述第二参考信号端的信号提供给所述第三节点；所述第三控制子电路在所述第三节点的控制下将所述第一参考信号端的信号提供给所述第一节点；所述第二输出子电路在所述第三节点的信号的控制下将所述第一参考信号端的信号提供给所述输出信号端；
在所述第二插入子阶段，所述输入子电路在所述第一时钟信号端的控制下，将所述输入信号端的信号提供给所述第一节点，以及将所述第一时钟信号端的信号提供给所述第二节点；所述第二控制子电路在所述第二节点的信号的控制下将所述第二参考信号端的信号提供给所述第三节点；所述第三控制子电路在所述第三节点的控制下将所述第一参考信号端的信号提供给所述第一节点；所述第二输出子电路在所述第三节点的信号的控制下将所述第一参考信号端的信号提供给所述输出信号端。
可选地，在本公开实施例提供的上述驱动方法中，所述第一时钟信号端的信号与所述第二时钟信号端的信号的周期相同，并且所述第一时钟信号端的有效脉冲信号的时长占一个时钟周期的时长的百分比与所述第二时钟信号端的有效脉冲信号的时长占一个所述时钟周期的时长的百分比相同；
所述第一时钟信号端的有效脉冲信号的时长占一个所述时钟周期的时长的百分比小于或等于50％。
附图说明
图1为本公开实施例提供的移位寄存器的结构示意图；
图2a为本公开实施例提供的移位寄存器的示例性的结构示意图；
图2b为本公开实施例提供的移位寄存器的示例性的结构示意图；
图3a为图2a所示的移位寄存器的示意性的输入输出时序图；
图3b为图2a所示的移位寄存器的示意性的输入输出时序图；
图3c为图2a所示的移位寄存器的示意性的输入输出时序图；
图4a为本公开实施例中的示意性的仿真模拟示意图；
图4b为本公开实施例中的示意性的仿真模拟示意图；
图4c为本公开实施例中的示意性的仿真模拟示意图；
图5为本公开实施例提供的驱动方法的流程图；
图6为本公开实施例提供的驱动控制电路的结构示意图。
具体实施方式
为了使本公开的目的，技术方案和优点更加清楚，下面结合附图，对本公开实施例提供的移位寄存器、其驱动方法、驱动控制电路及显示装置的具体实施方式进行详细地说明。应当理解，下面所描述的优选实施例仅用于说明和解释本公开，并不用于限定本公开。并且在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
目前，虽然可以通过输入较多的不同功能的控制信号来实现栅极扫描信号的输出，但是这样导致栅极驱动电路中组成各级移位寄存器的开关晶体管的个数较多，以及各开关晶体管之间连接的具体结构也比较复杂，导致工艺难度加大，生产成本增加，甚至由于需要使用较多的信号线将多种不同功能的控制信号输入各级移位寄存器，从而造成显示面板的开口率降低，使得该显示面板不具备竞争力。
本公开实施例提供一种移位寄存器、其驱动方法、驱动控制电路及显示装置，用以通过简单的结构，稳定的输出信号。
本公开的有益效果如下：
本公开实施例提供的移位寄存器、其驱动方法、驱动控制电路及显示装置，包括：输入子电路、第一控制子电路、第二控制子电路、第三控制子电路、节点稳定子电路、第一输出子电路以及第二输出子电路；通过上述七个子电路的相互配合，可以通过简单的结构以及较少的信号线即可使输出信号端稳定的输出移位后的信号，从而简化制备工艺，降低生产成本。并且，通过上述七个子电路的相互配合，仅需通过改变输入信号端的有效脉冲信号的时长就可以控制信号输出端输出的信号的有效脉冲信号的时长，而不需要进行电路的改动和工艺的改变，从而可以简化制备工艺，降低生产成本，有利于实现显示装置中面板的窄边框设计。
本公开实施例提供了一种移位寄存器，如图1所示，包括：输入子电路1、第一控制子电路2、第二控制子电路3、第三控制子电路4、节点稳定子电路5、第一输出子电路6以及第二输出子电路7；
输入子电路1分别与输入信号端Input(输入端)、第一时钟信号端CK1、第一节点A以及第二节点B相连，用于在第一时钟信号端CK1的控制下，将输入信号端Input (输入端)的信号提供给第一节点A，以及将第一时钟信号端CK1的信号提供给第二节点B；
第一控制子电路2分别与第一参考信号端Vref1、第一节点A以及第二节点B相连，用于在第一节点A的控制下将第一参考信号端Vref1的信号提供给第二节点B；
第二控制子电路3分别与第一参考信号端Vref1、第二参考信号端Vref2、第一节点A、第二节点B以及第三节点C相连，用于在第一节点A的信号的控制下将第一参考信号端Vref1的信号提供给第三节点C，在第二节点B的信号的控制下将第二参考信号端Vref2的信号提供给第三节点C；
第三控制子电路4分别与第一参考信号端Vref1、第一节点A以及第三节点C相连，用于在第三节点C的控制下将第一参考信号端Vref1的信号提供给第一节点A；
节点稳定子电路5与第一节点A相连，用于稳定第一节点A的电位；
第一输出子电路6分别与第一节点A、第二参考信号端Vref2以及移位寄存器的输出信号端Output(输出端)相连，用于在第一节点A的信号的控制下将第二参考信号端Vref2的信号提供给输出信号端Output(输出端)；
第二输出子电路7分别与第三节点C、第一参考信号端Vref1以及输出信号端Output(输出端)相连，用于在第三节点C的信号的控制下将第一参考信号端Vref1的信号提供给输出信号端Output(输出端)。
本公开实施例提供的移位寄存器，包括：输入子电路1、第一控制子电路2、第二控制子电路3、第三控制子电路4、节点稳定子电路5、第一输出子电路6以及第二输出子电路7；输入子电路1用于在第一时钟信号端的控制下，将输入信号端的信号提供给第一节点，以及将第一时钟信号端的信号提供给第二节点；第一控制子电路2用于在第一节点的控制下将第一参考信号端的信号提供给第二节点；第二控制子电路3用于在第一节点的信号的控制下将第一参考信号端的信号提供给第三节点，在第二节点的信号的控制下将第二参考信号端的信号提供给第三节点；第三控制子电路4用于在第三节点的控制下将第一参考信号端的信号提供给第一节点；节点稳定子电路5用于稳定第一节点的电位；第一输出子电路6用于在第一节点的信号的控制下将第二参考信号端的信号提供给输出信号端；第二输出子电路7用于在第三节点的信号的控制下将第一参考信号端的信号提供给输出信号端。本公开实施例提供的移位寄存器通过上述七个子电路的相互配合，可以通过简单的结构以及较少的信号线即可使输出信号端稳定的输出移位后的 信号，从而简化制备工艺，降低生产成本。并且通过上述七个子电路的相互配合，仅需通过改变输入信号端的有效脉冲信号的时长就可以控制信号输出端输出的信号的有效脉冲信号的时长，而不需要进行电路的改动和工艺的改变，从而可以简化制备工艺，降低生产成本，有利于实现显示装置中面板的窄边框设计。
在示例性地实施时，在本公开实施例提供的移位寄存器中，输入信号端的有效脉冲信号为高电位信号，第一参考信号端的信号为高电位信号，第二参考信号端的信号为低电位信号。或者，输入信号端的有效脉冲信号为低电位信号，第一参考信号端的信号为低电位信号，第二参考信号端的信号为高电位信号。
下面结合示例性实施例，对本公开提供的移位寄存器进行详细说明。需要说明的是，本实施例是为了更好的解释本公开，但不限制本公开。
在示例性地实施时，在本公开实施例提供的移位寄存器中，如图2a与图2b所示，输入子电路1例如可以包括：第一开关晶体管M1与第二开关晶体管M2；
第一开关晶体管M1的控制极与第一时钟信号端CK1相连，第一开关晶体管M1的第一极与输入信号端Input(输入端)相连，第一开关晶体管M1的第二极与第一节点A相连；
第二开关晶体管M2的控制极与第一极均与第一时钟信号端CK1相连，第二开关晶体管M2的第二极与第二节点B相连。
在示例性地实施时，在本公开实施例提供的移位寄存器中，如图2a所示，第一开关晶体管M1与第二开关晶体管M2可以为P型晶体管。或者，如图2b所示，第一开关晶体管M1与第二开关晶体管M2也可以为N型晶体管，在此不作限定。
在示例性地实施时，在本公开实施例提供的移位寄存器中，第一开关晶体管在第一时钟信号端的信号的控制下处于导通状态时，可以将输入信号端的信号提供给第一节点。第二开关晶体管在第一时钟信号端的信号的控制下处于导通状态时，可以将第一时钟信号端的信号提供给第二节点。
在示例性地实施时，在本公开实施例提供的移位寄存器中，如图2a与图2b所示，第一控制子电路2例如可以包括：第三开关晶体管M3；
第三开关晶体管M3的控制极与第一节点A相连，第三开关晶体管M3的第一极与第一参考信号端Vref1相连，第三开关晶体管M3的第二极与第二节点B相连。
在示例性地实施时，在本公开实施例提供的移位寄存器中，如图2a所示，第三开 关晶体管M3可以为P型晶体管。或者，如图2b所示，第三开关晶体管M3也可以为N型晶体管，在此不作限定。
在示例性地实施时，在本公开实施例提供的移位寄存器中，第三开关晶体管在第一节点的信号的控制下处于导通状态时，可以将第一参考信号端的信号提供给第二节点。
在示例性地实施时，在本公开实施例提供的移位寄存器中，如图2a与图2b所示，第二控制子电路3例如可以包括：第四开关晶体管M4与第五开关晶体管M5；
第四开关晶体管M4的控制极与第一节点A相连，第四开关晶体管M4的第一极与第一参考信号端Vref1相连，第四开关晶体管M4的第二极与第三节点C相连；
第五开关晶体管M5的控制极与第二节点B相连，第五开关晶体管M5的第一极与第二参考信号端Vref2相连，第五开关晶体管M5的第二极与第三节点C相连。
在示例性地实施时，在本公开实施例提供的移位寄存器中，如图2a所示，第四开关晶体管M4与第五开关晶体管M5可以为P型晶体管。或者，如图2b所示，第四开关晶体管M4与第五开关晶体管M5也可以为N型晶体管，在此不作限定。
在示例性地实施时，在本公开实施例提供的移位寄存器中，第四开关晶体管在第一节点的信号的控制下处于导通状态时，可以将第一参考信号端的信号提供给第三节点。第五开关晶体管在第二节点的信号的控制下处于导通状态时，可以将第二参考信号端的信号提供给第三节点。
在示例性地实施时，在本公开实施例提供的移位寄存器中，如图2a与图2b所示，第三控制子电路4具体可以包括：第六开关晶体管M6；
第六开关晶体管M6的控制极与第三节点C相连，第六开关晶体管M6的第一极与第一参考信号端Vref1相连，第六开关晶体管M6的第二极与第一节点A相连。
在示例性地实施时，在本公开实施例提供的移位寄存器中，如图2a所示，第六开关晶体管M6可以为P型晶体管。或者，如图2b所示，第六开关晶体管M6也可以为N型晶体管，在此不作限定。
在示例性地实施时，在本公开实施例提供的移位寄存器中，第六开关晶体管在第三节点的信号的控制下处于导通状态时，可以将第一参考信号端的信号提供给第一节点。
在示例性地实施时，在本公开实施例提供的移位寄存器中，如图2a与图2b所示，第一输出子电路6例如可以包括：第七开关晶体管M7；
第七开关晶体管M7的控制极与第一节点A相连，第七开关晶体管M7的第一极与第 二参考信号端Vref2相连，第七开关晶体管M7的第二极与输出信号端Output(输出端)相连。
在示例性地实施时，在本公开实施例提供的移位寄存器中，如图2a所示，第七开关晶体管M7可以为P型晶体管。或者，如图2b所示，第七开关晶体管M7也可以为N型晶体管，在此不作限定。
在示例性地实施时，在本公开实施例提供的移位寄存器中，第七开关晶体管在第一节点的信号的控制下处于导通状态时，可以将第二参考信号端的信号提供给输出信号端。
在示例性地实施时，在本公开实施例提供的移位寄存器中，如图2a与图2b所示，第二输出子电路7例如可以包括：第八开关晶体管M8；
第八开关晶体管M8的控制极与第三节点C相连，第八开关晶体管M8的第一极与第一参考信号端Vref1相连，第八开关晶体管M8的第二极与输出信号端Output(输出端)相连。
在示例性地实施时，在本公开实施例提供的移位寄存器中，如图2a所示，第八开关晶体管M8可以为P型晶体管。或者，如图2b所示，第八开关晶体管M8也可以为N型晶体管，在此不作限定。
在示例性地实施时，在本公开实施例提供的移位寄存器中，第八开关晶体管在第三节点的信号的控制下处于导通状态时，可以将第一参考信号端的信号提供给输出信号端。
在示例性地实施时，在本公开实施例提供的移位寄存器中，如图2a与图2b所示，节点稳定子电路5例如可以包括：电容Cst；电容Cst的第一端与第一节点A相连，电容Cst的第二端与第二时钟信号端CK2相连。
在示例性地实施时，在本公开实施例提供的移位寄存器中，电容可以保持第一节点的信号的电位稳定。并且在第一节点处于浮接状态时，由于电容的耦合作用可以保持电容两端的电压差稳定，即保持第一节点和第二时钟信号端之间的电压差稳定。
以上仅是举例说明本公开实施例提供的移位寄存器中各子电路的示例性结构，在示例性地实施时，上述各子电路的结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
为了简化制备工艺，在示例性地实施时，在本公开实施例提供的上述移位寄存器中， 如图2a所示，所有开关晶体管可以均为P型晶体管；或者，如图2b所示，所有开关晶体管也可以均为N型晶体管。
进一步的，在示例性地实施时，P型晶体管在高电位信号作用下截止，在低电位信号作用下导通；N型晶体管在高电位信号作用下导通，在低电位信号作用下截止。
需要说明的是，本公开上述实施例中提到的开关晶体管可以是薄膜晶体管(TFT，Thin Film Transistor)，也可以是金属氧化物半导体场效应管(MOS，Metal Oxide Scmiconductor)，在此不作限定。在示例性实施中，上述各开关晶体管的控制极作为其栅极，并且根据各开关晶体管的栅极的信号以及其类型，可以将其第一极作为源极，第二极作为漏极；或者可以将其第一极作为漏极，第二极作为源极，在此不做限定。
在示例性地实施时，在本公开实施例提供的移位寄存器中，第一时钟信号端的信号与第二时钟信号端的信号的周期相同，并且第一时钟信号端的有效脉冲信号的时长占一个时钟周期的时长的百分比与第二时钟信号端的有效脉冲信号的时长占一个时钟周期的时长的百分比也相同。其中，第一时钟信号端的有效脉冲信号用于控制第一晶体管与第五晶体管导通。
在示例性地实施时，第一时钟信号端的有效脉冲信号的时长占一个时钟周期的时长的百分比可以等于50％。
或者，为了使整个电路的工作更稳定，例如为了避免百分比为50％的时钟信号瞬间变化时，导致第七晶体管连接的第二参考信号端与第八晶体管连接的第一参考信号端导通而短路对移位寄存器造成的损耗，在示例性地实施时，第一时钟信号端的有效脉冲信号的时长占一个时钟周期的时长的百分比也可以小于50％。例如，如图3a至图3c所示，第一时钟信号端CK1的有效脉冲信号的时长占一个时钟周期的时长的百分比与第二时钟信号端CK2的有效脉冲信号的时长占一个时钟周期的时长的百分比均小于50％，此时，输入信号端Input(输入端)的有效脉冲信号为高电位信号，第一时钟信号端CK1的有效脉冲信号与第二时钟信号端CK2的有效脉冲信号均为低电位信号。或者，输入信号端的有效脉冲信号也可以为低电位信号，此时第一时钟信号端的有效脉冲信号与第二时钟信号端的有效脉冲信号均为高电位信号。在实际应用中，上述百分比需要根据实际应用环境来设计确定，在此不作限定。
下面结合电路时序图对本公开实施例提供的上述移位寄存器的工作过程作以描述。下述描述中以1表示高电位信号，0表示低电位信号，其中，1和0代表其逻辑电位， 仅是为了更好的解释本公开实施例提供的上述移位寄存器的工作过程，而不是在示例性地实施时施加在各开关晶体管的控制极上的电位。
以图2a所示的移位寄存器的结构为例对其工作过程作以描述；第一参考信号端Vref1的信号为高电位信号，第二参考信号端Vref2的信号为低电位信号；对应的输入输出时序图如图3a所示，例如，选取如图3a所示的输入输出时序图中的T1、T2、T3以及T4四个阶段。
在T1阶段，Input＝1，CK1＝0，CK2＝1。
由于CK1＝0，因此第一开关晶体管M1与第二开关晶体管M2均导通。其中，导通的第一开关晶体管M1将输入信号端Input的高电位信号提供给第一节点A，使第一节点A的信号为高电位信号，因此第三开关晶体管M3、第四开关晶体管M4以及第七开关晶体管M7均截止。导通的第二开关晶体管M2将第一时钟信号端CK1的低电位信号提供给第二节点B，使第二节点B的信号为低电位信号，因此第五开关晶体管M5导通以将第二参考信号端Vref2的低电位信号提供给第三节点C，使第三节点C的信号为低电位信号，因此第六开关晶体管M6与第八开关晶体管M8均导通。导通的第六开关晶体管M6将第一参考信号端Vref1的高电位信号提供给第一节点A，进一步使第一节点A的信号为高电位信号。导通的第八开关晶体管M8将第一参考信号端Vref1的高电位信号提供给输出信号端Output(输出端)，使输出信号端Output(输出端)输出高电位信号。
之后，Input＝1，CK1＝1，CK2＝1的时间内由于CK1＝1，因此第一开关晶体管M1与第二开关晶体管M2均截止，由于未有额外的信号输入到第二节点B为其充电，因此第二节点B保持为低电位信号。该时间内其余工作过程与本实施例T1阶段中Input＝1，CK1＝0，CK2＝1时的工作过程基本相同，在此不作详述。
在T2阶段，Input＝0，CK1＝1，CK2＝0。
由于CK1＝1，因此第一开关晶体管M1与第二开关晶体管M2均截止。由于未有额外的信号输入到第二节点B为其充电，因此第二节点B保持为低电位信号，使得第五开关晶体管M5导通以将第二参考信号端Vref2的低电位信号提供给第三节点C，使第三节点C的信号为低电位信号，因此第六开关晶体管M6与第八开关晶体管M8均导通。导通的第六开关晶体管M6将第一参考信号端Vref1的高电位信号提供给第一节点A，使第一节点A的信号为高电位信号，因此第三开关晶体管M3、第四开关晶体管M4以及第七开关晶体管M7均截止。导通的第八开关晶体管M8将第一参考信号端Vref1的高电位信 号提供给输出信号端Output(输出端)，使输出信号端Output(输出端)输出高电位信号。
之后，Input＝0，CK1＝1，CK2＝1的时间内第二时钟信号端CK2由低电位信号变为高电位信号，并且该时间内其余工作过程与本实施例T2阶段中Input＝0，CK1＝1，CK2＝0时的工作过程基本相同，在此不作详述。并且这样可以避免在百分比为50％的第一时钟信号端CK1信号的电位与第二时钟信号端CK2信号的电位同时翻转时，导致第七晶体管M7连接的第二参考信号端Vref2与第八晶体管M8连接的第一参考信号端Vref1导通而短路对移位寄存器造成的损耗，从而使电路输出更稳定。
在T3阶段，Input＝0，CK1＝0，CK2＝1。
由于CK1＝0，因此第一开关晶体管M1与第二开关晶体管M2均导通。其中，导通的第一开关晶体管M1将输入信号端Input(输入端)的低电位信号提供给第一节点A，使第一节点A的信号为低电位信号，因此第三开关晶体管M3、第四开关晶体管M4以及第七开关晶体管M7均导通并且电容Cst充电。导通的第三开关晶体管M3将第一参考信号端Vref1的高电位信号提供给第二节点B，使第二节点B的信号为高电位信号，因此第五开关晶体管M5截止。导通的第四开关晶体管M4将第一参考信号端Vref1的高电位信号提供给第三节点C，使第三节点C的信号为高电位信号，因此第六开关晶体管M6与第八开关晶体管M8均截止。导通的第七开关晶体管M7将第二参考信号端Vref2的低电位信号提供给输出信号端Output(输出端)，使输出信号端Output(输出端)输出低电位信号。
之后，Input＝0，CK1＝1，CK2＝1的时间内由于CK1＝1，因此第一开关晶体管M1与第二开关晶体管M2均截止，由于电容Cst的耦合作用保持第一节点A的信号为低电位信号。该时间内其余工作过程与本实施例T3阶段中Input＝0，CK1＝0，CK2＝1时的工作过程基本相同，在此不作详述。
在T4阶段，Input＝0，CK1＝1，CK2＝0。
由于CK1＝1，因此第一开关晶体管M1与第二开关晶体管M2均截止，由于CK2＝0以及电容Cst的耦合作用，可以使第一节点A的信号的电位被进一步拉低，以使第三开关晶体管M3、第四开关晶体管M4以及第七开关晶体管M7均可以完全导通。完全导通的第三开关晶体管M3将第一参考信号端Vref的高电位信号无电压损失的提供给第二节点B，使第二节点B的信号为高电位信号，因此使第五开关晶体管M5完全截止。完全导通 的第四开关晶体管M4将第一参考信号端Vref1的高电位信号无电压损失的提供给第三节点C，使第三节点C的信号为高电位信号，因此使第六开关晶体管M6与第八开关晶体管M8均完全截止。完全导通的第七开关晶体管M7将第二参考信号端Vref2的低电位信号无电压损失的提供给输出信号端Output(输出端)，使输出信号端Output(输出端)完全输出低电位信号。
之后，Input＝0，CK1＝1，CK2＝1时间内由于CK2＝1与电容Cst的耦合作用，使第一节点A的信号的电位恢复为开始的低电位，以为下一阶段稳定的输入信号端Input(输入端)的低电位信号做准备。该时间内其余工作过程与本实施例T4阶段中Input＝0，CK1＝1，CK2＝0时的工作过程基本相同，在此不作详述。
本公开实施例提供的上述移位寄存器，在T4阶段之后，一直重复执行T3阶段和T4阶段的工作过程，直至下一帧开始。
本公开实施例提供的上述移位寄存器，仅通过八个开关晶体管和一个电容的简单结构，即可实现信号稳定的移位输出。
下面以VGL分别代表输入信号端Input(输入端)的低电位信号的电压、第二参考信号端Vref2的低电位信号的电压以及第二时钟信号端CK2的低电位信号的电压，以及VGH代表第二时钟信号端CK2的高电位信号的电压，并将各开关晶体管的阈值电压均设置为V th为例进行说明。在实际应用中，在P型的开关晶体管的栅极为低电位信号时，该开关晶体管传输低电位信号的功能与其阈值电压有关。因此在实际应用中，在本公开实施例的T3阶段中，由于CK1＝0且Input＝0，因此第一开关晶体管M1的栅极与其需要传输的信号均为低电位信号，使得传输到第一节点A的信号的电压为VGL-V th。同理，第七开关晶体管的栅极与其需要传输的信号也均为低电位信号，因此导致信号输出端Output(输出端)输出的信号的电压为VGL-2V th，导致信号输出端Output(输出端)输出的低电位信号的电压无法达到VGL。在T4阶段中，由于第二时钟信号端CK2由高电位信号变换到低电位信号，由于电容Cst的耦合作用，可以使第一节点A的信号的电位被进一步拉低，使第一节点A的信号的电压跳变为VGL-V th-(VGH+|VGL|)，以控制第七开关晶体管M7完全导通，从而使信号输出端Output(输出端)输出的低电位信号的电压达到VGL，以使信号输出端Output(输出端)实现稳定输出。
以图2a所示的移位寄存器的结构为例对其示例性工作过程进行描述，在上述图3a所示的实施例的时序图中的T1阶段与T2阶段之间插入一个插入阶段T01，即在上述图 3a所示的实施例的基础上将输入信号端Input(输入端)的有效脉冲信号的时长延长一个时钟周期，对应的输入输出时序图如图3b所示。在图3b所示的时序图中，选取T1、T01、T2、T3、T4五个阶段，其中，插入阶段T01又分为第一插入子阶段T011与第二插入子阶段T012。
在T1阶段，Input＝1，CK1＝0，CK2＝1；并且之后Input＝1，CK1＝1，CK2＝1。该阶段的具体工作过程与上述图3a所示的实施例中T1阶段的工作过程基本相同，在此不作详述。
在T01阶段中的T011阶段中，Input＝1，CK1＝1，CK2＝0。
由于CK1＝1，因此第一开关晶体管M1与第二开关晶体管M2均截止。由于未有额外的信号输入到第二节点B为其充电，因此第二节点B保持为低电位信号，使得第五开关晶体管M5导通以将第二参考信号端Vref2的低电位信号提供给第三节点C，使第三节点C的信号为低电位信号，因此第六开关晶体管M6与第八开关晶体管M8均导通。导通的第六开关晶体管M6将第一参考信号端Vref1的高电位信号提供给第一节点A，使第一节点A的信号为高电位信号，因此第三开关晶体管M3、第四开关晶体管M4以及第七开关晶体管M7均截止。导通的第八开关晶体管M8将第一参考信号端Vref1的高电位信号提供给输出信号端Output(输出端)，使输出信号端Output(输出端)输出高电位信号。
之后，Input＝1，CK1＝1，CK2＝1的时间内由于第二时钟信号端CK2由低电位信号变为高电位信号，并且该时间内其余工作过程与本实施例T011阶段中Input＝1，CK1＝1，CK2＝0时的工作过程基本相同，在此不作详述。并且这样可以使电路中的信号具有了趋于稳定的缓冲时间，从而使输出稳定。
在T012阶段中，Input＝1，CK1＝0，CK2＝1。
由于CK1＝0，因此第一开关晶体管M1与第二开关晶体管M2均导通。其中，导通的第一开关晶体管M1将输入信号端Input的高电位信号提供给第一节点A，使第一节点A的信号为高电位信号，因此第三开关晶体管M3、第四开关晶体管M4以及第七开关晶体管M7均截止。导通的第二开关晶体管M2将第一时钟信号端CK1的低电位信号提供给第二节点B，使第二节点B的信号为低电位信号，因此第五开关晶体管M5导通以将第二参考信号端Vref2的低电位信号提供给第三节点C，使第三节点C的信号为低电位信号，因此第六开关晶体管M6与第八开关晶体管M8均导通。导通的第六开关晶体管M6将第 一参考信号端Vref1的高电位信号提供给第一节点A，进一步使第一节点A的信号为高电位信号。导通的第八开关晶体管M8将第一参考信号端Vref1的高电位信号提供给输出信号端Output(输出端)，使输出信号端Output(输出端)输出高电位信号。
之后，Input＝1，CK1＝1，CK2＝1的时间内由于CK1＝1，因此第一开关晶体管M1与第二开关晶体管M2均截止，由于未有额外的信号输入到第二节点B为其充电，因此第二节点B保持为低电位信号。该时间内其余工作过程与本实施例T012阶段中Input＝1，CK1＝0，CK2＝1时的工作过程基本相同，在此不作详述。
在T2阶段，Input＝0，CK1＝1，CK2＝0；并且之后Input＝0，CK1＝1，CK2＝1。该阶段的具体工作过程与上述图3a所示的实施例中T2阶段的工作过程基本相同，在此不作详述。
在T3阶段，Input＝0，CK1＝0，CK2＝1；并且之后Input＝0，CK1＝1，CK2＝1。该阶段的具体工作过程与上述图3a所示的实施例中T3阶段的工作过程基本相同，在此不作详述。
在T4阶段，Input＝0，CK1＝1，CK2＝0；并且之后Input＝0，CK1＝1，CK2＝1。该阶段的具体工作过程与上述图3a所示的实施例中T4阶段的工作过程基本相同，在此不作详述。
本公开实施例提供的上述移位寄存器，在T4阶段之后，一直重复执行T3阶段和T4阶段的工作过程，直至下一帧开始。
本公开实施例提供的上述移位寄存器，仅通过八个开关晶体管和一个电容的简单结构，即可实现信号稳定的移位输出。
以图2a所示的结构为例，采用图4a与图4b所示的各输入信号的仿真模拟时序图对移位寄存器的工作过程进行仿真模拟。在图4a与图4b中，纵坐标代表电压，横坐标代表时间，其中，图4a中的L1代表输入信号端Input(输入端)的信号，图4b中的L2代表第一时钟信号端CK1的信号，L3代表第二时钟信号端CK2的信号。在仿真模拟过程中，输出信号端Output(输出端)的信号的变化如图4c所示，在图4c中，纵坐标代表电压，横坐标代表时间，并且通过图4c可以看出，本公开实施例提供的上述移位寄存器运行稳定，可以使信号输出端Output(输出端)稳定的输出信号L4。
以图2a所示的移位寄存器的结构为例对其示例性工作过程进行描述，在上述图3a所示的实施例的时序图中的T1阶段与T2阶段之间插入两个插入阶段T01、T02，即在 上述图3a所示的实施例的基础上将输入信号端Input(输入端)的有效脉冲信号的时长延长两个时钟周期，对应的输入输出时序图如图3c所示。在图3c所示的时序图中，选取T1、T01、T02、T2、T3、T4六个阶段，其中，插入阶段T01又分为第一插入子阶段T011与第二插入子阶段T012；插入阶段T02又分为第一插入子阶段T021与第二插入子阶段T022。
在T1阶段，Input＝1，CK1＝0，CK2＝1；并且之后Input＝1，CK1＝1，CK2＝1。该阶段的具体工作过程与上述图3a所示的实施例中T1阶段的工作过程基本相同，在此不作详述。
在T01阶段中的T011阶段中，Input＝1，CK1＝1，CK2＝0。
由于CK1＝1，因此第一开关晶体管M1与第二开关晶体管M2均截止。由于未有额外的信号输入到第二节点B为其充电，因此第二节点B保持为低电位信号，使得第五开关晶体管M5导通以将第二参考信号端Vref2的低电位信号提供给第三节点C，使第三节点C的信号为低电位信号，因此第六开关晶体管M6与第八开关晶体管M8均导通。导通的第六开关晶体管M6将第一参考信号端Vref1的高电位信号提供给第一节点A，使第一节点A的信号为高电位信号，因此第三开关晶体管M3、第四开关晶体管M4以及第七开关晶体管M7均截止。导通的第八开关晶体管M8将第一参考信号端Vref1的高电位信号提供给输出信号端Output(输出端)，使输出信号端Output(输出端)输出高电位信号。
之后，Input＝1，CK1＝1，CK2＝1的时间内第二时钟信号端CK2由低电位信号变为高电位信号，并且该时间内其余工作过程与本实施例T011阶段中Input＝1，CK1＝1，CK2＝0时的工作过程基本相同，在此不作详述。
在T012阶段中，Input＝1，CK1＝0，CK2＝1。
由于CK1＝0，因此第一开关晶体管M1与第二开关晶体管M2均导通。其中，导通的第一开关晶体管M1将输入信号端Input(输入端)的高电位信号提供给第一节点A，使第一节点A的信号为高电位信号，因此第三开关晶体管M3、第四开关晶体管M4以及第七开关晶体管M7均截止。导通的第二开关晶体管M2将第一时钟信号端CK1的低电位信号提供给第二节点B，使第二节点B的信号为低电位信号，因此第五开关晶体管M5导通以将第二参考信号端Vref2的低电位信号提供给第三节点C，使第三节点C的信号为低电位信号，因此第六开关晶体管M6与第八开关晶体管M8均导通。导通的第六开关晶 体管M6将第一参考信号端Vref1的高电位信号提供给第一节点A，进一步使第一节点A的信号为高电位信号。导通的第八开关晶体管M8将第一参考信号端Vref1的高电位信号提供给输出信号端Output(输出端)，使输出信号端Output(输出端)输出高电位信号。
之后，Input＝1，CK1＝1，CK2＝1的时间内由于CK1＝1，因此第一开关晶体管M1与第二开关晶体管M2均截止，由于未有额外的信号输入到第二节点B为其充电，因此第二节点B保持为低电位信号。该时间内其余工作过程与本实施例T012阶段中Input＝1，CK1＝0，CK2＝1时的工作过程基本相同，在此不作详述。
在T02阶段中的T021阶段中，Input＝1，CK1＝1，CK2＝0。
由于CK1＝1，因此第一开关晶体管M1与第二开关晶体管M2均截止。由于未有额外的信号输入到第二节点B为其充电，因此第二节点B保持为低电位信号，使得第五开关晶体管M5导通以将第二参考信号端Vref2的低电位信号提供给第三节点C，使第三节点C的信号为低电位信号，因此第六开关晶体管M6与第八开关晶体管M8均导通。导通的第六开关晶体管M6将第一参考信号端Vref1的高电位信号提供给第一节点A，使第一节点A的信号为高电位信号，因此第三开关晶体管M3、第四开关晶体管M4以及第七开关晶体管M7均截止。导通的第八开关晶体管M8将第一参考信号端Vref1的高电位信号提供给输出信号端Output(输出端)，使输出信号端Output(输出端)输出高电位信号。
之后，Input＝1，CK1＝1，CK2＝1的时间内第二时钟信号端CK2由低电位信号变为高电位信号，并且该时间内其余工作过程与本实施例T021阶段中Input＝1，CK1＝1，CK2＝0时的工作过程基本相同，在此不作详述。
在T022阶段中，Input＝1，CK1＝0，CK2＝1。
由于CK1＝0，因此第一开关晶体管M1与第二开关晶体管M2均导通。其中，导通的第一开关晶体管M1将输入信号端Input(输入端)的高电位信号提供给第一节点A，使第一节点A的信号为高电位信号，因此第三开关晶体管M3、第四开关晶体管M4以及第七开关晶体管M7均截止。导通的第二开关晶体管M2将第一时钟信号端CK1的低电位信号提供给第二节点B，使第二节点B的信号为低电位信号，因此第五开关晶体管M5导通以将第二参考信号端Vref2的低电位信号提供给第三节点C，使第三节点C的信号为低电位信号，因此第六开关晶体管M6与第八开关晶体管M8均导通。导通的第六开关晶 体管M6将第一参考信号端Vref1的高电位信号提供给第一节点A，进一步使第一节点A的信号为高电位信号。导通的第八开关晶体管M8将第一参考信号端Vref1的高电位信号提供给输出信号端Output(输出端)，使输出信号端Output(输出端)输出高电位信号。
之后，Input＝1，CK1＝1，CK2＝1的时间内由于CK1＝1，因此第一开关晶体管M1与第二开关晶体管M2均截止，由于未有额外的信号输入到第二节点B为其充电，因此第二节点B保持为低电位信号。该时间内其余工作过程与本实施例T022阶段中Input＝1，CK1＝0，CK2＝1时的工作过程基本相同，在此不作详述。
在T2阶段，Input＝0，CK1＝1，CK2＝0；并且之后Input＝0，CK1＝1，CK2＝1。该阶段的工作过程与上述图3a所示的实施例中T2阶段的工作过程基本相同，在此不作详述。
在T3阶段，Input＝0，CK1＝0，CK2＝1；并且之后Input＝0，CK1＝1，CK2＝1。该阶段的工作过程与上述图3a所示的实施例中T3阶段的工作过程基本相同，在此不作详述。
在T4阶段，Input＝0，CK1＝1，CK2＝0；并且之后Input＝0，CK1＝1，CK2＝1。该阶段的工作过程与上述图3a所示的实施例中T4阶段的工作过程基本相同，在此不作详述。
本公开实施例提供的上述移位寄存器，在T4阶段之后，一直重复执行T3阶段和T4阶段的工作过程，直至下一帧开始。
本公开实施例提供的上述移位寄存器，仅通过八个开关晶体管和一个电容的简单结构，即可实现信号稳定的移位输出。
通过上述各个实施例可以看出，本公开实施例提供的上述移位寄存器，在上述图3a所示的实施例的输入信号端的信号的基础上，将输入信号端的有效脉冲信号的时长延长一个时钟信号周期，输出信号端即可输出上述图3b所示的实施例中对应时长的信号，将输入信号端的有效脉冲信号的时长延长两个时钟信号周期，输出信号端即可输出上述图3c所示的实施例中对应时长的信号，依此类推，通过延长有效脉冲信号的时长，即可使输出信号端输出与输入信号端的有效脉冲信号的时长相同时长的信号。上述移位寄存器由于仅需通过改变输入信号端的有效脉冲信号的时长来控制输出信号端输出的信号的有效脉冲信号的时长，而不需要进行电路的改动和工艺的改变，从而可以降低工艺复杂问题，降低成本。
在示例性地实施时，在上述移位寄存器中的各开关晶体管均为N型晶体管时，如图2b所示，此时第一参考信号端Vref1的信号为低电位信号，第二参考信号端Vref2的 信号为高电位信号，并且其对应的输入输出时序图中的输入信号端Input(输入端)的信号、第一时钟信号端CK1的信号以及第二时钟信号端CK2的信号与图3a、图3b以及图3c中对应的信号的电位相反，即将图3a、图3b以及图3c中的各信号的高电位变为低电位，以及将各信号的低电位变为高电位。并且，在上述移位寄存器中的各开关晶体管均为N型晶体管时的工作过程可以参见上述各个实施例中的工作过程，其仅将上述各个实施例中各开关晶体管的控制极的高电位信号变为低电位信号，以及将各开关晶体管的控制极的低电位信号变为高电位信号即可，在此不作赘述。
基于同一构思，本公开实施例还提供了一种本公开实施例提供的上述任一种移位寄存器的驱动方法，如图5所示，包括：第一阶段、第二阶段、第三阶段以及第四阶段；
S501、在第一阶段，输入子电路在第一时钟信号端的控制下，将输入信号端的信号提供给第一节点，以及将第一时钟信号端的信号提供给第二节点；第二控制子电路在第二节点的信号的控制下将第二参考信号端的信号提供给第三节点；第三控制子电路在第三节点的控制下将第一参考信号端的信号提供给第一节点；第二输出子电路在第三节点的信号的控制下将第一参考信号端的信号提供给输出信号端；
S502、在第二阶段，第二控制子电路在第二节点的信号的控制下将第二参考信号端的信号提供给第三节点；第三控制子电路在第三节点的控制下将第一参考信号端的信号提供给第一节点；第二输出子电路在第三节点的信号的控制下将第一参考信号端的信号提供给输出信号端；
S503、在第三阶段，输入子电路在第一时钟信号端的控制下，将输入信号端的信号提供给第一节点，以及将第一时钟信号端的信号提供给第二节点；第一控制子电路在第一节点的控制下将第一参考信号端的信号提供给第二节点；第二控制子电路在第一节点的信号的控制下将第一参考信号端的信号提供给第三节点；第一输出子电路在第一节点的信号的控制下将第二参考信号端的信号提供给输出信号端；
S504、在第四阶段，节点稳定子电路稳定第一节点的电位；第一控制子电路在第一节点的控制下将第一参考信号端的信号提供给第二节点；第二控制子电路在第一节点的信号的控制下将第一参考信号端的信号提供给第三节点；第一输出子电路在第一节点的信号的控制下将第二参考信号端的信号提供给输出信号端。
本公开实施例提供的上述移位寄存器的驱动方法，可以稳定的输出移位后的信号，简化制备工艺，降低生产成本。
在示例性地实施时，在本公开实施例提供的驱动方法中，在第一阶段之后，且在第二阶段之前，还可以包括：至少一个插入阶段；其中，插入阶段包括第一插入子阶段与第二插入子阶段；
在第一插入子阶段，第二控制子电路在第二节点的信号的控制下将第二参考信号端的信号提供给第三节点；第三控制子电路在第三节点的控制下将第一参考信号端的信号提供给第一节点；第二输出子电路在第三节点的信号的控制下将第一参考信号端的信号提供给输出信号端；
在第二插入子阶段，输入子电路在第一时钟信号端的控制下，将输入信号端的信号提供给第一节点，以及将第一时钟信号端的信号提供给第二节点；第二控制子电路在第二节点的信号的控制下将第二参考信号端的信号提供给第三节点；第三控制子电路在第三节点的控制下将第一参考信号端的信号提供给第一节点；第二输出子电路在第三节点的信号的控制下将第一参考信号端的信号提供给输出信号端。
本公开实施例提供的上述驱动方法，仅需通过插入至少一个插入阶段，就可以控制信号输出端输出的信号的有效脉冲信号的时长，而不需要进行电路的改动和工艺的改变，从而可以简化制备工艺，降低生产成本，有利于实现显示装置中面板的窄边框设计。
在实际应用中，在第一阶段与第二阶段之间插入一个插入阶段，其工作过程对应上述图3b所示的实施例。在第一阶段与第二阶段之间插入两个插入阶段，其工作过程对应上述图3c所示的实施例。当然，在第一阶段与第二阶段之间还可以插入三个、四个或更多个插入阶段，依此类推，在此不作赘述。
在示例性地实施时，在本公开实施例提供的驱动方法中，第一时钟信号端的信号与第二时钟信号端的信号的周期相同，并且第一时钟信号端的有效脉冲信号的时长占一个时钟周期的时长的百分比与第二时钟信号端的有效脉冲信号的时长占一个时钟周期的时长的百分比也相同。其中，第一时钟信号端的有效脉冲信号用于控制第一晶体管与第五晶体管导通。
在示例性地实施时，第一时钟信号端的有效脉冲信号的时长占一个时钟周期的时长的百分比可以等于50％。
或者，为了使整个电路的工作更稳定，例如为了避免百分比为50％的时钟信号瞬间变化时，导致第七晶体管连接的第二参考信号端与第八晶体管连接的第一参考信号端导通而短路对移位寄存器造成的损耗，在具体实施时，第一时钟信号端的有效脉冲信号的 时长占一个时钟周期的时长的百分比也可以小于50％。具体地，如图3a至图3c所示，第一时钟信号端CK1的有效脉冲信号的时长占一个时钟周期的时长的百分比与第二时钟信号端CK2的有效脉冲信号的时长占一个时钟周期的时长的百分比均小于50％，此时，输入信号端Input(输入端)的有效脉冲信号为高电位信号，第一时钟信号端CK1的有效脉冲信号与第二时钟信号端CK2的有效脉冲信号均为低电位信号。或者，输入信号端的有效脉冲信号也可以为低电位信号，此时第一时钟信号端的有效脉冲信号与第二时钟信号端的有效脉冲信号均为高电位信号。在实际应用中，上述百分比需要根据实际应用环境来设计确定，在此不作限定。
基于同一构思，本公开实施例还提供了一种驱动控制电路，如图6所示，包括：多个级联的本公开实施例提供的上述任一种移位寄存器：SR(1)、SR(2)…SR(n)…SR(N-1)、SR(N)(共N个移位寄存器，1≤n≤N)；N为正整数，n为正整数；
第一级移位寄存器SR(1)的输入信号端Input(输入端)与起始信号端STV相连；
除第一级移位寄存器SR(1)之外，其余各级移位寄存器SR(n)的输入信号端Input(输入端)分别与其相邻的上一级移位寄存器SR(n-1)的输出信号端Output(输入端)相连。
例如，上述驱动控制电路中的每个移位寄存器的结构与本公开上述移位寄存器在功能和结构上均相同，重复之处不再赘述。
本公开实施例提供的上述驱动控制电路可以应用于提供发光控制晶体管的发光控制信号，也可以应用于提供扫描控制晶体管的栅极扫描信号，在此不做限定。
在示例性地实施时，在本公开提供的驱动控制电路中，如图6所示，第2k-1级移位寄存器的第一时钟信号端CK1和第2k级移位寄存器的第二时钟信号端CK2均与同一时钟端即第一时钟端ck1相连；第2k-1级移位寄存器的第二时钟信号端CK2和第2k级移位寄存器的第一时钟信号端CK1均与同一时钟端即第二时钟端ck2相连；其中，k为正整数。
进一步地，在示例性地实施时，在本公开提供的驱动控制电路中，如图6所示，各级移位寄存器SR(n)的第一参考信号端Vref1均与同一信号端即第一参考端vref1相连；各级移位寄存器SR(n)的第二参考信号端Vref2均与同一信号端即第二参考端vref1相连。
基于同一构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述驱动控制电路。该显示装置的实施可以参见上述移位寄存器的实施例，重复之处不再赘述。
在示例性地实施时，本公开实施例提供的上述显示装置可以为有机发光显示装置，或者也可以为液晶显示装置，在此不作限定。
在有机发光显示装置中，一般设置有多个有机发光二极管、与各有机发光二极管连接的像素补偿电路、多条栅线以及多条发光控制信号线。一般像素补偿电路中设置有用于控制有机发光二极管发光的发光控制晶体管和用于控制数据信号输入的扫描控制晶体管。其中，发光控制晶体管的控制极与所在行对应的发光控制信号线连接，用于接收发光控制信号；扫描控制晶体管的控制极与所在行对应的栅线连接，用于接收栅极扫描信号。在示例性地实施时，在本公开实施例提供的上述显示装置为有机发光显示装置时，驱动控制电路可以应用于提供发光控制晶体管的发光控制信号，此时驱动控制电路中的每一级移位寄存器的信号输出端与一条发光控制信号线连接。或者，驱动控制电路也可以应用于提供扫描控制晶体管的栅极扫描信号，此时驱动控制电路为栅极驱动电路，并且驱动控制电路中的每一级移位寄存器的信号输出端与一条栅线连接。
进一步地，在本公开实施例提供的显示装置为有机发光显示装置时，可以设置两个驱动控制电路，其中一个驱动控制电路应用于提供发光控制晶体管的发光控制信号，且该驱动控制电路中的每一级移位寄存器的信号输出端与一条发光控制信号线连接；另一个驱动控制电路作为栅极驱动电路应用于提供扫描控制晶体管的栅极扫描信号，且该驱动控制电路中的每一级移位寄存器的信号输出端与一条栅线连接，在此不作限定。
在本公开实施例提供的上述显示装置为液晶显示装置时，一般设置有多个像素电极、与各像素电极连接的开关晶体管以及多条栅极。其中，每行开关晶体管的控制极与所在行对应的栅线连接。本公开实施例提供的上述驱动控制电路可以作为栅极驱动电路应用于提供开关晶体管的栅极驱动信号，并且驱动控制电路中的每一级移位寄存器的信号输出端与一条栅线连接。
在示例性地实施时，本公开实施例提供的显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不作赘述，也不应作为对本公开的限制。
本公开实施例提供的移位寄存器、其驱动方法、驱动控制电路及显示装置，包括：输入子电路、第一控制子电路、第二控制子电路、第三控制子电路、节点稳定子电路、第一输出子电路以及第二输出子电路；输入子电路用于在第一时钟信号端的控制下，将输入信号端的信号提供给第一节点，以及将第一时钟信号端的信号提供给第二节点；第一控制子电路用于在第一节点的控制下将第一参考信号端的信号提供给第二节点；第二控制子电路用于在第一节点的信号的控制下将第一参考信号端的信号提供给第三节点，在第二节点的信号的控制下将第二参考信号端的信号提供给第三节点；第三控制子电路用于在第三节点的控制下将第一参考信号端的信号提供给第一节点；节点稳定子电路用于稳定第一节点的电位；第一输出子电路用于在第一节点的信号的控制下将第二参考信号端的信号提供给输出信号端；第二输出子电路用于在第三节点的信号的控制下将第一参考信号端的信号提供给输出信号端。本公开实施例提供的移位寄存器通过上述七个子电路的相互配合，可以通过简单的结构以及较少的信号线即可使输出信号端稳定的输出移位后的信号，从而简化制备工艺，降低生产成本。并且通过上述七个子电路的相互配合，仅需通过改变输入信号端的有效脉冲信号的时长就可以控制信号输出端输出的信号的有效脉冲信号的时长，而不需要进行电路的改动和工艺的改变，从而可以简化制备工艺，降低生产成本，有利于实现显示装置中面板的窄边框设计。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (18)

  1. 一种移位寄存器，包括：输入子电路、第一控制子电路、第二控制子电路、第三控制子电路、节点稳定子电路、第一输出子电路以及第二输出子电路；
    所述输入子电路分别与输入信号端、第一时钟信号端、第一节点以及第二节点相连，用于在所述第一时钟信号端的控制下，将所述输入信号端的信号提供给所述第一节点，以及将所述第一时钟信号端的信号提供给所述第二节点；
    所述第一控制子电路分别与第一参考信号端、所述第一节点以及所述第二节点相连，用于在所述第一节点的控制下将所述第一参考信号端的信号提供给所述第二节点；
    所述第二控制子电路分别与所述第一参考信号端、第二参考信号端、所述第一节点、所述第二节点以及第三节点相连，用于在所述第一节点的信号的控制下将所述第一参考信号端的信号提供给所述第三节点，在所述第二节点的信号的控制下将所述第二参考信号端的信号提供给所述第三节点；
    所述第三控制子电路分别与所述第一参考信号端、所述第一节点以及所述第三节点相连，用于在所述第三节点的控制下将所述第一参考信号端的信号提供给所述第一节点；
    所述节点稳定子电路与所述第一节点相连，用于稳定所述第一节点的电位；
    所述第一输出子电路分别与所述第一节点、所述第二参考信号端以及所述移位寄存器的输出信号端相连，用于在所述第一节点的信号的控制下将所述第二参考信号端的信号提供给所述输出信号端；
    所述第二输出子电路分别与所述第三节点、所述第一参考信号端以及所述输出信号端相连，用于在所述第三节点的信号的控制下将所述第一参考信号端的信号提供给所述输出信号端。
  2. 如权利要求1所述的移位寄存器，其中，所述输入子电路包括：第一开关晶体管与第二开关晶体管；
    所述第一开关晶体管的控制极与所述第一时钟信号端相连，所述第一开关晶体管的第一极与所述输入信号端相连，所述第一开关晶体管的第二极与所述第一节点相连；
    所述第二开关晶体管的控制极与第一极均与所述第一时钟信号端相连，所述第二开 关晶体管的第二极与所述第二节点相连。
  3. 如权利要求1所述的移位寄存器，其中，所述第一控制子电路包括：第三开关晶体管；
    所述第三开关晶体管的控制极与所述第一节点相连，所述第三开关晶体管的第一极与所述第一参考信号端相连，所述第三开关晶体管的第二极与所述第二节点相连。
  4. 如权利要求1所述的移位寄存器，其中，所述第二控制子电路包括：第四开关晶体管与第五开关晶体管；
    所述第四开关晶体管的控制极与所述第一节点相连，所述第四开关晶体管的第一极与所述第一参考信号端相连，所述第四开关晶体管的第二极与所述第三节点相连；
    所述第五开关晶体管的控制极与所述第二节点相连，所述第五开关晶体管的第一极与所述第二参考信号端相连，所述第五开关晶体管的第二极与所述第三节点相连。
  5. 如权利要求1所述的移位寄存器，其中，所述第三控制子电路包括：第六开关晶体管；
    所述第六开关晶体管的控制极与所述第三节点相连，所述第六开关晶体管的第一极与所述第一参考信号端相连，所述第六开关晶体管的第二极与所述第一节点相连。
  6. 如权利要求1所述的移位寄存器，其中，所述第一输出子电路包括：第七开关晶体管；
    所述第七开关晶体管的控制极与所述第一节点相连，所述第七开关晶体管的第一极与所述第二参考信号端相连，所述第七开关晶体管的第二极与所述输出信号端相连。
  7. 如权利要求1所述的移位寄存器，其中，所述第二输出子电路包括：第八开关晶体管；
    所述第八开关晶体管的控制极与所述第三节点相连，所述第八开关晶体管的第一极与所述第一参考信号端相连，所述第八开关晶体管的第二极与所述输出信号端相连。
  8. 如权利要求2-7任一项所述的移位寄存器，其中，各个开关晶体管均为P型晶体管，各个开关晶体管的第一极为P型晶体管的源极，以及各个开关晶体管的第二极为P型晶体管的漏极。
  9. 如权利要求2-7任一项所述的移位寄存器，其中，各个开关晶体管均为N型晶体管，各个开关晶体管的第一极为N型晶体管的漏极，以及各个开关晶体管的第二极为N型晶体管的源极。
  10. 如权利要求1-7任一项所述的移位寄存器，其中，所述节点稳定子电路包括电容；所述电容的第一端与所述第一节点相连，所述电容的第二端与第二时钟信号端相连。
  11. 如权利要求1-7任一项所述的移位寄存器，其中，
    所述输入子电路包括第一开关晶体管与第二开关晶体管，其中，所述第一开关晶体管的控制极与所述第一时钟信号端相连，所述第一开关晶体管的第一极与所述输入信号端相连，所述第一开关晶体管的第二极与所述第一节点相连；以及所述第二开关晶体管的控制极与第一极均与所述第一时钟信号端相连，所述第二开关晶体管的第二极与所述第二节点相连；
    所述第一控制子电路包括第三开关晶体管，其中，所述第三开关晶体管的控制极与所述第一节点相连，所述第三开关晶体管的第一极与所述第一参考信号端相连，所述第三开关晶体管的第二极与所述第二节点相连；
    所述第二控制子电路包括第四开关晶体管与第五开关晶体管，其中，所述第四开关晶体管的控制极与所述第一节点相连，所述第四开关晶体管的第一极与所述第一参考信号端相连，所述第四开关晶体管的第二极与所述第三节点相连；以及所述第五开关晶体管的控制极与所述第二节点相连，所述第五开关晶体管的第一极与所述第二参考信号端相连，所述第五开关晶体管的第二极与所述第三节点相连；
    所述第三控制子电路包括第六开关晶体管，其中，所述第六开关晶体管的控制极与所述第三节点相连，所述第六开关晶体管的第一极与所述第一参考信号端相连，所述第六开关晶体管的第二极与所述第一节点相连；
    所述第一输出子电路包括第七开关晶体管，其中，所述第七开关晶体管的控制极与 所述第一节点相连，所述第七开关晶体管的第一极与所述第二参考信号端相连，所述第七开关晶体管的第二极与所述输出信号端相连；
    所述第二输出子电路包括第八开关晶体管，其中，所述第八开关晶体管的控制极与所述第三节点相连，所述第八开关晶体管的第一极与所述第一参考信号端相连，所述第八开关晶体管的第二极与所述输出信号端相连；以及
    所述节点稳定子电路包括电容，其中，所述电容的第一端与所述第一节点相连，所述电容的第二端与第二时钟信号端相连。
  12. 一种驱动控制电路，包括：多个级联的如权利要求1-11任一项所述的移位寄存器；
    第一级移位寄存器的输入信号端与起始信号端相连；
    除所述第一级移位寄存器之外，其余各级移位寄存器的输入信号端分别与其相邻的上一级移位寄存器的输出信号端相连。
  13. 一种显示装置，包括如权利要求12所述的驱动控制电路。
  14. 如权利要求13所述的显示装置，其中，所述显示装置包括多条发光控制信号线；所述驱动控制电路中的每一级移位寄存器的信号输出端与一条发光控制信号线连接。
  15. 如权利要求13所述的显示装置，其中，所述驱动控制电路为栅极驱动电路。
  16. 一种如权利要求1-11任一项所述的移位寄存器的驱动方法，包括：第一阶段、第二阶段、第三阶段以及第四阶段；
    在所述第一阶段，所述输入子电路在所述第一时钟信号端的控制下，将所述输入信号端的信号提供给所述第一节点，以及将所述第一时钟信号端的信号提供给所述第二节点；所述第二控制子电路在所述第二节点的信号的控制下将所述第二参考信号端的信号提供给所述第三节点；所述第三控制子电路在所述第三节点的控制下将所述第一参考信号端的信号提供给所述第一节点；所述第二输出子电路在所述第三节点的信号的控制下将所述第一参考信号端的信号提供给所述输出信号端；
    在所述第二阶段，所述第二控制子电路在所述第二节点的信号的控制下将所述第二参考信号端的信号提供给所述第三节点；所述第三控制子电路在所述第三节点的控制下将所述第一参考信号端的信号提供给所述第一节点；所述第二输出子电路在所述第三节点的信号的控制下将所述第一参考信号端的信号提供给所述输出信号端；
    在所述第三阶段，所述输入子电路在所述第一时钟信号端的控制下，将所述输入信号端的信号提供给所述第一节点，以及将所述第一时钟信号端的信号提供给所述第二节点；所述第一控制子电路在所述第一节点的控制下将所述第一参考信号端的信号提供给所述第二节点；所述第二控制子电路在所述第一节点的信号的控制下将所述第一参考信号端的信号提供给所述第三节点；所述第一输出子电路在所述第一节点的信号的控制下将所述第二参考信号端的信号提供给所述输出信号端；
    在所述第四阶段，所述节点稳定子电路稳定所述第一节点的电位；所述第一控制子电路在所述第一节点的控制下将所述第一参考信号端的信号提供给所述第二节点；所述第二控制子电路在所述第一节点的信号的控制下将所述第一参考信号端的信号提供给所述第三节点；所述第一输出子电路在所述第一节点的信号的控制下将所述第二参考信号端的信号提供给所述输出信号端。
  17. 如权利要求16所述的驱动方法，在所述第一阶段之后，且在所述第二阶段之前，还包括：至少一个插入阶段；其中，所述插入阶段包括第一插入子阶段与第二插入子阶段；
    在所述第一插入子阶段，所述第二控制子电路在所述第二节点的信号的控制下将所述第二参考信号端的信号提供给所述第三节点；所述第三控制子电路在所述第三节点的控制下将所述第一参考信号端的信号提供给所述第一节点；所述第二输出子电路在所述第三节点的信号的控制下将所述第一参考信号端的信号提供给所述输出信号端；
    在所述第二插入子阶段，所述输入子电路在所述第一时钟信号端的控制下，将所述输入信号端的信号提供给所述第一节点，以及将所述第一时钟信号端的信号提供给所述第二节点；所述第二控制子电路在所述第二节点的信号的控制下将所述第二参考信号端的信号提供给所述第三节点；所述第三控制子电路在所述第三节点的控制下将所述第一参考信号端的信号提供给所述第一节点；所述第二输出子电路在所述第三节点的信号的控制下将所述第一参考信号端的信号提供给所述输出信号端。
  18. 如权利要求17所述的驱动方法，其中，所述第一时钟信号端的信号与所述第二时钟信号端的信号的周期相同，并且所述第一时钟信号端的有效脉冲信号的时长占一个时钟周期的时长的百分比与所述第二时钟信号端的有效脉冲信号的时长占一个所述时钟周期的时长的百分比相同；
    所述第一时钟信号端的有效脉冲信号的时长占一个所述时钟周期的时长的百分比小于或等于50％。
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