WO2019140943A1 - 移位寄存器及其驱动方法、栅极驱动电路 - Google Patents

移位寄存器及其驱动方法、栅极驱动电路 Download PDF

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Publication number
WO2019140943A1
WO2019140943A1 PCT/CN2018/106986 CN2018106986W WO2019140943A1 WO 2019140943 A1 WO2019140943 A1 WO 2019140943A1 CN 2018106986 W CN2018106986 W CN 2018106986W WO 2019140943 A1 WO2019140943 A1 WO 2019140943A1
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Prior art keywords
pull
circuit
node
coupled
sub
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PCT/CN2018/106986
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English (en)
French (fr)
Inventor
冯思林
孙丽
王迎
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP18857433.9A priority Critical patent/EP3742424B1/en
Priority to US16/337,135 priority patent/US11373576B2/en
Publication of WO2019140943A1 publication Critical patent/WO2019140943A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present application belongs to the field of display technologies, and in particular, to a shift register, a driving method thereof, and a gate driving circuit.
  • the current display market is occupied by a flat panel display, and a common flat panel display device is represented by an LCD (Liquid Crystal Display) or an OLED (Organic Light Emitting Diode) display device.
  • LCD Liquid Crystal Display
  • OLED Organic Light Emitting Diode
  • each pixel is driven line by line or interlaced by a shift register (Shift Register).
  • a shift register (Shift Register).
  • Each row of pixels is driven by a shift register, and a plurality of shift registers constitute a gate drive circuit.
  • Each of the shift registers includes a plurality of Thin Film Transistors (TFTs) or Storage Capacitors (Cs).
  • TFTs Thin Film Transistors
  • Cs Storage Capacitors
  • the current gate drive circuit uses GOA (Gate driver On Array) technology, which is a gate drive circuit composed of thin film transistors integrated on the substrate. Since GOA technology has the advantages of reducing cost and improving module process yield, The more widely used.
  • a shift register including: an input sub-circuit coupled to an input signal terminal and a first clock signal terminal, and configured to be at a first clock signal end of the first clock signal Controlling, the input signal provided by the input signal terminal is output to the pull-up node; the output sub-circuit is coupled to the input sub-circuit, the output end and the second clock signal end, and is set to be under the control of the potential of the pull-up node And outputting the second clock signal of the second clock signal end to the output end; the reset control sub-circuit is coupled to the pull-down node, the input signal end, the first clock signal end, and the level signal respectively And configured to control a potential of the pull-down node according to the input signal and the first clock signal; a reset sub-circuit coupled to the output end, the pull-down node, the pull-up node, and the level signal end, And being set to reset the potential of the pull-up node and the output terminal under the control of the potential of the
  • the input sub-circuit includes a first transistor and a second transistor, wherein: the first transistor has a control electrode and a first pole coupled to the input signal terminal, and a second pole The first transistor of the second transistor is coupled; the second transistor has a control electrode coupled to the first clock signal end, and a second electrode coupled to the pull-up node.
  • the output sub-circuit includes a third transistor and a first capacitor, wherein: the third transistor has a control electrode coupled to the pull-up node, a first pole thereof and the second clock The signal terminal is coupled to the second terminal and the output terminal, the first capacitor has a first end coupled to the control electrode of the third transistor, and a second end coupled to the second transistor Polar coupling.
  • the reset sub-circuit includes: an output reset sub-circuit coupled to the output terminal, the pull-down node, and the level signal terminal, and configured to be at a potential of the pull-down node Controlling, resetting, the potential of the output terminal to a level signal provided by the level signal terminal; and a pull-up node reset sub-circuit coupled to the pull-up node, the pull-down node, and the level a signal terminal, and is arranged to reset the potential of the pull-up node to a level signal provided by the level signal terminal under the control of the potential of the pull-down node.
  • the output reset sub-circuit includes a fourth transistor having a control electrode coupled to the pull-down node, a first pole coupled to the output terminal, a second pole coupled to the level
  • the signal terminal is coupled to the signal
  • the pull-up node reset sub-circuit includes a seventh transistor, the control electrode is coupled to the pull-down node, the first pole is coupled to the pull-up node, and the second pole is coupled to the The flat signal ends are coupled.
  • the reset control sub-circuit includes a fifth transistor, a sixth transistor, and a second capacitor, wherein: the fifth transistor has a control electrode and a first pole coupled to the first clock signal terminal The second transistor is coupled to the pull-down node; the sixth transistor has a control electrode coupled to the input signal terminal, and a first pole coupled to the second electrode of the fifth transistor, the first a second pole is coupled to the level signal terminal; the second capacitor has a first end coupled to the first pole of the sixth transistor, and a second end coupled to the second pole of the sixth transistor Pick up.
  • a ratio of a width to length ratio of the fifth transistor to a width to length ratio of the sixth transistor is 1:5.
  • a driving method of the above shift register unit comprising: an input sub-circuit coupled to the output sub-circuit, an input signal terminal, and a first clock signal An output sub-circuit coupled to the output end and the second clock signal end; a reset control sub-circuit coupled to the pull-down node, the input signal end, the first clock signal end, and the level signal end a reset sub-circuit coupled to the output terminal, the pull-down node, the pull-up node, and the level signal terminal, the method comprising: providing a first clock signal and an input signal end provided at a first clock signal end Under the control of the input signal, the input signal is output to the pull-up node through the input sub-circuit; under the control of the potential of the pull-up node, the second clock signal is output to the output terminal through the output sub-circuit; the reset control sub-circuit Controlling a potential of the pull-down node according to the first clock signal and the input signal; re
  • the first clock signal and the second clock signal are complementary pulse signals.
  • each time period for driving the shift register is divided into an input phase, an output phase, a reset phase, and a hold phase
  • the method includes: in the input phase, by the a clock signal terminal providing a first level of the first clock signal, the input signal terminal providing a first level of the input signal, such that the input sub-circuit outputs the input signal to the Pulling up the node, and causing the output sub-circuit to output a second clock signal of a second level different from the first level to the output; at the output stage, passing the first clock signal Providing a second level of the first clock signal, the second level of the input signal being provided by the input signal terminal, such that the output sub-circuit maintains the pull-up node at the input stage a potential, and causing the output sub-circuit to output a second clock signal of a first level to the output; in the reset phase, providing the first level by the first clock signal end a clock signal, the input signal is provided by the input signal terminal, and the second clock signal of the second level is
  • a gate driving circuit including the above-described shift register unit in which a plurality of stages of the shift register unit are cascade-coupled is provided.
  • the output of the shift register of the previous stage is coupled to the input signal terminal of the shift register of the present stage.
  • 1 is a schematic diagram of a conventional gate driving circuit composed of a plurality of cascaded shift registers
  • FIG. 2 is a block diagram of a shift register in an embodiment of the present disclosure
  • FIG. 3 is a circuit diagram of a shift register in an embodiment of the present disclosure.
  • FIG. 4 is a timing diagram of a gate driving circuit in an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a gate drive circuit composed of cascaded plurality of shift registers in an embodiment of the present disclosure.
  • the gate drive circuit must ensure that the pixel has a certain charging time, so it is necessary to set some low or high hold points.
  • the shift registers of the stages are usually cascade-connected and disposed in the non-display area around the display area. For a certain shift register, the output signal of the previous stage is used as the input signal, and the output signal of the next stage is used as the reset signal, and the stages are closely related to each other. The above reasons lead to an increase in the area and power consumption of the GOA, which hinders the realization of the narrow bezel.
  • At least the reset signal of the shift register in the prior art is generally provided by the previous shift register to cause waste of the area of the GOA and increase power consumption, and provides a shift register that realizes self-reset by its own circuit structure.
  • the next shift register is not needed to reset the signal of the shift register of the current stage, the power consumption is low, the number of signal lines is small, and the circuit structure and layout are simplified.
  • the shift register includes an input sub-circuit 1, an output sub-circuit 2, a reset sub-circuit 3, and a reset control sub-circuit 4.
  • the input sub-circuit 1 is coupled to the output sub-circuit 2, the input signal end and the first clock signal end, and is arranged to output the input signal Input to the pull-up node PU under the control of the first clock signal CLKA of the first clock signal end.
  • the output sub-circuit 2 is coupled to the output terminal and the second clock signal terminal, and is configured to output the second clock signal CLKB of the second clock signal terminal to the output terminal under the control of the potential of the pull-up node PU.
  • the reset sub-circuit 3 is coupled to the output terminal, the pull-down node PD, the pull-up node PU, and the level signal terminal, and is configured to reset the potentials of the pull-up node PU and the output terminal OUT under the control of the potential of the pull-down node PD.
  • the reset control sub-circuit 4 is respectively coupled to the pull-down node PD, the input signal end, the first clock signal end and the level signal end, which are set according to the input signal Input of the input signal end and the first clock signal CLKA of the first clock signal end
  • the potential of the pull-down node PD is controlled such that the reset sub-circuit 3 resets the potential of the pull-up node PU and the output terminal OUT to the level signal VGL, wherein the level signal VGL is a signal having a constant level (for example, a constant low level signal) ).
  • the coupling point of the input sub-circuit 1 and the output sub-circuit 2 is a pull-up node PU
  • the coupling point of the reset control sub-circuit 4 and the reset sub-circuit 3 is a pull-down node PD.
  • the input sub-circuit 1 and the reset control sub-circuit 4 use the same input signal Input, and do not require the next shift register to reset the previous shift register, and the number of signal lines is small, simplifying the circuit structure and layout. wiring.
  • the input sub-circuit 1 introduces an input signal Input to charge the pull-up node PU.
  • the input sub-circuit 1 includes a first transistor M1 and a second transistor M2.
  • the first transistor M1 has a control electrode and a first pole coupled to the input signal terminal (for receiving the input signal Input), and a second pole coupled to the first electrode of the second transistor M2.
  • the second transistor M2 has a control electrode coupled to the first clock signal terminal (for receiving the first clock signal CLKA), and a second pole coupled to the pull-up node PU, that is, coupled to the output sub-circuit 2.
  • the output sub-circuit 2 outputs a gate drive signal of the present stage, and the output sub-circuit 2 includes a third transistor M3 and a first capacitor C1.
  • the third transistor M3 has a control electrode coupled to the pull-up node, a first pole coupled to the second clock signal terminal (for receiving the second clock signal CLKB), and a second pole and an output terminal (for transmitting the output) The signal OUT) is coupled.
  • the first capacitor C1 has a first end coupled to the control electrode of the third transistor M3 and a second end coupled to the second electrode of the third transistor M3.
  • the reset sub-circuit 3 implements a reset function, and the reset sub-circuit 3 includes a fourth transistor M4 and a seventh transistor M7.
  • the fourth transistor M4 has a control electrode coupled to the pull-down node PD, a first pole coupled to the output terminal, and a second pole coupled to the level signal terminal (for receiving the level signal VGL).
  • the seventh transistor M7 has a control electrode coupled to the pull-down node PD, a first pole coupled to the pull-up node PU, and a second pole coupled to the level signal terminal (for receiving the level signal VGL).
  • the reset control sub-circuit 4 controls the potential of the pull-down node PD to be the level signal VGL by the same input signal Input and the first clock signal CKLA as the input sub-circuit 1 to cause the reset sub-circuit 3 to be reset, and reset in the reset sub-circuit 3
  • the reset sub-circuit 3 is then held at the potential of the pull-up node PU by controlling the potential of the pull-down node PD to maintain the potential of the output terminal.
  • the reset control sub-circuit 4 includes a fifth transistor M5, a sixth transistor M6, and a second capacitor C2.
  • the fifth transistor M5 has a control electrode and a first pole coupled to the first clock signal end, and a second pole coupled to the pull-down node PD.
  • the sixth transistor M6 has a control electrode coupled to the input signal terminal, a first electrode coupled to the second electrode of the fifth transistor M5, and a second electrode coupled to the level signal terminal.
  • the second capacitor C2 has a first end coupled to the first electrode of the sixth transistor M6 and a second end coupled to the second electrode of the sixth transistor M6.
  • the transistors of each of the sub-circuits described above are all N-type transistors.
  • the transistors in the above sub-circuits may all be N-type thin film transistors or may be P-type thin film transistors; or a combination of N-type thin film transistors and P-type thin film transistors.
  • the first and second poles of the transistor may correspond to one of the source and the drain, respectively, and the other.
  • different types of thin film transistors can be selected, and only the port polarity of the transistor of the selected type can be changed according to the polarity of the transistor of the embodiment of the present disclosure. Flexible control, not detailed here.
  • an embodiment of the present disclosure further provides a driving method of the above shift register, where the driving method includes a first stage, a second stage, a third stage, and a fourth stage.
  • the input signal is output to the pull-up node through the input sub-circuit 1 under the control of the first clock signal and the input signal.
  • the first phase the input phase, is used to pull up the level of the pull-up node PU to a high level according to the input signal Input and the first clock signal CLKA, and pull down the potential of the pull-down node PD to a low level.
  • the second clock signal is output to the output through the output sub-circuit 2 under the control of the potential of the pull-up node.
  • the second stage that is, the output stage, is used to output the gate drive signal of the current stage according to the second clock signal CLKB when the pull-up node is at a high level.
  • the potential of the pull-down node PD is controlled, and under the control of the potential of the pull-down node PD, the potential of the pull-up node PU and the output terminal is reset by the reset sub-circuit 3.
  • the third phase, the reset phase is for charging the pull-down node PD according to the input signal Input and the first clock signal CLKA, thereby resetting the pull-up node PU and the output terminal.
  • the potential of the pull-down node PD is controlled by the reset control sub-circuit 4, so that the reset sub-circuit 3 resets the potential of the pull-up node PU and the output terminal to the level Signal VGL.
  • the fourth phase the hold phase, is used to maintain the pull-up node PU and the output low when the pull-down node PD is at a high level.
  • the first clock signal CLKA and the second clock signal CLKB are complementary pulse signals. That is, when the first clock signal CLKA is at a high level, the second clock signal CLKB is at a low level; when the first clock signal CLKA is at a low level, the second clock signal CLKB is at a high level. According to the timing of the first clock signal CLKA and the second clock signal CLKB, the existing clock timing can be directly adopted to avoid complicated clock design.
  • the output signal OUT of the previous stage shift register is the input signal Input of the input sub-circuit 1 and the reset sub-circuit 3 of the shift register of the stage. Since the input signal Input is used in both the input phase and the hold phase, the next shift register is not required to provide a reset signal to the shift register of the stage, simplifying the circuit.
  • the specific driving process of the driving method of the shift register includes an input phase, an output phase, a reset phase, and a hold phase.
  • the input signal Input and the first clock signal CLKA are at a high level
  • the second clock signal CLKB is at a low level
  • the first clock signal CLKA is valid
  • the first transistor M1 The second transistor M2 is turned on to charge the pull-up node PU; at the same time, the sixth transistor M6 is turned on, the second capacitor C2 is discharged through the sixth transistor M6, and the fifth transistor M5 is turned on, by setting the fifth transistor M5
  • the width to length ratio is smaller than the aspect ratio of the sixth transistor M6, and the pull-down node PD is pulled down to the low level signal VGL, so that the fourth transistor M4 and the seventh transistor M7 are turned off to ensure the normal input of the shift register;
  • the first transistor M1 and the second transistor M2 are turned on, and the first capacitor C1 is charged, that is, the pull-up node PU is charged, and the pull-up node PU is at a high level.
  • the third transistor M3 is turned on, because the second clock signal is at this time. CLKB is low, so the output is low.
  • the ratio of the aspect ratio of the fifth transistor M5 to the aspect ratio of the sixth transistor M6 is set to 1:5, so that the pull-down node PD is stably pulled down to a low level while avoiding the sixth transistor.
  • the occupied area of the M6 is too large.
  • the first clock signal CLKA the input signal Input is low level
  • the second clock signal CLKB is high level
  • the second clock signal CLKB is valid, due to the retention of the first capacitor C1
  • the pull-up node PU is kept at a high level
  • the third transistor M3 is turned on, and the output terminal outputs a high-level output signal OUT, that is, the shift register outputs the gate drive signal of the current stage.
  • the first clock signal CLKA is at a high level
  • the second clock signal CLKB and the input signal Input are at a low level. Since the input signal Input is low, the first transistor M1 and the sixth transistor M6 are turned off; the first clock signal CLKA is active, the fifth transistor M5 is turned on, and the second capacitor C2 is charged to the pull-down node PD through the fifth transistor M5. At this time, the pull-down node PD is at a high level, the fourth transistor M4 and the seventh transistor M7 are turned on, and the pull-up node PU and the output terminal are pulled low to achieve a reset, thereby implementing a self-reset function.
  • the input signal Input is kept at a low level, and when the second clock signal CLKB is at a high level, since the pull-up node PU is at a low level, the third transistor M3 is turned off, and the output The terminal is floated so as to substantially maintain the previous level, while the fifth transistor M5 and the sixth transistor M6 are turned off, the pull-down node PD is floated, thereby substantially maintaining the previous level, and due to the presence of the second capacitor C2, the pull-down is performed.
  • the node PD can maintain the previous level more stably; when the first clock signal CLKA is at a high level, the fifth transistor M5 is turned on, the second capacitor C2 is charged by the fifth transistor M5, and the pull-down node PD is at a high level, The four transistors M4 and the seventh transistor M7 are turned on, at which time the pull-up node PU and the output terminal are kept in a low state until the next frame input signal Input is valid.
  • the shift register is designed as a shift register including a gate drive circuit (GOA) of 7T2C, and the number of transistors and the number of signal lines are greatly reduced, the circuit structure and layout are simplified, and the structure is simple; in the corresponding driving method, In the hold phase, the pull-up node PU and the output signal OUT are kept at a low level. Before the next frame, the shift register of the stage is always at this stage, and the reset state is maintained.
  • GOA gate drive circuit
  • the shift register and its corresponding driving method realize the reset phase and the hold phase by the input signal Input and the corresponding circuit coupling, and do not need the next-stage shift register to reset the signal of the shift register of the current stage, but
  • the self-reset is realized by its own circuit structure, so that the shift register can achieve continuous reset, weaken the cascade relationship of the upper and lower shift registers, low power consumption, small number of signal lines, simplify circuit structure and layout.
  • the embodiment of the present disclosure further provides a gate driving circuit and a corresponding driving method thereof.
  • the gate driving circuit includes the above-mentioned shift register, and the multi-stage shift register is cascade-coupled to realize multi-line driving.
  • the output signal OUT of the shift register of the previous stage is the input sub-circuit of the shift register of the stage and the input signal of the reset sub-circuit.
  • the output signal of the gate drive circuit except the output signal of the previous stage shift register is used as the input signal of the next stage shift register, Additional interstage signal coupling is required to ensure low power consumption, save area, and a small number of signal lines, simplifying circuit structure and layout, and making the display panel's frame narrower, which is more conducive to narrow frame design.
  • the shift register provided by the embodiment of the present disclosure may be applied to a row scanning circuit of a display device, or an interlaced scanning circuit, and configured as the above-mentioned row scanning circuit, or the interlaced scanning circuit provides a corresponding gate. Pole drive signal.
  • the above display devices include, but are not limited to, LCD, OLED.

Abstract

移位寄存器及其驱动方法、栅极驱动电路。该移位寄存器中：输入子电路（1）用于在第一时钟信号端的第一时钟信号的控制下将输入信号输出至上拉节点；输出子电路（2）用于在上拉节点的电位的控制下，将第二时钟信号端的第二时钟信号输出至输出端；复位子电路（3）用于在下拉节点的电位的控制下，复位上拉节点和输出端的电位；复位控制子电路（4）用于控制下拉节点的电位，以复位上拉节点和输出端的电位至电平信号。

Description

移位寄存器及其驱动方法、栅极驱动电路
相关申请的交叉引用
本申请要求于2018年1月19日提交至中国知识产权局的中国专利申请No.201810054237.6的优先权，其全部内容以引用的方式合并于此。
技术领域
本申请属于显示技术领域，具体涉及一种移位寄存器及其驱动方法、栅极驱动电路。
背景技术
目前的显示市场由平板显示占据，常见的平板显示装置以LCD(Liquid Crystal Display：液晶显示装置)、OLED(Organic Light Emitting Diode：有机发光二极管)显示装置为代表。
在平板显示装置中，各像素通过移位寄存器(Shift Register)逐行或隔行驱动。每一行像素由一个移位寄存器进行驱动，多个移位寄存器构成栅极驱动电路。每一移位寄存器均包括多个薄膜晶体管(Thin Film Transistor：简称TFT)或存储电容(Storage Capacitor，简称Cs)。目前的栅极驱动电路多采用GOA(Gate driver On Array)技术，即在基板上集成薄膜晶体管组成的栅极驱动电路，由于GOA技术具有降低成本、提升模组工艺产量等优点，因此得到越来越广泛的应用。
发明内容
根据本公开的一个方面，提供一种移位寄存器，包括：输入子电路，其耦接至输入信号端和第一时钟信号端，并设置为在所述第一时钟信号端的第一时钟信号的控制下将所述输入信号端提供的输入信号输出至上拉节点；输出子电路，其耦接至输入子电路、输出端和第二时钟信号端，并设置为在上拉节点的电位的控制下，将所述第二 时钟信号端的第二时钟信号输出至所述输出端；复位控制子电路，其分别耦接至所述下拉节点、输入信号端、所述第一时钟信号端和电平信号端，并设置为根据所述输入信号和所述第一时钟信号控制下拉节点的电位；复位子电路，其耦接至所述输出端、下拉节点、上拉节点和所述电平信号端，并设置为在下拉节点的电位的控制下，复位所述上拉节点和所述输出端的电位。
在一个实施例中，所述输入子电路包括第一晶体管和第二晶体管，其中：所述第一晶体管，其控制极和第一极与所述输入信号端耦接，其第二极与所述第二晶体管的第一极耦接；所述第二晶体管，其控制极与第一时钟信号端耦接，其第二极与所述上拉节点耦接。
在一个实施例中，所述输出子电路包括第三晶体管和第一电容，其中：所述第三晶体管，其控制极与所述上拉节点耦接，其第一极与所述第二时钟信号端耦接，其第二极与输出端耦接，所述第一电容，其第一端与所述第三晶体管的控制极耦接，其第二端与所述第三晶体管的第二极耦接。
在一个实施例中，所述复位子电路包括：输出复位子电路，其耦接至所述输出端、所述下拉节点和所述电平信号端，并设置为在所述下拉节点的电位的控制下，将所述输出端的电位复位至所述电平信号端提供的电平信号；以及上拉节点复位子电路，其耦接至所述上拉节点、所述下拉节点和所述电平信号端，并设置为在所述下拉节点的电位的控制下，将所述上拉节点的电位复位至所述电平信号端提供的电平信号。
在一个实施例中，所述输出复位子电路包括包括第四晶体管，其控制极与所述下拉节点耦接，其第一极与所述输出端耦接，其第二极与所述电平信号端耦接；所述上拉节点复位子电路包括第七晶体管，其控制极与所述下拉节点耦接，其第一极与所述上拉节点耦接，其第二极与所述电平信号端耦接。
在一个实施例中，所述复位控制子电路包括第五晶体管、第六晶体管和第二电容，其中：所述第五晶体管，其控制极和第一极与所述第一时钟信号端耦接，其第二极与所述下拉节点耦接；所述第六晶 体管，其控制极与所述输入信号端耦接，其第一极与所述第五晶体管的第二极耦接，其第二极与所述电平信号端耦接；所述第二电容，其第一端与所述第六晶体管的第一极耦接，其第二端与所述第六晶体管的第二极耦接。
在一个实施例中，所述第五晶体管的宽长比与所述第六晶体管的宽长比之比为1∶5。
根据本公开的另一方面，提供一种上述的移位寄存器单元的驱动方法，所述移位寄存器包括：输入子电路，其耦接至所述输出子电路、输入信号端和第一时钟信号端；输出子电路，其耦接至输出端和第二时钟信号端；复位控制子电路，其分别耦接至所述下拉节点、输入信号端、所述第一时钟信号端和电平信号端；复位子电路，其耦接至所述输出端、下拉节点、上拉节点和所述电平信号端，所述方法包括：在第一时钟信号端提供的第一时钟信号和输入信号端提供的输入信号的控制下，通过输入子电路将输入信号输出至上拉节点；在上拉节点的电位的控制下，通过输出子电路将第二时钟信号输出至所述输出端；由复位控制子电路根据所述第一时钟信号和所述输入信号控制所述下拉节点的电位；在所述下拉节点的电位的控制下，通过复位子电路复位上拉节点和输出端的电位至所述电平信号端提供的电平信号。
在一个实施例中，所述第一时钟信号和所述第二时钟信号为互补脉冲信号。
在一个实施例中，用于驱动所述移位寄存器的每个时间周期被分为输入阶段、输出阶段、复位阶段和保持阶段，并且所述方法包括：在所述输入阶段，通过所述第一时钟信号端提供第一电平的所述第一时钟信号，通过所述输入信号端提供第一电平的所述输入信号，以使得所述输入子电路将所述输入信号输出至所述上拉节点，并且使得所述输出子电路将与所述第一电平不同的第二电平的第二时钟信号输出至所述输出端；在所述输出阶段，通过所述第一时钟信号端提供第二电平的所述第一时钟信号，通过所述输入信号端提供第二电平的所述输入信号，以使得所述输出子电路保持所述上拉节点在所述输入阶 段的电位，并且使得所述输出子电路将第一电平的第二时钟信号输出至所述输出端；在所述复位阶段，通过所述第一时钟信号端提供第一电平的所述第一时钟信号，通过所述输入信号端提供第二电平的所述输入信号，通过所述第二时钟信号端提供第二电平的所述第二时钟信号，以使得所述复位控制子电路将所述下拉节点的电位控制为第一电平，并且使得复位子电路复位所述上拉节点和所述输出端的电位至所述电平信号；以及在所述保持阶段，通过所述复位控制子电路保持所述下拉节点在所述复位阶段的电位，并且通过所述复位子电路保持所述上拉节点和所述输出端在所述复位阶段的电位。
根据本公开的再一方面，提供一种栅极驱动电路，包括上述移位寄存器单元，多级所述移位寄存器单元级联耦接。
在一个实施例中，前一级所述移位寄存器的输出端与本级所述移位寄存器的所述输入信号端耦接。
附图说明
图1为现有的由级联的多个移位寄存器组成的栅极驱动电路的示意图；
图2为本公开实施例中的移位寄存器的框图；
图3为本公开实施例中移位寄存器的电路示意图；
图4为本公开实施例中栅极驱动电路的时序图；
图5为本公开实施例中由级联的多个移位寄存器组成的栅极驱动电路的示意图。
具体实施方式
为使本领域技术人员更好地理解本公开实施例的技术方案，下面结合附图和具体实施方式对本公开实施例提供的移位寄存器及其驱动方法、栅极驱动电路及其驱动方法和显示基板作进一步详细描述。
栅极驱动电路必须保证像素具备一定的充电时间，因此需要设置一些低电平或高电平的保持点。另外，如图1所示，各级移位寄存 器通常级联连接并设置在显示区周边的非显示区。对某一移位寄存器而言，采用上一级的输出信号作为输入信号、下一级的输出信号作为复位信号，各级间互相紧密关联。上述的原因导致GOA的面积和功耗的增加，阻碍了窄边框的实现。
随着科技的进步和生产力的发展，对于栅极驱动电路的稳定性、功耗和窄边框的需求越来越高，欲满足这些需求，改变电路结构、减少GOA电路的TFT数量和信号线数目是最直接的路径。
本公开实施例至少针对现有技术中的移位寄存器的复位信号通常由上一个移位寄存器提供导致浪费GOA的面积和增加功耗的问题，提供一种移位寄存器通过自身电路结构实现自复位，不需要下一个移位寄存器给本级移位寄存器复位信号，功耗低，信号线数量少，简化电路结构和布局布线。
如图2所示，该移位寄存器包括输入子电路1、输出子电路2、复位子电路3和复位控制子电路4。
输入子电路1，耦接至输出子电路2、输入信号端和第一时钟信号端，其设置为在第一时钟信号端的第一时钟信号CLKA的控制下将输入信号Input输出至上拉节点PU。
输出子电路2，耦接至输出端和第二时钟信号端，其设置为在上拉节点PU的电位的控制下，将第二时钟信号端的第二时钟信号CLKB输出至输出端。
复位子电路3，耦接至输出端、下拉节点PD、上拉节点PU和电平信号端，其设置为在下拉节点PD的电位的控制下，复位上拉节点PU和输出端OUT的电位。
复位控制子电路4，分别耦接至下拉节点PD、输入信号端、第一时钟信号端和电平信号端，其设置为根据输入信号端的输入信号Input和第一时钟信号端的第一时钟信号CLKA控制下拉节点PD的电位，以使得复位子电路3复位上拉节点PU和输出端OUT的电位至电平信号VGL，其中电平信号VGL是具有恒定电平的信号(例如，恒定低电平信号)。
该移位寄存器中，输入子电路1与输出子电路2的耦接点为上拉节点PU，复位控制子电路4与复位子电路3的耦接点为下拉节点PD。
在该移位寄存器中，输入子电路1和复位控制子电路4使用相同的输入信号Input，不需要下一个移位寄存器给上一个移位寄存器复位信号，信号线数量少，简化电路结构和布局布线。
参考图3，以下将对各子电路的结构进行详细说明：
输入子电路1引入输入信号Input，实现对上拉节点PU充电。输入子电路1包括第一晶体管M1和第二晶体管M2。
第一晶体管M1，其控制极和第一极与输入信号端(用于接收输入信号Input)耦接，其第二极与第二晶体管M2的第一极耦接。
第二晶体管M2，其控制极与第一时钟信号端(用于接收第一时钟信号CLKA)耦接，其第二极与上拉节点PU耦接，也即与输出子电路2耦接。
输出子电路2输出本级栅极驱动信号，输出子电路2包括第三晶体管M3和第一电容C1。
第三晶体管M3，其控制极与上拉节点耦接，其第一极与第二时钟信号端(用于接收第二时钟信号CLKB耦接)，其第二极与输出端(用于传输输出信号OUT)耦接。
第一电容C1，其第一端与第三晶体管M3的控制极耦接，其第二端与第三晶体管M3的第二极耦接。
复位子电路3实现复位功能，复位子电路3包括第四晶体管M4和第七晶体管M7。
第四晶体管M4，其控制极与下拉节点PD耦接，其第一极与输出端耦接，其第二极与电平信号端(用于接收电平信号VGL)耦接。
第七晶体管M7，其控制极与下拉节点PD耦接，其第一极与上拉节点PU耦接，其第二极与电平信号端(用于接收电平信号VGL)耦接。
复位控制子电路4通过与输入子电路1相同的输入信号Input和第一时钟信号CKLA控制下拉节点PD的电位为电平信号VGL以使复 位子电路3实现复位，并在复位子电路3实现复位后通过控制下拉节点PD的电位而使复位子电路3保持上拉节点PU的电位，以保持输出端的电位。复位控制子电路4包括第五晶体管M5、第六晶体管M6和第二电容C2。
第五晶体管M5，其控制极和第一极与第一时钟信号端耦接，其第二极与下拉节点PD耦接。
第六晶体管M6，其控制极与输入信号端耦接，其第一极与第五晶体管M5的第二极耦接，其第二极与电平信号端耦接。
第二电容C2，其第一端与第六晶体管M6的第一极耦接，其第二端与第六晶体管M6的第二极耦接。
在一些实施例中，上述各子电路的晶体管均为N型晶体管。事实上，上述各子电路中的晶体管可以均为N型薄膜晶体管或者可以均为P型薄膜晶体管；或者为N型薄膜晶体管与P型薄膜晶体管的组合。晶体管的第一极和第二极可以分别对应源极和漏极中的一者和另一者。根据不同的应用场合，可以选用不同类型的薄膜晶体管，只需同时将选定类型的晶体管的端口极性按本公开实施例晶体管的端口极性在耦接上做相应的改变即可，从而实现灵活控制，这里不再详述。
相应的，本公开实施例还提供一种上述移位寄存器的驱动方法，该驱动方法包括第一阶段、第二阶段、第三阶段和第四阶段。
在第一阶段，在第一时钟信号和输入信号的控制下，通过输入子电路1将输入信号输出至上拉节点。第一阶段即输入阶段，用于根据输入信号Input和第一时钟信号CLKA，将上拉节点PU的电平上拉为高电平，同时将下拉节点PD的电位下拉为低电平。
在第二阶段，在上拉节点的电位的控制下，通过输出子电路2将第二时钟信号输出至输出端。第二阶段即输出阶段，用于在上拉节点为高电平的情况下，根据第二时钟信号CLKB，输出本级栅极驱动信号。
在第三阶段，在第一时钟信号的控制下，控制下拉节点PD的电位，在下拉节点PD的电位的控制下，通过复位子电路3复位上拉节点PU和输出端的电位。第三阶段即复位阶段，用于根据输入信号 Input和第一时钟信号CLKA，对下拉节点PD充电，从而对上拉节点PU和输出端复位。
在第四阶段，在第一时钟信号CLKA和输入信号Input的控制下，通过复位控制子电路4控制下拉节点PD的电位，以使得复位子电路3复位上拉节点PU和输出端的电位至电平信号VGL。第四阶段即保持阶段，用于在下拉节点PD为高电平的情况下，将上拉节点PU和输出端保持为低电平。
在一些实施例中，第一时钟信号CLKA和第二时钟信号CLKB为互补脉冲信号。即，第一时钟信号CLKA为高电平时，第二时钟信号CLKB为低电平；第一时钟信号CLKA为低电平时，第二时钟信号CLKB为高电平。根据第一时钟信号CLKA和第二时钟信号CLKB的时序，可直接采用现有的时钟时序，避免复杂的时钟设计。
其中，前一级移位寄存器的输出信号OUT为本级移位寄存器的输入子电路1和复位子电路3的输入信号Input。由于输入阶段和保持阶段均采用相同的输入信号Input，因此不需要下一个移位寄存器给本级移位寄存器提供复位信号，简化线路。
如图4所示，以所有晶体管为N型晶体管作为示例，该移位寄存器的驱动方法的具体驱动过程包括：输入阶段、输出阶段、复位阶段，以及保持阶段。
对应于前述第一阶段T1的输入阶段：输入信号Input和第一时钟信号CLKA为高电平，第二时钟信号CLKB为低电平，输入信号Input、第一时钟信号CLKA有效，第一晶体管M1、第二晶体管M2导通，以对上拉节点PU充电；同时，第六晶体管M6导通，第二电容C2通过第六晶体管M6放电，并且第五晶体管M5导通，通过设置第五晶体管M5的宽长比小于第六晶体管M6的宽长比，将下拉节点PD下拉至低电平的电平信号VGL，从而第四晶体管M4、第七晶体管M7关断，保证移位寄存器正常输入；由于第晶体管M1、第二晶体管M2导通，第一电容C1充电，即对上拉节点PU充电，上拉节点PU为高电平，此时第三晶体管M3导通，由于此时第二时钟信号CLKB为低电平，所以输出端输出低电平。在一个实施例中，设置第五晶体管 M5的宽长比与第六晶体管M6的宽长比之比为1∶5，以使得下拉节点PD被稳定地下拉至低电平，同时避免第六晶体管M6的占用面积过大。
对应于前述第二阶段T2的输出阶段：第一时钟信号CLKA、输入信号Input为低电平，第二时钟信号CLKB为高电平，第二时钟信号CLKB有效，由于第一电容C1的保持作用，上拉节点PU保持为高电平，第三晶体管M3导通，输出端输出高电平的输出信号OUT，即，该移位寄存器输出本级栅极驱动信号。
对应于前述第三阶段T3的复位阶段：第一时钟信号CLKA为高电平，第二时钟信号CLKB、输入信号Input为低电平。由于输入信号Input为低电平，第一晶体管M1、第六晶体管M6关断；第一时钟信号CLKA有效，第五晶体管M5导通，第二电容C2通过第五晶体管M5对下拉节点PD充电，此时下拉节点PD为高电平，第四晶体管M4和第七晶体管M7导通，上拉节点PU和输出端被拉低至低电平实现复位，从而实现自复位功能。
对应于前述第四阶段T4的保持阶段：输入信号Input保持为低电平，当第二时钟信号CLKB为高电平时，由于上拉节点PU为低电平，因此第三晶体管M3关断，输出端浮置，从而基本保持之前的电平，同时，第五晶体管M5和第六晶体管M6关断，下拉节点PD浮置，从而基本保持之前的电平，并且由于第二电容C2的存在，下拉节点PD能够更稳定地保持之前的电平；当第一时钟信号CLKA为高电平时，第五晶体管M5导通，第二电容C2通过第五晶体管M5充电，下拉节点PD为高电平，第四晶体管M4和第七晶体管M7导通，此时上拉节点PU和输出端保持低电平的状态，直至下一帧输入信号Input有效。
该移位寄存器中为包括7T2C的栅极驱动电路(GOA)的移位寄存器设计，晶体管数量和信号线数量均大大减少，简化了电路结构和布局布线，结构简单；在相应的驱动方法中，保持阶段将上拉节点PU、输出信号OUT保持为低电平，下一帧来之前，该级移位寄存器一直处于此阶段，实现对复位状态的保持。
可见，该移位寄存器及其相应的驱动方法，通过输入信号Input和相应的电路耦接而实现复位阶段和保持阶段，不需要下一级移位寄 存器给本级移位寄存器复位信号，而是通过自身电路结构实现自复位，使得该移位寄存器可实现持续复位，减弱上下移位寄存器的级联关系，功耗低，信号线数量少，简化电路结构和布局布线。
本公开实施例还提供一种栅极驱动电路及其相应的驱动方法，该栅极驱动电路包括上述的移位寄存器，多级移位寄存器级联耦接，从而实现多行驱动。
如图5所示，该栅极驱动电路中前一级移位寄存器的输出端与本级移位寄存器之间仅存在上一级输出端到本级输入端之间的耦接，前一级移位寄存器的输出端与本级移位寄存器的输入子电路和复位子电路耦接。
在上述移位寄存器的驱动方法的基础上，该栅极驱动电路的驱动方法中，前一级移位寄存器的输出信号OUT为本级移位寄存器的输入子电路和复位子电路的输入信号Input。
根据多个移位寄存器的输入信号关系，与现有的GOA电路设计相比，可知该栅极驱动电路中除了前一级移位寄存器的输出信号作为下一级移位寄存器的输入信号，不需要额外的级间信号耦接，能保证功耗低、节省面积，信号线数量少，简化电路结构和布局布线，使得显示面板的边框可以变得更窄，从而更利于窄边框设计。
可以理解的是，典型的，本公开实施例提供的移位寄存器可以被应用于显示装置的行扫描电路，或者隔行扫描电路中，并设置为上述行扫描电路，或者隔行扫描电路提供相应的栅极驱动信号。上述显示装置包括但不限于：LCD，OLED。
可以理解的是，以上实施方式仅仅是为了说明本公开实施例的原理而采用的示例性实施方式，然而本公开实施例并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开实施例的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (12)

  1. 一种移位寄存器，包括：
    输入子电路，其耦接至输入信号端和第一时钟信号端，并设置为在所述第一时钟信号端的第一时钟信号的控制下将所述输入信号端提供的输入信号输出至上拉节点；
    输出子电路，其耦接至所述输入子电路、输出端和第二时钟信号端，并设置为在上拉节点的电位的控制下，将所述第二时钟信号端的第二时钟信号输出至所述输出端；
    复位控制子电路，其分别耦接至所述下拉节点、输入信号端、所述第一时钟信号端和电平信号端，并设置为根据所述输入信号和所述第一时钟信号控制下拉节点的电位；
    复位子电路，其耦接至所述输出端、下拉节点、上拉节点和所述电平信号端，并设置为在下拉节点的电位的控制下，复位所述上拉节点和所述输出端的电位。
  2. 根据权利要求1所述的移位寄存器，其中，所述输入子电路包括第一晶体管和第二晶体管，其中：
    所述第一晶体管，其控制极和第一极与所述输入信号端耦接，其第二极与所述第二晶体管的第一极耦接；
    所述第二晶体管，其控制极与第一时钟信号端耦接，其第二极与所述上拉节点耦接。
  3. 根据权利要求1所述的移位寄存器，其中，所述输出子电路包括第三晶体管和第一电容，其中：
    所述第三晶体管，其控制极与所述上拉节点耦接，其第一极与所述第二时钟信号端耦接，其第二极与输出端耦接，
    所述第一电容，其第一端与所述第三晶体管的控制极耦接，其第二端与所述第三晶体管的第二极耦接。
  4. 根据权利要求1所述的栅极驱动电路，其中，所述复位子电路包括：
    输出复位子电路，其耦接至所述输出端、所述下拉节点和所述电平信号端，并设置为在所述下拉节点的电位的控制下，将所述输出端的电位复位至所述电平信号端提供的电平信号；以及
    上拉节点复位子电路，其耦接至所述上拉节点、所述下拉节点和所述电平信号端，并设置为在所述下拉节点的电位的控制下，将所述上拉节点的电位复位至所述电平信号端提供的电平信号。
  5. 根据权利要求4所述的栅极驱动电路，其中，
    所述输出复位子电路包括第四晶体管，其控制极与所述下拉节点耦接，其第一极与所述输出端耦接，其第二极与所述电平信号端耦接；
    所述上拉节点复位子电路包括第七晶体管，其控制极与所述下拉节点耦接，其第一极与所述上拉节点耦接，其第二极与所述电平信号端耦接。
  6. 根据权利要求1所述的移位寄存器，其中，所述复位控制子电路包括第五晶体管、第六晶体管和第二电容，其中：
    所述第五晶体管，其控制极和第一极与所述第一时钟信号端耦接，其第二极与所述下拉节点耦接；
    所述第六晶体管，其控制极与所述输入信号端耦接，其第一极与所述第五晶体管的第二极耦接，其第二极与所述电平信号端耦接；
    所述第二电容，其第一端与所述第六晶体管的第一极耦接，其第二端与所述第六晶体管的第二极耦接。
  7. 根据权利要求6所述的移位寄存器，其中，所述第五晶体管的宽长比与所述第六晶体管的宽长比之比为1∶5。
  8. 一种移位寄存器的驱动方法，
    所述移位寄存器包括：输入子电路，其耦接至输入信号端和第一时钟信号端；输出子电路，其耦接至输入子电路、输出端和第二时钟信号端；复位控制子电路，其分别耦接至下拉节点、输入信号端、第一时钟信号端和电平信号端；复位子电路，其耦接至输出端、下拉节点、上拉节点和电平信号端，
    所述方法包括：
    在第一时钟信号端提供的第一时钟信号和输入信号端提供的输入信号的控制下，通过输入子电路将输入信号输出至上拉节点；
    在上拉节点的电位的控制下，通过输出子电路将第二时钟信号段提供的第二时钟信号输出至所述输出端；
    由复位控制子电路根据所述第一时钟信号和所述输入信号控制所述下拉节点的电位；
    在所述下拉节点的电位的控制下，通过复位子电路复位上拉节点和输出端的电位至所述电平信号端提供的电平信号。
  9. 根据权利要求8所述的移位寄存器的驱动方法，其中，所述第一时钟信号和所述第二时钟信号为互补脉冲信号。
  10. 根据权利要求8所述的移位寄存器的驱动方法，其中，用于驱动所述移位寄存器的每个时间周期被分为输入阶段、输出阶段、复位阶段和保持阶段，并且
    所述方法包括：
    在所述输入阶段，通过所述第一时钟信号端提供第一电平的所述第一时钟信号，通过所述输入信号端提供第一电平的所述输入信号，以使得所述输入子电路将所述输入信号输出至所述上拉节点，并且使得所述输出子电路将与所述第一电平不同的第二电平的第二时钟信号输出至所述输出端；
    在所述输出阶段，通过所述第一时钟信号端提供第二电平的所述第一时钟信号，通过所述输入信号端提供第二电平的所述输入信号，以使得所述输出子电路保持所述上拉节点在所述输入阶段的电 位，并且使得所述输出子电路将第一电平的第二时钟信号输出至所述输出端；
    在所述复位阶段，通过所述第一时钟信号端提供第一电平的所述第一时钟信号，通过所述输入信号端提供第二电平的所述输入信号，通过所述第二时钟信号端提供第二电平的所述第二时钟信号，以使得所述复位控制子电路将所述下拉节点的电位控制为第一电平，并且使得复位子电路复位所述上拉节点和所述输出端的电位至所述电平信号；以及
    在所述保持阶段，通过所述复位控制子电路保持所述下拉节点在所述复位阶段的电位，并且通过所述复位子电路保持所述上拉节点和所述输出端在所述复位阶段的电位。
  11. 一种栅极驱动电路，包括多个权利要求1-7任一项的所述移位寄存器，所述多个移位寄存器级联耦接。
  12. 根据权利要求11所述的栅极驱动电路，其中，前一级所述移位寄存器的输出端与本级所述移位寄存器的所述输入信号端耦接。
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114067712B (zh) * 2020-07-31 2023-09-15 京东方科技集团股份有限公司 栅极驱动电路及显示面板
CN114613417A (zh) * 2020-12-09 2022-06-10 京东方科技集团股份有限公司 第一移位寄存器及其驱动方法、栅极驱动电路、显示装置
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090167668A1 (en) * 2007-12-31 2009-07-02 Hong Jae Kim Shift Register
CN104575396A (zh) * 2015-02-05 2015-04-29 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极扫描电路
CN104809985A (zh) * 2015-05-15 2015-07-29 京东方科技集团股份有限公司 一种移位寄存器单元及其驱动方法、栅极驱动电路
CN105931595A (zh) * 2016-07-13 2016-09-07 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
CN107452318A (zh) * 2017-09-20 2017-12-08 京东方科技集团股份有限公司 复位控制模块、其驱动方法及移位寄存器单元、显示装置
CN107507553A (zh) * 2017-09-25 2017-12-22 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、阵列基板和显示装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100281336B1 (ko) * 1998-10-21 2001-03-02 구본준 쉬프트 레지스터 회로
KR101002331B1 (ko) * 2004-09-07 2010-12-17 엘지디스플레이 주식회사 액정표시장치
CN102682689B (zh) * 2012-04-13 2014-11-26 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路及显示装置
CN102831860B (zh) * 2012-09-05 2014-10-15 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动器及显示装置
CN103165190A (zh) * 2013-02-01 2013-06-19 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器、阵列基板和显示装置
CN104867472B (zh) * 2015-06-15 2017-10-17 合肥京东方光电科技有限公司 一种移位寄存器单元、栅极驱动电路和显示装置
CN105609072B (zh) * 2016-01-07 2018-03-27 武汉华星光电技术有限公司 栅极驱动电路和使用栅极驱动电路的液晶显示器
CN105448269A (zh) * 2016-01-12 2016-03-30 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及显示装置
CN105810251A (zh) 2016-04-08 2016-07-27 京东方科技集团股份有限公司 移位寄存器、显示基板和显示装置
CN106448596B (zh) * 2016-10-31 2019-03-15 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090167668A1 (en) * 2007-12-31 2009-07-02 Hong Jae Kim Shift Register
CN104575396A (zh) * 2015-02-05 2015-04-29 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极扫描电路
CN104809985A (zh) * 2015-05-15 2015-07-29 京东方科技集团股份有限公司 一种移位寄存器单元及其驱动方法、栅极驱动电路
CN105931595A (zh) * 2016-07-13 2016-09-07 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
CN107452318A (zh) * 2017-09-20 2017-12-08 京东方科技集团股份有限公司 复位控制模块、其驱动方法及移位寄存器单元、显示装置
CN107507553A (zh) * 2017-09-25 2017-12-22 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、阵列基板和显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3742424A4 *

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