WO2017012305A1 - 移位寄存器单元、栅极驱动电路和显示装置 - Google Patents

移位寄存器单元、栅极驱动电路和显示装置 Download PDF

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WO2017012305A1
WO2017012305A1 PCT/CN2016/070799 CN2016070799W WO2017012305A1 WO 2017012305 A1 WO2017012305 A1 WO 2017012305A1 CN 2016070799 W CN2016070799 W CN 2016070799W WO 2017012305 A1 WO2017012305 A1 WO 2017012305A1
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node
module
transistor
shift register
output
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PCT/CN2016/070799
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English (en)
French (fr)
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冯思林
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Priority to US15/107,846 priority Critical patent/US20170193945A1/en
Publication of WO2017012305A1 publication Critical patent/WO2017012305A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register unit, a gate drive circuit including the shift register unit, and a display device including the gate drive circuit.
  • each pixel has a thin film transistor (TFT) whose gate is connected to a horizontal scanning line, the drain is connected to a vertical data line, and the source is connected to a pixel electrode.
  • TFT thin film transistor
  • an external driving chip is used to drive pixels on the display panel to display a picture, but in order to reduce the number of components and reduce the manufacturing cost, a technique of directly manufacturing a driving circuit structure on a display panel, such as an array substrate row driving technology (GOA), has been employed.
  • GOA array substrate row driving technology
  • a gate driving circuit is directly fabricated on an array substrate instead of an external driving chip. Since the gate driving circuit can be formed directly around the panel, the integration of the TFT-LCD panel is improved, the process steps are reduced, and the manufacturing cost is reduced.
  • the shift register unit 100 includes a set module 110 , a pull down module 120 , a pull down control module 130 , a reset module 140 , and an output module 150 .
  • the operation of the GOA circuit will be briefly described below with reference to FIG.
  • the thin film transistor M1' in the module 110 is set.
  • the pull-up node PU is at a high potential, so the thin film transistor M6' in the pull-down control module 130 and the thin film transistor M3' in the output module 150 are both in an on state, and the input signal is passed through the pull-up node PU.
  • the capacitor C1' in the input module 150 is precharged.
  • a low level signal is applied to the input terminal INPUT and the second control signal terminal CLK2, and a high level signal is applied to the first control signal terminal CLK1, resulting in the thin film transistor M1' and the pull-down control module 130 in the setting module 110.
  • the thin film transistor M5' is in an off state, and the pull-up node PU remains At a high potential, the thin film transistor M3' in the output module 150 is still in an on state, and a stable high level signal will be outputted at the output terminal OUTPUT.
  • a low level signal is applied to the input terminal INPUT and the first control signal terminal CLK1, and a high level signal is applied to the second control signal terminal CLK2 and the reset signal terminal RESET.
  • the thin film transistor M2 in the reset module 140 is reset.
  • the thin film transistor M4' in the pull-down module 120 is in an on state, the capacitor C1 is discharged through the output terminal OUTPUT and the thin film transistor M4', and the pull-up node PU and the output terminal OUTPUT are at a low potential.
  • a low level signal is applied to the input terminal INPUT, the second control signal terminal CLK2, and the reset signal terminal RESET, and a high level signal is applied to the first control signal terminal CLK1, causing the pull-down node PD to be at a low potential, so that the thin film transistor M2' and M4' are in an off state.
  • the high potential of the pull-down node PD causes the thin film transistors M8' and M9' to be turned on.
  • the thin film transistors M2' and M4' are now in an idle state; likewise, when the reset signal terminal RESET is at a high potential, the thin film transistors M2' and M4' provide a discharge path to the capacitor C1 while the film Transistors M8' and M9' are in an idle state. It can be seen that the utilization efficiency of the thin film transistor in the above circuit is not high, which causes waste of resources and increases the area of the GOA circuit.
  • the present disclosure provides a shift register unit, a gate drive circuit, and a display device having the advantage of reducing the area of the GOA circuit without changing the original operation mode and function of the shift register unit.
  • a shift register unit including a set module, a pull-down module, a pull-down control module, a reset module, and an output module
  • the output module includes a coupling between a first node and an output terminal a capacitor, the set module coupled to the first node to charge the capacitor in response to a set signal coupled to the first node and an output to provide a discharge path, the pull down control a module and a reset module coupled to the controlled end of the pull-down module via a second node to control a level state of the first node and the output by the pull-down module,
  • the purpose of reducing the footprint of the gate drive circuit is achieved, which is a narrow-border liquid crystal display.
  • the design is convenient.
  • the working principle and function of the shift register unit remain unchanged, no adaptation to other circuits is required, thereby greatly reducing development and manufacturing costs.
  • the reset module includes a transistor disposed between the second node and a reset signal terminal as a one-way switch to isolate the second node The effect of the level signal on the reset signal terminal.
  • the setting of the one-way switch can effectively eliminate abnormal bright spots on the display.
  • the set module includes a first transistor having a source and a gate connected to the input signal terminal, and a drain connected to the first node,
  • the pull-down module includes a second transistor and a fourth transistor, a source of the second transistor is connected to a drain of the first transistor, and a source of the fourth transistor is connected to the output end, The drains of the two transistors and the fourth transistor are connected to the reference voltage terminal, and the gate is connected to the second node.
  • the pull-down control module includes a fifth transistor and a sixth transistor, a source and a gate of the fifth transistor are connected to a second control signal end, a drain is connected to the second node, and a source of the sixth transistor a pole connected to the second node, a drain connected to the reference voltage terminal, and a gate connected to the first node
  • the output module further includes a third transistor having a source connected to the first signal control terminal, a drain connected to the output terminal, and a gate connected to the first node.
  • the reset module includes a seventh transistor having a source and a gate connected to the reset signal terminal and a drain connected to the second node.
  • a width to length ratio of the fifth transistor is larger than a width to length ratio of the sixth transistor.
  • the shift register unit described herein can ensure the stability of the output signal at the output of the shift register unit by designing the fifth and sixth transistor aspect ratios.
  • the first to seventh transistors are thin film transistors.
  • a gate driving circuit including n cascaded shift register units as described above, the n being an integer greater than one,
  • first control signal end and the second control signal end of the n shift registers are respectively Connected together, and the output of the shift register unit is coupled to the reset signal terminal of the previous stage shift register unit and the input terminal of the next stage shift register unit to use its output signal as the first stage shift The set signal of the bit register unit and the reset signal of the shift register unit of the next stage.
  • a display device including a gate drive circuit as described above.
  • 1 is a schematic diagram of a shift register unit in a prior art GOA circuit.
  • FIG. 2 is a block diagram of a shift register unit in accordance with one embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of a circuit for implementing the shift register unit of FIG. 2.
  • FIG. 4 is a signal timing diagram of the shift register shown in FIG.
  • FIG. 5 is a schematic diagram of a gate drive circuit in accordance with an embodiment of the present disclosure.
  • Coupled should be understood to include the case where electrical energy or electrical signals are directly transmitted between two units, or the case where electrical energy or electrical signals are indirectly transmitted through one or more third units.
  • the shift register unit 200 shown in FIG. 2 includes a set module 210, a pull-down module 220, a pull-down control module 230, a reset module 240, and an output module 250.
  • Setting module 210 via the first node or The pull up node PU is coupled to the output module and is configured to provide a set signal at the first node PU for performing a set operation in response to the input signal.
  • the output module 250 includes a capacitor coupled between the first node PU and the output terminal OUTPUT, by charging the capacitor via the first node PU and discharging the capacitor through the first node PU and the output terminal OUTPUT.
  • the function of the shift register 200 is implemented.
  • the pull-down module 220 is coupled to the first node PU and the output terminal OUTPUT to provide a discharge path for the capacitor.
  • the pull-down control module 230 and the reset module 240 are coupled to the controlled end of the pull-down module 220 via the second node or pull-down node PD, so that the level state at the first node PU and the output terminal OUTPUT can be controlled by means of the pull-down module.
  • the shift register unit 200 shown in FIG. 3 includes a set module 210, a pull-down module 220, a pull-down control module 230, a reset module 240, and an output module 250.
  • the structure of each module will be further described below.
  • the output module 250 includes a third transistor M3 and a capacitor C1.
  • the source of the third transistor M3 is connected to the first signal control terminal CLK1, and the drain and the gate are connected to both ends of the capacitor C1 (ie, the output terminal).
  • OUTPUT is connected to the first node PU).
  • the setting module 210 includes a first transistor M1 having a source and a gate connected to the input terminal INPUT and a drain connected to the first node PU, so that the input signal can be used at the first node. Apply a high or low signal.
  • the pull-down module 220 includes a second transistor M2 and a fourth transistor M4 which serve as discharge paths of the capacitor C1 and are respectively connected to both ends of the capacitor C1 (that is, the first node PU and the output terminal OUTPUT).
  • the source of the second transistor M2 and the drain of the first transistor M1 in the setting module 210 are connected to the first node PU, and the source of the fourth transistor M4 is connected to the output terminal OUTPUT;
  • the drains of the two transistors M2 and the fourth transistor M4 are connected to the reference voltage terminal VGL, and the gates are connected to the second node PD.
  • the gates of the second transistor M2 and the fourth transistor M4 can be regarded as the controlled ends of the pull-down module 210.
  • the pull-down control module 230 includes a fifth transistor M5 and a sixth transistor M6, wherein the source and the gate of the fifth transistor M5 are opposite to the second control signal terminal CLK2. Connected, the drain is connected to the second node PD, the source of the sixth transistor M6 is also connected to the second node PD, the drain is connected to the reference voltage terminal VGL, and the gate is connected to the first node PU.
  • the reset module 240 provides a reset signal to the controlled end of the pull-down module 220 via the second node PD.
  • the reset module 240 includes a seventh transistor M7 whose source and gate are connected to the reset signal terminal RESET, and the drain is connected to the second node PD, thereby forming a second node PD and a reset signal. A single-way switch between the ends.
  • the reset signal terminal RESET is directly connected to the second node PD
  • the reset signal terminal RESET and the next-stage shift register unit are When the output terminal OUTPUT is connected, due to the high potential of the second node PD, a line of abnormal bright spots will appear on the display screen.
  • the above-mentioned one-way switch setting can effectively isolate the influence of the potential state of the second node on the reset signal end, thereby eliminating abnormal bright spots.
  • the transistor M7 when the transistor M7 is connected between the reset signal terminal REST and the second node PD in the manner shown in FIG. 3, the transistor M7 enters an on state only when a high level signal is applied to the reset signal terminal RESET. Therefore, the high potential of the second node PD does not affect the reset signal terminal RESET.
  • the transistors M1-M7 are thin film transistors, and may be N-channel transistors or P-channel transistors.
  • FIG. 4 is a signal timing diagram of the shift register shown in FIG. The operation of the shift register unit according to this embodiment will be described below with reference to FIG.
  • a complementary square wave signal having a duty ratio of 50% is applied to the first clock input terminal CLK1 and the second clock input terminal CLK2, and the durations of the high level and the low level correspond to one clock signal interval.
  • the operation of the shift register unit during each interval in one frame period is described below.
  • a low level signal is applied to the input terminal INPUT, the first clock input terminal CLK1, and the reset signal terminal RESET, and the second clock input terminal CLK2 is applied with a high level.
  • Level signal is applied.
  • the transistors M1, M3, M6, and M7 are in an off state, and the transistor M5 is in an on state, such that the first node PU and the output terminal OUTPUT are at a low potential, and the second node PD is at a high potential.
  • the high potential of the second node PD causes the transistors M2 and M4 to be in an on state, thereby providing a discharge path for the first node PU and the output terminal OUTPUT to eliminate noise at the first node PU and the output terminal OUTPUT.
  • the larger size transistor M3 will make the parasitic capacitance between the gate and the drain non-negligible; in addition, when the first node PU is low, the first control signal When the terminal CLK1 is at a high potential, noise is also induced at the first node PU. Therefore, the noise canceling operation during the first clock signal interval is beneficial, especially for the above case.
  • the second clock signal interval T2 is entered.
  • a high level signal is applied to the first clock input terminal CLK1
  • a low level signal is applied to the input terminal INPUT, the second clock input terminal CLK2, and the reset signal terminal RESET.
  • the transistors M1, M5 are in an off state
  • the first node PU, the second node PD, and the output terminal OUTPUT are both at a low potential, and thus the transistors M2, M3, M4, and M7 are all in an off state.
  • a high level signal is applied as a set signal on the input terminal INPUT, and a low level signal is applied to the first clock input terminal CLK1 and the reset signal terminal RESET and the second clock input terminal CLK2 is applied.
  • High level signal is applied.
  • the transistor M1 is placed in an on state, and the first node PU is pulled up to a high potential to charge the capacitor C1.
  • transistors M3 and M6 are both in an on state, so that the second node PD remains at a low potential, and transistors M2 and M4 are still in an off state.
  • the output terminal OUTPUT is still in a low state.
  • a high level signal is applied to the first clock input terminal CLK1, and a low level signal is applied to the input terminal INPUT, the second clock input terminal CLK2, and the reset signal terminal RESET.
  • This causes transistors M1 and M5 to be in an off state and transistor M3 to be in an on state. Since the second node PD remains at a low potential, the transistor M2 is still in an off state, so that the high potential of the first node PU is maintained, while a high level signal is applied to the first clock input terminal CLK1 and the transistor M3 is turned on. State, thereby outputting a high level signal at the output terminal OUTPUT.
  • the resistance of the transistor M5 can be made much larger than the resistance of the transistor M6 by designing the aspect ratio of the transistor M5 to be larger than the aspect ratio of the transistor M6.
  • the above design ensures that the second node PD remains low during the fourth clock signal interval, thereby causing transistors M2 and M4 to be in an off state to ensure a stable high level signal is output at the output terminal OUTPUT.
  • the reset signal terminal RESET applies a high level signal as a reset signal
  • the second clock input terminal CLK2 also applies a high level signal and the input terminal INPUT and the first clock input terminal CLK1 are applied low.
  • Level signal Thereby, the transistors M1 and M3 are in an off state and the transistors M5 and M7 are in an on state.
  • the second node PD transitions to a high potential, causing the transistors M2 and M4 to enter a conducting state, thereby providing a discharge channel for the capacitor C1 and the output terminal OUTPUT, respectively, resulting in the first node PU and The output OUTPUT transitions to a low potential.
  • the low potential first node PU causes the transistor M6 to be in an off state, ensuring that the second node PD remains at a high potential.
  • a high level signal is applied to the first clock input terminal CLK1, and a low level signal is applied to the input terminal INPUT, the second clock input terminal CLK2, and the reset signal terminal RESET.
  • the first node PU and the second node PD are at a low potential, causing the transistors M2, M3, M4, and M6 to enter an off state.
  • the input terminal INPUT, the first clock input terminal CLK1, the second clock input terminal CLK2, and the reset signal terminal RESET will alternately repeat the level states during the 5th and 6th clock signal intervals until the next frame signal appears.
  • FIG. 5 is a schematic diagram of a gate drive circuit in accordance with an embodiment of the present disclosure.
  • the gate drive circuit shown in FIG. 5 includes a plurality of cascaded shift register cells, wherein each of the shift register cells can be a shift register unit according to FIGS. 1 through 4 or an equivalent variation thereof.
  • the n shift registers are cascaded in such a manner that the first control signal terminal CLK1 of each shift register is connected to the first control signal line, and the second control signal terminal CLK2 is connected to the second control signal.
  • the line, the VGL terminal is connected to the VGL line, and for a shift register unit, the output terminal OUTPUT is coupled with the reset signal terminal RESET of the previous stage shift register unit and the input terminal INPUT of the next stage shift register unit to Its output signal is used as a set signal of the previous stage shift register unit and a reset signal of the next stage shift register unit.
  • its input INPUT is connected to the set signal line to receive the set signal.

Abstract

一种移位寄存器单元(200)、包含该移位寄存器单元的栅极驱动电路和包含该栅极驱动电路的显示装置。该移位寄存器单元(200)，包括置位模块(210)、下拉模块(220)、下拉控制模块(230)、复位模块(240)和输出模块(250)，其中所述输出模块(250)包含耦合在第一节点PU与输出端OUTPUT之间的电容器C1，所述置位模块(210)耦合至所述第一节点PU以响应于置位信号而对所述电容器C1充电，所述下拉模块(220)与所述第一节点PU和输出端OUTPUT耦合以提供放电通路，所述下拉控制模块(230)和复位模块(240)经第二节点PD与所述下拉模块(220)的受控端耦合以借助所述下拉模块(220)控制所述第一节点PU和所述输出端OUTPUT的电平状态，其中在所述下拉模块(220)中仅配置两个晶体管以分别提供经所述第一节点PU和输出端OUTPUT的放电通路。

Description

移位寄存器单元、栅极驱动电路和显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种移位寄存器单元、包含该移位寄存器单元的栅极驱动电路和包含该栅极驱动电路的显示装置。
背景技术
在典型的有源矩阵液晶显示器中，每个像素具有一个薄膜晶体管(TFT)，其栅极连接至水平方向扫描线，漏极连接至垂直方向的数据线，而源极则连接至像素电极。当在水平方向的某一条扫描线上施加足够的正电压，则将使该条线上所有的TFT导通，此时该条线的像素电极将与垂直方向的数据线连接，视频信号被写入像素中，通过控制液晶不同的透光度可以达到控制色彩的效果。
一般利用外部驱动芯片来驱动显示面板上的像素以显示画面，但为了减少元件数目和降低制造成本，目前已采用将驱动电路结构直接制作在显示面板上的技术，例如阵列基板行驱动技术(GOA)的技术。在GOA技术中，栅极驱动电路被直接制作在阵列基板上来代替外部驱动芯片。由于栅极驱动电路可直接形成于面板周围，因此提高了TFT-LCD面板的集成度，减少了工艺步骤，并且降低了制造成本。
图1为现有技术GOA电路中的一个移位寄存器单元的示意图。如图1所示，该移位寄存器单元100包括置位模块110、下拉模块120、下拉控制模块130、复位模块140和输出模块150。以下结合图1简要描述该GOA电路的工作原理。
当输入端INPUT上施加高电平信号并且第一控制信号输入端CLK1和第二控制信号输入端CLK2上分别施加低电平信号和高电平信号时，置位模块110中的薄膜晶体管M1′处于导通状态，使得上拉节点PU处于高电位，因而下拉控制模块130中的薄膜晶体管M6′和输出模块150中的薄膜晶体管M3′均处于导通状态，此时输入信号经上拉节点PU对输入模块150中的电容器C1′进行预充电。随后，输入端INPUT和第二控制信号端CLK2上施加低电平信号而第一控制信号端CLK1上施加高电平信号，导致置位模块110中的薄膜晶体管M1′和下拉控制模块130中的薄膜晶体管M5′处于关断状态，上拉节点PU处仍然保持 高电位，输出模块150中的薄膜晶体管M3′仍然处于导通状态，此时输出端OUTPUT上将输出稳定的高电平信号。接着，在输入端INPUT和第一控制信号端CLK1上施加低电平信号，并且在第二控制信号端CLK2和复位信号端RESET上施加高电平信号，此时复位模块140中的薄膜晶体管M2′和下拉模块120中的薄膜晶体管M4′处于导通状态，电容器C1经输出端OUTPUT和薄膜晶体管M4′放电，上拉节点PU和输出端OUTPUT处于低电位。最后，在输入端INPUT、第二控制信号端CLK2和复位信号端RESET上施加低电平信号并且在第一控制信号端CLK1上施加高电平信号，导致下拉节点PD处于低电位，使得薄膜晶体管M2′和M4′处于关断状态。
在上述移位寄存器单元中，当输入端INPUT和第一控制信号端CLK1为低电位并且第二控制信号端CLK2为高电位时，下拉节点PD的高电位使得薄膜晶体管M8′和M9′导通以提供电容器C1的放电通道，但是薄膜晶体管M2′和M4′此时却处于闲置状态；同样，当复位信号端RESET为高电位时，薄膜晶体管M2′和M4′向电容器C1提供放电通道而薄膜晶体管M8′和M9′处于闲置状态。可见，在上述电路中薄膜晶体管的利用效率不高，这既造成资源浪费，也增加了GOA电路的面积。
发明内容
本公开提供一种移位寄存器单元、栅极驱动电路和显示装置，其具有在不改变移位寄存器单元原有工作方式和功能的前提下减少GOA电路面积的优点。
根据本公开的一方面，提供一种移位寄存器单元，包括置位模块、下拉模块、下拉控制模块、复位模块和输出模块，其中所述输出模块包含耦合在第一节点与输出端之间的电容器，所述置位模块耦合至所述第一节点以响应于置位信号而对所述电容器充电，所述下拉模块与所述第一节点和输出端耦合以提供放电通路，所述下拉控制模块和复位模块经第二节点与所述下拉模块的受控端耦合以借助所述下拉模块控制所述第一节点和所述输出端的电平状态，
其中，在所述下拉模块中仅配置两个晶体管以分别提供经所述第一节点和输出端的放电通路。
在上述移位寄存器单元中，通过减少用于放电通路的晶体管的数量，达到了缩小栅极驱动电路占用面积的目的，为窄边框液晶显示器 的设计提供了便利。此外，由于移位寄存器单元的工作原理和功能仍然保持不变，因此无需对其它电路作适应性的改动，从而大大降低了开发和制造成本。
根据本公开的实施例，在上述移位寄存器单元中，所述复位模块包含一个设置在所述第二节点与复位信号端之间的晶体管作为单向导通开关，以隔绝所述第二节点处的电平信号对所述复位信号端的影响。在这里所述的移位寄存器单元中，单向导通开关的设置可以有效消除显示屏上出现异常亮点。
根据本公开的实施例，在上述移位寄存器单元中，所述置位模块包括第一晶体管，其源极和栅极与输入信号端相连，漏极与所述第一节点相连，
所述下拉模块包括第二晶体管和第四晶体管，所述第二晶体管的源极与所述第一晶体管的漏极相连，所述第四晶体管的源极与所述输出端相连，所述第二晶体管和第四晶体管的漏极共接至基准电压端，栅极共接至所述第二节点，
所述下拉控制模块包括第五晶体管和第六晶体管，所述第五晶体管的源极和栅极与第二控制信号端相连，漏极与所述第二节点相连，所述第六晶体管的源极与所述第二节点相连，漏极连接至基准电压端，栅极与所述第一节点相连，
所述输出模块还包括第三晶体管，其源极与第一信号控制端相连，漏极与所述输出端相连，栅极与所述第一节点相连，
所述复位模块包含第七晶体管，其源极和栅极与复位信号端相连，漏极与所述第二节点相连。
根据本公开的实施例，在上述移位寄存器单元中，所述第五晶体管的宽长比大于所述第六晶体管的宽长比。在这里所述的移位寄存器单元，通过设计第五和第六晶体管宽长比，能够确保在移位寄存器单元的输出端上输出信号的稳定性。
根据本公开的实施例，在上述移位寄存器单元中，所述第一～第七晶体管为薄膜晶体管。
根据本公开的另一方面，提供了一种栅极驱动电路，其包括如上所述的n个级联的移位寄存器单元，所述n为大于1的整数，
其中，n个移位寄存器的第一控制信号端和第二控制信号端分别共 接在一起，并且所述移位寄存器单元的输出端与前一级移位寄存器单元的复位信号端和下一级移位寄存器单元的输入端耦合，以将其输出信号用作前一级移位寄存器单元的置位信号和下一级移位寄存器单元的复位信号。
根据本公开的另一方面，提供了一种显示装置，包括如上所述的栅极驱动电路。
附图说明
本实用新型的上述和/或其它方面和优点将通过以下结合附图的各个方面的描述变得更加清晰和更容易理解，附图中相同或相似的单元采用相同的标号表示，附图包括：
图1为现有技术GOA电路中的一个移位寄存器单元的示意图。
图2为按照本公开一个实施例的移位寄存器单元的框图。
图3为一种用于实施图2所示移位寄存器单元的电路的示意图。
图4为图3所示移位寄存器的信号时序图。
图5为按照本公开一个实施例的栅极驱动电路的示意图。
具体实施方式
下面参照其中图示了本公开示意性实施例的附图更为全面地说明本公开。但本公开可以按不同形式来实现，而不应解读为仅限于本文给出的各实施例。给出的上述各实施例旨在使本文的披露全面完整，以将本公开的保护范围更为全面地传达给本领域技术人员。
在本说明书中，“耦合”应当理解为包括在两个单元之间直接传送电能量或电信号的情形，或者经过一个或多个第三单元间接传送电能量或电信号的情形。
诸如“包含”和“包括”之类的用语表示除了具有在说明书和权利要求书中有直接和明确表述的单元和步骤以外，本公开的技术方案也不排除具有未被直接或明确表述的其它单元和步骤的情形。
诸如“第一”和“第二”之类的用语并不表示单元在时间、空间、大小等方面的顺序而仅仅是作区分各单元之用。
以下借助附图描述实现本公开的实施例。
图2为按照本公开一个实施例的移位寄存器单元的框图。图2所示的移位寄存器单元200包括置位模块210、下拉模块220、下拉控制模块230、复位模块240和输出模块250。置位模块210经第一节点或 上拉节点PU与输出模块耦合，其被配置为响应于输入信号而在第一节点PU处提供用于执行置位操作的置位信号。在本实施例中，输出模块250包含耦合在第一节点PU与输出端OUTPUT之间的电容器，通过经第一节点PU对电容器的充电以及经第一节点PU和输出端OUTPUT对电容器的放电来实现移位寄存器200的功能。下拉模块220与第一节点PU和输出端OUTPUT耦合，从而为上述电容器提供放电通路。下拉控制模块230和复位模块240则经第二节点或下拉节点PD与下拉模块220的受控端耦合，从而能够借助下拉模块来控制第一节点PU和输出端OUTPUT处的电平状态。
与图1所示的现有技术的移位寄存器单元不同，在本实施例中，仅在下拉模块220中为电容器经配置两个分别与第一节点和输出端耦合的晶体管作为电容器放电通路，由此减少了所用晶体管的数量。
图3为一种用于实施图2所示移位寄存器单元的电路的示意图。图3所示的移位寄存器单元200包括置位模块210、下拉模块220、下拉控制模块230、复位模块240和输出模块250，以下对每个模块的结构作进一步的描述。
参见图3，输出模块250包括第三晶体管M3和电容器C1，第三晶体管M3的源极与第一信号控制端CLK1相连，漏极和栅极连接至电容器C1的两端(也即与输出端OUTPUT和第一节点PU相连)。
如图3所示，置位模块210包括第一晶体管M1，该晶体管的源极和栅极都与输入端INPUT相连，漏极与第一节点PU相连，因此借助输入信号能够在第一节点处施加高电平或低电平信号。
如图3所示，下拉模块220包括第二晶体管M2和第四晶体管M4，它们作为电容器C1的放电通路而分别与电容器C1的两端(也即第一节点PU和输出端OUTPUT相连)。具体而言，第二晶体管M2的源极与置位模块210中的第一晶体管M1的漏极共接于第一节点PU，第四晶体管M4的源极则与输出端OUTPUT相连；此外，第二晶体管M2和第四晶体管M4的漏极共接至基准电压端VGL，栅极共接至第二节点PD。在本实施例中，第二晶体管M2和第四晶体管M4的栅极可以被视为下拉模块210的受控端。
参见图3，下拉控制模块230包括第五晶体管M5和第六晶体管M6，其中，第五晶体管M5的源极和栅极与第二控制信号端CLK2相 连，漏极与第二节点PD相连，第六晶体管M6的源极也与第二节点PD相连，漏极连接至基准电压端VGL，栅极与第一节点PU相连。
复位模块240经第二节点PD向下拉模块220的受控端提供复位信号。优选地，在本实施例中，复位模块240包含第七晶体管M7，其源极和栅极与复位信号端RESET相连，漏极与第二节点PD相连，从而构成在第二节点PD与复位信号端之间的单向导通开关。
需要指出的是，在包含多个级联的移位寄存器单元的栅极驱动电路中，如果复位信号端RESET与第二节点PD直接相连，则当复位信号端RESET与下一级移位寄存器单元的输出端OUTPUT相连时，由于第二节点PD的高电位的影响，将在显示屏上出现一行异常亮点。上述单向导通开关的设置能够有效隔绝第二节点的电位状态对复位信号端的影响，从而消除异常亮点。具体而言，当晶体管M7以图3所示方式连接在复位信号端REST与第二节点PD之间时，仅在复位信号端RESET上施加高电平信号时，晶体管M7才进入导通状态，因此第二节点PD的高电位不会对复位信号端RESET产生影响。
在本实施例中，晶体管M1-M7为薄膜晶体管，并且可以是N型沟道晶体管，也可以是P型沟道晶体管。
图4为图3所示移位寄存器的信号时序图。以下借助图4来描述按照本实施例的移位寄存器单元的工作原理。
参见图4，在第一时钟输入端CLK1和第二时钟输入端CLK2上施加占空比为50％的互补方波信号，并且高电平和低电平的持续时间对应于一个时钟信号间隔。以下描述一个帧周期内，移位寄存器单元在各个间隔期间的工作状态。
在图4所示时序图的第1个时钟信号间隔T1，输入端INPUT、第一时钟输入端CLK1和复位信号端RESET上均施加低电平信号，而第二时钟输入端CLK2上均施加高电平信号。在该阶段，晶体管M1、M3、M6和M7处于关断状态，而晶体管M5处于导通状态，使得第一节点PU和输出端OUTPUT为低电位，第二节点PD为高电位。第二节点PD的高电位使得晶体管M2和M4处于导通状态，从而为第一节点PU和输出端OUTPUT提供放电通路以消除第一节点PU和输出端OUTPUT处的噪声。较大尺寸的晶体管M3将使得栅极和漏极之间的寄生电容变得不可忽视；此外，当第一节点PU为低电位而第一控制信 号端CLK1处为高电位时，也会在第一节点PU处诱发噪声。因此第一时钟信号间隔期间的噪声消除操作是有益的，特别是对于上述情形。
随后进入第2个时钟信号间隔T2，此时第一时钟输入端CLK1上均施加高电平信号，输入端INPUT、第二时钟输入端CLK2和复位信号端RESET上均施加低电平信号。由此使得晶体管M1、M5处于关断状态，第一节点PU、第二节点PD以及输出端OUTPUT均处于低电位，并且进而使得晶体管M2、M3、M4和M7均处于关断状态。
在第3个时钟信号间隔T3，输入端INPUT上施加高电平信号作为置位信号，并且第一时钟输入端CLK1和复位信号端RESET上施加低电平信号而第二时钟输入端CLK2上施加高电平信号。由此使得晶体管M1处于导通状态，将第一节点PU上拉至高电位以对电容器C1进行充电。与此同时，晶体管M3和M6均处于导通状态，使得第二节点PD保持低电位，晶体管M2和M4仍然处于关断状态。此时，输出端OUTPUT仍然处于低电位状态。
在第4个时钟信号间隔T4，此时第一时钟输入端CLK1上施加高电平信号，输入端INPUT、第二时钟输入端CLK2和复位信号端RESET上施加低电平信号。由此使得晶体管M1和M5处于关断状态而晶体管M3处于导通状态。由于第二节点PD保持低电位，晶体管M2仍然处于关断状态，使得第一节点PU的高电位得以保持，与此同时，第一时钟输入端CLK1上施加高电平信号并且晶体管M3处于导通状态，由此在输出端OUTPUT输出高电平信号。
优选地，可以通过将晶体管M5的宽长比设计为大于晶体管M6的宽长比，使得晶体管M5的电阻远大于晶体管M6的电阻。上述设计确保第二节点PD在第4个时钟信号间隔内保持低电位，从而使晶体管M2和M4处于关断状态以保证在输出端OUTPUT上输出稳定的高电平信号。
在第5个时钟信号间隔T5，复位信号端RESET上施加高电平信号作为复位信号，并且第二时钟输入端CLK2也施加高电平信号而输入端INPUT和第一时钟输入端CLK1上施加低电平信号。由此使得晶体管M1和M3处于关断状态而晶体管M5和M7处于导通状态。此时第二节点PD转变为高电位，使晶体管M2和M4进入导通状态，从而分别为电容器C1和输出端OUTPUT提供放电通道，导致第一节点PU和 输出端OUTPUT转变为低电位。另一方面，低电位的第一节点PU使晶体管M6处于关断状态，确保了第二节点PD保持高电位。
在第6个时钟信号间隔T6，此时第一时钟输入端CLK1上施加高电平信号，输入端INPUT、第二时钟输入端CLK2和复位信号端RESET上施加低电平信号。由此使得晶体管M1、M5和M7处于关断状态。此时第一节点PU和第二节点PD处于低电位，使晶体管M2、M3、M4和M6进入关断状态。
随后，输入端INPUT、第一时钟输入端CLK1、第二时钟输入端CLK2和复位信号端RESET将不断交替重复第5和6个时钟信号间隔期间的电平状态，直到下一帧信号出现。
图5为按照本公开一个实施例的栅极驱动电路的示意图。图5所示的栅极驱动电路中包括了多个级联的移位寄存器单元，其中每个移位寄存器单元可以为根据图1至图4所述的移位寄存器单元或其等效变形。在本实施例中，n个移位寄存器按照下列方式级联：各个移位寄存器的第一控制信号端CLK1共接至第一控制信号线，第二控制信号端CLK2共接至第二控制信号线，VGL端共接至VGL线，并且对于一个移位寄存器单元，其输出端OUTPUT与上一级移位寄存器单元的复位信号端RESET和下一级移位寄存器单元的输入端INPUT耦合，以将其输出信号用作前一级移位寄存器单元的置位信号和下一级移位寄存器单元的复位信号。对于级联的第一个移位寄存器单元，其输入端INPUT与置位信号线相连以接收置位信号。
虽然已经示出并说明了各个示例性实施例，但本领域普通技术人员应当理解的是，可以对这些示例性实施例在形式和细节方面做出各种改变而不背离由所附权利要求书限定的本公开构思的精神和范围。

Claims (7)

  1. 一种移位寄存器单元，包括置位模块、下拉模块、下拉控制模块、复位模块和输出模块，其中所述输出模块包含耦合在第一节点与输出端之间的电容器，所述置位模块耦合至所述第一节点以响应于置位信号而对所述电容器充电，所述下拉模块与所述第一节点和输出端耦合以提供放电通路，所述下拉控制模块和复位模块经第二节点与所述下拉模块的受控端耦合以借助所述下拉模块控制所述第一节点和所述输出端的电平状态，
    其特征在于，在所述下拉模块中仅配置两个晶体管以分别提供经所述第一节点和输出端的放电通路。
  2. 如权利要求1所述的移位寄存器单元，其中，所述复位模块包含一个设置在所述第二节点与复位信号端之间的晶体管作为单向导通开关，以隔绝所述第二节点处的电平信号对所述复位信号端的影响。
  3. 如权利要求1所述的移位寄存器单元，其中，
    所述置位模块包括第一晶体管，其源极和栅极与输入信号端相连，漏极与所述第一节点相连，
    所述下拉模块包括第二晶体管和第四晶体管，所述第二晶体管的源极与所述第一晶体管的漏极相连，所述第四晶体管的源极与所述输出端相连，所述第二晶体管和第四晶体管的漏极共接至基准电压端，栅极共接至所述第二节点，
    所述下拉控制模块包括第五晶体管和第六晶体管，所述第五晶体管的源极和栅极与第二控制信号端相连，漏极与所述第二节点相连，所述第六晶体管的源极与所述第二节点相连，漏极连接至基准电压端，栅极与所述第一节点相连，
    所述输出模块还包括第三晶体管，其源极与第一信号控制端相连，漏极与所述输出端相连，栅极与所述第一节点相连，
    所述复位模块包含第七晶体管，其源极和栅极与复位信号端相连，漏极与所述第二节点相连。
  4. 如权利要求3所述的移位寄存器单元，其中，所述第五晶体管的宽长比大于所述第六晶体管的宽长比。
  5. 如权利要求1-4中任一项所述的移位寄存器单元，其中，所述 第一～第七晶体管为薄膜晶体管。
  6. 一种栅极驱动电路，包括n个级联的如权利要求1-5中任一项所述的移位寄存器单元，所述n为大于1的整数，
    其中，n个移位寄存器的第一控制信号端和第二控制信号端分别共接在一起，并且所述移位寄存器单元的输出端与前一级移位寄存器单元的复位信号端和下一级移位寄存器单元的输入端耦合，以将其输出信号用作前一级移位寄存器单元的置位信号和下一级移位寄存器单元的复位信号。
  7. 一种显示装置，包括如权利要求6所述的栅极驱动电路。
PCT/CN2016/070799 2015-07-20 2016-01-13 移位寄存器单元、栅极驱动电路和显示装置 WO2017012305A1 (zh)

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