WO2020010852A1 - 移位寄存器单元、驱动方法、栅极驱动电路和显示装置 - Google Patents

移位寄存器单元、驱动方法、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2020010852A1
WO2020010852A1 PCT/CN2019/076432 CN2019076432W WO2020010852A1 WO 2020010852 A1 WO2020010852 A1 WO 2020010852A1 CN 2019076432 W CN2019076432 W CN 2019076432W WO 2020010852 A1 WO2020010852 A1 WO 2020010852A1
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Prior art keywords
pull
node
terminal
gate
control
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PCT/CN2019/076432
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English (en)
French (fr)
Inventor
苏秋杰
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US16/612,998 priority Critical patent/US11221710B2/en
Publication of WO2020010852A1 publication Critical patent/WO2020010852A1/zh
Priority to US17/454,944 priority patent/US11481067B2/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04166—Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2354/00—Aspects of interface with display user

Definitions

  • the present disclosure relates to the technical field of display driving, and in particular, to a shift register unit, a driving method, a gate driving circuit, and a display device.
  • the touch time period lasts for a long time (on the order of milliseconds).
  • the GOA (Gate On Array) line 1 after each touch time period is set in the array.
  • the potential of the pull-up node PU in the cell on the substrate will cause a leakage phenomenon during the touch time period, so that the voltage of the pull-up node PU will decrease, which will cause the gate drive of the row of GOA units.
  • the voltage output from the signal output terminal drops, and even the corresponding row gate lines cannot be turned on, which affects the pixel charging.
  • a main object of the present disclosure is to provide a shift register unit, a driving method, a gate driving circuit, and a display device.
  • the present disclosure provides a shift register unit including a first pull-up node control circuit, a second pull-up node control circuit, a pull-down node control circuit, an output pull-up circuit, and an output pull-down circuit, wherein:
  • the first pull-up node control circuit is respectively connected to the first pull-up node, the first voltage terminal, the input terminal, the reset terminal, the pull-down node, and the second voltage terminal, and is used for an input connected at the input terminal.
  • the first pull-up node Under the control of the signal, the first pull-up node is controlled to be electrically connected to the second voltage terminal, and is used to control all the signals under the control of the reset signal output from the reset terminal and / or the voltage signal of the pull-down node.
  • the first pull-up node is electrically connected to the first voltage terminal;
  • the second pull-up node control circuit is respectively connected to the second pull-up node, the first voltage terminal, the input terminal, the reset terminal, the pull-down node, and the second voltage terminal, and is used for Under the control of the input signal, control the second pull-up node to be electrically connected to the input terminal, and under the control of the reset signal, control the second pull-up node to be electrically connected to the first voltage terminal ;
  • the pull-down node control circuit is respectively connected to the pull-down node, the second pull-up node, the second voltage terminal, and the third voltage terminal, and is configured to be controlled by a voltage signal of the second pull-up node. Controlling the potential of the pull-down node;
  • the output pull-up circuit is respectively connected to the first pull-up node, the clock signal terminal, and the gate drive signal output terminal, and is used to control the gate under the control of the voltage signal of the first pull-up node.
  • the driving signal output terminal is electrically connected with the clock signal terminal;
  • the output pull-down circuit is respectively connected to the pull-down node, the third voltage terminal, and the gate driving signal output terminal, and is used to control the gate driving signal under the control of the voltage signal of the pull-down node.
  • the output terminal is electrically connected to the third voltage terminal.
  • the first pull-up node control circuit includes:
  • a first transistor having a gate connected to the input terminal, a first electrode connected to the second voltage terminal, and a second electrode connected to the first pull-up node;
  • a second transistor having a gate connected to the reset terminal, a first electrode connected to the first pull-up node, and a second electrode connected to the first voltage terminal;
  • the seventh transistor has a gate connected to the pull-down node, a first electrode connected to the first pull-up node, and a second electrode connected to the first voltage terminal.
  • the second pull-up node control circuit includes:
  • An eleventh transistor the gate is connected to the input terminal, the first electrode is connected to the second voltage terminal, and the second electrode is connected to the second pull-up node; and,
  • the twelfth transistor has a gate connected to the reset terminal, a first electrode connected to the second pull-up node, and a second electrode connected to the first voltage terminal.
  • the pull-down node control circuit includes:
  • the ninth transistor, the gate and the first electrode are both connected to the second voltage terminal, and the second electrode is connected to the pull-down control node;
  • An eighth transistor a gate of which is connected to the second pull-up node, a first electrode of which is connected to the pull-down control node, and a second electrode of which is connected to the third voltage terminal;
  • a fifth transistor a gate of which is connected to the pull-down control node, a first electrode of which is connected to the second voltage terminal, and a second electrode of which is connected to the pull-down node;
  • the sixth transistor has a gate connected to the second pull-up node, a first electrode connected to the pull-down node, and a second electrode connected to the third voltage terminal.
  • the output pull-up circuit includes a third transistor, a gate connected to the first pull-up node, a first pole connected to the clock signal terminal, and a second pole connected to the gate drive signal output terminal; as well as,
  • a first end of the storage capacitor is connected to the first pull-up node, and a second end is connected to the gate drive signal output end.
  • the output pull-down circuit includes a tenth transistor, a gate is connected to the pull-down node, a first pole is connected to the gate driving signal output terminal, and a second pole is connected to the third voltage terminal.
  • the shift register unit of the present disclosure further includes an output reset circuit
  • the output reset circuit is respectively connected to the reset terminal, the gate driving signal output terminal, and the third voltage terminal, and is configured to control the gate driving signal under the control of the reset signal in a reset stage.
  • the output terminal is electrically connected to the third voltage terminal.
  • the output reset circuit includes a fourth transistor, a gate connected to the reset terminal, a first electrode connected to the gate driving signal output terminal, and a second electrode connected to a third voltage terminal.
  • the present disclosure also provides a driving method of a shift register unit, which is applied to the above-mentioned shift register unit.
  • the driving method of the shift register unit includes:
  • the first pull-up node control circuit controls the first pull-up node to be electrically connected to the second voltage terminal
  • the second pull-up node control circuit controls The second pull-up node is electrically connected to the second voltage terminal.
  • the pull-down node control circuit controls the potential of the pull-down node to a first level under the control of the voltage signal of the second pull-up node, and the output pull-up circuit is at the first level.
  • the control gate driving signal output terminal is electrically connected to the clock signal terminal under the control of the voltage signal of the pull-up node;
  • the output pull-up circuit bootstraps the potential of the first pull-up node, and the output pull-up circuit controls the gate under the control of the voltage signal of the first pull-up node
  • the driving signal output terminal is electrically connected with the clock signal terminal
  • the first pull-up node control circuit controls the first pull-up node to be electrically connected to the first voltage terminal under the control of a reset signal output from the reset terminal, and the second pull-up node control circuit is at Controlling the second pull-up node to be electrically connected to the first voltage terminal under the control of the reset signal;
  • the pull-down node control circuit controls the pull-down node to be electrically connected to the second voltage terminal under the control of the voltage signal of the second pull-up node, and outputs The pull-down circuit controls the output terminal of the gate driving signal to be electrically connected to the third voltage terminal under the control of the voltage signal of the pull-down node.
  • the driving method of the shift register unit further includes: providing a reverse voltage to the first voltage terminal during the touch time period to control the first pole and the first pole included in the first pull-up node control circuit.
  • a leakage current of a transistor connected to a pull-up node is smaller than a predetermined leakage current, and a leakage current of a transistor connected to a first pole and a second pull-up node included in a second pull-up node control circuit is smaller than the predetermined leakage current.
  • the shift register unit further includes an output reset circuit; a driving method of the shift register unit includes:
  • the output reset circuit controls the output terminal of the gate driving signal to be electrically connected to a third voltage terminal under the control of the reset signal.
  • the present disclosure also provides a gate driving circuit including a plurality of stages of the above-mentioned shift register units;
  • each stage of the shift register unit is connected to the gate drive signal output terminal of the adjacent previous-stage shift register unit;
  • the reset terminal of each stage of the shift register unit is connected to the gate drive signal output terminal of the adjacent next-stage shift register unit.
  • the present disclosure also provides a display device including the above gate driving circuit.
  • the present disclosure also provides a shift register unit including a first pull-up node control circuit, a second pull-up node control circuit, a pull-down node control circuit, an output pull-up circuit, and an output pull-down circuit, wherein:
  • the first pull-up node control circuit is directly connected to a first pull-up node, a first voltage terminal, an input terminal, a reset terminal, a pull-down node, and a second voltage terminal, respectively, and is used for an input signal connected at the input terminal.
  • a first pull-up node Under the control of controlling the first pull-up node to be electrically connected to the second voltage terminal, and used for controlling the reset signal output from the reset terminal and / or the voltage signal of the pull-down node to control the
  • a first pull-up node is electrically connected to the first voltage terminal;
  • the second pull-up node control circuit is directly connected to the second pull-up node, the first voltage terminal, the input terminal, the reset terminal, the pull-down node, and the second voltage terminal, respectively, and is used for Controlling the second pull-up node to be electrically connected to the input terminal under the control of the input signal, and controlling the second pull-up node to be electrically connected to the first voltage terminal under the control of the reset signal;
  • the pull-down node control circuit is directly connected to the pull-down node, the second pull-up node, the second voltage terminal, and the third voltage terminal, respectively, and is used to control under the control of the voltage signal of the second pull-up node.
  • the output pull-up circuit is directly connected to the first pull-up node, the clock signal terminal, and the gate drive signal output terminal, respectively, and is used to control the gate under the control of the voltage signal of the first pull-up node
  • the electrode driving signal output terminal is electrically connected with the clock signal terminal;
  • the output pull-down circuit is directly connected to the pull-down node, the third voltage terminal, and the gate driving signal output terminal, respectively, for controlling the gate driving under the control of the voltage signal of the pull-down node.
  • the signal output terminal is electrically connected to the third voltage terminal.
  • the first pull-up node control circuit includes:
  • a first transistor a gate is directly connected to the input terminal, a first pole is directly connected to the second voltage terminal, and a second pole is directly connected to the first pull-up node;
  • a second transistor having a gate directly connected to the reset terminal, a first pole directly connected to the first pull-up node, and a second pole directly connected to the first voltage terminal;
  • the seventh transistor has a gate directly connected to the pull-down node, a first pole directly connected to the first pull-up node, and a second pole directly connected to the first voltage terminal.
  • the second pull-up node control circuit includes:
  • a gate is directly connected to the reset terminal, a first pole is directly connected to the second pull-up node, and a second pole is directly connected to the first voltage terminal.
  • the pull-down node control circuit includes:
  • the ninth transistor, the gate and the first pole are directly connected to the second voltage terminal, and the second pole is directly connected to the pull-down control node;
  • An eighth transistor the gate is directly connected to the second pull-up node, the first pole is directly connected to the pull-down control node, and the second pole is directly connected to the third voltage terminal;
  • a fifth transistor a gate is directly connected to the pull-down control node, a first pole is directly connected to the second voltage terminal, and a second pole is directly connected to the pull-down node;
  • the sixth transistor has a gate directly connected to the second pull-up node, a first pole directly connected to the pull-down node, and a second pole directly connected to the third voltage terminal.
  • the output pull-up circuit includes a third transistor, the gate is directly connected to the first pull-up node, the first pole is directly connected to the clock signal terminal, and the second pole is connected to the gate drive signal output terminal. Direct connection; and,
  • the first end of the storage capacitor is directly connected to the first pull-up node, and the second end is directly connected to the gate drive signal output end.
  • the output pull-down circuit includes a tenth transistor, a gate is directly connected to the pull-down node, a first pole is directly connected to the gate driving signal output terminal, and a second pole is directly connected to the third voltage terminal. connection.
  • the shift register unit further includes an output reset circuit
  • the output reset circuit is directly connected to the reset terminal, the gate driving signal output terminal, and the third voltage terminal, respectively, and is configured to control the gate driving under the control of the reset signal in a reset stage.
  • the signal output terminal is electrically connected to the third voltage terminal.
  • the output reset circuit includes a fourth transistor, a gate is directly connected to the reset terminal, a first pole is directly connected to the gate driving signal output terminal, and a second pole is directly connected to the third voltage terminal.
  • FIG. 1 is a structural diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 2 is a structural diagram of a shift register unit according to another embodiment of the present disclosure.
  • FIG. 3 is a structural diagram of a shift register unit according to another embodiment of the present disclosure.
  • FIG. 4 is a circuit diagram of a specific embodiment of a shift register unit according to the present disclosure.
  • FIG. 6 is a structural diagram of a specific embodiment of a gate driving circuit according to the present disclosure.
  • FIG. 7 is an operation timing diagram of the specific embodiment of the gate driving circuit according to the present disclosure.
  • the transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • one of the poles is referred to as a first pole, and the other pole is referred to as a second pole.
  • the first pole may be a drain
  • the second pole may be a source
  • the first pole may be a source
  • the second pole may be a drain.
  • the shift register unit includes a first pull-up node control circuit 11, a second pull-up node control circuit 12, a pull-down node control circuit 13, an output pull-up circuit 14, and an output pull-down Circuit 15, where
  • the first pull-up node control circuit 11 is respectively connected to a first pull-up node PU1, a first voltage terminal VD1, an input terminal INPUT, a reset terminal RESET, a pull-down node PD, and a second voltage terminal VD2, and is configured to be connected to the input.
  • the first pull-up node PU1 Under the control of the input signal connected to the INPUT terminal, the first pull-up node PU1 is controlled to be electrically connected to the second voltage terminal VD2, and is used for a reset signal output from the reset terminal RESET and / or the pull-down node.
  • controlling the first pull-up node PU1 Under the control of the voltage signal of the PD, controlling the first pull-up node PU1 to be electrically connected to the first voltage terminal VD1;
  • the second pull-up node control circuit 12 is connected to the second pull-up node PU2, the first voltage terminal VD1, the input terminal INPUT, the reset terminal RESET, the pull-down node PD, and the second voltage terminal VD2, respectively.
  • the first voltage terminal VD1 is electrically connected;
  • the pull-down node control circuit 13 is respectively connected to the pull-down node PD, the second pull-up node PU2, the second voltage terminal VD2, and the third voltage terminal VD3, and is configured to be connected to the second pull-up node PU2. Controlling the potential of the pull-down node PD under the control of a voltage signal;
  • the output pull-up circuit 14 is respectively connected to the first pull-up node PU1, a clock signal terminal CLK, and a gate drive signal output terminal OUTPUT, and is used to be controlled by a voltage signal of the first pull-up node PU1. Controlling the gate driving signal output terminal OUTPUT to be electrically connected to the clock signal terminal CLK;
  • the output pull-down circuit 15 is respectively connected to the pull-down node PD, the third voltage terminal VD3, and the gate driving signal output terminal OUTPUT, and is used to control all voltages under the control of the voltage signal of the pull-down node PD.
  • the gate driving signal output terminal OUTPUT is electrically connected to the third voltage terminal VD3.
  • the shift register unit includes two pull-up nodes: a first pull-up node PU1 and a second pull-up node PU2.
  • the first pull-up node PU1 controls the gate driving signal output, and the second pull-up node PU1
  • the pull node PU2 controls the potential of the pull-down node PD, which avoids a situation in which a pull-up node and a pull-down node restrict each other in the related art and it is difficult to set the width-to-length ratio of the transistor in the pull-down node control circuit 13;
  • the shift register unit described above adds a first voltage terminal VD1, so that both the first pull-up node control circuit 11 and the second pull-up node control circuit 12 are connected to the first voltage terminal VD1.
  • the voltage output from the voltage terminal VD1 reduces the leakage current of the transistor, thereby avoiding the problem of erroneous output caused by the failure to maintain the potential of the first pull-up node PU1 and the potential of the second pull-up node PU2 during the touch time period.
  • the shift register unit in the related art includes only one pull-up node, the pull-up node performs the work of controlling the gate driving signal output and controlling the potential of the pull-down node at the same time, and the potential of the pull-up node is also affected by the pull-down node Therefore, it may be difficult to set the width-to-length ratio of the transistor in the pull-down node control module.
  • the shift register unit according to the embodiment of the present disclosure is provided with two pull-up nodes, and the gate is controlled by the first pull-up node PU1.
  • the pole drives the signal output, and the potential of the pull-down node is controlled by the second pull-up node PU2 to solve the above problem.
  • the first pull-up node control circuit may include:
  • a first pull-up node controlling transistor a gate of which is connected to the input terminal, a first pole of which is connected to the second voltage terminal, and a second pole of which is connected to the first pull-up node;
  • a second pull-up node control transistor a gate of which is connected to the reset terminal, a first pole of which is connected to the first pull-up node, and a second pole of which is connected to the first voltage terminal;
  • a third pull-up node controls the transistor, a gate is connected to the pull-down node, a first pole is connected to the first pull-up node, and a second pole is connected to the first voltage terminal.
  • the second pull-up node control circuit may include:
  • a fifth pull-up node control transistor a gate of which is connected to the input terminal, a first pole of which is connected to the second voltage terminal, and a second pole of which is connected to the second pull-up node;
  • the sixth pull-up node control transistor has a gate connected to the reset terminal, a first pole connected to the second pull-up node, and a second pole connected to the first voltage terminal.
  • the second voltage terminal is a high-voltage terminal to which a high voltage VDD is input.
  • the first voltage terminal is a first low voltage terminal to which the first low voltage VSS ′ is input;
  • the first pull-up node control circuit 11 includes:
  • a first pull-up node control transistor M1 a gate of which is connected to the input terminal INPUT, a drain of which is connected to a high-voltage terminal of the input high voltage VDD, and a source of which is connected to the first pull-up node PU1;
  • the second pull-up node control transistor M2 has a gate connected to the reset terminal RESET, a drain connected to the first pull-up node PU1, and a source connected to the first low voltage terminal of the input first low voltage VSS '. Connected; and,
  • a third pull-up node control transistor M7 a gate of which is connected to the pull-down node PD, a drain of which is connected to the first pull-up node PU1, and a source of which is connected to the first low voltage VSS ';
  • the second pull-up node control circuit 12 includes:
  • a fifth pull-up node control transistor M1 ' a gate of which is connected to the input terminal INPUT, a drain of which is connected to the high voltage VDD, and a source of which is connected to the second pull-up node PU2;
  • the sixth pull-up node control transistor M2 ' has a gate connected to the reset terminal RESET, a drain connected to the second pull-up node PU2, and a source connected to the first low voltage VSS'.
  • all transistors are n-type transistors as an example, but in actual operation, the above-mentioned transistors can also be replaced with p-type transistors.
  • M1 is turned on so that PU1 is connected to VDD, and M1 ’is turned on so that PU2 is also connected to VDD;
  • M2 In the reset phase included in the display time period, under the control of the reset signal connected to RESET, M2 is turned on so that PU1 is connected to VSS ′, and M2 ’is turned on so that PU2 is also connected to VSS’;
  • VSS ' is set to a reverse voltage to control the leakage current of M2 and the leakage current of M7 to be less than the predetermined leakage current, and to control the leakage current of M2' to be less than the predetermined leakage current.
  • the pull-down node PD due to the transistor leakage current has too strong control ability on the first pull-up node PU1 and the second pull-up node PU2, which causes the potential of PU1 and PU2 to be pulled low by the PD, causing the gate A case where the pole driving circuit is completely disabled.
  • the pull-down node control circuit may include:
  • the first pull-down node controls the transistor, the gate and the first electrode are both connected to the second voltage terminal, and the second electrode is connected to the pull-down control node;
  • a second pull-down node controls the transistor, a gate is connected to the second pull-up node, a first electrode is connected to the pull-down control node, and a second electrode is connected to the third voltage terminal;
  • a third pull-down node control transistor a gate of which is connected to the pull-down control node, a first electrode of which is connected to the second voltage terminal, and a second electrode of which is connected to the pull-down node;
  • a fourth pull-down node controls the transistor, a gate is connected to the second pull-up node, a first electrode is connected to the pull-down node, and a second electrode is connected to the third voltage terminal.
  • the output pull-up circuit may include: an output pull-up transistor, a gate connected to the first pull-up node, a first pole connected to the clock signal terminal, and a second pole connected to the gate drive signal Output connections; and
  • a first end of the storage capacitor is connected to the first pull-up node, and a second end is connected to the gate drive signal output end.
  • the output pull-down circuit may include an output pull-down transistor, a gate connected to the pull-down node, a first electrode connected to the gate driving signal output terminal, and a second electrode connected to the third voltage terminal.
  • the shift register unit may further include an output reset circuit 16;
  • the output reset circuit 16 is respectively connected to the reset terminal RESET, the gate driving signal output terminal OUTPUT, and the third voltage terminal VD3, and is configured to control the reset signal under the control of the reset signal in a reset phase.
  • the gate driving signal output terminal OUTPUT is electrically connected to the third voltage terminal VD3.
  • the output reset circuit may include: an output reset transistor, a gate connected to the reset terminal, a first electrode connected to the gate driving signal output terminal, and a second electrode connected to a third voltage terminal.
  • FIG. 4 is a circuit diagram of a specific embodiment of a shift register unit according to the present disclosure.
  • the shift register unit shown in FIG. 4 is an N-th stage shift register unit included in the gate driving circuit according to the embodiment of the present disclosure. After the N-th line of the screen is displayed (that is, after the N-th stage shift register unit included in the gate driving circuit is scanned), the touch time period is entered, and after the touch time period is over, the N + th scan is continued.
  • 1 row shift register unit; the N + 1th stage shift register unit in the gate driving circuit according to the embodiment of the present disclosure is connected to the first clock signal terminal CLK1.
  • the N is a positive integer.
  • a specific embodiment of the shift register unit includes a first pull-up node control circuit 11, a second pull-up node control circuit 12, a pull-down node control circuit 13, and an output pull-up circuit 14.
  • the first pull-up node control circuit 11 includes:
  • a first pull-up node control transistor M1 a gate of which is connected to the input terminal INPUT, a drain of which is connected to a high-voltage terminal of the input high voltage VDD, and a source of which is connected to the first pull-up node PU1;
  • a second pull-up node control transistor M2 a gate of which is connected to the reset terminal RESET, a drain of which is connected to the first pull-up node PU1, and a source of which is connected to the first low voltage VSS ';
  • a third pull-up node control transistor M7 a gate of which is connected to the pull-down node PD, a drain of which is connected to the first pull-up node PU1, and a source of which is connected to the first low voltage VSS ';
  • the second pull-up node control circuit 12 includes:
  • a fifth pull-up node control transistor M1 ' a gate of which is connected to the input terminal INPUT, a drain of which is connected to the high voltage VDD, and a source of which is connected to the second pull-up node PU2;
  • a sixth pull-up node control transistor M2 ' a gate of which is connected to the reset terminal RESET, a drain of which is connected to the second pull-up node PU2, and a source of which is connected to the first low voltage VSS';
  • the pull-down node control circuit 13 includes:
  • the first pull-down node controls the transistor M9, and both the gate and the drain are connected to the high voltage VDD, and the source is connected to the pull-down control node PDCN;
  • the second pull-down node controls the transistor M8, the gate is connected to the second pull-up node PU2, the drain is connected to the pull-down control node PDCN, and the source is connected to the second low voltage VSS;
  • a third pull-down node control transistor M5 a gate of which is connected to the pull-down control node PDCN, a drain of which is connected to a high voltage VDD, and a source of which is connected to the pull-down node PD;
  • a fourth pull-down node controls the transistor M6, a gate is connected to the second pull-up node PU2, a drain is connected to the pull-down node PD, and a source is connected to the second low voltage VSS;
  • the output pull-up circuit 14 includes an output pull-up transistor M3, a gate connected to the first pull-up node PU1, a drain connected to the clock signal terminal CLK, and a source connected to the gate driving signal output terminal OUTPUT; and ,
  • the storage capacitor C has a first terminal connected to the first pull-up node PU1 and a second terminal connected to the gate driving signal output terminal OUTPUT;
  • the output pull-down circuit 15 includes an output pull-down transistor M10, a gate of which is connected to the pull-down node PD, a drain of which is connected to the gate drive signal output terminal OUTPUT, and a source of which is connected to a second low voltage VSS;
  • the output reset circuit 16 includes an output reset transistor M4, a gate connected to the reset terminal RESET, a drain connected to the stage gate driving signal output terminal OUTPUT, and a source connected to the second low voltage VSS.
  • all transistors are n-type transistors, but not limited thereto.
  • the specific embodiment of the shift register unit shown in FIG. 4 of the present disclosure uses two pull-up nodes: a first pull-up node PU1 and a second pull-up node PU2.
  • PU1 is used to control the gate of M3, and PU2 is used to
  • M6 and M8 are controlled to discharge PD and PDCN, and the potential of PD is controlled through PU2, but PD cannot control the discharge of PU2, and only discharge of PU2 can be achieved through M2 '.
  • the advantages of the shift register unit described below are as follows: The two pull-up nodes work separately.
  • GOA Gate On Array, gate drive circuits provided on the array substrate
  • VSS is always -8V. Pulling VSS 'from a low level makes VSS' 0V, which can make the gate-source voltage of M2, M7 during the touch time period.
  • the leakage current of M2, M7, and M2' are negligible, which avoids the potential of PU1 and PU2 from being touched. The time period is reduced due to a large leakage.
  • VSS and VSS ' are both -8V, and during the touch period, VSS' is 0V and VSS is -8V.
  • the specific embodiment of the shift register unit shown in FIG. 4 of the present disclosure is in the display time period during operation.
  • the INPUT input is high, the RESET output is low, and the CLK output is low.
  • the potential is low and M3 is turned on so that OUTPUT is connected to CLK and OUTPUT outputs low level;
  • INPUT inputs a low level
  • RESET outputs a low level
  • CLK outputs a high level
  • the storage capacitor C bootstraps and raises the potential of PU1, and M3 turns on so that OUTPUT is connected to CLK, and OUTPUT outputs a high level
  • INPUT is input low level
  • RESET is output high level
  • CLK is output low level
  • the power of PDCN is taken by M9. Pull up to VDD, the potential of PD is pulled up to VDD by M5, and both M4 and M10 are turned on to pull down the potential of the gate drive signal output from OUTPUT to -8V;
  • INPUT is input low level
  • RESET is output low level
  • CLK interval is output high level and low level
  • PD potential is high level
  • M10 is turned on to continuously drive the gate of OUTPUT output The potential of the signal is pulled down to -8V.
  • the shift register unit in the related art only uses one pull-up node PU and the second low voltage terminal inputting the second low voltage VSS, that is, the shift register unit in the related art does not include M1 ′, M2 ′ in FIG. 4 And the first low-voltage terminal to which the first low-voltage VSS 'is input.
  • the gate drive circuit in the related art when the input terminal of the N-th row shift register unit inputs a high level (N is a positive integer) The potential of the pull-up node in the Nth row shift register unit is pulled up, and the pull-up node is connected to the drain of M1, the drain of M2, and the drain of M7.
  • a traditional LCD Liquid Crystal Display
  • a-Si amorphous silicon
  • the leakage current of the transistor is the smallest
  • the traditional OLED (organic light-emitting diode) display uses more
  • LTPS TFTs low temperature polysilicon thin film transistors
  • the touch time period may last on the order of ms (milliseconds), and the voltage drop of the pull-up node caused by the leakage current of the transistor during the touch time period cannot be ignored.
  • the potential of the pull-down control node PDCN and the potential of the pull-down node PD can theoretically be pulled up to a high voltage.
  • the ratio of the aspect ratio of M5 to the aspect ratio of M6 is generally set to 1: A, where A is an integer greater than or equal to 2 and less than or equal to 5.
  • A is an integer greater than or equal to 2 and less than or equal to 5.
  • the PD may discharge the PU, causing the PU's potential to be low, and the opening effect of M3 is poor, affecting the gate drive signal output. Output capability.
  • the ratio is too large, the PU's ability to control the PD is too strong, which will cause the potential of the PU to be low after the completion of a row of shift register units, but due to the poor noise-reduction ability of the PD, the PU's The potential is continuously high, resulting in abnormal display.
  • the method for driving a shift register unit includes:
  • the first pull-up node control circuit controls the first pull-up node to be connected to the second voltage terminal
  • the second pull-up node control circuit controls the first
  • the two pull-up nodes are electrically connected to the second voltage terminal.
  • the pull-down node control circuit controls the potential of the pull-down node to a first level under the control of the voltage signal of the second pull-up node, and the output pull-up circuit is on the first pull-up node.
  • the control gate driving signal output terminal is electrically connected to the clock signal terminal under the control of the voltage signal of the pull node;
  • the output pull-up circuit bootstraps the potential of the first pull-up node, and the output pull-up circuit controls the gate under the control of the voltage signal of the first pull-up node
  • the driving signal output terminal is electrically connected with the clock signal terminal
  • the first pull-up node control circuit controls the first pull-up node to be connected to the first voltage terminal under the control of a reset signal output from the reset terminal, and the second pull-up node control circuit Controlling the second pull-up node to be electrically connected to the first voltage terminal under the control of the reset signal;
  • the pull-down node control circuit controls the pull-down node to be connected to the second voltage terminal under the control of the voltage signal of the second pull-up node, and outputs pull-down The circuit controls the gate driving signal output terminal to be electrically connected to the third voltage terminal under the control of the voltage signal of the pull-down node.
  • the driving method of the shift register unit controls the gate driving signal output through the first pull-up node, and controls the potential of the pull-down node through the second pull-up node, thereby avoiding one pull-up node and one Pull-down nodes restrict each other and it is difficult to set the aspect ratio of the transistors in the pull-down node control circuit.
  • the driving method of the shift register unit may further include: providing a reverse voltage to the first voltage terminal during a touch time period to control the first pull-up node control circuit including the first
  • the leakage current of the transistor connected to the first pull-up node is smaller than the predetermined leakage current
  • the leakage current of the transistor connected to the first pole and the second pull-up node included in the second pull-up node control circuit is smaller than the predetermined leakage current.
  • the driving method of the shift register unit reduces the first pole and the first pull-up included in the first pull-up node control circuit by increasing the voltage output from the first voltage terminal during the touch time period.
  • the leakage current of the transistor connected to the node and the leakage current of the transistor connected to the first pole and the second pull-up node included in the second pull-up node control circuit so as to prevent the potential of the first pull-up node and the The problem of erroneous output caused by the potential of the second pull-up node
  • the shift register unit may further include an output reset circuit; a driving method of the shift register unit includes:
  • the output reset circuit controls the output terminal of the gate driving signal to be electrically connected to a third voltage terminal under the control of the reset signal.
  • the gate driving circuit according to the embodiment of the present disclosure includes a plurality of stages of the above-mentioned shift register units;
  • each stage of the shift register unit is connected to the gate drive signal output terminal of the adjacent previous-stage shift register unit;
  • the reset terminal of each stage of the shift register unit is connected to the gate drive signal output terminal of the adjacent next-stage shift register unit.
  • FIG. 6 is a structural diagram of a specific embodiment of a gate driving circuit according to the present disclosure.
  • the specific embodiment included in the gate driving circuit according to the present disclosure includes an M-stage shift register unit, where M is a positive integer.
  • the reference numeral GOA1 is a first-stage shift register unit included in the gate driving circuit.
  • GOA1 is connected to VSS and VSS ′, and GOA1 is connected to the first clock signal terminal CLK1.
  • the reference numeral is OUT1. It is the gate driving signal output terminal of GOA1, and the input terminal INPUT1 of GOA1 is connected to the start signal STV;
  • the GOA2 is a second-stage shift register unit included in the gate driving circuit.
  • GOA2 is connected to VSS and VSS ', and GOA2 is connected to the second clock signal terminal CLK2.
  • the OUT2 is the gate driving signal output terminal of GOA2.
  • the input terminal INPUT1 of GOA2 is connected to OUT1, the reset terminal of GOA2 is labeled RESET2, and OUT2 is connected to the reset terminal RESET1 of GOA1;
  • the reference numeral GOAN-1 is the N-1th stage shift register unit included in the gate driving circuit.
  • GOAN-1 is connected to VSS and VSS ', and GOAN-1 is connected to the first clock signal terminal CLK1.
  • OUTN-1 is the gate driving signal output terminal of GOAN-1, the input terminal of GOAN-1 is labeled as INPUTN-1, and the reset terminal of GOAN-1 is labeled as RESETN-1;
  • the GOAN is the Nth stage shift register unit included in the gate driving circuit.
  • GOAN is connected to VSS and VSS ', and GOAN is connected to the second clock signal terminal CLK2.
  • the OUTN is the gate driving signal output terminal of GOAN.
  • the input labeled GOPU is the input terminal of INPUTN, and the reset terminal of GOAN is labeled RESETN, INPUTN is connected to OUTN-1, and RESETN-1 is connected to OUTN;
  • the reference numeral GOAN + 1 is the N + 1th stage shift register unit included in the gate driving circuit.
  • GOAN + 1 is connected to VSS and VSS ', and GOAN + 1 is connected to the first clock signal terminal CLK1.
  • OUTN + 1 is the gate driving signal output terminal of GOAN + 1, the input terminal of GOAN + 1 is labeled as INPUTN + 1, the reset terminal of GOAN + 1 is labeled as RESETN + 1, and INPUTN + 1 is connected to OUTN.
  • RESETN is connected to OUTN + 1;
  • the GOAM is the Mth stage shift register unit included in the gate driving circuit.
  • GOAM is connected to VSS and VSS ', and GOAM is connected to the second clock signal terminal CLK2.
  • the OUTM is the gate driving signal output terminal of GOAM.
  • the input terminal labeled GOPU is the INPUTM, and the reset terminal of GOAM is labeled RESETM;
  • N is a positive integer, N is greater than 1 and N + 1 is less than M;
  • the first clock signal output by CLK1 and the second clock signal output by CLK2 are inverted from each other, and after the N-th row display scan is completed (that is, the gate is completed by GOAN) After the pole driving scan), the touch time period LHB is entered. After the touch time period LHB ends, the N + 1 row shift register unit GOAN + 1 is continuously scanned.
  • FIG. 7 is a timing chart of the operation of the specific embodiment of the gate driving circuit as shown in FIG. 6 in the present disclosure.
  • PU1-N is the first pull-up node in GOAN
  • PU-N + 1 is the first pull-up node in GOAN + 1
  • VSS ' is the first low voltage
  • VSS is always maintained at -8V.
  • the potentials of PU1-N and PU1-N + 1 can be maintained at a high level during the touch time period, so that After the LHB is completed, GOAN + 1 can work normally and OUTN + 1 can output the gate drive signal normally.
  • the display device includes the gate driving circuit described above.
  • the display device provided in the embodiments of the present disclosure may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

提供一种移位寄存器单元、驱动方法、栅极驱动电路和显示装置。移位寄存器单元包括第一上拉节点控制电路（11）、第二上拉节点控制电路（12）、下拉节点控制电路（13）、输出上拉电路（14）和输出下拉电路（15）；第一上拉节点控制电路（11）在输入信号的控制下，控制第一上拉节点(PU1)与第二电压端(VD2)连接，在复位信号和/或下拉节点(PD)的电压信号的控制下，控制第一上拉节点(PU1)与第一电压端(VD1)连接；第二上拉节点控制电路(12)在输入信号的控制下，控制第二上拉节点与输入端(INPUT)连接，在复位信号的控制下，控制第二上拉节点(12)与第一电压端(VD1)连接；下拉节点控制电路(13)分别与下拉节点(PD)、第二上拉节点、第二电压端(VD2)和第三电压端(VD3)连接。

Description

移位寄存器单元、驱动方法、栅极驱动电路和显示装置
相关申请的交叉引用
本申请主张在2018年7月11日在中国提交的中国专利申请No.201810757914.0的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示驱动技术领域，尤其涉及一种移位寄存器单元、驱动方法、栅极驱动电路和显示装置。
背景技术
In cell(内嵌式)触摸显示装置在工作时，触控时间段持续的时间较长(毫秒量级)，在每个触控时间段后的第1行GOA(Gate On Array，设置于阵列基板上的栅极驱动)单元中的上拉节点PU的电位在所述触控时间段内会出现漏电现象，使得所述上拉节点PU的电压降低，会导致该行GOA单元的栅极驱动信号输出端输出的电压下降，甚至相应行栅线无法开启，使得像素充电受到影响。
发明内容
本公开的主要目的在于提供一种移位寄存器单元、驱动方法、栅极驱动电路和显示装置。
一方面，本公开提供了一种移位寄存器单元，包括第一上拉节点控制电路、第二上拉节点控制电路、下拉节点控制电路、输出上拉电路和输出下拉电路，其中，
所述第一上拉节点控制电路分别与所述第一上拉节点、第一电压端、输入端、复位端、下拉节点和第二电压端连接，用于在所述输入端接入的输入信号的控制下，控制所述第一上拉节点与所述第二电压端电连接，并用于在所述复位端输出的复位信号和/或所述下拉节点的电压信号的控制下，控制所述第一上拉节点与所述第一电压端电连接；
所述第二上拉节点控制电路分别与所述第二上拉节点、所述第一电压端、所述输入端、所述复位端、所述下拉节点和第二电压端连接，用于在所述输入信号的控制下，控制所述第二上拉节点与所述输入端电连接，在所述复位信号的控制下，控制所述第二上拉节点与所述第一电压端电连接；
所述下拉节点控制电路分别与所述下拉节点、所述第二上拉节点、所述第二电压端和第三电压端连接，用于在所述第二上拉节点的电压信号的控制下控制所述下拉节点的电位；
所述输出上拉电路分别与所述第一上拉节点、时钟信号端、栅极驱动信号输出端连接，用于在所述第一上拉节点的电压信号的控制下，控制所述栅极驱动信号输出端与所述时钟信号端电连接；
所述输出下拉电路分别与所述下拉节点、所述第三电压端和所述栅极驱动信号输出端连接，用于在所述下拉节点的电压信号的控制下，控制所述栅极驱动信号输出端与所述第三电压端电连接。
实施时，所述第一上拉节点控制电路包括：
第一晶体管，栅极与所述输入端连接，第一极与所述第二电压端连接，第二极与所述第一上拉节点连接；
第二晶体管，栅极与所述复位端连接，第一极与所述第一上拉节点连接，第二极与所述第一电压端连接；以及，
第七晶体管，栅极与所述下拉节点连接，第一极与所述第一上拉节点连接，第二极与所述第一电压端连接。
实施时，所述第二上拉节点控制电路包括：
第十一晶体管，栅极与所述输入端连接，第一极与所述第二电压端连接，第二极与所述第二上拉节点连接；以及，
第十二晶体管，栅极与所述复位端连接，第一极与所述第二上拉节点连接，第二极与所述第一电压端连接。
实施时，所述下拉节点控制电路包括：
第九晶体管，栅极和第一极都与第二电压端连接，第二极与下拉控制节点连接；
第八晶体管，栅极与所述第二上拉节点连接，第一极与所述下拉控制节 点连接，第二极与所述第三电压端连接；
第五晶体管，栅极与所述下拉控制节点连接，第一极与所述第二电压端连接，第二极与所述下拉节点连接；以及，
第六晶体管，栅极与所述第二上拉节点连接，第一极与所述下拉节点连接，第二极与所述第三电压端连接。
实施时，输出上拉电路包括：第三晶体管，栅极与所述第一上拉节点连接，第一极与所述时钟信号端连接，第二极与所述栅极驱动信号输出端连接；以及，
存储电容，第一端与所述第一上拉节点连接，第二端与所述栅极驱动信号输出端连接。
实施时，所述输出下拉电路包括：第十晶体管，栅极与所述下拉节点连接，第一极与所述栅极驱动信号输出端连接，第二极与所述第三电压端连接。
实施时，本公开所述的移位寄存器单元还包括输出复位电路；
所述输出复位电路分别与所述复位端、所述栅极驱动信号输出端和所述第三电压端连接，用于在复位阶段，在所述复位信号的控制下控制所述栅极驱动信号输出端与所述第三电压端电连接。
实施时，所述输出复位电路包括：第四晶体管，栅极与所述复位端连接，第一极与所述栅极驱动信号输出端连接，第二极与第三电压端连接。
另一方面，本公开还提供了一种移位寄存器单元的驱动方法，应用于上述的移位寄存器单元，所述移位寄存器单元的驱动方法包括：
在显示时间段包括的输入阶段，在输入端接入的输入信号的控制下，第一上拉节点控制电路控制第一上拉节点与第二电压端电连接，第二上拉节点控制电路控制第二上拉节点与第二电压端电连接，下拉节点控制电路在第二上拉节点的电压信号的控制下，控制下拉节点的电位为第一电平，输出上拉电路在所述第一上拉节点的电压信号的控制下控制栅极驱动信号输出端与时钟信号端电连接；
在显示时间段包括的输出阶段，输出上拉电路自举拉升所述第一上拉节点的电位，输出上拉电路在所述第一上拉节点的电压信号的控制下控制所述栅极驱动信号输出端与所述时钟信号端电连接；
在显示时间段包括的复位阶段，第一上拉节点控制电路在复位端输出的复位信号的控制下控制所述第一上拉节点与第一电压端电连接，第二上拉节点控制电路在所述复位信号的控制下控制所述第二上拉节点与第一电压端电连接；
在所述复位阶段和所述显示时间段包括的输出截止保持阶段，下拉节点控制电路在所述第二上拉节点的电压信号的控制下控制所述下拉节点与第二电压端电连接，输出下拉电路在所述下拉节点的电压信号的控制下控制所述栅极驱动信号输出端与第三电压端电连接。
实施时，本公开所述的移位寄存器单元的驱动方法还包括：在触控时间段，向第一电压端提供反向电压，以控制第一上拉节点控制电路包括的第一极与第一上拉节点连接的晶体管的漏电流小于预定漏电流，并控制第二上拉节点控制电路包括的第一极与第二上拉节点连接的晶体管的漏电流小于所述预定漏电流。
实施时，所述移位寄存器单元还包括输出复位电路；所述移位寄存器单元的驱动方法包括：
在所述复位阶段，所述输出复位电路在所述复位信号的控制下，控制所述栅极驱动信号输出端与第三电压端电连接。
另一方面，本公开还提供了一种栅极驱动电路，包括多级上述的移位寄存器单元；
除了第一级移位寄存器单元之外，每一级移位寄存器单元的输入端与相邻上一级移位寄存器单元的栅极驱动信号输出端连接；
除了最后一级移位寄存器单元之外，每一级移位寄存器单元的复位端与相邻下一级移位寄存器单元的栅极驱动信号输出端连接。
另一方面，本公开还提供了一种显示装置，包括上述的栅极驱动电路。
另一方面，本公开还提供了一种移位寄存器单元，包括第一上拉节点控制电路、第二上拉节点控制电路、下拉节点控制电路、输出上拉电路和输出下拉电路，其中，
所述第一上拉节点控制电路分别与第一上拉节点、第一电压端、输入端、复位端、下拉节点和第二电压端直接连接，用于在所述输入端接入的输入信 号的控制下，控制所述第一上拉节点与所述第二电压端电连接，并用于在所述复位端输出的复位信号和/或所述下拉节点的电压信号的控制下，控制所述第一上拉节点与所述第一电压端电连接；
所述第二上拉节点控制电路分别与第二上拉节点、所述第一电压端、所述输入端、所述复位端、所述下拉节点和第二电压端直接连接，用于在所述输入信号的控制下，控制所述第二上拉节点与所述输入端电连接，在所述复位信号的控制下，控制所述第二上拉节点与所述第一电压端电连接；
所述下拉节点控制电路分别与下拉节点、所述第二上拉节点、所述第二电压端和第三电压端直接连接，用于在所述第二上拉节点的电压信号的控制下控制所述下拉节点的电位；
所述输出上拉电路分别与所述第一上拉节点、时钟信号端、栅极驱动信号输出端直接连接，用于在所述第一上拉节点的电压信号的控制下，控制所述栅极驱动信号输出端与所述时钟信号端电连接；
所述输出下拉电路分别与所述下拉节点、所述第三电压端和所述栅极驱动信号输出端直接连接，用于在所述下拉节点的电压信号的控制下，控制所述栅极驱动信号输出端与所述第三电压端电连接。
实施时，所述第一上拉节点控制电路包括：
第一晶体管，栅极与所述输入端直接连接，第一极与所述第二电压端直接连接，第二极与所述第一上拉节点直接连接；
第二晶体管，栅极与所述复位端直接连接，第一极与所述第一上拉节点直接连接，第二极与所述第一电压端直接连接；以及，
第七晶体管，栅极与所述下拉节点直接连接，第一极与所述第一上拉节点直接连接，第二极与所述第一电压端直接连接。
实施时，所述第二上拉节点控制电路包括：
第十一晶体管，栅极与所述输入端直接连接，第一极与所述第二电压端直接连接，第二极与所述第二上拉节点直接连接；以及，
第十二晶体管，栅极与所述复位端直接连接，第一极与所述第二上拉节点直接连接，第二极与所述第一电压端直接连接。
实施时，所述下拉节点控制电路包括：
第九晶体管，栅极和第一极都与第二电压端直接连接，第二极与下拉控制节点直接连接；
第八晶体管，栅极与所述第二上拉节点直接连接，第一极与所述下拉控制节点直接连接，第二极与所述第三电压端直接连接；
第五晶体管，栅极与所述下拉控制节点直接连接，第一极与所述第二电压端直接连接，第二极与所述下拉节点直接连接；以及，
第六晶体管，栅极与所述第二上拉节点直接连接，第一极与所述下拉节点直接连接，第二极与所述第三电压端直接连接。
实施时，输出上拉电路包括：第三晶体管，栅极与所述第一上拉节点直接连接，第一极与所述时钟信号端直接连接，第二极与所述栅极驱动信号输出端直接连接；以及，
存储电容，第一端与所述第一上拉节点直接连接，第二端与所述栅极驱动信号输出端直接连接。
实施时，所述输出下拉电路包括：第十晶体管，栅极与所述下拉节点直接连接，第一极与所述栅极驱动信号输出端直接连接，第二极与所述第三电压端直接连接。
实施时，所述的移位寄存器单元还包括输出复位电路；
所述输出复位电路分别与所述复位端、所述栅极驱动信号输出端和所述第三电压端直接连接，用于在复位阶段，在所述复位信号的控制下控制所述栅极驱动信号输出端与所述第三电压端电连接。
实施时，所述输出复位电路包括：第四晶体管，栅极与所述复位端直接连接，第一极与所述栅极驱动信号输出端直接连接，第二极与第三电压端直接连接。
附图说明
图1是本公开实施例所述的移位寄存器单元的结构图；
图2是本公开另一实施例所述的移位寄存器单元的结构图；
图3是本公开又一实施例所述的移位寄存器单元的结构图；
图4是本公开所述的移位寄存器单元的一具体实施例的电路图；
图5是本公开所述的移位寄存器单元的该具体实施例的工作时序图；
图6是本公开所述的栅极驱动电路的一具体实施例的结构图；
图7是本公开所述的栅极驱动电路的该具体实施例的工作时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。在实际操作时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
如图1所示，本公开实施例所述的移位寄存器单元包括第一上拉节点控制电路11、第二上拉节点控制电路12、下拉节点控制电路13、输出上拉电路14和输出下拉电路15，其中，
所述第一上拉节点控制电路11分别与第一上拉节点PU1、第一电压端VD1、输入端INPUT、复位端RESET、下拉节点PD和第二电压端VD2连接，用于在所述输入端INPUT接入的输入信号的控制下，控制所述第一上拉节点PU1与所述第二电压端VD2电连接，并用于在所述复位端RESET输出的复位信号和/或所述下拉节点PD的电压信号的控制下，控制所述第一上拉节点PU1与所述第一电压端VD1电连接；
所述第二上拉节点控制电路12分别与第二上拉节点PU2、所述第一电压端VD1、所述输入端INPUT、所述复位端RESET、所述下拉节点PD和第二电压端VD2连接，用于在所述输入信号的控制下，控制所述第二上拉节点PU2与所述输入端INPUT电连接，在所述复位信号的控制下，控制所述第二上拉节点PU2与所述第一电压端VD1电连接；
所述下拉节点控制电路13分别与所述下拉节点PD、所述第二上拉节点 PU2、所述第二电压端VD2和第三电压端VD3连接，用于在所述第二上拉节点PU2的电压信号的控制下控制所述下拉节点PD的电位；
所述输出上拉电路14分别与所述第一上拉节点PU1、时钟信号端CLK、栅极驱动信号输出端OUTPUT连接，用于在所述第一上拉节点PU1的电压信号的控制下，控制所述栅极驱动信号输出端OUTPUT与所述时钟信号端CLK电连接；
所述输出下拉电路15分别与所述下拉节点PD、所述第三电压端VD3和所述栅极驱动信号输出端OUTPUT连接，用于在所述下拉节点PD的电压信号的控制下，控制所述栅极驱动信号输出端OUTPUT与所述第三电压端VD3电连接。
本公开实施例所述的移位寄存器单元设置两个上拉节点：第一上拉节点PU1和第二上拉节点PU2，通过第一上拉节点PU1控制栅极驱动信号输出，通过第二上拉节点PU2控制下拉节点PD的电位，避免了相关技术中一个上拉节点和一个下拉节点相互制约而难以设置下拉节点控制电路13中的晶体管的宽长比的情况发生；并且本公开实施例所述的移位寄存器单元增加第一电压端VD1，使得第一上拉节点控制电路11和第二上拉节点控制电路12都与第一电压端VD1连接，可以通过在触控时间段调高第一电压端VD1输出的电压来减小晶体管的漏电流，从而避免在触控时间段无法保持第一上拉节点PU1的电位和第二上拉节点PU2的电位而导致的误输出的问题。
由于相关技术中的移位寄存器单元仅包括一个上拉节点，该上拉节点同时执行控制栅极驱动信号输出和控制下拉节点电位的工作，同时该上拉节点的电位也受该下拉节点的影响，从而会出现难以设置下拉节点控制模块中的晶体管的宽长比的情况，据此，本公开实施例所述的移位寄存器单元设置两个上拉节点，通过第一上拉节点PU1控制栅极驱动信号输出，通过第二上拉节点PU2控制下拉节点的电位，以解决上述问题。
具体地，所述第一上拉节点控制电路可以包括：
第一上拉节点控制晶体管，栅极与所述输入端连接，第一极与所述第二电压端连接，第二极与所述第一上拉节点连接；
第二上拉节点控制晶体管，栅极与所述复位端连接，第一极与所述第一 上拉节点连接，第二极与所述第一电压端连接；以及，
第三上拉节点控制晶体管，栅极与所述下拉节点连接，第一极与所述第一上拉节点连接，第二极与所述第一电压端连接。
具体地，所述第二上拉节点控制电路可以包括：
第五上拉节点控制晶体管，栅极与所述输入端连接，第一极与所述第二电压端连接，第二极与所述第二上拉节点连接；以及，
第六上拉节点控制晶体管，栅极与所述复位端连接，第一极与所述第二上拉节点连接，第二极与所述第一电压端连接。
在本公开的一些实施例中，在图1所示的移位寄存器单元的实施例的基础上，如图2所示，所述第二电压端为输入高电压VDD的高电压端，所述第一电压端为输入第一低电压VSS’的第一低电压端；
所述第一上拉节点控制电路11包括：
第一上拉节点控制晶体管M1，栅极与所述输入端INPUT连接，漏极与所述输入高电压VDD的高电压端连接，源极与所述第一上拉节点PU1连接；
第二上拉节点控制晶体管M2，栅极与所述复位端RESET连接，漏极与所述第一上拉节点PU1连接，源极与所述输入第一低电压VSS’的第一低电压端连接；以及，
第三上拉节点控制晶体管M7，栅极与所述下拉节点PD连接，漏极与所述第一上拉节点PU1连接，源极接入所述第一低电压VSS’；
所述第二上拉节点控制电路12包括：
第五上拉节点控制晶体管M1’，栅极与所述输入端INPUT连接，漏极接入所述高电压VDD，源极与所述第二上拉节点PU2连接；以及，
第六上拉节点控制晶体管M2’，栅极与所述复位端RESET连接，漏极与所述第二上拉节点PU2连接，源极接入所述第一低电压VSS’。
在图2所示的实施例中，以所有的晶体管都为n型晶体管为例说明，但是在实际操作上，如上晶体管也可以被替换为p型晶体管。
本公开如图2所示的移位寄存器单元的实施例在工作时，
在显示时间段包括的输入阶段，在INPUT接入的输入信号的控制下，M1打开，以使得PU1接入VDD，M1’打开，以使得PU2也接入VDD；
在显示时间段包括的复位阶段，在RESET接入的复位信号的控制下，M2打开，以使得PU1接入VSS’，M2’打开，以使得PU2也接入VSS’；
在触控时间段，将VSS’设置为反向电压，以控制M2的漏电流和M7的漏电流小于预定漏电流，并控制M2’的漏电流小于预定漏电流。
在图2所示的移位寄存器单元的实施例中，由于M2、M7和M2’都为n型晶体管，因此如果需要减小M2的漏电流、M7的漏电流和M2’的漏电流，则需要减小M2的栅源电压、M7的栅源电压和M2’的栅源电压，因此在触控时间段，需要提升VSS’的电位，例如，如果在显示时间段VSS’为-8V，则在触控时间段，可以将VSS’设置0V，以减小以上晶体管的栅源电压，进而减小在触控时间段的漏电流，以维持PU1的电位和PU2的电位，防止在下一次进入显示时间段时由于晶体管漏电流而导致的下拉节点PD对第一上拉节点PU1和第二上拉节点PU2的控制能力太强，而导致PU1的电位和PU2的电位被PD拉低，从而造成栅极驱动电路完全失效的情况。
具体地，所述下拉节点控制电路可以包括：
第一下拉节点控制晶体管，栅极和第一极都与第二电压端连接，第二极与下拉控制节点连接；
第二下拉节点控制晶体管，栅极与所述第二上拉节点连接，第一极与所述下拉控制节点连接，第二极与所述第三电压端连接；
第三下拉节点控制晶体管，栅极与所述下拉控制节点连接，第一极与所述第二电压端连接，第二极与所述下拉节点连接；以及，
第四下拉节点控制晶体管，栅极与所述第二上拉节点连接，第一极与所述下拉节点连接，第二极与所述第三电压端连接。
具体地，所述输出上拉电路可以包括：输出上拉晶体管，栅极与所述第一上拉节点连接，第一极与所述时钟信号端连接，第二极与所述栅极驱动信号输出端连接；以及，
存储电容，第一端与所述第一上拉节点连接，第二端与所述栅极驱动信号输出端连接。
具体地，所述输出下拉电路可以包括：输出下拉晶体管，栅极与所述下拉节点连接，第一极与所述栅极驱动信号输出端连接，第二极与所述第三电 压端连接。
在本公开的一些实施例中，在图1所示的实施例的基础上，如图3所示，所述移位寄存器单元还可以包括输出复位电路16；
所述输出复位电路16分别与所述复位端RESET、所述栅极驱动信号输出端OUTPUT和所述第三电压端VD3连接，用于在复位阶段，在所述复位信号的控制下控制所述栅极驱动信号输出端OUTPUT与所述第三电压端VD3电连接。
具体地，所述输出复位电路可以包括：输出复位晶体管，栅极与所述复位端连接，第一极与所述栅极驱动信号输出端连接，第二极与第三电压端连接。
下面通过一具体实施例来说明本公开所述的移位寄存器单元。
图4是本公开所述的移位寄存器单元的一具体实施例的电路图，图4所示的移位寄存器单元为本公开实施例所述的栅极驱动电路包括的第N级移位寄存器单元，在第N行画面显示完之后(也即扫描了所述栅极驱动电路包括的第N级移位寄存器单元之后)，进入触控时间段，触控时间段结束后，继续扫描第N+1行移位寄存器单元；本公开实施例所述的栅极驱动电路中的第N+1级移位寄存器单元与第一时钟信号端CLK1连接。所述N为正整数。
如图4所示，本公开所述的移位寄存器单元的一具体实施例包括第一上拉节点控制电路11、第二上拉节点控制电路12、下拉节点控制电路13、输出上拉电路14、输出下拉电路15和输出复位电路16，其中，
所述第一上拉节点控制电路11包括：
第一上拉节点控制晶体管M1，栅极与所述输入端INPUT连接，漏极与所述输入高电压VDD的高电压端连接，源极与所述第一上拉节点PU1连接；
第二上拉节点控制晶体管M2，栅极与所述复位端RESET连接，漏极与所述第一上拉节点PU1连接，源极接入第一低电压VSS’；以及，
第三上拉节点控制晶体管M7，栅极与所述下拉节点PD连接，漏极与所述第一上拉节点PU1连接，源极接入所述第一低电压VSS’；
所述第二上拉节点控制电路12包括：
第五上拉节点控制晶体管M1’，栅极与所述输入端INPUT连接，漏极接入 所述高电压VDD，源极与所述第二上拉节点PU2连接；以及，
第六上拉节点控制晶体管M2’，栅极与所述复位端RESET连接，漏极与所述第二上拉节点PU2连接，源极接入所述第一低电压VSS’；
所述下拉节点控制电路13包括：
第一下拉节点控制晶体管M9，栅极和漏极都接入高电压VDD，源极与下拉控制节点PDCN连接；
第二下拉节点控制晶体管M8，栅极与所述第二上拉节点PU2连接，漏极与所述下拉控制节点PDCN连接，源极接入第二低电压VSS；
第三下拉节点控制晶体管M5，栅极与所述下拉控制节点PDCN连接，漏极与接入高电压VDD，源极与所述下拉节点PD连接；以及，
第四下拉节点控制晶体管M6，栅极与所述第二上拉节点PU2连接，漏极与所述下拉节点PD连接，源极接入所述第二低电压VSS；
所述输出上拉电路14包括：输出上拉晶体管M3，栅极与所述第一上拉节点PU1连接，漏极与时钟信号端CLK连接，源极与栅极驱动信号输出端OUTPUT连接；以及，
存储电容C，第一端与所述第一上拉节点PU1连接，第二端与所述栅极驱动信号输出端OUTPUT连接；
所述输出下拉电路15包括：输出下拉晶体管M10，栅极与所述下拉节点PD连接，漏极与所述栅极驱动信号输出端OUTPUT连接，源极接入第二低电压VSS；
所述输出复位电路16包括：输出复位晶体管M4，栅极与所述复位端RESET连接，漏极与所述级栅极驱动信号输出端OUTPUT连接，源极接入第二低电压VSS。
在图4所示的具体实施例中，所有的晶体管都为n型晶体管，但不以此为限。
本公开如图4所示的移位寄存器单元的具体实施例采用了两个上拉节点：第一上拉节点PU1和第二上拉节点PU2，PU1用于控制M3的栅极，PU2用于控制M6的栅极和M8的栅极，来给PD和PDCN放电，通过PU2来控制PD的电位，但是PD不能控制PU2的放电，仅能通过M2’来实现PU2的放电，本公开实施例 所述的移位寄存器单元的优点如下：两个上拉节点分立工作，只需要将M5的宽长比和M6的宽长比的比例设置的尽量小即可，可以避免因设计比例失调带来的OUTPUT失效高发现象或者栅极驱动信号输出能力不足的影响，受晶体管工艺波动的影响也小，GOA(Gate On Array，设置于阵列基板上的栅极驱动电路)的信赖性高。同时在进行触控扫描的触控时间段内，VSS一直为-8V，将VSS’由低电平拉高，使得VSS’为0V，能够使得在触控时间段，M2的栅源电压、M7的栅源电压和M2’的栅源电压都为-8V，此时M2的漏电流、M7的漏电流和M2’的漏电流小至可以忽略，避免了PU1的电位和PU2的电位在触控时间段因大幅漏电而降低。
本公开如图4所示的移位寄存器单元的具体实施例在工作时，在显示时间段，VSS和VSS’都为-8V，在触控时间段，VSS’为0V，VSS为-8V。
如图5所示，本公开如图4所示的移位寄存器单元的具体实施例在工作时，在显示时间段，
在输入阶段t51，INPUT输入高电平，RESET输出低电平，CLK输出低电平，M1和M1’都打开，以使得PU1和PU2都接入VDD，M6和M8都打开，以控制PD的电位为低电平，M3打开，以使得OUTPUT与CLK连接，OUTPUT输出低电平；
在输出阶段t52，INPUT输入低电平，RESET输出低电平，CLK输出高电平，存储电容C自举拉升PU1的电位，M3打开，以使得OUTPUT与CLK连接，OUTPUT输出高电平；
在复位阶段t53，INPUT输入低电平，RESET输出高电平，CLK输出低电平，M2和M2’都打开，以将PU1的电位和PU2的电位拉低为-8V，PDCN的电被M9拉高为VDD，PD的电位被M5拉高为VDD，M4和M10都打开，以将OUTPUT输出的栅极驱动信号的电位拉低为-8V；
在输出截止保持阶段t54，INPUT输入低电平，RESET输出低电平，CLK间隔输出高电平、低电平，PD的电位为高电平，M10打开，以持续将OUTPUT输出的栅极驱动信号的电位拉低为-8V。
相关技术中的移位寄存器单元仅采用一个上拉节点PU及输入第二低电压VSS的第二低电压端，也即相关技术中的移位寄存器单元不包含图4中的 M1’、M2’和输入第一低电压VSS’的第一低电压端，相关技术中的栅极驱动电路在正常显示扫描时，当第N行移位寄存器单元的输入端输入高电平时(N为正整数)，第N行移位寄存器单元中的上拉节点的电位被拉高，而该上拉节点与M1的漏极、M2的漏极和M7的漏极都连接，对于传统LCD(Liquid Crystal Display，液晶显示器)使用较多的a-Si(非晶硅)薄膜晶体管来说，晶体管的栅源电压大约在-8V时，晶体管的漏电流最小，并且对于传统的OLED(有机发光二极管)显示器使用较多的LTPS TFT(低温多晶硅薄膜晶体管)来说，晶体管的栅源电压大约在-8V时，晶体管的漏电流最小，而如果晶体管的栅源电压为0V，则漏电流比较大。而对于内嵌式触控显示装置，触控时间段可能持续的时间为ms(毫秒)数量级，在触控时间段晶体管的漏电流导致的上拉节点的电压降低不可忽视。在相关技术中的移位寄存器单元中，由于M5的漏极和M9的漏极直接接入直流高电压，所以下拉控制节点PDCN的电位和下拉节点PD的电位理论上可以一直拉高为高电平，但是实际工作时，通过输入端输入的输入信号对上拉节点充电后，下拉节点PD的电位能够被上拉节点通过M6拉低为低电平，因此在上拉节点PU和下拉节点PD的制约关系上要满足PU的电压更强。因此在设计M5的宽长比与M6的宽长比的比例时，一般将该比例设为1：A，其中A为大于等于2而小于等于5的整数。当该比例过小时，PU对PD的控制能力差，当PU的电位需要为高电平时，可能PD会对PU进行放电，造成PU的电位低，M3的开启效果差，影响栅极驱动信号输出端的输出能力。当该比例过大时，PU对PD的控制能力过强，会导致一行移位寄存器单元工作结束后，PU的电位本应为低电平，但是由于PD的放噪能力差，从而导致PU的电位持续为高电平，导致显示异常。在设计栅极驱动电路之前会模拟出一个合适的M5的宽长比与M6的宽长比的比例，但是工艺上的波动是难以预估和控制的，因此实际做出来的栅极驱动电路还是会有比例设计失衡的情况发生，尤其是应用到内嵌式触控显示产品中，即使正常扫描行的PU和PD制约能力平衡，但是由于触控时间段内PU的电位会因漏电而降低，会导致触控时间段之后的几行移位寄存器单元中的下拉节点PD对PU的控制能力过强，导致栅极驱动电路失效。
本公开实施例所述的移位寄存器单元的驱动方法，应用于上述的移位寄 存器单元，所述移位寄存器单元的驱动方法包括：
在显示时间段包括的输入阶段，在输入端接入的输入信号的控制下，第一上拉节点控制电路控制第一上拉节点与第二电压端连接，第二上拉节点控制电路控制第二上拉节点与第二电压端电连接，下拉节点控制电路在第二上拉节点的电压信号的控制下，控制下拉节点的电位为第一电平，输出上拉电路在所述第一上拉节点的电压信号的控制下控制栅极驱动信号输出端与时钟信号端电连接；
在显示时间段包括的输出阶段，输出上拉电路自举拉升所述第一上拉节点的电位，输出上拉电路在所述第一上拉节点的电压信号的控制下控制所述栅极驱动信号输出端与所述时钟信号端电连接；
在显示时间段包括的复位阶段，第一上拉节点控制电路在复位端输出的复位信号的控制下控制所述第一上拉节点与第一电压端连接，第二上拉节点控制电路在所述复位信号的控制下控制所述第二上拉节点与第一电压端电连接；
在所述复位阶段和所述显示时间段包括的输出截止保持阶段，下拉节点控制电路在所述第二上拉节点的电压信号的控制下控制所述下拉节点与第二电压端连接，输出下拉电路在所述下拉节点的电压信号的控制下控制所述栅极驱动信号输出端与第三电压端电连接。
本公开实施例所述的移位寄存器单元的驱动方法通过第一上拉节点控制栅极驱动信号输出，通过第二上拉节点控制下拉节点的电位，避免了相关技术中一个上拉节点和一个下拉节点相互制约而难以设置下拉节点控制电路中的晶体管的宽长比的情况发生。
具体地，本公开实施例所述的移位寄存器单元的驱动方法还可以包括：在触控时间段，向第一电压端提供反向电压，以控制第一上拉节点控制电路包括的第一极与第一上拉节点连接的晶体管的漏电流小于预定漏电流，并控制第二上拉节点控制电路包括的第一极与第二上拉节点连接的晶体管的漏电流小于所述预定漏电流。
并本公开实施例所述的移位寄存器单元的驱动方法通过在触控时间段调高第一电压端输出的电压来减小第一上拉节点控制电路包括的第一极与第一 上拉节点连接的晶体管的漏电流以及第二上拉节点控制电路包括的第一极与第二上拉节点连接的晶体管的漏电流，从而避免在触控时间段无法保持第一上拉节点的电位和第二上拉节点的电位而导致的误输出的问题
在具体实施时，所述移位寄存器单元还可以包括输出复位电路；所述移位寄存器单元的驱动方法包括：
在所述复位阶段，所述输出复位电路在所述复位信号的控制下，控制所述栅极驱动信号输出端与第三电压端电连接。
本公开实施例所述的栅极驱动电路包括多级上述的移位寄存器单元；
除了第一级移位寄存器单元之外，每一级移位寄存器单元的输入端与相邻上一级移位寄存器单元的栅极驱动信号输出端连接；
除了最后一级移位寄存器单元之外，每一级移位寄存器单元的复位端与相邻下一级移位寄存器单元的栅极驱动信号输出端连接。
图6是本公开所述的栅极驱动电路的一具体实施例的结构图，本公开所述的栅极驱动电路包括的该具体实施例包括M级移位寄存器单元，M为正整数。
如图6所示，标号为GOA1的为所述栅极驱动电路包括的第一级移位寄存器单元，GOA1接入VSS和VSS’，并GOA1与第一时钟信号端CLK1连接，标号为OUT1的为GOA1的栅极驱动信号输出端，GOA1的输入端INPUT1接入起始信号STV；
标号为GOA2的为栅极驱动电路包括的第二级移位寄存器单元，GOA2接入VSS和VSS’，并GOA2与第二时钟信号端CLK2连接，标号为OUT2为GOA2的栅极驱动信号输出端，GOA2的输入端INPUT1与OUT1连接，标号为RESET2的为GOA2的复位端，OUT2与GOA1的复位端RESET1连接；
标号为GOAN-1的为所述栅极驱动电路包括的第N-1级移位寄存器单元，GOAN-1接入VSS和VSS’，并GOAN-1与第一时钟信号端CLK1连接，标号为OUTN-1为GOAN-1的栅极驱动信号输出端，标号为INPUTN-1的为GOAN-1的输入端，标号为RESETN-1的为GOAN-1的复位端；
标号为GOAN的为栅极驱动电路包括的第N级移位寄存器单元，GOAN接入VSS和VSS’，并GOAN与第二时钟信号端CLK2连接，标号为OUTN为GOAN的栅极驱动信号输出端，标号为INPUTN的为GOAN的输入端，标号为 RESETN的为GOAN的复位端，INPUTN与OUTN-1连接，RESETN-1与OUTN连接；
标号为GOAN+1的为所述栅极驱动电路包括的第N+1级移位寄存器单元，GOAN+1接入VSS和VSS’，并GOAN+1与第一时钟信号端CLK1连接，标号为OUTN+1为GOAN+1的栅极驱动信号输出端，标号为INPUTN+1的为GOAN+1的输入端，标号为RESETN+1的为GOAN+1的复位端，INPUTN+1与OUTN连接，RESETN与OUTN+1连接；
标号为GOAM的为栅极驱动电路包括的第M级移位寄存器单元，GOAM接入VSS和VSS’，并GOAM与第二时钟信号端CLK2连接，标号为OUTM为GOAM的栅极驱动信号输出端，标号为INPUTM的为GOAM的输入端，标号为RESETM的为GOAM的复位端；
其中，N为正整数，N大于1并N+1小于M；
在图6所示的栅极驱动电路的具体实施例中，CLK1输出的第一时钟信号和CLK2输出第二时钟信号相互反相，并在第N行显示扫描结束之后(也即GOAN完成了栅极驱动扫描后)，进入触控时间段LHB，触控时间段LHB结束后，继续扫描第N+1行移位寄存器单元GOAN+1。
当图6中的栅极驱动电路包括的各级移位寄存器单元的结构如图4所示时，图7是本公开如图6所示的栅极驱动电路的具体实施例在工作时序图。
在图7中，PU1-N为GOAN中的第一上拉节点，PU-N+1为GOAN+1中的第一上拉节点，VSS’为第一低电压。
如图7所示，在第一显示时间段TD1，扫描GOA1至GOAN，在第二显示时间段TD2，扫描GOAN+1至GOAM，在触控时间段LHB进行触控扫描，在触控时间段LHB，VSS’被拉升为0V，在第一显示时间段TD1和第二显示时间段TD2，VSS’为-8V。
并在第一显示时间段TD1、触控时间段LHB和第二显示时间段TD2，VSS一直保持为-8V。
由图7可知，本公开所述的栅极驱动电路的具体实施例在工作时，在触控时间段LHB，PU1-N的电位和PU1-N+1的电位能够维持为高电平，以使得LHB结束后，GOAN+1能够正常工作，OUTN+1能够正常输出栅极驱动信号。
本公开实施例所述的显示装置包括上述的栅极驱动电路。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (21)

  1. 一种移位寄存器单元，包括第一上拉节点控制电路、第二上拉节点控制电路、下拉节点控制电路、输出上拉电路和输出下拉电路，其中，
    所述第一上拉节点控制电路分别与第一上拉节点、第一电压端、输入端、复位端、下拉节点和第二电压端连接，用于在所述输入端接入的输入信号的控制下，控制所述第一上拉节点与所述第二电压端电连接，并用于在所述复位端输出的复位信号和/或所述下拉节点的电压信号的控制下，控制所述第一上拉节点与所述第一电压端电连接；
    所述第二上拉节点控制电路分别与第二上拉节点、所述第一电压端、所述输入端、所述复位端、所述下拉节点和第二电压端连接，用于在所述输入信号的控制下，控制所述第二上拉节点与所述输入端电连接，在所述复位信号的控制下，控制所述第二上拉节点与所述第一电压端电连接；
    所述下拉节点控制电路分别与下拉节点、所述第二上拉节点、所述第二电压端和第三电压端连接，用于在所述第二上拉节点的电压信号的控制下控制所述下拉节点的电位；
    所述输出上拉电路分别与所述第一上拉节点、时钟信号端、栅极驱动信号输出端连接，用于在所述第一上拉节点的电压信号的控制下，控制所述栅极驱动信号输出端与所述时钟信号端电连接；
    所述输出下拉电路分别与所述下拉节点、所述第三电压端和所述栅极驱动信号输出端连接，用于在所述下拉节点的电压信号的控制下，控制所述栅极驱动信号输出端与所述第三电压端电连接。
  2. 如权利要求1所述的移位寄存器单元，其中，所述第一上拉节点控制电路包括：
    第一晶体管，栅极与所述输入端连接，第一极与所述第二电压端连接，第二极与所述第一上拉节点连接；
    第二晶体管，栅极与所述复位端连接，第一极与所述第一上拉节点连接，第二极与所述第一电压端连接；以及，
    第七晶体管，栅极与所述下拉节点连接，第一极与所述第一上拉节点连 接，第二极与所述第一电压端连接。
  3. 如权利要求1所述的移位寄存器单元，其中，所述第二上拉节点控制电路包括：
    第十一晶体管，栅极与所述输入端连接，第一极与所述第二电压端连接，第二极与所述第二上拉节点连接；以及，
    第十二晶体管，栅极与所述复位端连接，第一极与所述第二上拉节点连接，第二极与所述第一电压端连接。
  4. 如权利要求1至3中任一权利要求所述的移位寄存器单元，其中，所述下拉节点控制电路包括：
    第九晶体管，栅极和第一极都与第二电压端连接，第二极与下拉控制节点连接；
    第八晶体管，栅极与所述第二上拉节点连接，第一极与所述下拉控制节点连接，第二极与所述第三电压端连接；
    第五晶体管，栅极与所述下拉控制节点连接，第一极与所述第二电压端连接，第二极与所述下拉节点连接；以及，
    第六晶体管，栅极与所述第二上拉节点连接，第一极与所述下拉节点连接，第二极与所述第三电压端连接。
  5. 如权利要求1至3中任一权利要求所述的移位寄存器单元，其中，输出上拉电路包括：第三晶体管，栅极与所述第一上拉节点连接，第一极与所述时钟信号端连接，第二极与所述栅极驱动信号输出端连接；以及，
    存储电容，第一端与所述第一上拉节点连接，第二端与所述栅极驱动信号输出端连接。
  6. 如权利要求1至3中任一权利要求所述的移位寄存器单元，其中，所述输出下拉电路包括：第十晶体管，栅极与所述下拉节点连接，第一极与所述栅极驱动信号输出端连接，第二极与所述第三电压端连接。
  7. 如权利要求1至3中任一权利要求所述的移位寄存器单元，还包括输出复位电路；
    所述输出复位电路分别与所述复位端、所述栅极驱动信号输出端和所述第三电压端连接，用于在复位阶段，在所述复位信号的控制下控制所述栅极 驱动信号输出端与所述第三电压端电连接。
  8. 如权利要求7所述的移位寄存器单元，其中，所述输出复位电路包括：第四晶体管，栅极与所述复位端连接，第一极与所述栅极驱动信号输出端连接，第二极与第三电压端连接。
  9. 一种移位寄存器单元的驱动方法，应用于如权利要求1至8中任一权利要求所述的移位寄存器单元，其中，所述移位寄存器单元的驱动方法包括：
    在显示时间段包括的输入阶段，在输入端接入的输入信号的控制下，第一上拉节点控制电路控制第一上拉节点与第二电压端电连接，第二上拉节点控制电路控制第二上拉节点与第二电压端电连接，下拉节点控制电路在第二上拉节点的电压信号的控制下，控制下拉节点的电位为第一电平，输出上拉电路在所述第一上拉节点的电压信号的控制下控制栅极驱动信号输出端与时钟信号端电连接；
    在显示时间段包括的输出阶段，输出上拉电路自举拉升所述第一上拉节点的电位，输出上拉电路在所述第一上拉节点的电压信号的控制下控制所述栅极驱动信号输出端与所述时钟信号端电连接；
    在显示时间段包括的复位阶段，第一上拉节点控制电路在复位端输出的复位信号的控制下控制所述第一上拉节点与第一电压端电连接，第二上拉节点控制电路在所述复位信号的控制下控制所述第二上拉节点与第一电压端电连接；
    在所述复位阶段和所述显示时间段包括的输出截止保持阶段，下拉节点控制电路在所述第二上拉节点的电压信号的控制下控制所述下拉节点与第二电压端电连接，输出下拉电路在所述下拉节点的电压信号的控制下控制所述栅极驱动信号输出端与第三电压端电连接。
  10. 如权利要求9所述的移位寄存器单元的驱动方法，还包括：在触控时间段，向第一电压端提供反向电压，以控制第一上拉节点控制电路包括的第一极与第一上拉节点连接的晶体管的漏电流小于预定漏电流，并控制第二上拉节点控制电路包括的第一极与第二上拉节点连接的晶体管的漏电流小于所述预定漏电流。
  11. 如权利要求9或10所述的移位寄存器单元的驱动方法，其中，所述 移位寄存器单元还包括输出复位电路；所述移位寄存器单元的驱动方法包括：
    在所述复位阶段，所述输出复位电路在所述复位信号的控制下，控制所述栅极驱动信号输出端与第三电压端电连接。
  12. 一种栅极驱动电路，包括多级如权利要求1至8中任一权利要求所述的移位寄存器单元；
    除了第一级移位寄存器单元之外，每一级移位寄存器单元的输入端与相邻上一级移位寄存器单元的栅极驱动信号输出端连接；
    除了最后一级移位寄存器单元之外，每一级移位寄存器单元的复位端与相邻下一级移位寄存器单元的栅极驱动信号输出端连接。
  13. 一种显示装置，包括如权利要求12所述的栅极驱动电路。
  14. 一种移位寄存器单元，包括第一上拉节点控制电路、第二上拉节点控制电路、下拉节点控制电路、输出上拉电路和输出下拉电路，其中，
    所述第一上拉节点控制电路分别与第一上拉节点、第一电压端、输入端、复位端、下拉节点和第二电压端直接连接，用于在所述输入端接入的输入信号的控制下，控制所述第一上拉节点与所述第二电压端电连接，并用于在所述复位端输出的复位信号和/或所述下拉节点的电压信号的控制下，控制所述第一上拉节点与所述第一电压端电连接；
    所述第二上拉节点控制电路分别与第二上拉节点、所述第一电压端、所述输入端、所述复位端、所述下拉节点和第二电压端直接连接，用于在所述输入信号的控制下，控制所述第二上拉节点与所述输入端电连接，在所述复位信号的控制下，控制所述第二上拉节点与所述第一电压端电连接；
    所述下拉节点控制电路分别与下拉节点、所述第二上拉节点、所述第二电压端和第三电压端直接连接，用于在所述第二上拉节点的电压信号的控制下控制所述下拉节点的电位；
    所述输出上拉电路分别与所述第一上拉节点、时钟信号端、栅极驱动信号输出端直接连接，用于在所述第一上拉节点的电压信号的控制下，控制所述栅极驱动信号输出端与所述时钟信号端电连接；
    所述输出下拉电路分别与所述下拉节点、所述第三电压端和所述栅极驱动信号输出端直接连接，用于在所述下拉节点的电压信号的控制下，控制所 述栅极驱动信号输出端与所述第三电压端电连接。
  15. 如权利要求14所述的移位寄存器单元，其中，所述第一上拉节点控制电路包括：
    第一晶体管，栅极与所述输入端直接连接，第一极与所述第二电压端直接连接，第二极与所述第一上拉节点直接连接；
    第二晶体管，栅极与所述复位端直接连接，第一极与所述第一上拉节点直接连接，第二极与所述第一电压端直接连接；以及，
    第七晶体管，栅极与所述下拉节点直接连接，第一极与所述第一上拉节点直接连接，第二极与所述第一电压端直接连接。
  16. 如权利要求14所述的移位寄存器单元，其中，所述第二上拉节点控制电路包括：
    第十一晶体管，栅极与所述输入端直接连接，第一极与所述第二电压端直接连接，第二极与所述第二上拉节点直接连接；以及，
    第十二晶体管，栅极与所述复位端直接连接，第一极与所述第二上拉节点直接连接，第二极与所述第一电压端直接连接。
  17. 如权利要求14至16中任一权利要求所述的移位寄存器单元，其中，所述下拉节点控制电路包括：
    第九晶体管，栅极和第一极都与第二电压端直接连接，第二极与下拉控制节点直接连接；
    第八晶体管，栅极与所述第二上拉节点直接连接，第一极与所述下拉控制节点直接连接，第二极与所述第三电压端直接连接；
    第五晶体管，栅极与所述下拉控制节点直接连接，第一极与所述第二电压端直接连接，第二极与所述下拉节点直接连接；以及，
    第六晶体管，栅极与所述第二上拉节点直接连接，第一极与所述下拉节点直接连接，第二极与所述第三电压端直接连接。
  18. 如权利要求14至16中任一权利要求所述的移位寄存器单元，其中，输出上拉电路包括：第三晶体管，栅极与所述第一上拉节点直接连接，第一极与所述时钟信号端直接连接，第二极与所述栅极驱动信号输出端直接连接；以及，
    存储电容，第一端与所述第一上拉节点直接连接，第二端与所述栅极驱动信号输出端直接连接。
  19. 如权利要求14至16中任一权利要求所述的移位寄存器单元，其中，所述输出下拉电路包括：第十晶体管，栅极与所述下拉节点直接连接，第一极与所述栅极驱动信号输出端直接连接，第二极与所述第三电压端直接连接。
  20. 如权利要求14至16中任一权利要求所述的移位寄存器单元，还包括输出复位电路；
    所述输出复位电路分别与所述复位端、所述栅极驱动信号输出端和所述第三电压端直接连接，用于在复位阶段，在所述复位信号的控制下控制所述栅极驱动信号输出端与所述第三电压端电连接。
  21. 如权利要求20所述的移位寄存器单元，其中，所述输出复位电路包括：第四晶体管，栅极与所述复位端直接连接，第一极与所述栅极驱动信号输出端直接连接，第二极与第三电压端直接连接。
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