WO2023087298A1 - 移位寄存器单元、栅极驱动电路及显示装置 - Google Patents

移位寄存器单元、栅极驱动电路及显示装置 Download PDF

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Publication number
WO2023087298A1
WO2023087298A1 PCT/CN2021/132026 CN2021132026W WO2023087298A1 WO 2023087298 A1 WO2023087298 A1 WO 2023087298A1 CN 2021132026 W CN2021132026 W CN 2021132026W WO 2023087298 A1 WO2023087298 A1 WO 2023087298A1
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WIPO (PCT)
Prior art keywords
pull
pole
node
transistor
control
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PCT/CN2021/132026
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English (en)
French (fr)
Inventor
任锦宇
刘海生
彭宽军
张方振
王锦谦
马国靖
王丹
王玮
冯莎
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/132026 priority Critical patent/WO2023087298A1/zh
Priority to CN202180003513.6A priority patent/CN116830202A/zh
Publication of WO2023087298A1 publication Critical patent/WO2023087298A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • the disclosure belongs to the field of display technology, and in particular relates to a shift register unit, a gate drive circuit and a display device.
  • GOA Gate Driver on Array, integrated gate drive circuit
  • COF Chip On Film, chip-on-film
  • COG Chip On Glass
  • the chip is directly fixed on the glass) process, which not only saves the cost, but also can achieve a symmetrical and beautiful design on both sides of the panel, and can also save the Bonding (pressure welding) area of the gate drive circuit and the peripheral wiring space, thereby realizing
  • the design of the narrow frame of the display device improves the production capacity and yield rate of the display device.
  • the active layer material of the thin film transistor used in the GOA circuit can be a-Si (amorphous silicon), LTPS (low temperature polysilicon), metal oxide semiconductor, such as a typical material IGZO (Indium Gallium Zinc Oxide, Indium Gallium Zinc Oxide) wait.
  • metal oxide transistors such as thin-film transistors whose active layer material is IGZO
  • IGZO Indium Gallium Zinc Oxide
  • GOA circuits usually use metal oxide transistors (such as thin-film transistors whose active layer material is IGZO) as thin-film transistors in the GOA circuit, but when the size and resolution of the display are further increased, it is necessary to use higher mobility Oxide material thin film transistors are used in GOA circuits.
  • the threshold voltage of the thin film transistor is unstable, and negative bias fluctuations are prone to occur, causing the thin film transistor to generate leakage current, which affects the working performance of the GOA circuit, and causes the display panel driven to be prone to poor display. question.
  • the present disclosure aims to solve at least one of the technical problems existing in the prior art, and provides a shift register unit, a gate driving circuit and a display device.
  • an embodiment of the present disclosure provides a shift register unit, the shift register unit includes: an input subcircuit, an output subcircuit, a pull-down control subcircuit, a pull-down subcircuit, a first noise reduction subcircuit, a first an auxiliary control subcircuit and a second auxiliary control subcircuit;
  • the input subcircuit is configured to pull up the potential of the pull-up node through the input signal in response to the input signal at the signal input terminal; the pull-up node is at least simultaneously connected to the input subcircuit and the output subcircuit , the first noise reduction sub-circuit;
  • the output subcircuit is configured to output a signal through a signal output terminal in response to the potential of the pull-up node being pulled high;
  • the pull-down control subcircuit is configured to use the first power supply voltage signal to control the potential of the pull-down node in response to the first power supply voltage signal; the pull-down node is at least simultaneously connected to the pull-down control subcircuit, the pull-down subcircuit and the first noise reduction sub-circuit;
  • the pull-down sub-circuit is configured to pull down the potential of the pull-down node through a first reference level signal in response to the potential of the pull-down control node; the pull-down control node is at least simultaneously connected to the pull-down sub-circuit, the first an auxiliary control subcircuit and said second auxiliary control subcircuit;
  • the first denoising sub-circuit is configured to denoise the potential of the pull-up node through a second reference level signal in response to the potential of the pull-down node;
  • the first auxiliary control sub-circuit is configured to write a third reference level signal into the pull-down control node when the pull-down node is a first reference level signal, and control the pull-down sub-circuit to close, so that controlling the first noise reduction sub-circuit to be turned off;
  • the second auxiliary control sub-circuit is configured to write a first reference level signal into the pull-down control node when the pull-down node is a first power supply voltage signal, and control the pull-down sub-circuit to turn off, so as to Controlling the first noise reduction sub-circuit to reduce noise on the pull-up node through the second reference level signal.
  • the first auxiliary control subcircuit includes: a first storage capacitor; one end of the first storage capacitor is connected to the pull-down control node, and the other end is connected to the first power supply voltage terminal; the pull-down control node connecting said input subcircuit;
  • the second auxiliary control sub-circuit includes: a ninth transistor and a tenth transistor; the control pole of the ninth transistor is connected to the auxiliary control terminal, the first pole is connected to the first reference level terminal, and the second pole is connected to the pull-down control node ; The control pole of the tenth transistor is connected to the pull-down node, the first pole is connected to the first reference level terminal, and the second pole is connected to the pull-down control node.
  • the first auxiliary control subcircuit includes: an eleventh transistor; the control electrode and the first electrode of the eleventh transistor are both connected to the signal input terminal, and the second electrode is connected to the pull-down control node;
  • the second auxiliary control sub-circuit includes: a twelfth transistor and a thirteenth transistor; the control pole of the twelfth transistor is connected to the auxiliary control terminal, the first pole is connected to the first reference level terminal, and the second pole is connected to the A pull-down control node; the control pole of the thirteenth transistor is connected to the pull-down node, the first pole is connected to the first reference level terminal, and the second pole is connected to the pull-down control node.
  • the first auxiliary control subcircuit includes: a fourteenth transistor; the control electrode and the first electrode of the fourteenth transistor are connected to the first power supply voltage terminal, and the second electrode is connected to the pull-down control node ;
  • the second auxiliary control sub-circuit includes: a fifteenth transistor and a sixteenth transistor; the control pole of the fifteenth transistor is connected to the pull-down node, the first pole is connected to the first reference level terminal, and the second pole is connected to the pull-down node.
  • the shift register unit further includes: a second noise reduction sub-circuit
  • the second denoising sub-circuit is configured to denoise the potential of the signal output terminal through a second reference level signal in response to the potential of the pull-down node.
  • the second noise reduction sub-circuit includes: a fourth transistor
  • the control pole of the fourth transistor is connected to the pull-down node, the first pole is connected to the second reference level terminal, and the second pole is connected to the signal output terminal.
  • the shift register unit further includes: a reset subcircuit
  • the reset subcircuit is configured to reset the potential of the pull-up node through a second reference level signal in response to a reset signal.
  • the reset subcircuit includes: a second transistor
  • the control pole of the second transistor is connected to the reset signal terminal, the first pole is connected to the second reference level terminal, and the second pole is connected to the pull-up node.
  • the input subcircuit includes: a first transistor
  • control electrode and the first electrode of the first transistor are connected to the signal input terminal, and the second electrode is connected to the pull-up node.
  • the output subcircuit includes: a third transistor and a second storage capacitor;
  • the control pole of the third transistor is connected to the pull-up node, the first pole is connected to the clock signal terminal, and the second pole is connected to the signal output terminal;
  • One end of the second storage capacitor is connected to the pull-up node, and the other end is connected to the signal output end.
  • the pull-down control subcircuit includes: a fifth transistor
  • control electrode and the first electrode of the fifth transistor are connected to the first power supply voltage terminal, and the second electrode is connected to the pull-down node.
  • the pull-down sub-circuit includes: a sixth transistor and a seventh transistor;
  • the control pole of the sixth transistor is connected to the pull-down control node, the first pole is connected to the first reference level terminal, and the second pole is connected to the pull-down node;
  • the control pole of the seventh transistor is connected to the signal input terminal, the first pole is connected to the first power supply voltage terminal, and the second pole is connected to the pull-down node.
  • the first noise reduction sub-circuit includes: an eighth transistor;
  • the control electrode of the eighth transistor is connected to the pull-down node, the first electrode is connected to the first reference level terminal, and the second electrode is connected to the pull-up node.
  • an embodiment of the present disclosure provides a shift register unit, the shift register unit includes: an input subcircuit, a reset subcircuit, an output subcircuit, a pull-down control subcircuit, a pull-down subcircuit, a first noise reduction subcircuit circuit, a second noise reduction subcircuit, a first auxiliary control subcircuit, and a second auxiliary control subcircuit;
  • the pull-up node is at least simultaneously connected to the input subcircuit, the output subcircuit, and the first noise reduction subcircuit;
  • the pull-down node is at least simultaneously connected to the pull-down control sub-circuit, the pull-down sub-circuit and the first noise reduction sub-circuit;
  • the pull-down control node is at least simultaneously connected to the pull-down sub-circuit, the first auxiliary control sub-circuit and the a second auxiliary control subcircuit;
  • the input subcircuit includes: a first transistor; the reset subcircuit includes: a second transistor; the output subcircuit includes: a third transistor and a second storage capacitor; the second noise reduction subcircuit includes: a fourth Transistor; the pull-down control sub-circuit includes: a fifth transistor; the pull-down sub-circuit includes: a sixth transistor and a seventh transistor; the first noise reduction sub-circuit includes: an eighth transistor; the first auxiliary control sub-circuit
  • the circuit includes: a first storage capacitor; the second auxiliary control sub-circuit includes: a ninth transistor and a tenth transistor;
  • control pole and the first pole of the first transistor are connected to the signal input terminal, and the second pole is connected to the pull-up node; the pull-up node is at least simultaneously connected to the input sub-circuit, the output sub-circuit, and the second a noise reduction sub-circuit;
  • the control pole of the second transistor is connected to the reset signal terminal, the first pole is connected to the second reference level terminal, and the second pole is connected to the pull-up node;
  • the control pole of the third transistor is connected to the pull-up node, the first pole is connected to the clock signal terminal, and the second pole is connected to the signal output terminal;
  • One end of the second storage capacitor is connected to the pull-up node, and the other end is connected to the signal output end;
  • the control pole of the fourth transistor is connected to the pull-down node, the first pole is connected to the second reference level terminal, and the second pole is connected to the signal output terminal;
  • control electrode and the first electrode of the fifth transistor are connected to the first power supply voltage terminal, and the second electrode is connected to the pull-down node;
  • the control pole of the sixth transistor is connected to the pull-down control node, the first pole is connected to the first reference level terminal, and the second pole is connected to the pull-down node;
  • the control pole of the seventh transistor is connected to the signal input terminal, the first pole is connected to the first power supply voltage terminal, and the second pole is connected to the pull-down node;
  • the control pole of the eighth transistor is connected to the pull-down node, the first pole is connected to the first reference level terminal, and the second pole is connected to the pull-up node;
  • One end of the first storage capacitor is connected to the pull-down control node, and the other end is connected to the first power supply voltage end; the pull-down control node is connected to the second pole of the first transistor;
  • the control pole of the ninth transistor is connected to the auxiliary control terminal, the first pole is connected to the first reference level terminal, and the second pole is connected to the pull-down control node; the control pole of the tenth transistor is connected to the pull-down node, and the first pole is connected to the pull-down control node. connected to the first reference level terminal, and the second pole connected to the pull-down control node.
  • an embodiment of the present disclosure provides a shift register unit, the shift register unit includes: an input subcircuit, a reset subcircuit, an output subcircuit, a pull-down control subcircuit, a pull-down subcircuit, a first noise reduction subcircuit circuit, a second noise reduction subcircuit, a first auxiliary control subcircuit, and a second auxiliary control subcircuit;
  • the pull-up node is at least simultaneously connected to the input subcircuit, the output subcircuit, and the first noise reduction subcircuit;
  • the pull-down node is at least simultaneously connected to the pull-down control sub-circuit, the pull-down sub-circuit and the first noise reduction sub-circuit;
  • the pull-down control node is at least simultaneously connected to the pull-down sub-circuit, the first auxiliary control sub-circuit and the a second auxiliary control subcircuit;
  • the input subcircuit includes: a first transistor; the reset subcircuit includes: a second transistor; the output subcircuit includes: a third transistor and a second storage capacitor; the second noise reduction subcircuit includes: a fourth Transistor; the pull-down control sub-circuit includes: a fifth transistor; the pull-down sub-circuit includes: a sixth transistor and a seventh transistor; the first noise reduction sub-circuit includes: an eighth transistor; the first auxiliary control sub-circuit
  • the circuit includes: an eleventh transistor; the second auxiliary control sub-circuit includes: a twelfth transistor and a thirteenth transistor;
  • control pole and the first pole of the first transistor are connected to the signal input terminal, and the second pole is connected to the pull-up node; the pull-up node is at least simultaneously connected to the input sub-circuit, the output sub-circuit, and the second a noise reduction sub-circuit;
  • the control pole of the second transistor is connected to the reset signal terminal, the first pole is connected to the second reference level terminal, and the second pole is connected to the pull-up node;
  • the control pole of the third transistor is connected to the pull-up node, the first pole is connected to the clock signal terminal, and the second pole is connected to the signal output terminal;
  • One end of the second storage capacitor is connected to the pull-up node, and the other end is connected to the signal output end;
  • the control pole of the fourth transistor is connected to the pull-down node, the first pole is connected to the second reference level terminal, and the second pole is connected to the signal output terminal;
  • control electrode and the first electrode of the fifth transistor are connected to the first power supply voltage terminal, and the second electrode is connected to the pull-down node;
  • the control pole of the sixth transistor is connected to the pull-down control node, the first pole is connected to the first reference level terminal, and the second pole is connected to the pull-down node;
  • the control pole of the seventh transistor is connected to the signal input terminal, the first pole is connected to the first power supply voltage terminal, and the second pole is connected to the pull-down node;
  • the control pole of the eighth transistor is connected to the pull-down node, the first pole is connected to the first reference level terminal, and the second pole is connected to the pull-up node;
  • control pole and the first pole of the eleventh transistor are both connected to the signal input terminal, and the second pole is connected to the pull-down control node;
  • the control pole of the twelfth transistor is connected to the auxiliary control terminal, the first pole is connected to the first reference level terminal, and the second pole is connected to the pull-down control node; the control pole of the thirteenth transistor is connected to the pull-down node, and the first pole is connected to the pull-down control node.
  • One pole is connected to the first reference level terminal, and the second pole is connected to the pull-down control node.
  • an embodiment of the present disclosure provides a shift register unit, the shift register unit includes: an input subcircuit, a reset subcircuit, an output subcircuit, a pull-down control subcircuit, a pull-down subcircuit, a first noise reduction subcircuit circuit, a second noise reduction subcircuit, a first auxiliary control subcircuit, and a second auxiliary control subcircuit;
  • the pull-up node is at least simultaneously connected to the input subcircuit, the output subcircuit, and the first noise reduction subcircuit;
  • the pull-down node is at least simultaneously connected to the pull-down control sub-circuit, the pull-down sub-circuit and the first noise reduction sub-circuit;
  • the pull-down control node is at least simultaneously connected to the pull-down sub-circuit, the first auxiliary control sub-circuit and the a second auxiliary control subcircuit;
  • the input subcircuit includes: a first transistor; the reset subcircuit includes: a second transistor; the output subcircuit includes: a third transistor and a second storage capacitor; the second noise reduction subcircuit includes: a fourth Transistor; the pull-down control sub-circuit includes: a fifth transistor; the pull-down sub-circuit includes: a sixth transistor and a seventh transistor; the first noise reduction sub-circuit includes: an eighth transistor; the first auxiliary control sub-circuit The circuit includes: a fourteenth transistor; the second auxiliary control sub-circuit includes: a fifteenth transistor and a sixteenth transistor;
  • control pole and the first pole of the first transistor are connected to the signal input terminal, and the second pole is connected to the pull-up node; the pull-up node is at least simultaneously connected to the input sub-circuit, the output sub-circuit, and the second a noise reduction sub-circuit;
  • the control pole of the second transistor is connected to the reset signal terminal, the first pole is connected to the second reference level terminal, and the second pole is connected to the pull-up node;
  • the control pole of the third transistor is connected to the pull-up node, the first pole is connected to the clock signal terminal, and the second pole is connected to the signal output terminal;
  • One end of the second storage capacitor is connected to the pull-up node, and the other end is connected to the signal output end;
  • the control pole of the fourth transistor is connected to the pull-down node, the first pole is connected to the second reference level terminal, and the second pole is connected to the signal output terminal;
  • control electrode and the first electrode of the fifth transistor are connected to the first power supply voltage terminal, and the second electrode is connected to the pull-down node;
  • the control pole of the sixth transistor is connected to the pull-down control node, the first pole is connected to the first reference level terminal, and the second pole is connected to the pull-down node;
  • the control pole of the seventh transistor is connected to the signal input terminal, the first pole is connected to the first power supply voltage terminal, and the second pole is connected to the pull-down node;
  • the control pole of the eighth transistor is connected to the pull-down node, the first pole is connected to the first reference level terminal, and the second pole is connected to the pull-up node;
  • control electrode and the first electrode of the fourteenth transistor are connected to the first power supply voltage terminal, and the second electrode is connected to the pull-down control node;
  • the control pole of the fifteenth transistor is connected to the pull-down node, the first pole is connected to the first reference level terminal, and the second pole is connected to the pull-down control node; the control pole of the sixteenth transistor is connected to the auxiliary control terminal, and the control pole of the sixteenth transistor is connected to the auxiliary control terminal.
  • One pole is connected to the first reference level terminal, and the second pole is connected to the pull-down control node.
  • an embodiment of the present disclosure provides a gate drive circuit, the gate drive circuit includes a plurality of shift register units as described above that are cascaded to each other.
  • the signal input end of the current-stage shift register unit is connected to the signal output end of the upper-stage shift register unit;
  • the reset signal end of the shift register unit of the current stage is connected to the signal output end of the shift register unit of the next stage;
  • the auxiliary control terminal of the shift register unit of the current stage is connected to the signal output terminal of the shift register unit of the next stage.
  • an embodiment of the present disclosure provides a display device, the display device including the gate driving circuit provided above.
  • the embodiment of the present disclosure provides a driving method of a shift register unit, which is used to drive the shift register unit provided above, and the driving method of the shift register unit includes:
  • the pull-down node is the first reference level signal
  • use the first auxiliary control sub-circuit to write the third reference level signal into the pull-down control node, and control the pull-down sub-circuit to close, so as to control the first - the noise reduction sub-circuit is turned off;
  • the pull-down node is the first power supply voltage signal
  • use the second auxiliary control sub-circuit to write the first reference level signal into the pull-down control node, and control the pull-down sub-circuit to turn off, so as to control the first
  • a noise reduction sub-circuit performs noise reduction on the pull-up node through the second reference level signal.
  • Fig. 1 is a schematic diagram of the circuit structure of an exemplary shift register unit
  • FIG. 2 is a schematic diagram of a circuit structure of a shift register unit provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic circuit structure diagram of another shift register unit provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic circuit structure diagram of another shift register unit provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present disclosure.
  • the transistors used in the embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference in their source and drain functions. of. In the embodiments of the present disclosure, in order to distinguish the source and drain of the transistor, one of them is called the first pole, the other is called the second pole, and the gate is called the control pole. In addition, according to the characteristics of transistors, transistors can be divided into N-type and P-type. In the following embodiments, N-type transistors are used for illustration. The source of the N-type transistor, when the gate is input with a high level, the source and drain are turned on, and the P-type is opposite. It is conceivable that the realization by using P-type transistors can be easily thought of by those skilled in the art without any creative efforts, and thus also falls within the protection scope of the embodiments of the present invention.
  • the third reference level signal refers to a high-level signal, and both the first reference level signal and the second reference level signal refer to a low-level signal; correspondingly, the first The power supply voltage terminal refers to the signal terminal VDD; the first reference level terminal refers to the first low level terminal LVGL, the first reference level signal refers to the first low level signal; the second reference level terminal refers to the second low level terminal VGL, the second reference level signal refers to a second low level signal, wherein the voltage of the first low level signal is lower than the voltage of the second low level signal.
  • FIG. 1 is a schematic diagram of the circuit structure of an exemplary shift register unit.
  • the first noise reduction sub-circuit 105 the second noise reduction sub-circuit 106 and the reset sub-circuit 107 .
  • the input subcircuit 101 includes a first transistor M1;
  • the output subcircuit 102 includes a third transistor M3 and a second storage capacitor C2;
  • the pull-down control subcircuit 103 includes a transistor M5;
  • the pull-down subcircuit 104 includes a sixth transistor M6 and a seventh transistor M7;
  • the first noise reduction sub-circuit 105 includes an eighth transistor M8;
  • the second noise reduction sub-circuit 106 includes a fourth transistor M4;
  • the reset sub-circuit 107 includes a second transistor M2.
  • the gate and source of the first transistor M1 are connected to the signal input terminal Input, and the drain is connected to the pull-up node PU.
  • the gate of the third transistor M3 is connected to the pull-up node PU, the source is connected to the clock signal terminal CLK, and the gate is connected to the signal output terminal Output; one end of the second storage capacitor C2 is connected to the pull-up node PU, and the other end is connected to the signal output terminal Output.
  • the gate and source of the fifth transistor M5 are connected to the first power supply voltage terminal VDD, and the drain is connected to the pull-down node PD.
  • the gate of the sixth transistor M6 is connected to the pull-up node PU, the source is connected to the first reference level terminal LVGL, and the drain is connected to the pull-down node PD.
  • the gate of the seventh transistor M7 is connected to the signal input terminal Input, the source is connected to the first low-level terminal LVGL, and the drain is connected to the pull-down node PD.
  • the gate of the eighth transistor M8 is connected to the pull-down node PD, the source is connected to the first low-level terminal LVGL, and the drain is connected to the pull-up node PU.
  • the gate of the fourth transistor M4 is connected to the pull-down node PD, the source is connected to the second reference level terminal VGL, and the drain is connected to the signal output terminal Output.
  • the gate of the second transistor M2 is connected to the reset signal terminal Reset, the source is connected to the first reference level terminal LVGL, and the drain is connected to the pull-up node PU.
  • Pre-charging stage the signal input terminal Input inputs a high-level signal, and the first transistor M1 is turned on. At this time, the high-level signal input by the signal input terminal Input pulls up the potential of the pull-up node PU, and stores it through the second storage capacitor C2 .
  • Output stage the signal input terminal Input inputs a low-level signal, and the first transistor M1 is turned off.
  • the second storage capacitor C2 is charged in the pre-charging stage, the potential of the pull-up node PU is further pulled up; because the gate of the third transistor M3 is connected to the pull-up node PU, the third transistor M3 is turned on, and the output signal terminal Output outputs the clock signal of the clock signal terminal CLK as an output signal.
  • the clock signal is a high-level signal
  • the output signal is also a high-level signal.
  • Reset stage the signal input terminal Input inputs a low-level signal, and the first transistor M1 is turned off. At this time, the reset signal terminal Reset inputs a high-level signal, the second transistor M2 is turned on, the pull-up node PU is written into the first low-level signal of the first low-level terminal LVGL, and the potential of the pull-up node PU is reset.
  • Noise reduction stage the signal input terminal Input inputs a low-level signal, and the first transistor M1 is turned off.
  • the reset signal terminal Reset inputs a low-level signal, and the second transistor M2 is turned off.
  • the potential of the pull-up node PU remains the potential in the reset phase, which is the second low level potential.
  • the third transistor M3, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8 and the pull-down node PD maintain the working state of the reset stage, and the pull-up node PU and the signal output terminal Output are continuously lowered. noise.
  • the Vth (threshold voltage) of the thin film transistor is unstable, and the Vg of the eighth transistor M8 is prone to negative voltage. Partial volatility.
  • the pull-up node PU leaks electricity through the eighth transistor M8, which affects the working performance of the shift register unit circuit and causes the display panel driven by it to be prone to poor display.
  • embodiments of the present disclosure provide a shift register unit, a gate drive circuit, and a display device.
  • the shift register unit, gate drive circuit, and display device provided by the embodiments of the present disclosure will be The device is described in further detail.
  • FIG. 2 is a schematic circuit structure diagram of a shift register unit provided by an embodiment of the present disclosure.
  • the shift register unit provided by an embodiment of the present disclosure includes : input subcircuit 101, output subcircuit 102, pull-down control subcircuit 103, pull-down subcircuit 104, first noise reduction subcircuit 105, first auxiliary control subcircuit 108 and second auxiliary control subcircuit 109; input subcircuit 101 It is configured to respond to the input signal of the signal input terminal Input, and pull up the potential of the pull-up node PU through the input signal; the pull-up node PU is at least simultaneously connected to the input sub-circuit 101, the output sub-circuit 102, and the first noise reduction sub-circuit 105; the output subcircuit 102 is configured to output a signal through the signal output terminal Output in response to the potential of the pull-up node PU being pulled high; the pull-down control subcircuit 103
  • the pull-down node PD is the first low level signal.
  • the pull-down control node PC is a high-level signal
  • the pull-down sub-circuit 104 is continuously closed at this time, so that the potential of the pull-down node PD is continuously pulled down by the first low-level signal, thereby ensuring that the first noise reduction sub-circuit 105 is fully turn off, and the voltage of the first low-level signal and the second low-level signal can be used to control the first noise reduction sub-circuit 105 to be fully turned off, thereby preventing the first noise reduction sub-circuit 105 from affecting the pull-up node PU potential, that is, to avoid leakage of the pull-up node PU.
  • a second auxiliary control sub-circuit 109 is added to the shift register unit.
  • the pull-down node PD is a first power supply voltage signal, that is, the pull-down node PD is a high-level signal.
  • the pull-down control node PC is the first low-level signal, and the pull-down sub-circuit 104 remains turned off at this time, so that the pull-down node PD is continuously written into the first power supply voltage signal, thereby ensuring that the first noise reduction sub-circuit 105 is fully closed, and then can It is ensured that the first denoising sub-circuit 105 continuously denoises the pull-up node PU through the second low-level signal.
  • the potential of the pull-up node PU can reach the preset potential, avoiding the first noise reduction sub-circuit
  • the influence of 105 on the potential of the pull-up node PU can ensure the stability of the output signal of the signal output terminal Output, thereby ensuring a good display effect of the driven display panel.
  • the first auxiliary control subcircuit 108 includes: a first storage capacitor C1; one end of the first storage capacitor C1 is connected to the pull-down control node PC, and the other end is connected to the first power supply voltage terminal VDD;
  • the pull-down control node PC is connected to the input sub-circuit 101;
  • the second auxiliary control sub-circuit 109 includes: a ninth transistor 109 and a tenth transistor M10; the gate of the ninth transistor M9 is connected to the auxiliary control terminal PA, and the source is connected to the first low-level terminal
  • the drain of LVGL is connected to the pull-down control node PC; the gate of the tenth transistor M10 is connected to the pull-down node PD, the source is connected to the first low-level terminal LVGL, and the drain is connected to the pull-down control node PC.
  • the high-level signal stored in the first storage capacitor C1 can pull up the potential of the pull-down control node PC to control the pull-down sub-circuit 104 to remain closed. , so that the potential of the pull-down node PD is continuously pulled down by the first low-level signal, thereby ensuring that the first noise reduction sub-circuit 105 is fully turned off, thereby preventing the first noise reduction sub-circuit 105 from affecting the potential of the pull-up node PU, namely Avoid leakage of the pull-up node PU.
  • the ninth transistor M9 When the auxiliary control node PA writes a high-level signal, the ninth transistor M9 is turned on, the pull-up node PU is discharged to the second low-level potential, and the first storage capacitor C1 is discharged to the first low-level potential, so that the pull-down control
  • the node PC is at the first low level potential, the pull-down sub-circuit 104 is turned off, the pull-down node PD writes the first power supply voltage signal, that is, the pull-down node PD is at a high level, the tenth transistor M10 is continuously turned on, and the pull-down sub-circuit 104 is continuously turned off.
  • the pull-down node PD is continuously written with the first power supply voltage signal
  • the first noise reduction sub-circuit 105 is continuously closed, thereby performing continuous noise reduction on the pull-up node PU. It can be seen that in the shift register unit provided by the embodiment of the present disclosure, no matter whether the first noise reduction sub-circuit 105 is turned off or closed, the potential of the pull-up node PU can reach the preset potential, avoiding the first noise reduction sub-circuit
  • the influence of 105 on the potential of the pull-up node PU can ensure the stability of the output signal of the signal output terminal Output, thereby ensuring a good display effect of the driven display panel.
  • FIG. 3 is a schematic circuit structure diagram of another shift register unit provided by an embodiment of the present disclosure.
  • the first auxiliary control sub-circuit 108 includes: an eleventh transistor M11; The gate and source of a transistor M11 are both connected to the signal input terminal Input, and the drain is connected to the pull-down control node PC;
  • the second auxiliary control sub-circuit 109 includes: the twelfth transistor M12 and the thirteenth transistor M13; the twelfth transistor M12
  • the gate of the transistor M13 is connected to the auxiliary control terminal PA, the source is connected to the first low-level terminal LVGL, and the drain is connected to the pull-down control node PC; the gate of the thirteenth transistor M13 is connected to the pull-down node PD, and the source is connected to the first low-level terminal LVGL. Drain connection pulls down control node PC.
  • the pull-down sub-circuit 104 remains closed, so that the potential of the pull-down node PD is continuously pulled down by the first low-level signal, thereby ensuring that the first noise reduction sub-circuit
  • the circuit 105 is fully turned off, thereby preventing the first noise reduction sub-circuit 105 from affecting the potential of the pull-up node PU, that is, avoiding leakage of the pull-up node PU.
  • the auxiliary control node PA When the auxiliary control node PA writes a high level signal, the twelfth transistor M12 is turned on, the pull-down control node PC is pulled down to the first low level, the pull-down sub-circuit 104 is turned off, and the pull-down node PD is at the first low level, The thirteenth transistor M13 is turned on, the pull-down node PD is continuously written with the first low-level signal, the pull-down sub-circuit 104 is continuously turned off, the pull-down node PD is continuously written with the first power supply voltage signal, and the first noise reduction sub-circuit 105 is continuously Closed, so as to continuously reduce noise on the pull-up node PU.
  • the potential of the pull-up node PU can reach the preset potential, avoiding the first noise reduction sub-circuit
  • the influence of 105 on the potential of the pull-up node PU can ensure the stability of the output signal of the signal output terminal Output, thereby ensuring a good display effect of the driven display panel.
  • FIG. 4 is a schematic circuit structure diagram of another shift register unit provided by an embodiment of the present disclosure.
  • the first auxiliary control sub-circuit 108 includes: a fourteenth transistor M14; The gate and source of the fourth transistor M14 are connected to the first power supply voltage terminal VDD, and the drain is connected to the pull-down control node PC;
  • the second auxiliary control sub-circuit 109 includes: the fifteenth transistor M14 and the sixteenth transistor M15; the fifteenth transistor The gate of M15 is connected to the pull-down node PD, the source is connected to the first low-level terminal LVGL, and the drain is connected to the pull-down control node PC; the gate of the sixteenth transistor M16 is connected to the auxiliary control terminal PA, and the source is connected to the first low-level terminal LVGL , the drain connection pulls down the control node PC.
  • the pull-down sub-circuit 104 remains closed, so that the potential of the pull-down node PD is continuously pulled down by the first low-level signal, thereby ensuring that the first noise reduction sub-circuit
  • the circuit 105 is fully turned off, thereby preventing the first noise reduction sub-circuit 105 from affecting the potential of the pull-up node PU, that is, avoiding leakage of the pull-up node PU.
  • the sixteenth transistor M16 is turned on, the pull-down control node PC is pulled down to the first low level, the pull-down sub-circuit 104 is turned off, and the pull-down node PD is at the first low level,
  • the fifteenth transistor M15 is turned on, the pull-down node PD is continuously written with the first low-level signal, the pull-down sub-circuit 104 is continuously turned off, the pull-down node PD is continuously written with the first power supply voltage signal, and the first noise reduction sub-circuit 105 is continuously Closed, so as to continuously reduce noise on the pull-up node PU.
  • the potential of the pull-up node PU can reach the preset potential, avoiding the first noise reduction sub-circuit
  • the influence of 105 on the potential of the pull-up node PU can ensure the stability of the output signal of the signal output terminal Output, thereby ensuring a good display effect of the driven display panel.
  • the shift register unit further includes: a second noise reduction sub-circuit 106; the second noise reduction sub-circuit 106 is configured to respond to the pull-down node PD Potential, the potential of the signal output terminal Output is noise-reduced by using the second low-level signal.
  • the second noise reduction sub-circuit 106 includes: a fourth transistor M4; the gate of the fourth transistor M4 is connected to the pull-down node PD, the source is connected to the second low level terminal VGL, and the drain is connected to the signal output terminal Output.
  • the pull-down node PD is at a high level potential, and the fourth transistor M4 is turned on. At this time, the noise reduction of the signal output terminal Output can be performed through the second low level signal.
  • the shift register unit further includes: a reset subcircuit 107; the reset subcircuit 107 is configured to respond to the reset signal, through the second low level signal pair The potential of the node PU is pulled up to reset.
  • the reset sub-circuit 107 includes: a second transistor M2; the gate of the second transistor M2 is connected to the reset signal terminal Reset, the source is connected to the second low level terminal VGL, and the drain is connected to the pull-up node PU.
  • the reset signal terminal Reset inputs a high-level signal, and the second transistor M2 is turned on. At this time, the pull-up node PU can be reset through the second low-level signal.
  • the second noise reduction sub-circuit 106 and the reset sub-circuit 107 can be set at the same time, or only one of the second noise reduction sub-circuit 106 and the reset sub-circuit 107 can be set, for example
  • the circuits shown in FIG. 2 and FIG. 4 are provided with the second noise reduction sub-circuit 106 and the reset sub-circuit 107 , while the circuit shown in FIG. 3 is only provided with the second noise reduction sub-circuit 106 .
  • the input sub-circuit 101 includes: a first transistor M1; the gate and source of the first transistor M1 are connected to the signal input terminal Input, and the drain is connected to the pull-up Node PUs.
  • a high-level signal is written into the signal input terminal Input, and the first transistor M1 is turned on, so that the pull-up node can be precharged by the high-level signal written into the signal input terminal Input.
  • the output subcircuit 102 includes: a third transistor M3 and a second storage capacitor C2; the gate of the third transistor M3 is connected to the pull-up node PU, and the source is It is connected to the clock signal terminal CLK, and the drain is connected to the signal output terminal Output; one end of the second storage capacitor C2 is connected to the pull-up node PU, and the other end is connected to the signal output terminal Output.
  • the potential of the pull-up node PU is high level
  • the third transistor M3 is turned on, and the clock signal of the clock signal terminal CLK is output to the output signal terminal Output, and the clock signal of the clock signal terminal CLK is high level, thus When the potential of the signal output terminal Output is pulled high, that is, a high-level signal is output.
  • the pull-down control subcircuit 103 includes: a fifth transistor M5; the gate and source of the fifth transistor M5 are connected to the first power supply voltage terminal VDD, and the drain is Connect the drop-down node PD.
  • the gate and source of the fifth transistor M5 are connected to the first power supply voltage terminal VDD, that is, the first power supply voltage signal is written into it. At this time, the fifth transistor M5 is turned on, and the potential of the pull-down node PD is the potential of the first power supply voltage. , that is, the potential of the pull-down node PD is at a high level.
  • the pull-down sub-circuit includes: a sixth transistor M6 and a seventh transistor M7; the gate of the sixth transistor M6 is connected to the pull-down control node PC, and the source is connected to the first reference voltage
  • the drain of the flat terminal LVGL is connected to the pull-down node PD; the gate of the seventh transistor M7 is connected to the signal input terminal Input, the source is connected to the first power supply voltage terminal VDD, and the drain is connected to the pull-down node PD.
  • the seventh transistor M7 When the signal input terminal Input writes a high-level signal, the seventh transistor M7 is turned on, the pull-down node PD is written with the first low-level signal, and at the same time, the auxiliary control terminal is written with a high-level signal, the sixth transistor M6 is turned on, and the pull-down node PD is written into a high-level signal.
  • the first level signal can be continuously written in, ensuring that the potential of the pull-down node PD is continuously pulled down.
  • the first noise reduction sub-circuit 105 includes: an eighth transistor M8; the gate of the eighth transistor M8 is connected to the pull-down node PD, and the source is connected to the second lower
  • the drain of the level terminal VGL is connected to the pull-up node PU.
  • the pull-down node PD is at a high-level potential, and the eighth transistor M8 is turned on. At this time, the pull-down node PU can be noise-reduced through the second low-level signal.
  • FIG. 5 is a schematic structural diagram of the gate drive circuit provided by an embodiment of the present disclosure.
  • the gate drive circuit includes A plurality of shift register units cascaded with each other; wherein, the signal input terminal Input of the shift register unit of this stage is connected to the signal output terminal Output of the shift register unit of the upper stage; the reset signal terminal Reset of the shift register unit of the present stage The signal output terminal Output of the shift register unit of the next stage is connected; the auxiliary control terminal PA of the shift register unit of the present stage is connected with the signal output terminal Output of the shift register unit of the next stage.
  • the gate drive circuit provided by the embodiments of the present disclosure can output scan signals step by step to drive the display panel to scan row by row to realize the display function. Since the first auxiliary control sub-circuit 108 is added to the shift register unit, when the pull-up node PU is a high-level signal, the pull-down node PD is a first low-level signal, and the pull-down control node PC is a high-level signal At this time, the pull-down sub-circuit 104 is continuously closed, so that the potential of the pull-down node PD is continuously pulled down by the first low-level signal, thereby ensuring that the first noise reduction sub-circuit 105 is fully turned off, and can pass the first low-level signal and The voltage of the second low-level signal is used to control the first noise reduction sub-circuit 105 to be fully turned off, thereby preventing the first noise reduction sub-circuit 105 from affecting the potential of the pull-up node PU, that is, avoiding leakage of the pull-up node PU.
  • a second auxiliary control sub-circuit 109 is added to the shift register unit.
  • the pull-up node PU is a low-level signal
  • the pull-down node PD is a first power supply voltage signal, that is, the pull-down node PD is a high-level signal.
  • the pull-down control node PC is the first low-level signal
  • the pull-down sub-circuit 104 remains turned off at this time, so that the pull-down node PD is continuously written into the first power supply voltage signal, thereby ensuring that the first noise reduction sub-circuit 105 is fully closed, and then can It is ensured that the first denoising sub-circuit 105 continuously denoises the pull-up node PU through the second low-level signal.
  • the potential of the pull-up node PU can reach the preset potential, avoiding the first noise reduction sub-circuit
  • the influence of 105 on the potential of the pull-up node PU can ensure the stability of the output signal of the signal output terminal Output, thereby ensuring a good display effect of the driven display panel.
  • An embodiment of the present disclosure also provides a display device, which includes the gate drive circuit provided in any one of the above embodiments.
  • the display device can be a display device such as a large-size TV, a monitor, and a car navigation. Its implementation principle and The technical effect is the same as the implementation principle and technical effect of the gate drive circuit provided by any of the above embodiments, and will not be repeated here.
  • An embodiment of the present disclosure also provides a driving method for a shift register unit, which drives the shift register unit provided in any of the above embodiments, and the driving method for the shift register unit includes:
  • the pull-down node is the first reference level signal
  • use the first auxiliary control subcircuit to write the third reference level signal into the pull-down control node, and control the pull-down subcircuit to close, so as to control the first noise reduction subcircuit to turn off;
  • the pull-down node is the first power supply voltage signal
  • use the second auxiliary control sub-circuit to write the first reference level signal into the pull-down control node, and control the pull-down sub-circuit to turn off, so as to control the first noise reduction sub-circuit through the second
  • the reference level signal denoises the pull-up node.
  • the high-level signal stored in the first storage capacitor C1 can pull up the pull-down control node PC.
  • the ninth transistor M9 When the auxiliary control node PA writes a high-level signal, the ninth transistor M9 is turned on, the pull-up node PU is discharged to the second low-level potential, and the first storage capacitor C1 is discharged to the first low-level potential, so that the pull-down control
  • the node PC is at the first low level potential
  • the pull-down sub-circuit 104 is turned off, the pull-down node PD writes the first power supply voltage signal, that is, the pull-down node PD is at a high level
  • the tenth transistor M10 is continuously turned on, and the pull-down sub-circuit 104 is continuously turned off. is off, the pull-down node PD is continuously written with the first power supply voltage signal, and the first noise reduction sub-circuit 105 is continuously closed, thereby performing continuous noise reduction on the pull-up node PU.
  • the pull-down sub-circuit 104 remains closed, so that the potential of the pull-down node PD is sustained by the first low-level signal. pull down, so as to ensure that the first noise reduction sub-circuit 105 is fully turned off, thereby preventing the first noise reduction sub-circuit 105 from affecting the potential of the pull-up node PU, that is, avoiding leakage of the pull-up node PU.
  • the auxiliary control node PA When the auxiliary control node PA writes a high level signal, the twelfth transistor M12 is turned on, the pull-down control node PC is pulled down to the first low level, the pull-down sub-circuit 104 is turned off, and the pull-down node PD is at the first low level, The thirteenth transistor M13 is turned on, the pull-down node PD is continuously written with the first low-level signal, the pull-down sub-circuit 104 is continuously turned off, the pull-down node PD is continuously written with the first power supply voltage signal, and the first noise reduction sub-circuit 105 is continuously Closed, so as to continuously reduce noise on the pull-up node PU.
  • the pull-down sub-circuit 104 remains closed, so that the potential of the pull-down node PD is maintained by the first low-level signal. pull down, so as to ensure that the first noise reduction sub-circuit 105 is fully turned off, thereby preventing the first noise reduction sub-circuit 105 from affecting the potential of the pull-up node PU, that is, avoiding leakage of the pull-up node PU.
  • the sixteenth transistor M16 is turned on, the pull-down control node PC is pulled down to the first low level, the pull-down sub-circuit 104 is turned off, and the pull-down node PD is at the first low level,
  • the fifteenth transistor M15 is turned on, the pull-down node PD is continuously written with the first low-level signal, the pull-down sub-circuit 104 is continuously turned off, the pull-down node PD is continuously written with the first power supply voltage signal, and the first noise reduction sub-circuit 105 is continuously Closed, so as to continuously reduce noise on the pull-up node PU.
  • the driving method of the shift register unit provided by the embodiment of the present disclosure can make the potential of the pull-up node PU reach the preset potential regardless of whether the first noise reduction sub-circuit 105 is turned off or closed, avoiding the first drop
  • the influence of the noise circuit 105 on the potential of the pull-up node PU can ensure the stability of the output signal of the signal output terminal Output, thereby ensuring a good display effect of the driven display panel.

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Abstract

一种移位寄存器单元、栅极驱动电路及显示装置，属于显示技术领域，其可解决现有的移位寄存器单元中的薄膜晶体管的阈值电压不稳定，容易产生漏电流的问题。移位寄存器单元包括：输入子电路(101)、输出子电路(102)、下拉控制子电路(103)、下拉子电路(104)、第一降噪子电路(105)、第一辅助控制子电路(108)和第二辅助控制子电路(109)；第一辅助控制子电路(108)被配置为在下拉节点(PD)为第一参考电平信号时，将第三参考电平信号写入下拉控制节点(PC)，并控制下拉子电路(104)闭合，以控制第一降噪子电路(105)关断；第二辅助控制子电路(109)被配置为在下拉节点(PD)为第一电源电压信号时，将第一参考电平信号写入下拉控制节点(PC)，并控制下拉子电路(104)关断，以控制第一降噪子电路(105)通过第二参考电平信号对上拉节点(PU)进行降噪。

Description

移位寄存器单元、栅极驱动电路及显示装置 技术领域
本公开属于显示技术领域，具体涉及一种移位寄存器单元、栅极驱动电路及显示装置。
背景技术
GOA(Gate Driver on Array，集成栅极驱动电路)技术可以将栅极驱动电路集成在显示面板的阵列基板上，相比传统的COF(Chip On Film，覆晶薄膜)或COG(Chip On Glass，芯片直接固定在玻璃上)工艺，其不仅节约了成本，而且可以做到面板两边对称的美观设计，同时也可省去栅极驱动电路的Bonding(压焊)区域以及外围布线空间，从而实现了显示装置窄边框的设计，提高了显示装置的产能和良率。
GOA电路中所用的薄膜晶体管其有源层材料可选用a-Si(非晶硅)、LTPS(低温多晶硅)、金属氧化物半导体，如典型的材料IGZO(Indium Gallium Zinc Oxide，氧化铟镓锌)等。大尺寸显示屏通常选用金属氧化物晶体管(如有源层材料为IGZO的薄膜晶体管)作为GOA电路中的薄膜晶体管，但当显示器尺寸以及分辨率进一步增大时，需要选用具有更高迁移率的氧化物材料薄膜晶体管应用于GOA电路。当选用更高迁移率的薄膜晶体管时，薄膜晶体管的阈值电压不稳定，易发生负偏波动，造成薄膜晶体管产生漏电流，而影响GOA电路的工作性能，造成所驱动的显示面板容易发生显示不良问题。
发明内容
本公开旨在至少解决现有技术中存在的技术问题之一，提供一种移位寄 存器单元、栅极驱动电路及显示装置。
第一方面，本公开实施例提供一种移位寄存器单元，所述移位寄存器单元包括：输入子电路、输出子电路、下拉控制子电路、下拉子电路、第一降噪子电路、第一辅助控制子电路和第二辅助控制子电路；
所述输入子电路被配置为响应于信号输入端的输入信号，通过所述输入信号对上拉节点的电位进行拉高；所述上拉节点至少同时连接所述输入子电路、所述输出子电路、所述第一降噪子电路；
所述输出子电路被配置为响应于所述上拉节点被拉高后的电位，通过信号输出端输出信号；
所述下拉控制子电路被配置为响应于第一电源电压信号，利用所述第一电源电压信号控制下拉节点的电位；所述下拉节点至少同时连接所述下拉控制子电路、所述下拉子电路和所述第一降噪子电路；
所述下拉子电路被配置为响应于所述下拉控制节点的电位，通过第一参考电平信号下拉所述下拉节点的电位；所述下拉控制节点至少同时连接所述下拉子电路、所述第一辅助控制子电路和所述第二辅助控制子电路；
所述第一降噪子电路被配置为响应于所述下拉节点的电位，通过第二参考电平信号对所述上拉节点的电位进行降噪；
所述第一辅助控制子电路被配置为在所述下拉节点为第一参考电平信号时，将第三参考电平信号写入所述下拉控制节点，并控制所述下拉子电路闭合，以控制所述第一降噪子电路关断；
所述第二辅助控制子电路被配置为在所述下拉节点为第一电源电压信号时，将第一参考电平信号写入所述下拉控制节点，并控制所述下拉子电路关断，以控制所述第一降噪子电路通过所述第二参考电平信号对所述上拉节点进行降噪。
可选地，所述第一辅助控制子电路包括：第一存储电容；所述第一存储 电容的一端连接所述下拉控制节点，另一端连接所述第一电源电压端；所述下拉控制节点连接所述输入子电路；
所述第二辅助控制子电路包括：第九晶体管和第十晶体管；所述第九晶体管的控制极连接辅助控制端，第一极连接第一参考电平端，第二极连接所述下拉控制节点；所述第十晶体管的控制极连接所述下拉节点，第一极连接所述第一参考电平端，第二极连接所述下拉控制节点。
可选地，所述第一辅助控制子电路包括：第十一晶体管；所述第十一晶体管的控制极和第一极均连接信号输入端，第二极连接所述下拉控制节点；
所述第二辅助控制子电路包括：第十二晶体管和第十三晶体管；所述第十二晶体管的控制极连接辅助控制端，第一极连接第一参考电平端，第二极连接所述下拉控制节点；所述第十三晶体管的控制极连接所述下拉节点，第一极连接所述第一参考电平端，第二极连接所述下拉控制节点。
可选地，所述第一辅助控制子电路包括：第十四晶体管；所述第十四晶体管的控制极和第一极连接所述第一电源电压端，第二极连接所述下拉控制节点；
所述第二辅助控制子电路包括：第十五晶体管和第十六晶体管；所述第十五晶体管的控制极连接所述下拉节点，第一极连接第一参考电平端，第二极连接所述下拉控制节点；所述第十六晶体管的控制极连接辅助控制端，第一极连接第一参考电平端，第二极连接所述下拉控制节点。
可选地，所述移位寄存器单元还包括：第二降噪子电路；
所述第二降噪子电路被配置为响应于所述下拉节点的电位，通过第二参考电平信号对信号输出端的电位进行降噪。
可选地，所述第二降噪子电路包括：第四晶体管；
所述第四晶体管的控制极连接所述下拉节点，第一极连接第二参考电平端，第二极连接信号输出端。
可选地，所述移位寄存器单元还包括：复位子电路；
所述复位子电路被配置为响应于复位信号，通过第二参考电平信号对所述上拉节点的电位进行复位。
可选地，所述复位子电路包括：第二晶体管；
所述第二晶体管的控制极连接复位信号端，第一极连接第二参考电平端，第二极连接所述上拉节点。
可选地，所述输入子电路包括：第一晶体管；
所述第一晶体管的控制极和第一极连接信号输入端，第二极连接所述上拉节点。
可选地，所述输出子电路包括：第三晶体管和第二存储电容；
所述第三晶体管的控制极连接所述上拉节点，第一极连接时钟信号端，第二极连接信号输出端；
所述第二存储电容的一端连接所述上拉节点，另一端连接信号输出端。
可选地，所述下拉控制子电路包括：第五晶体管；
所述第五晶体管的控制极和第一极连接第一电源电压端，第二极连接所述下拉节点。
可选地，所述下拉子电路包括：第六晶体管和第七晶体管；
所述第六晶体管的控制极连接所述下拉控制节点，第一极连接第一参考电平端，第二极连接所述下拉节点；
所述第七晶体管的控制极连接信号输入端，第一极连接第一电源电压端，第二极连接所述下拉节点。
可选地，所述第一降噪子电路包括：第八晶体管；
所述第八晶体管的控制极连接所述下拉节点，第一极连接第一参考电平端，第二极连接所述上拉节点。
第二方面，本公开实施例提供一种移位寄存器单元，所述移位寄存器单 元包括：输入子电路、复位子电路、输出子电路、下拉控制子电路、下拉子电路、第一降噪子电路、第二降噪子电路、第一辅助控制子电路和第二辅助控制子电路；上拉节点至少同时连接所述输入子电路、所述输出子电路、所述第一降噪子电路；下拉节点至少同时连接所述下拉控制子电路、所述下拉子电路和所述第一降噪子电路；下拉控制节点至少同时连接所述下拉子电路、所述第一辅助控制子电路和所述第二辅助控制子电路；
所述输入子电路包括：第一晶体管；所述复位子电路包括：第二晶体管；所述输出子电路包括：第三晶体管和第二存储电容；所述第二降噪子电路包括：第四晶体管；所述下拉控制子电路包括：第五晶体管；所述下拉子电路包括：第六晶体管和第七晶体管；所述第一降噪子电路包括：第八晶体管；所述第一辅助控制子电路包括：第一存储电容；所述第二辅助控制子电路包括：第九晶体管和第十晶体管；
所述第一晶体管的控制极和第一极连接信号输入端，第二极连接所述上拉节点；所述上拉节点至少同时连接所述输入子电路、所述输出子电路、所述第一降噪子电路；
所述第二晶体管的控制极连接复位信号端，第一极连接第二参考电平端，第二极连接所述上拉节点；
所述第三晶体管的控制极连接所述上拉节点，第一极连接时钟信号端，第二极连接信号输出端；
所述第二存储电容的一端连接所述上拉节点，另一端连接信号输出端；
所述第四晶体管的控制极连接所述下拉节点，第一极连接第二参考电平端，第二极连接信号输出端；
所述第五晶体管的控制极和第一极连接第一电源电压端，第二极连接所述下拉节点；
所述第六晶体管的控制极连接所述下拉控制节点，第一极连接第一参考 电平端，第二极连接所述下拉节点；
所述第七晶体管的控制极连接信号输入端，第一极连接第一电源电压端，第二极连接所述下拉节点；
所述第八晶体管的控制极连接所述下拉节点，第一极连接第一参考电平端，第二极连接所述上拉节点；
所述第一存储电容的一端连接所述下拉控制节点，另一端连接所述第一电源电压端；所述下拉控制节点连接所述第一晶体管的第二极；
所述第九晶体管的控制极连接辅助控制端，第一极连接第一参考电平端，第二极连接所述下拉控制节点；所述第十晶体管的控制极连接所述下拉节点，第一极连接所述第一参考电平端，第二极连接所述下拉控制节点。
第三方面，本公开实施例提供一种移位寄存器单元，所述移位寄存器单元包括：输入子电路、复位子电路、输出子电路、下拉控制子电路、下拉子电路、第一降噪子电路、第二降噪子电路、第一辅助控制子电路和第二辅助控制子电路；上拉节点至少同时连接所述输入子电路、所述输出子电路、所述第一降噪子电路；下拉节点至少同时连接所述下拉控制子电路、所述下拉子电路和所述第一降噪子电路；下拉控制节点至少同时连接所述下拉子电路、所述第一辅助控制子电路和所述第二辅助控制子电路；
所述输入子电路包括：第一晶体管；所述复位子电路包括：第二晶体管；所述输出子电路包括：第三晶体管和第二存储电容；所述第二降噪子电路包括：第四晶体管；所述下拉控制子电路包括：第五晶体管；所述下拉子电路包括：第六晶体管和第七晶体管；所述第一降噪子电路包括：第八晶体管；所述第一辅助控制子电路包括：第十一晶体管；所述第二辅助控制子电路包括：第十二晶体管和第十三晶体管；
所述第一晶体管的控制极和第一极连接信号输入端，第二极连接所述上拉节点；所述上拉节点至少同时连接所述输入子电路、所述输出子电路、所 述第一降噪子电路；
所述第二晶体管的控制极连接复位信号端，第一极连接第二参考电平端，第二极连接所述上拉节点；
所述第三晶体管的控制极连接所述上拉节点，第一极连接时钟信号端，第二极连接信号输出端；
所述第二存储电容的一端连接所述上拉节点，另一端连接信号输出端；
所述第四晶体管的控制极连接所述下拉节点，第一极连接第二参考电平端，第二极连接信号输出端；
所述第五晶体管的控制极和第一极连接第一电源电压端，第二极连接所述下拉节点；
所述第六晶体管的控制极连接所述下拉控制节点，第一极连接第一参考电平端，第二极连接所述下拉节点；
所述第七晶体管的控制极连接信号输入端，第一极连接第一电源电压端，第二极连接所述下拉节点；
所述第八晶体管的控制极连接所述下拉节点，第一极连接第一参考电平端，第二极连接所述上拉节点；
所述第十一晶体管的控制极和第一极均连接信号输入端，第二极连接所述下拉控制节点；
所述第十二晶体管的控制极连接辅助控制端，第一极连接第一参考电平端，第二极连接所述下拉控制节点；所述第十三晶体管的控制极连接所述下拉节点，第一极连接所述第一参考电平端，第二极连接所述下拉控制节点。
第四方面，本公开实施例提供一种移位寄存器单元，所述移位寄存器单元包括：输入子电路、复位子电路、输出子电路、下拉控制子电路、下拉子电路、第一降噪子电路、第二降噪子电路、第一辅助控制子电路和第二辅助控制子电路；上拉节点至少同时连接所述输入子电路、所述输出子电路、所 述第一降噪子电路；下拉节点至少同时连接所述下拉控制子电路、所述下拉子电路和所述第一降噪子电路；下拉控制节点至少同时连接所述下拉子电路、所述第一辅助控制子电路和所述第二辅助控制子电路；
所述输入子电路包括：第一晶体管；所述复位子电路包括：第二晶体管；所述输出子电路包括：第三晶体管和第二存储电容；所述第二降噪子电路包括：第四晶体管；所述下拉控制子电路包括：第五晶体管；所述下拉子电路包括：第六晶体管和第七晶体管；所述第一降噪子电路包括：第八晶体管；所述第一辅助控制子电路包括：第十四晶体管；所述第二辅助控制子电路包括：第十五晶体管和第十六晶体管；
所述第一晶体管的控制极和第一极连接信号输入端，第二极连接所述上拉节点；所述上拉节点至少同时连接所述输入子电路、所述输出子电路、所述第一降噪子电路；
所述第二晶体管的控制极连接复位信号端，第一极连接第二参考电平端，第二极连接所述上拉节点；
所述第三晶体管的控制极连接所述上拉节点，第一极连接时钟信号端，第二极连接信号输出端；
所述第二存储电容的一端连接所述上拉节点，另一端连接信号输出端；
所述第四晶体管的控制极连接所述下拉节点，第一极连接第二参考电平端，第二极连接信号输出端；
所述第五晶体管的控制极和第一极连接第一电源电压端，第二极连接所述下拉节点；
所述第六晶体管的控制极连接所述下拉控制节点，第一极连接第一参考电平端，第二极连接所述下拉节点；
所述第七晶体管的控制极连接信号输入端，第一极连接第一电源电压端，第二极连接所述下拉节点；
所述第八晶体管的控制极连接所述下拉节点，第一极连接第一参考电平端，第二极连接所述上拉节点；
所述第十四晶体管的控制极和第一极连接所述第一电源电压端，第二极连接所述下拉控制节点；
所述第十五晶体管的控制极连接所述下拉节点，第一极连接第一参考电平端，第二极连接所述下拉控制节点；所述第十六晶体管的控制极连接辅助控制端，第一极连接第一参考电平端，第二极连接所述下拉控制节点。
第五方面，本公开实施例提供一种栅极驱动电路，所述栅极驱动电路包括多个相互级联的如上述的移位寄存器单元。
可选地，本级移位寄存器单元的信号输入端连接上一级移位寄存器单元的信号输出端；
本级移位寄存器单元的复位信号端连接下一级移位寄存器单元的信号输出端；
本级移位寄存器单元的辅助控制端连接下一级移位寄存器单元的信号输出端。
第六方面，本公开实施例提供一种显示装置，所述显示装置包括如上述提供的栅极驱动电路。
第七方面，本公开实施例提供一种移位寄存器单元的驱动方法，用于驱动如上述提供的移位寄存器单元，所述移位寄存器单元的驱动方法包括：
在所述下拉节点为第一参考电平信号时，利用第一辅助控制子电路将第三参考电平信号写入所述下拉控制节点，并控制所述下拉子电路闭合，以控制所述第一降噪子电路关断；
在所述下拉节点为第一电源电压信号时，利用第二辅助控制子电路将第一参考电平信号写入所述下拉控制节点，并控制所述下拉子电路关断，以控制所述第一降噪子电路通过所述第二参考电平信号对所述上拉节点进行降 噪。
附图说明
图1为一种示例性的移位寄存器单元的电路结构示意图；
图2为本公开实施例提供的一种移位寄存器单元的电路结构示意图；
图3为本公开实施例提供的另一种移位寄存器单元的电路结构示意图；
图4为本公开实施例提供的又一种移位寄存器单元的电路结构示意图；
图5为本公开实施例提供的栅极驱动电路的结构示意图。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开实施例中所采用的晶体管可以为薄膜晶体管或场效应管或其他特性的相同器件，由于采用的晶体管的源极和漏极是对称的，所以其源极、漏极功能上是没有区别的。在本公开实施例中，为区分晶体管的源极和漏极，将其中一极称为第一极，另一极称为第二极，栅极称为控制极。此外按照晶 体管的特性区分可以将晶体管分为N型和P型，以下实施例中是以N型晶体管进行说明的，当采用N型晶体管时，第一极为N型晶体管的漏极，第二极为N型晶体管的源极，栅极输入高电平时，源漏极导通，P型相反。可以想到的是采用P型晶体管实现是本领域技术人员可以在没有付出创造性劳动前提下轻易想到的，因此也是在本发明实施例的保护范围内的。
在此需要说明的是，本实施例中第三参考电平信号是指高电平信号，第一参考电平信号和第二参考电平信号均是指低电平信号；相应的，第一电源电压端是指信号端VDD；第一参考电平端是指第一低电平端LVGL，第一参考电平信号是指第一低电平信号；第二参考电平端是指第二低电平端VGL，第二参考电平信号是指第二低电平信号，其中，第一低电平信号的电压低于第二低电平信号的电压。
图1为一种示例性的移位寄存器单元的电路结构示意图，如图1所示，该移位寄存器单元包括输入子电路101、输出子电路102、下拉控制子电路103、下拉子电路104、第一降噪子电路105、第二降噪子电路106和复位子电路107。其中，输入子电路101包括第一晶体管M1；输出子电路102包括第三晶体管M3和第二存储电容C2；下拉控制子电路103包括晶体管M5；下拉子电路104包括第六晶体管M6和第七晶体管M7；第一降噪子电路105包括第八晶体管M8；第二降噪子电路106包括第四晶体管M4；复位子电路107包括第二晶体管M2。
具体的，第一晶体管M1的栅极和源极连接信号输入端Input，漏极连接上拉节点PU。第三晶体管M3的栅极连接上拉节点PU，源极连接时钟信号端CLK，栅极连接信号输出端Output；第二存储电容C2的一端连接上拉节点PU，另一端连接信号输出端Output。第五晶体管M5的栅极和源极连接第一电源电压端VDD，漏极连接下拉节点PD。第六晶体管M6的栅极连接上拉节点PU，源极连接第一参考电平端LVGL，漏极连接下拉节点PD。第 七晶体管M7的栅极连接信号输入端Input，源极连接第一低电平端LVGL，漏极连接下拉节点PD。第八晶体管M8的栅极连接下拉节点PD，源极连接第一低电平端LVGL，漏极连接上拉节点PU。第四晶体管M4的栅极连接下拉节点PD，源极连接第二参考电平端VGL，漏极连接信号输出端Output。第二晶体管M2的栅极连接复位信号端Reset，源极连接第一参考电平端LVGL，漏极连接上拉节点PU。
对于图1所示的移位寄存器单元，其具体的工作过程可以包括如下阶段：
预充阶段：信号输入端Input输入高电平信号，第一晶体管M1打开，此时信号输入端Input输入的高电平信号拉高上拉节点PU的电位，并通过第二存储电容C2进行存储。
输出阶段：信号输入端Input输入低电平信号，第一晶体管M1关闭。此时由于在预充阶段第二存储电容C2被充电，上拉节点PU的电位被进一步拉高；由于第三晶体管M3的栅极连接上拉节点PU，第三晶体管M3被打开，输出信号端Output将时钟信号端CLK的时钟信号作为输出信号输出。此时时钟信号为高电平信号，输出信号也为高电平信号。
复位阶段：信号输入端Input输入低电平信号，第一晶体管M1关闭。此时复位信号端Reset输入高电平信号，第二晶体管M2被打开，上拉节点PU被写入第一低电平端LVGL的第一低电平信号，上拉节点PU的电位被复位。
降噪阶段：信号输入端Input输入低电平信号，第一晶体管M1关闭。复位信号端Reset输入低电平信号，第二晶体管M2被关闭。此时上拉节点PU的电位保持复位阶段的电位，为第二低电平电位。此时，第三晶体管M3、第四晶体管M4、第六晶体管M6、第七晶体管M7、第八晶体管M8和下拉节点PD保持复位阶段的工作状态，上拉节点PU和信号输出端Output被持续降噪。
在大尺寸及高分辨率的显示器中，当选用了具有更高迁移率的氧化物薄膜晶体管时，薄膜晶体管的Vth(阈值电压)不稳定，第八晶体管M8的Vg第八晶体管M8易发生负偏波动。当第八晶体管M8发生负偏波动时，造成上拉节点PU通过第八晶体管M8发生漏电，而影响移位寄存器单元电路的工作性能，造成所驱动的显示面板容易发生显示不良问题。
为了至少解决上述的技术问题之一，本公开实施例提供了一种移位寄存器单元、栅极驱动电路及显示装置，下面将对本公开实施例提供的移位寄存器单元、栅极驱动电路及显示装置进行进一步详细描述。
本公开实施例提供了一种移位寄存器单元，图2为本公开实施例提供的一种移位寄存器单元的电路结构示意图，如图2所示，本公开实施例提供的移位寄存器单元包括：输入子电路101、输出子电路102、下拉控制子电路103、下拉子电路104、第一降噪子电路105、第一辅助控制子电路108和第二辅助控制子电路109；输入子电路101被配置为响应于信号输入端Input的输入信号，通过输入信号对上拉节点PU的电位进行拉高；上拉节点PU至少同时连接输入子电路101、输出子电路102、第一降噪子电路105；输出子电路102被配置为响应于上拉节点PU被拉高后的电位，通过信号输出端Output输出信号；下拉控制子电路103被配置为响应于第一电源电压信号，利用第一电源电压信号控制下拉节点PD的电位；下拉节点PD至少同时连接下拉控制子电路103、下拉子电路104和第一降噪子电路105；下拉子电路104被配置为响应于下拉控制节点PC的电位，通过第一低电平信号下拉下拉节点PD的电位；下拉控制节点PC至少同时连接下拉子电路104、第一辅助控制子电路108和第二辅助控制子电路109；第一降噪子电路105被配置为响应于下拉节点PD的电位，通过第二低电平信号对上拉节点PU的电位进行降噪；第一辅助控制子电路108被配置为在下拉节点PD为第一低电平信号时，将高电平信号写入下拉控制节点PC，并控制下拉子电路104闭 合，以控制第一降噪子电路105关断；第二辅助控制子电路109被配置为在下拉节点PD为第一电源电压信号时，将第一低电平信号写入下拉控制节点PC，并控制下拉子电路104关断，以控制第一降噪子电路105通过第二低电平信号对上拉节点PU进行降噪。
本公开实施例提供的移位寄存器单元中，由于在本移位寄存器单元中增加了第一辅助控制子电路108，可以在上拉节点PU为高电平信号时，下拉节点PD为第一低电平信号，下拉控制节点PC为高电平信号，此时下拉子电路104持续闭合，使得下拉节点PD的电位被第一低电平信号持续拉低，从而保证第一降噪子电路105充分关断，并且可以通过第一低电平信号和第二低电平信号的电压，来控制第一降噪子电路105充分关断，进而可以避免第一降噪子电路105影响上拉节点PU的电位，即避免上拉节点PU发生漏电。同时，移位寄存器单元中增加了第二辅助控制子电路109，可以在上拉节点PU为低电平信号时，下拉节点PD为第一电源电压信号，即下拉节点PD为高电平信号，下拉控制节点PC为第一低电平信号，此时下拉子电路104保持关断，使得下拉节点PD被持续写入第一电源电压信号，从而保证第一降噪子电路105充分闭合，进而可以保证第一降噪子电路105通过第二低电平信号对上拉节点PU持续进行降噪。可以看出，本公开实施例提供的移位寄存器单元中无论第一降噪子电路105关断和闭合，均可以使得上拉节点PU的电位达到预设电位，避免了第一降噪子电路105对上拉节点PU的电位的影响，从而可以保证信号输出端Output的输出信号的稳定，进而可以保证所驱动的显示面板良好的显示效果。
在一些实施例中，如图2所示，第一辅助控制子电路108包括：第一存储电容C1；第一存储电容C1的一端连接下拉控制节点PC，另一端连接第一电源电压端VDD；下拉控制节点PC连接输入子电路101；第二辅助控制子电路109包括：第九晶体管109和第十晶体管M10；第九晶体管M9的栅 极连接辅助控制端PA，源极连接第一低电平端LVGL，漏极连接下拉控制节点PC；第十晶体管M10的栅极连接下拉节点PD，源极连接第一低电平端LVGL，漏极连接下拉控制节点PC。
第一存储电容C1和上拉节点PU同时被充入了高电平信号时，第一存储电容C1存储的高电平信号可以拉高下拉控制节点PC的电位，以控制下拉子电路104保持闭合，使得下拉节点PD的电位被第一低电平信号持续拉低，从而保证第一降噪子电路105充分关断，进而可以避免第一降噪子电路105影响上拉节点PU的电位，即避免上拉节点PU发生漏电。辅助控制节点PA写入高电平信号时，第九晶体管M9打开，上拉节点PU被放电至第二低电平电位，第一存储电容C1被放电至第一低电平电位，使得下拉控制节点PC为第一低电平电位，下拉子电路104关断，下拉节点PD写入第一电源电压信号，即下拉节点PD为高电平，第十晶体管M10持续打开，下拉子电路104持续关断，下拉节点PD被持续写入第一电源电压信号，第一降噪子电路105持续闭合，从而对上拉节点PU进行持续降噪。可以看出，本公开实施例提供的移位寄存器单元中无论第一降噪子电路105关断和闭合，均可以使得上拉节点PU的电位达到预设电位，避免了第一降噪子电路105对上拉节点PU的电位的影响，从而可以保证信号输出端Output的输出信号的稳定，进而可以保证所驱动的显示面板良好的显示效果。
在一些实施例中，图3为本公开实施例提供的另一种移位寄存器单元的电路结构示意图，如图3所示，第一辅助控制子电路108包括：第十一晶体管M11；第十一晶体管M11的栅极和源极均连接信号输入端Input，漏极连接下拉控制节点PC；第二辅助控制子电路109包括：第十二晶体管M12和第十三晶体管M13；第十二晶体管M12的栅极连接辅助控制端PA，源极连接第一低电平端LVGL，漏极连接下拉控制节点PC；第十三晶体管M13的栅极连接下拉节点PD，源极连接第一低电平端LVGL，漏极连接下拉控制节 点PC。
下拉控制节点PC和上拉节点PU同时被充入高电平信号时，下拉子电路104保持闭合，使得下拉节点PD的电位被第一低电平信号持续拉低，从而保证第一降噪子电路105充分关断，进而可以避免第一降噪子电路105影响上拉节点PU的电位，即避免上拉节点PU发生漏电。辅助控制节点PA写入高电平信号时，第十二晶体管M12打开，下拉控制节点PC被下拉至第一低电平，下拉子电路104关断，并且下拉节点PD为第一低电平，第十三晶体管M13打开，下拉节点PD被持续写入第一低电平信号，下拉子电路104持续关断，下拉节点PD被持续写入第一电源电压信号，第一降噪子电路105持续闭合，从而对上拉节点PU进行持续降噪。可以看出，本公开实施例提供的移位寄存器单元中无论第一降噪子电路105关断和闭合，均可以使得上拉节点PU的电位达到预设电位，避免了第一降噪子电路105对上拉节点PU的电位的影响，从而可以保证信号输出端Output的输出信号的稳定，进而可以保证所驱动的显示面板良好的显示效果。
在一些实施例中，图4为本公开实施例提供的又一种移位寄存器单元的电路结构示意图，如图4所示，第一辅助控制子电路108包括：第十四晶体管M14；第十四晶体管M14的栅极和源极连接第一电源电压端VDD，漏极连接下拉控制节点PC；第二辅助控制子电路109包括：第十五晶体管M14和第十六晶体管M15；第十五晶体管M15的栅极连接下拉节点PD，源极连接第一低电平端LVGL，漏极连接下拉控制节点PC；第十六晶体管M16的栅极连接辅助控制端PA，源极连接第一低电平端LVGL，漏极连接下拉控制节点PC。
下拉控制节点PC和下拉节点PD同时被写入第一电源电压信号时，下拉子电路104保持闭合，使得下拉节点PD的电位被第一低电平信号持续拉低，从而保证第一降噪子电路105充分关断，进而可以避免第一降噪子电路 105影响上拉节点PU的电位，即避免上拉节点PU发生漏电。辅助控制节点PA写入高电平信号时，第十六晶体管M16打开，下拉控制节点PC被下拉至第一低电平，下拉子电路104关断，并且下拉节点PD为第一低电平，第十五晶体管M15打开，下拉节点PD被持续写入第一低电平信号，下拉子电路104持续关断，下拉节点PD被持续写入第一电源电压信号，第一降噪子电路105持续闭合，从而对上拉节点PU进行持续降噪。可以看出，本公开实施例提供的移位寄存器单元中无论第一降噪子电路105关断和闭合，均可以使得上拉节点PU的电位达到预设电位，避免了第一降噪子电路105对上拉节点PU的电位的影响，从而可以保证信号输出端Output的输出信号的稳定，进而可以保证所驱动的显示面板良好的显示效果。
在一些实施例中，如图2、图3、和图4所示，移位寄存器单元还包括：第二降噪子电路106；第二降噪子电路106被配置为响应于下拉节点PD的电位，通过第二低电平信号对信号输出端Output的电位进行降噪。
具体地，第二降噪子电路106包括：第四晶体管M4；第四晶体管M4的栅极连接下拉节点PD，源极连接第二低电平端VGL，漏极连接信号输出端Output。
在降噪阶段，下拉节点PD为高电平电位，第四晶体管M4打开，此时可以通过第二低电平信号对信号输出端Output进行降噪。
在一些实施例中，如图2、图3和图4所示，移位寄存器单元还包括：复位子电路107；复位子电路107被配置为响应于复位信号，通过第二低电平信号对上拉节点PU的电位进行复位。
具体地，复位子电路107包括：第二晶体管M2；第二晶体管M2的栅极连接复位信号端Reset，源极连接第二低电平端VGL，漏极连接上拉节点PU。
在复位极端，复位信号端Reset输入高电平信号，第二晶体管M2打开， 此时可以通过第二低电平信号对上拉节点PU进行复位。
在此需要说明的是，在同一以为寄存器中，可以同时设置第二降噪子电路106和复位子电路107，也可仅设置第二降噪子电路106和复位子电路107中一者，例如图2和图4所示的电路中设置有第二降噪子电路106和复位子电路107，图3所示的电路中仅设置有第二降噪子电路106。
在一些实施例中，如图2、图3和图4所示，输入子电路101包括：第一晶体管M1；第一晶体管M1的栅极和源极连接信号输入端Input，漏极连接上拉节点PU。
在输入阶段，信号输入端Input写入高电平信号，第一晶体管M1打开，可以通过信号输入端Input写入的高电平信号对上拉节点进行预充电。
在一些实施例中，如图2、图3和图4所示，输出子电路102包括：第三晶体管M3和第二存储电容C2；第三晶体管M3的栅极连接上拉节点PU，源极连接时钟信号端CLK，漏极连接信号输出端Output；第二存储电容C2的一端连接上拉节点PU，另一端连接信号输出端Output。
在输出阶段，上拉节点PU的电位为高电平，第三晶体管M3被打开，将时钟信号端CLK的时钟信号输出至输出信号端Output，时钟信号端CLK的时钟信号为高电平，此时信号输出端Output的电位被拉高，也即输出高电平信号。
在一些实施例中，如图2、图3和图4所示，下拉控制子电路103包括：第五晶体管M5；第五晶体管M5的栅极和源极连接第一电源电压端VDD，漏极连接下拉节点PD。
第五晶体管M5的栅极和源极连接第一电源电压端VDD，也即被写入第一电源电压信号，此时第五晶体管M5打开，下拉节点PD的电位则为第一电源电压的电位，也即下拉节点PD的电位为高电平。
在一些实施例中，如图2和图4所示，下拉子电路包括：第六晶体管 M6和第七晶体管M7；第六晶体管M6的栅极连接下拉控制节点PC，源极连接第一参考电平端LVGL，漏极连接下拉节点PD；第七晶体管M7的栅极连接信号输入端Input，源极连接第一电源电压端VDD，漏极连接下拉节点PD。
信号输入端Input写入高电平信号时，第七晶体管M7打开，下拉节点PD被写入第一低电平信号，同时辅助控制端写入高电平信号，第六晶体管M6打开，下拉节点可以持续被写入第一电平信号，保证下拉节点PD的电位被持续拉低。
在一些实施例中，如图2、图3和图4所示，第一降噪子电路105包括：第八晶体管M8；第八晶体管M8的栅极连接下拉节点PD，源极连接第二低电平端VGL，漏极连接上拉节点PU。
在降噪阶段，下拉节点PD为高电平电位，第八晶体管M8打开，此时可以通过第二低电平信号对拉节点PU进行降噪。
本公开实施例还提供了一种栅极驱动电路，图5为本公开实施例提供的栅极驱动电路的结构示意图，如图5所示，该栅极驱动电路包括如上述任一实施例提供的相互级联的多个移位寄存器单元；其中，本级移位寄存器单元的信号输入端Input连接上一级移位寄存器单元的信号输出端Output；本级移位寄存器单元的复位信号端Reset连接下一级移位寄存器单元的信号输出端Output；本级移位寄存器单元的辅助控制端PA连接下一级移位寄存器单元的信号输出端Output。
本公开实施例提供的栅极驱动电路可以逐级输出扫描信号，以驱动显示面板进行逐行扫描，以实现显示功能。由于在移位寄存器单元中增加了第一辅助控制子电路108，可以在上拉节点PU为高电平信号时，下拉节点PD为第一低电平信号，下拉控制节点PC为高电平信号，此时下拉子电路104持续闭合，使得下拉节点PD的电位被第一低电平信号持续拉低，从而保证第 一降噪子电路105充分关断，并且可以通过第一低电平信号和第二低电平信号的电压，来控制第一降噪子电路105充分关断，进而可以避免第一降噪子电路105影响上拉节点PU的电位，即避免上拉节点PU发生漏电。同时，移位寄存器单元中增加了第二辅助控制子电路109，可以在上拉节点PU为低电平信号时，下拉节点PD为第一电源电压信号，即下拉节点PD为高电平信号，下拉控制节点PC为第一低电平信号，此时下拉子电路104保持关断，使得下拉节点PD被持续写入第一电源电压信号，从而保证第一降噪子电路105充分闭合，进而可以保证第一降噪子电路105通过第二低电平信号对上拉节点PU持续进行降噪。可以看出，本公开实施例提供的移位寄存器单元中无论第一降噪子电路105关断和闭合，均可以使得上拉节点PU的电位达到预设电位，避免了第一降噪子电路105对上拉节点PU的电位的影响，从而可以保证信号输出端Output的输出信号的稳定，进而可以保证所驱动的显示面板良好的显示效果。
本公开实施例还提供了一种显示装置，该显示装置包括如上述任一实施例提供的栅极驱动电路，该显示装置可以为大尺寸电视、显示器、车载导航等显示设备，其实现原理及技术效果与上述任一实施例提供的栅极驱动电路的实现原理及技术效果相同，在此不在赘述。
本公开实施例还提供了一种移位寄存器单元的驱动方法，驱动如上述任一实施例提供的移位寄存器单元，移位寄存器单元的驱动方法包括：
在下拉节点为第一参考电平信号时，利用第一辅助控制子电路将第三参考电平信号写入下拉控制节点，并控制下拉子电路闭合，以控制第一降噪子电路关断；
在下拉节点为第一电源电压信号时，利用第二辅助控制子电路将第一参考电平信号写入下拉控制节点，并控制下拉子电路关断，以控制第一降噪子电路通过第二参考电平信号对上拉节点进行降噪。
下面将结合图2、图3和图4所示的具体的移位寄存器单元，对本公开实施例提供的移位寄存器单元的驱动方法进行详细说明。
图2所示的移位寄存器中，第一存储电容C1和上拉节点PU同时被充入了高电平信号时，第一存储电容C1存储的高电平信号可以拉高下拉控制节点PC的电位，以控制下拉子电路104保持闭合，使得下拉节点PD的电位被第一低电平信号持续拉低，从而保证第一降噪子电路105充分关断，进而可以避免第一降噪子电路105影响上拉节点PU的电位，即避免上拉节点PU发生漏电。辅助控制节点PA写入高电平信号时，第九晶体管M9打开，上拉节点PU被放电至第二低电平电位，第一存储电容C1被放电至第一低电平电位，使得下拉控制节点PC为第一低电平电位，下拉子电路104关断，下拉节点PD写入第一电源电压信号，即下拉节点PD为高电平，第十晶体管M10持续打开，下拉子电路104持续关断，下拉节点PD被持续写入第一电源电压信号，第一降噪子电路105持续闭合，从而对上拉节点PU进行持续降噪。
图3所示的移位寄存器中，下拉控制节点PC和上拉节点PU同时被充入高电平信号时，下拉子电路104保持闭合，使得下拉节点PD的电位被第一低电平信号持续拉低，从而保证第一降噪子电路105充分关断，进而可以避免第一降噪子电路105影响上拉节点PU的电位，即避免上拉节点PU发生漏电。辅助控制节点PA写入高电平信号时，第十二晶体管M12打开，下拉控制节点PC被下拉至第一低电平，下拉子电路104关断，并且下拉节点PD为第一低电平，第十三晶体管M13打开，下拉节点PD被持续写入第一低电平信号，下拉子电路104持续关断，下拉节点PD被持续写入第一电源电压信号，第一降噪子电路105持续闭合，从而对上拉节点PU进行持续降噪。
图4所示的移位寄存器中，下拉控制节点PC和下拉节点PD同时被写 入第一电源电压信号时，下拉子电路104保持闭合，使得下拉节点PD的电位被第一低电平信号持续拉低，从而保证第一降噪子电路105充分关断，进而可以避免第一降噪子电路105影响上拉节点PU的电位，即避免上拉节点PU发生漏电。辅助控制节点PA写入高电平信号时，第十六晶体管M16打开，下拉控制节点PC被下拉至第一低电平，下拉子电路104关断，并且下拉节点PD为第一低电平，第十五晶体管M15打开，下拉节点PD被持续写入第一低电平信号，下拉子电路104持续关断，下拉节点PD被持续写入第一电源电压信号，第一降噪子电路105持续闭合，从而对上拉节点PU进行持续降噪。
可以看出，本公开实施例提供的移位寄存器单元的驱动方法，无论第一降噪子电路105关断和闭合，均可以使得上拉节点PU的电位达到预设电位，避免了第一降噪子电路105对上拉节点PU的电位的影响，从而可以保证信号输出端Output的输出信号的稳定，进而可以保证所驱动的显示面板良好的显示效果。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (20)

  1. 一种移位寄存器单元，其中，所述移位寄存器单元包括：输入子电路、输出子电路、下拉控制子电路、下拉子电路、第一降噪子电路、第一辅助控制子电路和第二辅助控制子电路；
    所述输入子电路被配置为响应于信号输入端的输入信号，通过所述输入信号对上拉节点的电位进行拉高；所述上拉节点至少同时连接所述输入子电路、所述输出子电路、所述第一降噪子电路；
    所述输出子电路被配置为响应于所述上拉节点被拉高后的电位，通过信号输出端输出信号；
    所述下拉控制子电路被配置为响应于第一电源电压信号，利用所述第一电源电压信号控制下拉节点的电位；所述下拉节点至少同时连接所述下拉控制子电路、所述下拉子电路和所述第一降噪子电路；
    所述下拉子电路被配置为响应于所述下拉控制节点的电位，通过第一参考电平信号下拉所述下拉节点的电位；所述下拉控制节点至少同时连接所述下拉子电路、所述第一辅助控制子电路和所述第二辅助控制子电路；
    所述第一降噪子电路被配置为响应于所述下拉节点的电位，通过第二参考电平信号对所述上拉节点的电位进行降噪；
    所述第一辅助控制子电路被配置为在所述下拉节点为第一参考电平信号时，将第三参考电平信号写入所述下拉控制节点，并控制所述下拉子电路闭合，以控制所述第一降噪子电路关断；
    所述第二辅助控制子电路被配置为在所述下拉节点为第一电源电压信号时，将第一参考电平信号写入所述下拉控制节点，并控制所述下拉子电路关断，以控制所述第一降噪子电路通过所述第二参考电平信号对所述上拉节点进行降噪。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述第一辅助控制子电路包括：第一存储电容；所述第一存储电容的一端连接所述下拉控制节 点，另一端连接所述第一电源电压端；所述下拉控制节点连接所述输入子电路；
    所述第二辅助控制子电路包括：第九晶体管和第十晶体管；所述第九晶体管的控制极连接辅助控制端，第一极连接第一参考电平端，第二极连接所述下拉控制节点；所述第十晶体管的控制极连接所述下拉节点，第一极连接所述第一参考电平端，第二极连接所述下拉控制节点。
  3. 根据权利要求1所述的移位寄存器单元，其中，所述第一辅助控制子电路包括：第十一晶体管；所述第十一晶体管的控制极和第一极均连接信号输入端，第二极连接所述下拉控制节点；
    所述第二辅助控制子电路包括：第十二晶体管和第十三晶体管；所述第十二晶体管的控制极连接辅助控制端，第一极连接第一参考电平端，第二极连接所述下拉控制节点；所述第十三晶体管的控制极连接所述下拉节点，第一极连接所述第一参考电平端，第二极连接所述下拉控制节点。
  4. 根据权利要求1所述的移位寄存器单元，其中，所述第一辅助控制子电路包括：第十四晶体管；所述第十四晶体管的控制极和第一极连接所述第一电源电压端，第二极连接所述下拉控制节点；
    所述第二辅助控制子电路包括：第十五晶体管和第十六晶体管；所述第十五晶体管的控制极连接所述下拉节点，第一极连接第一参考电平端，第二极连接所述下拉控制节点；所述第十六晶体管的控制极连接辅助控制端，第一极连接第一参考电平端，第二极连接所述下拉控制节点。
  5. 根据权利要求1所述的移位寄存器单元，其中，所述移位寄存器单元还包括：第二降噪子电路；
    所述第二降噪子电路被配置为响应于所述下拉节点的电位，通过第二参考电平信号对信号输出端的电位进行降噪。
  6. 根据权利要求5所述的移位寄存器单元，其中，所述第二降噪子电路包括：第四晶体管；
    所述第四晶体管的控制极连接所述下拉节点，第一极连接第二参考电平端，第二极连接信号输出端。
  7. 根据权利要求1所述的移位寄存器单元，其中，所述移位寄存器单元还包括：复位子电路；
    所述复位子电路被配置为响应于复位信号，通过第二参考电平信号对所述上拉节点的电位进行复位。
  8. 根据权利要求7所述的移位寄存器单元，其中，所述复位子电路包括：第二晶体管；
    所述第二晶体管的控制极连接复位信号端，第一极连接第二参考电平端，第二极连接所述上拉节点。
  9. 根据权利要求1所述的移位寄存器单元，其中，所述输入子电路包括：第一晶体管；
    所述第一晶体管的控制极和第一极连接信号输入端，第二极连接所述上拉节点。
  10. 根据权利要求1所述的移位寄存器单元，其中，所述输出子电路包括：第三晶体管和第二存储电容；
    所述第三晶体管的控制极连接所述上拉节点，第一极连接时钟信号端，第二极连接信号输出端；
    所述第二存储电容的一端连接所述上拉节点，另一端连接信号输出端。
  11. 根据权利要求1所述的移位寄存器单元，其中，所述下拉控制子电路包括：第五晶体管；
    所述第五晶体管的控制极和第一极连接第一电源电压端，第二极连接所述下拉节点。
  12. 根据权利要求1所述的移位寄存器单元，其中，所述下拉子电路包括：第六晶体管和第七晶体管；
    所述第六晶体管的控制极连接所述下拉控制节点，第一极连接第一参考 电平端，第二极连接所述下拉节点；
    所述第七晶体管的控制极连接信号输入端，第一极连接第一电源电压端，第二极连接所述下拉节点。
  13. 根据权利要求12所述的移位寄存器单元，其中，所述第一降噪子电路包括：第八晶体管；
    所述第八晶体管的控制极连接所述下拉节点，第一极连接第一参考电平端，第二极连接所述上拉节点。
  14. 一种移位寄存器单元，其中，所述移位寄存器单元包括：输入子电路、复位子电路、输出子电路、下拉控制子电路、下拉子电路、第一降噪子电路、第二降噪子电路、第一辅助控制子电路和第二辅助控制子电路；上拉节点至少同时连接所述输入子电路、所述输出子电路、所述第一降噪子电路；下拉节点至少同时连接所述下拉控制子电路、所述下拉子电路和所述第一降噪子电路；下拉控制节点至少同时连接所述下拉子电路、所述第一辅助控制子电路和所述第二辅助控制子电路；
    所述输入子电路包括：第一晶体管；所述复位子电路包括：第二晶体管；所述输出子电路包括：第三晶体管和第二存储电容；所述第二降噪子电路包括：第四晶体管；所述下拉控制子电路包括：第五晶体管；所述下拉子电路包括：第六晶体管和第七晶体管；所述第一降噪子电路包括：第八晶体管；所述第一辅助控制子电路包括：第一存储电容；所述第二辅助控制子电路包括：第九晶体管和第十晶体管；
    所述第一晶体管的控制极和第一极连接信号输入端，第二极连接所述上拉节点；所述上拉节点至少同时连接所述输入子电路、所述输出子电路、所述第一降噪子电路；
    所述第二晶体管的控制极连接复位信号端，第一极连接第二参考电平端，第二极连接所述上拉节点；
    所述第三晶体管的控制极连接所述上拉节点，第一极连接时钟信号端， 第二极连接信号输出端；
    所述第二存储电容的一端连接所述上拉节点，另一端连接信号输出端；
    所述第四晶体管的控制极连接所述下拉节点，第一极连接第二参考电平端，第二极连接信号输出端；
    所述第五晶体管的控制极和第一极连接第一电源电压端，第二极连接所述下拉节点；
    所述第六晶体管的控制极连接所述下拉控制节点，第一极连接第一参考电平端，第二极连接所述下拉节点；
    所述第七晶体管的控制极连接信号输入端，第一极连接第一电源电压端，第二极连接所述下拉节点；
    所述第八晶体管的控制极连接所述下拉节点，第一极连接第一参考电平端，第二极连接所述上拉节点；
    所述第一存储电容的一端连接所述下拉控制节点，另一端连接所述第一电源电压端；所述下拉控制节点连接所述第一晶体管的第二极；
    所述第九晶体管的控制极连接辅助控制端，第一极连接第一参考电平端，第二极连接所述下拉控制节点；所述第十晶体管的控制极连接所述下拉节点，第一极连接所述第一参考电平端，第二极连接所述下拉控制节点。
  15. 一种移位寄存器单元，其中，所述移位寄存器单元包括：输入子电路、复位子电路、输出子电路、下拉控制子电路、下拉子电路、第一降噪子电路、第二降噪子电路、第一辅助控制子电路和第二辅助控制子电路；上拉节点至少同时连接所述输入子电路、所述输出子电路、所述第一降噪子电路；下拉节点至少同时连接所述下拉控制子电路、所述下拉子电路和所述第一降噪子电路；下拉控制节点至少同时连接所述下拉子电路、所述第一辅助控制子电路和所述第二辅助控制子电路；
    所述输入子电路包括：第一晶体管；所述复位子电路包括：第二晶体管；所述输出子电路包括：第三晶体管和第二存储电容；所述第二降噪子电路包 括：第四晶体管；所述下拉控制子电路包括：第五晶体管；所述下拉子电路包括：第六晶体管和第七晶体管；所述第一降噪子电路包括：第八晶体管；所述第一辅助控制子电路包括：第十一晶体管；所述第二辅助控制子电路包括：第十二晶体管和第十三晶体管；
    所述第一晶体管的控制极和第一极连接信号输入端，第二极连接所述上拉节点；所述上拉节点至少同时连接所述输入子电路、所述输出子电路、所述第一降噪子电路；
    所述第二晶体管的控制极连接复位信号端，第一极连接第二参考电平端，第二极连接所述上拉节点；
    所述第三晶体管的控制极连接所述上拉节点，第一极连接时钟信号端，第二极连接信号输出端；
    所述第二存储电容的一端连接所述上拉节点，另一端连接信号输出端；
    所述第四晶体管的控制极连接所述下拉节点，第一极连接第二参考电平端，第二极连接信号输出端；
    所述第五晶体管的控制极和第一极连接第一电源电压端，第二极连接所述下拉节点；
    所述第六晶体管的控制极连接所述下拉控制节点，第一极连接第一参考电平端，第二极连接所述下拉节点；
    所述第七晶体管的控制极连接信号输入端，第一极连接第一电源电压端，第二极连接所述下拉节点；
    所述第八晶体管的控制极连接所述下拉节点，第一极连接第一参考电平端，第二极连接所述上拉节点；
    所述第十一晶体管的控制极和第一极均连接信号输入端，第二极连接所述下拉控制节点；
    所述第十二晶体管的控制极连接辅助控制端，第一极连接第一参考电平端，第二极连接所述下拉控制节点；所述第十三晶体管的控制极连接所述下 拉节点，第一极连接所述第一参考电平端，第二极连接所述下拉控制节点。
  16. 一种移位寄存器单元，其中，所述移位寄存器单元包括：输入子电路、复位子电路、输出子电路、下拉控制子电路、下拉子电路、第一降噪子电路、第二降噪子电路、第一辅助控制子电路和第二辅助控制子电路；上拉节点至少同时连接所述输入子电路、所述输出子电路、所述第一降噪子电路；下拉节点至少同时连接所述下拉控制子电路、所述下拉子电路和所述第一降噪子电路；下拉控制节点至少同时连接所述下拉子电路、所述第一辅助控制子电路和所述第二辅助控制子电路；
    所述输入子电路包括：第一晶体管；所述复位子电路包括：第二晶体管；所述输出子电路包括：第三晶体管和第二存储电容；所述第二降噪子电路包括：第四晶体管；所述下拉控制子电路包括：第五晶体管；所述下拉子电路包括：第六晶体管和第七晶体管；所述第一降噪子电路包括：第八晶体管；所述第一辅助控制子电路包括：第十四晶体管；所述第二辅助控制子电路包括：第十五晶体管和第十六晶体管；
    所述第一晶体管的控制极和第一极连接信号输入端，第二极连接所述上拉节点；所述上拉节点至少同时连接所述输入子电路、所述输出子电路、所述第一降噪子电路；
    所述第二晶体管的控制极连接复位信号端，第一极连接第二参考电平端，第二极连接所述上拉节点；
    所述第三晶体管的控制极连接所述上拉节点，第一极连接时钟信号端，第二极连接信号输出端；
    所述第二存储电容的一端连接所述上拉节点，另一端连接信号输出端；
    所述第四晶体管的控制极连接所述下拉节点，第一极连接第二参考电平端，第二极连接信号输出端；
    所述第五晶体管的控制极和第一极连接第一电源电压端，第二极连接所述下拉节点；
    所述第六晶体管的控制极连接所述下拉控制节点，第一极连接第一参考电平端，第二极连接所述下拉节点；
    所述第七晶体管的控制极连接信号输入端，第一极连接第一电源电压端，第二极连接所述下拉节点；
    所述第八晶体管的控制极连接所述下拉节点，第一极连接第一参考电平端，第二极连接所述上拉节点；
    所述第十四晶体管的控制极和第一极连接所述第一电源电压端，第二极连接所述下拉控制节点；
    所述第十五晶体管的控制极连接所述下拉节点，第一极连接第一参考电平端，第二极连接所述下拉控制节点；所述第十六晶体管的控制极连接辅助控制端，第一极连接第一参考电平端，第二极连接所述下拉控制节点。
  17. 一种栅极驱动电路，其中，所述栅极驱动电路包括多个相互级联的如权利要求1-16任一项所述移位寄存器单元。
  18. 根据权利要求17所述的栅极驱动电路，其中，本级移位寄存器单元的信号输入端连接上一级移位寄存器单元的信号输出端；
    本级移位寄存器单元的复位信号端连接下一级移位寄存器单元的信号输出端；
    本级移位寄存器单元的辅助控制端连接下一级移位寄存器单元的信号输出端。
  19. 一种显示装置，其中，所述显示装置包括如权利要求17-18任一项所述的栅极驱动电路。
  20. 一种移位寄存器单元单元的驱动方法，用于驱动如权利要求1-16任一项所述的移位寄存器单元，其中，所述移位寄存器单元的驱动方法包括：
    在所述下拉节点为第一参考电平信号时，利用第一辅助控制子电路将第三参考电平信号写入所述下拉控制节点，并控制所述下拉子电路闭合，以控制所述第一降噪子电路关断；
    在所述下拉节点为第一电源电压信号时，利用第二辅助控制子电路将第一参考电平信号写入所述下拉控制节点，并控制所述下拉子电路关断，以控制所述第一降噪子电路通过所述第二参考电平信号对所述上拉节点进行降噪。
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