WO2017133117A1 - 移位寄存器及其驱动方法、栅极驱动电路和显示装置 - Google Patents

移位寄存器及其驱动方法、栅极驱动电路和显示装置 Download PDF

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WO2017133117A1
WO2017133117A1 PCT/CN2016/081699 CN2016081699W WO2017133117A1 WO 2017133117 A1 WO2017133117 A1 WO 2017133117A1 CN 2016081699 W CN2016081699 W CN 2016081699W WO 2017133117 A1 WO2017133117 A1 WO 2017133117A1
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Prior art keywords
node
signal
voltage
voltage source
shift register
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PCT/CN2016/081699
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English (en)
French (fr)
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吕磊
徐飞
洪俊
杨杰
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Priority to US15/538,932 priority Critical patent/US9984642B2/en
Publication of WO2017133117A1 publication Critical patent/WO2017133117A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure relates to a shift register and a driving method thereof, a gate driving circuit, and a display device.
  • TFT-LCDs Thin film transistor liquid crystal displays
  • the driving circuit of the TFT-LCD mainly includes a gate driving circuit and a data driving circuit.
  • the data driving circuit is configured to sequentially latch the input data according to the clock signal timing and convert the latched data into an analog signal and input the data to the data line of the display panel.
  • the gate driving circuit is usually implemented by a shift register that converts a clock signal into an on/off voltage, which are respectively output to respective gate lines of the display panel.
  • a gate line on the display panel is typically docked with a shift register (ie, the stage of the shift register).
  • Progressive scanning of pixels in the display panel is achieved by causing the respective shift registers to sequentially output the turn-on voltage.
  • Such progressive scanning of pixels can be divided into one-way scanning and two-way scanning according to the scanning direction.
  • the conventional gate drive circuit can only drive one row of gate lines, and the development of circuits with fewer TFTs is of great significance for implementing ultra-narrow bezels.
  • GOA Gate Driver on Array
  • the GOA technology directly integrates the gate driving circuit of the TFT-LCD on the array substrate, thereby replacing the driving chip made of the silicon chip bonded on the outer edge of the panel. Since the technology can directly drive the driving circuit on the array substrate, there is no need to bond the IC and the wiring around the panel, which reduces the manufacturing process of the panel, reduces the product cost, and improves the integration degree of the TFT-LCD panel, so that the panel can be realized. Narrow borders and high resolution.
  • GOA technology has inherent problems in terms of service life and the like. In the GOA design of the actual product, how to use less circuit components to realize the shift register function and reduce the noise at the output terminal to keep the gate drive circuit stable for a long time is GOA. Key issues in design.
  • the present disclosure provides a shift register and a driving method thereof, a gate driving circuit, and a display device.
  • a shift register can be implemented to drive two rows of gate lines, reducing the number of transistors used, reducing circuit cost, eliminating noise at the output of the shift register, and improving the stability of the operation.
  • a shift register including:
  • a pre-charging module coupled to the first voltage source and the signal input, configured to provide a voltage of the first voltage source to the first node under control of an input signal from the signal input, the first node being an output of the pre-charging module node;
  • a reset module connected to the second voltage source, the reset signal end, and the first node, configured to provide a voltage of the second voltage source to the first node under control of an input signal from the reset signal terminal;
  • control module connected to the third voltage source, the fourth voltage source, and the first node, configured to provide a voltage from the third voltage source to the second node or to the fourth voltage under the control of the voltage of the first node
  • the voltage of the source is provided to the second node, and the second node is an output node of the control module;
  • a first pull-up module connected to the first clock signal end, the first signal output end, and the first node, configured to provide a clock signal from the first clock signal end to the first signal under the control of the voltage of the first node Output
  • a second pull-up module connected to the first clock signal end, the second clock signal end, the first node and the second signal output end, configured to be under the control of the clock signal of the first clock signal end and the voltage of the first node a clock signal of the second clock signal end is provided to the second signal output end;
  • a first pull-down module connected to the fourth voltage source, the first signal output end and the second signal output end, configured to provide the voltage of the fourth voltage source to the first under the control of the output signal of the second signal output end Signal output
  • the second pull-down module is connected to the fourth voltage source, the second signal output end and the second node, and is configured to provide the voltage of the fourth voltage source to the second signal output terminal under the control of the voltage of the second node.
  • a gate driving circuit including a plurality of serially connected shift registers, each of the shift registers being the shift register described above, wherein the last shift is transmitted Outside the register, the second signal output of each of the remaining shift registers is connected to the signal input of the next shift register adjacent thereto; except for the first shift register, the remainder of each shift register A signal output is connected to a reset signal end of a previous shift register adjacent thereto;
  • the signal input end of the first shift register inputs a frame start signal; in the reverse scan, the reset signal end of the last shift register inputs a frame start signal.
  • a display device including the above-described gate driving circuit is disclosed.
  • a driving method of a shift register including a pre-charging module, a reset module, a control module, a first pull-up module, a second pull-up module, and a first pull-down is disclosed.
  • Module, second pull-down module, the driving method includes:
  • the pre-charging module Providing, by the pre-charging module, the voltage of the first voltage source to the output node of the pre-charging module under the control of the input signal from the signal input;
  • the voltage from the third voltage source is supplied to the output node of the control module or the voltage from the fourth voltage source is supplied to the output node of the control module by the control module under the control of the voltage of the output node of the pre-charging module;
  • the voltage of the fourth voltage source is supplied to the second signal output by the second pull-down module under the control of the voltage of the output node of the control module.
  • Figure 1 shows a circuit diagram of a conventional shift register
  • FIG. 2 is a timing diagram of signals of the shift register of FIG. 1 when performing forward scanning
  • FIG. 3 illustrates a block diagram of a shift register in accordance with an embodiment of the present disclosure
  • FIG. 4 illustrates a circuit configuration diagram of the shift register of FIG. 3 in accordance with an embodiment of the present disclosure
  • FIG. 5 is a timing chart showing signals of the shift register of FIG. 4 when performing forward scanning
  • FIG. 6 shows a schematic diagram of a gate drive circuit formed by cascading a plurality of shift registers in accordance with an embodiment of the present disclosure.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other device having the same characteristics.
  • the connection modes of the drain and the source of each transistor are interchangeable. Therefore, the drain and source of each transistor in the embodiment of the present disclosure are practically indistinguishable.
  • the drain and source of each transistor in the embodiment of the present disclosure are practically indistinguishable.
  • the gate one of which is called the drain and the other is called the source.
  • Figure 1 shows a circuit diagram of a conventional shift register.
  • the shift register 100 includes first to ninth transistors M1-M9 and a first capacitor C1.
  • the first transistor M1 functions as a pre-charging module
  • the second transistor M2 functions as a reset module
  • the third to sixth transistors M3-M6 serve as a control module
  • the seventh transistor M7 and the first capacitor C1 serve as a pull-up module
  • the eighth transistor M8 As a pull-down module
  • the ninth transistor M9 acts as a noise canceling module.
  • the pre-charging module is connected to the first voltage source VDD and the signal input terminal INPUT, and configured to provide the voltage of the first voltage source VDD to the first node PU under the control of the input signal from the signal input terminal INPUT, the first The node PU is an output node of the pre-charging module;
  • the reset module is connected to the second voltage source VSS, the reset signal terminal RESET and the first node PU, and is configured to provide the voltage of the second voltage source VSS to the first control under the control of the input signal from the reset signal terminal RESET a node PU;
  • the control module is configured to connect the third voltage source GCH, the fourth voltage source VGL, and the first node PU, and configured to provide the voltage from the third voltage source GCH to the second node under the control of the voltage of the first node PU
  • the PD or the voltage from the fourth voltage source VGL is provided to the second node PD, the second node PD is the output node of the control module, the third voltage source GCH is a constant high voltage source, and the fourth voltage source VGL is constant low. power source;
  • the pull-up module is connected to the clock signal terminal CLK, the signal output terminal OUTPUT and the first node PU, and is configured to provide a clock signal from the clock signal terminal CLK to the signal output terminal OUTPUT under the control of the voltage of the first node PU. ;
  • the pull-down module is connected to the fourth voltage source VGL, the signal output terminal OUTPUT and the second node PD, configured to supply the voltage of the fourth voltage source VGL to the signal output terminal OUTPUT under the control of the voltage of the second node PD;
  • the noise canceling module is connected to the fourth voltage source VGL, the first node PU, and the second node PD.
  • the noise canceling module maintains the first node PU at a low level during a non-operating time of the shift register (a time between when the shift register completes one frame output until the arrival of the next frame).
  • the shift register 100 described above is capable of bidirectional scanning.
  • the structure of the shift register does not change, but the functions of the signal input terminal INPUT and the reset signal terminal RESET are changed.
  • a high level signal is input from the first voltage source VDD, and a low level signal is input from the second voltage source VSS;
  • a low level signal is input from the first voltage source VDD, A high level signal is input from the second voltage source VSS.
  • the signal input terminal INPUT at the time of forward scanning is used as the reset signal terminal RESET at the time of reverse scanning, and the reset signal terminal RESET at the time of forward scanning is used as the signal input terminal INPUT at the time of reverse scanning.
  • FIG. 2 Shown in FIG. 2 is a timing diagram of the signals of the shift register of FIG. 1 when performing a forward scan. Referring now to Figure 2, the four stages of operation of the shift register of Figure 1 are illustrated.
  • the signal input by the INPUT shift register signal input terminal INPUT is the output signal of the signal output terminal OUTPUT of the shift register of the previous stage, and at this time is a high level signal, so that the first transistor M1 is turned on;
  • the high level signal input from the first voltage source VDD charges the first capacitor C1, the level of the first node PU is pulled high, so that the fifth transistor M5 and the sixth transistor M6 are turned on; by designing the fifth transistor M5 and The ratio of the sixth transistor M6 is such that the level of the second node PD is at a low level, and the eighth transistor M8 and the ninth transistor M9 are turned off, thereby ensuring that the signal output terminal OUTPUT stably outputs a low level.
  • the signal input by the INPUT shift register signal input terminal INPUT is a low level signal
  • the first transistor M1 is turned off
  • the first node PU continues to maintain a high level
  • the seventh transistor M7 remains in an on state.
  • the clock signal of the clock signal terminal CLK becomes a high level signal due to The bootstrap effect of the first capacitor C1
  • the first node PU point level rises
  • the signal output terminal OUTPUT outputs a high level
  • the eighth transistor M8 and the ninth transistor M9 remain off, ensuring that the signal output terminal OUTPUT stably outputs a high level.
  • the signal output terminal OUTPUT of the next stage shift register outputs a high level signal to the reset signal terminal RESET of the shift register of the current stage.
  • the second transistor M2 is turned on, the level of the first node PU is pulled low, and the fifth to seventh transistors M5-M7 are turned off; the third voltage source GCH is always at a high level, and the level of the second node PD is pulled high.
  • the eighth transistor M8 and the ninth transistor M9 are turned on, and the second node PU and the signal output terminal OUTPUT stably output a low level to complete driving of one row of gate lines.
  • the reset signal terminal RESET becomes a low level, and the second transistor M2 is turned off.
  • the first node PU is always at a low level, and the second node PD is always at a high level, the eighth The transistor M8 and the ninth transistor M9 are always in an on state, and the second node PU and the signal output terminal OUTPUT can be continuously noise-canned, so that the coupled noise voltage generated by the clock signal terminal CLK is eliminated, thereby ensuring the signal output terminal OUTPUT. Output low level steadily.
  • the above conventional shift register can only drive one row of gate lines and requires 9 transistors and 1 capacitor.
  • Each stage of the gate drive circuit composed of such a shift register can only drive one row of gate lines.
  • To drive two rows of gate lines up to 18 transistors and 2 capacitors are needed, which is disadvantageous for achieving a narrow border. the design of.
  • the present application proposes a new shift register that can implement a shift register to drive two rows of gate lines.
  • FIG. 3 shows a block diagram of a shift register in accordance with an embodiment of the present disclosure.
  • the shift register 300 includes:
  • the pre-charging module 301 is connected to the first voltage source VDD and the signal input terminal INPUT, and configured to provide the voltage of the first voltage source VDD to the first node PU under the control of the input signal from the signal input terminal INPUT, the first The node PU is an output node of the pre-charging module 301;
  • the reset module 302 is connected to the second voltage source VSS, the reset signal terminal RESET and the first node PU, and is configured to provide the voltage of the second voltage source VSS to the first control under the control of the input signal from the reset signal terminal RESET a node PU;
  • the control module 303 is connected to the third voltage source GCH, the fourth voltage source VGL and the first node PU, and configured to provide the voltage from the third voltage source GCH to the second node under the control of the voltage of the first node PU
  • the PD or the voltage from the fourth voltage source VGL is supplied to the second node PD, the second node PD is the output node of the control module 303, the third voltage source GCH is a constant high voltage source, and the fourth voltage source VGL is constant.
  • the first pull-up module 304 is connected to the first clock signal terminal CLK1, the first signal output terminal OUTPUT1 and the first node PU, and configured to be from the first clock signal terminal CLK1 under the control of the voltage of the first node PU
  • the clock signal is supplied to the first signal output terminal OUTPUT1;
  • the second pull-up module 305 is connected to the first clock signal terminal CLK1, the second clock signal terminal CLK2, the first node PU and the second signal output terminal OUTPUT2, and is configured as a clock signal and a first node at the first clock signal terminal CLK1.
  • the clock signal from the second clock signal terminal CLK2 is supplied to the second signal output terminal OUTPUT2 under the control of the voltage of the PU;
  • the first pull-down module 306 is connected to the fourth voltage source VGL, the first signal output terminal OUTPUT1 and the second signal output terminal OUTPUT2, and configured to be the fourth voltage source under the control of the output signal of the second signal output terminal OUTPUT2
  • the voltage of VGL is supplied to the first signal output terminal OUTPUT1;
  • a second pull-down module 307 connected to the fourth voltage source VGL, the second signal output terminal OUTPUT2 and the second node PD, configured to provide the voltage of the fourth voltage source VGL to the first under the control of the voltage of the second node PD Two signal output terminals OUTPUT2.
  • the second pull-down module 307 also maintains the second signal output terminal OUTPUT2 low during the non-operating time of the shift register 300 (the time between when the shift register completes one frame output until the arrival of the next frame).
  • the shift register 300 further includes:
  • the noise canceling module 308 is connected to the fourth voltage source VGL, the first signal output terminal OUTPUT1, the first node PU, and the second node PD.
  • the noise canceling module 308 maintains the first node PU and the first signal output terminal OUTPUT1 at a low level during the non-working time of the shift register 300.
  • the shift register 300 has two signal outputs, so that two rows of gate lines can be driven while ensuring no interference between the outputs.
  • FIG. 4 shows a circuit configuration diagram of the shift register 300 of FIG. 3 in accordance with an embodiment of the present disclosure.
  • the pre-charging module 301 includes a first transistor M1 whose drain is connected to the first
  • the voltage source VDD has a gate connected to the signal input terminal INPUT and a source connected to the first node PU.
  • the reset module 302 includes a second transistor M2 having a drain connected to the first node PU, a gate connected to the reset signal terminal RESET, and a source connected to the second voltage source VSS.
  • the control module 303 includes: a third transistor M3 having a drain and a gate connected to the third voltage source GCH; a fourth transistor M4 having a drain connected to the third voltage source GCH and a gate connected to the source of the third transistor M3 a source connected to the second node PD; a fifth transistor M5 having a drain connected to the source of the third transistor M3, a gate connected to the first node PU, and a source connected to the fourth voltage source VGL;
  • the transistor M6 has a drain connected to the second node PD, a gate connected to the first node PU, and a source connected to the fourth voltage source VGL.
  • the first pull-up module 304 includes: a seventh transistor M7 having a drain connected to the first clock signal terminal CLK1, a gate connected to the first node PU, a source connected to the first signal output terminal OUTPUT1, and a first capacitor C1, Connected between the first node PU and the first signal output terminal OUTPUT1.
  • the second pull-up module 305 includes: an eighth transistor M8 having a gate connected to the first clock signal terminal CLK1, a source connected to the first node PU, and a second capacitor C2 connected to the drain of the eighth transistor M8 and The second signal output terminal OUTPUT2 is connected; the ninth transistor M9 has a drain connected to the second clock signal terminal CLK2, a gate connected to the drain of the eighth transistor M8, and a source connected to the second signal output terminal OUTPUT2.
  • the first pull-down module 306 includes a tenth transistor M10 having a drain connected to the first signal output terminal OUTPUT1, a gate connected to the second signal output terminal OUTPUT2, and a source connected to the fourth voltage source VGL.
  • the second pull-down module 307 includes an eleventh transistor M11 whose drain is connected to the second signal output terminal OUTPUT2, the gate is connected to the second node PD, and the source is connected to the fourth voltage source VGL.
  • the noise canceling module 308 includes: a twelfth transistor M12 having a drain connected to the first signal output terminal OUTPUT1, a gate connected to the second node PD, a source connected to the fourth voltage source VGL, and a thirteenth transistor M13
  • the drain is connected to the first node PU, the gate is connected to the second node PD, and the source is connected to the fourth voltage source VGL.
  • a shift register can be driven to drive two rows of gate lines, which reduces the number of transistors used, reduces circuit cost, eliminates noise at the output of the shift register, and improves work stability.
  • the shift register according to the present application only needs 13
  • the transistors compared to the shift registers known in Figure 1, reduce the use of five transistors.
  • the shift register of the present application can reduce the use of thousands of transistors, thereby realizing the function of gate line driving in a smaller area, and achieving a narrower border. Reduce the cost of the gate drive circuit.
  • each module shown in FIG. 4 is merely an example, and each module may also adopt other suitable circuit structures, as long as the respective functions can be respectively implemented, and the disclosure does not limit this. .
  • FIG. 5 is a timing chart showing signals of the shift register of FIG. 4 when performing forward scanning.
  • a specific operational procedure of the shift register of FIG. 4 according to an embodiment of the present disclosure will be described below with reference to FIG. Hereinafter, an example in which the above transistors are N-type transistors will be described.
  • the shift register according to the present disclosure is capable of bidirectional scanning.
  • the structure of the shift register does not change, but the functions of the signal input terminal INPUT and the reset signal terminal RESET are changed.
  • a high level signal is input from the first voltage source VDD, and a low level signal is input from the second voltage source VSS;
  • the reverse scan is performed, a low level signal is input from the first voltage source VDD, A high level signal is input from the second voltage source VSS.
  • the signal input terminal INPUT at the time of forward scanning is used as the reset signal terminal RESET at the time of reverse scanning, and the reset signal terminal RESET at the time of forward scanning is used as the signal input terminal INPUT at the time of reverse scanning.
  • the working process includes the following stages. This working process will be described below with reference to FIGS. 4 and 5.
  • the first stage T1 the signal input by the INPUT shift register signal input terminal INPUT is the output signal of the signal output end OUTPUT of the shift register of the previous stage, and at this time is a high level signal, so that the first transistor M1 is turned on;
  • the high level signal input by the first voltage source VDD charges the first capacitor C1, the level of the first node PU is pulled high, so that the fifth transistor M5 and the sixth transistor M6 are turned on; by designing the fifth transistor M5 and the The ratio of the six transistors M6 is such that the level of the second node PD is low, and the eleventh to thirteenth transistors M11-M13 are turned off, and the clock signal outputted by the first clock signal terminal CLK1 is a low level signal.
  • the eighth transistor M8 and the ninth transistor M9 are turned off, and the first signal output terminal OUTPUT1 and the second signal output terminal OUTPUT2 stably output a low level.
  • the second stage T2 the signal input to the INPUT shift register signal input terminal is low level
  • the signal, the first transistor M1 is turned off, the first node PU continues to remain high, and the seventh transistor M7 remains in an on state.
  • the clock signal of the first clock signal terminal CLK1 becomes a high level signal, so the first signal output terminal OUTPUT1 outputs a high level; meanwhile, the eighth transistor M8 is turned on, and the first node PU charges the second capacitor C2, so that The third node PO is at a high level, and the ninth transistor M9 is turned on. Since the clock signal of the second clock signal terminal CLK2 is a low level signal at this time, the second signal output terminal OUTPUT2 outputs a low level.
  • the tenth transistor M10 is turned off, and since the fifth transistor M5 and the sixth transistor M6 are still turned on, the second node PD remains at a low level, and the eleventh to thirteenth transistors M11-M13 remain turned off to ensure the first signal output.
  • the terminal OUTPUT1 stabilizes the output high level and the second signal output terminal OUTPUT2 stabilizes the output low level.
  • the third stage T3 the clock signal of the first clock signal terminal CLK1 is a low level signal, and the clock signal of the second clock signal terminal CLK2 is a high level signal. Since the third node PO is at a high level, the ninth transistor M9 leads The second signal output terminal OUTPUT2 outputs a high level. At the same time, the tenth transistor M10 is turned on, and the output of the first signal output terminal OUPUT1 is pulled to a low level to complete driving of the first row of gate lines.
  • the fourth stage T4 the clock signal of the first clock signal terminal CLK1 becomes a high level, the eighth transistor M8 is turned on, and the first signal output end of the next stage shift register outputs a high level to the shift register of the current stage.
  • the level of the second node PD is pulled high by the third voltage source GCH, the eleventh to thirteenth transistors M11-M13 are turned on, and the second signal output terminal OUTPUT2 and the first signal output terminal OUTPUT1 are both stable and output low. Level, complete the driving of the second row of gate lines.
  • the reset signal terminal RESET becomes a low level, and the second transistor M2 is turned off.
  • the PU point of the first node is always at a low level, and the PD point of the second node is always at a high level, the eleventh to The thirteenth transistor M11-M13 is always in an on state, and can continuously perform noise cancellation on the first node PU, the first signal output terminal OUTPUT1 and the second signal output terminal OUTPUT2, and the first clock signal terminal CLK1 is continuously turned on.
  • the eight-transistor M8 can continuously perform noise cancellation on the third node PO, thereby ensuring the stability of the low-voltage signal output of the second signal output terminal OUTPUT2 and the first signal output terminal OUTPUT1.
  • the shift register re-executes the first stage after receiving the high level signal of the signal input terminal INPUT.
  • the present disclosure also provides a method of driving a shift register.
  • the method will be described below in conjunction with FIG. 4.
  • the shift register includes a pre-charging module 301, a reset module 302, a control module 303, a first pull-up module 304, a second pull-up module 305, a first pull-down module 306, and a second pull-down module 307.
  • the driving method includes:
  • the voltage of the first voltage source VDD is supplied to the output node PU of the pre-charging module 301 by the pre-charging module 301 under the control of the input signal from the signal input terminal INPUT;
  • the voltage of the second voltage source VSS is supplied to the output node PU of the pre-charging module 301 by the reset module 302 under the control of the input signal from the reset signal terminal;
  • the voltage from the third voltage source GCH is supplied to the output node PD of the control module 303 or the voltage from the fourth voltage source VGL is supplied to the control module by the control module 303 under the control of the voltage of the output node PU of the pre-charging module 301.
  • the clock signal from the first clock signal terminal CLK1 is supplied to the first signal output terminal OUTPUT1 by the first pull-up module 304 under the control of the voltage of the output node PU of the pre-charging module 301;
  • the clock signal from the second clock signal terminal CLK2 is supplied to the second signal output terminal OUTPUT2 by the second pull-up module 305 under the control of the clock signal of the first clock signal terminal CLK1 and the voltage of the output node PU of the pre-charging module 301. ;
  • the first voltage drop terminal 306 is supplied to the first signal output terminal OUTPUT1 under the control of the output signal of the second signal output terminal OUTPUT2;
  • the voltage of the fourth voltage source VGL is supplied to the second signal output terminal OUTPUT2 by the second pull-down module 307 under the control of the voltage of the output node PD of the control module 303.
  • FIG. 6 shows a schematic diagram of a gate drive circuit formed by cascading a plurality of shift registers in accordance with an embodiment of the present disclosure.
  • a plurality of the above-described shift registers in FIG. 4 are connected in series.
  • the second signal output terminal OUTPUT2 of each of the shift registers Ri (1 ⁇ i ⁇ m) and the signal input terminal INPUT of the next shift register Ri+1 adjacent thereto Connected; except for the first shift register R1, the first signal output terminal OUTPUT1 of each of the shift registers Ri (1 ⁇ i ⁇ m) and the previous shift register adjacent thereto
  • the reset signal terminal RESET of Ri-1 is connected.
  • the signal input terminal INPUT of the first shift register R1 inputs a frame start signal STV; during reverse scanning, the reset signal terminal RESET of the last shift register Rm inputs a frame start. Signal STV.
  • the clock signals input to the first clock signal terminals of the adjacent two-stage shift registers are the same, and the clock signals input to the second clock signal terminals are the same.
  • the gate driving circuit may employ GOA technology as a gate driving circuit of a display device to provide a progressive scanning function to transmit a scanning signal to a display area.
  • the gate driving circuit according to an embodiment of the present disclosure can reduce the number of transistors used, reduce circuit cost, eliminate noise at the output, and improve work stability.
  • the present disclosure also provides a display device including the above-described gate driving circuit.
  • the display device here can be: electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator and the like with any display product or component.

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Abstract

一种移位寄存器及其驱动方法、栅极驱动电路和显示装置。该移位寄存器(300)包括：预充电模块(301)、复位模块(302)、控制模块(303)、第一上拉模块(304)、第二上拉模块(305)、第一下拉模块(306)和第二下拉模块(307)。该移位寄存器可以实现一个移位寄存器驱动两行栅线，减少晶体管使用数量，降低电路成本，消除移位寄存器输出端的噪声，提高工作的稳定性。

Description

移位寄存器及其驱动方法、栅极驱动电路和显示装置 技术领域
本公开涉及一种移位寄存器及其驱动方法、栅极驱动电路和显示装置。
背景技术
薄膜晶体管液晶显示器(TFT-LCD)广泛应用于生产生活的各个领域，其采用M*N点排列的逐行扫描矩阵显示。在进行显示时，TFT-LCD通过驱动电路来驱动显示面板中的各个像素进行显示。TFT-LCD的驱动电路主要包含栅极驱动电路和数据驱动电路。其中，数据驱动电路用于依据时钟信号定时将输入的数据顺序锁存并将锁存的数据转换成模拟信号后输入到显示面板的数据线。栅极驱动电路通常用移位寄存器来实现，所述移位寄存器将时钟信号转换成开启/断开电压，分别输出到显示面板的各条栅线上。显示面板上的一条栅线通常与一个移位寄存器(即移位寄存器的一级)对接。通过使得各个移位寄存器依序轮流输出开启电压，实现对显示面板中像素的逐行扫描。像素的这种逐行扫描按照扫描方向可分为单向扫描和双向扫描。目前，在移动产品中，考虑到移动产品产能和良率的提升，通常要求能够实现双向扫描。
随着移动产品例如手机，平板电脑等产品越来越轻薄化和精细化，窄边框成为发展的趋势。传统的栅极驱动电路一级电路只能驱动一行栅线，开发出TFT数目更少的电路对于实现超窄边框具有很重要的意义。
另一方面，随着平板显示的发展，高分辨率、窄边框成为发展的趋势。针对这一趋势，出现了阵列基板栅极驱动(Gate Driver on Array，GOA)技术。GOA技术直接将TFT-LCD的栅极驱动电路集成制作在阵列基板上，由此来代替在面板外沿粘接的、由硅芯片制作的驱动芯片。由于该技术可以将驱动电路直接做在阵列基板上，面板周围无需再粘接IC和布线，减少了面板的制作程序，降低了产品成本，同时提高了TFT-LCD面板的集成度，使面板实现窄边框和高分辨率。但是GOA技术存在固有的使用寿命等方面的问题。在实际产品的GOA设计中，如何使用较少的电路元器件来实现移位寄存功能、并且减小输出端噪声以保持栅极驱动电路长期稳定工作，是GOA 设计的关键问题。
发明内容
本公开提供了一种移位寄存器及其驱动方法、栅极驱动电路和显示装置。可以实现一个移位寄存器驱动两行栅线，减少晶体管使用数量，降低电路成本，消除移位寄存器输出端的噪声，提高工作的稳定性。
根据本公开的一方面，公开了一种移位寄存器，包括：
预充电模块，连接第一电压源和信号输入端，配置为在来自信号输入端的输入信号的控制下将第一电压源的电压提供至第一节点，所述第一节点为预充电模块的输出节点；
复位模块，连接第二电压源、复位信号端和所述第一节点，配置为在来自复位信号端的输入信号的控制下将第二电压源的电压提供至所述第一节点；
控制模块，连接第三电压源、第四电压源和所述第一节点，配置为在第一节点的电压的控制下将来自第三电压源的电压提供给第二节点或者将来自第四电压源的电压提供给第二节点，所述第二节点为控制模块的输出节点；
第一上拉模块，连接第一时钟信号端、第一信号输出端和所述第一节点，配置为在第一节点的电压的控制下将来自第一时钟信号端的时钟信号提供给第一信号输出端；
第二上拉模块，连接第一时钟信号端、第二时钟信号端、第一节点和第二信号输出端，配置为在第一时钟信号端的时钟信号和第一节点的电压的控制下将来自第二时钟信号端的时钟信号提供给第二信号输出端；
第一下拉模块，连接第四电压源、第一信号输出端和第二信号输出端，配置为在第二信号输出端的输出信号的控制下将所述第四电压源的电压提供给第一信号输出端；
第二下拉模块，连接第四电压源、第二信号输出端和第二节点，配置为在第二节点的电压的控制下将所述第四电压源的电压提供给第二信号输出端。
根据本公开的又一方面，公开了一种栅极驱动电路，包括多个串联的移位寄存器，每个所述移位寄存器是上述移位寄存器，其中除最后一个移位寄 存器外，其余每个移位寄存器的第二信号输出端均和与其相邻的下一个移位寄存器的信号输入端相连；除第一个移位寄存器外，其余每个移位寄存器的第一信号输出端均和与其相邻的上一个移位寄存器的复位信号端相连；
在正向扫描时，所述第一个移位寄存器的信号输入端输入帧起始信号；在反向扫描时，所述最后一个移位寄存器的复位信号端输入帧起始信号。
根据本公开的再一方面，公开了一种显示装置，包含上述栅极驱动电路。
根据本公开的再一方面，公开了一种移位寄存器的驱动方法，该移位寄存器包含预充电模块、复位模块、控制模块、第一上拉模块、第二上拉模块、第一下拉模块、第二下拉模块，该驱动方法包含：
由预充电模块在来自信号输入端的输入信号的控制下将第一电压源的电压提供至预充电模块的输出节点；
由复位模块在来自复位信号端的输入信号的控制下将第二电压源的电压提供至所述预充电模块的输出节点；
由控制模块在预充电模块的输出节点的电压的控制下将来自第三电压源的电压提供给控制模块的输出节点或者将来自第四电压源的电压提供给控制模块的输出节点；
由第一上拉模块在预充电模块的输出节点的电压的控制下将来自第一时钟信号端的时钟信号提供给第一信号输出端；
由第二上拉模块在第一时钟信号端的时钟信号和预充电模块的输出节点的电压的控制下将来自第二时钟信号端的时钟信号提供给第二信号输出端；
由第一下拉模块在第二信号输出端的输出信号的控制下将所述第四电压源的电压提供给第一信号输出端；
由第二下拉模块在控制模块的输出节点的电压的控制下将所述第四电压源的电压提供给第二信号输出端。
附图说明
图1示出了传统的移位寄存器的电路图；
图2中所示的是图1中的移位寄存器在进行正向扫描时各信号的时序图；
图3示出了根据本公开实施例的移位寄存器的框图；
图4示出了根据本公开实施例的图3的移位寄存器的一种电路结构图；
图5示出了图4中的移位寄存器在进行正向扫描时各信号的时序图；
图6示出了由根据本公开实施例的多个移位寄存器级联形成的栅极驱动电路的示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本实施例中，每个晶体管的漏极和源极的连接方式可以互换，因此，本公开实施例中各晶体管的漏极、源极实际是没有区别的。这里，仅仅是为了区分晶体管除栅极之外的两极，而将其中一极称为漏极，另一极称为源极。
图1示出了传统的移位寄存器的电路图。如图1所示，该移位寄存器100包含第一至第九晶体管M1-M9以及第一电容C1。其中，第一晶体管M1作为预充电模块，第二晶体管M2作为复位模块，第三至第六晶体管M3-M6作为控制模块，第七晶体管M7和第一电容C1作为上拉模块，第八晶体管M8作为下拉模块，第九晶体管M9作为放噪模块。
上述预充电模块，连接第一电压源VDD和信号输入端INPUT，配置为在来自信号输入端INPUT的输入信号的控制下将第一电压源VDD的电压提供至第一节点PU，所述第一节点PU为预充电模块的输出节点；
上述复位模块，连接第二电压源VSS、复位信号端RESET和所述第一节点PU，配置为在来自复位信号端RESET的输入信号的控制下将第二电压源VSS的电压提供至所述第一节点PU；
上述控制模块，连接第三电压源GCH、第四电压源VGL和所述第一节点PU，配置为在第一节点PU的电压的控制下将来自第三电压源GCH的电压提供给第二节点PD或者将来自第四电压源VGL的电压提供给第二节点PD，所述第二节点PD为控制模块的输出节点，第三电压源GCH为恒定高电压源，第四电压源VGL为恒定低电压源；
上述上拉模块，连接时钟信号端CLK、信号输出端OUTPUT和所述第一节点PU，配置为在第一节点PU的电压的控制下将来自时钟信号端CLK的时钟信号提供给信号输出端OUTPUT；
上述下拉模块，连接第四电压源VGL、信号输出端OUTPUT和第二节点PD，配置为在第二节点PD的电压的控制下将所述第四电压源VGL的电压提供给信号输出端OUTPUT；
上述放噪模块，连接第四电压源VGL、第一节点PU和第二节点PD。放噪模块在所述移位寄存器的非工作时间(移位寄存器完成一帧输出直至下一帧到来之间的时间)内维持所述第一节点PU为低电平。
下面以上述晶体管均为N型晶体管为例进行说明。
需要说明的是，上述移位寄存器100能够进行双向扫描。其中，在进行正向扫描和反向扫描时，所述移位寄存器的结构不发生改变，只是信号输入端INPUT和复位信号端RESET的功能发生转变。例如，当正向扫描时，从第一电压源VDD输入高电平信号，从第二电压源VSS输入低电平信号；当反向扫描时，从第一电压源VDD输入低电平信号，从第二电压源VSS输入高电平信号。正向扫描时的信号输入端INPUT用作反向扫描时的复位信号端RESET，而正向扫描时的复位信号端RESET则用作反向扫描时的信号输入端INPUT。
图2中所示的是图1中的移位寄存器在进行正向扫描时各信号的时序图。下面参照图2，说明图1中的移位寄存器的四个工作阶段。
在第一阶段T1，本级移位寄存器信号输入端INPUT输入的信号为上一级移位寄存器的信号输出端OUTPUT的输出信号，此时为高电平信号，使得第一晶体管M1导通；从第一电压源VDD输入的高电平信号对第一电容C1充电，第一节点PU的电平被拉高，使得第五晶体管M5和第六晶体管M6导通；通过设计第五晶体管M5和第六晶体管M6的比例，使得第二节点PD的电平为低电平，进而第八晶体管M8和第九晶体管M9截止，从而保证信号输出端OUTPUT稳定地输出低电平。
在第二阶段T2，本级移位寄存器信号输入端INPUT输入的信号为低电平信号，第一晶体管M1截止，第一节点PU继续保持高电平，第七晶体管M7保持导通状态。此时时钟信号端CLK的时钟信号变为高电平信号，由于 第一电容C1的自举效应，第一节点PU点电平升高，信号输出端OUTPUT输出高电平；由于第五晶体管M5和第六晶体管M6仍然导通，第二节点PD点仍保持低电平，第八晶体管M8和第九晶体管M9保持截止，保证信号输出端OUTPUT稳定地输出高电平。
在第三阶段T3，下一级移位寄存器的信号输出端OUTPUT输出高电平信号给本级移位寄存器的复位信号端RESET。第二晶体管M2导通，第一节点PU的电平被拉低，第五至第七晶体管M5-M7截止；第三电压源GCH始终为高电平，第二节点PD的电平被拉高，第八晶体管M8和第九晶体管M9导通，第二节点PU和信号输出端OUTPUT稳定地输出低电平，完成对一行栅线的驱动。
在第四阶段T4，复位信号端RESET变为低电平，第二晶体管M2截止，在下一帧到来之前，第一节点PU一直处于低电平，第二节点PD一直处于高电平，第八晶体管M8和第九晶体管M9一直处于导通状态，可以持续地对第二节点PU和信号输出端OUTPUT进行放噪，使得由时钟信号端CLK产生的耦合噪声电压得以消除，从而保证信号输出端OUTPUT稳定地输出低电平。
上述传统的移位寄存器只能驱动一行栅线，需要9个晶体管和1个电容。由这种移位寄存器组成的栅极驱动电路的每一级只能驱动一行栅线，若要实现对两行栅线的驱动，需要多达18个晶体管和2个电容，不利于实现窄边框的设计。
针对上述问题本申请提出一种新的移位寄存器，可以实现一个移位寄存器驱动两行栅线。
图3示出了根据本公开实施例的移位寄存器的框图。如图3所示，该移位寄存器300包括：
预充电模块301，连接第一电压源VDD和信号输入端INPUT，配置为在来自信号输入端INPUT的输入信号的控制下将第一电压源VDD的电压提供至第一节点PU，所述第一节点PU为预充电模块301的输出节点；
复位模块302，连接第二电压源VSS、复位信号端RESET和所述第一节点PU，配置为在来自复位信号端RESET的输入信号的控制下将第二电压源VSS的电压提供至所述第一节点PU；
控制模块303，连接第三电压源GCH、第四电压源VGL和所述第一节点PU，配置为在第一节点PU的电压的控制下将来自第三电压源GCH的电压提供给第二节点PD或者将来自第四电压源VGL的电压提供给第二节点PD，所述第二节点PD为控制模块303的输出节点，第三电压源GCH为恒定高电压源，第四电压源VGL为恒定低电压源；
第一上拉模块304，连接第一时钟信号端CLK1、第一信号输出端OUTPUT1和所述第一节点PU，配置为在第一节点PU的电压的控制下将来自第一时钟信号端CLK1的时钟信号提供给第一信号输出端OUTPUT1；
第二上拉模块305，连接第一时钟信号端CLK1、第二时钟信号端CLK2、第一节点PU和第二信号输出端OUTPUT2，配置为在第一时钟信号端CLK1的时钟信号和第一节点PU的电压的控制下将来自第二时钟信号端CLK2的时钟信号提供给第二信号输出端OUTPUT2；
第一下拉模块306，连接第四电压源VGL、第一信号输出端OUTPUT1和第二信号输出端OUTPUT2，配置为在第二信号输出端OUTPUT2的输出信号的控制下将所述第四电压源VGL的电压提供给第一信号输出端OUTPUT1；
第二下拉模块307，连接第四电压源VGL、第二信号输出端OUTPUT2和第二节点PD，配置为在第二节点PD的电压的控制下将所述第四电压源VGL的电压提供给第二信号输出端OUTPUT2。第二下拉模块307还在所述移位寄存器300的非工作时间(移位寄存器完成一帧输出直至下一帧到来之间的时间)内维持所述第二信号输出端OUTPUT2为低电平。
可选地，如图3所示，该移位寄存器300还包括：
放噪模块308，连接第四电压源VGL、第一信号输出端OUTPUT1、第一节点PU和第二节点PD。放噪模块308在所述移位寄存器300的非工作时间内维持所述第一节点PU和第一信号输出端OUTPUT1为低电平。
由图3可看出，该移位寄存器300具有两个信号输出端，因此可以驱动两行栅线，同时保证各输出之间没有干扰。
图4示出了根据本公开实施例的图3的移位寄存器300的一种电路结构图。
如图4所示，预充电模块301包括第一晶体管M1，其漏极连接至第一 电压源VDD，栅极连接至信号输入端INPUT，源极连接至第一节点PU。
复位模块302包括第二晶体管M2，其漏极连接至第一节点PU，栅极连接至复位信号端RESET，源极连接至第二电压源VSS。
控制模块303包括：第三晶体管M3，其漏极和栅极连接至第三电压源GCH；第四晶体管M4，其漏极连接至第三电压源GCH，栅极连接至第三晶体管M3的源极，源极连接至第二节点PD；第五晶体管M5，其漏极连接至第三晶体管M3的源极，栅极连接至第一节点PU，源极连接至第四电压源VGL；第六晶体管M6，其漏极连接至第二节点PD，栅极连接至第一节点PU，源极连接至第四电压源VGL。
第一上拉模块304包括：第七晶体管M7，其漏极连接至第一时钟信号端CLK1，栅极连接至第一节点PU，源极连接至第一信号输出端OUTPUT1；第一电容C1，连接在第一节点PU和第一信号输出端之间OUTPUT1。
第二上拉模块305包括：第八晶体管M8，其栅极连接至第一时钟信号端CLK1，源极连接至第一节点PU；第二电容C2，连接在第八晶体管M8的漏极和第二信号输出端OUTPUT2之间；第九晶体管M9，其漏极连接至第二时钟信号端CLK2，栅极连接至第八晶体管M8的漏极，源极连接至第二信号输出端OUTPUT2。
第一下拉模块306包括第十晶体管M10，其漏极连接至第一信号输出端OUTPUT1，栅极连接至第二信号输出端OUTPUT2，源极连接至第四电压源VGL。
第二下拉模块307包括第十一晶体管M11，其漏极连接至第二信号输出端OUTPUT2，栅极连接至第二节点PD，源极连接至第四电压源VGL。
放噪模块308包括：第十二晶体管M12，其漏极连接至第一信号输出端OUTPUT1，栅极连接至第二节点PD，源极连接至第四电压源VGL；第十三晶体管M13，其漏极连接至第一节点PU，栅极连接至第二节点PD，源极连接至第四电压源VGL。
利用本公开的移位寄存器，可以实现一个移位寄存器驱动两行栅线，减少晶体管使用数量，降低电路成本，消除移位寄存器输出端的噪声，提高工作的稳定性。
由图4可看出，为了驱动两行栅线，根据本申请的移位寄存器仅需要13 个晶体管，与图1中已知的移位寄存器相比，减少了5个晶体管的使用。对于一个需要一千多行栅线输出的面板，采用本申请的移位寄存器，可减少几千个晶体管的使用，从而在更小的面积下实现栅线驱动的功能，实现更窄的边框，降低栅极驱动电路成本。
能够理解，图4中所示出的各个模块的示例电路结构仅仅是一种示例，各个模块也可以采用其他适当的电路结构，只要能分别实现各自的功能即可，本公开对此不做限制。
图5示出了图4中的移位寄存器在进行正向扫描时各信号的时序图。以下将参考图5对根据本公开实施例的图4中的移位寄存器的具体工作过程进行描述。下面以上述晶体管均为N型晶体管为例进行说明。
需要说明的是，根据本公开的移位寄存器能够进行双向扫描。在进行正向扫描和反向扫描时，所述移位寄存器的结构不发生改变，只是信号输入端INPUT和复位信号端RESET的功能发生转变。例如，当正向扫描时，从第一电压源VDD输入高电平信号，从第二电压源VSS输入低电平信号；当反向扫描时，从第一电压源VDD输入低电平信号，从第二电压源VSS输入高电平信号。正向扫描时的信号输入端INPUT用作反向扫描时的复位信号端RESET，而正向扫描时的复位信号端RESET则用作反向扫描时的信号输入端INPUT。
如图5所示，在一帧期间，该工作过程包括以下几个阶段。下面参照图4和图5对该工作过程进行描述。
第一阶段T1：本级移位寄存器信号输入端INPUT输入的信号为上一级移位寄存器的信号输出端OUTPUT的输出信号，此时为高电平信号，使得第一晶体管M1导通；从第一电压源VDD输入的高电平信号对第一电容C1充电，第一节点PU的电平被拉高，使得第五晶体管M5和第六晶体管M6导通；通过设计第五晶体管M5和第六晶体管M6的比例，使得第二节点PD的电平为低电平，进而第十一至第十三晶体管M11-M13截止，此时第一时钟信号端CLK1输出的时钟信号为低电平信号，第八晶体管M8和第九晶体管M9截止，第一信号输出端OUTPUT1和第二信号输出端OUTPUT2稳定地输出低电平。
第二阶段T2：本级移位寄存器信号输入端INPUT输入的信号为低电平 信号，第一晶体管M1截止，第一节点PU继续保持高电平，第七晶体管M7保持导通状态。此时第一时钟信号端CLK1的时钟信号变为高电平信号，因此第一信号输出端OUTPUT1输出高电平；同时第八晶体管M8导通，第一节点PU对第二电容C2充电，使得第三节点PO为高电平，第九晶体管M9导通，由于此时第二时钟信号端CLK2的时钟信号为低电平信号，因此第二信号输出端OUTPUT2输出低电平。第十晶体管M10截止，同时由于第五晶体管M5和第六晶体管M6仍然导通，第二节点PD仍保持低电平，第十一至第十三晶体管M11-M13保持截止，保证第一信号输出端OUTPUT1稳定输出高电平和第二信号输出端OUTPUT2稳定输出低电平。
第三阶段T3：第一时钟信号端CLK1的时钟信号为低电平信号，第二时钟信号端CLK2的时钟信号为高电平信号，由于第三节点PO为高电平，第九晶体管M9导通，第二信号输出端OUTPUT2输出高电平。同时，第十晶体管M10导通，第一信号输出端OUPUT1的输出被拉到低电平，完成对第一行栅线的驱动。
第四阶段T4：第一时钟信号端CLK1的时钟信号变为高电平，第八晶体管M8导通，同时下一级移位寄存器的第一信号输出端输出高电平给本级移位寄存器的复位信号端RESET，第二晶体管M2导通，第一节点PU和第三节点PO的电平被拉低，第七晶体管M7和第九晶体管M9截止，同时第五晶体管M5和第六晶体管M6也截止，第二节点PD的电平被第三电压源GCH拉高，第十一至第十三晶体管M11-M13导通，第二信号输出端OUTPUT2和第一信号输出端OUTPUT1均稳定输出低电平，完成对第二行栅线的驱动。
此后，复位信号端RESET变为低电平，第二晶体管M2截止，在下一帧到来之前，第一节点PU点一直处于低电平，第二节点PD点一直处于高电平，第十一至第十三晶体管M11-M13一直处于导通状态，可以持续地对第一节点PU、第一信号输出端OUTPUT1和第二信号输出端OUTPUT2进行放噪，同时第一时钟信号端CLK1通过不断打开第八晶体管M8，可不断对第三节点PO进行放噪，从而保证第二信号输出端OUTPUT2和第一信号输出端OUTPUT1的低压信号输出的稳定性。直至下一帧到来，所述移位寄存器接收到信号输入端INPUT的高电平信号后，重新执行上述第一阶段。
由图5可以看出，第二时钟信号端CLK2的时钟信号与第一时钟信号端 CLK1的时钟信号反相。
根据本公开实施例的移位寄存器在反向扫描时的具体工作过程与正向扫描时的工作过程相似，在此不再赘述。
本公开还提供了一种移位寄存器的驱动方法。下面结合图4对该方法进行说明。如图4所示，移位寄存器包含预充电模块301、复位模块302、控制模块303、第一上拉模块304、第二上拉模块305、第一下拉模块306、第二下拉模块307，该驱动方法包含：
由预充电模块301在来自信号输入端INPUT的输入信号的控制下将第一电压源VDD的电压提供至预充电模块301的输出节点PU；
由复位模块302在来自复位信号端的输入信号的控制下将第二电压源VSS的电压提供至所述预充电模块301的输出节点PU；
由控制模块303在预充电模块301的输出节点PU的电压的控制下将来自第三电压源GCH的电压提供给控制模块303的输出节点PD或者将来自第四电压源VGL的电压提供给控制模块303的输出节点PD；
由第一上拉模块304在预充电模块301的输出节点PU的电压的控制下将来自第一时钟信号端CLK1的时钟信号提供给第一信号输出端OUTPUT1；
由第二上拉模块305在第一时钟信号端CLK1的时钟信号和预充电模块301的输出节点PU的电压的控制下将来自第二时钟信号端CLK2的时钟信号提供给第二信号输出端OUTPUT2；
由第一下拉模块306在第二信号输出端OUTPUT2的输出信号的控制下将所述第四电压源VGL的电压提供给第一信号输出端OUTPUT1；
由第二下拉模块307在控制模块303的输出节点PD的电压的控制下将所述第四电压源VGL的电压提供给第二信号输出端OUTPUT2。
图6示出了由根据本公开实施例的多个移位寄存器级联形成的栅极驱动电路的示意图。
如图6所示，在该栅极驱装置中，多个图4中的上述移位寄存器串联连接。其中除最后一个移位寄存器Rm外，其余每个移位寄存器Ri(1≤i＜m)的第二信号输出端OUTPUT2均和与其相邻的下一个移位寄存器Ri+1的信号输入端INPUT相连；除第一个移位寄存器R1外，其余每个移位寄存器Ri(1＜i≤m)的第一信号输出端OUTPUT1均和与其相邻的上一个移位寄存器 Ri-1的复位信号端RESET相连。在正向扫描时，所述第一个移位寄存器R1的信号输入端INPUT输入帧起始信号STV；在反向扫描时，所述最后一个移位寄存器Rm的复位信号端RESET输入帧起始信号STV。
如图6所示，在该栅极驱动电路中，相邻两级移位寄存器的第一时钟信号端输入的时钟信号相同，第二时钟信号端输入的时钟信号相同。
根据本公开实施例的栅极驱动电路在正向扫描时各移位寄存器的具体工作过程与参照图4和图5描述的工作过程相似，在此不再赘述。
根据本公开实施例的栅极驱动电路在反向扫描时的具体工作过程与正向扫描时的工作过程相似，在此不再赘述。
根据本公开实施例的栅极驱动电路可以采用GOA技术，用作显示装置的栅极驱动电路，以提供逐行扫描功能，将扫描信号传送至显示区域。
根据本公开实施例的栅极驱动电路可以减少晶体管使用数量，降低电路成本，消除输出端的噪声，提高工作的稳定性。
本公开还提供了一种包含上述栅极驱动电路的显示装置。
这里的显示装置可以为：电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
本申请要求于2016年2月4日递交的中国专利申请第201610078430.4号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (18)

  1. 一种移位寄存器，包括：
    预充电模块，连接第一电压源和信号输入端，配置为在来自信号输入端的输入信号的控制下将第一电压源的电压提供至第一节点，所述第一节点为预充电模块的输出节点；
    复位模块，连接第二电压源、复位信号端和所述第一节点，配置为在来自复位信号端的输入信号的控制下将第二电压源的电压提供至所述第一节点；
    控制模块，连接第三电压源、第四电压源和所述第一节点，配置为在第一节点的电压的控制下将来自第三电压源的电压提供给第二节点或者将来自第四电压源的电压提供给第二节点，所述第二节点为控制模块的输出节点；
    第一上拉模块，连接第一时钟信号端、第一信号输出端和所述第一节点，配置为在第一节点的电压的控制下将来自第一时钟信号端的时钟信号提供给第一信号输出端；
    第二上拉模块，连接第一时钟信号端、第二时钟信号端、第一节点和第二信号输出端，配置为在第一时钟信号端的时钟信号和第一节点的电压的控制下将来自第二时钟信号端的时钟信号提供给第二信号输出端；
    第一下拉模块，连接第四电压源、第一信号输出端和第二信号输出端，配置为在第二信号输出端的输出信号的控制下将所述第四电压源的电压提供给第一信号输出端；
    第二下拉模块，连接第四电压源、第二信号输出端和第二节点，配置为在第二节点的电压的控制下将所述第四电压源的电压提供给第二信号输出端。
  2. 根据权利要求1所述的移位寄存器，还包括：
    放噪模块，连接第四电压源、第一信号输出端、第一节点和第二节点。
  3. 根据权利要求1-2中任一项所述的移位寄存器，所述预充电模块包括：
    第一晶体管，其漏极连接至第一电压源，栅极连接至信号输入端，源极连接至第一节点。
  4. 根据权利要求1-3中任一项所述的移位寄存器，所述复位模块包括：
    第二晶体管，其漏极连接至第一节点，栅极连接至复位信号端，源极连接至第二电压源。
  5. 根据权利要求1-4中任一项所述的移位寄存器，所述控制模块包括：
    第三晶体管，其漏极和栅极连接至第三电压源；
    第四晶体管，其漏极连接至第三电压源，栅极连接至第三晶体管的源极，源极连接至第二节点；
    第五晶体管，其漏极连接至第三晶体管的源极，栅极连接至第一节点，源极连接至第四电压源；
    第六晶体管，其漏极连接至第二节点，栅极连接至第一节点，源极连接至第四电压源。
  6. 根据权利要求1-5中任一项所述的移位寄存器，所述第一上拉模块包括：
    第七晶体管，其漏极连接至第一时钟信号端，栅极连接至第一节点，源极连接至第一信号输出端；
    第一电容，连接在第一节点和第一信号输出端之间。
  7. 根据权利要求1-6中任一项所述的移位寄存器，所述第二上拉模块包括：
    第八晶体管，其栅极连接至第一时钟信号端，源极连接至第一节点；
    第二电容，连接在第八晶体管的漏极和第二信号输出端之间；
    第九晶体管，其漏极连接至第二时钟信号端，栅极连接至第八晶体管的漏极，源极连接至第二信号输出端。
  8. 根据权利要求1-7中任一项所述的移位寄存器，所述第一下拉模块包括：
    第十晶体管，其漏极连接至第一信号输出端，栅极连接至第二信号输出端，源极连接至第四电压源。
  9. 根据权利要求1-8中任一项所述的移位寄存器，所述第二下拉模块包括：
    第十一晶体管，其漏极连接至第二信号输出端，栅极连接至第二节点，源极连接至第四电压源。
  10. 根据权利要求2-9中任一项所述的移位寄存器，所述放噪模块包括：
    第十二晶体管，其漏极连接至第一信号输出端，栅极连接至第二节点，源极连接至第四电压源；
    第十三晶体管，其漏极连接至第一节点，栅极连接至第二节点，源极连接至第四电压源。
  11. 根据权利要求1-10中任一项所述的移位寄存器，
    在正向扫描时，第一电压源输出高电平信号，第二电压源输出低电平信号；
    在反向扫描时，第一电压源输出低电平信号，第二电压源输出高电平信号；
    其中，正向扫描时的信号输入端用作反向扫描时的复位信号端，正向扫描时的复位信号端用作反向扫描时的信号输入端。
  12. 根据权利要求3-11中任一项所述的移位寄存器，其中，所述晶体管均为N型晶体管。
  13. 根据权利要求1-12中任一项所述的移位寄存器，其中所述第二时钟信号端的时钟信号与第一时钟信号端的时钟信号反相。
  14. 根据权利要求1-13中任一项所述的移位寄存器，第三电压源为恒定高电压源，第四电压源为恒定低电压源。
  15. 一种栅极驱动电路，包括多个串联的移位寄存器，每个所述移位寄存器是如权利要求1-14中任一项所述的移位寄存器，
    其中除最后一个移位寄存器外，其余每个移位寄存器的第二信号输出端均和与其相邻的下一个移位寄存器的信号输入端相连；除第一个移位寄存器外，其余每个移位寄存器的第一信号输出端均和与其相邻的上一个移位寄存器的复位信号端相连；
    在正向扫描时，所述第一个移位寄存器的信号输入端输入帧起始信号；在反向扫描时，所述最后一个移位寄存器的复位信号端输入帧起始信号。
  16. 根据权利要求15所述的栅极驱动电路，其中
    相邻两级移位寄存器的第一时钟信号端输入的时钟信号相同，第二时钟信号端输入的时钟信号相同。
  17. 一种包含根据权利要求15-16中任一项所述的栅极驱动电路的显示装置。
  18. 一种移位寄存器的驱动方法，该移位寄存器包含预充电模块、复位模块、控制模块、第一上拉模块、第二上拉模块、第一下拉模块、第二下拉模块，该驱动方法包含：
    由预充电模块在来自信号输入端的输入信号的控制下将第一电压源的电压提供至预充电模块的输出节点；
    由复位模块在来自复位信号端的输入信号的控制下将第二电压源的电压提供至所述预充电模块的输出节点；
    由控制模块在预充电模块的输出节点的电压的控制下将来自第三电压源的电压提供给控制模块的输出节点或者将来自第四电压源的电压提供给控制模块的输出节点；
    由第一上拉模块在预充电模块的输出节点的电压的控制下将来自第一时钟信号端的时钟信号提供给第一信号输出端；
    由第二上拉模块在第一时钟信号端的时钟信号和预充电模块的输出节点的电压的控制下将来自第二时钟信号端的时钟信号提供给第二信号输出端；
    由第一下拉模块在第二信号输出端的输出信号的控制下将所述第四电压源的电压提供给第一信号输出端；
    由第二下拉模块在控制模块的输出节点的电压的控制下将所述第四电压源的电压提供给第二信号输出端。
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Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105529009B (zh) * 2016-02-04 2018-03-20 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN105957556A (zh) * 2016-05-11 2016-09-21 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及其驱动方法、显示装置
CN107516491A (zh) * 2016-06-17 2017-12-26 群创光电股份有限公司 显示设备
CN106023943A (zh) * 2016-08-02 2016-10-12 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN106326859B (zh) * 2016-08-23 2019-11-01 京东方科技集团股份有限公司 指纹识别驱动电路、阵列基板、显示装置及指纹识别方法
CN106448596B (zh) * 2016-10-31 2019-03-15 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN106601190B (zh) * 2017-03-06 2018-12-21 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置
CN106611582A (zh) * 2017-03-08 2017-05-03 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路、显示面板及驱动方法
CN106683634B (zh) * 2017-03-30 2019-01-22 京东方科技集团股份有限公司 一种移位寄存器、goa电路及其驱动方法、显示装置
CN107039017A (zh) * 2017-06-21 2017-08-11 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN107316600A (zh) * 2017-07-21 2017-11-03 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN107369407B (zh) * 2017-09-22 2021-02-26 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示面板
CN107403602B (zh) * 2017-09-25 2020-05-19 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器电路和显示装置
CN107507556B (zh) * 2017-09-30 2020-06-12 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、栅极驱动电路以及显示装置
CN107633799A (zh) * 2017-10-13 2018-01-26 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路及显示装置
CN108154835B (zh) * 2018-01-02 2020-12-25 京东方科技集团股份有限公司 移位寄存器单元、其驱动方法、栅极驱动电路及显示装置
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CN111179797B (zh) * 2018-11-13 2021-11-02 合肥京东方卓印科技有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及相关装置
CN109461401B (zh) * 2018-12-20 2022-06-14 昆山龙腾光电股份有限公司 栅极驱动电路及其显示装置
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CN109686334B (zh) * 2019-02-18 2021-01-22 京东方科技集团股份有限公司 栅极驱动电路及其驱动方法、和显示装置
CN109686296B (zh) * 2019-03-05 2022-05-20 合肥鑫晟光电科技有限公司 移位寄存器模块及驱动方法、栅极驱动电路
TWI690932B (zh) * 2019-09-05 2020-04-11 友達光電股份有限公司 移位暫存器
CN112634812A (zh) * 2021-01-08 2021-04-09 厦门天马微电子有限公司 显示面板和显示装置
CN113744679B (zh) * 2021-07-29 2024-02-09 北京大学深圳研究生院 一种栅极驱动电路及显示面板
CN115862549A (zh) * 2021-09-27 2023-03-28 乐金显示有限公司 栅极驱动电路以及包括栅极驱动电路的显示面板
CN115512672B (zh) * 2022-10-25 2023-10-27 业成科技（成都）有限公司 扫描驱动电路及其操作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060097819A (ko) * 2005-03-07 2006-09-18 삼성전자주식회사 쉬프트 레지스터 및 이를 구비한 표시 장치
CN102708799A (zh) * 2012-05-31 2012-10-03 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器电路、阵列基板及显示器件
CN104966506A (zh) * 2015-08-06 2015-10-07 京东方科技集团股份有限公司 一种移位寄存器、显示面板的驱动方法及相关装置
CN105529009A (zh) * 2016-02-04 2016-04-27 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101350635B1 (ko) * 2009-07-03 2014-01-10 엘지디스플레이 주식회사 듀얼 쉬프트 레지스터
CN103578433B (zh) * 2012-07-24 2015-10-07 北京京东方光电科技有限公司 一种栅极驱动电路、方法及液晶显示器
CN103208251B (zh) * 2013-04-15 2015-07-29 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路及显示装置
CN103310755B (zh) * 2013-07-03 2016-01-13 深圳市华星光电技术有限公司 阵列基板行驱动电路
CN103761952B (zh) * 2013-12-31 2016-01-27 深圳市华星光电技术有限公司 一种液晶面板的扫描驱动电路、液晶面板和一种驱动方法
CN104157248A (zh) * 2014-05-08 2014-11-19 京东方科技集团股份有限公司 栅极驱动电路、栅极驱动方法和显示装置
CN105047228B (zh) * 2015-09-09 2018-11-23 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、驱动电路和显示装置
CN105244003B (zh) * 2015-11-12 2018-01-09 深圳市华星光电技术有限公司 栅极驱动电路以及移位寄存电路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060097819A (ko) * 2005-03-07 2006-09-18 삼성전자주식회사 쉬프트 레지스터 및 이를 구비한 표시 장치
CN102708799A (zh) * 2012-05-31 2012-10-03 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器电路、阵列基板及显示器件
CN104966506A (zh) * 2015-08-06 2015-10-07 京东方科技集团股份有限公司 一种移位寄存器、显示面板的驱动方法及相关装置
CN105529009A (zh) * 2016-02-04 2016-04-27 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置

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